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FMC ADC 100M 14b 4cha - Gateware
Commit a37d85ff authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Merge branch 'proposed_master'

parents 94c7ce24 dfb7b6bf
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.gitignore
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hdl/ip_cores/ddr3-sp6-core/
hdl/ip_cores/general-cores/
hdl/ip_cores/gn4124-core/
hdl/ip_cores/vme64x-core/
hdl/ip_cores/wr-cores/
hdl/ip_cores/.lso
hdl/ip_cores/_xmsgs
hdl/*/sim/modelsim.ini
hdl/*/sim/work/
hdl/*/sim/*/transcript
hdl/*/sim/*/vsim.wlf
hdl/*/sim/*/Makefile
hdl/*/sim/*/modelsim.ini
hdl/*/sim/*/work/
hdl/*/testbench/top/transcript
hdl/*/testbench/top/vsim.wlf
hdl/*/testbench/top/Makefile
hdl/*/testbench/top/modelsim.ini
hdl/*/testbench/top/work/
hdl/*/testbench/top/NullFile
hdl/*/sim/fifo_generator_v6_1/
hdl/*/syn/_ngo/
hdl/*/syn/_xmsgs/
......@@ -58,13 +62,13 @@ hdl/*/syn/*_summary.html
hdl/*/release/
hdl/*/chipscope/*.vcd
hdl/*/chipscope/*.wlf
hdl/svec/sim/testbench/fifo_generator_v6_1/
hdl/svec/sim/testbench/modelsim.ini
hdl/svec/sim/testbench/simdrv_defs.svh
hdl/svec/sim/testbench/transcript
hdl/svec/sim/testbench/vsim.wlf
hdl/svec/sim/testbench/vsim_stacktrace.vstf
hdl/svec/sim/testbench/work/
hdl/svec/sim/testbench/top/fifo_generator_v6_1/
hdl/svec/sim/testbench/top/modelsim.ini
hdl/svec/sim/testbench/top/simdrv_defs.svh
hdl/svec/sim/testbench/top/transcript
hdl/svec/sim/testbench/top/vsim.wlf
hdl/svec/sim/testbench/top/vsim_stacktrace.vstf
hdl/svec/sim/testbench/top/work/
doc/manual/*.html
*.texi
*.aux
......
.gitmodules 0 → 100644
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[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
doc/fig/Makefile
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......@@ -2,7 +2,7 @@ SVG=$(wildcard *.svg)
PDF=$(SVG:.svg=.pdf)
.PHONY: all
all: $(PDF) acq_fsm.pdf
all: $(PDF)
%.pdf : %.svg
inkscape --without-gui $< -A $@
......@@ -14,11 +14,3 @@ clean:
show:
$(info all svg: $(SVG))
$(info all pdf: $(PDF))
acq_fsm.pdf: acq_fsm.dia
dia -e acq_fsm.pdf acq_fsm.dia
# crop around front panel
# bbox origin is in bottom left corner of the page
# bbox unit is [points]
pdfcrop --bbox '50 550 550 780' acq_fsm.pdf acq_fsm.pdf
doc/fig/acq_fsm.pdf
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doc/fig/acq_fsm.svg 0 → 100644
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doc/fig/cern_logo.pdf
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doc/fig/spec_fw_arch.pdf
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doc/fig/svec_fw_arch.pdf
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doc/fig/trig_hw_int.pdf
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doc/fig/trigger_unit.pdf
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doc/manual/fmc_adc_100Ms_csr.tex
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......@@ -133,6 +133,10 @@ Channel 4 offset calibration register
REG @tab
@code{ch4_sat} @tab
Channel 4 saturation register
@item @code{0x84} @tab
REG @tab
@code{multi_depth} @tab
Multi-shot sample depth register
@end multitable
@regsection @code{ctl} - Control register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -352,13 +356,13 @@ Sampling clock frequency
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{DECI}
@code{UNDERSAMPLE}
@tab @code{0} @tab
Sample rate decimation
Undersampling ratio
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{deci} @tab Decimation factor. Takes one sample every N samples and discards the others (N = decimation factor).
@item @code{undersample} @tab Undersampling ratio. Takes one sample every N samples and discards the others (N = undersampling ratio).
@end multitable
@regsection @code{pre_samples} - Pre-trigger samples
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -659,3 +663,16 @@ Saturation value for channel 4
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@end multitable
@regsection @code{multi_depth} - Multi-shot sample depth register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{MULTI_DEPTH}
@tab @code{X} @tab
Multi-shot sample depth
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{multi_depth} @tab Maximum sample depth allowed in multi-shot acquisition mode, excluding two samples already reserved for time tag
@end multitable
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
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hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
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......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Fri Mar 21 08:14:07 2014
-- Created : Mon Apr 18 16:09:20 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -82,8 +82,8 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Sampling clock frequency' in reg: 'Sampling clock frequency'
fmc_adc_core_fs_freq_i : in std_logic_vector(31 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Sample rate decimation' in reg: 'Sample rate'
fmc_adc_core_sr_deci_o : out std_logic_vector(31 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Undersampling ratio' in reg: 'Sample rate'
fmc_adc_core_sr_undersample_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Pre-trigger samples' in reg: 'Pre-trigger samples'
fmc_adc_core_pre_samples_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Post-trigger samples' in reg: 'Post-trigger samples'
......@@ -129,7 +129,9 @@ entity fmc_adc_100Ms_csr is
-- Port for std_logic_vector field: 'Offset calibration for channel 4' in reg: 'Channel 4 offset calibration register'
fmc_adc_core_ch4_offset_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Saturation value for channel 4' in reg: 'Channel 4 saturation register'
fmc_adc_core_ch4_sat_val_o : out std_logic_vector(14 downto 0)
fmc_adc_core_ch4_sat_val_o : out std_logic_vector(14 downto 0);
-- Port for std_logic_vector field: 'Multi-shot sample depth' in reg: 'Multi-shot sample depth register'
fmc_adc_core_multi_depth_i : in std_logic_vector(31 downto 0)
);
end fmc_adc_100Ms_csr;
......@@ -193,12 +195,12 @@ signal fmc_adc_core_fs_freq_lwb_in_progress : std_logic ;
signal fmc_adc_core_fs_freq_lwb_s0 : std_logic ;
signal fmc_adc_core_fs_freq_lwb_s1 : std_logic ;
signal fmc_adc_core_fs_freq_lwb_s2 : std_logic ;
signal fmc_adc_core_sr_deci_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_sr_deci_swb : std_logic ;
signal fmc_adc_core_sr_deci_swb_delay : std_logic ;
signal fmc_adc_core_sr_deci_swb_s0 : std_logic ;
signal fmc_adc_core_sr_deci_swb_s1 : std_logic ;
signal fmc_adc_core_sr_deci_swb_s2 : std_logic ;
signal fmc_adc_core_sr_undersample_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_sr_undersample_swb : std_logic ;
signal fmc_adc_core_sr_undersample_swb_delay : std_logic ;
signal fmc_adc_core_sr_undersample_swb_s0 : std_logic ;
signal fmc_adc_core_sr_undersample_swb_s1 : std_logic ;
signal fmc_adc_core_sr_undersample_swb_s2 : std_logic ;
signal fmc_adc_core_pre_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_post_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_ch1_ctl_ssr_int : std_logic_vector(6 downto 0);
......@@ -302,9 +304,9 @@ begin
fmc_adc_core_fs_freq_lwb <= '0';
fmc_adc_core_fs_freq_lwb_delay <= '0';
fmc_adc_core_fs_freq_lwb_in_progress <= '0';
fmc_adc_core_sr_deci_int <= "00000000000000000000000000000000";
fmc_adc_core_sr_deci_swb <= '0';
fmc_adc_core_sr_deci_swb_delay <= '0';
fmc_adc_core_sr_undersample_int <= "00000000000000000000000000000000";
fmc_adc_core_sr_undersample_swb <= '0';
fmc_adc_core_sr_undersample_swb_delay <= '0';
fmc_adc_core_pre_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_post_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_ch1_ctl_ssr_int <= "0000000";
......@@ -361,8 +363,8 @@ begin
rddata_reg(31 downto 0) <= fmc_adc_core_fs_freq_int;
fmc_adc_core_fs_freq_lwb_in_progress <= '0';
end if;
fmc_adc_core_sr_deci_swb <= fmc_adc_core_sr_deci_swb_delay;
fmc_adc_core_sr_deci_swb_delay <= '0';
fmc_adc_core_sr_undersample_swb <= fmc_adc_core_sr_undersample_swb_delay;
fmc_adc_core_sr_undersample_swb_delay <= '0';
fmc_adc_core_ch1_sta_val_lwb <= fmc_adc_core_ch1_sta_val_lwb_delay;
fmc_adc_core_ch1_sta_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch1_sta_val_lwb_in_progress = '1')) then
......@@ -609,11 +611,11 @@ begin
ack_in_progress <= '1';
when "001001" =>
if (wb_we_i = '1') then
fmc_adc_core_sr_deci_int <= wrdata_reg(31 downto 0);
fmc_adc_core_sr_deci_swb <= '1';
fmc_adc_core_sr_deci_swb_delay <= '1';
fmc_adc_core_sr_undersample_int <= wrdata_reg(31 downto 0);
fmc_adc_core_sr_undersample_swb <= '1';
fmc_adc_core_sr_undersample_swb_delay <= '1';
end if;
rddata_reg(31 downto 0) <= fmc_adc_core_sr_deci_int;
rddata_reg(31 downto 0) <= fmc_adc_core_sr_undersample_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "001010" =>
......@@ -1148,6 +1150,12 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= fmc_adc_core_multi_depth_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -1381,21 +1389,21 @@ begin
end process;
-- Sample rate decimation
-- asynchronous std_logic_vector register : Sample rate decimation (type RW/RO, fs_clk_i <-> clk_sys_i)
-- Undersampling ratio
-- asynchronous std_logic_vector register : Undersampling ratio (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_sr_deci_swb_s0 <= '0';
fmc_adc_core_sr_deci_swb_s1 <= '0';
fmc_adc_core_sr_deci_swb_s2 <= '0';
fmc_adc_core_sr_deci_o <= "00000000000000000000000000000000";
fmc_adc_core_sr_undersample_swb_s0 <= '0';
fmc_adc_core_sr_undersample_swb_s1 <= '0';