Commit a26af799 authored by Dimitris Lampridis's avatar Dimitris Lampridis

syn: removed (and ignored) all hdlmake-generated files from SPEC and SVEC.…

syn: removed (and ignored) all hdlmake-generated files from SPEC and SVEC. Xilinx ISE project files could be added on official release commits if necessary
parent 0d62e067
*
!.gitignore
!Manifest.py
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := spec_fmc_adc_100Ms.xise
ISE_CRAP := *.b spec_top_fmc_adc_100Ms_summary.html *.tcl spec_top_fmc_adc_100Ms.bld spec_top_fmc_adc_100Ms.cmd_log *.drc spec_top_fmc_adc_100Ms.lso *.ncd spec_top_fmc_adc_100Ms.ngc spec_top_fmc_adc_100Ms.ngd spec_top_fmc_adc_100Ms.ngr spec_top_fmc_adc_100Ms.pad spec_top_fmc_adc_100Ms.par spec_top_fmc_adc_100Ms.pcf spec_top_fmc_adc_100Ms.prj spec_top_fmc_adc_100Ms.ptwx spec_top_fmc_adc_100Ms.stx spec_top_fmc_adc_100Ms.syr spec_top_fmc_adc_100Ms.twr spec_top_fmc_adc_100Ms.twx spec_top_fmc_adc_100Ms.gise spec_top_fmc_adc_100Ms.unroutes spec_top_fmc_adc_100Ms.ut spec_top_fmc_adc_100Ms.xpi spec_top_fmc_adc_100Ms.xst spec_top_fmc_adc_100Ms_bitgen.xwbt spec_top_fmc_adc_100Ms_envsettings.html spec_top_fmc_adc_100Ms_guide.ncd spec_top_fmc_adc_100Ms_map.map spec_top_fmc_adc_100Ms_map.mrp spec_top_fmc_adc_100Ms_map.ncd spec_top_fmc_adc_100Ms_map.ngm spec_top_fmc_adc_100Ms_map.xrpt spec_top_fmc_adc_100Ms_ngdbuild.xrpt spec_top_fmc_adc_100Ms_pad.csv spec_top_fmc_adc_100Ms_pad.txt spec_top_fmc_adc_100Ms_par.xrpt spec_top_fmc_adc_100Ms_summary.xml spec_top_fmc_adc_100Ms_usage.xml spec_top_fmc_adc_100Ms_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_top_fmc_adc_100Ms" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_top_fmc_adc_100Ms" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="spec_top_fmc_adc_100Ms" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
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<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../rtl/spec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
</project>
Release 13.3 par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
pcbe15575:: Fri Apr 25 16:32:51 2014
par -w -intstyle ise -ol high -mt off spec_top_fmc_adc_100Ms_map.ncd
spec_top_fmc_adc_100Ms.ncd spec_top_fmc_adc_100Ms.pcf
Constraints file: spec_top_fmc_adc_100Ms.pcf.
Loading device for application Rf_Device from file '6slx45t.nph' in environment /opt/Xilinx/13.3/ISE_DS/ISE/.
"spec_top_fmc_adc_100Ms" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:42 - Your license support version '2014.04' for ISE expires in 4 days after which you will not qualify
for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.20 2011-10-03".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 6,815 out of 54,576 12%
Number used as Flip Flops: 6,786
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 29
Number of Slice LUTs: 6,024 out of 27,288 22%
Number used as logic: 5,626 out of 27,288 20%
Number using O6 output only: 3,598
Number using O5 output only: 363
Number using O5 and O6: 1,665
Number used as ROM: 0
Number used as Memory: 34 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 34
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 32
Number used exclusively as route-thrus: 364
Number with same-slice register load: 340
Number with same-slice carry load: 24
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,500 out of 6,822 36%
Nummber of MUXCYs used: 1,660 out of 13,644 12%
Number of LUT Flip Flop pairs used: 8,097
Number with an unused Flip Flop: 2,095 out of 8,097 25%
Number with an unused LUT: 2,073 out of 8,097 25%
Number of fully used LUT-FF pairs: 3,929 out of 8,097 48%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 192 out of 296 64%
Number of LOCed IOBs: 192 out of 192 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 23 out of 116 19%
Number of RAMB8BWERs: 7 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 2 out of 32 6%
Number used as BUFIO2FBs: 2
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 5 out of 16 31%
Number used as BUFGs: 4
Number used as BUFGMUX: 1
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 38 out of 376 10%
Number used as ILOGIC2s: 0
Number used as ISERDES2s: 38
Number of IODELAY2/IODRP2/IODRP2_MCBs: 25 out of 376 6%
Number used as IODELAY2s: 2
Number used as IODRP2s: 1
Number used as IODRP2_MCBs: 22
Number of OLOGIC2/OSERDES2s: 67 out of 376 17%
Number used as OLOGIC2s: 0
Number used as OSERDES2s: 67
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 2 out of 8 25%
Number of BUFPLL_MCBs: 1 out of 4 25%
Number of DSP48A1s: 4 out of 58 6%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 1 out of 2 50%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 4 out of 4 100%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 24 secs
Finished initial Timing Analysis. REAL time: 25 secs
WARNING:Par:288 - The signal aux_buttons_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal aux_buttons_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VC_RDY<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VC_RDY<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal P_WR_REQ<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal P_WR_REQ<1>_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 40605 unrouted; REAL time: 26 secs
Phase 2 : 34579 unrouted; REAL time: 30 secs
Phase 3 : 13915 unrouted; REAL time: 55 secs
Phase 4 : 13928 unrouted; (Setup:0, Hold:1824, Component Switching Limit:0) REAL time: 58 secs
Updating file: spec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:1501, Component Switching Limit:0) REAL time: 1 mins 26 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:1501, Component Switching Limit:0) REAL time: 1 mins 26 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:1501, Component Switching Limit:0) REAL time: 1 mins 26 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:1501, Component Switching Limit:0) REAL time: 1 mins 26 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 27 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 30 secs
Total REAL time to Router completion: 1 mins 30 secs
Total CPU time to Router completion: 1 mins 23 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_125 | BUFGMUX_X3Y13| No | 1208 | 0.069 | 1.280 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_0/cmp_fmc_adc_100M | | | | | |
| s_core/fs_clk | BUFGMUX_X2Y2| No | 226 | 0.257 | 1.473 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/c3_mcb_d | | | | | |
| rp_clk | BUFGMUX_X2Y3| No | 79 | 0.052 | 1.285 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X2Y12| No | 635 | 0.187 | 1.398 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/io_c | | | | | |
| lk | Local| | 41 | 0.064 | 1.562 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_0/cmp_fmc_adc_100M | | | | | |
| s_core/clk_fb_buf | Local| | 19 | 0.000 | 1.473 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/c3_syscl | | | | | |
| k_2x | Local| | 35 | 0.576 | 1.548 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/memc3_wr | | | | | |
|apper_inst/memc3_mcb | | | | | |
|_raw_wrapper_inst/io | | | | | |
| i_drp_clk | Local| | 22 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/c3_syscl | | | | | |
| k_2x_180 | Local| | 37 | 0.590 | 1.562 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/memc3_wr | | | | | |
|apper_inst/memc3_mcb | | | | | |
|_raw_wrapper_inst/id | | | | | |
| elay_dqs_ioi_m | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/memc3_wr | | | | | |
|apper_inst/memc3_mcb | | | | | |
|_raw_wrapper_inst/id | | | | | |
| elay_udqs_ioi_m | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/memc3_wr | | | | | |
|apper_inst/memc3_mcb | | | | | |
|_raw_wrapper_inst/id | | | | | |
| elay_dqs_ioi_s | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/memc3_wr | | | | | |
|apper_inst/memc3_mcb | | | | | |
|_raw_wrapper_inst/id | | | | | |
| elay_udqs_ioi_s | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 18
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | MINPERIOD | 0.001ns| 1.499ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | | | | |
nfrastructure_inst_clk_2x_0_0 = P | | | | |
ERIOD TIMEGRP "cmp_ddr_ctrl_cmp_d | | | | |
dr3_ctrl_wrapper_gen_spec_bank3_64b_32b_c | | | | |
mp_ddr3_ctrl_memc3_infrastructure_inst_cl | | | | |
k_2x_0_0" TS_ddr_clk_buf / 2 HIGH | | | | |
50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | MINPERIOD | 0.001ns| 1.499ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | | | | |
nfrastructure_inst_clk_2x_180_0 = | | | | |
PERIOD TIMEGRP "cmp_ddr_ctrl_cmp | | | | |
_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b | | | | |
_cmp_ddr3_ctrl_memc3_infrastructure_inst_ | | | | |
clk_2x_180_0" TS_ddr_clk_buf / 2 | | | | |
PHASE 0.75 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | MINPERIOD | 0.001ns| 1.499ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | | | | |
nfrastructure_inst_clk_2x_180 = P | | | | |
ERIOD TIMEGRP "cmp_ddr_ctrl_cmp_d | | | | |
dr3_ctrl_wrapper_gen_spec_bank3_64b_32b_c | | | | |
mp_ddr3_ctrl_memc3_infrastructure_inst_cl | | | | |
k_2x_180" TS_SYS_CLK5 / 2 PHASE 0 | | | | |
.75 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | MINPERIOD | 0.001ns| 1.499ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | | | | |
nfrastructure_inst_clk_2x_0 = PER | | | | |
IOD TIMEGRP "cmp_ddr_ctrl_cmp_ddr | | | | |
3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp | | | | |
_ddr3_ctrl_memc3_infrastructure_inst_clk_ | | | | |
2x_0" TS_SYS_CLK5 / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.035ns| 4.965ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.042ns| | 0| 0
core_cmp_clk_in_rx_pllout_x1_0" T | | | | |
S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | | | | |
PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | MINLOWPULSE | 0.364ns| 1.636ns| 0| 0
0Ms_core_dco_clk = PERIOD TIMEGRP | | | | |
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100 | | | | |
Ms_core_dco_clk" TS_adc_dco_n_i H | | | | |
IGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.099ns| 7.901ns| 0| 0
clk_125_buf" TS_clk20_vcxo_i / 6.25 | HOLD | 0.287ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_SYS_CLK5 = PERIOD TIMEGRP "SYS_CLK5" 3 | MINLOWPULSE | 0.428ns| 2.572ns| 0| 0
ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_ddr_clk_buf = PERIOD TIMEGRP "ddr_clk_ | MINLOWPULSE | 0.428ns| 2.572ns| 0| 0
buf" TS_clk20_vcxo_i / 16.6666667 | | | | |
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | SETUP | 0.946ns| 7.054ns| 0| 0
0Ms_core_fs_clk_buf = PERIOD TIMEGRP | HOLD | 0.399ns| | 0| 0
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_ | | | | |
100Ms_core_fs_clk_buf" TS_cmp_fmc | | | | |
_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_d | | | | |
co_clk / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_adc_dco_n_i = PERIOD TIMEGRP "adc_dco_ | MINPERIOD | 1.075ns| 0.925ns| 0| 0
n_i" 2 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
PERIOD TIMEGRP "cmp_gn4124_core_ | | | | |
cmp_clk_in_buf_P_clk" TS_p2l_clkp HIGH 50 | | | | |
% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
= PERIOD TIMEGRP "cmp_gn4124_cor | | | | |
e_cmp_clk_in_buf_P_clk_0" TS_p2l_clkn HIG | | | | |
H 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | MINPERIOD | 1.876ns| 3.124ns| 0| 0
1 = PERIOD TIMEGRP "cmp_gn4124_co | | | | |
re_cmp_clk_in_rx_pllout_x1" TS_cm | | | | |
p_gn4124_core_cmp_clk_in_buf_P_clk PHASE | | | | |
1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk20_vcxo_i = PERIOD TIMEGRP "clk20_v | MINLOWPULSE | 30.000ns| 20.000ns| 0| 0
cxo_i_grp" 50 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | SETUP | 4.268ns| 7.731ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | HOLD | 0.270ns| | 0| 0
nfrastructure_inst_mcb_drp_clk_bufg_in_0 | | | | |
= PERIOD TIMEGRP "cmp_ddr | | | | |
_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank | | | | |
3_64b_32b_cmp_ddr3_ctrl_memc3_infrastruct | | | | |
ure_inst_mcb_drp_clk_bufg_in_0" T | | | | |
S_ddr_clk_buf / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | MINPERIOD | 10.270ns| 1.730ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | | | | |
nfrastructure_inst_mcb_drp_clk_bufg_in | | | | |
= PERIOD TIMEGRP "cmp_ddr_c | | | | |
trl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_ | | | | |
64b_32b_cmp_ddr3_ctrl_memc3_infrastructur | | | | |
e_inst_mcb_drp_clk_bufg_in" TS_SY | | | | |
S_CLK5 / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
s_int_0 = PERIOD TIMEGRP "cmp_gn4 | | | | |
124_core_cmp_clk_in_rx_pllout_xs_int_0" | | | | |
TS_cmp_gn4124_core_cmp_clk_in_buf_ | | | | |
P_clk_0 / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
s_int = PERIOD TIMEGRP "cmp_gn412 | | | | |
4_core_cmp_clk_in_rx_pllout_xs_int" | | | | |
TS_cmp_gn4124_core_cmp_clk_in_buf_P_cl | | | | |
k / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | N/A | N/A| N/A| N/A| N/A
0Ms_core_serdes_clk = PERIOD TIMEGRP | | | | |
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_ | | | | |
100Ms_core_serdes_clk" TS_cmp_fmc | | | | |
_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_d | | | | |
co_clk / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_p2l_clkp
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clkp | 5.000ns| 0.925ns| 3.124ns| 0| 0| 0| 0|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 3.124ns| 0| 0| 0| 0|
| buf_P_clk | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 3.124ns| N/A| 0| 0| 0| 0|
| _rx_pllout_x1 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_p2l_clkn
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clkn | 5.000ns| 0.925ns| 4.965ns| 0| 0| 0| 29557|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.965ns| 0| 0| 0| 29557|
| buf_P_clk_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.965ns| N/A| 0| 0| 29557| 0|
| _rx_pllout_x1_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_clk20_vcxo_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk20_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 398349|
| TS_sys_clk_125_buf | 8.000ns| 7.901ns| N/A| 0| 0| 387949| 0|
| TS_ddr_clk_buf | 3.000ns| 2.572ns| 2.998ns| 0| 0| 0| 10400|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 12.000ns| 7.731ns| N/A| 0| 0| 10400| 0|
| _wrapper_gen_spec_bank3_64b_3| | | | | | | |
| 2b_cmp_ddr3_ctrl_memc3_infras| | | | | | | |
| tructure_inst_mcb_drp_clk_buf| | | | | | | |
| g_in_0 | | | | | | | |
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| _wrapper_gen_spec_bank3_64b_3| | | | | | | |
| 2b_cmp_ddr3_ctrl_memc3_infras| | | | | | | |
| tructure_inst_clk_2x_180_0 | | | | | | | |
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| _wrapper_gen_spec_bank3_64b_3| | | | | | | |
| 2b_cmp_ddr3_ctrl_memc3_infras| | | | | | | |
| tructure_inst_clk_2x_0_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_SYS_CLK5
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_SYS_CLK5 | 3.000ns| 2.572ns| 2.998ns| 0| 0| 0| 0|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_| 12.000ns| 1.730ns| N/A| 0| 0| 0| 0|
| wrapper_gen_spec_bank3_64b_32b| | | | | | | |
| _cmp_ddr3_ctrl_memc3_infrastru| | | | | | | |
| cture_inst_mcb_drp_clk_bufg_in| | | | | | | |
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| wrapper_gen_spec_bank3_64b_32b| | | | | | | |
| _cmp_ddr3_ctrl_memc3_infrastru| | | | | | | |
| cture_inst_clk_2x_180 | | | | | | | |
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| wrapper_gen_spec_bank3_64b_32b| | | | | | | |
| _cmp_ddr3_ctrl_memc3_infrastru| | | | | | | |
| cture_inst_clk_2x_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_adc_dco_n_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc_dco_n_i | 2.000ns| 0.925ns| 1.764ns| 0| 0| 0| 53971|
| TS_cmp_fmc_adc_mezzanine_0_cmp| 2.000ns| 1.636ns| 1.764ns| 0| 0| 0| 53971|
| _fmc_adc_100Ms_core_dco_clk | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_0_cm| 8.000ns| 7.054ns| N/A| 0| 0| 53971| 0|
| p_fmc_adc_100Ms_core_fs_clk_b| | | | | | | |
| uf | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_0_cm| 1.000ns| N/A| N/A| 0| 0| 0| 0|
| p_fmc_adc_100Ms_core_serdes_c| | | | | | | |
| lk | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 33 secs
Total CPU time to PAR completion: 1 mins 26 secs
Peak Memory Usage: 337 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 8
Number of info messages: 1
Writing design to file spec_top_fmc_adc_100Ms.ncd
PAR done!
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
Release 13.3 Map O.76xd (lin)
Xilinx Mapping Report File for Design 'spec_top_fmc_adc_100Ms'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr
off -lc off -power off -o spec_top_fmc_adc_100Ms_map.ncd
spec_top_fmc_adc_100Ms.ngd spec_top_fmc_adc_100Ms.pcf
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Fri Apr 25 16:27:42 2014
Design Summary
--------------
Number of errors: 0
Number of warnings: 8
Slice Logic Utilization:
Number of Slice Registers: 6,815 out of 54,576 12%
Number used as Flip Flops: 6,786
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 29
Number of Slice LUTs: 6,024 out of 27,288 22%
Number used as logic: 5,626 out of 27,288 20%
Number using O6 output only: 3,598
Number using O5 output only: 363
Number using O5 and O6: 1,665
Number used as ROM: 0
Number used as Memory: 34 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 34
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 32
Number used exclusively as route-thrus: 364
Number with same-slice register load: 340
Number with same-slice carry load: 24
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,500 out of 6,822 36%
Nummber of MUXCYs used: 1,660 out of 13,644 12%
Number of LUT Flip Flop pairs used: 8,097
Number with an unused Flip Flop: 2,095 out of 8,097 25%
Number with an unused LUT: 2,073 out of 8,097 25%
Number of fully used LUT-FF pairs: 3,929 out of 8,097 48%
Number of unique control sets: 251
Number of slice register sites lost
to control set restrictions: 532 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 192 out of 296 64%
Number of LOCed IOBs: 192 out of 192 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 23 out of 116 19%
Number of RAMB8BWERs: 7 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 2 out of 32 6%
Number used as BUFIO2FBs: 2
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 5 out of 16 31%
Number used as BUFGs: 4
Number used as BUFGMUX: 1
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 38 out of 376 10%
Number used as ILOGIC2s: 0
Number used as ISERDES2s: 38
Number of IODELAY2/IODRP2/IODRP2_MCBs: 25 out of 376 6%
Number used as IODELAY2s: 2
Number used as IODRP2s: 1
Number used as IODRP2_MCBs: 22
Number of OLOGIC2/OSERDES2s: 67 out of 376 17%
Number used as OLOGIC2s: 0
Number used as OSERDES2s: 67
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 2 out of 8 25%
Number of BUFPLL_MCBs: 1 out of 4 25%
Number of DSP48A1s: 4 out of 58 6%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 1 out of 2 50%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 4 out of 4 100%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.73
Peak Memory Usage: 415 MB
Total REAL time to MAP completion: 5 mins 2 secs
Total CPU time to MAP completion (all processors): 4 mins 55 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your license support version '2014.04' for ISE expires in
4 days after which you will not qualify for Xilinx software updates or new
releases.
WARNING:MapLib:701 - Signal L_CLKp connected to top level port L_CLKp has been
removed.
WARNING:MapLib:701 - Signal L_CLKn connected to top level port L_CLKn has been
removed.
WARNING:MapLib:701 - Signal DDR3_ZIO connected to top level port DDR3_ZIO has
been removed.
WARNING:MapLib:41 - All members of TNM group
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc
3_infrastructure_inst_clk0_bufg_in" have been optimized out of the design.
WARNING:MapLib:41 - All members of TNM group
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc
3_infrastructure_inst_clk0_bufg_in_0" have been optimized out of the design.
WARNING:MapLib:50 - The period specification
"TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_m
emc3_infrastructure_inst_clk0_bufg_in" has been discarded because the group
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc
3_infrastructure_inst_clk0_bufg_in" has been optimized away.
WARNING:MapLib:50 - The period specification
"TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_m
emc3_infrastructure_inst_clk0_bufg_in_0" has been discarded because the group
"cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc
3_infrastructure_inst_clk0_bufg_in_0" has been optimized away.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Section 3 - Informational
-------------------------
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
supports the use of up to 2 processors. Based on the the user options and
machine load, Map will use 2 processors during this run.
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
INFO:LIT:243 - Logical network
cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3
_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 8 more times for the following
(max. 5 shown):
N776,
N778,
aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
94 block(s) removed
2 block(s) optimized away
74 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<24>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_24" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/clk0_bufg" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/U_BUFG_CLK0" (CKBUF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/clk0_bufg_in" is loadless and has been removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<23>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_23" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<22>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_22" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<21>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_21" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<20>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_20" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<19>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_19" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<18>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_18" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<17>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_17" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<16>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_16" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<15>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_15" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<14>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_14" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<13>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_13" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<12>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_12" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<11>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_11" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<10>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_10" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<9>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_9" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<8>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_8" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<7>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_7" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<6>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_6" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<5>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_5" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<4>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_4" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<3>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_3" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<2>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_2" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<1>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_1" (FF) removed.
The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r<0>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst0_sync_r_0" (FF) removed.
*The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst_tmp" is loadless and has been removed.
* Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/rst_tmp1" (ROM) removed.
* The signal
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/syn_clk0_powerup_pll_locked" is loadless and has been
removed.
* Loadless block
"cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_i
nfrastructure_inst/syn_clk0_powerup_pll_locked" (FF) removed.
Loadless block "cmp_clk_250_buf" (CKBUF) removed.
The signal "sys_clk_250_buf" is loadless and has been removed.
Loadless block
"cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/Madd_pre_trig_value[31]_GND_383_
o_add_67_OUT31" (ROM) removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" (FF)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master_rstpot" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master_rstpot"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable" is loadless and has
been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable_rstpot" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable_rstpot" (ROM)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<5>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_5" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter5" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<5>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<4>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<4>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<3>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<3>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<2>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<2>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<1>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<1>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<0>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<0>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>_inv" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>_inv1_INV_0"
(BUF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_8" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter8" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<8>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<7>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<7>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<6>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<6>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<5>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<5>"
(MUX) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<5>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<5>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<6>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<6>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<6>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_6" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter6" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<6>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<7>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<7>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<7>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_7" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter7" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<7>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<0>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<0>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<0>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_0" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<0>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<1>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<1>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<1>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_1" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter1" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<1>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<2>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<2>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<2>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_2" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter2" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<2>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<3>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<3>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<3>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_3" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter3" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<3>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<4>" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<4>"
(ROM) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<4>" is loadless and
has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_4" (FF) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter4" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<4>"
(XOR) removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4" is loadless
and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4" (FF)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4-In" is
loadless and has been removed.
Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/_n0366_inv1" (ROM)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[10].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[11].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[12].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[13].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[14].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[15].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[1].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[2].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[3].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[4].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[5].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[6].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[7].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[8].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[9].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
Loadless block "cmp_l_clk_buf" (IBUFDS) removed.
The signal "L_CLKp" is loadless and has been removed.
Loadless block "L_CLKp" (PAD) removed.
The signal "L_CLKn" is loadless and has been removed.
Loadless block "L_CLKn" (PAD) removed.
The trimmed logic reported below is either:
1. part of a cycle
2. part of disabled logic
3. a side-effect of other trimmed logic
The signal "DDR3_ZIO" is unused and has been removed.
Unused block "DDR3_ZIO_OBUFT" (TRI) removed.
Unused block "DDR3_ZIO" (PAD) removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| DDR3_A<0> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_A<1> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_A<2> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_A<3> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_A<4> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_A<5> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_A<6> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_A<7> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_A<8> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_A<9> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_A<10> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_A<11> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_A<12> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_A<13> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_BA<0> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_BA<1> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_BA<2> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_CAS_N | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_CKE | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_CK_N | IOB | OUTPUT | DIFF_SSTL15_II | | | | OSERDES | | |
| DDR3_CK_P | IOB | OUTPUT | DIFF_SSTL15_II | | | | OSERDES | | |
| DDR3_DQ<0> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<1> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<2> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<3> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<4> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<5> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<6> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<7> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<8> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<9> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<10> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<11> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<12> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<13> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<14> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_DQ<15> | IOB | BIDIR | SSTL15_II | | | | | | |
| DDR3_LDM | IOB | OUTPUT | SSTL15_II | | | | | | |
| DDR3_LDQS_N | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLUP | |
| DDR3_LDQS_P | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLDOWN | |
| DDR3_ODT | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_RAS_N | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_RESET_N | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| DDR3_RZQ | IOB | BIDIR | SSTL15_II | | | | | | DEFAULT |
| DDR3_UDM | IOB | OUTPUT | SSTL15_II | | | | | | |
| DDR3_UDQS_N | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLUP | |
| DDR3_UDQS_P | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLDOWN | |
| DDR3_WE_N | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| GPIO<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| GPIO<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| L2P_CLKn | IOB | OUTPUT | DIFF_SSTL18_I | | | | OSERDES | | |
| L2P_CLKp | IOB | OUTPUT | DIFF_SSTL18_I | | | | OSERDES | | |
| L2P_DATA<0> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<1> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<2> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<3> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<4> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<5> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<6> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<7> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<8> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<9> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<10> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<11> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<12> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<13> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<14> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DATA<15> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_DFRAME | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L2P_EDB | IOB | OUTPUT | SSTL18_I | | | | | | |
| L2P_RDY | IOB | INPUT | SSTL18_I | | | | | | |
| L2P_VALID | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
| L_RST_N | IOB | INPUT | LVCMOS18 | | | | | | |
| L_WR_RDY<0> | IOB | INPUT | SSTL18_I | | | | | | |
| L_WR_RDY<1> | IOB | INPUT | SSTL18_I | | | | | | |
| P2L_CLKn | IOB | INPUT | DIFF_SSTL18_I | | | | | | |
| P2L_CLKp | IOB | INPUT | DIFF_SSTL18_I | | | | ISERDES | | VARIABLE |
| P2L_DATA<0> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<1> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<2> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<3> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<4> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<5> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<6> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<7> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<8> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<9> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<10> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<11> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<12> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<13> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<14> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DATA<15> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_DFRAME | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P2L_RDY | IOB | OUTPUT | SSTL18_I | | | | | | |
| P2L_VALID | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
| P_RD_D_RDY<0> | IOB | INPUT | SSTL18_I | | | | | | |
| P_RD_D_RDY<1> | IOB | INPUT | SSTL18_I | | | | | | |
| P_WR_RDY<0> | IOB | OUTPUT | SSTL18_I | | | | | | |
| P_WR_RDY<1> | IOB | OUTPUT | SSTL18_I | | | | | | |
| P_WR_REQ<0> | IOB | INPUT | SSTL18_I | | | | | | |
| P_WR_REQ<1> | IOB | INPUT | SSTL18_I | | | | | | |
| RX_ERROR | IOB | OUTPUT | SSTL18_I | | | | | | |
| TX_ERROR | IOB | INPUT | SSTL18_I | | | | | | |
| VC_RDY<0> | IOB | INPUT | SSTL18_I | | | | | | |
| VC_RDY<1> | IOB | INPUT | SSTL18_I | | | | | | |
| adc0_dco_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_dco_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_ext_trigger_n_i | IOB | INPUT | LVDS_25 | FALSE | | | | | |
| adc0_ext_trigger_p_i | IOB | INPUT | LVDS_25 | FALSE | | | | | |
| adc0_fr_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_fr_p_i | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_gpio_dac_clr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_led_acq_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_led_trig_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_si570_oe_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_one_wire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc0_outa_n_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outa_n_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outa_n_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outa_n_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outa_p_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outa_p_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outa_p_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outa_p_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outb_n_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outb_n_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outb_n_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outb_n_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outb_p_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outb_p_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outb_p_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outb_p_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_si570_scl_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc0_si570_sda_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_adc_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_dac1_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_dac2_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_dac3_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_dac4_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_din_i | IOB | INPUT | LVCMOS25 | | | | | | |
| adc0_spi_dout_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_sck_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| aux_buttons_i<0> | IOB | INPUT | LVCMOS18 | | | | | | |
| aux_buttons_i<1> | IOB | INPUT | LVCMOS18 | | | | | | |
| aux_leds_o<0> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| aux_leds_o<1> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| aux_leds_o<2> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| aux_leds_o<3> | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| carrier_one_wire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| clk20_vcxo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| fmc0_prsnt_m2c_n_i | IOB | INPUT | LVCMOS25 | | | | | | |
| fmc0_sys_scl_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| fmc0_sys_sda_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| led_green_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| led_red_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pcb_ver_i<0> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<1> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<2> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<3> | IOB | INPUT | LVCMOS15 | | | | | | |
| pll20dac_sync_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll25dac_sync_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| plldac_din_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| plldac_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
*
!.gitignore
!Manifest.py
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := svec_fmc_adc_100Ms.xise
ISE_CRAP := *.b svec_top_fmc_adc_100Ms_summary.html *.tcl svec_top_fmc_adc_100Ms.bld svec_top_fmc_adc_100Ms.cmd_log *.drc svec_top_fmc_adc_100Ms.lso *.ncd svec_top_fmc_adc_100Ms.ngc svec_top_fmc_adc_100Ms.ngd svec_top_fmc_adc_100Ms.ngr svec_top_fmc_adc_100Ms.pad svec_top_fmc_adc_100Ms.par svec_top_fmc_adc_100Ms.pcf svec_top_fmc_adc_100Ms.prj svec_top_fmc_adc_100Ms.ptwx svec_top_fmc_adc_100Ms.stx svec_top_fmc_adc_100Ms.syr svec_top_fmc_adc_100Ms.twr svec_top_fmc_adc_100Ms.twx svec_top_fmc_adc_100Ms.gise svec_top_fmc_adc_100Ms.unroutes svec_top_fmc_adc_100Ms.ut svec_top_fmc_adc_100Ms.xpi svec_top_fmc_adc_100Ms.xst svec_top_fmc_adc_100Ms_bitgen.xwbt svec_top_fmc_adc_100Ms_envsettings.html svec_top_fmc_adc_100Ms_guide.ncd svec_top_fmc_adc_100Ms_map.map svec_top_fmc_adc_100Ms_map.mrp svec_top_fmc_adc_100Ms_map.ncd svec_top_fmc_adc_100Ms_map.ngm svec_top_fmc_adc_100Ms_map.xrpt svec_top_fmc_adc_100Ms_ngdbuild.xrpt svec_top_fmc_adc_100Ms_pad.csv svec_top_fmc_adc_100Ms_pad.txt svec_top_fmc_adc_100Ms_par.xrpt svec_top_fmc_adc_100Ms_summary.xml svec_top_fmc_adc_100Ms_usage.xml svec_top_fmc_adc_100Ms_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
<file xil_pn:name="../svec_top_fmc_adc_100Ms.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
</project>
Release 13.3 par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
pcbe15575:: Fri Apr 25 16:44:56 2014
par -w -intstyle ise -ol high -mt off svec_top_fmc_adc_100Ms_map.ncd
svec_top_fmc_adc_100Ms.ncd svec_top_fmc_adc_100Ms.pcf
Constraints file: svec_top_fmc_adc_100Ms.pcf.
Loading device for application Rf_Device from file '6slx150t.nph' in environment /opt/Xilinx/13.3/ISE_DS/ISE/.
"svec_top_fmc_adc_100Ms" is an NCD, version 3.2, device xc6slx150t, package fgg900, speed -3
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
WARNING:Security:42 - Your license support version '2014.04' for ISE expires in 4 days after which you will not qualify
for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.20 2011-10-03".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 9,485 out of 184,304 5%
Number used as Flip Flops: 9,427
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 58
Number of Slice LUTs: 11,668 out of 92,152 12%
Number used as logic: 11,397 out of 92,152 12%
Number using O6 output only: 8,207
Number using O5 output only: 403
Number using O5 and O6: 2,787
Number used as ROM: 0
Number used as Memory: 77 out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 77
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 72
Number used exclusively as route-thrus: 194
Number with same-slice register load: 172
Number with same-slice carry load: 22
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 4,581 out of 23,038 19%
Nummber of MUXCYs used: 2,760 out of 46,076 5%
Number of LUT Flip Flop pairs used: 13,878
Number with an unused Flip Flop: 5,329 out of 13,878 38%
Number with an unused LUT: 2,210 out of 13,878 15%
Number of fully used LUT-FF pairs: 6,339 out of 13,878 45%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 356 out of 540 65%
Number of LOCed IOBs: 356 out of 356 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 38 out of 268 14%
Number of RAMB8BWERs: 12 out of 536 2%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 2 out of 32 6%
Number used as BUFIO2FBs: 2
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 7 out of 16 43%
Number used as BUFGs: 5
Number used as BUFGMUX: 2
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 36 out of 586 6%
Number used as ILOGIC2s: 0
Number used as ISERDES2s: 36
Number of IODELAY2/IODRP2/IODRP2_MCBs: 46 out of 586 7%
Number used as IODELAY2s: 0
Number used as IODRP2s: 2
Number used as IODRP2_MCBs: 44
Number of OLOGIC2/OSERDES2s: 94 out of 586 16%
Number used as OLOGIC2s: 0
Number used as OSERDES2s: 94
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 2 out of 8 25%
Number of BUFPLL_MCBs: 2 out of 4 50%
Number of DSP48A1s: 8 out of 180 4%
Number of GTPA1_DUALs: 0 out of 4 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 2 out of 4 50%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 5 out of 6 83%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 24 secs
Finished initial Timing Analysis. REAL time: 24 secs
Starting Router
Phase 1 : 74031 unrouted; REAL time: 29 secs
Phase 2 : 64172 unrouted; REAL time: 1 mins 4 secs
Phase 3 : 28426 unrouted; REAL time: 2 mins 1 secs
Phase 4 : 28545 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 19 secs
Updating file: svec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:72, Hold:0, Component Switching Limit:0) REAL time: 3 mins 41 secs
Phase 6 : 0 unrouted; (Setup:45, Hold:0, Component Switching Limit:0) REAL time: 3 mins 47 secs
Updating file: svec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 14 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 14 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 14 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 20 secs
Total REAL time to Router completion: 5 mins 20 secs
Total CPU time to Router completion: 5 mins 30 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_62_5 | BUFGMUX_X2Y2| No | 588 | 0.270 | 1.437 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_125 | BUFGMUX_X2Y1| No | 1899 | 0.350 | 1.436 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c4 | | | | | |
| _mcb_drp_clk | BUFGMUX_X2Y3| No | 79 | 0.166 | 1.438 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c5 | | | | | |
| _mcb_drp_clk | BUFGMUX_X3Y13| No | 78 | 0.185 | 1.289 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_0/cmp_fmc_adc_100M | | | | | |
| s_core/fs_clk | BUFGMUX_X2Y12| No | 240 | 0.376 | 1.463 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_1/cmp_fmc_adc_100M | | | | | |
| s_core/fs_clk | BUFGMUX_X2Y10| No | 240 | 0.377 | 1.463 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc4_infrastructure_i | | | | | |
| nst/sys_clk_ibufg | BUFGMUX_X2Y9| No | 5 | 0.183 | 1.276 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_1/cmp_fmc_adc_100M | | | | | |
| s_core/clk_fb_buf | Local| | 19 | 0.000 | 2.017 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_0/cmp_fmc_adc_100M | | | | | |
| s_core/clk_fb_buf | Local| | 19 | 0.000 | 2.017 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c5 | | | | | |
| _sysclk_2x | Local| | 35 | 0.576 | 1.953 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c4 | | | | | |
| _sysclk_2x | Local| | 35 | 0.571 | 1.948 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc5_wrapper_inst/mem | | | | | |
|c5_mcb_raw_wrapper_i | | | | | |
|nst/idelay_dqs_ioi_s | | | | | |
| | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc5_wrapper_inst/mem | | | | | |
|c5_mcb_raw_wrapper_i | | | | | |
|nst/idelay_dqs_ioi_m | | | | | |
| | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc5_wrapper_inst/mem | | | | | |
|c5_mcb_raw_wrapper_i | | | | | |
| nst/ioi_drp_clk | Local| | 22 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c5 | | | | | |
| _sysclk_2x_180 | Local| | 37 | 0.590 | 1.967 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc5_wrapper_inst/mem | | | | | |
|c5_mcb_raw_wrapper_i | | | | | |
|nst/idelay_udqs_ioi_ | | | | | |
| s | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc5_wrapper_inst/mem | | | | | |
|c5_mcb_raw_wrapper_i | | | | | |
|nst/idelay_udqs_ioi_ | | | | | |
| m | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc4_wrapper_inst/mem | | | | | |
|c4_mcb_raw_wrapper_i | | | | | |
| nst/ioi_drp_clk | Local| | 22 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c4 | | | | | |
| _sysclk_2x_180 | Local| | 37 | 0.590 | 1.967 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc4_wrapper_inst/mem | | | | | |
|c4_mcb_raw_wrapper_i | | | | | |
|nst/idelay_dqs_ioi_s | | | | | |
| | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc4_wrapper_inst/mem | | | | | |
|c4_mcb_raw_wrapper_i | | | | | |
|nst/idelay_dqs_ioi_m | | | | | |
| | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc4_wrapper_inst/mem | | | | | |
|c4_mcb_raw_wrapper_i | | | | | |
|nst/idelay_udqs_ioi_ | | | | | |
| s | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc4_wrapper_inst/mem | | | | | |
|c4_mcb_raw_wrapper_i | | | | | |
|nst/idelay_udqs_ioi_ | | | | | |
| m | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 11
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapp | MINPERIOD | 0.001ns| 1.499ns| 0| 0
er_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_m | | | | |
emc4_infrastructure_inst_clk_2x_180 | | | | |
= PERIOD TIMEGRP "cmp_ddr_ctrl | | | | |
_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_ban | | | | |
k4_64b_32b_cmp_ddr3_ctrl_memc4_infrastruc | | | | |
ture_inst_clk_2x_180" TS_ddr_clk_ | | | | |
buf / 2 PHASE 0.75 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapp | MINPERIOD | 0.001ns| 1.499ns| 0| 0
er_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_m | | | | |
emc4_infrastructure_inst_clk_2x_0 | | | | |
= PERIOD TIMEGRP "cmp_ddr_ctrl_b | | | | |
ank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4 | | | | |
_64b_32b_cmp_ddr3_ctrl_memc4_infrastructu | | | | |
re_inst_clk_2x_0" TS_ddr_clk_buf | | | | |
/ 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapp | MINPERIOD | 0.001ns| 1.499ns| 0| 0
er_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_m | | | | |
emc5_infrastructure_inst_clk_2x_0 | | | | |
= PERIOD TIMEGRP "cmp_ddr_ctrl_b | | | | |
ank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5 | | | | |
_64b_32b_cmp_ddr3_ctrl_memc5_infrastructu | | | | |
re_inst_clk_2x_0" TS_ddr_clk_buf | | | | |
/ 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapp | MINPERIOD | 0.001ns| 1.499ns| 0| 0
er_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_m | | | | |
emc5_infrastructure_inst_clk_2x_180 | | | | |
= PERIOD TIMEGRP "cmp_ddr_ctrl | | | | |
_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_ban | | | | |
k5_64b_32b_cmp_ddr3_ctrl_memc5_infrastruc | | | | |
ture_inst_clk_2x_180" TS_ddr_clk_ | | | | |
buf / 2 PHASE 0.75 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | MINLOWPULSE | 0.364ns| 1.636ns| 0| 0
0Ms_core_dco_clk = PERIOD TIMEGRP | | | | |
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100 | | | | |
Ms_core_dco_clk" TS_adc0_dco_n_i | | | | |
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_10 | MINLOWPULSE | 0.364ns| 1.636ns| 0| 0
0Ms_core_dco_clk = PERIOD TIMEGRP | | | | |
"cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100 | | | | |
Ms_core_dco_clk" TS_adc1_dco_n_i | | | | |
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.233ns| 7.767ns| 0| 0
clk_125_buf" TS_clk_20m_vcxo_i / 6.25 | HOLD | 0.170ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_62_5_buf = PERIOD TIMEGRP "sys | SETUP | 0.277ns| 15.723ns| 0| 0
_clk_62_5_buf" TS_clk_20m_vcxo_i / | HOLD | 0.057ns| | 0| 0
3.125 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | SETUP | 0.296ns| 7.704ns| 0| 0
0Ms_core_fs_clk_buf = PERIOD TIMEGRP | HOLD | 0.438ns| | 0| 0
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_ | | | | |
100Ms_core_fs_clk_buf" TS_cmp_fmc | | | | |
_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_d | | | | |
co_clk / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_ddr_clk_buf = PERIOD TIMEGRP "ddr_clk_ | SETUP | 1.545ns| 1.454ns| 0| 0
buf" TS_clk_20m_vcxo_i / 16.6666667 | HOLD | 0.562ns| | 0| 0
HIGH 50% | MINLOWPULSE | 0.428ns| 2.572ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_10 | SETUP | 0.454ns| 7.546ns| 0| 0
0Ms_core_fs_clk_buf = PERIOD TIMEGRP | HOLD | 0.399ns| | 0| 0
"cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_ | | | | |
100Ms_core_fs_clk_buf" TS_cmp_fmc | | | | |
_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_d | | | | |
co_clk / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_adc0_dco_n_i = PERIOD TIMEGRP "adc0_dc | MINPERIOD | 1.075ns| 0.925ns| 0| 0
o_n_i" 2 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_adc1_dco_n_i = PERIOD TIMEGRP "adc1_dc | MINPERIOD | 1.075ns| 0.925ns| 0| 0
o_n_i" 2 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_2 | MINLOWPULSE | 30.000ns| 20.000ns| 0| 0
0m_vcxo_i" 50 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapp | SETUP | 4.933ns| 7.066ns| 0| 0
er_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_m | HOLD | 0.417ns| | 0| 0
emc5_infrastructure_inst_mcb_drp_clk_bufg | | | | |
_in = PERIOD TIMEGRP "cmp | | | | |
_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen | | | | |
_svec_bank5_64b_32b_cmp_ddr3_ctrl_memc5_i | | | | |
nfrastructure_inst_mcb_drp_clk_bufg_in" | | | | |
TS_ddr_clk_buf / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapp | SETUP | 5.132ns| 6.867ns| 0| 0
er_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_m | HOLD | 0.388ns| | 0| 0
emc4_infrastructure_inst_mcb_drp_clk_bufg | | | | |
_in = PERIOD TIMEGRP "cmp | | | | |
_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen | | | | |
_svec_bank4_64b_32b_cmp_ddr3_ctrl_memc4_i | | | | |
nfrastructure_inst_mcb_drp_clk_bufg_in" | | | | |
TS_ddr_clk_buf / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | N/A | N/A| N/A| N/A| N/A
0Ms_core_serdes_clk = PERIOD TIMEGRP | | | | |
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_ | | | | |
100Ms_core_serdes_clk" TS_cmp_fmc | | | | |
_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_d | | | | |
co_clk / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_10 | N/A | N/A| N/A| N/A| N/A
0Ms_core_serdes_clk = PERIOD TIMEGRP | | | | |
"cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_ | | | | |
100Ms_core_serdes_clk" TS_cmp_fmc | | | | |
_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_d | | | | |
co_clk / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_clk_20m_vcxo_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_20m_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 2532520|
| TS_sys_clk_62_5_buf | 16.000ns| 15.723ns| N/A| 0| 0| 1756234| 0|
| TS_sys_clk_125_buf | 8.000ns| 7.767ns| N/A| 0| 0| 755348| 0|
| TS_ddr_clk_buf | 3.000ns| 2.572ns| 2.998ns| 0| 0| 6| 20932|
| TS_cmp_ddr_ctrl_bank4_cmp_ddr| 12.000ns| 6.867ns| N/A| 0| 0| 10471| 0|
| 3_ctrl_wrapper_gen_svec_bank4| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc4_| | | | | | | |
| infrastructure_inst_mcb_drp_c| | | | | | | |
| lk_bufg_in | | | | | | | |
| TS_cmp_ddr_ctrl_bank4_cmp_ddr| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| 3_ctrl_wrapper_gen_svec_bank4| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc4_| | | | | | | |
| infrastructure_inst_clk_2x_18| | | | | | | |
| 0 | | | | | | | |
| TS_cmp_ddr_ctrl_bank4_cmp_ddr| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| 3_ctrl_wrapper_gen_svec_bank4| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc4_| | | | | | | |
| infrastructure_inst_clk_2x_0 | | | | | | | |
| TS_cmp_ddr_ctrl_bank5_cmp_ddr| 12.000ns| 7.066ns| N/A| 0| 0| 10461| 0|
| 3_ctrl_wrapper_gen_svec_bank5| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc5_| | | | | | | |
| infrastructure_inst_mcb_drp_c| | | | | | | |
| lk_bufg_in | | | | | | | |
| TS_cmp_ddr_ctrl_bank5_cmp_ddr| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| 3_ctrl_wrapper_gen_svec_bank5| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc5_| | | | | | | |
| infrastructure_inst_clk_2x_18| | | | | | | |
| 0 | | | | | | | |
| TS_cmp_ddr_ctrl_bank5_cmp_ddr| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| 3_ctrl_wrapper_gen_svec_bank5| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc5_| | | | | | | |
| infrastructure_inst_clk_2x_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_adc0_dco_n_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc0_dco_n_i | 2.000ns| 0.925ns| 1.926ns| 0| 0| 0| 53953|
| TS_cmp_fmc_adc_mezzanine_0_cmp| 2.000ns| 1.636ns| 1.926ns| 0| 0| 0| 53953|
| _fmc_adc_100Ms_core_dco_clk | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_0_cm| 8.000ns| 7.704ns| N/A| 0| 0| 53953| 0|
| p_fmc_adc_100Ms_core_fs_clk_b| | | | | | | |
| uf | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_0_cm| 1.000ns| N/A| N/A| 0| 0| 0| 0|
| p_fmc_adc_100Ms_core_serdes_c| | | | | | | |
| lk | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_adc1_dco_n_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc1_dco_n_i | 2.000ns| 0.925ns| 1.887ns| 0| 0| 0| 53971|
| TS_cmp_fmc_adc_mezzanine_1_cmp| 2.000ns| 1.636ns| 1.887ns| 0| 0| 0| 53971|
| _fmc_adc_100Ms_core_dco_clk | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_1_cm| 8.000ns| 7.546ns| N/A| 0| 0| 53971| 0|
| p_fmc_adc_100Ms_core_fs_clk_b| | | | | | | |
| uf | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_1_cm| 1.000ns| N/A| N/A| 0| 0| 0| 0|
| p_fmc_adc_100Ms_core_serdes_c| | | | | | | |
| lk | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 5 mins 28 secs
Total CPU time to PAR completion: 5 mins 38 secs
Peak Memory Usage: 615 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0
Writing design to file svec_top_fmc_adc_100Ms.ncd
PAR done!
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
Release 13.3 Map O.76xd (lin)
Xilinx Mapping Report File for Design 'svec_top_fmc_adc_100Ms'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr
off -lc off -power off -o svec_top_fmc_adc_100Ms_map.ncd
svec_top_fmc_adc_100Ms.ngd svec_top_fmc_adc_100Ms.pcf
Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Fri Apr 25 16:36:58 2014
Design Summary
--------------
Number of errors: 0
Number of warnings: 7
Slice Logic Utilization:
Number of Slice Registers: 9,485 out of 184,304 5%
Number used as Flip Flops: 9,427
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 58
Number of Slice LUTs: 11,668 out of 92,152 12%
Number used as logic: 11,397 out of 92,152 12%
Number using O6 output only: 8,207
Number using O5 output only: 403
Number using O5 and O6: 2,787
Number used as ROM: 0
Number used as Memory: 77 out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 77
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 72
Number used exclusively as route-thrus: 194
Number with same-slice register load: 172
Number with same-slice carry load: 22
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 4,581 out of 23,038 19%
Nummber of MUXCYs used: 2,760 out of 46,076 5%
Number of LUT Flip Flop pairs used: 13,878
Number with an unused Flip Flop: 5,329 out of 13,878 38%
Number with an unused LUT: 2,210 out of 13,878 15%
Number of fully used LUT-FF pairs: 6,339 out of 13,878 45%
Number of unique control sets: 369
Number of slice register sites lost
to control set restrictions: 808 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 356 out of 540 65%
Number of LOCed IOBs: 356 out of 356 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 38 out of 268 14%
Number of RAMB8BWERs: 12 out of 536 2%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 2 out of 32 6%
Number used as BUFIO2FBs: 2
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 7 out of 16 43%
Number used as BUFGs: 5
Number used as BUFGMUX: 2
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 36 out of 586 6%
Number used as ILOGIC2s: 0
Number used as ISERDES2s: 36
Number of IODELAY2/IODRP2/IODRP2_MCBs: 46 out of 586 7%
Number used as IODELAY2s: 0
Number used as IODRP2s: 2
Number used as IODRP2_MCBs: 44
Number of OLOGIC2/OSERDES2s: 94 out of 586 16%
Number used as OLOGIC2s: 0
Number used as OSERDES2s: 94
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 2 out of 8 25%
Number of BUFPLL_MCBs: 2 out of 4 50%
Number of DSP48A1s: 8 out of 180 4%
Number of GTPA1_DUALs: 0 out of 4 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 2 out of 4 50%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 5 out of 6 83%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.97
Peak Memory Usage: 624 MB
Total REAL time to MAP completion: 7 mins 51 secs
Total CPU time to MAP completion (all processors): 8 mins 5 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your license support version '2014.04' for ISE expires in
4 days after which you will not qualify for Xilinx software updates or new
releases.
WARNING:MapLib:701 - Signal ddr0_zio_b connected to top level port ddr0_zio_b
has been removed.
WARNING:MapLib:701 - Signal ddr1_zio_b connected to top level port ddr1_zio_b
has been removed.
WARNING:MapLib:41 - All members of TNM group
"cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctr
l_memc4_infrastructure_inst_clk0_bufg_in" have been optimized out of the
design.
WARNING:MapLib:41 - All members of TNM group
"cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctr
l_memc5_infrastructure_inst_clk0_bufg_in" have been optimized out of the
design.
WARNING:MapLib:50 - The period specification
"TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_
ctrl_memc4_infrastructure_inst_clk0_bufg_in" has been discarded because the
group
"cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctr
l_memc4_infrastructure_inst_clk0_bufg_in" has been optimized away.
WARNING:MapLib:50 - The period specification
"TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_
ctrl_memc5_infrastructure_inst_clk0_bufg_in" has been discarded because the
group
"cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctr
l_memc5_infrastructure_inst_clk0_bufg_in" has been optimized away.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Section 3 - Informational
-------------------------
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
supports the use of up to 2 processors. Based on the the user options and
machine load, Map will use 2 processors during this run.
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
INFO:LIT:243 - Logical network
cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl
/memc4_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 6 more times for the following
(max. 5 shown):
cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl
/memc5_infrastructure_inst/rst0_sync_r<24>,
N1803,
N1805,
N1809,
N1811
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
62 block(s) removed
2 block(s) optimized away
60 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<24>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_24" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/clk0_bufg" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/U_BUFG_CLK0" (CKBUF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/clk0_bufg_in" is loadless and has been removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<23>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_23" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<22>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_22" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<21>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_21" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<20>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_20" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<19>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_19" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<18>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_18" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<17>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_17" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<16>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_16" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<15>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_15" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<14>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_14" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<13>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_13" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<12>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_12" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<11>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_11" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<10>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_10" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<9>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_9" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<8>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_8" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<7>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_7" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<6>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_6" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<5>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_5" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<4>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_4" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<3>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_3" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<2>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_2" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<1>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_1" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<0>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_0" (FF) removed.
*The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst_tmp" is loadless and has been removed.
* Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst_tmp1" (ROM) removed.
* The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/syn_clk0_powerup_pll_locked" is loadless and has been
removed.
* Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/syn_clk0_powerup_pll_locked" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<24>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_24" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/clk0_bufg" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/U_BUFG_CLK0" (CKBUF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/clk0_bufg_in" is loadless and has been removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<23>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_23" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<22>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_22" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<21>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_21" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<20>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_20" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<19>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_19" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<18>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_18" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<17>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_17" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<16>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_16" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<15>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_15" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<14>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_14" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<13>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_13" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<12>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_12" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<11>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_11" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<10>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_10" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<9>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_9" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<8>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_8" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<7>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_7" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<6>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_6" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<5>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_5" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<4>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_4" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<3>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_3" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<2>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_2" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<1>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_1" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<0>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_0" (FF) removed.
*The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst_tmp" is loadless and has been removed.
* Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst_tmp1" (ROM) removed.
* The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/syn_clk0_powerup_pll_locked" is loadless and has been
removed.
* Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/syn_clk0_powerup_pll_locked" (FF) removed.
Loadless block
"cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/Madd_pre_trig_value[31]_GND_208_
o_add_67_OUT31" (ROM) removed.
Loadless block
"cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/Madd_pre_trig_value[31]_GND_208_
o_add_67_OUT31" (ROM) removed.
The trimmed logic reported below is either:
1. part of a cycle
2. part of disabled logic
3. a side-effect of other trimmed logic
The signal "ddr0_zio_b" is unused and has been removed.
Unused block "ddr0_zio_b_OBUFT" (TRI) removed.
The signal "ddr1_zio_b" is unused and has been removed.
Unused block "ddr1_zio_b_OBUFT" (TRI) removed.
Unused block "ddr0_zio_b" (PAD) removed.
Unused block "ddr1_zio_b" (PAD) removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| adc0_dco_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_dco_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_ext_trigger_n_i | IOB | INPUT | LVDS_25 | FALSE | | | | | |
| adc0_ext_trigger_p_i | IOB | INPUT | LVDS_25 | FALSE | | | | | |
| adc0_fr_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_fr_p_i | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_gpio_dac_clr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_led_acq_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_led_trig_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_si570_oe_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_one_wire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc0_outa_n_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outa_n_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outa_n_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outa_n_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outa_p_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outa_p_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outa_p_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outa_p_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outb_n_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outb_n_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outb_n_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outb_n_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outb_p_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outb_p_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outb_p_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outb_p_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_si570_scl_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc0_si570_sda_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_adc_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_dac1_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_dac2_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_dac3_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_dac4_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_din_i | IOB | INPUT | LVCMOS25 | | | | | | |
| adc0_spi_dout_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_sck_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_dco_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_dco_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_ext_trigger_n_i | IOB | INPUT | LVDS_25 | FALSE | | | | | |
| adc1_ext_trigger_p_i | IOB | INPUT | LVDS_25 | FALSE | | | | | |
| adc1_fr_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_fr_p_i | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_gpio_dac_clr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_led_acq_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_led_trig_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_si570_oe_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch1_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch1_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch1_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch1_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch1_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch1_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch1_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch2_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch2_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch2_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch2_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch2_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch2_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch2_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch3_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch3_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch3_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch3_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch3_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch3_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch3_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch4_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch4_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch4_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch4_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch4_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch4_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch4_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_one_wire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc1_outa_n_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outa_n_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outa_n_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outa_n_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outa_p_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_outa_p_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_outa_p_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_outa_p_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_outb_n_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outb_n_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outb_n_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outb_n_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outb_p_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_outb_p_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_outb_p_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_outb_p_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_si570_scl_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc1_si570_sda_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc1_spi_cs_adc_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_spi_cs_dac1_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_spi_cs_dac2_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_spi_cs_dac3_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_spi_cs_dac4_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_spi_din_i | IOB | INPUT | LVCMOS25 | | | | | | |
| adc1_spi_dout_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_spi_sck_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| carrier_one_wire_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| carrier_scl_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| carrier_sda_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| clk_20m_vcxo_i | IOB | INPUT | LVCMOS33 | | | | | | |
| ddr0_a_o<0> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<1> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<2> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<3> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<4> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<5> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<6> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<7> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<8> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<9> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<10> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<11> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<12> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<13> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_ba_o<0> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_ba_o<1> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_ba_o<2> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_cas_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_ck_n_o | IOB | OUTPUT | DIFF_SSTL15_II | | | | OSERDES | | |
| ddr0_ck_p_o | IOB | OUTPUT | DIFF_SSTL15_II | | | | OSERDES | | |
| ddr0_cke_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_dq_b<0> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<1> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<2> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<3> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<4> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<5> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<6> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<7> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<8> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<9> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<10> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<11> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<12> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<13> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<14> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<15> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_ldm_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| ddr0_ldqs_n_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLUP | |
| ddr0_ldqs_p_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLDOWN | |
| ddr0_odt_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_ras_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_reset_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_rzq_b | IOB | BIDIR | SSTL15_II | | | | | | DEFAULT |
| ddr0_udm_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| ddr0_udqs_n_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLUP | |
| ddr0_udqs_p_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLDOWN | |
| ddr0_we_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<0> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<1> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<2> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<3> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<4> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<5> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<6> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<7> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<8> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<9> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<10> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<11> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<12> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<13> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_ba_o<0> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_ba_o<1> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_ba_o<2> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_cas_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_ck_n_o | IOB | OUTPUT | DIFF_SSTL15_II | | | | OSERDES | | |
| ddr1_ck_p_o | IOB | OUTPUT | DIFF_SSTL15_II | | | | OSERDES | | |
| ddr1_cke_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_dq_b<0> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<1> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<2> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<3> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<4> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<5> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<6> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<7> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<8> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<9> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<10> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<11> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<12> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<13> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<14> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<15> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_ldm_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| ddr1_ldqs_n_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLUP | |
| ddr1_ldqs_p_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLDOWN | |
| ddr1_odt_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_ras_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_reset_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_rzq_b | IOB | BIDIR | SSTL15_II | | | | | | DEFAULT |
| ddr1_udm_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| ddr1_udqs_n_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLUP | |
| ddr1_udqs_p_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLDOWN | |
| ddr1_we_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| fmc0_prsnt_m2c_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| fmc0_scl_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| fmc0_sda_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| fmc1_prsnt_m2c_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| fmc1_scl_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| fmc1_sda_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_oen_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_oen_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pcbrev_i<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| pcbrev_i<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| pcbrev_i<2> | IOB | INPUT | LVCMOS25 | | | | | | |
| pcbrev_i<3> | IOB | INPUT | LVCMOS25 | | | | | | |
| pcbrev_i<4> | IOB | INPUT | LVCMOS25 | | | | | | |
| pll20dac_din_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll20dac_sclk_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll20dac_sync_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll25dac_din_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll25dac_sclk_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll25dac_sync_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| rst_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_addr_b<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<8> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<9> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<10> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<11> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<12> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<13> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<14> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<15> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<16> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<17> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<18> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<19> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<20> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<21> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<22> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<23> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<24> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<25> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<26> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<27> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<28> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<29> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<30> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<31> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_dir_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_oe_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_am_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_am_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_am_i<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_am_i<3> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_am_i<4> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_am_i<5> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_as_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_berr_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<0> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<8> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<9> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<10> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<11> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<12> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<13> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<14> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<15> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<16> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<17> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<18> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<19> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<20> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<21> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<22> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<23> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<24> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<25> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<26> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<27> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<28> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<29> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<30> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<31> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_dir_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_oe_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_ds_n_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_ds_n_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_dtack_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_dtack_oe_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_ga_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_ga_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_ga_i<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_ga_i<3> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_ga_i<4> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_ga_i<5> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_iack_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_iackin_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_iackout_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_irq_n_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_irq_n_o<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_irq_n_o<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_irq_n_o<4> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_irq_n_o<5> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_irq_n_o<6> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_irq_n_o<7> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_lword_n_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_retry_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_retry_oe_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_sysreset_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_write_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
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