hdl: Move timetag core outside of spec dir.

The timetag core is meant to be shared between different carriers.

hdl: Move timetag core outside of spec dir.
The timetag core is meant to be shared between different carriers.
9ddb9144 · Matthieu Cattin · 9c1921a3 · 9ddb9144 · 9ddb9144 · 9ddb9144
Commit 9ddb9144 authored Jul 04, 2013 by Matthieu Cattin
10 changed files
--- a/hdl/ip_cores/timetag_core/rtl/Manifest.py
+++ b/hdl/ip_cores/timetag_core/rtl/Manifest.py
+files = [
+    "timetag_core_regs.vhd",
+    "timetag_core.vhd"]
--- a/hdl/spec/rtl/timetag_core.vhd
+++ b/hdl/spec/rtl/timetag_core.vhd
--- a/hdl/spec/rtl/timetag_core_regs.vhd
+++ b/hdl/spec/rtl/timetag_core_regs.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ../rtl/timetag_core_regs.vhd
 -- Author         : auto-generated by wbgen2 from timetag_core_regs.wb
-- Created        : Mon May  6 17:45:24 2013
+-- Created        : Thu Jul  4 18:04:57 2013
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb

--- a/hdl/ip_cores/timetag_core/wb_gen/Makefile
+++ b/hdl/ip_cores/timetag_core/wb_gen/Makefile
+WBGEN2=~/projects/wbgen2/wbgen2
+RTL=../rtl/
+TEX=../../../../documentation/manuals/firmware/
+
+timetag_core_regs:
+	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
+	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
--- a/hdl/spec/wb_gen/timetag_core_regs.h
+++ b/hdl/spec/wb_gen/timetag_core_regs.h
@@ -3,7 +3,7 @@

  * File           : timetag_core_regs.h
  * Author         : auto-generated by wbgen2 from timetag_core_regs.wb
-  * Created        : Mon May  6 17:45:24 2013
+  * Created        : Thu Jul  4 18:04:57 2013
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb

--- a/hdl/spec/wb_gen/timetag_core_regs.htm
+++ b/hdl/spec/wb_gen/timetag_core_regs.htm
--- a/hdl/spec/wb_gen/timetag_core_regs.wb
+++ b/hdl/spec/wb_gen/timetag_core_regs.wb
--- a/hdl/spec/rtl/Manifest.py
+++ b/hdl/spec/rtl/Manifest.py
 files = [
    "spec_top_fmc_adc_100Ms.vhd",
    "carrier_csr.vhd",
-    "timetag_core_regs.vhd",
-    "timetag_core.vhd",
    "irq_controller_regs.vhd",
    "irq_controller.vhd",
    "sdb_meta_pkg.vhd"]
--- a/hdl/spec/syn/Manifest.py
+++ b/hdl/spec/syn/Manifest.py
@@ -15,10 +15,11 @@ files = [
    "../../ip_cores/adc_serdes.vhd",
    "../../ip_cores/monostable/monostable_rtl.vhd",
    "../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd",
-    "../../ip_cores/utils/utils_pkg.vhd",]
+    "../../ip_cores/utils/utils_pkg.vhd"]

 modules = { "local" : ["../rtl",
-                       "../../adc/rtl"],
+                       "../../adc/rtl",
+                       "../../ip_cores/timetag_core/rtl"],
            "git" : ["git://ohwr.org/hdl-core-lib/general-cores.git::sdb_extension",
                     "git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::spec_bank3_64b_32b",
                     "git://ohwr.org/hdl-core-lib/gn4124-core.git::master"]}

--- a/hdl/spec/wb_gen/Makefile
+++ b/hdl/spec/wb_gen/Makefile
@@ -6,10 +6,6 @@ carrier_csr:
 	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
 	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb

-timetag_core_regs:
-	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
-	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
-
 irq_controller_regs:
 	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
 	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb