Skip to content

F
FMC ADC 100M 14b 4cha - Gateware
Commit 91a35cb4 authored by mcattin's avatar mcattin
Browse files
Options

Update general-cores library components interfaces. 

Wishbone components map updated to fit the new entities.
 -> generic to select interface mode (classic/pipelined) and address granularity (byte/word).
 -> wishbone address port size.



git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@126 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent d63286ab
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 2156 additions and 1347 deletions
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ 91a35cb4
......@@ -715,9 +715,11 @@ begin
------------------------------------------------------------------------------
cmp_carrier_onewire : wb_onewire_master
generic map(
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
)
port map(
clk_sys_i => sys_clk_125,
......@@ -727,7 +729,7 @@ begin
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_adr_i => wb_adr(1 downto 0),
wb_adr_i => wb_adr(2 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_CARRIER_ONE_WIRE * 32 + 31 downto 32 * c_CSR_WB_CARRIER_ONE_WIRE),
wb_ack_o => wb_ack(c_CSR_WB_CARRIER_ONE_WIRE),
......@@ -892,11 +894,15 @@ begin
-- Access to mezzanine EEPROM
------------------------------------------------------------------------------
cmp_fmc_sys_i2c : wb_i2c_master
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
)
port map (
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_adr_i => wb_adr(2 downto 0),
wb_adr_i => wb_adr(4 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_FMC_SYS_I2C * 32 + 31 downto 32 * c_CSR_WB_FMC_SYS_I2C),
wb_we_i => wb_we,
......@@ -930,11 +936,15 @@ begin
-- ADC control
------------------------------------------------------------------------------
cmp_fmc_spi : wb_spi
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
)
port map (
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_adr_i => wb_adr(2 downto 0),
wb_adr_i => wb_adr(4 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_FMC_SPI * 32 + 31 downto c_CSR_WB_FMC_SPI * 32),
wb_sel_i => wb_sel,
......@@ -980,11 +990,15 @@ begin
-- Note: I2C registers are 8-bit wide, but accessed as 32-bit registers
------------------------------------------------------------------------------
cmp_fmc_i2c : wb_i2c_master
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
)
port map (
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_adr_i => wb_adr(2 downto 0),
wb_adr_i => wb_adr(4 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_FMC_I2C * 32 + 31 downto 32 * c_CSR_WB_FMC_I2C),
wb_we_i => wb_we,
......@@ -1079,6 +1093,8 @@ begin
------------------------------------------------------------------------------
cmp_fmc_onewire : wb_onewire_master
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
......@@ -1091,7 +1107,7 @@ begin
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_adr_i => wb_adr(1 downto 0),
wb_adr_i => wb_adr(2 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_FMC_ONE_WIRE * 32 + 31 downto 32 * c_CSR_WB_FMC_ONE_WIRE),
wb_ack_o => wb_ack(c_CSR_WB_FMC_ONE_WIRE),
......
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ 91a35cb4
......@@ -546,8 +546,8 @@ NET "AUX_LEDS_O[3]" IOSTANDARD = "LVCMOS18";
INST "cmp_gn4124_core/l2p_rdy_t" IOB=FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t*" IOB=FALSE;
INST "cmp_fmc_spi/cmp_wrapped_spi/shift/s_out" IOB=FALSE;
INST "cmp_fmc_spi/cmp_wrapped_spi/clgen/clk_out" IOB=FALSE;
INST "cmp_fmc_spi/Wrapped_SPI/shift/s_out" IOB=FALSE;
INST "cmp_fmc_spi/Wrapped_SPI/clgen/clk_out" IOB=FALSE;
#===============================================================================
......
hdl/spec/syn/spec_fmc_adc_100Ms.xise
View file @ 91a35cb4
This diff is collapsed.
hdl/spec/syn/spec_top_fmc_adc_100Ms.par
View file @ 91a35cb4
This diff is collapsed.
hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
View file @ 91a35cb4
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
View file @ 91a35cb4
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
View file @ 91a35cb4
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jul 11 17:02:59 2012
Mapped Date : Fri Aug 3 16:35:35 2012
Design Summary
--------------
......@@ -23,11 +23,11 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,386 out of 27,288 19%
Number used as logic: 4,924 out of 27,288 18%
Number using O6 output only: 3,103
Number of Slice LUTs: 5,460 out of 27,288 20%
Number used as logic: 4,929 out of 27,288 18%
Number using O6 output only: 3,109
Number using O5 output only: 279
Number using O5 and O6: 1,542
Number using O5 and O6: 1,541
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -36,18 +36,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 460
Number with same-slice register load: 449
Number used exclusively as route-thrus: 529
Number with same-slice register load: 518
Number with same-slice carry load: 11
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,496 out of 6,822 36%
Number of occupied Slices: 2,365 out of 6,822 34%
Nummber of MUXCYs used: 1,424 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,727
Number with an unused Flip Flop: 1,807 out of 7,727 23%
Number with an unused LUT: 2,341 out of 7,727 30%
Number of fully used LUT-FF pairs: 3,579 out of 7,727 46%
Number of LUT Flip Flop pairs used: 7,523
Number with an unused Flip Flop: 1,673 out of 7,523 22%
Number with an unused LUT: 2,063 out of 7,523 27%
Number of fully used LUT-FF pairs: 3,787 out of 7,523 50%
Number of unique control sets: 261
Number of slice register sites lost
to control set restrictions: 686 out of 54,576 1%
......@@ -102,9 +102,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.76
Peak Memory Usage: 411 MB
Total REAL time to MAP completion: 4 mins 32 secs
Total CPU time to MAP completion (all processors): 4 mins 36 secs
Peak Memory Usage: 413 MB
Total REAL time to MAP completion: 4 mins 48 secs
Total CPU time to MAP completion (all processors): 4 mins 50 secs
Table of Contents
-----------------
......@@ -164,8 +164,8 @@ INFO:LIT:243 - Logical network
_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 9 more times for the following
(max. 5 shown):
N640,
N642,
N648,
N650,
aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment