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FMC ADC 100M 14b 4cha - Gateware
Commit 7cba45b1 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: remove unused test_data feature from CSR

parent d6bd022b
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Showing with 1 addition and 23 deletions
hdl/cheby/fmc_adc_100Ms_csr.cheby
View file @ 7cba45b1
...@@ -41,13 +41,6 @@ memory-map: ...@@ -41,13 +41,6 @@ memory-map:
description: Manual serdes bitslip (ignore on read) description: Manual serdes bitslip (ignore on read)
x-hdl: x-hdl:
type: wire type: wire
- field:
name: test_data_en
range: 5
description: Enable test data
comment: |
Write the DDR RAM address counter value instead of ADC data to DDR.
Note that no timetags are appended at the end of test data.
- field: - field:
name: trig_led name: trig_led
range: 6 range: 6
......
hdl/cheby/fmc_adc_100Ms_csr.vhd
View file @ 7cba45b1
...@@ -12,7 +12,6 @@ package fmc_adc_100ms_csr_pkg is ...@@ -12,7 +12,6 @@ package fmc_adc_100ms_csr_pkg is
ctl_fmc_clk_oe : std_logic; ctl_fmc_clk_oe : std_logic;
ctl_offset_dac_clr_n : std_logic; ctl_offset_dac_clr_n : std_logic;
ctl_man_bitslip : std_logic; ctl_man_bitslip : std_logic;
ctl_test_data_en : std_logic;
ctl_trig_led : std_logic; ctl_trig_led : std_logic;
ctl_acq_led : std_logic; ctl_acq_led : std_logic;
ctl_clear_trig_stat : std_logic; ctl_clear_trig_stat : std_logic;
...@@ -117,7 +116,6 @@ architecture syn of fmc_adc_100ms_csr is ...@@ -117,7 +116,6 @@ architecture syn of fmc_adc_100ms_csr is
signal wb_wip : std_logic; signal wb_wip : std_logic;
signal ctl_fmc_clk_oe_reg : std_logic; signal ctl_fmc_clk_oe_reg : std_logic;
signal ctl_offset_dac_clr_n_reg : std_logic; signal ctl_offset_dac_clr_n_reg : std_logic;
signal ctl_test_data_en_reg : std_logic;
signal ctl_trig_led_reg : std_logic; signal ctl_trig_led_reg : std_logic;
signal ctl_acq_led_reg : std_logic; signal ctl_acq_led_reg : std_logic;
signal trig_en_ext_reg : std_logic; signal trig_en_ext_reg : std_logic;
...@@ -198,7 +196,6 @@ begin ...@@ -198,7 +196,6 @@ begin
-- Assign outputs -- Assign outputs
fmc_adc_100ms_csr_o.ctl_fmc_clk_oe <= ctl_fmc_clk_oe_reg; fmc_adc_100ms_csr_o.ctl_fmc_clk_oe <= ctl_fmc_clk_oe_reg;
fmc_adc_100ms_csr_o.ctl_offset_dac_clr_n <= ctl_offset_dac_clr_n_reg; fmc_adc_100ms_csr_o.ctl_offset_dac_clr_n <= ctl_offset_dac_clr_n_reg;
fmc_adc_100ms_csr_o.ctl_test_data_en <= ctl_test_data_en_reg;
fmc_adc_100ms_csr_o.ctl_trig_led <= ctl_trig_led_reg; fmc_adc_100ms_csr_o.ctl_trig_led <= ctl_trig_led_reg;
fmc_adc_100ms_csr_o.ctl_acq_led <= ctl_acq_led_reg; fmc_adc_100ms_csr_o.ctl_acq_led <= ctl_acq_led_reg;
fmc_adc_100ms_csr_o.trig_en_ext <= trig_en_ext_reg; fmc_adc_100ms_csr_o.trig_en_ext <= trig_en_ext_reg;
...@@ -306,7 +303,6 @@ begin ...@@ -306,7 +303,6 @@ begin
fmc_adc_100ms_csr_o.ctl_wr <= '0'; fmc_adc_100ms_csr_o.ctl_wr <= '0';
ctl_fmc_clk_oe_reg <= '0'; ctl_fmc_clk_oe_reg <= '0';
ctl_offset_dac_clr_n_reg <= '0'; ctl_offset_dac_clr_n_reg <= '0';
ctl_test_data_en_reg <= '0';
ctl_trig_led_reg <= '0'; ctl_trig_led_reg <= '0';
ctl_acq_led_reg <= '0'; ctl_acq_led_reg <= '0';
trig_en_ext_reg <= '0'; trig_en_ext_reg <= '0';
...@@ -349,7 +345,6 @@ begin ...@@ -349,7 +345,6 @@ begin
ctl_fmc_clk_oe_reg <= wb_i.dat(2); ctl_fmc_clk_oe_reg <= wb_i.dat(2);
ctl_offset_dac_clr_n_reg <= wb_i.dat(3); ctl_offset_dac_clr_n_reg <= wb_i.dat(3);
fmc_adc_100ms_csr_o.ctl_man_bitslip <= wb_i.dat(4); fmc_adc_100ms_csr_o.ctl_man_bitslip <= wb_i.dat(4);
ctl_test_data_en_reg <= wb_i.dat(5);
ctl_trig_led_reg <= wb_i.dat(6); ctl_trig_led_reg <= wb_i.dat(6);
ctl_acq_led_reg <= wb_i.dat(7); ctl_acq_led_reg <= wb_i.dat(7);
fmc_adc_100ms_csr_o.ctl_clear_trig_stat <= wb_i.dat(8); fmc_adc_100ms_csr_o.ctl_clear_trig_stat <= wb_i.dat(8);
...@@ -476,7 +471,6 @@ begin ...@@ -476,7 +471,6 @@ begin
reg_rdat_int(2) <= ctl_fmc_clk_oe_reg; reg_rdat_int(2) <= ctl_fmc_clk_oe_reg;
reg_rdat_int(3) <= ctl_offset_dac_clr_n_reg; reg_rdat_int(3) <= ctl_offset_dac_clr_n_reg;
reg_rdat_int(4) <= fmc_adc_100ms_csr_i.ctl_man_bitslip; reg_rdat_int(4) <= fmc_adc_100ms_csr_i.ctl_man_bitslip;
reg_rdat_int(5) <= ctl_test_data_en_reg;
reg_rdat_int(6) <= ctl_trig_led_reg; reg_rdat_int(6) <= ctl_trig_led_reg;
reg_rdat_int(7) <= ctl_acq_led_reg; reg_rdat_int(7) <= ctl_acq_led_reg;
reg_rdat_int(8) <= fmc_adc_100ms_csr_i.ctl_clear_trig_stat; reg_rdat_int(8) <= fmc_adc_100ms_csr_i.ctl_clear_trig_stat;
......
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ 7cba45b1
...@@ -315,7 +315,6 @@ architecture rtl of fmc_adc_100Ms_core is ...@@ -315,7 +315,6 @@ architecture rtl of fmc_adc_100Ms_core is
-- RAM address counter -- RAM address counter
signal ram_addr_cnt : unsigned(28 downto 0); signal ram_addr_cnt : unsigned(28 downto 0);
signal test_data_en : std_logic;
signal trig_addr : std_logic_vector(31 downto 0); signal trig_addr : std_logic_vector(31 downto 0);
signal mem_ovr : std_logic; signal mem_ovr : std_logic;
...@@ -517,7 +516,6 @@ begin ...@@ -517,7 +516,6 @@ begin
ctl_reg_wr <= csr_regout.ctl_wr; ctl_reg_wr <= csr_regout.ctl_wr;
fsm_cmd <= csr_regout.ctl_fsm_cmd; fsm_cmd <= csr_regout.ctl_fsm_cmd;
serdes_man_bitslip <= csr_regout.ctl_man_bitslip and ctl_reg_wr; serdes_man_bitslip <= csr_regout.ctl_man_bitslip and ctl_reg_wr;
test_data_en <= csr_regout.ctl_test_data_en;
trig_led_man <= csr_regout.ctl_trig_led; trig_led_man <= csr_regout.ctl_trig_led;
acq_led_man <= csr_regout.ctl_acq_led; acq_led_man <= csr_regout.ctl_acq_led;
trig_storage_clear <= csr_regout.ctl_clear_trig_stat and ctl_reg_wr; trig_storage_clear <= csr_regout.ctl_clear_trig_stat and ctl_reg_wr;
...@@ -1594,11 +1592,7 @@ begin ...@@ -1594,11 +1592,7 @@ begin
wb_ddr_master_o.adr <= "00" & std_logic_vector(ram_addr_cnt) & "0"; wb_ddr_master_o.adr <= "00" & std_logic_vector(ram_addr_cnt) & "0";
wb_ddr_master_o.we <= '1'; wb_ddr_master_o.we <= '1';
wb_ddr_master_o.sel <= X"FF"; wb_ddr_master_o.sel <= X"FF";
wb_ddr_master_o.dat <= wb_ddr_fifo_dout(63 downto 0);
with test_data_en select
wb_ddr_master_o.dat <=
x"00000000" & "000" & std_logic_vector(ram_addr_cnt) when '1',
wb_ddr_fifo_dout(63 downto 0) when others;
-- Store trigger DDR address (byte address) -- Store trigger DDR address (byte address)
p_trig_addr : process (wb_ddr_clk_i) p_trig_addr : process (wb_ddr_clk_i)
......
hdl/testbench/include/fmc_adc_100Ms_csr.v
View file @ 7cba45b1
...@@ -8,8 +8,6 @@ ...@@ -8,8 +8,6 @@
`define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N 'h8 `define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N 'h8
`define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP_OFFSET 4 `define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP_OFFSET 4
`define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP 'h10 `define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP 'h10
`define FMC_ADC_100MS_CSR_CTL_TEST_DATA_EN_OFFSET 5
`define FMC_ADC_100MS_CSR_CTL_TEST_DATA_EN 'h20
`define FMC_ADC_100MS_CSR_CTL_TRIG_LED_OFFSET 6 `define FMC_ADC_100MS_CSR_CTL_TRIG_LED_OFFSET 6
`define FMC_ADC_100MS_CSR_CTL_TRIG_LED 'h40 `define FMC_ADC_100MS_CSR_CTL_TRIG_LED 'h40
`define FMC_ADC_100MS_CSR_CTL_ACQ_LED_OFFSET 7 `define FMC_ADC_100MS_CSR_CTL_ACQ_LED_OFFSET 7
......
software/include/hw/fmc_adc_100Ms_csr.h
View file @ 7cba45b1
...@@ -11,7 +11,6 @@ ...@@ -11,7 +11,6 @@
#define FMC_ADC_100MS_CSR_CTL_FMC_CLK_OE 0x4UL #define FMC_ADC_100MS_CSR_CTL_FMC_CLK_OE 0x4UL
#define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N 0x8UL #define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N 0x8UL
#define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP 0x10UL #define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP 0x10UL
#define FMC_ADC_100MS_CSR_CTL_TEST_DATA_EN 0x20UL
#define FMC_ADC_100MS_CSR_CTL_TRIG_LED 0x40UL #define FMC_ADC_100MS_CSR_CTL_TRIG_LED 0x40UL
#define FMC_ADC_100MS_CSR_CTL_ACQ_LED 0x80UL #define FMC_ADC_100MS_CSR_CTL_ACQ_LED 0x80UL
#define FMC_ADC_100MS_CSR_CTL_CLEAR_TRIG_STAT 0x100UL #define FMC_ADC_100MS_CSR_CTL_CLEAR_TRIG_STAT 0x100UL
......
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