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FMC ADC 100M 14b 4cha - Gateware
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FMC ADC 100M 14b 4cha - Gateware
Commits
7c913fc1
Commit
7c913fc1
authored
Mar 20, 2014
by
Matthieu Cattin
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doc: Update doc to describe new features.
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offset_gain_corr.pdf
documentation/figures/offset_gain_corr.pdf
+0
-0
offset_gain_corr.svg
documentation/figures/offset_gain_corr.svg
+177
-74
trigger_unit.pdf
documentation/figures/trigger_unit.pdf
+0
-0
trigger_unit.svg
documentation/figures/trigger_unit.svg
+45
-10
fmc_adc_100Ms_csr.tex
documentation/manuals/gateware/fmc_adc_100Ms_csr.tex
+165
-21
fmcadc100m14b4cha_gateware_manual.in
...ion/manuals/gateware/fmcadc100m14b4cha_gateware_manual.in
+57
-37
fmc_adc_100Ms_csr.vhd
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
+1
-1
fmc_adc_100Ms_csr.h
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
+1
-1
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documentation/figures/offset_gain_corr.pdf
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...
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documentation/manuals/gateware/fmc_adc_100Ms_csr.tex
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7c913fc1
...
@@ -27,88 +27,112 @@ REG @tab
...
@@ -27,88 +27,112 @@ REG @tab
Number of shots
Number of shots
@item @code
{
0x18
}
@tab
@item @code
{
0x18
}
@tab
REG @tab
REG @tab
@code
{
shots
_
cnt
}
@tab
Remaining shots counter
@item @code
{
0x1c
}
@tab
REG @tab
@code
{
trig
_
pos
}
@tab
@code
{
trig
_
pos
}
@tab
Trigger address register
Trigger address register
@item @code
{
0x1c
}
@tab
@item @code
{
0x20
}
@tab
REG @tab
@code
{
fs
_
freq
}
@tab
Sampling clock frequency
@item @code
{
0x24
}
@tab
REG @tab
REG @tab
@code
{
sr
}
@tab
@code
{
sr
}
@tab
Sample rate
Sample rate
@item @code
{
0x2
0
}
@tab
@item @code
{
0x2
8
}
@tab
REG @tab
REG @tab
@code
{
pre
_
samples
}
@tab
@code
{
pre
_
samples
}
@tab
Pre-trigger samples
Pre-trigger samples
@item @code
{
0x2
4
}
@tab
@item @code
{
0x2
c
}
@tab
REG @tab
REG @tab
@code
{
post
_
samples
}
@tab
@code
{
post
_
samples
}
@tab
Post-trigger samples
Post-trigger samples
@item @code
{
0x
28
}
@tab
@item @code
{
0x
30
}
@tab
REG @tab
REG @tab
@code
{
samples
_
cnt
}
@tab
@code
{
samples
_
cnt
}
@tab
Samples counter
Samples counter
@item @code
{
0x
2c
}
@tab
@item @code
{
0x
34
}
@tab
REG @tab
REG @tab
@code
{
ch1
_
ctl
}
@tab
@code
{
ch1
_
ctl
}
@tab
Channel 1 control register
Channel 1 control register
@item @code
{
0x3
0
}
@tab
@item @code
{
0x3
8
}
@tab
REG @tab
REG @tab
@code
{
ch1
_
sta
}
@tab
@code
{
ch1
_
sta
}
@tab
Channel 1 status register
Channel 1 status register
@item @code
{
0x3
4
}
@tab
@item @code
{
0x3
c
}
@tab
REG @tab
REG @tab
@code
{
ch1
_
gain
}
@tab
@code
{
ch1
_
gain
}
@tab
Channel 1 gain calibration register
Channel 1 gain calibration register
@item @code
{
0x
38
}
@tab
@item @code
{
0x
40
}
@tab
REG @tab
REG @tab
@code
{
ch1
_
offset
}
@tab
@code
{
ch1
_
offset
}
@tab
Channel 1 offset calibration register
Channel 1 offset calibration register
@item @code
{
0x3c
}
@tab
@item @code
{
0x44
}
@tab
REG @tab
@code
{
ch1
_
sat
}
@tab
Channel 1 saturation register
@item @code
{
0x48
}
@tab
REG @tab
REG @tab
@code
{
ch2
_
ctl
}
@tab
@code
{
ch2
_
ctl
}
@tab
Channel 2 control register
Channel 2 control register
@item @code
{
0x4
0
}
@tab
@item @code
{
0x4
c
}
@tab
REG @tab
REG @tab
@code
{
ch2
_
sta
}
@tab
@code
{
ch2
_
sta
}
@tab
Channel 2 status register
Channel 2 status register
@item @code
{
0x
44
}
@tab
@item @code
{
0x
50
}
@tab
REG @tab
REG @tab
@code
{
ch2
_
gain
}
@tab
@code
{
ch2
_
gain
}
@tab
Channel 2 gain calibration register
Channel 2 gain calibration register
@item @code
{
0x
48
}
@tab
@item @code
{
0x
54
}
@tab
REG @tab
REG @tab
@code
{
ch2
_
offset
}
@tab
@code
{
ch2
_
offset
}
@tab
Channel 2 offset calibration register
Channel 2 offset calibration register
@item @code
{
0x4c
}
@tab
@item @code
{
0x58
}
@tab
REG @tab
@code
{
ch2
_
sat
}
@tab
Channel 2 saturation register
@item @code
{
0x5c
}
@tab
REG @tab
REG @tab
@code
{
ch3
_
ctl
}
@tab
@code
{
ch3
_
ctl
}
@tab
Channel 3 control register
Channel 3 control register
@item @code
{
0x
5
0
}
@tab
@item @code
{
0x
6
0
}
@tab
REG @tab
REG @tab
@code
{
ch3
_
sta
}
@tab
@code
{
ch3
_
sta
}
@tab
Channel 3 status register
Channel 3 status register
@item @code
{
0x
5
4
}
@tab
@item @code
{
0x
6
4
}
@tab
REG @tab
REG @tab
@code
{
ch3
_
gain
}
@tab
@code
{
ch3
_
gain
}
@tab
Channel 3 gain calibration register
Channel 3 gain calibration register
@item @code
{
0x
5
8
}
@tab
@item @code
{
0x
6
8
}
@tab
REG @tab
REG @tab
@code
{
ch3
_
offset
}
@tab
@code
{
ch3
_
offset
}
@tab
Channel 3 offset calibration register
Channel 3 offset calibration register
@item @code
{
0x5c
}
@tab
@item @code
{
0x6c
}
@tab
REG @tab
@code
{
ch3
_
sat
}
@tab
Channel 3 saturation register
@item @code
{
0x70
}
@tab
REG @tab
REG @tab
@code
{
ch4
_
ctl
}
@tab
@code
{
ch4
_
ctl
}
@tab
Channel 4 control register
Channel 4 control register
@item @code
{
0x
60
}
@tab
@item @code
{
0x
74
}
@tab
REG @tab
REG @tab
@code
{
ch4
_
sta
}
@tab
@code
{
ch4
_
sta
}
@tab
Channel 4 status register
Channel 4 status register
@item @code
{
0x
64
}
@tab
@item @code
{
0x
78
}
@tab
REG @tab
REG @tab
@code
{
ch4
_
gain
}
@tab
@code
{
ch4
_
gain
}
@tab
Channel 4 gain calibration register
Channel 4 gain calibration register
@item @code
{
0x
68
}
@tab
@item @code
{
0x
7c
}
@tab
REG @tab
REG @tab
@code
{
ch4
_
offset
}
@tab
@code
{
ch4
_
offset
}
@tab
Channel 4 offset calibration register
Channel 4 offset calibration register
@item @code
{
0x80
}
@tab
REG @tab
@code
{
ch4
_
sat
}
@tab
Channel 4 saturation register
@end multitable
@end multitable
@regsection @code
{
ctl
}
- Control register
@regsection @code
{
ctl
}
- Control register
@multitable @columnfractions .10 .10 .15 .10 .55
@multitable @columnfractions .10 .10 .15 .10 .55
...
@@ -227,11 +251,21 @@ Software trigger enable
...
@@ -227,11 +251,21 @@ Software trigger enable
@code
{
INT
_
TRIG
_
SEL
}
@code
{
INT
_
TRIG
_
SEL
}
@tab @code
{
0
}
@tab
@tab @code
{
0
}
@tab
Channel selection for internal trigger
Channel selection for internal trigger
@item @code
{
15...6
}
@item @code
{
6
}
@tab R/W @tab
@code
{
INT
_
TRIG
_
TEST
_
EN
}
@tab @code
{
0
}
@tab
Enable internal trigger test mode
@item @code
{
7
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
0
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@item @code
{
15...8
}
@tab R/W @tab
@code
{
INT
_
TRIG
_
THRES
_
FILT
}
@tab @code
{
0
}
@tab
Internal trigger threshold glitch filter
@item @code
{
31...16
}
@item @code
{
31...16
}
@tab R/W @tab
@tab R/W @tab
@code
{
INT
_
TRIG
_
THRES
}
@code
{
INT
_
TRIG
_
THRES
}
...
@@ -245,7 +279,9 @@ Threshold for internal trigger
...
@@ -245,7 +279,9 @@ Threshold for internal trigger
@item @code
{
hw
_
trig
_
en
}
@tab 0: disable@*1: enable
@item @code
{
hw
_
trig
_
en
}
@tab 0: disable@*1: enable
@item @code
{
sw
_
trig
_
en
}
@tab 0: disable@*1: enable
@item @code
{
sw
_
trig
_
en
}
@tab 0: disable@*1: enable
@item @code
{
int
_
trig
_
sel
}
@tab 00: channel 1@*01: channel 2@*10: channel 3@*11: channel 4
@item @code
{
int
_
trig
_
sel
}
@tab 00: channel 1@*01: channel 2@*10: channel 3@*11: channel 4
@item @code
{
int
_
trig
_
test
_
en
}
@tab Test mode:@* ch1 = Channel 1 input(analogue)@* ch2 = Channel input over threshold (digital)@* ch3 = Channel input over threshold filtered (digital)@* ch4 = Trigger (digital)
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@item @code
{
int
_
trig
_
thres
_
filt
}
@tab Configures the internal trigger threshold glitch filter length.
@item @code
{
int
_
trig
_
thres
}
@tab Treated as binary two's complement and compared to raw ADC data.
@item @code
{
int
_
trig
_
thres
}
@tab Treated as binary two's complement and compared to raw ADC data.
@end multitable
@end multitable
@regsection @code
{
trig
_
dly
}
- Trigger delay
@regsection @code
{
trig
_
dly
}
- Trigger delay
...
@@ -290,6 +326,25 @@ Reserved
...
@@ -290,6 +326,25 @@ Reserved
@item @code
{
nb
}
@tab Number of shots required in multi-shot mode, set to one for single-shot mode.
@item @code
{
nb
}
@tab Number of shots required in multi-shot mode, set to one for single-shot mode.
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@end multitable
@end multitable
@regsection @code
{
shots
_
cnt
}
- Remaining shots counter
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code
{
15...0
}
@tab R/O @tab
@code
{
VAL
}
@tab @code
{
X
}
@tab
Remaining shots counter
@item @code
{
31...16
}
@tab R/W @tab
@code
{
RESERVED
}
@tab @code
{
0
}
@tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code
{
val
}
@tab Counts the number of remaining shots to acquire.
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@end multitable
@regsection @code
{
trig
_
pos
}
- Trigger address register
@regsection @code
{
trig
_
pos
}
- Trigger address register
@multitable @columnfractions .10 .10 .15 .10 .55
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
...
@@ -303,6 +358,19 @@ Trigger address
...
@@ -303,6 +358,19 @@ Trigger address
@headitem Field @tab Description
@headitem Field @tab Description
@item @code
{
trig
_
pos
}
@tab Trigger address in DDR memory.@*Only used in single-shot mode.
@item @code
{
trig
_
pos
}
@tab Trigger address in DDR memory.@*Only used in single-shot mode.
@end multitable
@end multitable
@regsection @code
{
fs
_
freq
}
- Sampling clock frequency
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code
{
31...0
}
@tab R/O @tab
@code
{
FS
_
FREQ
}
@tab @code
{
X
}
@tab
Sampling clock frequency
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code
{
fs
_
freq
}
@tab ADC sampling clock frequency in Hz
@end multitable
@regsection @code
{
sr
}
- Sample rate
@regsection @code
{
sr
}
- Sample rate
@multitable @columnfractions .10 .10 .15 .10 .55
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
...
@@ -431,6 +499,25 @@ Reserved
...
@@ -431,6 +499,25 @@ Reserved
@item @code
{
val
}
@tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@item @code
{
val
}
@tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@end multitable
@end multitable
@regsection @code
{
ch1
_
sat
}
- Channel 1 saturation register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code
{
14...0
}
@tab R/W @tab
@code
{
VAL
}
@tab @code
{
0
}
@tab
Saturation value for channel 1
@item @code
{
31...15
}
@tab R/W @tab
@code
{
RESERVED
}
@tab @code
{
0
}
@tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code
{
val
}
@tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@end multitable
@regsection @code
{
ch2
_
ctl
}
- Channel 2 control register
@regsection @code
{
ch2
_
ctl
}
- Channel 2 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
...
@@ -507,6 +594,25 @@ Reserved
...
@@ -507,6 +594,25 @@ Reserved
@item @code
{
val
}
@tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@item @code
{
val
}
@tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@end multitable
@end multitable
@regsection @code
{
ch2
_
sat
}
- Channel 2 saturation register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code
{
14...0
}
@tab R/W @tab
@code
{
VAL
}
@tab @code
{
0
}
@tab
Saturation value for channel 2
@item @code
{
31...15
}
@tab R/W @tab
@code
{
RESERVED
}
@tab @code
{
0
}
@tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code
{
val
}
@tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@end multitable
@regsection @code
{
ch3
_
ctl
}
- Channel 3 control register
@regsection @code
{
ch3
_
ctl
}
- Channel 3 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
...
@@ -583,6 +689,25 @@ Reserved
...
@@ -583,6 +689,25 @@ Reserved
@item @code
{
val
}
@tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@item @code
{
val
}
@tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@end multitable
@end multitable
@regsection @code
{
ch3
_
sat
}
- Channel 3 saturation register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code
{
14...0
}
@tab R/W @tab
@code
{
VAL
}
@tab @code
{
0
}
@tab
Saturation value for channel 3
@item @code
{
31...15
}
@tab R/W @tab
@code
{
RESERVED
}
@tab @code
{
0
}
@tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code
{
val
}
@tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@end multitable
@regsection @code
{
ch4
_
ctl
}
- Channel 4 control register
@regsection @code
{
ch4
_
ctl
}
- Channel 4 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
...
@@ -659,3 +784,22 @@ Reserved
...
@@ -659,3 +784,22 @@ Reserved
@item @code
{
val
}
@tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@item @code
{
val
}
@tab Offset applied to all data coming from the ADC. The format is binary two's complement.
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@end multitable
@end multitable
@regsection @code
{
ch4
_
sat
}
- Channel 4 saturation register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code
{
14...0
}
@tab R/W @tab
@code
{
VAL
}
@tab @code
{
0
}
@tab
Saturation value for channel 4
@item @code
{
31...15
}
@tab R/W @tab
@code
{
RESERVED
}
@tab @code
{
0
}
@tab
Reserved
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code
{
val
}
@tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@item @code
{
reserved
}
@tab Ignore on read, write with 0's
@end multitable
documentation/manuals/gateware/fmcadc100m14b4cha_gateware_manual.in
View file @
7c913fc1
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hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @
7c913fc1
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created :
Wed Mar 19 16:50:21
2014
-- Created :
Thu Mar 20 11:08:14
2014
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
...
...
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @
7c913fc1
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created :
Wed Mar 19 16:50:21
2014
* Created :
Thu Mar 20 11:08:15
2014
* Standard : ANSI C
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
...
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