Commit 776745de authored by Matthieu Cattin's avatar Matthieu Cattin

hdl: Change ddr-sp6-core module to master branch, add custom variable to select…

hdl: Change ddr-sp6-core module to master branch, add custom variable to select ddr copntrollers (requires hdlmake v2.1).
parent e746eb6d
......@@ -21,7 +21,9 @@ modules = { "local" : ["../rtl",
"../../adc/rtl",
"../../ip_cores/timetag_core/rtl"],
"git" : ["git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::spec_bank3_64b_32b",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::master",
"git://ohwr.org/hdl-core-lib/gn4124-core.git::master"]}
fetchto="../../ip_cores"
ctrls = ["bank3_64b_32b"]
......@@ -21,7 +21,9 @@ modules = { "local" : ["../rtl",
"../../adc/rtl",
"../../ip_cores/timetag_core/rtl"],
"git" : ["git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::svec_bank4_64b_32b_bank5_64b_32b",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::master",
"git://ohwr.org/hdl-core-lib/vme64x-core.git::master"]}
fetchto="../../ip_cores"
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
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