Commit 769d01ee authored by Matthieu Cattin's avatar Matthieu Cattin

syn: Update xise project with sdb meta-info package, resynth.

parent 0b680c53
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......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Mar 5 13:58:38 2013
Mapped Date : Thu Mar 7 12:35:52 2013
Design Summary
--------------
......@@ -23,10 +23,10 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,656 out of 27,288 20%
Number used as logic: 5,168 out of 27,288 18%
Number of Slice LUTs: 5,450 out of 27,288 19%
Number used as logic: 5,169 out of 27,288 18%
Number using O6 output only: 3,262
Number using O5 output only: 280
Number using O5 output only: 281
Number using O5 and O6: 1,626
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
......@@ -36,18 +36,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 486
Number with same-slice register load: 475
Number used exclusively as route-thrus: 279
Number with same-slice register load: 268
Number with same-slice carry load: 11
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,412 out of 6,822 35%
Number of occupied Slices: 2,618 out of 6,822 38%
Nummber of MUXCYs used: 1,424 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,602
Number with an unused Flip Flop: 1,775 out of 7,602 23%
Number with an unused LUT: 1,946 out of 7,602 25%
Number of fully used LUT-FF pairs: 3,881 out of 7,602 51%
Number of LUT Flip Flop pairs used: 7,968
Number with an unused Flip Flop: 1,934 out of 7,968 24%
Number with an unused LUT: 2,518 out of 7,968 31%
Number of fully used LUT-FF pairs: 3,516 out of 7,968 44%
Number of unique control sets: 260
Number of slice register sites lost
to control set restrictions: 673 out of 54,576 1%
......@@ -102,9 +102,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 418 MB
Total REAL time to MAP completion: 4 mins 46 secs
Total CPU time to MAP completion (all processors): 4 mins 46 secs
Peak Memory Usage: 417 MB
Total REAL time to MAP completion: 4 mins 50 secs
Total CPU time to MAP completion (all processors): 4 mins 53 secs
Table of Contents
-----------------
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