sim: introduce new svec_ref_design testbench

71387ac4 · Dimitris Lampridis · d1059605 · 71387ac4 · 71387ac4 · 71387ac4
Commit 71387ac4 authored Nov 27, 2018 by Dimitris Lampridis
6 changed files
--- a/hdl/testbench/svec_ref_design/.gitignore
+++ b/hdl/testbench/svec_ref_design/.gitignore
+Makefile
+work/
+transcript
+vsim.wlf
+NullFile
+modelsim.ini
--- a/hdl/testbench/svec_ref_design/Manifest.py
+++ b/hdl/testbench/svec_ref_design/Manifest.py
+board      = "svec"
+sim_tool   = "modelsim"
+top_module = "main"
+action     = "simulation"
+target     = "xilinx"
+syn_device = "xc6slx150t"
+
+vcom_opt = "-93 -mixedsvvh"
+
+fetchto = "../../ip_cores"
+
+include_dirs = [
+    "../include",
+    fetchto + "/general-cores/sim/",
+    fetchto + "/general-cores/modules/wishbone/wb_spi/",
+    fetchto + "/vme64x-core/hdl/sim/vme64x_bfm/",
+]
+
+files = [
+    "main.sv",
+    "synthesis_descriptor.vhd",
+]
+
+modules = {
+    "local" : [
+        "../../top/svec_ref_design",
+    ],
+    "git" : [
+        "git://ohwr.org/hdl-core-lib/general-cores.git",
+        "git://ohwr.org/hdl-core-lib/wr-cores.git",
+        "git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
+        "git://ohwr.org/hdl-core-lib/vme64x-core.git",
+    ],
+}
+
+ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
--- a/hdl/testbench/svec_ref_design/main.sv
+++ b/hdl/testbench/svec_ref_design/main.sv
--- a/hdl/testbench/svec_ref_design/run.do
+++ b/hdl/testbench/svec_ref_design/run.do
+vsim -quiet -t 10fs -L unisim work.main -novopt
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+
+radix -hexadecimal
+
+log -r /*
+
+run -all
+
+wave zoomfull
--- a/hdl/testbench/svec_ref_design/run_ci.do
+++ b/hdl/testbench/svec_ref_design/run_ci.do
+vsim -quiet -t 10fs -L unisim work.main
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+
+run -all
--- a/hdl/testbench/svec_ref_design/synthesis_descriptor.vhd
+++ b/hdl/testbench/svec_ref_design/synthesis_descriptor.vhd
+--------------------------------------------------------------------------------
+-- SDB meta information for svec_ref_fmc_adc_100Ms_wr.xise.
+--
+-- This file was automatically generated by ../../ip_cores/general-cores/tools/sdb_desc_gen.tcl on:
+-- Thursday, November 15 2018
+--
+-- ../../ip_cores/general-cores/tools/sdb_desc_gen.tcl is part of OHWR general-cores:
+-- https://www.ohwr.org/projects/general-cores/wiki
+--
+-- For more information on SDB meta information, see also:
+-- https://www.ohwr.org/projects/sdb/wiki
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wishbone_pkg.all;
+
+package synthesis_descriptor is
+
+  constant c_sdb_synthesis_info : t_sdb_synthesis := (
+    syn_module_name  => "svec_ref_fmc_adc",
+    syn_commit_id    => "f98f833b0a46c659dd2c68d6bfeb6d9*",
+    syn_tool_name    => "ISE     ",
+    syn_tool_version => x"00000147",
+    syn_date         => x"20181115",
+    syn_username     => "Dimitris Lampri");
+
+  constant c_sdb_repo_url : t_sdb_repo_url := (
+    repo_url => "ssh://git@gitlab.cern.ch:7999/dlamprid/fmc-adc-100m14b4cha-gw.g");
+
+end package synthesis_descriptor;