Skip to content

F
FMC ADC 100M 14b 4cha - Gateware
Commit 67d75c4d authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

[hdl] remove use of component declarations in fmc_adc_100Ms_core 

Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
parent 33101cf1
Hide whitespace changes
Inline Side-by-side
Showing with 1 addition and 17 deletions
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ 67d75c4d
......@@ -115,22 +115,6 @@ end fmc_adc_100Ms_core;
architecture rtl of fmc_adc_100Ms_core is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component offset_gain_s
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
offset_i : in std_logic_vector(15 downto 0); --! Signed offset input (two's complement)
gain_i : in std_logic_vector(15 downto 0); --! Unsigned gain input
sat_i : in std_logic_vector(14 downto 0); --! Unsigned saturation value input
data_i : in std_logic_vector(15 downto 0); --! Signed data input (two's complement)
data_o : out std_logic_vector(15 downto 0) --! Signed data output (two's complement)
);
end component offset_gain_s;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
......@@ -724,7 +708,7 @@ begin
-- Offset and gain calibration
------------------------------------------------------------------------------
l_offset_gain_calibr : for I in 0 to 3 generate
cmp_offset_gain_calibr : offset_gain_s
cmp_offset_gain_calibr : entity work.offset_gain_s
port map(
rst_n_i => fs_rst_n,
clk_i => fs_clk,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment