Commit 523e8a0a authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl/sim: sanitized and updated SPEC simulation. Tested with ModelSIM 10.2a,…

hdl/sim: sanitized and updated SPEC simulation. Tested with ModelSIM 10.2a, works. Did not verify simulation results
parent d9169fd0
hdl/ip_cores/.lso hdl/ip_cores/.lso
hdl/ip_cores/_xmsgs hdl/ip_cores/_xmsgs
hdl/*/sim/transcript
hdl/*/sim/vsim.wlf
hdl/*/sim/Makefile
hdl/*/sim/modelsim.ini hdl/*/sim/modelsim.ini
hdl/*/sim/work/ hdl/*/sim/work/
hdl/*/sim/fifo_generator_v6_1/ hdl/*/sim/fifo_generator_v6_1/
......
This diff is collapsed.
sim_tool="modelsim"
top_module="main"
target = "xilinx" target = "xilinx"
action = "simulation" action = "simulation"
syn_device = "xc6slx45t"
ctrls = ["bank3_64b_32b" ]
files = ["testbench/gn412x_bfm.vhd", files = ["testbench/gn412x_bfm.vhd",
"testbench/cmd_router.vhd", "testbench/cmd_router.vhd",
...@@ -20,8 +25,8 @@ modules = { "local" : ["../rtl", ...@@ -20,8 +25,8 @@ modules = { "local" : ["../rtl",
"../../ip_cores/timetag_core/rtl", "../../ip_cores/timetag_core/rtl",
"testbench", "testbench",
"sim_models/2048Mb_ddr3"], "sim_models/2048Mb_ddr3"],
"git" : ["git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master", "git" : ["git://ohwr.org/hdl-core-lib/general-cores.git@@c26ee857158e4a65fd9d2add8b63fcb6fb4691ea",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::spec_bank3_64b_32b", "git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git@@e4d6755cc9c9c5cb005ce12eb82b12552922b882",
"git://ohwr.org/hdl-core-lib/gn4124-core.git::master"]} "git://ohwr.org/hdl-core-lib/gn4124-core.git@@e0dcb3f9a3e6804f64c544743bdf46b5fcbbefab"]}
fetchto="../../ip_cores" fetchto="../../ip_cores"
~/projects/hdl-make/hdlmake
\ No newline at end of file
...@@ -559,7 +559,8 @@ ...@@ -559,7 +559,8 @@
parameter TWLO = 9000; // tWLO ps Write levelization output delay parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin `else
`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
......
vsim -novopt -t 1ps tb_spec vsim -novopt -t 1ps tb_spec
log -r /* log -r /*
##do wave_serdes.do do wave.do
##do wave_wb_buses.do do wave_reset.do
##do wave_datapath.do do wave_serdes.do
##do wave_multishot.do do wave_wb_buses.do
##do wave_onewire.do do wave_datapath.do
##do wave_adc_core.do do wave_multishot.do
##do wave_gnum.do do wave_onewire.do
##do wave_end_acq_irq.do do wave_adc_core.do
##do wave_ddr_wb.do do wave_gnum.do
do wave_trig_tag.do do wave_end_acq_irq.do
do wave_ddr_wb.do
view wave view wave
view transcript view transcript
......
...@@ -12,11 +12,11 @@ add wave -noupdate /tb_spec/adc_outa_p_i ...@@ -12,11 +12,11 @@ add wave -noupdate /tb_spec/adc_outa_p_i
add wave -noupdate /tb_spec/adc_outb_n_i add wave -noupdate /tb_spec/adc_outb_n_i
add wave -noupdate /tb_spec/adc_outb_p_i add wave -noupdate /tb_spec/adc_outb_p_i
add wave -noupdate -divider serdes add wave -noupdate -divider serdes
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/bitslip_sreg add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/bitslip_sreg
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_bitslip add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_bitslip
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_synced add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_synced
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_clk add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_clk
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/fs_clk add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {510000 ps} 0} WaveRestoreCursors {{Cursor 1} {510000 ps} 0}
configure wave -namecolwidth 464 configure wave -namecolwidth 464
......
This diff is collapsed.
...@@ -3,63 +3,62 @@ quietly WaveActivateNextPane {} 0 ...@@ -3,63 +3,62 @@ quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {Wishbone CSR interface} add wave -noupdate -divider {Wishbone CSR interface}
add wave -noupdate /tb_spec/U1/sys_clk_125 add wave -noupdate /tb_spec/U1/sys_clk_125
add wave -noupdate -divider trigger add wave -noupdate -divider trigger
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sw_trig_en add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig_en
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sw_trig add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_d add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_d
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_align add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_align
add wave -noupdate -divider {acq fsm} add wave -noupdate -divider {acq fsm}
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/post_trig_done add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/post_trig_done
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_cnt add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/shots_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_value add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/shots_value
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_decr add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/shots_decr
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_done add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/shots_done
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_fsm_current_state add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
add wave -noupdate -divider datapath add wave -noupdate -divider datapath
add wave -noupdate -radix hexadecimal /tb_spec/ADC_DATA add wave -noupdate -radix hexadecimal /tb_spec/ADC_DATA
add wave -noupdate /tb_spec/U1/adc_dco_n_i add wave -noupdate /tb_spec/U1/adc0_dco_n_i
add wave -noupdate /tb_spec/U1/adc_dco_p_i add wave -noupdate /tb_spec/U1/adc0_dco_p_i
add wave -noupdate /tb_spec/U1/adc_fr_p_i add wave -noupdate /tb_spec/U1/adc0_fr_p_i
add wave -noupdate /tb_spec/U1/adc_outa_p_i(0) add wave -noupdate /tb_spec/U1/adc0_outa_p_i(0)
add wave -noupdate /tb_spec/U1/adc_outb_p_i(0) add wave -noupdate /tb_spec/U1/adc0_outb_p_i(0)
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_fr add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_out_fr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_data add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_out_data
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/locked_out add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/locked_out
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_clk add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_rst_n add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_rst_n
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_synced add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_synced
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_cnt add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/decim_cnt
add wave -noupdate -radix decimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_factor add wave -noupdate -radix decimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/decim_factor
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_en add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/decim_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_wr add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_din add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_din
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_full add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_full
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dreq add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dout add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_dout(48)
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dout(48) add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_empty
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_empty add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_rd
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_rd add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_valid add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_out_data
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_data add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr_en
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr_en add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_din
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_din add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_full
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_full add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dreq
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dreq add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_rd
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_rd add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dout add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_empty
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_empty add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_valid
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_valid add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ram_addr_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/ram_addr_cnt
add wave -noupdate -divider {adc to ddr WB} add wave -noupdate -divider {adc to ddr WB}
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_ack_i add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_ack_i
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_clk_i add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_clk_i
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_dat_o add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_dat_o
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stb_o add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_stb_o
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_we_o add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_adr_o add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_adr_o
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stall_i add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_stall_i
add wave -noupdate -divider {ddr controller} add wave -noupdate -divider {ddr controller}
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/status_o(0) add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/status_o(0)
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/wb0_clk_i add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/wb0_clk_i
......
This diff is collapsed.
This diff is collapsed.
onerror {resume} onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_ack add wave -noupdate -radix hexadecimal /tb_spec/u1/cnx_master_out
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_adr add wave -noupdate -radix hexadecimal /tb_spec/u1/cnx_master_in
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_cyc
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_sel
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_stall
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_stb
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_we
add wave -noupdate -divider {Wishbone CSR interface} add wave -noupdate -divider {Wishbone CSR interface}
add wave -noupdate /tb_spec/u1/sys_clk_125 add wave -noupdate /tb_spec/u1/sys_clk_125
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_adr add wave -noupdate -radix hexadecimal /tb_spec/u1/cnx_slave_out
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_dat_o add wave -noupdate -radix hexadecimal /tb_spec/u1/cnx_slave_in
add wave -noupdate /tb_spec/u1/wb_dat_i
add wave -noupdate /tb_spec/u1/wb_stb
add wave -noupdate /tb_spec/u1/wb_we
add wave -noupdate /tb_spec/u1/wb_sel
add wave -noupdate /tb_spec/u1/wb_cyc(10)
add wave -noupdate /tb_spec/u1/wb_stall(10)
add wave -noupdate /tb_spec/u1/wb_ack(10)
add wave -noupdate -divider onewire add wave -noupdate -divider onewire
add wave -noupdate -radix unsigned -subitemconfig {{/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[7]} {-radix unsigned} {/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[6]} {-radix unsigned} {/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[5]} {-radix unsigned} {/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[4]} {-radix unsigned} {/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[3]} {-radix unsigned} {/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[2]} {-radix unsigned} {/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[1]} {-radix unsigned} {/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[0]} {-radix unsigned}} /tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst add wave -noupdate /tb_spec/u1/adc0_one_wire_b
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/cnt add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_onewire/owr_pwren_o(0)
add wave -noupdate /tb_spec/u1/one_wire_b add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_onewire/owr_en_o(0)
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/owr_pwren_o(0) add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_onewire/owr_i(0)
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/owr_en_o(0) add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_onewire/clk_sys_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/owr_i(0) add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_onewire/rst_n_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/clk_sys_i add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_onewire/slave_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/rst_n_i add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_onewire/slave_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_cyc_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_sel_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_stb_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_we_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_adr_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_ack_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_int_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/bus_wen
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/bus_ren
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/rst
add wave -noupdate /tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/pls
add wave -noupdate -divider l2p add wave -noupdate -divider l2p
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt
......
...@@ -4,7 +4,6 @@ add wave -noupdate /tb_spec/u1/sys_clk_in ...@@ -4,7 +4,6 @@ add wave -noupdate /tb_spec/u1/sys_clk_in
add wave -noupdate /tb_spec/u1/sys_clk_125 add wave -noupdate /tb_spec/u1/sys_clk_125
add wave -noupdate /tb_spec/u1/sys_clk_250 add wave -noupdate /tb_spec/u1/sys_clk_250
add wave -noupdate /tb_spec/u1/sys_clk_pll_locked add wave -noupdate /tb_spec/u1/sys_clk_pll_locked
add wave -noupdate /tb_spec/u1/sys_rst
add wave -noupdate /tb_spec/u1/sys_rst_n add wave -noupdate /tb_spec/u1/sys_rst_n
add wave -noupdate /tb_spec/u1/l_rst_n add wave -noupdate /tb_spec/u1/l_rst_n
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
......
...@@ -12,15 +12,15 @@ add wave -noupdate /tb_spec/adc_outb_p_i(2) ...@@ -12,15 +12,15 @@ add wave -noupdate /tb_spec/adc_outb_p_i(2)
add wave -noupdate /tb_spec/adc_outa_p_i add wave -noupdate /tb_spec/adc_outa_p_i
add wave -noupdate /tb_spec/adc_outb_p_i add wave -noupdate /tb_spec/adc_outb_p_i
add wave -noupdate -divider serdes add wave -noupdate -divider serdes
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_in_p add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_in_p
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_clk add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_clk
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/fs_clk add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_out_raw add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_out_raw
add wave -noupdate -radix binary /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_out_fr add wave -noupdate -radix binary /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_out_fr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_out_data add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_out_data
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/bitslip_sreg add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/bitslip_sreg
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_bitslip add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_bitslip
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_synced add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_synced
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {760625 ps} 0} WaveRestoreCursors {{Cursor 1} {760625 ps} 0}
configure wave -namecolwidth 366 configure wave -namecolwidth 366
......
...@@ -49,53 +49,12 @@ add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_ddr_we ...@@ -49,53 +49,12 @@ add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_ddr_we
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_ddr_ack add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_ddr_ack
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_ddr_stall add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_ddr_stall
add wave -noupdate -divider {Wishbone CSR master} add wave -noupdate -divider {Wishbone CSR master}
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_ack add wave -noupdate /tb_spec/u1/cnx_master_out
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_adr add wave -noupdate /tb_spec/u1/cnx_master_in
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_cyc
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_sel
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_stall
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_stb
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_we
add wave -noupdate -divider {Wishbone CSR slaves} add wave -noupdate -divider {Wishbone CSR slaves}
add wave -noupdate -radix hexadecimal /tb_spec/u1/sys_clk_125 add wave -noupdate -radix hexadecimal /tb_spec/u1/sys_clk_125
add wave -noupdate /tb_spec/u1/wb_cyc(9) add wave -noupdate /tb_spec/u1/cnx_slave_out
add wave -noupdate /tb_spec/u1/wb_cyc(8) add wave -noupdate /tb_spec/u1/cnx_slave_in
add wave -noupdate /tb_spec/u1/wb_cyc(7)
add wave -noupdate /tb_spec/u1/wb_cyc(6)
add wave -noupdate /tb_spec/u1/wb_cyc(5)
add wave -noupdate /tb_spec/u1/wb_cyc(4)
add wave -noupdate /tb_spec/u1/wb_cyc(3)
add wave -noupdate /tb_spec/u1/wb_cyc(2)
add wave -noupdate /tb_spec/u1/wb_cyc(1)
add wave -noupdate /tb_spec/u1/wb_cyc(0)
add wave -noupdate /tb_spec/u1/wb_ack(9)
add wave -noupdate /tb_spec/u1/wb_ack(8)
add wave -noupdate /tb_spec/u1/wb_ack(7)
add wave -noupdate /tb_spec/u1/wb_ack(6)
add wave -noupdate /tb_spec/u1/wb_ack(5)
add wave -noupdate /tb_spec/u1/wb_ack(4)
add wave -noupdate /tb_spec/u1/wb_ack(3)
add wave -noupdate /tb_spec/u1/wb_ack(2)
add wave -noupdate /tb_spec/u1/wb_ack(1)
add wave -noupdate /tb_spec/u1/wb_ack(0)
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_adr
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_stb
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_we
add wave -noupdate -radix hexadecimal -subitemconfig {/tb_spec/u1/wb_sel(3) {-radix hexadecimal} /tb_spec/u1/wb_sel(2) {-radix hexadecimal} /tb_spec/u1/wb_sel(1) {-radix hexadecimal} /tb_spec/u1/wb_sel(0) {-radix hexadecimal}} /tb_spec/u1/wb_sel
add wave -noupdate /tb_spec/u1/wb_stall(9)
add wave -noupdate /tb_spec/u1/wb_stall(8)
add wave -noupdate /tb_spec/u1/wb_stall(7)
add wave -noupdate /tb_spec/u1/wb_stall(6)
add wave -noupdate /tb_spec/u1/wb_stall(5)
add wave -noupdate /tb_spec/u1/wb_stall(4)
add wave -noupdate /tb_spec/u1/wb_stall(3)
add wave -noupdate /tb_spec/u1/wb_stall(2)
add wave -noupdate /tb_spec/u1/wb_stall(1)
add wave -noupdate /tb_spec/u1/wb_stall(0)
add wave -noupdate -divider IOs add wave -noupdate -divider IOs
add wave -noupdate /tb_spec/led_red add wave -noupdate /tb_spec/led_red
add wave -noupdate /tb_spec/led_green add wave -noupdate /tb_spec/led_green
...@@ -109,8 +68,12 @@ add wave -noupdate /tb_spec/spi_cs_dac2_n_o ...@@ -109,8 +68,12 @@ add wave -noupdate /tb_spec/spi_cs_dac2_n_o
add wave -noupdate /tb_spec/spi_cs_dac3_n_o add wave -noupdate /tb_spec/spi_cs_dac3_n_o
add wave -noupdate /tb_spec/spi_cs_dac4_n_o add wave -noupdate /tb_spec/spi_cs_dac4_n_o
add wave -noupdate -divider {FMC I2C} add wave -noupdate -divider {FMC I2C}
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_i2c/wb_dat_i add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/scl_pad_i
add wave -noupdate /tb_spec/u1/cmp_fmc_i2c/wb_adr_i add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/scl_pad_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/scl_padoen_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/sda_pad_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/sda_pad_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/sda_padoen_o
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {13971949 ps} 0} WaveRestoreCursors {{Cursor 1} {13971949 ps} 0}
configure wave -namecolwidth 464 configure wave -namecolwidth 464
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment