sim: simulation modif for gnum.

Tying to find the PC hang bug.

sim: simulation modif for gnum.
Tying to find the PC hang bug.
4d567730 · Matthieu Cattin · 555b7a24 · 4d567730 · 4d567730 · 4d567730
Commit 4d567730 authored Jan 25, 2013 by Matthieu Cattin
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Showing with 15 additions and 15 deletions

cmd0.vec hdl/spec/sim/cmd0.vec +12 -12

ddr3_parameters.vh hdl/spec/sim/sim_models/2048Mb_ddr3/ddr3_parameters.vh +1 -1

spec.do hdl/spec/sim/spec.do +2 -2

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--- a/hdl/spec/sim/cmd0.vec
+++ b/hdl/spec/sim/cmd0.vec
@@ -282,11 +282,11 @@ wr FF00000000001010 F 00000000
 -- DMA length
 wr FF00000000001014 F 00001000
 -- Next item address (lsb)
-wr FF00000000001018 F 00000000
+wr FF00000000001018 F 20000000
 -- Next item address (msb)
 wr FF0000000000101C F 00000000
 -- DMA attributes (from carrier to host, last item)
-wr FF00000000001020 F 00000000
+wr FF00000000001020 F 00000001
 -- Start DMA
 wr FF00000000001000 F 00000001

@@ -295,32 +295,32 @@ wait %d3000
 ---------------------------------------------

 -- start acquisition
-wr FF00000000001900 F 00000001
+--wr FF00000000001900 F 00000001

 wait   %d500
 -- sw trigger
-wr FF00000000001910 F FFFFFFFF
+--wr FF00000000001910 F FFFFFFFF

 wait %d400

 -- DMA
 ------------------------------
 -- Carrier start address
-wr FF00000000001008 F 00000000
+--wr FF00000000001008 F 00000000
 -- Host start address (lsb)
-wr FF0000000000100C F 40000000
+--wr FF0000000000100C F 40000000
 -- Host start address (msb)
-wr FF00000000001010 F 00000000
+--wr FF00000000001010 F 00000000
 -- DMA length
-wr FF00000000001014 F 00000200
+--wr FF00000000001014 F 00000200
 -- Next item address (lsb)
-wr FF00000000001018 F 20000000
+--wr FF00000000001018 F 20000000
 -- Next item address (msb)
-wr FF0000000000101C F 00000000
+--wr FF0000000000101C F 00000000
 -- DMA attributes (from carrier to host, last item)
-wr FF00000000001020 F 00000000
+--wr FF00000000001020 F 00000000
 -- Start DMA
-wr FF00000000001000 F 00000001
+--wr FF00000000001000 F 00000001

 wait %d1000


--- a/hdl/spec/sim/sim_models/2048Mb_ddr3/ddr3_parameters.vh
+++ b/hdl/spec/sim/sim_models/2048Mb_ddr3/ddr3_parameters.vh
@@ -820,7 +820,7 @@
    parameter RZQ              =     240; // termination resistance
    parameter PRE_DEF_PAT      =   8'hAA; // value returned during mpr pre-defined pattern readout
    parameter STOP_ON_ERROR    =       1; // If set to 1, the model will halt on command sequence/major errors
-    parameter DEBUG            =       1; // Turn on Debug messages
+    parameter DEBUG            =       0; // Turn on Debug messages
    parameter BUS_DELAY        =       0; // delay in nanoseconds
    parameter RANDOM_OUT_DELAY =       0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
    parameter RANDOM_SEED    = 711689044; //seed value for random generator.

--- a/hdl/spec/sim/spec.do
+++ b/hdl/spec/sim/spec.do
@@ -6,9 +6,9 @@ log -r /*
 ##do wave_multishot.do
 ##do wave_onewire.do
 ##do wave_adc_core.do
-##do wave_gnum.do
+do wave_gnum.do
 ##do wave_end_acq_irq.do
-do wave_ddr_wb.do
+##do wave_ddr_wb.do

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