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FMC ADC 100M 14b 4cha - Gateware
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FMC ADC 100M 14b 4cha - Gateware
Commits
426788b5
Commit
426788b5
authored
Apr 08, 2016
by
Dimitris Lampridis
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hdl/sim: sanitized and updated SVEC simulation. Tested with ModelSIM 10.2a, works.
parent
2e05f2a2
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6 changed files
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20 additions
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1549 deletions
+20
-1549
.gitignore
.gitignore
+5
-5
ddr3_parameters.vh
hdl/svec/sim/2048Mb_ddr3/ddr3_parameters.vh
+2
-1
Makefile
hdl/svec/sim/testbench/Makefile
+0
-1537
Manifest.py
hdl/svec/sim/testbench/Manifest.py
+6
-2
main.sv
hdl/svec/sim/testbench/main.sv
+3
-1
svec.do
hdl/svec/sim/testbench/svec.do
+4
-3
No files found.
.gitignore
View file @
426788b5
hdl/ip_cores/.lso
hdl/ip_cores/_xmsgs
hdl/*/sim/transcript
hdl/*/sim/vsim.wlf
hdl/*/sim/Makefile
hdl/*/sim/modelsim.ini
hdl/*/sim/work/
hdl/*/sim/
*/
transcript
hdl/*/sim/
*/
vsim.wlf
hdl/*/sim/
*/
Makefile
hdl/*/sim/
*/
modelsim.ini
hdl/*/sim/
*/
work/
hdl/*/testbench/top/transcript
hdl/*/testbench/top/vsim.wlf
hdl/*/testbench/top/Makefile
...
...
hdl/svec/sim/2048Mb_ddr3/ddr3_parameters.vh
View file @
426788b5
...
...
@@ -559,7 +559,8 @@
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
`else
`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
...
...
hdl/svec/sim/testbench/Makefile
deleted
100644 → 0
View file @
2e05f2a2
This diff is collapsed.
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hdl/svec/sim/testbench/Manifest.py
View file @
426788b5
sim_tool
=
"modelsim"
top_module
=
"main"
action
=
"simulation"
target
=
"xilinx"
vlog_opt
=
"+incdir+../vme64x_bfm +incdir+../2048Mb_ddr3"
syn_device
=
"xc6slx150t"
include_dirs
=
[
"../vme64x_bfm"
,
"../2048Mb_ddr3"
,
"../../../ip_cores/general-cores/sim"
]
files
=
[
"main.sv"
,
"../../../ip_cores/adc_sync_fifo.vhd"
,
...
...
@@ -21,3 +23,5 @@ modules = { "local" : [ "../../rtl",
"git://ohwr.org/hdl-core-lib/vme64x-core.git::master"
]}
fetchto
=
"../../../ip_cores"
ctrls
=
[
"bank4_64b_32b"
,
"bank5_64b_32b"
]
hdl/svec/sim/testbench/main.sv
View file @
426788b5
...
...
@@ -117,7 +117,9 @@ module main;
int
i
,
result
;
CBusAccessor_VME64x
acc
=
new
(
VME
.
master
)
;
CBusAccessor_VME64x
acc
;
acc
=
new
(
VME
.
master
)
;
#
20u
s
;
...
...
hdl/svec/sim/testbench/svec.do
View file @
426788b5
vsim -novopt -t 1ps main
log -r /*
#
log -r /*
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
#view wave
#view transcript
#do wave_interrupt.do
do wave_ddr.do
do wave_interrupt.do
#do wave_ddr.do
#do wave.do
radix -hexadecimal
run 50 us
...
...
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