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FMC ADC 100M 14b 4cha - Gateware
Commit 30b96948 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: recalibrate trigger delays using WR 

Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
parent 10cf6af5
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Showing with 6 additions and 6 deletions
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ 30b96948
......@@ -43,13 +43,13 @@ entity fmc_adc_mezzanine is
-- Only used on Xilinx Spartan6 FPGAs
g_SPARTAN6_USE_PLL : boolean := TRUE;
-- External trigger delay calibration value
g_TRIG_DELAY_EXT : natural := 7;
g_TRIG_DELAY_EXT : natural := 8;
-- Software and time trigger delay calibration value
g_TRIG_DELAY_SW : natural := 9;
g_TRIG_DELAY_SW : natural := 12;
-- Value to be subtracted from trigger tag coarse counter.
-- This is useful if you know that the system introduces
-- some systematic delay wrt the actual trigger time
g_TAG_ADJUST : natural := 24;
g_TAG_ADJUST : natural := 27;
-- FMC-ADC identification number
g_FMC_ADC_NR : natural := 0;
-- WB interface configuration
......
hdl/rtl/fmc_adc_mezzanine_pkg.vhd
View file @ 30b96948
......@@ -48,13 +48,13 @@ package fmc_adc_mezzanine_pkg is
-- Only used on Xilinx Spartan6 FPGAs
g_SPARTAN6_USE_PLL : boolean := TRUE;
-- External trigger delay calibration value
g_TRIG_DELAY_EXT : natural := 7;
g_TRIG_DELAY_EXT : natural := 8;
-- Software and time trigger delay calibration value
g_TRIG_DELAY_SW : natural := 9;
g_TRIG_DELAY_SW : natural := 12;
-- Value to be subtracted from trigger tag coarse counter.
-- This is useful if you know that the system introduces
-- some systematic delay wrt the actual trigger time
g_TAG_ADJUST : natural := 24;
g_TAG_ADJUST : natural := 27;
-- FMC-ADC identification number
g_FMC_ADC_NR : natural := 0;
-- WB interface configuration
......
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