hdl: Fix "unused" field width of the reset register.

2f858137 · Matthieu Cattin · f9628bce · 2f858137 · 2f858137 · 2f858137
Commit 2f858137 authored Aug 15, 2013 by Matthieu Cattin
6 changed files
--- a/documentation/manuals/firmware/spec/carrier_csr.tex
+++ b/documentation/manuals/firmware/spec/carrier_csr.tex
@@ -120,7 +120,7 @@ Controls software reset of the mezzanine including the ddr interface and the tim
 @code{FMC0_N}
 @tab @code{0} @tab 
 State of the reset line
-@item @code{20...1}
+@item @code{31...1}
 @tab R/W @tab
 @code{RESERVED}
 @tab @code{0} @tab 

--- a/hdl/spec/rtl/carrier_csr.vhd
+++ b/hdl/spec/rtl/carrier_csr.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ../rtl/carrier_csr.vhd
 -- Author         : auto-generated by wbgen2 from carrier_csr.wb
-- Created        : Fri Jul 26 16:52:08 2013
+-- Created        : Thu Aug  8 14:54:22 2013
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
@@ -54,7 +54,7 @@ entity carrier_csr is
 -- Port for BIT field: 'State of the reset line' in reg: 'Reset Register'
    carrier_csr_rst_fmc0_n_o                 : out    std_logic;
 -- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register'
-    carrier_csr_rst_reserved_o               : out    std_logic_vector(19 downto 0)
+    carrier_csr_rst_reserved_o               : out    std_logic_vector(30 downto 0)
  );
 end carrier_csr;

@@ -65,7 +65,7 @@ signal carrier_csr_ctrl_led_red_int             : std_logic      ;
 signal carrier_csr_ctrl_dac_clr_n_int           : std_logic      ;
 signal carrier_csr_ctrl_reserved_int            : std_logic_vector(28 downto 0);
 signal carrier_csr_rst_fmc0_n_int               : std_logic      ;
-signal carrier_csr_rst_reserved_int             : std_logic_vector(19 downto 0);
+signal carrier_csr_rst_reserved_int             : std_logic_vector(30 downto 0);
 signal ack_sreg                                 : std_logic_vector(9 downto 0);
 signal rddata_reg                               : std_logic_vector(31 downto 0);
 signal wrdata_reg                               : std_logic_vector(31 downto 0);
@@ -98,7 +98,7 @@ begin
      carrier_csr_ctrl_dac_clr_n_int <= '0';
      carrier_csr_ctrl_reserved_int <= "00000000000000000000000000000";
      carrier_csr_rst_fmc0_n_int <= '0';
-      carrier_csr_rst_reserved_int <= "00000000000000000000";
+      carrier_csr_rst_reserved_int <= "0000000000000000000000000000000";
    elsif rising_edge(clk_sys_i) then
 -- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
@@ -145,21 +145,10 @@ begin
          when "11" => 
            if (wb_we_i = '1') then
              carrier_csr_rst_fmc0_n_int <= wrdata_reg(0);
-              carrier_csr_rst_reserved_int <= wrdata_reg(20 downto 1);
+              carrier_csr_rst_reserved_int <= wrdata_reg(31 downto 1);
            end if;
            rddata_reg(0) <= carrier_csr_rst_fmc0_n_int;
-            rddata_reg(20 downto 1) <= carrier_csr_rst_reserved_int;
-            rddata_reg(21) <= 'X';
-            rddata_reg(22) <= 'X';
-            rddata_reg(23) <= 'X';
-            rddata_reg(24) <= 'X';
-            rddata_reg(25) <= 'X';
-            rddata_reg(26) <= 'X';
-            rddata_reg(27) <= 'X';
-            rddata_reg(28) <= 'X';
-            rddata_reg(29) <= 'X';
-            rddata_reg(30) <= 'X';
-            rddata_reg(31) <= 'X';
+            rddata_reg(31 downto 1) <= carrier_csr_rst_reserved_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>

--- a/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+++ b/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
@@ -197,7 +197,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
      carrier_csr_ctrl_dac_clr_n_o     : out std_logic;
      carrier_csr_ctrl_reserved_o      : out std_logic_vector(28 downto 0);
      carrier_csr_rst_fmc0_n_o         : out std_logic;
-      carrier_csr_rst_reserved_o       : out std_logic_vector(19 downto 0)
+      carrier_csr_rst_reserved_o       : out std_logic_vector(30 downto 0)
      );
  end component carrier_csr;


--- a/hdl/spec/wb_gen/carrier_csr.h
+++ b/hdl/spec/wb_gen/carrier_csr.h
@@ -3,7 +3,7 @@

  * File           : carrier_csr.h
  * Author         : auto-generated by wbgen2 from carrier_csr.wb
-  * Created        : Fri Jul 26 16:52:08 2013
+  * Created        : Thu Aug  8 14:54:22 2013
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
@@ -94,10 +94,10 @@
 #define CARRIER_CSR_RST_FMC0_N                WBGEN2_GEN_MASK(0, 1)

 /* definitions for field: Reserved in reg: Reset Register */
-#define CARRIER_CSR_RST_RESERVED_MASK         WBGEN2_GEN_MASK(1, 20)
+#define CARRIER_CSR_RST_RESERVED_MASK         WBGEN2_GEN_MASK(1, 31)
 #define CARRIER_CSR_RST_RESERVED_SHIFT        1
-#define CARRIER_CSR_RST_RESERVED_W(value)     WBGEN2_GEN_WRITE(value, 1, 20)
-#define CARRIER_CSR_RST_RESERVED_R(reg)       WBGEN2_GEN_READ(reg, 1, 20)
+#define CARRIER_CSR_RST_RESERVED_W(value)     WBGEN2_GEN_WRITE(value, 1, 31)
+#define CARRIER_CSR_RST_RESERVED_R(reg)       WBGEN2_GEN_READ(reg, 1, 31)

 PACKED struct CARRIER_CSR_WB {
  /* [0x0]: REG Carrier type and PCB version */

--- a/hdl/spec/wb_gen/carrier_csr.htm
+++ b/hdl/spec/wb_gen/carrier_csr.htm
@@ -480,7 +480,7 @@ carrier_csr_rst_fmc0_n_o

 </td>
 <td  class="td_pblock_right">
-carrier_csr_rst_reserved_o[19:0]
+carrier_csr_rst_reserved_o[30:0]
 </td>
 <td  class="td_arrow_right">
 &rArr;
@@ -1366,29 +1366,29 @@ Controls software reset of the mezzanine including the ddr interface and the tim
 </td>
 </tr>
 <tr>
-<td  class="td_unused">
-
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+RESERVED[30:23]
 </td>
-<td  class="td_unused">
-
+<td >
+
 </td>
-<td  class="td_unused">
-
+<td >
+
 </td>
-<td  class="td_unused">
-
+<td >
+
 </td>
-<td  class="td_unused">
-
+<td >
+
 </td>
-<td  class="td_unused">
-
+<td >
+
 </td>
-<td  class="td_unused">
-
+<td >
+
 </td>
-<td  class="td_unused">
-
+<td >
+
 </td>
 </tr>
 </table>
@@ -1420,17 +1420,17 @@ Controls software reset of the mezzanine including the ddr interface and the tim
 </td>
 </tr>
 <tr>
-<td  class="td_unused">
-
+<td style="border: solid 1px black;" colspan=8  class="td_field">
+RESERVED[22:15]
 </td>
-<td  class="td_unused">
-
+<td >
+
 </td>
-<td  class="td_unused">
-
+<td >
+
 </td>
-<td style="border: solid 1px black;" colspan=5  class="td_field">
-RESERVED[19:15]
+<td >
+
 </td>
 <td >


--- a/hdl/spec/wb_gen/carrier_csr.wb
+++ b/hdl/spec/wb_gen/carrier_csr.wb
@@ -154,7 +154,7 @@ peripheral {
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
      type = SLV;
-      size = 20;
+      size = 31;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };