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FMC ADC 100M 14b 4cha - Gateware
Commits
2b23e6d5
Commit
2b23e6d5
authored
Dec 10, 2019
by
Dimitris Lampridis
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remove unused I2C master from fmc_adc_mezzanine, it is handled by the Convention
parent
920b7a16
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5 changed files
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16 additions
and
119 deletions
+16
-119
fmc_adc_mezzanine_mmap.cheby
hdl/cheby/fmc_adc_mezzanine_mmap.cheby
+0
-8
fmc_adc_mezzanine_mmap.vhd
hdl/cheby/fmc_adc_mezzanine_mmap.vhd
+8
-67
fmc_adc_mezzanine.vhd
hdl/rtl/fmc_adc_mezzanine.vhd
+6
-33
fmc_adc_mezzanine_mmap.v
hdl/testbench/include/fmc_adc_mezzanine_mmap.v
+0
-2
fmc_adc_mezzanine_mmap.h
software/include/hw/fmc_adc_mezzanine_mmap.h
+2
-9
No files found.
hdl/cheby/fmc_adc_mezzanine_mmap.cheby
View file @
2b23e6d5
...
...
@@ -11,14 +11,6 @@ memory-map:
address: 0x1000
description: FMC ADC 100M CSR
filename: fmc_adc_100Ms_csr.cheby
- submap:
name: fmc_i2c_master
address: 0x1400
size: 0x100
interface: wb-32-be
x-hdl:
busgroup: True
description: Mezzanine system management I2C master
- submap:
name: fmc_adc_eic
address: 0x1500
...
...
hdl/cheby/fmc_adc_mezzanine_mmap.vhd
View file @
2b23e6d5
...
...
@@ -17,10 +17,6 @@ entity fmc_adc_mezzanine_mmap is
fmc_adc_100m_csr_i
:
in
t_wishbone_master_in
;
fmc_adc_100m_csr_o
:
out
t_wishbone_master_out
;
-- Mezzanine system management I2C master
fmc_i2c_master_i
:
in
t_wishbone_master_in
;
fmc_i2c_master_o
:
out
t_wishbone_master_out
;
-- FMC ADC Embedded Interrupt Controller
fmc_adc_eic_i
:
in
t_wishbone_master_in
;
fmc_adc_eic_o
:
out
t_wishbone_master_out
;
...
...
@@ -58,12 +54,6 @@ architecture syn of fmc_adc_mezzanine_mmap is
signal
fmc_adc_100m_csr_tr
:
std_logic
;
signal
fmc_adc_100m_csr_wack
:
std_logic
;
signal
fmc_adc_100m_csr_rack
:
std_logic
;
signal
fmc_i2c_master_re
:
std_logic
;
signal
fmc_i2c_master_wt
:
std_logic
;
signal
fmc_i2c_master_rt
:
std_logic
;
signal
fmc_i2c_master_tr
:
std_logic
;
signal
fmc_i2c_master_wack
:
std_logic
;
signal
fmc_i2c_master_rack
:
std_logic
;
signal
fmc_adc_eic_re
:
std_logic
;
signal
fmc_adc_eic_wt
:
std_logic
;
signal
fmc_adc_eic_rt
:
std_logic
;
...
...
@@ -151,26 +141,6 @@ begin
fmc_adc_100m_csr_o
.
we
<=
fmc_adc_100m_csr_wt
;
fmc_adc_100m_csr_o
.
dat
<=
wb_i
.
dat
;
-- Assignments for submap fmc_i2c_master
fmc_i2c_master_tr
<=
fmc_i2c_master_wt
or
fmc_i2c_master_rt
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
fmc_i2c_master_rt
<=
'0'
;
else
fmc_i2c_master_rt
<=
(
fmc_i2c_master_rt
or
fmc_i2c_master_re
)
and
not
fmc_i2c_master_rack
;
end
if
;
end
if
;
end
process
;
fmc_i2c_master_o
.
cyc
<=
fmc_i2c_master_tr
;
fmc_i2c_master_o
.
stb
<=
fmc_i2c_master_tr
;
fmc_i2c_master_wack
<=
fmc_i2c_master_i
.
ack
and
fmc_i2c_master_wt
;
fmc_i2c_master_rack
<=
fmc_i2c_master_i
.
ack
and
fmc_i2c_master_rt
;
fmc_i2c_master_o
.
adr
<=
((
23
downto
0
=>
'0'
)
&
wb_i
.
adr
(
7
downto
2
))
&
(
1
downto
0
=>
'0'
);
fmc_i2c_master_o
.
sel
<=
(
others
=>
'1'
);
fmc_i2c_master_o
.
we
<=
fmc_i2c_master_wt
;
fmc_i2c_master_o
.
dat
<=
wb_i
.
dat
;
-- Assignments for submap fmc_adc_eic
fmc_adc_eic_tr
<=
fmc_adc_eic_wt
or
fmc_adc_eic_rt
;
process
(
clk_i
)
begin
...
...
@@ -277,7 +247,6 @@ begin
if
rst_n_i
=
'0'
then
wr_ack_int
<=
'0'
;
fmc_adc_100m_csr_wt
<=
'0'
;
fmc_i2c_master_wt
<=
'0'
;
fmc_adc_eic_wt
<=
'0'
;
si570_i2c_master_wt
<=
'0'
;
ds18b20_onewire_master_wt
<=
'0'
;
...
...
@@ -286,7 +255,6 @@ begin
else
wr_ack_int
<=
'0'
;
fmc_adc_100m_csr_wt
<=
'0'
;
fmc_i2c_master_wt
<=
'0'
;
fmc_adc_eic_wt
<=
'0'
;
si570_i2c_master_wt
<=
'0'
;
ds18b20_onewire_master_wt
<=
'0'
;
...
...
@@ -298,18 +266,9 @@ begin
fmc_adc_100m_csr_wt
<=
(
fmc_adc_100m_csr_wt
or
wr_int
)
and
not
fmc_adc_100m_csr_wack
;
wr_ack_int
<=
fmc_adc_100m_csr_wack
;
when
"1010"
=>
case
wb_i
.
adr
(
8
downto
8
)
is
when
"0"
=>
-- Submap fmc_i2c_master
fmc_i2c_master_wt
<=
(
fmc_i2c_master_wt
or
wr_int
)
and
not
fmc_i2c_master_wack
;
wr_ack_int
<=
fmc_i2c_master_wack
;
when
"1"
=>
-- Submap fmc_adc_eic
fmc_adc_eic_wt
<=
(
fmc_adc_eic_wt
or
wr_int
)
and
not
fmc_adc_eic_wack
;
wr_ack_int
<=
fmc_adc_eic_wack
;
when
others
=>
wr_ack_int
<=
wr_int
;
end
case
;
-- Submap fmc_adc_eic
fmc_adc_eic_wt
<=
(
fmc_adc_eic_wt
or
wr_int
)
and
not
fmc_adc_eic_wack
;
wr_ack_int
<=
fmc_adc_eic_wack
;
when
"1011"
=>
case
wb_i
.
adr
(
8
downto
8
)
is
when
"0"
=>
...
...
@@ -353,13 +312,6 @@ begin
case
wb_i
.
adr
(
12
downto
9
)
is
when
"1000"
=>
when
"1010"
=>
case
wb_i
.
adr
(
8
downto
8
)
is
when
"0"
=>
when
"1"
=>
when
others
=>
reg_rdat_int
<=
(
others
=>
'X'
);
rd_ack1_int
<=
rd_int
;
end
case
;
when
"1011"
=>
case
wb_i
.
adr
(
8
downto
8
)
is
when
"0"
=>
...
...
@@ -385,11 +337,10 @@ begin
end
process
;
-- Process for read requests.
process
(
wb_i
.
adr
,
reg_rdat_int
,
rd_ack1_int
,
rd_int
,
rd_int
,
fmc_adc_100m_csr_i
.
dat
,
fmc_adc_100m_csr_rack
,
fmc_adc_100m_csr_rt
,
rd_int
,
fmc_
i2c_master_i
.
dat
,
fmc_i2c_master_rack
,
fmc_i2c_master_rt
,
rd_int
,
fmc_
adc_eic_i
.
dat
,
fmc_adc_eic_rack
,
fmc_adc_eic_rt
,
rd_int
,
si570_i2c_master_i
.
dat
,
si570_i2c_master_rack
,
si570_i2c_master_rt
,
rd_int
,
ds18b20_onewire_master_i
.
dat
,
ds18b20_onewire_master_rack
,
ds18b20_onewire_master_rt
,
rd_int
,
fmc_spi_master_i
.
dat
,
fmc_spi_master_rack
,
fmc_spi_master_rt
,
rd_int
,
timetag_core_i
.
dat
,
timetag_core_rack
,
timetag_core_rt
)
begin
process
(
wb_i
.
adr
,
reg_rdat_int
,
rd_ack1_int
,
rd_int
,
rd_int
,
fmc_adc_100m_csr_i
.
dat
,
fmc_adc_100m_csr_rack
,
fmc_adc_100m_csr_rt
,
rd_int
,
fmc_adc_eic_i
.
dat
,
fmc_adc_eic_rack
,
fmc_adc_eic_rt
,
rd_int
,
si570_i2c_master_i
.
dat
,
si570_i2c_master_rack
,
si570_i2c_master_rt
,
rd_int
,
ds18b20_onewire_master_i
.
dat
,
ds18b20_onewire_master_rack
,
ds18b20_onewire_master_rt
,
rd_int
,
fmc_spi_master_i
.
dat
,
fmc_spi_master_rack
,
fmc_spi_master_rt
,
rd_int
,
timetag_core_i
.
dat
,
timetag_core_rack
,
timetag_core_rt
)
begin
-- By default ack read requests
wb_o
.
dat
<=
(
others
=>
'0'
);
fmc_adc_100m_csr_re
<=
'0'
;
fmc_i2c_master_re
<=
'0'
;
fmc_adc_eic_re
<=
'0'
;
si570_i2c_master_re
<=
'0'
;
ds18b20_onewire_master_re
<=
'0'
;
...
...
@@ -402,20 +353,10 @@ begin
wb_o
.
dat
<=
fmc_adc_100m_csr_i
.
dat
;
rd_ack_int
<=
fmc_adc_100m_csr_rack
;
when
"1010"
=>
case
wb_i
.
adr
(
8
downto
8
)
is
when
"0"
=>
-- Submap fmc_i2c_master
fmc_i2c_master_re
<=
rd_int
;
wb_o
.
dat
<=
fmc_i2c_master_i
.
dat
;
rd_ack_int
<=
fmc_i2c_master_rack
;
when
"1"
=>
-- Submap fmc_adc_eic
fmc_adc_eic_re
<=
rd_int
;
wb_o
.
dat
<=
fmc_adc_eic_i
.
dat
;
rd_ack_int
<=
fmc_adc_eic_rack
;
when
others
=>
rd_ack_int
<=
rd_int
;
end
case
;
-- Submap fmc_adc_eic
fmc_adc_eic_re
<=
rd_int
;
wb_o
.
dat
<=
fmc_adc_eic_i
.
dat
;
rd_ack_int
<=
fmc_adc_eic_rack
;
when
"1011"
=>
case
wb_i
.
adr
(
8
downto
8
)
is
when
"0"
=>
...
...
hdl/rtl/fmc_adc_mezzanine.vhd
View file @
2b23e6d5
...
...
@@ -134,16 +134,15 @@ architecture rtl of fmc_adc_mezzanine is
------------------------------------------------------------------------------
-- Number of slaves on the wishbone crossbar
constant
c_NUM_WB_SLAVES
:
integer
:
=
7
;
constant
c_NUM_WB_SLAVES
:
integer
:
=
6
;
-- Wishbone slave(s)
constant
c_WB_SLAVE_FMC_ADC
:
integer
:
=
0
;
-- Mezzanine ADC core
constant
c_WB_SLAVE_FMC_SYS_I2C
:
integer
:
=
1
;
-- Mezzanine system I2C interface (EEPROM)
constant
c_WB_SLAVE_FMC_EIC
:
integer
:
=
2
;
-- Mezzanine interrupt controller
constant
c_WB_SLAVE_FMC_I2C
:
integer
:
=
3
;
-- Mezzanine I2C controller
constant
c_WB_SLAVE_FMC_ONEWIRE
:
integer
:
=
4
;
-- Mezzanine onewire interface
constant
c_WB_SLAVE_FMC_SPI
:
integer
:
=
5
;
-- Mezzanine SPI interface
constant
c_WB_SLAVE_TIMETAG
:
integer
:
=
6
;
-- Mezzanine timetag core
constant
c_WB_SLAVE_FMC_EIC
:
integer
:
=
1
;
-- Mezzanine interrupt controller
constant
c_WB_SLAVE_FMC_I2C
:
integer
:
=
2
;
-- Mezzanine I2C controller
constant
c_WB_SLAVE_FMC_ONEWIRE
:
integer
:
=
3
;
-- Mezzanine onewire interface
constant
c_WB_SLAVE_FMC_SPI
:
integer
:
=
4
;
-- Mezzanine SPI interface
constant
c_WB_SLAVE_TIMETAG
:
integer
:
=
5
;
-- Mezzanine timetag core
------------------------------------------------------------------------------
-- Signals declaration
...
...
@@ -240,8 +239,6 @@ begin
wb_o
=>
cnx_master_in
,
fmc_adc_100m_csr_i
=>
cnx_slave_out
(
c_WB_SLAVE_FMC_ADC
),
fmc_adc_100m_csr_o
=>
cnx_slave_in
(
c_WB_SLAVE_FMC_ADC
),
fmc_i2c_master_i
=>
cnx_slave_out
(
c_WB_SLAVE_FMC_SYS_I2C
),
fmc_i2c_master_o
=>
cnx_slave_in
(
c_WB_SLAVE_FMC_SYS_I2C
),
fmc_adc_eic_i
=>
cnx_slave_out
(
c_WB_SLAVE_FMC_EIC
),
fmc_adc_eic_o
=>
cnx_slave_in
(
c_WB_SLAVE_FMC_EIC
),
si570_i2c_master_i
=>
cnx_slave_out
(
c_WB_SLAVE_FMC_I2C
),
...
...
@@ -253,30 +250,6 @@ begin
timetag_core_i
=>
cnx_slave_out
(
c_WB_SLAVE_TIMETAG
),
timetag_core_o
=>
cnx_slave_in
(
c_WB_SLAVE_TIMETAG
));
------------------------------------------------------------------------------
-- Mezzanine system managment I2C master
-- Access to mezzanine EEPROM
------------------------------------------------------------------------------
cmp_fmc_sys_i2c
:
xwb_i2c_master
generic
map
(
g_interface_mode
=>
CLASSIC
,
g_address_granularity
=>
BYTE
)
port
map
(
clk_sys_i
=>
sys_clk_i
,
rst_n_i
=>
sys_rst_n_i
,
slave_i
=>
cnx_slave_in
(
c_WB_SLAVE_FMC_SYS_I2C
),
slave_o
=>
cnx_slave_out
(
c_WB_SLAVE_FMC_SYS_I2C
),
desc_o
=>
open
,
scl_pad_i
(
0
)
=>
'1'
,
scl_pad_o
(
0
)
=>
open
,
scl_padoen_o
(
0
)
=>
open
,
sda_pad_i
(
0
)
=>
'1'
,
sda_pad_o
(
0
)
=>
open
,
sda_padoen_o
(
0
)
=>
open
);
------------------------------------------------------------------------------
-- Mezzanine SPI master
-- Offset DACs control
...
...
hdl/testbench/include/fmc_adc_mezzanine_mmap.v
View file @
2b23e6d5
`define
FMC_ADC_MEZZANINE_MMAP_SIZE
8192
`define
ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR
'
h1000
`define
FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR_SIZE 512
`define
ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_I2C_MASTER
'
h1400
`define
FMC_ADC_MEZZANINE_MMAP_FMC_I2C_MASTER_SIZE 256
`define
ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC
'
h1500
`define
FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC_SIZE 16
`define
ADDR_FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER
'
h1600
...
...
software/include/hw/fmc_adc_mezzanine_mmap.h
View file @
2b23e6d5
...
...
@@ -9,10 +9,6 @@
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR 0x1000UL
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR_SIZE 512
/* Mezzanine system management I2C master */
#define FMC_ADC_MEZZANINE_MMAP_FMC_I2C_MASTER 0x1400UL
#define FMC_ADC_MEZZANINE_MMAP_FMC_I2C_MASTER_SIZE 256
/* FMC ADC Embedded Interrupt Controller */
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC 0x1500UL
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC_SIZE 16
...
...
@@ -40,11 +36,8 @@ struct fmc_adc_mezzanine_mmap {
/* [0x1000]: SUBMAP FMC ADC 100M CSR */
struct
fmc_adc_100ms_csr
fmc_adc_100m_csr
;
/* padding to: 1280 words */
uint32_t
__padding_1
[
128
];
/* [0x1400]: SUBMAP Mezzanine system management I2C master */
uint32_t
fmc_i2c_master
[
64
];
/* padding to: 1344 words */
uint32_t
__padding_1
[
192
];
/* [0x1500]: SUBMAP FMC ADC Embedded Interrupt Controller */
uint32_t
fmc_adc_eic
[
4
];
...
...
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