hdl: Implements a seris of new features:

- Variable data saturation. - Optional trigger threshold detection deglitch filter. - Internal trigger test mode. - Sampling frequency counter. - Remaining shot counter. - Defined DAC (for VCXO) control outputs value. - Check number of samples in multi-shot (shouldn't exceed ram depth).

hdl: Implements a seris of new features:
- Variable data saturation. - Optional trigger threshold detection deglitch filter. - Internal trigger test mode. - Sampling frequency counter. - Remaining shot counter. - Defined DAC (for VCXO) control outputs value. - Check number of samples in multi-shot (shouldn't exceed ram depth).
267af46a · Matthieu Cattin · eb59690b · 267af46a · 267af46a · 267af46a
Commit 267af46a authored Mar 20, 2014 by Matthieu Cattin
18 changed files
--- a/hdl/adc/rtl/Manifest.py
+++ b/hdl/adc/rtl/Manifest.py
@@ -5,4 +5,5 @@ files = [
    "fmc_adc_100Ms_core_pkg.vhd",
    "fmc_adc_100Ms_csr.vhd",
    "fmc_adc_eic.vhd",
-    "offset_gain_s.vhd"]
+    "offset_gain_s.vhd",
+    "var_sat_s.vhd"]
--- a/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
--- a/hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
@@ -61,7 +61,7 @@ package fmc_adc_100Ms_core_pkg is
      sys_rst_n_i : in std_logic;

      -- CSR wishbone interface
-      wb_csr_adr_i : in  std_logic_vector(4 downto 0);
+      wb_csr_adr_i : in  std_logic_vector(5 downto 0);
      wb_csr_dat_i : in  std_logic_vector(31 downto 0);
      wb_csr_dat_o : out std_logic_vector(31 downto 0);
      wb_csr_cyc_i : in  std_logic;

--- a/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
--- a/hdl/adc/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/adc/rtl/fmc_adc_mezzanine.vhd
@@ -183,7 +183,7 @@ architecture rtl of fmc_adc_mezzanine is
    wbd_width     => x"4",                 -- 32-bit port granularity
    sdb_component => (
      addr_first  => x"0000000000000000",
-      addr_last   => x"000000000000007F",
+      addr_last   => x"00000000000000FF",
      product     => (
        vendor_id => x"000000000000CE42",  -- CERN
        device_id => x"00000608",
@@ -447,7 +447,7 @@ begin
      sys_clk_i   => sys_clk_i,
      sys_rst_n_i => sys_rst_n_i,

-      wb_csr_adr_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).adr(6 downto 2),  -- cnx_master_out.adr is byte address
+      wb_csr_adr_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).adr(7 downto 2),  -- cnx_master_out.adr is byte address
      wb_csr_dat_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).dat,
      wb_csr_dat_o => cnx_master_in(c_WB_SLAVE_FMC_ADC).dat,
      wb_csr_cyc_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).cyc,

--- a/hdl/adc/rtl/var_sat_s.vhd
+++ b/hdl/adc/rtl/var_sat_s.vhd
+--------------------------------------------------------------------------------
+-- CERN (BE-CO-HT)
+-- Variable saturation, signed data input and output (two's complement)
+-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
+--------------------------------------------------------------------------------
+--
+-- unit name: var_sat_s (var_sat_s.vhd)
+--
+-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
+--
+-- date: 14-03-2013
+--
+-- version: 1.0
+--
+-- description: Variable saturation.
+--              Latency = 1
+--
+--                           ________
+--                          |        |
+--              data_i ---->|saturate|--> data_o
+--                          |________|
+--                              ^
+--                              |
+--                            sat_i
+--
+--
+-- dependencies:
+--
+--------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--------------------------------------------------------------------------------
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--------------------------------------------------------------------------------
+-- TODO: - 
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library UNIMACRO;
+use UNIMACRO.vcomponents.all;
+
+
+------------------------------------------------------------------------------
+-- Entity declaration
+------------------------------------------------------------------------------
+entity var_sat_s is
+  port (
+    rst_n_i : in  std_logic;                      --! Reset (active low)
+    clk_i   : in  std_logic;                      --! Clock
+    sat_i   : in  std_logic_vector(14 downto 0);  --! Unsigned saturation value input
+    data_i  : in  std_logic_vector(15 downto 0);  --! Signed data input (two's complement)
+    data_o  : out std_logic_vector(15 downto 0)   --! Signed data output (two's complement)
+    );
+end entity var_sat_s;
+
+
+------------------------------------------------------------------------------
+-- Architecture declaration
+------------------------------------------------------------------------------
+architecture rtl of var_sat_s is
+
+  ------------------------------------------------------------------------------
+  -- Constants declaration
+  ------------------------------------------------------------------------------
+  constant c_one : signed(15 downto 0) := X"0001";
+
+  ------------------------------------------------------------------------------
+  -- Signals declaration
+  ------------------------------------------------------------------------------
+  signal pos_sat : signed(15 downto 0);
+  signal neg_sat : signed(15 downto 0);
+
+
+begin
+
+  pos_sat <= signed('0' & sat_i);
+  neg_sat <= signed(not('0' & sat_i))+c_one;
+
+  ------------------------------------------------------------------------------
+  -- Saturate
+  ------------------------------------------------------------------------------
+  p_saturate : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        data_o <= (others => '0');
+      elsif signed(data_i) >= pos_sat then
+        data_o <= std_logic_vector(pos_sat);  -- saturate positive
+      elsif signed(data_i) <= neg_sat then
+        data_o <= std_logic_vector(neg_sat);  -- saturate negative
+      else
+        data_o <= data_i;
+      end if;
+    end if;
+  end process p_saturate;
+
+
+end architecture rtl;
--- a/hdl/adc/wb_gen/Makefile
+++ b/hdl/adc/wb_gen/Makefile
 WBGEN2=~/projects/wbgen2/wbgen2
 RTL=../rtl/
-TEX=../../../documentation/manuals/firmware/
+TEX=../../../documentation/manuals/gateware/

 fmc_adc_100Ms_csr:
 	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb

--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
@@ -187,14 +187,34 @@ peripheral {
      clock = "fs_clk_i";
    };

+    field {
+      name = "Enable internal trigger test mode";
+      description = "Test mode:\n  ch1 = Channel 1 input(analogue)\n ch2 = Channel input over threshold (digital)\n  ch3 = Channel input over threshold filtered (digital)\n  ch4 = Trigger (digital)";
+      prefix = "int_trig_test_en";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
+    };
+
    field {
      name = "Reserved";
      description = "Ignore on read, write with 0's";
      prefix = "reserved";
+      type = BIT;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
+    field {
+      name = "Internal trigger threshold glitch filter";
+      description = "Configures the internal trigger threshold glitch filter length.";
+      prefix = "int_trig_thres_filt";
      type = SLV;
-      size = 10;
+      size = 8;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
+      clock = "fs_clk_i";
    };

    field {
@@ -261,6 +281,31 @@ peripheral {
    };
  };

+  reg {
+    name = "Remaining shots counter";
+    prefix = "shots_cnt";
+
+    field {
+      name = "Remaining shots counter";
+      description = "Counts the number of remaining shots to acquire.";
+      prefix = "val";
+      type = SLV;
+      size = 16;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's";
+      prefix = "reserved";
+      type = SLV;
+      size = 16;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+  };
+
  reg {
    name = "Trigger address register";
    prefix = "trig_pos";
@@ -275,6 +320,21 @@ peripheral {
    };
  };

+  reg {
+    name = "Sampling clock frequency";
+    prefix = "fs_freq";
+
+    field {
+      name = "Sampling clock frequency";
+      description = "ADC sampling clock frequency in Hz";
+      type = SLV;
+      size = 32;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+      clock = "fs_clk_i";
+    };
+  };
+
  reg {
    name = "Sample rate";
    prefix = "sr";
@@ -434,6 +494,31 @@ peripheral {
    };
  };

+  reg {
+    name = "Channel 1 saturation register";
+    prefix = "ch1_sat";
+
+    field {
+      name = "Saturation value for channel 1";
+      description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
+      prefix = "val";
+      type = SLV;
+      size = 15;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's";
+      prefix = "reserved";
+      type = SLV;
+      size = 17;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+  };
+
  reg {
    name = "Channel 2 control register";
    prefix = "ch2_ctl";
@@ -535,6 +620,31 @@ peripheral {
    };
  };

+  reg {
+    name = "Channel 2 saturation register";
+    prefix = "ch2_sat";
+
+    field {
+      name = "Saturation value for channel 2";
+      description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
+      prefix = "val";
+      type = SLV;
+      size = 15;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's";
+      prefix = "reserved";
+      type = SLV;
+      size = 17;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+  };
+
  reg {
    name = "Channel 3 control register";
    prefix = "ch3_ctl";
@@ -636,6 +746,31 @@ peripheral {
    };
  };

+  reg {
+    name = "Channel 3 saturation register";
+    prefix = "ch3_sat";
+
+    field {
+      name = "Saturation value for channel 3";
+      description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
+      prefix = "val";
+      type = SLV;
+      size = 15;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's";
+      prefix = "reserved";
+      type = SLV;
+      size = 17;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+  };
+
  reg {
    name = "Channel 4 control register";
    prefix = "ch4_ctl";
@@ -737,4 +872,29 @@ peripheral {
    };
  };

+  reg {
+    name = "Channel 4 saturation register";
+    prefix = "ch4_sat";
+
+    field {
+      name = "Saturation value for channel 4";
+      description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
+      prefix = "val";
+      type = SLV;
+      size = 15;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+
+    field {
+      name = "Reserved";
+      description = "Ignore on read, write with 0's";
+      prefix = "reserved";
+      type = SLV;
+      size = 17;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+  };
+
 };
--- a/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+++ b/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
@@ -60,6 +60,12 @@ entity spec_top_fmc_adc_100Ms is
      -- Local oscillator
      clk20_vcxo_i : in std_logic;      -- 20MHz VCXO clock

+      -- DAC interface (20MHz and 25MHz VCXO)
+      pll25dac_sync_n_o : out std_logic;  -- 25MHz VCXO
+      pll20dac_sync_n_o : out std_logic;  -- 20MHz VCXO
+      plldac_din_o      : out std_logic;
+      plldac_sclk_o     : out std_logic;
+
      -- Carrier font panel LEDs
      led_red_o   : out std_logic;
      led_green_o : out std_logic;
@@ -453,6 +459,15 @@ begin
  -- 250.000 MHz fast system clock
  -- 333.333 MHz DDR3 clock
  ------------------------------------------------------------------------------
+
+  -- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a
+  -- write sequence arrives to the DAC.
+  -- To avoid spurious writes, the DAC interface outputs are fixed to safe values.
+  pll25dac_sync_n_o <= '1';
+  pll20dac_sync_n_o <= '1';
+  plldac_din_o      <= '0';
+  plldac_sclk_o     <= '0';
+
  cmp_sys_clk_buf : IBUFG
    port map (
      I => clk20_vcxo_i,

--- a/hdl/spec/spec_top_fmc_adc_100Ms.ucf
+++ b/hdl/spec/spec_top_fmc_adc_100Ms.ucf
@@ -43,14 +43,14 @@ NET "clk20_vcxo_i" IOSTANDARD = "LVCMOS25";
 #----------------------------------------
 # DAC interface (for VCXO)
 #----------------------------------------
-#NET "PLL25DAC1_SYNC_N" LOC = A3;
-#NET "PLL25DAC1_SYNC_N" IOSTANDARD = "LVCMOS25";
-#NET "PLL25DAC2_SYNC_N" LOC = B3;
-#NET "PLL25DAC2_SYNC_N" IOSTANDARD = "LVCMOS25";
-#NET "PLL25DAC_DIN" LOC = C4;
-#NET "PLL25DAC_DIN" IOSTANDARD = "LVCMOS25";
-#NET "PLL25DAC_SCLK" LOC = A4;
-#NET "PLL25DAC_SCLK" IOSTANDARD = "LVCMOS25";
+NET "pll25dac_sync_n_o" LOC = A3;
+NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS25";
+NET "pll20dac_sync_n_o" LOC = B3;
+NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS25";
+NET "plldac_din_o" LOC = C4;
+NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
+NET "plldac_sclk_o" LOC = A4;
+NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";

 #----------------------------------------
 # 1-wire thermometer w/ ID

--- a/hdl/spec/syn/spec_fmc_adc_100Ms.xise
+++ b/hdl/spec/syn/spec_fmc_adc_100Ms.xise
--- a/hdl/spec/wb_gen/Makefile
+++ b/hdl/spec/wb_gen/Makefile
 WBGEN2=~/projects/wbgen2/wbgen2
 RTL=../rtl/
-TEX=../../../documentation/manuals/firmware/spec/
+TEX=../../../documentation/manuals/gateware/spec/

 carrier_csr:
 	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb

--- a/hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
+++ b/hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
@@ -62,6 +62,14 @@ entity svec_top_fmc_adc_100Ms is
      -- Local 20MHz VCXO oscillator
      clk_20m_vcxo_i : in std_logic;

+      -- DAC interface (20MHz and 25MHz VCXO)
+      pll20dac_din_o    : out std_logic;
+      pll20dac_sclk_o   : out std_logic;
+      pll20dac_sync_n_o : out std_logic;
+      pll25dac_din_o    : out std_logic;
+      pll25dac_sclk_o   : out std_logic;
+      pll25dac_sync_n_o : out std_logic;
+
      -- Reset from system fpga
      rst_n_i : in std_logic;

@@ -561,6 +569,17 @@ begin
  -- 125.000 MHz system clock
  -- 333.333 MHz DDR3 clock
  ------------------------------------------------------------------------------
+
+  -- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a
+  -- write sequence arrives to the DAC.
+  -- To avoid spurious writes, the DAC interface outputs are fixed to safe values.
+  pll20dac_din_o    <= '0';
+  pll20dac_sclk_o   <= '0';
+  pll20dac_sync_n_o <= '1';
+  pll25dac_din_o    <= '0';
+  pll25dac_sclk_o   <= '0';
+  pll25dac_sync_n_o <= '1';
+
  cmp_sys_clk_buf : IBUFG
    port map (
      I => clk_20m_vcxo_i,
@@ -878,7 +897,7 @@ begin
  cnx_master_in(c_WB_SLAVE_SVEC_CSR).int   <= '0';

  -- external software reset registers (to assign a non-zero default value)
-  p_sw_rst_fmc0: process (sys_clk_125)
+  p_sw_rst_fmc0 : process (sys_clk_125)
  begin
    if rising_edge(sys_clk_125) then
      if sys_rst_n = '0' then
@@ -891,7 +910,7 @@ begin

  sw_rst_fmc0_n_i <= sw_rst_fmc0_n;

-  p_sw_rst_fmc1: process (sys_clk_125)
+  p_sw_rst_fmc1 : process (sys_clk_125)
  begin
    if rising_edge(sys_clk_125) then
      if sys_rst_n = '0' then

--- a/hdl/svec/svec_top_fmc_adc_100Ms.ucf
+++ b/hdl/svec/svec_top_fmc_adc_100Ms.ucf
@@ -457,18 +457,18 @@ NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
 #----------------------------------------
 # Clock controls
 #----------------------------------------
-#NET "pll20dac_din_o" LOC = U28;
-#NET "pll20dac_sclk_o" LOC = AA28;
-#NET "pll20dac_sync_n_o" LOC = N28;
-#NET "pll25dac_din_o" LOC = P25;
-#NET "pll25dac_sclk_o" LOC = N27;
-#NET "pll25dac_sync_n_o" LOC = P26;
-#NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
-#NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
-#NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
-#NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
-#NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
-#NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
+NET "pll20dac_din_o" LOC = U28;
+NET "pll20dac_sclk_o" LOC = AA28;
+NET "pll20dac_sync_n_o" LOC = N28;
+NET "pll25dac_din_o" LOC = P25;
+NET "pll25dac_sclk_o" LOC = N27;
+NET "pll25dac_sync_n_o" LOC = P26;
+NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
+NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
+NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
+NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
+NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
+NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";

 #----------------------------------------
 # UART

--- a/hdl/svec/syn/svec_fmc_adc_100Ms.xise
+++ b/hdl/svec/syn/svec_fmc_adc_100Ms.xise
--- a/hdl/svec/wb_gen/Makefile
+++ b/hdl/svec/wb_gen/Makefile
 WBGEN2=~/projects/wbgen2/wbgen2
 RTL=../rtl/
-TEX=../../../documentation/manuals/firmware/svec/
+TEX=../../../documentation/manuals/gateware/svec/

 carrier_csr:
 	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb