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FMC ADC 100M 14b 4cha - Gateware
Commit 267af46a authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Implements a seris of new features: 

- Variable data saturation.
- Optional trigger threshold detection deglitch filter.
- Internal trigger test mode.
- Sampling frequency counter.
- Remaining shot counter.
- Defined DAC (for VCXO) control outputs value.
- Check number of samples in multi-shot (shouldn't exceed ram depth).
parent eb59690b
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Showing with 4073 additions and 1166 deletions
hdl/adc/rtl/Manifest.py
View file @ 267af46a
......@@ -5,4 +5,5 @@ files = [
"fmc_adc_100Ms_core_pkg.vhd",
"fmc_adc_100Ms_csr.vhd",
"fmc_adc_eic.vhd",
"offset_gain_s.vhd"]
"offset_gain_s.vhd",
"var_sat_s.vhd"]
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ 267af46a
......@@ -39,14 +39,14 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.timetag_core_pkg.all;
use work.genram_pkg.all;
use work.gencores_pkg.all;
entity fmc_adc_100Ms_core is
......@@ -60,7 +60,7 @@ entity fmc_adc_100Ms_core is
sys_rst_n_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(4 downto 0);
wb_csr_adr_i : in std_logic_vector(5 downto 0);
wb_csr_dat_i : in std_logic_vector(31 downto 0);
wb_csr_dat_o : out std_logic_vector(31 downto 0);
wb_csr_cyc_i : in std_logic;
......@@ -148,81 +148,94 @@ architecture rtl of fmc_adc_100Ms_core is
component fmc_adc_100Ms_csr
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
fmc_adc_core_ctl_fsm_cmd_o : out std_logic_vector(1 downto 0);
fmc_adc_core_ctl_fsm_cmd_wr_o : out std_logic;
fmc_adc_core_ctl_fmc_clk_oe_o : out std_logic;
fmc_adc_core_ctl_offset_dac_clr_n_o : out std_logic;
fmc_adc_core_ctl_man_bitslip_o : out std_logic;
fmc_adc_core_ctl_test_data_en_o : out std_logic;
fmc_adc_core_ctl_trig_led_o : out std_logic;
fmc_adc_core_ctl_acq_led_o : out std_logic;
fmc_adc_core_ctl_reserved_o : out std_logic_vector(23 downto 0);
fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0);
fmc_adc_core_sta_serdes_pll_i : in std_logic;
fmc_adc_core_sta_serdes_synced_i : in std_logic;
fmc_adc_core_sta_acq_cfg_i : in std_logic;
fmc_adc_core_sta_reserved_i : in std_logic_vector(25 downto 0);
fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic;
fmc_adc_core_trig_cfg_hw_trig_pol_o : out std_logic;
fmc_adc_core_trig_cfg_hw_trig_en_o : out std_logic;
fmc_adc_core_trig_cfg_sw_trig_en_o : out std_logic;
fmc_adc_core_trig_cfg_int_trig_sel_o : out std_logic_vector(1 downto 0);
fmc_adc_core_trig_cfg_reserved_o : out std_logic_vector(9 downto 0);
fmc_adc_core_trig_cfg_int_trig_thres_o : out std_logic_vector(15 downto 0);
fmc_adc_core_trig_dly_o : out std_logic_vector(31 downto 0);
fmc_adc_core_sw_trig_o : out std_logic_vector(31 downto 0);
fmc_adc_core_sw_trig_wr_o : out std_logic;
fmc_adc_core_shots_nb_o : out std_logic_vector(15 downto 0);
fmc_adc_core_shots_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0);
fmc_adc_core_sr_deci_o : out std_logic_vector(31 downto 0);
fmc_adc_core_pre_samples_o : out std_logic_vector(31 downto 0);
fmc_adc_core_post_samples_o : out std_logic_vector(31 downto 0);
fmc_adc_core_samples_cnt_i : in std_logic_vector(31 downto 0);
fmc_adc_core_ch1_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch1_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch1_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch1_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch1_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_offset_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch2_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch2_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch2_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch2_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_offset_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch3_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch3_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch3_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch3_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_offset_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch4_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch4_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch4_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch4_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_offset_reserved_o : out std_logic_vector(15 downto 0)
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
fmc_adc_core_ctl_fsm_cmd_o : out std_logic_vector(1 downto 0);
fmc_adc_core_ctl_fsm_cmd_wr_o : out std_logic;
fmc_adc_core_ctl_fmc_clk_oe_o : out std_logic;
fmc_adc_core_ctl_offset_dac_clr_n_o : out std_logic;
fmc_adc_core_ctl_man_bitslip_o : out std_logic;
fmc_adc_core_ctl_test_data_en_o : out std_logic;
fmc_adc_core_ctl_trig_led_o : out std_logic;
fmc_adc_core_ctl_acq_led_o : out std_logic;
fmc_adc_core_ctl_reserved_o : out std_logic_vector(23 downto 0);
fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0);
fmc_adc_core_sta_serdes_pll_i : in std_logic;
fmc_adc_core_sta_serdes_synced_i : in std_logic;
fmc_adc_core_sta_acq_cfg_i : in std_logic;
fmc_adc_core_sta_reserved_i : in std_logic_vector(25 downto 0);
fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic;
fmc_adc_core_trig_cfg_hw_trig_pol_o : out std_logic;
fmc_adc_core_trig_cfg_hw_trig_en_o : out std_logic;
fmc_adc_core_trig_cfg_sw_trig_en_o : out std_logic;
fmc_adc_core_trig_cfg_int_trig_sel_o : out std_logic_vector(1 downto 0);
fmc_adc_core_trig_cfg_int_trig_test_en_o : out std_logic;
fmc_adc_core_trig_cfg_reserved_o : out std_logic;
fmc_adc_core_trig_cfg_int_trig_thres_filt_o : out std_logic_vector(7 downto 0);
fmc_adc_core_trig_cfg_int_trig_thres_o : out std_logic_vector(15 downto 0);
fmc_adc_core_trig_dly_o : out std_logic_vector(31 downto 0);
fmc_adc_core_sw_trig_o : out std_logic_vector(31 downto 0);
fmc_adc_core_sw_trig_wr_o : out std_logic;
fmc_adc_core_shots_nb_o : out std_logic_vector(15 downto 0);
fmc_adc_core_shots_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_shots_cnt_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_shots_cnt_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0);
fmc_adc_core_fs_freq_i : in std_logic_vector(31 downto 0);
fmc_adc_core_sr_deci_o : out std_logic_vector(31 downto 0);
fmc_adc_core_pre_samples_o : out std_logic_vector(31 downto 0);
fmc_adc_core_post_samples_o : out std_logic_vector(31 downto 0);
fmc_adc_core_samples_cnt_i : in std_logic_vector(31 downto 0);
fmc_adc_core_ch1_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch1_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch1_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch1_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch1_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_offset_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_sat_val_o : out std_logic_vector(14 downto 0);
fmc_adc_core_ch1_sat_reserved_o : out std_logic_vector(16 downto 0);
fmc_adc_core_ch2_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch2_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch2_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch2_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch2_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_offset_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_sat_val_o : out std_logic_vector(14 downto 0);
fmc_adc_core_ch2_sat_reserved_o : out std_logic_vector(16 downto 0);
fmc_adc_core_ch3_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch3_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch3_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch3_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch3_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_offset_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_sat_val_o : out std_logic_vector(14 downto 0);
fmc_adc_core_ch3_sat_reserved_o : out std_logic_vector(16 downto 0);
fmc_adc_core_ch4_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch4_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch4_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch4_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch4_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_offset_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_offset_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_sat_val_o : out std_logic_vector(14 downto 0);
fmc_adc_core_ch4_sat_reserved_o : out std_logic_vector(16 downto 0)
);
end component fmc_adc_100Ms_csr;
......@@ -256,6 +269,16 @@ architecture rtl of fmc_adc_100Ms_core is
);
end component offset_gain_s;
component var_sat_s
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
sat_i : in std_logic_vector(14 downto 0); --! Unsigned saturation value input
data_i : in std_logic_vector(15 downto 0); --! Signed data input (two's complement)
data_o : out std_logic_vector(15 downto 0) --! Signed data output (two's complement)
);
end component var_sat_s;
component monostable
generic(
g_INPUT_POLARITY : std_logic := '1'; --! trigger_i polarity
......@@ -282,6 +305,7 @@ architecture rtl of fmc_adc_100Ms_core is
-- Types declaration
------------------------------------------------------------------------------
type t_acq_fsm_state is (IDLE, PRE_TRIG, WAIT_TRIG, POST_TRIG, TRIG_TAG, DECR_SHOT);
type t_data_pipe is array (natural range<>) of std_logic_vector(63 downto 0);
------------------------------------------------------------------------------
-- Signals declaration
......@@ -293,15 +317,18 @@ architecture rtl of fmc_adc_100Ms_core is
signal fs_rst_n : std_logic;
-- Clocks and PLL
signal dco_clk : std_logic;
signal dco_clk_buf : std_logic;
signal clk_fb : std_logic;
signal clk_fb_buf : std_logic;
signal locked_in : std_logic;
signal locked_out : std_logic;
signal serdes_clk : std_logic;
signal fs_clk : std_logic;
signal fs_clk_buf : std_logic;
signal dco_clk : std_logic;
signal dco_clk_buf : std_logic;
signal clk_fb : std_logic;
signal clk_fb_buf : std_logic;
signal locked_in : std_logic;
signal locked_out : std_logic;
signal serdes_clk : std_logic;
signal fs_clk : std_logic;
signal fs_clk_buf : std_logic;
signal fs_freq : std_logic_vector(31 downto 0);
signal fs_freq_t : std_logic_vector(31 downto 0);
signal fs_freq_valid : std_logic;
-- SerDes
signal serdes_in_p : std_logic_vector(8 downto 0);
......@@ -316,27 +343,36 @@ architecture rtl of fmc_adc_100Ms_core is
signal bitslip_sreg : std_logic_vector(7 downto 0);
-- Trigger
signal ext_trig_a : std_logic;
signal ext_trig : std_logic;
signal int_trig : std_logic;
signal int_trig_over_thres : std_logic;
signal int_trig_over_thres_d : std_logic;
signal int_trig_sel : std_logic_vector(1 downto 0);
signal int_trig_data : std_logic_vector(15 downto 0);
signal int_trig_thres : std_logic_vector(15 downto 0);
signal hw_trig_pol : std_logic;
signal hw_trig : std_logic;
signal hw_trig_t : std_logic;
signal hw_trig_sel : std_logic;
signal hw_trig_en : std_logic;
signal sw_trig : std_logic;
signal sw_trig_t : std_logic;
signal sw_trig_en : std_logic;
signal trig : std_logic;
signal trig_delay : std_logic_vector(31 downto 0);
signal trig_delay_cnt : unsigned(31 downto 0);
signal trig_d : std_logic;
signal trig_align : std_logic;
signal ext_trig_a : std_logic;
signal ext_trig : std_logic;
signal int_trig : std_logic;
signal int_trig_over_thres : std_logic;
signal int_trig_over_thres_d : std_logic;
signal int_trig_over_thres_filt : std_logic;
signal int_trig_over_thres_filt_d : std_logic;
signal int_trig_sel : std_logic_vector(1 downto 0);
signal int_trig_data : std_logic_vector(15 downto 0);
signal int_trig_thres : std_logic_vector(15 downto 0);
signal int_trig_test_en : std_logic;
signal int_trig_thres_filt : std_logic_vector(7 downto 0);
signal hw_trig_pol : std_logic;
signal hw_trig : std_logic;
signal hw_trig_t : std_logic;
signal hw_trig_sel : std_logic;
signal hw_trig_en : std_logic;
signal sw_trig : std_logic;
signal sw_trig_t : std_logic;
signal sw_trig_en : std_logic;
signal trig : std_logic;
signal trig_delay : std_logic_vector(31 downto 0);
signal trig_delay_cnt : unsigned(31 downto 0);
signal trig_d : std_logic;
signal trig_align : std_logic;
-- Internal trigger test mode
signal int_trig_over_thres_tst : std_logic_vector(15 downto 0);
signal int_trig_over_thres_filt_tst : std_logic_vector(15 downto 0);
signal trig_tst : std_logic_vector(15 downto 0);
-- Decimation
signal decim_factor : std_logic_vector(31 downto 0);
......@@ -352,12 +388,14 @@ architecture rtl of fmc_adc_100Ms_core is
signal sync_fifo_rd : std_logic;
signal sync_fifo_valid : std_logic;
-- Gain/offset calibration
-- Gain/offset calibration and saturation value
signal gain_calibr : std_logic_vector(63 downto 0);
signal offset_calibr : std_logic_vector(63 downto 0);
signal data_calibr_in : std_logic_vector(63 downto 0);
signal data_calibr_out : std_logic_vector(63 downto 0);
signal data_calibr_out_d : std_logic_vector(63 downto 0);
signal data_calibr_out_t : std_logic_vector(63 downto 0);
signal data_calibr_out_d : t_data_pipe(3 downto 0);
signal sat_val : std_logic_vector(59 downto 0);
-- Acquisition FSM
signal acq_fsm_current_state : t_acq_fsm_state;
......@@ -391,6 +429,7 @@ architecture rtl of fmc_adc_100Ms_core is
signal samples_cnt : unsigned(31 downto 0);
signal shots_value : std_logic_vector(15 downto 0);
signal shots_cnt : unsigned(15 downto 0);
signal remaining_shots : std_logic_vector(15 downto 0);
signal shots_done : std_logic;
signal shots_decr : std_logic;
signal single_shot : std_logic;
......@@ -432,6 +471,7 @@ architecture rtl of fmc_adc_100Ms_core is
signal ram_addr_cnt : unsigned(24 downto 0);
signal test_data_en : std_logic;
signal trig_addr : std_logic_vector(31 downto 0);
signal mem_ovr : std_logic;
-- Wishbone interface to DDR
signal wb_ddr_stall_t : std_logic;
......@@ -564,6 +604,33 @@ begin
O => clk_fb
);
-- Sampinling clock frequency meter
cmp_fs_freq : gc_frequency_meter
generic map(
g_with_internal_timebase => true,
g_clk_sys_freq => 125000000,
g_counter_bits => 32
)
port map(
clk_sys_i => sys_clk_i,
clk_in_i => fs_clk,
rst_n_i => sys_rst_n_i,
pps_p1_i => '0',
freq_o => fs_freq_t,
freq_valid_o => fs_freq_valid
);
p_fs_freq : process (fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
fs_freq <= (others => '0');
elsif rising_edge(fs_clk) then
if fs_freq_valid = '1' then
fs_freq <= fs_freq_t;
end if;
end if;
end process p_fs_freq;
--gen_fb_clk_check : if (g_carrier_type /= "SPEC" and
-- g_carrier_type /= "SVEC") generate
-- assert false report "[fmc_adc_100Ms_core] Selected carrier type not supported. Must be SPEC or SVEC." severity failure;
......@@ -683,81 +750,94 @@ begin
------------------------------------------------------------------------------
cmp_fmc_adc_100Ms_csr : fmc_adc_100Ms_csr
port map(
rst_n_i => sys_rst_n_i,
clk_sys_i => sys_clk_i,
wb_adr_i => wb_csr_adr_i,
wb_dat_i => wb_csr_dat_i,
wb_dat_o => wb_csr_dat_o,
wb_cyc_i => wb_csr_cyc_i,
wb_sel_i => wb_csr_sel_i,
wb_stb_i => wb_csr_stb_i,
wb_we_i => wb_csr_we_i,
wb_ack_o => wb_csr_ack_o,
wb_stall_o => open,
fs_clk_i => fs_clk,
fmc_adc_core_ctl_fsm_cmd_o => fsm_cmd,
fmc_adc_core_ctl_fsm_cmd_wr_o => fsm_cmd_wr,
fmc_adc_core_ctl_fmc_clk_oe_o => gpio_si570_oe_o,
fmc_adc_core_ctl_offset_dac_clr_n_o => gpio_dac_clr_n_o,
fmc_adc_core_ctl_man_bitslip_o => serdes_man_bitslip,
fmc_adc_core_ctl_test_data_en_o => test_data_en,
fmc_adc_core_ctl_trig_led_o => trig_led_man,
fmc_adc_core_ctl_acq_led_o => acq_led_man,
fmc_adc_core_ctl_reserved_o => open,
fmc_adc_core_sta_fsm_i => acq_fsm_state,
fmc_adc_core_sta_serdes_pll_i => locked_out,
fmc_adc_core_sta_serdes_synced_i => serdes_synced,
fmc_adc_core_sta_acq_cfg_i => acq_config_ok,
fmc_adc_core_sta_reserved_i => (others => '0'),
fmc_adc_core_trig_cfg_hw_trig_sel_o => hw_trig_sel,
fmc_adc_core_trig_cfg_hw_trig_pol_o => hw_trig_pol,
fmc_adc_core_trig_cfg_hw_trig_en_o => hw_trig_en,
fmc_adc_core_trig_cfg_sw_trig_en_o => sw_trig_en,
fmc_adc_core_trig_cfg_int_trig_sel_o => int_trig_sel,
fmc_adc_core_trig_cfg_reserved_o => open,
fmc_adc_core_trig_cfg_int_trig_thres_o => int_trig_thres,
fmc_adc_core_trig_dly_o => trig_delay,
fmc_adc_core_sw_trig_o => open,
fmc_adc_core_sw_trig_wr_o => sw_trig_t,
fmc_adc_core_shots_nb_o => shots_value,
fmc_adc_core_shots_reserved_o => open,
fmc_adc_core_trig_pos_i => trig_addr,
fmc_adc_core_sr_deci_o => decim_factor,
fmc_adc_core_pre_samples_o => pre_trig_value,
fmc_adc_core_post_samples_o => post_trig_value,
fmc_adc_core_samples_cnt_i => std_logic_vector(samples_cnt),
fmc_adc_core_ch1_ctl_ssr_o => gpio_ssr_ch1_o,
fmc_adc_core_ch1_ctl_reserved_o => open,
fmc_adc_core_ch1_sta_val_i => serdes_out_data(15 downto 0),
fmc_adc_core_ch1_sta_reserved_i => (others => '0'),
fmc_adc_core_ch1_gain_val_o => gain_calibr(15 downto 0),
fmc_adc_core_ch1_gain_reserved_o => open,
fmc_adc_core_ch1_offset_val_o => offset_calibr(15 downto 0),
fmc_adc_core_ch1_offset_reserved_o => open,
fmc_adc_core_ch2_ctl_ssr_o => gpio_ssr_ch2_o,
fmc_adc_core_ch2_ctl_reserved_o => open,
fmc_adc_core_ch2_sta_val_i => serdes_out_data(31 downto 16),
fmc_adc_core_ch2_sta_reserved_i => (others => '0'),
fmc_adc_core_ch2_gain_val_o => gain_calibr(31 downto 16),
fmc_adc_core_ch2_gain_reserved_o => open,
fmc_adc_core_ch2_offset_val_o => offset_calibr(31 downto 16),
fmc_adc_core_ch2_offset_reserved_o => open,
fmc_adc_core_ch3_ctl_ssr_o => gpio_ssr_ch3_o,
fmc_adc_core_ch3_ctl_reserved_o => open,
fmc_adc_core_ch3_sta_val_i => serdes_out_data(47 downto 32),
fmc_adc_core_ch3_sta_reserved_i => (others => '0'),
fmc_adc_core_ch3_gain_val_o => gain_calibr(47 downto 32),
fmc_adc_core_ch3_gain_reserved_o => open,
fmc_adc_core_ch3_offset_val_o => offset_calibr(47 downto 32),
fmc_adc_core_ch3_offset_reserved_o => open,
fmc_adc_core_ch4_ctl_ssr_o => gpio_ssr_ch4_o,
fmc_adc_core_ch4_ctl_reserved_o => open,
fmc_adc_core_ch4_sta_val_i => serdes_out_data(63 downto 48),
fmc_adc_core_ch4_sta_reserved_i => (others => '0'),
fmc_adc_core_ch4_gain_val_o => gain_calibr(63 downto 48),
fmc_adc_core_ch4_gain_reserved_o => open,
fmc_adc_core_ch4_offset_val_o => offset_calibr(63 downto 48),
fmc_adc_core_ch4_offset_reserved_o => open
rst_n_i => sys_rst_n_i,
clk_sys_i => sys_clk_i,
wb_adr_i => wb_csr_adr_i,
wb_dat_i => wb_csr_dat_i,
wb_dat_o => wb_csr_dat_o,
wb_cyc_i => wb_csr_cyc_i,
wb_sel_i => wb_csr_sel_i,
wb_stb_i => wb_csr_stb_i,
wb_we_i => wb_csr_we_i,
wb_ack_o => wb_csr_ack_o,
wb_stall_o => open,
fs_clk_i => fs_clk,
fmc_adc_core_ctl_fsm_cmd_o => fsm_cmd,
fmc_adc_core_ctl_fsm_cmd_wr_o => fsm_cmd_wr,
fmc_adc_core_ctl_fmc_clk_oe_o => gpio_si570_oe_o,
fmc_adc_core_ctl_offset_dac_clr_n_o => gpio_dac_clr_n_o,
fmc_adc_core_ctl_man_bitslip_o => serdes_man_bitslip,
fmc_adc_core_ctl_test_data_en_o => test_data_en,
fmc_adc_core_ctl_trig_led_o => trig_led_man,
fmc_adc_core_ctl_acq_led_o => acq_led_man,
fmc_adc_core_ctl_reserved_o => open,
fmc_adc_core_sta_fsm_i => acq_fsm_state,
fmc_adc_core_sta_serdes_pll_i => locked_out,
fmc_adc_core_sta_serdes_synced_i => serdes_synced,
fmc_adc_core_sta_acq_cfg_i => acq_config_ok,
fmc_adc_core_sta_reserved_i => (others => '0'),
fmc_adc_core_trig_cfg_hw_trig_sel_o => hw_trig_sel,
fmc_adc_core_trig_cfg_hw_trig_pol_o => hw_trig_pol,
fmc_adc_core_trig_cfg_hw_trig_en_o => hw_trig_en,
fmc_adc_core_trig_cfg_sw_trig_en_o => sw_trig_en,
fmc_adc_core_trig_cfg_int_trig_sel_o => int_trig_sel,
fmc_adc_core_trig_cfg_int_trig_test_en_o => int_trig_test_en,
fmc_adc_core_trig_cfg_reserved_o => open,
fmc_adc_core_trig_cfg_int_trig_thres_filt_o => int_trig_thres_filt,
fmc_adc_core_trig_cfg_int_trig_thres_o => int_trig_thres,
fmc_adc_core_trig_dly_o => trig_delay,
fmc_adc_core_sw_trig_o => open,
fmc_adc_core_sw_trig_wr_o => sw_trig_t,
fmc_adc_core_shots_nb_o => shots_value,
fmc_adc_core_shots_reserved_o => open,
fmc_adc_core_shots_cnt_val_i => remaining_shots,
fmc_adc_core_shots_cnt_reserved_o => open,
fmc_adc_core_trig_pos_i => trig_addr,
fmc_adc_core_fs_freq_i => fs_freq,
fmc_adc_core_sr_deci_o => decim_factor,
fmc_adc_core_pre_samples_o => pre_trig_value,
fmc_adc_core_post_samples_o => post_trig_value,
fmc_adc_core_samples_cnt_i => std_logic_vector(samples_cnt),
fmc_adc_core_ch1_ctl_ssr_o => gpio_ssr_ch1_o,
fmc_adc_core_ch1_ctl_reserved_o => open,
fmc_adc_core_ch1_sta_val_i => serdes_out_data(15 downto 0),
fmc_adc_core_ch1_sta_reserved_i => (others => '0'),
fmc_adc_core_ch1_gain_val_o => gain_calibr(15 downto 0),
fmc_adc_core_ch1_gain_reserved_o => open,
fmc_adc_core_ch1_offset_val_o => offset_calibr(15 downto 0),
fmc_adc_core_ch1_offset_reserved_o => open,
fmc_adc_core_ch1_sat_val_o => sat_val(14 downto 0),
fmc_adc_core_ch1_sat_reserved_o => open,
fmc_adc_core_ch2_ctl_ssr_o => gpio_ssr_ch2_o,
fmc_adc_core_ch2_ctl_reserved_o => open,
fmc_adc_core_ch2_sta_val_i => serdes_out_data(31 downto 16),
fmc_adc_core_ch2_sta_reserved_i => (others => '0'),
fmc_adc_core_ch2_gain_val_o => gain_calibr(31 downto 16),
fmc_adc_core_ch2_gain_reserved_o => open,
fmc_adc_core_ch2_offset_val_o => offset_calibr(31 downto 16),
fmc_adc_core_ch2_offset_reserved_o => open,
fmc_adc_core_ch2_sat_val_o => sat_val(29 downto 15),
fmc_adc_core_ch2_sat_reserved_o => open,
fmc_adc_core_ch3_ctl_ssr_o => gpio_ssr_ch3_o,
fmc_adc_core_ch3_ctl_reserved_o => open,
fmc_adc_core_ch3_sta_val_i => serdes_out_data(47 downto 32),
fmc_adc_core_ch3_sta_reserved_i => (others => '0'),
fmc_adc_core_ch3_gain_val_o => gain_calibr(47 downto 32),
fmc_adc_core_ch3_gain_reserved_o => open,
fmc_adc_core_ch3_offset_val_o => offset_calibr(47 downto 32),
fmc_adc_core_ch3_offset_reserved_o => open,
fmc_adc_core_ch3_sat_val_o => sat_val(44 downto 30),
fmc_adc_core_ch3_sat_reserved_o => open,
fmc_adc_core_ch4_ctl_ssr_o => gpio_ssr_ch4_o,
fmc_adc_core_ch4_ctl_reserved_o => open,
fmc_adc_core_ch4_sta_val_i => serdes_out_data(63 downto 48),
fmc_adc_core_ch4_sta_reserved_i => (others => '0'),
fmc_adc_core_ch4_gain_val_o => gain_calibr(63 downto 48),
fmc_adc_core_ch4_gain_reserved_o => open,
fmc_adc_core_ch4_offset_val_o => offset_calibr(63 downto 48),
fmc_adc_core_ch4_offset_reserved_o => open,
fmc_adc_core_ch4_sat_val_o => sat_val(59 downto 45),
fmc_adc_core_ch4_sat_reserved_o => open
);
------------------------------------------------------------------------------
......@@ -771,7 +851,16 @@ begin
offset_i => offset_calibr((I+1)*16-1 downto I*16),
gain_i => gain_calibr((I+1)*16-1 downto I*16),
data_i => data_calibr_in((I+1)*16-1 downto I*16),
data_o => data_calibr_out((I+1)*16-1 downto I*16)
data_o => data_calibr_out_t((I+1)*16-1 downto I*16)
);
cmp_var_sat : var_sat_s
port map (
rst_n_i => fs_rst_n,
clk_i => fs_clk,
sat_i => sat_val((I+1)*15-1 downto I*15),
data_i => data_calibr_out_t((I+1)*16-1 downto I*16),
data_o => data_calibr_out((I+1)*16-1 downto I*16)
);
end generate l_offset_gain_calibr;
......@@ -813,25 +902,45 @@ begin
data_calibr_out(63 downto 48) when int_trig_sel = "11" else -- CH4 selected
(others => '0');
-- Detects input data going over the internal trigger threshold
p_int_trig : process (fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
int_trig_over_thres <= '0';
int_trig_over_thres_d <= '0';
data_calibr_out_d <= (others => '0');
int_trig_over_thres <= '0';
elsif rising_edge(fs_clk) then
if signed(int_trig_data) > signed(int_trig_thres) then
int_trig_over_thres <= '1';
else
int_trig_over_thres <= '0';
end if;
int_trig_over_thres_d <= int_trig_over_thres;
data_calibr_out_d <= data_calibr_out; -- delay data to compensate for threshold detection delay
end if;
end process p_int_trig;
int_trig <= int_trig_over_thres and not(int_trig_over_thres_d) when hw_trig_pol = '0' else -- positive slope
not(int_trig_over_thres) and int_trig_over_thres_d; -- negative slope
-- Filters out glitches from over threshold signal (rejects noise around the threshold -> hysteresis)
cmp_dyn_glitch_filt : gc_dyn_glitch_filt
generic map(
g_len_width => 8
)
port map(
clk_i => fs_clk,
rst_n_i => fs_rst_n,
len_i => int_trig_thres_filt(7 downto 0),
dat_i => int_trig_over_thres,
dat_o => int_trig_over_thres_filt
);
-- Detects whether it's a positive or negative slope
p_int_trig_slope : process (fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
int_trig_over_thres_filt_d <= '0';
elsif rising_edge(fs_clk) then
int_trig_over_thres_filt_d <= int_trig_over_thres_filt;
end if;
end process;
int_trig <= int_trig_over_thres_filt and not(int_trig_over_thres_filt_d) when hw_trig_pol = '0' else -- positive slope
not(int_trig_over_thres_filt) and int_trig_over_thres_filt_d; -- negative slope
-- Hardware trigger selection
-- internal = adc data threshold
......@@ -972,8 +1081,28 @@ begin
end if;
end process;
-- Internal trigger test mode
int_trig_over_thres_tst <= X"1000" when int_trig_over_thres = '1' else X"0000";
int_trig_over_thres_filt_tst <= X"1000" when int_trig_over_thres_filt = '1' else X"0000";
trig_tst <= X"1000" when trig_align = '1' else X"0000";
-- Delay data to compoensate for internal trigger detection
p_data_delay : process (fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
data_calibr_out_d <= (others => (others => '0'));
elsif rising_edge(fs_clk) then
data_calibr_out_d <= data_calibr_out_d(data_calibr_out_d'left-1 downto 0) & data_calibr_out;
end if;
end process p_data_delay;
-- An additional 1 fs_clk period delay is added when internal hw trigger is selected
sync_fifo_din <= trig_align & data_calibr_out_d when hw_trig_sel = '0' else trig_align & data_calibr_out;
sync_fifo_din <= (trig_align &
trig_tst & int_trig_over_thres_filt_tst &
int_trig_over_thres_tst &
data_calibr_out_d(3)(15 downto 0)) when int_trig_test_en = '1' else
(trig_align & data_calibr_out_d(3)) when hw_trig_sel = '0' else
(trig_align & data_calibr_out);
-- FOR DEBUG: FR instead of CH1 and SerDes Synced instead of CH2
--sync_fifo_din <= trig_align & serdes_out_data(63 downto 32) &
......@@ -1012,6 +1141,7 @@ begin
multishot_buffer_sel <= std_logic(shots_cnt(0));
shots_done <= '1' when shots_cnt = to_unsigned(1, shots_cnt'length) else '0';
remaining_shots <= std_logic_vector(shots_cnt);
------------------------------------------------------------------------------
-- Pre-trigger counter
......@@ -1104,10 +1234,11 @@ begin
-- Check acquisition configuration
-- Post-trigger sample must be > 0
-- Shot number must be > 0
acq_config_ok <= '0' when
unsigned(post_trig_value) = to_unsigned(0, post_trig_value'length) and
unsigned(shots_value) = to_unsigned(0, shots_value'length)
else '1';
-- Number of sample (+time-tag) in multi-shot must be < multi-shot ram size
acq_config_ok <= '0' when (unsigned(post_trig_value) = to_unsigned(0, post_trig_value'length)) else
'0' when (unsigned(shots_value) = to_unsigned(0, shots_value'length)) else
'0' when (unsigned(pre_trig_value)+unsigned(post_trig_value)+4 > to_unsigned(g_multishot_ram_size, pre_trig_value'length) and single_shot = '0') else
'1';
-- FSM transitions
p_acq_fsm_transitions : process(sys_clk_i, sys_rst_n_i)
......
hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
View file @ 267af46a
......@@ -61,7 +61,7 @@ package fmc_adc_100Ms_core_pkg is
sys_rst_n_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(4 downto 0);
wb_csr_adr_i : in std_logic_vector(5 downto 0);
wb_csr_dat_i : in std_logic_vector(31 downto 0);
wb_csr_dat_o : out std_logic_vector(31 downto 0);
wb_csr_cyc_i : in std_logic;
......
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @ 267af46a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Tue Dec 17 09:57:20 2013
-- Created : Wed Mar 19 16:50:21 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -18,7 +18,7 @@ entity fmc_adc_100Ms_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -65,8 +65,12 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_trig_cfg_sw_trig_en_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel selection for internal trigger' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_int_trig_sel_o : out std_logic_vector(1 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_reserved_o : out std_logic_vector(9 downto 0);
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Enable internal trigger test mode' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_int_trig_test_en_o : out std_logic;
-- Port for BIT field: 'Reserved' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_reserved_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Internal trigger threshold glitch filter' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_int_trig_thres_filt_o : out std_logic_vector(7 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Threshold for internal trigger' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_int_trig_thres_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Trigger delay value' in reg: 'Trigger delay'
......@@ -78,8 +82,14 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_shots_nb_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Number of shots'
fmc_adc_core_shots_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Remaining shots counter' in reg: 'Remaining shots counter'
fmc_adc_core_shots_cnt_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Remaining shots counter'
fmc_adc_core_shots_cnt_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Trigger address' in reg: 'Trigger address register'
fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Sampling clock frequency' in reg: 'Sampling clock frequency'
fmc_adc_core_fs_freq_i : in std_logic_vector(31 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Sample rate decimation' in reg: 'Sample rate'
fmc_adc_core_sr_deci_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Pre-trigger samples' in reg: 'Pre-trigger samples'
......@@ -104,6 +114,10 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_ch1_offset_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 1 offset calibration register'
fmc_adc_core_ch1_offset_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Saturation value for channel 1' in reg: 'Channel 1 saturation register'
fmc_adc_core_ch1_sat_val_o : out std_logic_vector(14 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 1 saturation register'
fmc_adc_core_ch1_sat_reserved_o : out std_logic_vector(16 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 2' in reg: 'Channel 2 control register'
fmc_adc_core_ch2_ctl_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 2 control register'
......@@ -120,6 +134,10 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_ch2_offset_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 2 offset calibration register'
fmc_adc_core_ch2_offset_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Saturation value for channel 2' in reg: 'Channel 2 saturation register'
fmc_adc_core_ch2_sat_val_o : out std_logic_vector(14 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 2 saturation register'
fmc_adc_core_ch2_sat_reserved_o : out std_logic_vector(16 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 3' in reg: 'Channel 3 control register'
fmc_adc_core_ch3_ctl_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 3 control register'
......@@ -136,6 +154,10 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_ch3_offset_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 3 offset calibration register'
fmc_adc_core_ch3_offset_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Saturation value for channel 3' in reg: 'Channel 3 saturation register'
fmc_adc_core_ch3_sat_val_o : out std_logic_vector(14 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 3 saturation register'
fmc_adc_core_ch3_sat_reserved_o : out std_logic_vector(16 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 4' in reg: 'Channel 4 control register'
fmc_adc_core_ch4_ctl_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 4 control register'
......@@ -151,7 +173,11 @@ entity fmc_adc_100Ms_csr is
-- Port for std_logic_vector field: 'Offset calibration for channel 4' in reg: 'Channel 4 offset calibration register'
fmc_adc_core_ch4_offset_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 4 offset calibration register'
fmc_adc_core_ch4_offset_reserved_o : out std_logic_vector(15 downto 0)
fmc_adc_core_ch4_offset_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Saturation value for channel 4' in reg: 'Channel 4 saturation register'
fmc_adc_core_ch4_sat_val_o : out std_logic_vector(14 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 4 saturation register'
fmc_adc_core_ch4_sat_reserved_o : out std_logic_vector(16 downto 0)
);
end fmc_adc_100Ms_csr;
......@@ -186,7 +212,16 @@ signal fmc_adc_core_trig_cfg_int_trig_sel_swb_delay : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_sel_swb_s0 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_sel_swb_s1 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_sel_swb_s2 : std_logic ;
signal fmc_adc_core_trig_cfg_reserved_int : std_logic_vector(9 downto 0);
signal fmc_adc_core_trig_cfg_int_trig_test_en_int : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_test_en_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_test_en_sync1 : std_logic ;
signal fmc_adc_core_trig_cfg_reserved_int : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_thres_filt_int : std_logic_vector(7 downto 0);
signal fmc_adc_core_trig_cfg_int_trig_thres_filt_swb : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_delay : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s0 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s1 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s2 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_thres_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_trig_cfg_int_trig_thres_swb : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_thres_swb_delay : std_logic ;
......@@ -201,6 +236,14 @@ signal fmc_adc_core_sw_trig_wr_sync1 : std_logic ;
signal fmc_adc_core_sw_trig_wr_sync2 : std_logic ;
signal fmc_adc_core_shots_nb_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_shots_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_shots_cnt_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_fs_freq_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_fs_freq_lwb : std_logic ;
signal fmc_adc_core_fs_freq_lwb_delay : std_logic ;
signal fmc_adc_core_fs_freq_lwb_in_progress : std_logic ;
signal fmc_adc_core_fs_freq_lwb_s0 : std_logic ;
signal fmc_adc_core_fs_freq_lwb_s1 : std_logic ;
signal fmc_adc_core_fs_freq_lwb_s2 : std_logic ;
signal fmc_adc_core_sr_deci_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_sr_deci_swb : std_logic ;
signal fmc_adc_core_sr_deci_swb_delay : std_logic ;
......@@ -222,6 +265,8 @@ signal fmc_adc_core_ch1_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_gain_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_offset_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_core_ch1_sat_reserved_int : std_logic_vector(16 downto 0);
signal fmc_adc_core_ch2_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch2_ctl_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch2_sta_val_int : std_logic_vector(15 downto 0);
......@@ -235,6 +280,8 @@ signal fmc_adc_core_ch2_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_gain_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_offset_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_core_ch2_sat_reserved_int : std_logic_vector(16 downto 0);
signal fmc_adc_core_ch3_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch3_ctl_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch3_sta_val_int : std_logic_vector(15 downto 0);
......@@ -248,6 +295,8 @@ signal fmc_adc_core_ch3_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_gain_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_offset_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_core_ch3_sat_reserved_int : std_logic_vector(16 downto 0);
signal fmc_adc_core_ch4_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch4_ctl_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch4_sta_val_int : std_logic_vector(15 downto 0);
......@@ -261,11 +310,13 @@ signal fmc_adc_core_ch4_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_gain_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_offset_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_core_ch4_sat_reserved_int : std_logic_vector(16 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal rwaddr_reg : std_logic_vector(5 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -304,7 +355,11 @@ begin
fmc_adc_core_trig_cfg_int_trig_sel_int <= "00";
fmc_adc_core_trig_cfg_int_trig_sel_swb <= '0';
fmc_adc_core_trig_cfg_int_trig_sel_swb_delay <= '0';
fmc_adc_core_trig_cfg_reserved_int <= "0000000000";
fmc_adc_core_trig_cfg_int_trig_test_en_int <= '0';
fmc_adc_core_trig_cfg_reserved_int <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_filt_int <= "00000000";
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_int <= "0000000000000000";
fmc_adc_core_trig_cfg_int_trig_thres_swb <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_swb_delay <= '0';
......@@ -313,6 +368,10 @@ begin
fmc_adc_core_sw_trig_wr_int_delay <= '0';
fmc_adc_core_shots_nb_int <= "0000000000000000";
fmc_adc_core_shots_reserved_int <= "0000000000000000";
fmc_adc_core_shots_cnt_reserved_int <= "0000000000000000";
fmc_adc_core_fs_freq_lwb <= '0';
fmc_adc_core_fs_freq_lwb_delay <= '0';
fmc_adc_core_fs_freq_lwb_in_progress <= '0';
fmc_adc_core_sr_deci_int <= "00000000000000000000000000000000";
fmc_adc_core_sr_deci_swb <= '0';
fmc_adc_core_sr_deci_swb_delay <= '0';
......@@ -327,6 +386,8 @@ begin
fmc_adc_core_ch1_gain_reserved_int <= "0000000000000000";
fmc_adc_core_ch1_offset_val_int <= "0000000000000000";
fmc_adc_core_ch1_offset_reserved_int <= "0000000000000000";
fmc_adc_core_ch1_sat_val_int <= "000000000000000";
fmc_adc_core_ch1_sat_reserved_int <= "00000000000000000";
fmc_adc_core_ch2_ctl_ssr_int <= "0000000";
fmc_adc_core_ch2_ctl_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch2_sta_val_lwb <= '0';
......@@ -336,6 +397,8 @@ begin
fmc_adc_core_ch2_gain_reserved_int <= "0000000000000000";
fmc_adc_core_ch2_offset_val_int <= "0000000000000000";
fmc_adc_core_ch2_offset_reserved_int <= "0000000000000000";
fmc_adc_core_ch2_sat_val_int <= "000000000000000";
fmc_adc_core_ch2_sat_reserved_int <= "00000000000000000";
fmc_adc_core_ch3_ctl_ssr_int <= "0000000";
fmc_adc_core_ch3_ctl_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch3_sta_val_lwb <= '0';
......@@ -345,6 +408,8 @@ begin
fmc_adc_core_ch3_gain_reserved_int <= "0000000000000000";
fmc_adc_core_ch3_offset_val_int <= "0000000000000000";
fmc_adc_core_ch3_offset_reserved_int <= "0000000000000000";
fmc_adc_core_ch3_sat_val_int <= "000000000000000";
fmc_adc_core_ch3_sat_reserved_int <= "00000000000000000";
fmc_adc_core_ch4_ctl_ssr_int <= "0000000";
fmc_adc_core_ch4_ctl_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch4_sta_val_lwb <= '0';
......@@ -354,6 +419,8 @@ begin
fmc_adc_core_ch4_gain_reserved_int <= "0000000000000000";
fmc_adc_core_ch4_offset_val_int <= "0000000000000000";
fmc_adc_core_ch4_offset_reserved_int <= "0000000000000000";
fmc_adc_core_ch4_sat_val_int <= "000000000000000";
fmc_adc_core_ch4_sat_reserved_int <= "00000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -368,10 +435,18 @@ begin
fmc_adc_core_ctl_man_bitslip_int_delay <= '0';
fmc_adc_core_trig_cfg_int_trig_sel_swb <= fmc_adc_core_trig_cfg_int_trig_sel_swb_delay;
fmc_adc_core_trig_cfg_int_trig_sel_swb_delay <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb <= fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_delay;
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_swb <= fmc_adc_core_trig_cfg_int_trig_thres_swb_delay;
fmc_adc_core_trig_cfg_int_trig_thres_swb_delay <= '0';
fmc_adc_core_sw_trig_wr_int <= fmc_adc_core_sw_trig_wr_int_delay;
fmc_adc_core_sw_trig_wr_int_delay <= '0';
fmc_adc_core_fs_freq_lwb <= fmc_adc_core_fs_freq_lwb_delay;
fmc_adc_core_fs_freq_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_fs_freq_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= fmc_adc_core_fs_freq_int;
fmc_adc_core_fs_freq_lwb_in_progress <= '0';
end if;
fmc_adc_core_sr_deci_swb <= fmc_adc_core_sr_deci_swb_delay;
fmc_adc_core_sr_deci_swb_delay <= '0';
fmc_adc_core_ch1_sta_val_lwb <= fmc_adc_core_ch1_sta_val_lwb_delay;
......@@ -401,8 +476,8 @@ begin
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
case rwaddr_reg(5 downto 0) is
when "000000" =>
if (wb_we_i = '1') then
fmc_adc_core_ctl_fsm_cmd_wr_o <= '1';
fmc_adc_core_ctl_fmc_clk_oe_int <= wrdata_reg(2);
......@@ -425,7 +500,7 @@ begin
rddata_reg(1) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "00001" =>
when "000001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(2 downto 0) <= fmc_adc_core_sta_fsm_i;
......@@ -435,7 +510,7 @@ begin
rddata_reg(31 downto 6) <= fmc_adc_core_sta_reserved_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
when "000010" =>
if (wb_we_i = '1') then
fmc_adc_core_trig_cfg_hw_trig_sel_int <= wrdata_reg(0);
fmc_adc_core_trig_cfg_hw_trig_pol_int <= wrdata_reg(1);
......@@ -444,7 +519,11 @@ begin
fmc_adc_core_trig_cfg_int_trig_sel_int <= wrdata_reg(5 downto 4);
fmc_adc_core_trig_cfg_int_trig_sel_swb <= '1';
fmc_adc_core_trig_cfg_int_trig_sel_swb_delay <= '1';
fmc_adc_core_trig_cfg_reserved_int <= wrdata_reg(15 downto 6);
fmc_adc_core_trig_cfg_int_trig_test_en_int <= wrdata_reg(6);
fmc_adc_core_trig_cfg_reserved_int <= wrdata_reg(7);
fmc_adc_core_trig_cfg_int_trig_thres_filt_int <= wrdata_reg(15 downto 8);
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb <= '1';
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_delay <= '1';
fmc_adc_core_trig_cfg_int_trig_thres_int <= wrdata_reg(31 downto 16);
fmc_adc_core_trig_cfg_int_trig_thres_swb <= '1';
fmc_adc_core_trig_cfg_int_trig_thres_swb_delay <= '1';
......@@ -454,18 +533,20 @@ begin
rddata_reg(2) <= fmc_adc_core_trig_cfg_hw_trig_en_int;
rddata_reg(3) <= fmc_adc_core_trig_cfg_sw_trig_en_int;
rddata_reg(5 downto 4) <= fmc_adc_core_trig_cfg_int_trig_sel_int;
rddata_reg(15 downto 6) <= fmc_adc_core_trig_cfg_reserved_int;
rddata_reg(6) <= fmc_adc_core_trig_cfg_int_trig_test_en_int;
rddata_reg(7) <= fmc_adc_core_trig_cfg_reserved_int;
rddata_reg(15 downto 8) <= fmc_adc_core_trig_cfg_int_trig_thres_filt_int;
rddata_reg(31 downto 16) <= fmc_adc_core_trig_cfg_int_trig_thres_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "00011" =>
when "000011" =>
if (wb_we_i = '1') then
fmc_adc_core_trig_dly_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fmc_adc_core_trig_dly_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
when "000100" =>
if (wb_we_i = '1') then
fmc_adc_core_sw_trig_wr_int <= '1';
fmc_adc_core_sw_trig_wr_int_delay <= '1';
......@@ -504,7 +585,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "00101" =>
when "000101" =>
if (wb_we_i = '1') then
fmc_adc_core_shots_nb_int <= wrdata_reg(15 downto 0);
fmc_adc_core_shots_reserved_int <= wrdata_reg(31 downto 16);
......@@ -513,13 +594,31 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_core_shots_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
when "000110" =>
if (wb_we_i = '1') then
fmc_adc_core_shots_cnt_reserved_int <= wrdata_reg(31 downto 16);
end if;
rddata_reg(15 downto 0) <= fmc_adc_core_shots_cnt_val_i;
rddata_reg(31 downto 16) <= fmc_adc_core_shots_cnt_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= fmc_adc_core_trig_pos_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
when "001000" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
fmc_adc_core_fs_freq_lwb <= '1';
fmc_adc_core_fs_freq_lwb_delay <= '1';
fmc_adc_core_fs_freq_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "001001" =>
if (wb_we_i = '1') then
fmc_adc_core_sr_deci_int <= wrdata_reg(31 downto 0);
fmc_adc_core_sr_deci_swb <= '1';
......@@ -528,27 +627,27 @@ begin
rddata_reg(31 downto 0) <= fmc_adc_core_sr_deci_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "01000" =>
when "001010" =>
if (wb_we_i = '1') then
fmc_adc_core_pre_samples_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fmc_adc_core_pre_samples_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
when "001011" =>
if (wb_we_i = '1') then
fmc_adc_core_post_samples_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fmc_adc_core_post_samples_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
when "001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= fmc_adc_core_samples_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
when "001101" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch1_ctl_reserved_int <= wrdata_reg(31 downto 7);
......@@ -557,7 +656,7 @@ begin
rddata_reg(31 downto 7) <= fmc_adc_core_ch1_ctl_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
when "001110" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
......@@ -568,7 +667,7 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_core_ch1_sta_reserved_i;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "01101" =>
when "001111" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch1_gain_reserved_int <= wrdata_reg(31 downto 16);
......@@ -577,7 +676,7 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_core_ch1_gain_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
when "010000" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_offset_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch1_offset_reserved_int <= wrdata_reg(31 downto 16);
......@@ -586,7 +685,16 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_core_ch1_offset_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
when "010001" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_sat_val_int <= wrdata_reg(14 downto 0);
fmc_adc_core_ch1_sat_reserved_int <= wrdata_reg(31 downto 15);
end if;
rddata_reg(14 downto 0) <= fmc_adc_core_ch1_sat_val_int;
rddata_reg(31 downto 15) <= fmc_adc_core_ch1_sat_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010010" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch2_ctl_reserved_int <= wrdata_reg(31 downto 7);
......@@ -595,7 +703,7 @@ begin
rddata_reg(31 downto 7) <= fmc_adc_core_ch2_ctl_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
when "010011" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
......@@ -606,7 +714,7 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_core_ch2_sta_reserved_i;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10001" =>
when "010100" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch2_gain_reserved_int <= wrdata_reg(31 downto 16);
......@@ -615,7 +723,7 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_core_ch2_gain_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
when "010101" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_offset_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch2_offset_reserved_int <= wrdata_reg(31 downto 16);
......@@ -624,7 +732,16 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_core_ch2_offset_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011" =>
when "010110" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_sat_val_int <= wrdata_reg(14 downto 0);
fmc_adc_core_ch2_sat_reserved_int <= wrdata_reg(31 downto 15);
end if;
rddata_reg(14 downto 0) <= fmc_adc_core_ch2_sat_val_int;
rddata_reg(31 downto 15) <= fmc_adc_core_ch2_sat_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010111" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch3_ctl_reserved_int <= wrdata_reg(31 downto 7);
......@@ -633,7 +750,7 @@ begin
rddata_reg(31 downto 7) <= fmc_adc_core_ch3_ctl_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100" =>
when "011000" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
......@@ -644,7 +761,7 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_core_ch3_sta_reserved_i;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10101" =>
when "011001" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch3_gain_reserved_int <= wrdata_reg(31 downto 16);
......@@ -653,7 +770,7 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_core_ch3_gain_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10110" =>
when "011010" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_offset_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch3_offset_reserved_int <= wrdata_reg(31 downto 16);
......@@ -662,7 +779,16 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_core_ch3_offset_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10111" =>
when "011011" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_sat_val_int <= wrdata_reg(14 downto 0);
fmc_adc_core_ch3_sat_reserved_int <= wrdata_reg(31 downto 15);
end if;
rddata_reg(14 downto 0) <= fmc_adc_core_ch3_sat_val_int;
rddata_reg(31 downto 15) <= fmc_adc_core_ch3_sat_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011100" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch4_ctl_reserved_int <= wrdata_reg(31 downto 7);
......@@ -671,7 +797,7 @@ begin
rddata_reg(31 downto 7) <= fmc_adc_core_ch4_ctl_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11000" =>
when "011101" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
......@@ -682,7 +808,7 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_core_ch4_sta_reserved_i;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "11001" =>
when "011110" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch4_gain_reserved_int <= wrdata_reg(31 downto 16);
......@@ -691,7 +817,7 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_core_ch4_gain_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11010" =>
when "011111" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_offset_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch4_offset_reserved_int <= wrdata_reg(31 downto 16);
......@@ -700,6 +826,15 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_core_ch4_offset_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100000" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_sat_val_int <= wrdata_reg(14 downto 0);
fmc_adc_core_ch4_sat_reserved_int <= wrdata_reg(31 downto 15);
end if;
rddata_reg(14 downto 0) <= fmc_adc_core_ch4_sat_val_int;
rddata_reg(31 downto 15) <= fmc_adc_core_ch4_sat_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -834,8 +969,44 @@ begin
end process;
-- Enable internal trigger test mode
-- synchronizer chain for field : Enable internal trigger test mode (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_trig_cfg_int_trig_test_en_o <= '0';
fmc_adc_core_trig_cfg_int_trig_test_en_sync0 <= '0';
fmc_adc_core_trig_cfg_int_trig_test_en_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_core_trig_cfg_int_trig_test_en_sync0 <= fmc_adc_core_trig_cfg_int_trig_test_en_int;
fmc_adc_core_trig_cfg_int_trig_test_en_sync1 <= fmc_adc_core_trig_cfg_int_trig_test_en_sync0;
fmc_adc_core_trig_cfg_int_trig_test_en_o <= fmc_adc_core_trig_cfg_int_trig_test_en_sync1;
end if;
end process;
-- Reserved
fmc_adc_core_trig_cfg_reserved_o <= fmc_adc_core_trig_cfg_reserved_int;
-- Internal trigger threshold glitch filter
-- asynchronous std_logic_vector register : Internal trigger threshold glitch filter (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s0 <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s1 <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s2 <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_filt_o <= "00000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s0 <= fmc_adc_core_trig_cfg_int_trig_thres_filt_swb;
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s1 <= fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s0;
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s2 <= fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s1;
if ((fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s2 = '0') and (fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_s1 = '1')) then
fmc_adc_core_trig_cfg_int_trig_thres_filt_o <= fmc_adc_core_trig_cfg_int_trig_thres_filt_int;
end if;
end if;
end process;
-- Threshold for internal trigger
-- asynchronous std_logic_vector register : Threshold for internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
......@@ -880,7 +1051,30 @@ begin
fmc_adc_core_shots_nb_o <= fmc_adc_core_shots_nb_int;
-- Reserved
fmc_adc_core_shots_reserved_o <= fmc_adc_core_shots_reserved_int;
-- Remaining shots counter
-- Reserved
fmc_adc_core_shots_cnt_reserved_o <= fmc_adc_core_shots_cnt_reserved_int;
-- Trigger address
-- Sampling clock frequency
-- asynchronous std_logic_vector register : Sampling clock frequency (type RO/WO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_fs_freq_lwb_s0 <= '0';
fmc_adc_core_fs_freq_lwb_s1 <= '0';
fmc_adc_core_fs_freq_lwb_s2 <= '0';
fmc_adc_core_fs_freq_int <= "00000000000000000000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_fs_freq_lwb_s0 <= fmc_adc_core_fs_freq_lwb;
fmc_adc_core_fs_freq_lwb_s1 <= fmc_adc_core_fs_freq_lwb_s0;
fmc_adc_core_fs_freq_lwb_s2 <= fmc_adc_core_fs_freq_lwb_s1;
if ((fmc_adc_core_fs_freq_lwb_s1 = '1') and (fmc_adc_core_fs_freq_lwb_s2 = '0')) then
fmc_adc_core_fs_freq_int <= fmc_adc_core_fs_freq_i;
end if;
end if;
end process;
-- Sample rate decimation
-- asynchronous std_logic_vector register : Sample rate decimation (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
......@@ -939,6 +1133,10 @@ begin
fmc_adc_core_ch1_offset_val_o <= fmc_adc_core_ch1_offset_val_int;
-- Reserved
fmc_adc_core_ch1_offset_reserved_o <= fmc_adc_core_ch1_offset_reserved_int;
-- Saturation value for channel 1
fmc_adc_core_ch1_sat_val_o <= fmc_adc_core_ch1_sat_val_int;
-- Reserved
fmc_adc_core_ch1_sat_reserved_o <= fmc_adc_core_ch1_sat_reserved_int;
-- Solid state relays control for channel 2
fmc_adc_core_ch2_ctl_ssr_o <= fmc_adc_core_ch2_ctl_ssr_int;
-- Reserved
......@@ -972,6 +1170,10 @@ begin
fmc_adc_core_ch2_offset_val_o <= fmc_adc_core_ch2_offset_val_int;
-- Reserved
fmc_adc_core_ch2_offset_reserved_o <= fmc_adc_core_ch2_offset_reserved_int;
-- Saturation value for channel 2
fmc_adc_core_ch2_sat_val_o <= fmc_adc_core_ch2_sat_val_int;
-- Reserved
fmc_adc_core_ch2_sat_reserved_o <= fmc_adc_core_ch2_sat_reserved_int;
-- Solid state relays control for channel 3
fmc_adc_core_ch3_ctl_ssr_o <= fmc_adc_core_ch3_ctl_ssr_int;
-- Reserved
......@@ -1005,6 +1207,10 @@ begin
fmc_adc_core_ch3_offset_val_o <= fmc_adc_core_ch3_offset_val_int;
-- Reserved
fmc_adc_core_ch3_offset_reserved_o <= fmc_adc_core_ch3_offset_reserved_int;
-- Saturation value for channel 3
fmc_adc_core_ch3_sat_val_o <= fmc_adc_core_ch3_sat_val_int;
-- Reserved
fmc_adc_core_ch3_sat_reserved_o <= fmc_adc_core_ch3_sat_reserved_int;
-- Solid state relays control for channel 4
fmc_adc_core_ch4_ctl_ssr_o <= fmc_adc_core_ch4_ctl_ssr_int;
-- Reserved
......@@ -1038,6 +1244,10 @@ begin
fmc_adc_core_ch4_offset_val_o <= fmc_adc_core_ch4_offset_val_int;
-- Reserved
fmc_adc_core_ch4_offset_reserved_o <= fmc_adc_core_ch4_offset_reserved_int;
-- Saturation value for channel 4
fmc_adc_core_ch4_sat_val_o <= fmc_adc_core_ch4_sat_val_int;
-- Reserved
fmc_adc_core_ch4_sat_reserved_o <= fmc_adc_core_ch4_sat_reserved_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
hdl/adc/rtl/fmc_adc_mezzanine.vhd
View file @ 267af46a
......@@ -183,7 +183,7 @@ architecture rtl of fmc_adc_mezzanine is
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000007F",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000608",
......@@ -447,7 +447,7 @@ begin
sys_clk_i => sys_clk_i,
sys_rst_n_i => sys_rst_n_i,
wb_csr_adr_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_csr_adr_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).adr(7 downto 2), -- cnx_master_out.adr is byte address
wb_csr_dat_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).dat,
wb_csr_dat_o => cnx_master_in(c_WB_SLAVE_FMC_ADC).dat,
wb_csr_cyc_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).cyc,
......
hdl/adc/rtl/var_sat_s.vhd 0 → 100644
View file @ 267af46a
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Variable saturation, signed data input and output (two's complement)
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: var_sat_s (var_sat_s.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 14-03-2013
--
-- version: 1.0
--
-- description: Variable saturation.
-- Latency = 1
--
-- ________
-- | |
-- data_i ---->|saturate|--> data_o
-- |________|
-- ^
-- |
-- sat_i
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
------------------------------------------------------------------------------
-- Entity declaration
------------------------------------------------------------------------------
entity var_sat_s is
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
sat_i : in std_logic_vector(14 downto 0); --! Unsigned saturation value input
data_i : in std_logic_vector(15 downto 0); --! Signed data input (two's complement)
data_o : out std_logic_vector(15 downto 0) --! Signed data output (two's complement)
);
end entity var_sat_s;
------------------------------------------------------------------------------
-- Architecture declaration
------------------------------------------------------------------------------
architecture rtl of var_sat_s is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_one : signed(15 downto 0) := X"0001";
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal pos_sat : signed(15 downto 0);
signal neg_sat : signed(15 downto 0);
begin
pos_sat <= signed('0' & sat_i);
neg_sat <= signed(not('0' & sat_i))+c_one;
------------------------------------------------------------------------------
-- Saturate
------------------------------------------------------------------------------
p_saturate : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
data_o <= (others => '0');
elsif signed(data_i) >= pos_sat then
data_o <= std_logic_vector(pos_sat); -- saturate positive
elsif signed(data_i) <= neg_sat then
data_o <= std_logic_vector(neg_sat); -- saturate negative
else
data_o <= data_i;
end if;
end if;
end process p_saturate;
end architecture rtl;
hdl/adc/wb_gen/Makefile
View file @ 267af46a
WBGEN2=~/projects/wbgen2/wbgen2
RTL=../rtl/
TEX=../../../documentation/manuals/firmware/
TEX=../../../documentation/manuals/gateware/
fmc_adc_100Ms_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @ 267af46a
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Tue Dec 17 09:57:20 2013
* Created : Wed Mar 19 16:50:21 2014
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -106,11 +106,17 @@
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_W(value) WBGEN2_GEN_WRITE(value, 4, 2)
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 4, 2)
/* definitions for field: Enable internal trigger test mode in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_TEST_EN WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Reserved in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_RESERVED_MASK WBGEN2_GEN_MASK(6, 10)
#define FMC_ADC_CORE_TRIG_CFG_RESERVED_SHIFT 6
#define FMC_ADC_CORE_TRIG_CFG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 6, 10)
#define FMC_ADC_CORE_TRIG_CFG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 6, 10)
#define FMC_ADC_CORE_TRIG_CFG_RESERVED WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Internal trigger threshold glitch filter in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_THRES_FILT_MASK WBGEN2_GEN_MASK(8, 8)
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_THRES_FILT_SHIFT 8
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_THRES_FILT_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_THRES_FILT_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: Threshold for internal trigger in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_THRES_MASK WBGEN2_GEN_MASK(16, 16)
......@@ -136,8 +142,24 @@
#define FMC_ADC_CORE_SHOTS_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_SHOTS_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Remaining shots counter */
/* definitions for field: Remaining shots counter in reg: Remaining shots counter */
#define FMC_ADC_CORE_SHOTS_CNT_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_SHOTS_CNT_VAL_SHIFT 0
#define FMC_ADC_CORE_SHOTS_CNT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_SHOTS_CNT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Remaining shots counter */
#define FMC_ADC_CORE_SHOTS_CNT_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_SHOTS_CNT_RESERVED_SHIFT 16
#define FMC_ADC_CORE_SHOTS_CNT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_SHOTS_CNT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Trigger address register */
/* definitions for register: Sampling clock frequency */
/* definitions for register: Sample rate */
/* definitions for field: Sample rate decimation in reg: Sample rate */
......@@ -208,6 +230,20 @@
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 1 saturation register */
/* definitions for field: Saturation value for channel 1 in reg: Channel 1 saturation register */
#define FMC_ADC_CORE_CH1_SAT_VAL_MASK WBGEN2_GEN_MASK(0, 15)
#define FMC_ADC_CORE_CH1_SAT_VAL_SHIFT 0
#define FMC_ADC_CORE_CH1_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_CORE_CH1_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for field: Reserved in reg: Channel 1 saturation register */
#define FMC_ADC_CORE_CH1_SAT_RESERVED_MASK WBGEN2_GEN_MASK(15, 17)
#define FMC_ADC_CORE_CH1_SAT_RESERVED_SHIFT 15
#define FMC_ADC_CORE_CH1_SAT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 15, 17)
#define FMC_ADC_CORE_CH1_SAT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 15, 17)
/* definitions for register: Channel 2 control register */
/* definitions for field: Solid state relays control for channel 2 in reg: Channel 2 control register */
......@@ -264,6 +300,20 @@
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 2 saturation register */
/* definitions for field: Saturation value for channel 2 in reg: Channel 2 saturation register */
#define FMC_ADC_CORE_CH2_SAT_VAL_MASK WBGEN2_GEN_MASK(0, 15)
#define FMC_ADC_CORE_CH2_SAT_VAL_SHIFT 0
#define FMC_ADC_CORE_CH2_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_CORE_CH2_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for field: Reserved in reg: Channel 2 saturation register */
#define FMC_ADC_CORE_CH2_SAT_RESERVED_MASK WBGEN2_GEN_MASK(15, 17)
#define FMC_ADC_CORE_CH2_SAT_RESERVED_SHIFT 15
#define FMC_ADC_CORE_CH2_SAT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 15, 17)
#define FMC_ADC_CORE_CH2_SAT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 15, 17)
/* definitions for register: Channel 3 control register */
/* definitions for field: Solid state relays control for channel 3 in reg: Channel 3 control register */
......@@ -320,6 +370,20 @@
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 3 saturation register */
/* definitions for field: Saturation value for channel 3 in reg: Channel 3 saturation register */
#define FMC_ADC_CORE_CH3_SAT_VAL_MASK WBGEN2_GEN_MASK(0, 15)
#define FMC_ADC_CORE_CH3_SAT_VAL_SHIFT 0
#define FMC_ADC_CORE_CH3_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_CORE_CH3_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for field: Reserved in reg: Channel 3 saturation register */
#define FMC_ADC_CORE_CH3_SAT_RESERVED_MASK WBGEN2_GEN_MASK(15, 17)
#define FMC_ADC_CORE_CH3_SAT_RESERVED_SHIFT 15
#define FMC_ADC_CORE_CH3_SAT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 15, 17)
#define FMC_ADC_CORE_CH3_SAT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 15, 17)
/* definitions for register: Channel 4 control register */
/* definitions for field: Solid state relays control for channel 4 in reg: Channel 4 control register */
......@@ -376,6 +440,20 @@
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 4 saturation register */
/* definitions for field: Saturation value for channel 4 in reg: Channel 4 saturation register */
#define FMC_ADC_CORE_CH4_SAT_VAL_MASK WBGEN2_GEN_MASK(0, 15)
#define FMC_ADC_CORE_CH4_SAT_VAL_SHIFT 0
#define FMC_ADC_CORE_CH4_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_CORE_CH4_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for field: Reserved in reg: Channel 4 saturation register */
#define FMC_ADC_CORE_CH4_SAT_RESERVED_MASK WBGEN2_GEN_MASK(15, 17)
#define FMC_ADC_CORE_CH4_SAT_RESERVED_SHIFT 15
#define FMC_ADC_CORE_CH4_SAT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 15, 17)
#define FMC_ADC_CORE_CH4_SAT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 15, 17)
PACKED struct FMC_ADC_CORE_WB {
/* [0x0]: REG Control register */
uint32_t CTL;
......@@ -389,48 +467,60 @@ PACKED struct FMC_ADC_CORE_WB {
uint32_t SW_TRIG;
/* [0x14]: REG Number of shots */
uint32_t SHOTS;
/* [0x18]: REG Trigger address register */
/* [0x18]: REG Remaining shots counter */
uint32_t SHOTS_CNT;
/* [0x1c]: REG Trigger address register */
uint32_t TRIG_POS;
/* [0x1c]: REG Sample rate */
/* [0x20]: REG Sampling clock frequency */
uint32_t FS_FREQ;
/* [0x24]: REG Sample rate */
uint32_t SR;
/* [0x20]: REG Pre-trigger samples */
/* [0x28]: REG Pre-trigger samples */
uint32_t PRE_SAMPLES;
/* [0x24]: REG Post-trigger samples */
/* [0x2c]: REG Post-trigger samples */
uint32_t POST_SAMPLES;
/* [0x28]: REG Samples counter */
/* [0x30]: REG Samples counter */
uint32_t SAMPLES_CNT;
/* [0x2c]: REG Channel 1 control register */
/* [0x34]: REG Channel 1 control register */
uint32_t CH1_CTL;
/* [0x30]: REG Channel 1 status register */
/* [0x38]: REG Channel 1 status register */
uint32_t CH1_STA;
/* [0x34]: REG Channel 1 gain calibration register */
/* [0x3c]: REG Channel 1 gain calibration register */
uint32_t CH1_GAIN;
/* [0x38]: REG Channel 1 offset calibration register */
/* [0x40]: REG Channel 1 offset calibration register */
uint32_t CH1_OFFSET;
/* [0x3c]: REG Channel 2 control register */
/* [0x44]: REG Channel 1 saturation register */
uint32_t CH1_SAT;
/* [0x48]: REG Channel 2 control register */
uint32_t CH2_CTL;
/* [0x40]: REG Channel 2 status register */
/* [0x4c]: REG Channel 2 status register */
uint32_t CH2_STA;
/* [0x44]: REG Channel 2 gain calibration register */
/* [0x50]: REG Channel 2 gain calibration register */
uint32_t CH2_GAIN;
/* [0x48]: REG Channel 2 offset calibration register */
/* [0x54]: REG Channel 2 offset calibration register */
uint32_t CH2_OFFSET;
/* [0x4c]: REG Channel 3 control register */
/* [0x58]: REG Channel 2 saturation register */
uint32_t CH2_SAT;
/* [0x5c]: REG Channel 3 control register */
uint32_t CH3_CTL;
/* [0x50]: REG Channel 3 status register */
/* [0x60]: REG Channel 3 status register */
uint32_t CH3_STA;
/* [0x54]: REG Channel 3 gain calibration register */
/* [0x64]: REG Channel 3 gain calibration register */
uint32_t CH3_GAIN;
/* [0x58]: REG Channel 3 offset calibration register */
/* [0x68]: REG Channel 3 offset calibration register */
uint32_t CH3_OFFSET;
/* [0x5c]: REG Channel 4 control register */
/* [0x6c]: REG Channel 3 saturation register */
uint32_t CH3_SAT;
/* [0x70]: REG Channel 4 control register */
uint32_t CH4_CTL;
/* [0x60]: REG Channel 4 status register */
/* [0x74]: REG Channel 4 status register */
uint32_t CH4_STA;
/* [0x64]: REG Channel 4 gain calibration register */
/* [0x78]: REG Channel 4 gain calibration register */
uint32_t CH4_GAIN;
/* [0x68]: REG Channel 4 offset calibration register */
/* [0x7c]: REG Channel 4 offset calibration register */
uint32_t CH4_OFFSET;
/* [0x80]: REG Channel 4 saturation register */
uint32_t CH4_SAT;
};
#endif
hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
View file @ 267af46a
Changes suppressed. Click to show.
......@@ -40,27 +40,33 @@
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Trigger delay</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Software trigger</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Number of shots</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Trigger address register</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Sample rate</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Pre-trigger samples</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Post-trigger samples</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">Samples counter</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">Channel 1 control register</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">Channel 1 status register</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">Channel 1 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">Channel 1 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">Channel 2 control register</a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">Channel 2 status register</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">Channel 2 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">Channel 2 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.20. <A href="#sect_3_20">Channel 3 control register</a></span><br/>
<span style="margin-left: 20px; ">3.21. <A href="#sect_3_21">Channel 3 status register</a></span><br/>
<span style="margin-left: 20px; ">3.22. <A href="#sect_3_22">Channel 3 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.23. <A href="#sect_3_23">Channel 3 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.24. <A href="#sect_3_24">Channel 4 control register</a></span><br/>
<span style="margin-left: 20px; ">3.25. <A href="#sect_3_25">Channel 4 status register</a></span><br/>
<span style="margin-left: 20px; ">3.26. <A href="#sect_3_26">Channel 4 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.27. <A href="#sect_3_27">Channel 4 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Remaining shots counter</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Trigger address register</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Sampling clock frequency</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Sample rate</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">Pre-trigger samples</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">Post-trigger samples</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">Samples counter</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">Channel 1 control register</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">Channel 1 status register</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">Channel 1 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">Channel 1 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">Channel 1 saturation register</a></span><br/>
<span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">Channel 2 control register</a></span><br/>
<span style="margin-left: 20px; ">3.20. <A href="#sect_3_20">Channel 2 status register</a></span><br/>
<span style="margin-left: 20px; ">3.21. <A href="#sect_3_21">Channel 2 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.22. <A href="#sect_3_22">Channel 2 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.23. <A href="#sect_3_23">Channel 2 saturation register</a></span><br/>
<span style="margin-left: 20px; ">3.24. <A href="#sect_3_24">Channel 3 control register</a></span><br/>
<span style="margin-left: 20px; ">3.25. <A href="#sect_3_25">Channel 3 status register</a></span><br/>
<span style="margin-left: 20px; ">3.26. <A href="#sect_3_26">Channel 3 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.27. <A href="#sect_3_27">Channel 3 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.28. <A href="#sect_3_28">Channel 3 saturation register</a></span><br/>
<span style="margin-left: 20px; ">3.29. <A href="#sect_3_29">Channel 4 control register</a></span><br/>
<span style="margin-left: 20px; ">3.30. <A href="#sect_3_30">Channel 4 status register</a></span><br/>
<span style="margin-left: 20px; ">3.31. <A href="#sect_3_31">Channel 4 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.32. <A href="#sect_3_32">Channel 4 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.33. <A href="#sect_3_33">Channel 4 saturation register</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -190,6 +196,23 @@ SHOTS
REG
</td>
<td >
<A href="#SHOTS_CNT">Remaining shots counter</a>
</td>
<td class="td_code">
fmc_adc_core_shots_cnt
</td>
<td class="td_code">
SHOTS_CNT
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x7
</td>
<td >
REG
</td>
<td >
<A href="#TRIG_POS">Trigger address register</a>
</td>
<td class="td_code">
......@@ -199,9 +222,26 @@ fmc_adc_core_trig_pos
TRIG_POS
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x8
</td>
<td >
REG
</td>
<td >
<A href="#FS_FREQ">Sampling clock frequency</a>
</td>
<td class="td_code">
fmc_adc_core_fs_freq
</td>
<td class="td_code">
FS_FREQ
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x7
0x9
</td>
<td >
REG
......@@ -218,7 +258,7 @@ SR
</tr>
<tr class="tr_odd">
<td class="td_code">
0x8
0xa
</td>
<td >
REG
......@@ -235,7 +275,7 @@ PRE_SAMPLES
</tr>
<tr class="tr_even">
<td class="td_code">
0x9
0xb
</td>
<td >
REG
......@@ -252,7 +292,7 @@ POST_SAMPLES
</tr>
<tr class="tr_odd">
<td class="td_code">
0xa
0xc
</td>
<td >
REG
......@@ -269,7 +309,7 @@ SAMPLES_CNT
</tr>
<tr class="tr_even">
<td class="td_code">
0xb
0xd
</td>
<td >
REG
......@@ -286,7 +326,7 @@ CH1_CTL
</tr>
<tr class="tr_odd">
<td class="td_code">
0xc
0xe
</td>
<td >
REG
......@@ -303,7 +343,7 @@ CH1_STA
</tr>
<tr class="tr_even">
<td class="td_code">
0xd
0xf
</td>
<td >
REG
......@@ -320,7 +360,7 @@ CH1_GAIN
</tr>
<tr class="tr_odd">
<td class="td_code">
0xe
0x10
</td>
<td >
REG
......@@ -337,7 +377,24 @@ CH1_OFFSET
</tr>
<tr class="tr_even">
<td class="td_code">
0xf
0x11
</td>
<td >
REG
</td>
<td >
<A href="#CH1_SAT">Channel 1 saturation register</a>
</td>
<td class="td_code">
fmc_adc_core_ch1_sat
</td>
<td class="td_code">
CH1_SAT
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x12
</td>
<td >
REG
......@@ -352,9 +409,9 @@ fmc_adc_core_ch2_ctl
CH2_CTL
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x10
0x13
</td>
<td >
REG
......@@ -369,9 +426,9 @@ fmc_adc_core_ch2_sta
CH2_STA
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x11
0x14
</td>
<td >
REG
......@@ -386,9 +443,9 @@ fmc_adc_core_ch2_gain
CH2_GAIN
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x12
0x15
</td>
<td >
REG
......@@ -403,9 +460,26 @@ fmc_adc_core_ch2_offset
CH2_OFFSET
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x16
</td>
<td >
REG
</td>
<td >
<A href="#CH2_SAT">Channel 2 saturation register</a>
</td>
<td class="td_code">
fmc_adc_core_ch2_sat
</td>
<td class="td_code">
CH2_SAT
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x13
0x17
</td>
<td >
REG
......@@ -422,7 +496,7 @@ CH3_CTL
</tr>
<tr class="tr_odd">
<td class="td_code">
0x14
0x18
</td>
<td >
REG
......@@ -439,7 +513,7 @@ CH3_STA
</tr>
<tr class="tr_even">
<td class="td_code">
0x15
0x19
</td>
<td >
REG
......@@ -456,7 +530,7 @@ CH3_GAIN
</tr>
<tr class="tr_odd">
<td class="td_code">
0x16
0x1a
</td>
<td >
REG
......@@ -473,7 +547,24 @@ CH3_OFFSET
</tr>
<tr class="tr_even">
<td class="td_code">
0x17
0x1b
</td>
<td >
REG
</td>
<td >
<A href="#CH3_SAT">Channel 3 saturation register</a>
</td>
<td class="td_code">
fmc_adc_core_ch3_sat
</td>
<td class="td_code">
CH3_SAT
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x1c
</td>
<td >
REG
......@@ -488,9 +579,9 @@ fmc_adc_core_ch4_ctl
CH4_CTL
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x18
0x1d
</td>
<td >
REG
......@@ -505,9 +596,9 @@ fmc_adc_core_ch4_sta
CH4_STA
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x19
0x1e
</td>
<td >
REG
......@@ -522,9 +613,9 @@ fmc_adc_core_ch4_gain
CH4_GAIN
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x1a
0x1f
</td>
<td >
REG
......@@ -539,6 +630,23 @@ fmc_adc_core_ch4_offset
CH4_OFFSET
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x20
</td>
<td >
REG
</td>
<td >
<A href="#CH4_SAT">Channel 4 saturation register</a>
</td>
<td class="td_code">
fmc_adc_core_ch4_sat
</td>
<td class="td_code">
CH4_SAT
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
......@@ -582,7 +690,7 @@ fmc_adc_core_ctl_fsm_cmd_o[1:0]
&rArr;
</td>
<td class="td_pblock_left">
wb_adr_i[4:0]
wb_adr_i[5:0]
</td>
<td class="td_sym_center">
......@@ -962,7 +1070,41 @@ fmc_adc_core_trig_cfg_int_trig_sel_o[1:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_trig_cfg_reserved_o[9:0]
fmc_adc_core_trig_cfg_int_trig_test_en_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_trig_cfg_reserved_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_trig_cfg_int_trig_thres_filt_o[7:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1200,7 +1342,7 @@ fmc_adc_core_shots_reserved_o[15:0]
</td>
<td class="td_pblock_right">
<b>Trigger address register:</b>
<b>Remaining shots counter:</b>
</td>
<td class="td_arrow_right">
......@@ -1217,7 +1359,7 @@ fmc_adc_core_shots_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_trig_pos_i[31:0]
fmc_adc_core_shots_cnt_val_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1229,6 +1371,23 @@ fmc_adc_core_trig_pos_i[31:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_shots_cnt_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1251,7 +1410,7 @@ fmc_adc_core_trig_pos_i[31:0]
</td>
<td class="td_pblock_right">
<b>Sample rate:</b>
<b>Trigger address register:</b>
</td>
<td class="td_arrow_right">
......@@ -1268,10 +1427,10 @@ fmc_adc_core_trig_pos_i[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_sr_deci_o[31:0]
fmc_adc_core_trig_pos_i[31:0]
</td>
<td class="td_arrow_right">
&rArr;
&lArr;
</td>
</tr>
<tr>
......@@ -1302,7 +1461,7 @@ fmc_adc_core_sr_deci_o[31:0]
</td>
<td class="td_pblock_right">
<b>Pre-trigger samples:</b>
<b>Sampling clock frequency:</b>
</td>
<td class="td_arrow_right">
......@@ -1319,10 +1478,10 @@ fmc_adc_core_sr_deci_o[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_pre_samples_o[31:0]
fmc_adc_core_fs_freq_i[31:0]
</td>
<td class="td_arrow_right">
&rArr;
&lArr;
</td>
</tr>
<tr>
......@@ -1353,7 +1512,7 @@ fmc_adc_core_pre_samples_o[31:0]
</td>
<td class="td_pblock_right">
<b>Post-trigger samples:</b>
<b>Sample rate:</b>
</td>
<td class="td_arrow_right">
......@@ -1370,7 +1529,7 @@ fmc_adc_core_pre_samples_o[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_post_samples_o[31:0]
fmc_adc_core_sr_deci_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1404,7 +1563,7 @@ fmc_adc_core_post_samples_o[31:0]
</td>
<td class="td_pblock_right">
<b>Samples counter:</b>
<b>Pre-trigger samples:</b>
</td>
<td class="td_arrow_right">
......@@ -1421,10 +1580,10 @@ fmc_adc_core_post_samples_o[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_samples_cnt_i[31:0]
fmc_adc_core_pre_samples_o[31:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
<tr>
......@@ -1455,7 +1614,7 @@ fmc_adc_core_samples_cnt_i[31:0]
</td>
<td class="td_pblock_right">
<b>Channel 1 control register:</b>
<b>Post-trigger samples:</b>
</td>
<td class="td_arrow_right">
......@@ -1472,24 +1631,7 @@ fmc_adc_core_samples_cnt_i[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_ctl_ssr_o[6:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_ctl_reserved_o[24:0]
fmc_adc_core_post_samples_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1523,7 +1665,7 @@ fmc_adc_core_ch1_ctl_reserved_o[24:0]
</td>
<td class="td_pblock_right">
<b>Channel 1 status register:</b>
<b>Samples counter:</b>
</td>
<td class="td_arrow_right">
......@@ -1540,24 +1682,7 @@ fmc_adc_core_ch1_ctl_reserved_o[24:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_sta_val_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_sta_reserved_i[15:0]
fmc_adc_core_samples_cnt_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1591,7 +1716,7 @@ fmc_adc_core_ch1_sta_reserved_i[15:0]
</td>
<td class="td_pblock_right">
<b>Channel 1 gain calibration register:</b>
<b>Channel 1 control register:</b>
</td>
<td class="td_arrow_right">
......@@ -1608,7 +1733,7 @@ fmc_adc_core_ch1_sta_reserved_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_gain_val_o[15:0]
fmc_adc_core_ch1_ctl_ssr_o[6:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1625,7 +1750,7 @@ fmc_adc_core_ch1_gain_val_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_gain_reserved_o[15:0]
fmc_adc_core_ch1_ctl_reserved_o[24:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1659,7 +1784,7 @@ fmc_adc_core_ch1_gain_reserved_o[15:0]
</td>
<td class="td_pblock_right">
<b>Channel 1 offset calibration register:</b>
<b>Channel 1 status register:</b>
</td>
<td class="td_arrow_right">
......@@ -1676,10 +1801,146 @@ fmc_adc_core_ch1_gain_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_offset_val_o[15:0]
fmc_adc_core_ch1_sta_val_i[15:0]
</td>
<td class="td_arrow_right">
&rArr;
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_sta_reserved_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 1 gain calibration register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_gain_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_gain_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 1 offset calibration register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_offset_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -1725,6 +1986,74 @@ fmc_adc_core_ch1_offset_reserved_o[15:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 1 saturation register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_sat_val_o[14:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_sat_reserved_o[16:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 2 control register:</b>
......@@ -1999,7 +2328,7 @@ fmc_adc_core_ch2_offset_reserved_o[15:0]
</td>
<td class="td_pblock_right">
<b>Channel 3 control register:</b>
<b>Channel 2 saturation register:</b>
</td>
<td class="td_arrow_right">
......@@ -2016,7 +2345,7 @@ fmc_adc_core_ch2_offset_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_ctl_ssr_o[6:0]
fmc_adc_core_ch2_sat_val_o[14:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2033,7 +2362,7 @@ fmc_adc_core_ch3_ctl_ssr_o[6:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_ctl_reserved_o[24:0]
fmc_adc_core_ch2_sat_reserved_o[16:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2067,7 +2396,7 @@ fmc_adc_core_ch3_ctl_reserved_o[24:0]
</td>
<td class="td_pblock_right">
<b>Channel 3 status register:</b>
<b>Channel 3 control register:</b>
</td>
<td class="td_arrow_right">
......@@ -2084,10 +2413,10 @@ fmc_adc_core_ch3_ctl_reserved_o[24:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_sta_val_i[15:0]
fmc_adc_core_ch3_ctl_ssr_o[6:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
<tr>
......@@ -2101,10 +2430,10 @@ fmc_adc_core_ch3_sta_val_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_sta_reserved_i[15:0]
fmc_adc_core_ch3_ctl_reserved_o[24:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
<tr>
......@@ -2135,7 +2464,7 @@ fmc_adc_core_ch3_sta_reserved_i[15:0]
</td>
<td class="td_pblock_right">
<b>Channel 3 gain calibration register:</b>
<b>Channel 3 status register:</b>
</td>
<td class="td_arrow_right">
......@@ -2152,10 +2481,10 @@ fmc_adc_core_ch3_sta_reserved_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_gain_val_o[15:0]
fmc_adc_core_ch3_sta_val_i[15:0]
</td>
<td class="td_arrow_right">
&rArr;
&lArr;
</td>
</tr>
<tr>
......@@ -2169,10 +2498,10 @@ fmc_adc_core_ch3_gain_val_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_gain_reserved_o[15:0]
fmc_adc_core_ch3_sta_reserved_i[15:0]
</td>
<td class="td_arrow_right">
&rArr;
&lArr;
</td>
</tr>
<tr>
......@@ -2203,7 +2532,7 @@ fmc_adc_core_ch3_gain_reserved_o[15:0]
</td>
<td class="td_pblock_right">
<b>Channel 3 offset calibration register:</b>
<b>Channel 3 gain calibration register:</b>
</td>
<td class="td_arrow_right">
......@@ -2220,7 +2549,7 @@ fmc_adc_core_ch3_gain_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_offset_val_o[15:0]
fmc_adc_core_ch3_gain_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2237,7 +2566,7 @@ fmc_adc_core_ch3_offset_val_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_offset_reserved_o[15:0]
fmc_adc_core_ch3_gain_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2271,7 +2600,7 @@ fmc_adc_core_ch3_offset_reserved_o[15:0]
</td>
<td class="td_pblock_right">
<b>Channel 4 control register:</b>
<b>Channel 3 offset calibration register:</b>
</td>
<td class="td_arrow_right">
......@@ -2288,7 +2617,7 @@ fmc_adc_core_ch3_offset_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_ctl_ssr_o[6:0]
fmc_adc_core_ch3_offset_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2305,7 +2634,7 @@ fmc_adc_core_ch4_ctl_ssr_o[6:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_ctl_reserved_o[24:0]
fmc_adc_core_ch3_offset_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2339,7 +2668,7 @@ fmc_adc_core_ch4_ctl_reserved_o[24:0]
</td>
<td class="td_pblock_right">
<b>Channel 4 status register:</b>
<b>Channel 3 saturation register:</b>
</td>
<td class="td_arrow_right">
......@@ -2356,10 +2685,10 @@ fmc_adc_core_ch4_ctl_reserved_o[24:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_sta_val_i[15:0]
fmc_adc_core_ch3_sat_val_o[14:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
<tr>
......@@ -2373,10 +2702,10 @@ fmc_adc_core_ch4_sta_val_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_sta_reserved_i[15:0]
fmc_adc_core_ch3_sat_reserved_o[16:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
<tr>
......@@ -2407,7 +2736,7 @@ fmc_adc_core_ch4_sta_reserved_i[15:0]
</td>
<td class="td_pblock_right">
<b>Channel 4 gain calibration register:</b>
<b>Channel 4 control register:</b>
</td>
<td class="td_arrow_right">
......@@ -2424,7 +2753,7 @@ fmc_adc_core_ch4_sta_reserved_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_gain_val_o[15:0]
fmc_adc_core_ch4_ctl_ssr_o[6:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2441,7 +2770,7 @@ fmc_adc_core_ch4_gain_val_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_gain_reserved_o[15:0]
fmc_adc_core_ch4_ctl_reserved_o[24:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2475,7 +2804,7 @@ fmc_adc_core_ch4_gain_reserved_o[15:0]
</td>
<td class="td_pblock_right">
<b>Channel 4 offset calibration register:</b>
<b>Channel 4 status register:</b>
</td>
<td class="td_arrow_right">
......@@ -2492,10 +2821,10 @@ fmc_adc_core_ch4_gain_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_offset_val_o[15:0]
fmc_adc_core_ch4_sta_val_i[15:0]
</td>
<td class="td_arrow_right">
&rArr;
&lArr;
</td>
</tr>
<tr>
......@@ -2509,7 +2838,211 @@ fmc_adc_core_ch4_offset_val_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_offset_reserved_o[15:0]
fmc_adc_core_ch4_sta_reserved_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 4 gain calibration register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_gain_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_gain_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 4 offset calibration register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_offset_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_offset_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 4 saturation register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_sat_val_o[14:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_sat_reserved_o[16:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2526,7 +3059,1634 @@ fmc_adc_core_ch4_offset_reserved_o[15:0]
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ctl
fmc_adc_core_ctl
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CTL
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ACQ_LED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TRIG_LED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TEST_DATA_EN
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
MAN_BITSLIP
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
OFFSET_DAC_CLR_N
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_CLK_OE
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
FSM_CMD[1:0]
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
FSM_CMD
</b>[<i>read/write</i>]: State machine commands (ignore on read)
<br>1: ACQ_START (start acquisition, only when FSM is idle)<br>2: ACQ_STOP (stop acquisition, anytime)
<li><b>
FMC_CLK_OE
</b>[<i>read/write</i>]: FMC Si750 output enable
<li><b>
OFFSET_DAC_CLR_N
</b>[<i>read/write</i>]: Offset DACs clear (active low)
<li><b>
MAN_BITSLIP
</b>[<i>write-only</i>]: Manual serdes bitslip (ignore on read)
<li><b>
TEST_DATA_EN
</b>[<i>read/write</i>]: Enable test data
<br>Write the address counter value instead of ADC data to DDR
<li><b>
TRIG_LED
</b>[<i>read/write</i>]: Manual TRIG LED
<br>Manual control of the front panel TRIG LED
<li><b>
ACQ_LED
</b>[<i>read/write</i>]: Manual ACQ LED
<br>Manual control of the front panel ACQ LED
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="STA"></a>
<h3><a name="sect_3_2">3.2. Status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_sta
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
STA
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[25:18]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[17:10]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[9:2]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=2 class="td_field">
RESERVED[1:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ACQ_CFG
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SERDES_SYNCED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SERDES_PLL
</td>
<td style="border: solid 1px black;" colspan=3 class="td_field">
FSM[2:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
FSM
</b>[<i>read-only</i>]: State machine status
<br>States:<br>0: illegal<br>1: IDLE<br>2: PRE_TRIG<br>3: WAIT_TRIG<br>4: POST_TRIG<br>5: TRIG_TAG<br>6: DECR_SHOT<br>7: illegal
<li><b>
SERDES_PLL
</b>[<i>read-only</i>]: SerDes PLL status
<br>Sampling clock recovery PLL.<br>0: not locked<br>1: locked
<li><b>
SERDES_SYNCED
</b>[<i>read-only</i>]: SerDes synchronization status
<br>0: bitslip in progress<br>1: serdes synchronized
<li><b>
ACQ_CFG
</b>[<i>read-only</i>]: Acquisition configuration status
<br>0: Unauthorised acquisition configuration (will prevent acquisition to start)<br>1: Valid acquisition configuration<br>- Shot number > 0<br>- Post-trigger sample > 0
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="TRIG_CFG"></a>
<h3><a name="sect_3_3">3.3. Trigger configuration</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_trig_cfg
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_CFG
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
INT_TRIG_THRES[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
INT_TRIG_THRES[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
INT_TRIG_THRES_FILT[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
INT_TRIG_TEST_EN
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
INT_TRIG_SEL[1:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SW_TRIG_EN
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
HW_TRIG_EN
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
HW_TRIG_POL
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
HW_TRIG_SEL
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
HW_TRIG_SEL
</b>[<i>read/write</i>]: Hardware trigger selection
<br>0: internal (data threshold)<br>1: external (front panel trigger input)
<li><b>
HW_TRIG_POL
</b>[<i>read/write</i>]: Hardware trigger polarity
<br>0: positive edge/slope<br>1: negative edge/slope
<li><b>
HW_TRIG_EN
</b>[<i>read/write</i>]: Hardware trigger enable
<br>0: disable<br>1: enable
<li><b>
SW_TRIG_EN
</b>[<i>read/write</i>]: Software trigger enable
<br>0: disable<br>1: enable
<li><b>
INT_TRIG_SEL
</b>[<i>read/write</i>]: Channel selection for internal trigger
<br>00: channel 1<br>01: channel 2<br>10: channel 3<br>11: channel 4
<li><b>
INT_TRIG_TEST_EN
</b>[<i>read/write</i>]: Enable internal trigger test mode
<br>Test mode:<br> ch1 = Channel 1 input(analogue)<br> ch2 = Channel input over threshold (digital)<br> ch3 = Channel input over threshold filtered (digital)<br> ch4 = Trigger (digital)
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
<li><b>
INT_TRIG_THRES_FILT
</b>[<i>read/write</i>]: Internal trigger threshold glitch filter
<br>Configures the internal trigger threshold glitch filter length.
<li><b>
INT_TRIG_THRES
</b>[<i>read/write</i>]: Threshold for internal trigger
<br>Treated as binary two's complement and compared to raw ADC data.
</ul>
<a name="TRIG_DLY"></a>
<h3><a name="sect_3_4">3.4. Trigger delay</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_trig_dly
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_DLY
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
TRIG_DLY
</b>[<i>read/write</i>]: Trigger delay value
<br>Delay to apply on the trigger in sampling clock period.<br>The default clock frequency is 100MHz (period = 10ns).
</ul>
<a name="SW_TRIG"></a>
<h3><a name="sect_3_5">3.5. Software trigger</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_sw_trig
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
SW_TRIG
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x10
</td>
</tr>
</table>
<p>
Writing (anything) to this register generates a software trigger.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SW_TRIG[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SW_TRIG[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SW_TRIG[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SW_TRIG[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
SW_TRIG
</b>[<i>write-only</i>]: Software trigger (ignore on read)
</ul>
<a name="SHOTS"></a>
<h3><a name="sect_3_6">3.6. Number of shots</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_shots
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x5
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
SHOTS
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x14
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
NB[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
NB[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
NB
</b>[<i>read/write</i>]: Number of shots
<br>Number of shots required in multi-shot mode, set to one for single-shot mode.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="SHOTS_CNT"></a>
<h3><a name="sect_3_7">3.7. Remaining shots counter</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_shots_cnt
</td>
</tr>
<tr>
......@@ -2534,7 +4694,7 @@ fmc_adc_core_ctl
<b>HW address: </b>
</td>
<td class="td_code">
0x0
0x6
</td>
</tr>
<tr>
......@@ -2542,7 +4702,7 @@ fmc_adc_core_ctl
<b>C prefix: </b>
</td>
<td class="td_code">
CTL
SHOTS_CNT
</td>
</tr>
<tr>
......@@ -2550,7 +4710,7 @@ CTL
<b>C offset: </b>
</td>
<td class="td_code">
0x0
0x18
</td>
</tr>
</table>
......@@ -2583,7 +4743,7 @@ CTL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[23:16]
RESERVED[15:8]
</td>
<td >
......@@ -2637,7 +4797,7 @@ RESERVED[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
RESERVED[7:0]
</td>
<td >
......@@ -2691,7 +4851,7 @@ RESERVED[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
VAL[15:8]
</td>
<td >
......@@ -2744,26 +4904,26 @@ RESERVED[7:0]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ACQ_LED
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[7:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TRIG_LED
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TEST_DATA_EN
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
MAN_BITSLIP
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
OFFSET_DAC_CLR_N
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_CLK_OE
<td >
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
FSM_CMD[1:0]
<td >
</td>
<td >
......@@ -2772,44 +4932,23 @@ FSM_CMD[1:0]
</table>
<ul>
<li><b>
FSM_CMD
</b>[<i>read/write</i>]: State machine commands (ignore on read)
<br>1: ACQ_START (start acquisition, only when FSM is idle)<br>2: ACQ_STOP (stop acquisition, anytime)
<li><b>
FMC_CLK_OE
</b>[<i>read/write</i>]: FMC Si750 output enable
<li><b>
OFFSET_DAC_CLR_N
</b>[<i>read/write</i>]: Offset DACs clear (active low)
<li><b>
MAN_BITSLIP
</b>[<i>write-only</i>]: Manual serdes bitslip (ignore on read)
<li><b>
TEST_DATA_EN
</b>[<i>read/write</i>]: Enable test data
<br>Write the address counter value instead of ADC data to DDR
<li><b>
TRIG_LED
</b>[<i>read/write</i>]: Manual TRIG LED
<br>Manual control of the front panel TRIG LED
<li><b>
ACQ_LED
</b>[<i>read/write</i>]: Manual ACQ LED
<br>Manual control of the front panel ACQ LED
VAL
</b>[<i>read-only</i>]: Remaining shots counter
<br>Counts the number of remaining shots to acquire.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="STA"></a>
<h3><a name="sect_3_2">3.2. Status register</a></h3>
<a name="TRIG_POS"></a>
<h3><a name="sect_3_8">3.8. Trigger address register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_sta
fmc_adc_core_trig_pos
</td>
</tr>
<tr>
......@@ -2817,7 +4956,7 @@ fmc_adc_core_sta
<b>HW address: </b>
</td>
<td class="td_code">
0x1
0x7
</td>
</tr>
<tr>
......@@ -2825,7 +4964,7 @@ fmc_adc_core_sta
<b>C prefix: </b>
</td>
<td class="td_code">
STA
TRIG_POS
</td>
</tr>
<tr>
......@@ -2833,7 +4972,7 @@ STA
<b>C offset: </b>
</td>
<td class="td_code">
0x4
0x1c
</td>
</tr>
</table>
......@@ -2866,7 +5005,7 @@ STA
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[25:18]
TRIG_POS[31:24]
</td>
<td >
......@@ -2920,7 +5059,7 @@ RESERVED[25:18]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[17:10]
TRIG_POS[23:16]
</td>
<td >
......@@ -2974,7 +5113,7 @@ RESERVED[17:10]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[9:2]
TRIG_POS[15:8]
</td>
<td >
......@@ -3027,20 +5166,20 @@ RESERVED[9:2]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=2 class="td_field">
RESERVED[1:0]
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_POS[7:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ACQ_CFG
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SERDES_SYNCED
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SERDES_PLL
<td >
</td>
<td style="border: solid 1px black;" colspan=3 class="td_field">
FSM[2:0]
<td >
</td>
<td >
......@@ -3055,35 +5194,19 @@ FSM[2:0]
</table>
<ul>
<li><b>
FSM
</b>[<i>read-only</i>]: State machine status
<br>States:<br>0: illegal<br>1: IDLE<br>2: PRE_TRIG<br>3: WAIT_TRIG<br>4: POST_TRIG<br>5: TRIG_TAG<br>6: DECR_SHOT<br>7: illegal
<li><b>
SERDES_PLL
</b>[<i>read-only</i>]: SerDes PLL status
<br>Sampling clock recovery PLL.<br>0: not locked<br>1: locked
<li><b>
SERDES_SYNCED
</b>[<i>read-only</i>]: SerDes synchronization status
<br>0: bitslip in progress<br>1: serdes synchronized
<li><b>
ACQ_CFG
</b>[<i>read-only</i>]: Acquisition configuration status
<br>0: Unauthorised acquisition configuration (will prevent acquisition to start)<br>1: Valid acquisition configuration<br>- Shot number > 0<br>- Post-trigger sample > 0
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
TRIG_POS
</b>[<i>read-only</i>]: Trigger address
<br>Trigger address in DDR memory.<br>Only used in single-shot mode.
</ul>
<a name="TRIG_CFG"></a>
<h3><a name="sect_3_3">3.3. Trigger configuration</a></h3>
<a name="FS_FREQ"></a>
<h3><a name="sect_3_9">3.9. Sampling clock frequency</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_trig_cfg
fmc_adc_core_fs_freq
</td>
</tr>
<tr>
......@@ -3091,7 +5214,7 @@ fmc_adc_core_trig_cfg
<b>HW address: </b>
</td>
<td class="td_code">
0x2
0x8
</td>
</tr>
<tr>
......@@ -3099,7 +5222,7 @@ fmc_adc_core_trig_cfg
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_CFG
FS_FREQ
</td>
</tr>
<tr>
......@@ -3107,7 +5230,7 @@ TRIG_CFG
<b>C offset: </b>
</td>
<td class="td_code">
0x8
0x20
</td>
</tr>
</table>
......@@ -3140,7 +5263,7 @@ TRIG_CFG
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
INT_TRIG_THRES[15:8]
FS_FREQ[31:24]
</td>
<td >
......@@ -3194,7 +5317,7 @@ INT_TRIG_THRES[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
INT_TRIG_THRES[7:0]
FS_FREQ[23:16]
</td>
<td >
......@@ -3248,7 +5371,7 @@ INT_TRIG_THRES[7:0]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[9:2]
FS_FREQ[15:8]
</td>
<td >
......@@ -3301,23 +5424,23 @@ RESERVED[9:2]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=2 class="td_field">
RESERVED[1:0]
<td style="border: solid 1px black;" colspan=8 class="td_field">
FS_FREQ[7:0]
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
INT_TRIG_SEL[1:0]
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SW_TRIG_EN
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
HW_TRIG_EN
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
HW_TRIG_POL
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
HW_TRIG_SEL
<td >
</td>
<td >
......@@ -3329,43 +5452,19 @@ HW_TRIG_SEL
</table>
<ul>
<li><b>
HW_TRIG_SEL
</b>[<i>read/write</i>]: Hardware trigger selection
<br>0: internal (data threshold)<br>1: external (front panel trigger input)
<li><b>
HW_TRIG_POL
</b>[<i>read/write</i>]: Hardware trigger polarity
<br>0: positive edge/slope<br>1: negative edge/slope
<li><b>
HW_TRIG_EN
</b>[<i>read/write</i>]: Hardware trigger enable
<br>0: disable<br>1: enable
<li><b>
SW_TRIG_EN
</b>[<i>read/write</i>]: Software trigger enable
<br>0: disable<br>1: enable
<li><b>
INT_TRIG_SEL
</b>[<i>read/write</i>]: Channel selection for internal trigger
<br>00: channel 1<br>01: channel 2<br>10: channel 3<br>11: channel 4
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
<li><b>
INT_TRIG_THRES
</b>[<i>read/write</i>]: Threshold for internal trigger
<br>Treated as binary two's complement and compared to raw ADC data.
FS_FREQ
</b>[<i>read-only</i>]: Sampling clock frequency
<br>ADC sampling clock frequency in Hz
</ul>
<a name="TRIG_DLY"></a>
<h3><a name="sect_3_4">3.4. Trigger delay</a></h3>
<a name="SR"></a>
<h3><a name="sect_3_10">3.10. Sample rate</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_trig_dly
fmc_adc_core_sr
</td>
</tr>
<tr>
......@@ -3373,7 +5472,7 @@ fmc_adc_core_trig_dly
<b>HW address: </b>
</td>
<td class="td_code">
0x3
0x9
</td>
</tr>
<tr>
......@@ -3381,7 +5480,7 @@ fmc_adc_core_trig_dly
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_DLY
SR
</td>
</tr>
<tr>
......@@ -3389,7 +5488,7 @@ TRIG_DLY
<b>C offset: </b>
</td>
<td class="td_code">
0xc
0x24
</td>
</tr>
</table>
......@@ -3422,7 +5521,7 @@ TRIG_DLY
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[31:24]
DECI[31:24]
</td>
<td >
......@@ -3476,7 +5575,7 @@ TRIG_DLY[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[23:16]
DECI[23:16]
</td>
<td >
......@@ -3530,7 +5629,7 @@ TRIG_DLY[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[15:8]
DECI[15:8]
</td>
<td >
......@@ -3584,7 +5683,7 @@ TRIG_DLY[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[7:0]
DECI[7:0]
</td>
<td >
......@@ -3611,19 +5710,19 @@ TRIG_DLY[7:0]
</table>
<ul>
<li><b>
TRIG_DLY
</b>[<i>read/write</i>]: Trigger delay value
<br>Delay to apply on the trigger in sampling clock period.<br>The default clock frequency is 100MHz (period = 10ns).
DECI
</b>[<i>read/write</i>]: Sample rate decimation
<br>Decimation factor. Takes one sample every N samples and discards the others (N = decimation factor).
</ul>
<a name="SW_TRIG"></a>
<h3><a name="sect_3_5">3.5. Software trigger</a></h3>
<a name="PRE_SAMPLES"></a>
<h3><a name="sect_3_11">3.11. Pre-trigger samples</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_sw_trig
fmc_adc_core_pre_samples
</td>
</tr>
<tr>
......@@ -3631,7 +5730,7 @@ fmc_adc_core_sw_trig
<b>HW address: </b>
</td>
<td class="td_code">
0x4
0xa
</td>
</tr>
<tr>
......@@ -3639,7 +5738,7 @@ fmc_adc_core_sw_trig
<b>C prefix: </b>
</td>
<td class="td_code">
SW_TRIG
PRE_SAMPLES
</td>
</tr>
<tr>
......@@ -3647,13 +5746,10 @@ SW_TRIG
<b>C offset: </b>
</td>
<td class="td_code">
0x10
0x28
</td>
</tr>
</table>
<p>
Writing (anything) to this register generates a software trigger.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
......@@ -3683,7 +5779,7 @@ Writing (anything) to this register generates a software trigger.
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SW_TRIG[31:24]
PRE_SAMPLES[31:24]
</td>
<td >
......@@ -3737,7 +5833,7 @@ SW_TRIG[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SW_TRIG[23:16]
PRE_SAMPLES[23:16]
</td>
<td >
......@@ -3791,7 +5887,7 @@ SW_TRIG[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SW_TRIG[15:8]
PRE_SAMPLES[15:8]
</td>
<td >
......@@ -3845,7 +5941,7 @@ SW_TRIG[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SW_TRIG[7:0]
PRE_SAMPLES[7:0]
</td>
<td >
......@@ -3872,18 +5968,19 @@ SW_TRIG[7:0]
</table>
<ul>
<li><b>
SW_TRIG
</b>[<i>write-only</i>]: Software trigger (ignore on read)
PRE_SAMPLES
</b>[<i>read/write</i>]: Pre-trigger samples
<br>Number of requested pre-trigger samples (>1).
</ul>
<a name="SHOTS"></a>
<h3><a name="sect_3_6">3.6. Number of shots</a></h3>
<a name="POST_SAMPLES"></a>
<h3><a name="sect_3_12">3.12. Post-trigger samples</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_shots
fmc_adc_core_post_samples
</td>
</tr>
<tr>
......@@ -3891,7 +5988,7 @@ fmc_adc_core_shots
<b>HW address: </b>
</td>
<td class="td_code">
0x5
0xb
</td>
</tr>
<tr>
......@@ -3899,7 +5996,7 @@ fmc_adc_core_shots
<b>C prefix: </b>
</td>
<td class="td_code">
SHOTS
POST_SAMPLES
</td>
</tr>
<tr>
......@@ -3907,7 +6004,7 @@ SHOTS
<b>C offset: </b>
</td>
<td class="td_code">
0x14
0x2c
</td>
</tr>
</table>
......@@ -3940,7 +6037,7 @@ SHOTS
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
POST_SAMPLES[31:24]
</td>
<td >
......@@ -3994,7 +6091,7 @@ RESERVED[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
POST_SAMPLES[23:16]
</td>
<td >
......@@ -4048,7 +6145,7 @@ RESERVED[7:0]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
NB[15:8]
POST_SAMPLES[15:8]
</td>
<td >
......@@ -4102,7 +6199,7 @@ NB[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
NB[7:0]
POST_SAMPLES[7:0]
</td>
<td >
......@@ -4129,23 +6226,19 @@ NB[7:0]
</table>
<ul>
<li><b>
NB
</b>[<i>read/write</i>]: Number of shots
<br>Number of shots required in multi-shot mode, set to one for single-shot mode.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
POST_SAMPLES
</b>[<i>read/write</i>]: Post-trigger samples
<br>Number of requested post-trigger samples (>1).
</ul>
<a name="TRIG_POS"></a>
<h3><a name="sect_3_7">3.7. Trigger address register</a></h3>
<a name="SAMPLES_CNT"></a>
<h3><a name="sect_3_13">3.13. Samples counter</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_trig_pos
fmc_adc_core_samples_cnt
</td>
</tr>
<tr>
......@@ -4153,7 +6246,7 @@ fmc_adc_core_trig_pos
<b>HW address: </b>
</td>
<td class="td_code">
0x6
0xc
</td>
</tr>
<tr>
......@@ -4161,7 +6254,7 @@ fmc_adc_core_trig_pos
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_POS
SAMPLES_CNT
</td>
</tr>
<tr>
......@@ -4169,7 +6262,7 @@ TRIG_POS
<b>C offset: </b>
</td>
<td class="td_code">
0x18
0x30
</td>
</tr>
</table>
......@@ -4202,7 +6295,7 @@ TRIG_POS
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_POS[31:24]
SAMPLES_CNT[31:24]
</td>
<td >
......@@ -4256,7 +6349,7 @@ TRIG_POS[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_POS[23:16]
SAMPLES_CNT[23:16]
</td>
<td >
......@@ -4310,7 +6403,7 @@ TRIG_POS[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_POS[15:8]
SAMPLES_CNT[15:8]
</td>
<td >
......@@ -4364,7 +6457,7 @@ TRIG_POS[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_POS[7:0]
SAMPLES_CNT[7:0]
</td>
<td >
......@@ -4391,19 +6484,19 @@ TRIG_POS[7:0]
</table>
<ul>
<li><b>
TRIG_POS
</b>[<i>read-only</i>]: Trigger address
<br>Trigger address in DDR memory.<br>Only used in single-shot mode.
SAMPLES_CNT
</b>[<i>read-only</i>]: Samples counter
<br>Counts the number of samples.<br> It is reset on START and then counts the number of pre-trigger + post-trigger samples
</ul>
<a name="SR"></a>
<h3><a name="sect_3_8">3.8. Sample rate</a></h3>
<a name="CH1_CTL"></a>
<h3><a name="sect_3_14">3.14. Channel 1 control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_sr
fmc_adc_core_ch1_ctl
</td>
</tr>
<tr>
......@@ -4411,7 +6504,7 @@ fmc_adc_core_sr
<b>HW address: </b>
</td>
<td class="td_code">
0x7
0xd
</td>
</tr>
<tr>
......@@ -4419,7 +6512,7 @@ fmc_adc_core_sr
<b>C prefix: </b>
</td>
<td class="td_code">
SR
CH1_CTL
</td>
</tr>
<tr>
......@@ -4427,7 +6520,7 @@ SR
<b>C offset: </b>
</td>
<td class="td_code">
0x1c
0x34
</td>
</tr>
</table>
......@@ -4460,7 +6553,7 @@ SR
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DECI[31:24]
RESERVED[24:17]
</td>
<td >
......@@ -4514,7 +6607,7 @@ DECI[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DECI[23:16]
RESERVED[16:9]
</td>
<td >
......@@ -4568,7 +6661,7 @@ DECI[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DECI[15:8]
RESERVED[8:1]
</td>
<td >
......@@ -4621,11 +6714,11 @@ DECI[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DECI[7:0]
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
</td>
<td >
......@@ -4649,19 +6742,23 @@ DECI[7:0]
</table>
<ul>
<li><b>
DECI
</b>[<i>read/write</i>]: Sample rate decimation
<br>Decimation factor. Takes one sample every N samples and discards the others (N = decimation factor).
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 1
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="PRE_SAMPLES"></a>
<h3><a name="sect_3_9">3.9. Pre-trigger samples</a></h3>
<a name="CH1_STA"></a>
<h3><a name="sect_3_15">3.15. Channel 1 status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_pre_samples
fmc_adc_core_ch1_sta
</td>
</tr>
<tr>
......@@ -4669,7 +6766,7 @@ fmc_adc_core_pre_samples
<b>HW address: </b>
</td>
<td class="td_code">
0x8
0xe
</td>
</tr>
<tr>
......@@ -4677,7 +6774,7 @@ fmc_adc_core_pre_samples
<b>C prefix: </b>
</td>
<td class="td_code">
PRE_SAMPLES
CH1_STA
</td>
</tr>
<tr>
......@@ -4685,7 +6782,7 @@ PRE_SAMPLES
<b>C offset: </b>
</td>
<td class="td_code">
0x20
0x38
</td>
</tr>
</table>
......@@ -4718,7 +6815,7 @@ PRE_SAMPLES
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
PRE_SAMPLES[31:24]
RESERVED[15:8]
</td>
<td >
......@@ -4772,7 +6869,7 @@ PRE_SAMPLES[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
PRE_SAMPLES[23:16]
RESERVED[7:0]
</td>
<td >
......@@ -4826,7 +6923,7 @@ PRE_SAMPLES[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
PRE_SAMPLES[15:8]
VAL[15:8]
</td>
<td >
......@@ -4880,7 +6977,7 @@ PRE_SAMPLES[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
PRE_SAMPLES[7:0]
VAL[7:0]
</td>
<td >
......@@ -4907,19 +7004,23 @@ PRE_SAMPLES[7:0]
</table>
<ul>
<li><b>
PRE_SAMPLES
</b>[<i>read/write</i>]: Pre-trigger samples
<br>Number of requested pre-trigger samples (>1).
VAL
</b>[<i>read-only</i>]: Channel 1 current ADC value
<br>Current ADC raw value. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="POST_SAMPLES"></a>
<h3><a name="sect_3_10">3.10. Post-trigger samples</a></h3>
<a name="CH1_GAIN"></a>
<h3><a name="sect_3_16">3.16. Channel 1 gain calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_post_samples
fmc_adc_core_ch1_gain
</td>
</tr>
<tr>
......@@ -4927,7 +7028,7 @@ fmc_adc_core_post_samples
<b>HW address: </b>
</td>
<td class="td_code">
0x9
0xf
</td>
</tr>
<tr>
......@@ -4935,7 +7036,7 @@ fmc_adc_core_post_samples
<b>C prefix: </b>
</td>
<td class="td_code">
POST_SAMPLES
CH1_GAIN
</td>
</tr>
<tr>
......@@ -4943,7 +7044,7 @@ POST_SAMPLES
<b>C offset: </b>
</td>
<td class="td_code">
0x24
0x3c
</td>
</tr>
</table>
......@@ -4976,7 +7077,7 @@ POST_SAMPLES
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
POST_SAMPLES[31:24]
RESERVED[15:8]
</td>
<td >
......@@ -5030,7 +7131,7 @@ POST_SAMPLES[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
POST_SAMPLES[23:16]
RESERVED[7:0]
</td>
<td >
......@@ -5084,7 +7185,7 @@ POST_SAMPLES[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
POST_SAMPLES[15:8]
VAL[15:8]
</td>
<td >
......@@ -5138,7 +7239,7 @@ POST_SAMPLES[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
POST_SAMPLES[7:0]
VAL[7:0]
</td>
<td >
......@@ -5165,19 +7266,23 @@ POST_SAMPLES[7:0]
</table>
<ul>
<li><b>
POST_SAMPLES
</b>[<i>read/write</i>]: Post-trigger samples
<br>Number of requested post-trigger samples (>1).
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 1
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="SAMPLES_CNT"></a>
<h3><a name="sect_3_11">3.11. Samples counter</a></h3>
<a name="CH1_OFFSET"></a>
<h3><a name="sect_3_17">3.17. Channel 1 offset calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_samples_cnt
fmc_adc_core_ch1_offset
</td>
</tr>
<tr>
......@@ -5185,7 +7290,7 @@ fmc_adc_core_samples_cnt
<b>HW address: </b>
</td>
<td class="td_code">
0xa
0x10
</td>
</tr>
<tr>
......@@ -5193,7 +7298,7 @@ fmc_adc_core_samples_cnt
<b>C prefix: </b>
</td>
<td class="td_code">
SAMPLES_CNT
CH1_OFFSET
</td>
</tr>
<tr>
......@@ -5201,7 +7306,7 @@ SAMPLES_CNT
<b>C offset: </b>
</td>
<td class="td_code">
0x28
0x40
</td>
</tr>
</table>
......@@ -5234,7 +7339,7 @@ SAMPLES_CNT
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SAMPLES_CNT[31:24]
RESERVED[15:8]
</td>
<td >
......@@ -5288,7 +7393,7 @@ SAMPLES_CNT[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SAMPLES_CNT[23:16]
RESERVED[7:0]
</td>
<td >
......@@ -5342,7 +7447,7 @@ SAMPLES_CNT[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SAMPLES_CNT[15:8]
VAL[15:8]
</td>
<td >
......@@ -5396,7 +7501,7 @@ SAMPLES_CNT[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SAMPLES_CNT[7:0]
VAL[7:0]
</td>
<td >
......@@ -5423,19 +7528,23 @@ SAMPLES_CNT[7:0]
</table>
<ul>
<li><b>
SAMPLES_CNT
</b>[<i>read-only</i>]: Samples counter
<br>Counts the number of samples.<br> It is reset on START and then counts the number of pre-trigger + post-trigger samples
VAL
</b>[<i>read/write</i>]: Offset calibration for channel 1
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH1_CTL"></a>
<h3><a name="sect_3_12">3.12. Channel 1 control register</a></h3>
<a name="CH1_SAT"></a>
<h3><a name="sect_3_18">3.18. Channel 1 saturation register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch1_ctl
fmc_adc_core_ch1_sat
</td>
</tr>
<tr>
......@@ -5443,7 +7552,7 @@ fmc_adc_core_ch1_ctl
<b>HW address: </b>
</td>
<td class="td_code">
0xb
0x11
</td>
</tr>
<tr>
......@@ -5451,7 +7560,7 @@ fmc_adc_core_ch1_ctl
<b>C prefix: </b>
</td>
<td class="td_code">
CH1_CTL
CH1_SAT
</td>
</tr>
<tr>
......@@ -5459,7 +7568,7 @@ CH1_CTL
<b>C offset: </b>
</td>
<td class="td_code">
0x2c
0x44
</td>
</tr>
</table>
......@@ -5492,7 +7601,7 @@ CH1_CTL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[24:17]
RESERVED[16:9]
</td>
<td >
......@@ -5546,7 +7655,7 @@ RESERVED[24:17]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
RESERVED[8:1]
</td>
<td >
......@@ -5599,11 +7708,11 @@ RESERVED[16:9]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=7 class="td_field">
VAL[14:8]
</td>
<td >
......@@ -5653,11 +7762,11 @@ RESERVED[8:1]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[7:0]
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
<td >
</td>
<td >
......@@ -5681,23 +7790,23 @@ SSR[6:0]
</table>
<ul>
<li><b>
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 1
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
VAL
</b>[<i>read/write</i>]: Saturation value for channel 1
<br>Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH1_STA"></a>
<h3><a name="sect_3_13">3.13. Channel 1 status register</a></h3>
<a name="CH2_CTL"></a>
<h3><a name="sect_3_19">3.19. Channel 2 control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch1_sta
fmc_adc_core_ch2_ctl
</td>
</tr>
<tr>
......@@ -5705,7 +7814,7 @@ fmc_adc_core_ch1_sta
<b>HW address: </b>
</td>
<td class="td_code">
0xc
0x12
</td>
</tr>
<tr>
......@@ -5713,7 +7822,7 @@ fmc_adc_core_ch1_sta
<b>C prefix: </b>
</td>
<td class="td_code">
CH1_STA
CH2_CTL
</td>
</tr>
<tr>
......@@ -5721,7 +7830,7 @@ CH1_STA
<b>C offset: </b>
</td>
<td class="td_code">
0x30
0x48
</td>
</tr>
</table>
......@@ -5754,7 +7863,7 @@ CH1_STA
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
RESERVED[24:17]
</td>
<td >
......@@ -5808,7 +7917,7 @@ RESERVED[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
RESERVED[16:9]
</td>
<td >
......@@ -5862,7 +7971,7 @@ RESERVED[7:0]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[15:8]
RESERVED[8:1]
</td>
<td >
......@@ -5915,11 +8024,11 @@ VAL[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[7:0]
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
</td>
<td >
......@@ -5943,23 +8052,23 @@ VAL[7:0]
</table>
<ul>
<li><b>
VAL
</b>[<i>read-only</i>]: Channel 1 current ADC value
<br>Current ADC raw value. The format is binary two's complement.
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 2
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH1_GAIN"></a>
<h3><a name="sect_3_14">3.14. Channel 1 gain calibration register</a></h3>
<a name="CH2_STA"></a>
<h3><a name="sect_3_20">3.20. Channel 2 status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch1_gain
fmc_adc_core_ch2_sta
</td>
</tr>
<tr>
......@@ -5967,7 +8076,7 @@ fmc_adc_core_ch1_gain
<b>HW address: </b>
</td>
<td class="td_code">
0xd
0x13
</td>
</tr>
<tr>
......@@ -5975,7 +8084,7 @@ fmc_adc_core_ch1_gain
<b>C prefix: </b>
</td>
<td class="td_code">
CH1_GAIN
CH2_STA
</td>
</tr>
<tr>
......@@ -5983,7 +8092,7 @@ CH1_GAIN
<b>C offset: </b>
</td>
<td class="td_code">
0x34
0x4c
</td>
</tr>
</table>
......@@ -6206,22 +8315,22 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 1
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
</b>[<i>read-only</i>]: Channel 2 current ACD value
<br>Current ADC raw value. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH1_OFFSET"></a>
<h3><a name="sect_3_15">3.15. Channel 1 offset calibration register</a></h3>
<a name="CH2_GAIN"></a>
<h3><a name="sect_3_21">3.21. Channel 2 gain calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch1_offset
fmc_adc_core_ch2_gain
</td>
</tr>
<tr>
......@@ -6229,7 +8338,7 @@ fmc_adc_core_ch1_offset
<b>HW address: </b>
</td>
<td class="td_code">
0xe
0x14
</td>
</tr>
<tr>
......@@ -6237,7 +8346,7 @@ fmc_adc_core_ch1_offset
<b>C prefix: </b>
</td>
<td class="td_code">
CH1_OFFSET
CH2_GAIN
</td>
</tr>
<tr>
......@@ -6245,7 +8354,7 @@ CH1_OFFSET
<b>C offset: </b>
</td>
<td class="td_code">
0x38
0x50
</td>
</tr>
</table>
......@@ -6468,22 +8577,22 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read/write</i>]: Offset calibration for channel 1
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
</b>[<i>read/write</i>]: Gain calibration for channel 2
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH2_CTL"></a>
<h3><a name="sect_3_16">3.16. Channel 2 control register</a></h3>
<a name="CH2_OFFSET"></a>
<h3><a name="sect_3_22">3.22. Channel 2 offset calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch2_ctl
fmc_adc_core_ch2_offset
</td>
</tr>
<tr>
......@@ -6491,7 +8600,7 @@ fmc_adc_core_ch2_ctl
<b>HW address: </b>
</td>
<td class="td_code">
0xf
0x15
</td>
</tr>
<tr>
......@@ -6499,7 +8608,7 @@ fmc_adc_core_ch2_ctl
<b>C prefix: </b>
</td>
<td class="td_code">
CH2_CTL
CH2_OFFSET
</td>
</tr>
<tr>
......@@ -6507,7 +8616,7 @@ CH2_CTL
<b>C offset: </b>
</td>
<td class="td_code">
0x3c
0x54
</td>
</tr>
</table>
......@@ -6540,7 +8649,7 @@ CH2_CTL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[24:17]
RESERVED[15:8]
</td>
<td >
......@@ -6594,7 +8703,7 @@ RESERVED[24:17]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
RESERVED[7:0]
</td>
<td >
......@@ -6648,7 +8757,7 @@ RESERVED[16:9]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
VAL[15:8]
</td>
<td >
......@@ -6701,11 +8810,11 @@ RESERVED[8:1]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[7:0]
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
<td >
</td>
<td >
......@@ -6729,23 +8838,23 @@ SSR[6:0]
</table>
<ul>
<li><b>
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 2
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
VAL
</b>[<i>read/write</i>]: Offset calibration for channel 2
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH2_STA"></a>
<h3><a name="sect_3_17">3.17. Channel 2 status register</a></h3>
<a name="CH2_SAT"></a>
<h3><a name="sect_3_23">3.23. Channel 2 saturation register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch2_sta
fmc_adc_core_ch2_sat
</td>
</tr>
<tr>
......@@ -6753,7 +8862,7 @@ fmc_adc_core_ch2_sta
<b>HW address: </b>
</td>
<td class="td_code">
0x10
0x16
</td>
</tr>
<tr>
......@@ -6761,7 +8870,7 @@ fmc_adc_core_ch2_sta
<b>C prefix: </b>
</td>
<td class="td_code">
CH2_STA
CH2_SAT
</td>
</tr>
<tr>
......@@ -6769,7 +8878,7 @@ CH2_STA
<b>C offset: </b>
</td>
<td class="td_code">
0x40
0x58
</td>
</tr>
</table>
......@@ -6802,7 +8911,7 @@ CH2_STA
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
RESERVED[16:9]
</td>
<td >
......@@ -6856,7 +8965,7 @@ RESERVED[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
RESERVED[8:1]
</td>
<td >
......@@ -6909,11 +9018,11 @@ RESERVED[7:0]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[15:8]
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=7 class="td_field">
VAL[14:8]
</td>
<td >
......@@ -6992,22 +9101,22 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read-only</i>]: Channel 2 current ACD value
<br>Current ADC raw value. The format is binary two's complement.
</b>[<i>read/write</i>]: Saturation value for channel 2
<br>Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH2_GAIN"></a>
<h3><a name="sect_3_18">3.18. Channel 2 gain calibration register</a></h3>
<a name="CH3_CTL"></a>
<h3><a name="sect_3_24">3.24. Channel 3 control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch2_gain
fmc_adc_core_ch3_ctl
</td>
</tr>
<tr>
......@@ -7015,7 +9124,7 @@ fmc_adc_core_ch2_gain
<b>HW address: </b>
</td>
<td class="td_code">
0x11
0x17
</td>
</tr>
<tr>
......@@ -7023,7 +9132,7 @@ fmc_adc_core_ch2_gain
<b>C prefix: </b>
</td>
<td class="td_code">
CH2_GAIN
CH3_CTL
</td>
</tr>
<tr>
......@@ -7031,7 +9140,7 @@ CH2_GAIN
<b>C offset: </b>
</td>
<td class="td_code">
0x44
0x5c
</td>
</tr>
</table>
......@@ -7064,7 +9173,7 @@ CH2_GAIN
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
RESERVED[24:17]
</td>
<td >
......@@ -7118,7 +9227,7 @@ RESERVED[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
RESERVED[16:9]
</td>
<td >
......@@ -7172,7 +9281,7 @@ RESERVED[7:0]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[15:8]
RESERVED[8:1]
</td>
<td >
......@@ -7225,11 +9334,11 @@ VAL[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[7:0]
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
</td>
<td >
......@@ -7253,23 +9362,23 @@ VAL[7:0]
</table>
<ul>
<li><b>
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 2
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 3
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH2_OFFSET"></a>
<h3><a name="sect_3_19">3.19. Channel 2 offset calibration register</a></h3>
<a name="CH3_STA"></a>
<h3><a name="sect_3_25">3.25. Channel 3 status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch2_offset
fmc_adc_core_ch3_sta
</td>
</tr>
<tr>
......@@ -7277,7 +9386,7 @@ fmc_adc_core_ch2_offset
<b>HW address: </b>
</td>
<td class="td_code">
0x12
0x18
</td>
</tr>
<tr>
......@@ -7285,7 +9394,7 @@ fmc_adc_core_ch2_offset
<b>C prefix: </b>
</td>
<td class="td_code">
CH2_OFFSET
CH3_STA
</td>
</tr>
<tr>
......@@ -7293,7 +9402,7 @@ CH2_OFFSET
<b>C offset: </b>
</td>
<td class="td_code">
0x48
0x60
</td>
</tr>
</table>
......@@ -7516,22 +9625,22 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read/write</i>]: Offset calibration for channel 2
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
</b>[<i>read-only</i>]: Channel 3 current ADC value
<br>Current ADC raw value. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH3_CTL"></a>
<h3><a name="sect_3_20">3.20. Channel 3 control register</a></h3>
<a name="CH3_GAIN"></a>
<h3><a name="sect_3_26">3.26. Channel 3 gain calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch3_ctl
fmc_adc_core_ch3_gain
</td>
</tr>
<tr>
......@@ -7539,7 +9648,7 @@ fmc_adc_core_ch3_ctl
<b>HW address: </b>
</td>
<td class="td_code">
0x13
0x19
</td>
</tr>
<tr>
......@@ -7547,7 +9656,7 @@ fmc_adc_core_ch3_ctl
<b>C prefix: </b>
</td>
<td class="td_code">
CH3_CTL
CH3_GAIN
</td>
</tr>
<tr>
......@@ -7555,7 +9664,7 @@ CH3_CTL
<b>C offset: </b>
</td>
<td class="td_code">
0x4c
0x64
</td>
</tr>
</table>
......@@ -7588,7 +9697,7 @@ CH3_CTL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[24:17]
RESERVED[15:8]
</td>
<td >
......@@ -7642,7 +9751,7 @@ RESERVED[24:17]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
RESERVED[7:0]
</td>
<td >
......@@ -7696,7 +9805,7 @@ RESERVED[16:9]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
VAL[15:8]
</td>
<td >
......@@ -7749,11 +9858,11 @@ RESERVED[8:1]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[7:0]
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
<td >
</td>
<td >
......@@ -7777,23 +9886,23 @@ SSR[6:0]
</table>
<ul>
<li><b>
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 3
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 3
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH3_STA"></a>
<h3><a name="sect_3_21">3.21. Channel 3 status register</a></h3>
<a name="CH3_OFFSET"></a>
<h3><a name="sect_3_27">3.27. Channel 3 offset calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch3_sta
fmc_adc_core_ch3_offset
</td>
</tr>
<tr>
......@@ -7801,7 +9910,7 @@ fmc_adc_core_ch3_sta
<b>HW address: </b>
</td>
<td class="td_code">
0x14
0x1a
</td>
</tr>
<tr>
......@@ -7809,7 +9918,7 @@ fmc_adc_core_ch3_sta
<b>C prefix: </b>
</td>
<td class="td_code">
CH3_STA
CH3_OFFSET
</td>
</tr>
<tr>
......@@ -7817,7 +9926,7 @@ CH3_STA
<b>C offset: </b>
</td>
<td class="td_code">
0x50
0x68
</td>
</tr>
</table>
......@@ -8040,22 +10149,22 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read-only</i>]: Channel 3 current ADC value
<br>Current ADC raw value. The format is binary two's complement.
</b>[<i>read/write</i>]: Offset calibration for channel 3
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH3_GAIN"></a>
<h3><a name="sect_3_22">3.22. Channel 3 gain calibration register</a></h3>
<a name="CH3_SAT"></a>
<h3><a name="sect_3_28">3.28. Channel 3 saturation register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch3_gain
fmc_adc_core_ch3_sat
</td>
</tr>
<tr>
......@@ -8063,7 +10172,7 @@ fmc_adc_core_ch3_gain
<b>HW address: </b>
</td>
<td class="td_code">
0x15
0x1b
</td>
</tr>
<tr>
......@@ -8071,7 +10180,7 @@ fmc_adc_core_ch3_gain
<b>C prefix: </b>
</td>
<td class="td_code">
CH3_GAIN
CH3_SAT
</td>
</tr>
<tr>
......@@ -8079,7 +10188,7 @@ CH3_GAIN
<b>C offset: </b>
</td>
<td class="td_code">
0x54
0x6c
</td>
</tr>
</table>
......@@ -8112,7 +10221,7 @@ CH3_GAIN
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
RESERVED[16:9]
</td>
<td >
......@@ -8166,7 +10275,7 @@ RESERVED[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
RESERVED[8:1]
</td>
<td >
......@@ -8219,11 +10328,11 @@ RESERVED[7:0]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[15:8]
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=7 class="td_field">
VAL[14:8]
</td>
<td >
......@@ -8302,22 +10411,22 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 3
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
</b>[<i>read/write</i>]: Saturation value for channel 3
<br>Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH3_OFFSET"></a>
<h3><a name="sect_3_23">3.23. Channel 3 offset calibration register</a></h3>
<a name="CH4_CTL"></a>
<h3><a name="sect_3_29">3.29. Channel 4 control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch3_offset
fmc_adc_core_ch4_ctl
</td>
</tr>
<tr>
......@@ -8325,7 +10434,7 @@ fmc_adc_core_ch3_offset
<b>HW address: </b>
</td>
<td class="td_code">
0x16
0x1c
</td>
</tr>
<tr>
......@@ -8333,7 +10442,7 @@ fmc_adc_core_ch3_offset
<b>C prefix: </b>
</td>
<td class="td_code">
CH3_OFFSET
CH4_CTL
</td>
</tr>
<tr>
......@@ -8341,7 +10450,7 @@ CH3_OFFSET
<b>C offset: </b>
</td>
<td class="td_code">
0x58
0x70
</td>
</tr>
</table>
......@@ -8374,7 +10483,7 @@ CH3_OFFSET
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
RESERVED[24:17]
</td>
<td >
......@@ -8428,7 +10537,7 @@ RESERVED[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
RESERVED[16:9]
</td>
<td >
......@@ -8482,7 +10591,7 @@ RESERVED[7:0]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[15:8]
RESERVED[8:1]
</td>
<td >
......@@ -8535,11 +10644,11 @@ VAL[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[7:0]
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
</td>
<td >
......@@ -8563,23 +10672,23 @@ VAL[7:0]
</table>
<ul>
<li><b>
VAL
</b>[<i>read/write</i>]: Offset calibration for channel 3
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 4
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH4_CTL"></a>
<h3><a name="sect_3_24">3.24. Channel 4 control register</a></h3>
<a name="CH4_STA"></a>
<h3><a name="sect_3_30">3.30. Channel 4 status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch4_ctl
fmc_adc_core_ch4_sta
</td>
</tr>
<tr>
......@@ -8587,7 +10696,7 @@ fmc_adc_core_ch4_ctl
<b>HW address: </b>
</td>
<td class="td_code">
0x17
0x1d
</td>
</tr>
<tr>
......@@ -8595,7 +10704,7 @@ fmc_adc_core_ch4_ctl
<b>C prefix: </b>
</td>
<td class="td_code">
CH4_CTL
CH4_STA
</td>
</tr>
<tr>
......@@ -8603,7 +10712,7 @@ CH4_CTL
<b>C offset: </b>
</td>
<td class="td_code">
0x5c
0x74
</td>
</tr>
</table>
......@@ -8636,7 +10745,7 @@ CH4_CTL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[24:17]
RESERVED[15:8]
</td>
<td >
......@@ -8690,7 +10799,7 @@ RESERVED[24:17]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
RESERVED[7:0]
</td>
<td >
......@@ -8744,7 +10853,7 @@ RESERVED[16:9]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
VAL[15:8]
</td>
<td >
......@@ -8797,11 +10906,11 @@ RESERVED[8:1]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[7:0]
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
<td >
</td>
<td >
......@@ -8825,23 +10934,23 @@ SSR[6:0]
</table>
<ul>
<li><b>
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 4
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
VAL
</b>[<i>read-only</i>]: Channel 4 current ADC value
<br>Current ADC raw value. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH4_STA"></a>
<h3><a name="sect_3_25">3.25. Channel 4 status register</a></h3>
<a name="CH4_GAIN"></a>
<h3><a name="sect_3_31">3.31. Channel 4 gain calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch4_sta
fmc_adc_core_ch4_gain
</td>
</tr>
<tr>
......@@ -8849,7 +10958,7 @@ fmc_adc_core_ch4_sta
<b>HW address: </b>
</td>
<td class="td_code">
0x18
0x1e
</td>
</tr>
<tr>
......@@ -8857,7 +10966,7 @@ fmc_adc_core_ch4_sta
<b>C prefix: </b>
</td>
<td class="td_code">
CH4_STA
CH4_GAIN
</td>
</tr>
<tr>
......@@ -8865,7 +10974,7 @@ CH4_STA
<b>C offset: </b>
</td>
<td class="td_code">
0x60
0x78
</td>
</tr>
</table>
......@@ -9088,22 +11197,22 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read-only</i>]: Channel 4 current ADC value
<br>Current ADC raw value. The format is binary two's complement.
</b>[<i>read/write</i>]: Gain calibration for channel 4
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH4_GAIN"></a>
<h3><a name="sect_3_26">3.26. Channel 4 gain calibration register</a></h3>
<a name="CH4_OFFSET"></a>
<h3><a name="sect_3_32">3.32. Channel 4 offset calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch4_gain
fmc_adc_core_ch4_offset
</td>
</tr>
<tr>
......@@ -9111,7 +11220,7 @@ fmc_adc_core_ch4_gain
<b>HW address: </b>
</td>
<td class="td_code">
0x19
0x1f
</td>
</tr>
<tr>
......@@ -9119,7 +11228,7 @@ fmc_adc_core_ch4_gain
<b>C prefix: </b>
</td>
<td class="td_code">
CH4_GAIN
CH4_OFFSET
</td>
</tr>
<tr>
......@@ -9127,7 +11236,7 @@ CH4_GAIN
<b>C offset: </b>
</td>
<td class="td_code">
0x64
0x7c
</td>
</tr>
</table>
......@@ -9350,22 +11459,22 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 4
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
</b>[<i>read/write</i>]: Offset calibration for channel 4
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH4_OFFSET"></a>
<h3><a name="sect_3_27">3.27. Channel 4 offset calibration register</a></h3>
<a name="CH4_SAT"></a>
<h3><a name="sect_3_33">3.33. Channel 4 saturation register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch4_offset
fmc_adc_core_ch4_sat
</td>
</tr>
<tr>
......@@ -9373,7 +11482,7 @@ fmc_adc_core_ch4_offset
<b>HW address: </b>
</td>
<td class="td_code">
0x1a
0x20
</td>
</tr>
<tr>
......@@ -9381,7 +11490,7 @@ fmc_adc_core_ch4_offset
<b>C prefix: </b>
</td>
<td class="td_code">
CH4_OFFSET
CH4_SAT
</td>
</tr>
<tr>
......@@ -9389,7 +11498,7 @@ CH4_OFFSET
<b>C offset: </b>
</td>
<td class="td_code">
0x68
0x80
</td>
</tr>
</table>
......@@ -9422,7 +11531,7 @@ CH4_OFFSET
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
RESERVED[16:9]
</td>
<td >
......@@ -9476,7 +11585,7 @@ RESERVED[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
RESERVED[8:1]
</td>
<td >
......@@ -9529,11 +11638,11 @@ RESERVED[7:0]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[15:8]
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=7 class="td_field">
VAL[14:8]
</td>
<td >
......@@ -9612,8 +11721,8 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read/write</i>]: Offset calibration for channel 4
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
</b>[<i>read/write</i>]: Saturation value for channel 4
<br>Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
View file @ 267af46a
......@@ -187,14 +187,34 @@ peripheral {
clock = "fs_clk_i";
};
field {
name = "Enable internal trigger test mode";
description = "Test mode:\n ch1 = Channel 1 input(analogue)\n ch2 = Channel input over threshold (digital)\n ch3 = Channel input over threshold filtered (digital)\n ch4 = Trigger (digital)";
prefix = "int_trig_test_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Internal trigger threshold glitch filter";
description = "Configures the internal trigger threshold glitch filter length.";
prefix = "int_trig_thres_filt";
type = SLV;
size = 10;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
......@@ -261,6 +281,31 @@ peripheral {
};
};
reg {
name = "Remaining shots counter";
prefix = "shots_cnt";
field {
name = "Remaining shots counter";
description = "Counts the number of remaining shots to acquire.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Trigger address register";
prefix = "trig_pos";
......@@ -275,6 +320,21 @@ peripheral {
};
};
reg {
name = "Sampling clock frequency";
prefix = "fs_freq";
field {
name = "Sampling clock frequency";
description = "ADC sampling clock frequency in Hz";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Sample rate";
prefix = "sr";
......@@ -434,6 +494,31 @@ peripheral {
};
};
reg {
name = "Channel 1 saturation register";
prefix = "ch1_sat";
field {
name = "Saturation value for channel 1";
description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
prefix = "val";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 2 control register";
prefix = "ch2_ctl";
......@@ -535,6 +620,31 @@ peripheral {
};
};
reg {
name = "Channel 2 saturation register";
prefix = "ch2_sat";
field {
name = "Saturation value for channel 2";
description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
prefix = "val";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 3 control register";
prefix = "ch3_ctl";
......@@ -636,6 +746,31 @@ peripheral {
};
};
reg {
name = "Channel 3 saturation register";
prefix = "ch3_sat";
field {
name = "Saturation value for channel 3";
description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
prefix = "val";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 4 control register";
prefix = "ch4_ctl";
......@@ -737,4 +872,29 @@ peripheral {
};
};
reg {
name = "Channel 4 saturation register";
prefix = "ch4_sat";
field {
name = "Saturation value for channel 4";
description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
prefix = "val";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ 267af46a
......@@ -60,6 +60,12 @@ entity spec_top_fmc_adc_100Ms is
-- Local oscillator
clk20_vcxo_i : in std_logic; -- 20MHz VCXO clock
-- DAC interface (20MHz and 25MHz VCXO)
pll25dac_sync_n_o : out std_logic; -- 25MHz VCXO
pll20dac_sync_n_o : out std_logic; -- 20MHz VCXO
plldac_din_o : out std_logic;
plldac_sclk_o : out std_logic;
-- Carrier font panel LEDs
led_red_o : out std_logic;
led_green_o : out std_logic;
......@@ -453,6 +459,15 @@ begin
-- 250.000 MHz fast system clock
-- 333.333 MHz DDR3 clock
------------------------------------------------------------------------------
-- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a
-- write sequence arrives to the DAC.
-- To avoid spurious writes, the DAC interface outputs are fixed to safe values.
pll25dac_sync_n_o <= '1';
pll20dac_sync_n_o <= '1';
plldac_din_o <= '0';
plldac_sclk_o <= '0';
cmp_sys_clk_buf : IBUFG
port map (
I => clk20_vcxo_i,
......
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ 267af46a
......@@ -43,14 +43,14 @@ NET "clk20_vcxo_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# DAC interface (for VCXO)
#----------------------------------------
#NET "PLL25DAC1_SYNC_N" LOC = A3;
#NET "PLL25DAC1_SYNC_N" IOSTANDARD = "LVCMOS25";
#NET "PLL25DAC2_SYNC_N" LOC = B3;
#NET "PLL25DAC2_SYNC_N" IOSTANDARD = "LVCMOS25";
#NET "PLL25DAC_DIN" LOC = C4;
#NET "PLL25DAC_DIN" IOSTANDARD = "LVCMOS25";
#NET "PLL25DAC_SCLK" LOC = A4;
#NET "PLL25DAC_SCLK" IOSTANDARD = "LVCMOS25";
NET "pll25dac_sync_n_o" LOC = A3;
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "pll20dac_sync_n_o" LOC = B3;
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "plldac_din_o" LOC = C4;
NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
NET "plldac_sclk_o" LOC = A4;
NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer w/ ID
......
hdl/spec/syn/spec_fmc_adc_100Ms.xise
View file @ 267af46a
......@@ -374,13 +374,13 @@
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
......@@ -398,411 +398,441 @@
<file xil_pn:name="../../adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core_regs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/var_sat_s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
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<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
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<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
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<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/dma_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
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<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
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<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../rtl/spec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
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<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
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<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../rtl/spec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
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<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
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<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
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<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
</files>
<bindings/>
......
hdl/spec/wb_gen/Makefile
View file @ 267af46a
WBGEN2=~/projects/wbgen2/wbgen2
RTL=../rtl/
TEX=../../../documentation/manuals/firmware/spec/
TEX=../../../documentation/manuals/gateware/spec/
carrier_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
......
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @ 267af46a
......@@ -62,6 +62,14 @@ entity svec_top_fmc_adc_100Ms is
-- Local 20MHz VCXO oscillator
clk_20m_vcxo_i : in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic;
pll20dac_sync_n_o : out std_logic;
pll25dac_din_o : out std_logic;
pll25dac_sclk_o : out std_logic;
pll25dac_sync_n_o : out std_logic;
-- Reset from system fpga
rst_n_i : in std_logic;
......@@ -561,6 +569,17 @@ begin
-- 125.000 MHz system clock
-- 333.333 MHz DDR3 clock
------------------------------------------------------------------------------
-- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a
-- write sequence arrives to the DAC.
-- To avoid spurious writes, the DAC interface outputs are fixed to safe values.
pll20dac_din_o <= '0';
pll20dac_sclk_o <= '0';
pll20dac_sync_n_o <= '1';
pll25dac_din_o <= '0';
pll25dac_sclk_o <= '0';
pll25dac_sync_n_o <= '1';
cmp_sys_clk_buf : IBUFG
port map (
I => clk_20m_vcxo_i,
......@@ -878,7 +897,7 @@ begin
cnx_master_in(c_WB_SLAVE_SVEC_CSR).int <= '0';
-- external software reset registers (to assign a non-zero default value)
p_sw_rst_fmc0: process (sys_clk_125)
p_sw_rst_fmc0 : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
......@@ -891,7 +910,7 @@ begin
sw_rst_fmc0_n_i <= sw_rst_fmc0_n;
p_sw_rst_fmc1: process (sys_clk_125)
p_sw_rst_fmc1 : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
......
hdl/svec/svec_top_fmc_adc_100Ms.ucf
View file @ 267af46a
......@@ -457,18 +457,18 @@ NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock controls
#----------------------------------------
#NET "pll20dac_din_o" LOC = U28;
#NET "pll20dac_sclk_o" LOC = AA28;
#NET "pll20dac_sync_n_o" LOC = N28;
#NET "pll25dac_din_o" LOC = P25;
#NET "pll25dac_sclk_o" LOC = N27;
#NET "pll25dac_sync_n_o" LOC = P26;
#NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
#NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
#NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
#NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
#NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
#NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_din_o" LOC = U28;
NET "pll20dac_sclk_o" LOC = AA28;
NET "pll20dac_sync_n_o" LOC = N28;
NET "pll25dac_din_o" LOC = P25;
NET "pll25dac_sclk_o" LOC = N27;
NET "pll25dac_sync_n_o" LOC = P26;
NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# UART
......
hdl/svec/syn/svec_fmc_adc_100Ms.xise
View file @ 267af46a
......@@ -375,13 +375,13 @@
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
......@@ -399,438 +399,468 @@
<file xil_pn:name="../../adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core_regs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/var_sat_s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
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<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
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<file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
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<bindings/>
......
hdl/svec/wb_gen/Makefile
View file @ 267af46a
WBGEN2=~/projects/wbgen2/wbgen2
RTL=../rtl/
TEX=../../../documentation/manuals/firmware/svec/
TEX=../../../documentation/manuals/gateware/svec/
carrier_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
......
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