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FMC ADC 100M 14b 4cha - Gateware
Commit 162b78cd authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: add extra address decoder for channel control registers. 

This helps with timing, but also provides a more logical structure
for the registers, but not having to manually copy 4 times the same
set of registers (once for each channel).
Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
parent 246c1d60
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hdl/cheby/fmc_adc_100Ms_channel_regs.cheby 0 → 100644
View file @ 162b78cd
memory-map:
bus: wb-32-be
name: fmc_adc_100ms_channel_regs
description: FMC ADC 100MS/s channel configuration registers
comment: |
Wishbone slave for FMC ADC 100MS/s CSR
x-hdl:
busgroup: True
iogroup: fmc_adc_100ms_ch
children:
- reg:
name: ctl
address: 0x00000000
width: 32
access: rw
description: Channel control register
children:
- field:
name: ssr
range: 6-0
description: Solid state relays control for channel
comment: |
Controls input voltage range, termination and DC offset error calibration
0x23: 100mV range
0x11: 1V range
0x45: 10V range
0x00: Open input
0x42: 100mV range calibration
0x40: 1V range calibration
0x44: 10V range calibration
Bit3 is indepandant of the others and enables the 50ohms termination.
- reg:
name: sta
address: 0x00000004
width: 32
access: ro
description: Channel status register
children:
- field:
name: val
range: 15-0
description: Channel current ADC value
comment: |
Current ADC raw value. The format depends on ADC configuration; Upon reset, the ADC is
configured for "offset binary". The FMC-ADC driver when loaded, will change this to
binary two\'s complement.
- reg:
name: calib
address: 0x00000008
width: 32
access: rw
description: Channel calibration register
children:
- field:
name: gain
range: 15-0
description: Gain calibration for channel
comment: |
Gain applied to all data coming from the ADC.
Fixed point format:
Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
- field:
name: offset
range: 31-16
description: Offset calibration for channel
comment: |
Offset applied to all data coming from the ADC. The format is binary two\'s complement.
- reg:
name: sat
address: 0x0000000c
width: 32
access: rw
description: Channel saturation register
children:
- field:
name: val
range: 14-0
description: Saturation value for channel
comment: |
Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
- reg:
name: trig_thres
address: 0x00000010
width: 32
access: rw
description: Channel trigger threshold configuration register
children:
- field:
name: val
range: 15-0
description: Threshold for internal trigger
comment: |
Treated as binary two\'s complement and compared to raw ADC data.
- field:
name: hyst
range: 31-16
description: Internal trigger threshold hysteresis
comment: |
Configures the internal trigger threshold hysteresis.
The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.
- reg:
name: trig_dly
address: 0x00000014
width: 32
access: rw
description: Channel trigger delay
comment: |
Delay to apply on the trigger in sampling clock period.
The default clock frequency is 100MHz (period = 10ns).
hdl/cheby/fmc_adc_100Ms_channel_regs.vhd 0 → 100644
View file @ 162b78cd
-- Do not edit; this file was generated by Cheby using these options:
-- -i fmc_adc_100Ms_channel_regs.cheby --gen-hdl=fmc_adc_100Ms_channel_regs.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package fmc_adc_100ms_channel_regs_pkg is
type t_fmc_adc_100ms_ch_master_out is record
ctl_ssr : std_logic_vector(6 downto 0);
calib_gain : std_logic_vector(15 downto 0);
calib_offset : std_logic_vector(15 downto 0);
sat_val : std_logic_vector(14 downto 0);
trig_thres_val : std_logic_vector(15 downto 0);
trig_thres_hyst : std_logic_vector(15 downto 0);
trig_dly : std_logic_vector(31 downto 0);
end record t_fmc_adc_100ms_ch_master_out;
subtype t_fmc_adc_100ms_ch_slave_in is t_fmc_adc_100ms_ch_master_out;
type t_fmc_adc_100ms_ch_slave_out is record
sta_val : std_logic_vector(15 downto 0);
end record t_fmc_adc_100ms_ch_slave_out;
subtype t_fmc_adc_100ms_ch_master_in is t_fmc_adc_100ms_ch_slave_out;
end fmc_adc_100ms_channel_regs_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.fmc_adc_100ms_channel_regs_pkg.all;
entity fmc_adc_100ms_channel_regs is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- Wires and registers
fmc_adc_100ms_ch_i : in t_fmc_adc_100ms_ch_master_in;
fmc_adc_100ms_ch_o : out t_fmc_adc_100ms_ch_master_out
);
end fmc_adc_100ms_channel_regs;
architecture syn of fmc_adc_100ms_channel_regs is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal ctl_ssr_reg : std_logic_vector(6 downto 0);
signal calib_gain_reg : std_logic_vector(15 downto 0);
signal calib_offset_reg : std_logic_vector(15 downto 0);
signal sat_val_reg : std_logic_vector(14 downto 0);
signal trig_thres_val_reg : std_logic_vector(15 downto 0);
signal trig_thres_hyst_reg : std_logic_vector(15 downto 0);
signal trig_dly_reg : std_logic_vector(31 downto 0);
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
fmc_adc_100ms_ch_o.ctl_ssr <= ctl_ssr_reg;
fmc_adc_100ms_ch_o.calib_gain <= calib_gain_reg;
fmc_adc_100ms_ch_o.calib_offset <= calib_offset_reg;
fmc_adc_100ms_ch_o.sat_val <= sat_val_reg;
fmc_adc_100ms_ch_o.trig_thres_val <= trig_thres_val_reg;
fmc_adc_100ms_ch_o.trig_thres_hyst <= trig_thres_hyst_reg;
fmc_adc_100ms_ch_o.trig_dly <= trig_dly_reg;
-- Process for write requests.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
ctl_ssr_reg <= "0000000";
calib_gain_reg <= "0000000000000000";
calib_offset_reg <= "0000000000000000";
sat_val_reg <= "000000000000000";
trig_thres_val_reg <= "0000000000000000";
trig_thres_hyst_reg <= "0000000000000000";
trig_dly_reg <= "00000000000000000000000000000000";
else
wr_ack_int <= '0';
case wb_i.adr(4 downto 2) is
when "000" =>
-- Register ctl
if wr_int = '1' then
ctl_ssr_reg <= wb_i.dat(6 downto 0);
end if;
wr_ack_int <= wr_int;
when "001" =>
-- Register sta
when "010" =>
-- Register calib
if wr_int = '1' then
calib_gain_reg <= wb_i.dat(15 downto 0);
calib_offset_reg <= wb_i.dat(31 downto 16);
end if;
wr_ack_int <= wr_int;
when "011" =>
-- Register sat
if wr_int = '1' then
sat_val_reg <= wb_i.dat(14 downto 0);
end if;
wr_ack_int <= wr_int;
when "100" =>
-- Register trig_thres
if wr_int = '1' then
trig_thres_val_reg <= wb_i.dat(15 downto 0);
trig_thres_hyst_reg <= wb_i.dat(31 downto 16);
end if;
wr_ack_int <= wr_int;
when "101" =>
-- Register trig_dly
if wr_int = '1' then
trig_dly_reg <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= wr_int;
end case;
end if;
end if;
end process;
-- Process for registers read.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => '0');
case wb_i.adr(4 downto 2) is
when "000" =>
-- ctl
reg_rdat_int(6 downto 0) <= ctl_ssr_reg;
rd_ack1_int <= rd_int;
when "001" =>
-- sta
reg_rdat_int(15 downto 0) <= fmc_adc_100ms_ch_i.sta_val;
rd_ack1_int <= rd_int;
when "010" =>
-- calib
reg_rdat_int(15 downto 0) <= calib_gain_reg;
reg_rdat_int(31 downto 16) <= calib_offset_reg;
rd_ack1_int <= rd_int;
when "011" =>
-- sat
reg_rdat_int(14 downto 0) <= sat_val_reg;
rd_ack1_int <= rd_int;
when "100" =>
-- trig_thres
reg_rdat_int(15 downto 0) <= trig_thres_val_reg;
reg_rdat_int(31 downto 16) <= trig_thres_hyst_reg;
rd_ack1_int <= rd_int;
when "101" =>
-- trig_dly
reg_rdat_int <= trig_dly_reg;
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
end if;
end if;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
case wb_i.adr(4 downto 2) is
when "000" =>
-- ctl
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "001" =>
-- sta
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "010" =>
-- calib
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "011" =>
-- sat
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "100" =>
-- trig_thres
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "101" =>
-- trig_dly
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
end process;
end syn;
hdl/cheby/fmc_adc_100Ms_csr.cheby
View file @ 162b78cd
This diff is collapsed.
hdl/cheby/fmc_adc_100Ms_csr.vhd
View file @ 162b78cd
This diff is collapsed.
hdl/rtl/Manifest.py
View file @ 162b78cd
......@@ -8,6 +8,7 @@ files = [
"timetag_core.vhd",
"../cheby/fmc_adc_mezzanine_mmap.vhd",
"../cheby/fmc_adc_100Ms_csr.vhd",
"../cheby/fmc_adc_100Ms_channel_regs.vhd",
"../cheby/fmc_adc_eic_regs.vhd",
"../cheby/fmc_adc_aux_trigin.vhd",
"../cheby/fmc_adc_aux_trigout.vhd",
......
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ 162b78cd
......@@ -38,6 +38,7 @@ use work.genram_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_100ms_csr_pkg.all;
use work.fmc_adc_100ms_channel_regs_pkg.all;
entity fmc_adc_100Ms_core is
generic (
......@@ -136,6 +137,11 @@ architecture rtl of fmc_adc_100Ms_core is
type t_fmc_adc_vec32_array is array (positive range<>) of std_logic_vector(31 downto 0);
type t_fmc_adc_uint32_array is array (positive range<>) of unsigned(31 downto 0);
type t_fmc_adc_channel_regin_array is array (1 to 4) of t_fmc_adc_100ms_ch_master_in;
type t_fmc_adc_channel_regout_array is array (1 to 4) of t_fmc_adc_100ms_ch_master_out;
type t_fmc_adc_channel_wbin_array is array (1 to 4) of t_wishbone_slave_in;
type t_fmc_adc_channel_wbout_array is array (1 to 4) of t_wishbone_slave_out;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
......@@ -313,20 +319,28 @@ architecture rtl of fmc_adc_100Ms_core is
signal trig_addr : std_logic_vector(31 downto 0);
signal mem_ovr : std_logic;
-- IO from CSR registers
signal csr_regin : t_fmc_adc_100ms_csr_master_in;
signal csr_regout : t_fmc_adc_100ms_csr_master_out;
-- LEDs
signal trig_led : std_logic;
signal trig_led_man : std_logic;
signal acq_led : std_logic;
signal acq_led_man : std_logic;
-- IO from CSR registers
signal csr_regin : t_fmc_adc_100ms_csr_master_in;
signal csr_regout : t_fmc_adc_100ms_csr_master_out;
-- IO from channel registers
signal channel_regin : t_fmc_adc_channel_regin_array;
signal channel_regout : t_fmc_adc_channel_regout_array;
-- from/to wb slave adapters
signal wb_csr_in : t_wishbone_slave_in;
signal wb_csr_out : t_wishbone_slave_out;
-- CSR <-> channel regs wishbone interfaces
signal wb_channel_in : t_fmc_adc_channel_wbin_array;
signal wb_channel_out : t_fmc_adc_channel_wbout_array;
begin
------------------------------------------------------------------------------
......@@ -469,7 +483,15 @@ begin
wb_i => wb_csr_in,
wb_o => wb_csr_out,
fmc_adc_100Ms_csr_i => csr_regin,
fmc_adc_100Ms_csr_o => csr_regout);
fmc_adc_100Ms_csr_o => csr_regout,
fmc_adc_ch1_i => wb_channel_out(1),
fmc_adc_ch1_o => wb_channel_in(1),
fmc_adc_ch2_i => wb_channel_out(2),
fmc_adc_ch2_o => wb_channel_in(2),
fmc_adc_ch3_i => wb_channel_out(3),
fmc_adc_ch3_o => wb_channel_in(3),
fmc_adc_ch4_i => wb_channel_out(4),
fmc_adc_ch4_o => wb_channel_in(4));
csr_regin.sta_fsm <= acq_fsm_state;
csr_regin.sta_serdes_pll <= serdes_locked_sync;
......@@ -490,10 +512,6 @@ begin
csr_regin.trig_pos <= trig_addr;
csr_regin.fs_freq <= fs_freq;
csr_regin.samples_cnt <= std_logic_vector(samples_cnt);
csr_regin.ch1_sta_val <= serdes_out_data_synced(15 downto 0);
csr_regin.ch2_sta_val <= serdes_out_data_synced(31 downto 16);
csr_regin.ch3_sta_val <= serdes_out_data_synced(47 downto 32);
csr_regin.ch4_sta_val <= serdes_out_data_synced(63 downto 48);
csr_regin.multi_depth <= c_MULTISHOT_SAMPLE_DEPTH;
ctl_reg_wr <= csr_regout.ctl_wr;
......@@ -504,10 +522,6 @@ begin
acq_led_man <= csr_regout.ctl_acq_led;
trig_storage_clear <= csr_regout.ctl_clear_trig_stat and ctl_reg_wr;
sync_calib_apply <= csr_regout.ctl_calib_apply and ctl_reg_wr;
int_trig_delay_in(1) <= csr_regout.ch1_trig_dly;
int_trig_delay_in(2) <= csr_regout.ch2_trig_dly;
int_trig_delay_in(3) <= csr_regout.ch3_trig_dly;
int_trig_delay_in(4) <= csr_regout.ch4_trig_dly;
int_trig_en_in(1) <= csr_regout.trig_en_ch1;
int_trig_en_in(2) <= csr_regout.trig_en_ch2;
int_trig_en_in(3) <= csr_regout.trig_en_ch3;
......@@ -516,39 +530,45 @@ begin
int_trig_pol_in(2) <= csr_regout.trig_pol_ch2;
int_trig_pol_in(3) <= csr_regout.trig_pol_ch3;
int_trig_pol_in(4) <= csr_regout.trig_pol_ch4;
int_trig_thres_in(1) <= csr_regout.ch1_trig_thres_val;
int_trig_thres_in(2) <= csr_regout.ch2_trig_thres_val;
int_trig_thres_in(3) <= csr_regout.ch3_trig_thres_val;
int_trig_thres_in(4) <= csr_regout.ch4_trig_thres_val;
int_trig_thres_hyst_in(1) <= csr_regout.ch1_trig_thres_hyst;
int_trig_thres_hyst_in(2) <= csr_regout.ch2_trig_thres_hyst;
int_trig_thres_hyst_in(3) <= csr_regout.ch3_trig_thres_hyst;
int_trig_thres_hyst_in(4) <= csr_regout.ch4_trig_thres_hyst;
shots_value <= csr_regout.shots_nbr;
pre_trig_value <= csr_regout.pre_samples;
post_trig_value <= csr_regout.post_samples;
sync_calib_in <= csr_regout.ch4_calib_offset & csr_regout.ch3_calib_offset &
csr_regout.ch2_calib_offset & csr_regout.ch1_calib_offset &
csr_regout.ch4_calib_gain & csr_regout.ch3_calib_gain &
csr_regout.ch2_calib_gain & csr_regout.ch1_calib_gain;
sat_val_in <= csr_regout.ch4_sat_val & csr_regout.ch3_sat_val &
csr_regout.ch2_sat_val & csr_regout.ch1_sat_val;
-- Delays for user-controlled GPIO outputs to help with timing
p_delay_gpio_ssr : process (sys_clk_i) is
begin
if rising_edge(sys_clk_i) then
gpio_si570_oe_o <= csr_regout.ctl_fmc_clk_oe;
gpio_dac_clr_n_o <= csr_regout.ctl_offset_dac_clr_n;
gpio_ssr_ch1_o <= csr_regout.ch1_ctl_ssr;
gpio_ssr_ch2_o <= csr_regout.ch2_ctl_ssr;
gpio_ssr_ch3_o <= csr_regout.ch3_ctl_ssr;
gpio_ssr_ch4_o <= csr_regout.ch4_ctl_ssr;
gpio_ssr_ch1_o <= channel_regout(1).ctl_ssr;
gpio_ssr_ch2_o <= channel_regout(2).ctl_ssr;
gpio_ssr_ch3_o <= channel_regout(3).ctl_ssr;
gpio_ssr_ch4_o <= channel_regout(4).ctl_ssr;
end if;
end process p_delay_gpio_ssr;
-- Channel registers' submaps
gen_ch_reg_submap : for I in 1 to 4 generate
fmc_adc_100ms_channel_regs_1 : entity work.fmc_adc_100ms_channel_regs
port map (
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
wb_i => wb_channel_in(I),
wb_o => wb_channel_out(I),
fmc_adc_100ms_ch_i => channel_regin(I),
fmc_adc_100ms_ch_o => channel_regout(I));
channel_regin(I).sta_val <= serdes_out_data_synced((16*I)-1 downto 16*(I-1));
int_trig_delay_in(I) <= channel_regout(I).trig_dly;
int_trig_thres_in(I) <= channel_regout(I).trig_thres_val;
int_trig_thres_hyst_in(I) <= channel_regout(I).trig_thres_hyst;
sync_calib_in(64+(16*I)-1 downto 64+16*(I-1)) <= channel_regout(I).calib_offset;
sync_calib_in((16*I)-1 downto 16*(I-1)) <= channel_regout(I).calib_gain;
sat_val_in((15*I)-1 downto 15*(I-1)) <= channel_regout(I).sat_val;
end generate gen_ch_reg_submap;
cmp_ext_trig_en_sync : gc_sync
port map (
clk_i => fs_clk,
......
hdl/testbench/include/fmc_adc_100Ms_channel_regs.v 0 → 100644
View file @ 162b78cd
`define FMC_ADC_100MS_CHANNEL_REGS_SIZE 24
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_CTL 'h0
`define FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR 'h7f
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_STA 'h4
`define FMC_ADC_100MS_CHANNEL_REGS_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CHANNEL_REGS_STA_VAL 'hffff
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_CALIB 'h8
`define FMC_ADC_100MS_CHANNEL_REGS_CALIB_GAIN_OFFSET 0
`define FMC_ADC_100MS_CHANNEL_REGS_CALIB_GAIN 'hffff
`define FMC_ADC_100MS_CHANNEL_REGS_CALIB_OFFSET_OFFSET 16
`define FMC_ADC_100MS_CHANNEL_REGS_CALIB_OFFSET 'hffff0000
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_SAT 'hc
`define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL 'h7fff
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES 'h10
`define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_VAL 'hffff
`define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_HYST 'hffff0000
`define ADDR_FMC_ADC_100MS_CHANNEL_REGS_TRIG_DLY 'h14
hdl/testbench/include/fmc_adc_100Ms_csr.v
View file @ 162b78cd
......@@ -88,83 +88,11 @@
`define ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES 'h30
`define ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES 'h34
`define ADDR_FMC_ADC_100MS_CSR_SAMPLES_CNT 'h38
`define ADDR_FMC_ADC_100MS_CSR_CH1_CTL 'h80
`define FMC_ADC_100MS_CSR_CH1_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_CTL_SSR 'h7f
`define ADDR_FMC_ADC_100MS_CSR_CH1_STA 'h84
`define FMC_ADC_100MS_CSR_CH1_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_STA_VAL 'hffff
`define ADDR_FMC_ADC_100MS_CSR_CH1_CALIB 'h88
`define FMC_ADC_100MS_CSR_CH1_CALIB_GAIN_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_CALIB_GAIN 'hffff
`define FMC_ADC_100MS_CSR_CH1_CALIB_OFFSET_OFFSET 16
`define FMC_ADC_100MS_CSR_CH1_CALIB_OFFSET 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH1_SAT 'h8c
`define FMC_ADC_100MS_CSR_CH1_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_SAT_VAL 'h7fff
`define ADDR_FMC_ADC_100MS_CSR_CH1_TRIG_THRES 'h90
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL 'hffff
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH1_TRIG_DLY 'h94
`define ADDR_FMC_ADC_100MS_CSR_CH2_CTL 'hc0
`define FMC_ADC_100MS_CSR_CH2_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_CTL_SSR 'h7f
`define ADDR_FMC_ADC_100MS_CSR_CH2_STA 'hc4
`define FMC_ADC_100MS_CSR_CH2_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_STA_VAL 'hffff
`define ADDR_FMC_ADC_100MS_CSR_CH2_CALIB 'hc8
`define FMC_ADC_100MS_CSR_CH2_CALIB_GAIN_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_CALIB_GAIN 'hffff
`define FMC_ADC_100MS_CSR_CH2_CALIB_OFFSET_OFFSET 16
`define FMC_ADC_100MS_CSR_CH2_CALIB_OFFSET 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH2_SAT 'hcc
`define FMC_ADC_100MS_CSR_CH2_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_SAT_VAL 'h7fff
`define ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_THRES 'hd0
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL 'hffff
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_DLY 'hd4
`define ADDR_FMC_ADC_100MS_CSR_CH3_CTL 'h100
`define FMC_ADC_100MS_CSR_CH3_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_CTL_SSR 'h7f
`define ADDR_FMC_ADC_100MS_CSR_CH3_STA 'h104
`define FMC_ADC_100MS_CSR_CH3_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_STA_VAL 'hffff
`define ADDR_FMC_ADC_100MS_CSR_CH3_CALIB 'h108
`define FMC_ADC_100MS_CSR_CH3_CALIB_GAIN_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_CALIB_GAIN 'hffff
`define FMC_ADC_100MS_CSR_CH3_CALIB_OFFSET_OFFSET 16
`define FMC_ADC_100MS_CSR_CH3_CALIB_OFFSET 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH3_SAT 'h10c
`define FMC_ADC_100MS_CSR_CH3_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_SAT_VAL 'h7fff
`define ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_THRES 'h110
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL 'hffff
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_DLY 'h114
`define ADDR_FMC_ADC_100MS_CSR_CH4_CTL 'h140
`define FMC_ADC_100MS_CSR_CH4_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_CTL_SSR 'h7f
`define ADDR_FMC_ADC_100MS_CSR_CH4_STA 'h144
`define FMC_ADC_100MS_CSR_CH4_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_STA_VAL 'hffff
`define ADDR_FMC_ADC_100MS_CSR_CH4_CALIB 'h148
`define FMC_ADC_100MS_CSR_CH4_CALIB_GAIN_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_CALIB_GAIN 'hffff
`define FMC_ADC_100MS_CSR_CH4_CALIB_OFFSET_OFFSET 16
`define FMC_ADC_100MS_CSR_CH4_CALIB_OFFSET 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH4_SAT 'h14c
`define FMC_ADC_100MS_CSR_CH4_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_SAT_VAL 'h7fff
`define ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_THRES 'h150
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL 'hffff
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_DLY 'h154
`define ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH1 'h80
`define FMC_ADC_100MS_CSR_FMC_ADC_CH1_SIZE 32
`define ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH2 'hc0
`define FMC_ADC_100MS_CSR_FMC_ADC_CH2_SIZE 32
`define ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH3 'h100
`define FMC_ADC_100MS_CSR_FMC_ADC_CH3_SIZE 32
`define ADDR_FMC_ADC_100MS_CSR_FMC_ADC_CH4 'h140
`define FMC_ADC_100MS_CSR_FMC_ADC_CH4_SIZE 32
software/include/hw/fmc_adc_100Ms_channel_regs.h 0 → 100644
View file @ 162b78cd
#ifndef __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__
#define __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__
#define FMC_ADC_100MS_CHANNEL_REGS_SIZE 24
/* Channel control register */
#define FMC_ADC_100MS_CHANNEL_REGS_CTL 0x0UL
#define FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR_MASK 0x7fUL
#define FMC_ADC_100MS_CHANNEL_REGS_CTL_SSR_SHIFT 0
/* Channel status register */
#define FMC_ADC_100MS_CHANNEL_REGS_STA 0x4UL
#define FMC_ADC_100MS_CHANNEL_REGS_STA_VAL_MASK 0xffffUL
#define FMC_ADC_100MS_CHANNEL_REGS_STA_VAL_SHIFT 0
/* Channel calibration register */
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB 0x8UL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_GAIN_MASK 0xffffUL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_GAIN_SHIFT 0
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_OFFSET_MASK 0xffff0000UL
#define FMC_ADC_100MS_CHANNEL_REGS_CALIB_OFFSET_SHIFT 16
/* Channel saturation register */
#define FMC_ADC_100MS_CHANNEL_REGS_SAT 0xcUL
#define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_MASK 0x7fffUL
#define FMC_ADC_100MS_CHANNEL_REGS_SAT_VAL_SHIFT 0
/* Channel trigger threshold configuration register */
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES 0x10UL
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_VAL_MASK 0xffffUL
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_HYST_MASK 0xffff0000UL
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_THRES_HYST_SHIFT 16
/* Channel trigger delay */
#define FMC_ADC_100MS_CHANNEL_REGS_TRIG_DLY 0x14UL
struct fmc_adc_100ms_channel_regs {
/* [0x0]: REG (rw) Channel control register */
uint32_t ctl;
/* [0x4]: REG (ro) Channel status register */
uint32_t sta;
/* [0x8]: REG (rw) Channel calibration register */
uint32_t calib;
/* [0xc]: REG (rw) Channel saturation register */
uint32_t sat;
/* [0x10]: REG (rw) Channel trigger threshold configuration register */
uint32_t trig_thres;
/* [0x14]: REG (rw) Channel trigger delay */
uint32_t trig_dly;
};
#endif /* __CHEBY__FMC_ADC_100MS_CHANNEL_REGS__H__ */
software/include/hw/fmc_adc_100Ms_csr.h
View file @ 162b78cd
#ifndef __CHEBY__FMC_ADC_100MS_CSR__H__
#define __CHEBY__FMC_ADC_100MS_CSR__H__
#include "fmc_adc_100ms_channel_regs.h"
#define FMC_ADC_100MS_CSR_SIZE 512
/* Control register */
......@@ -89,133 +91,21 @@
/* Samples counter */
#define FMC_ADC_100MS_CSR_SAMPLES_CNT 0x38UL
/* Channel 1 control register */
#define FMC_ADC_100MS_CSR_CH1_CTL 0x80UL
#define FMC_ADC_100MS_CSR_CH1_CTL_SSR_MASK 0x7fUL
#define FMC_ADC_100MS_CSR_CH1_CTL_SSR_SHIFT 0
/* Channel 1 status register */
#define FMC_ADC_100MS_CSR_CH1_STA 0x84UL
#define FMC_ADC_100MS_CSR_CH1_STA_VAL_MASK 0xffffUL
#define FMC_ADC_100MS_CSR_CH1_STA_VAL_SHIFT 0
/* Channel 1 calibration register */
#define FMC_ADC_100MS_CSR_CH1_CALIB 0x88UL
#define FMC_ADC_100MS_CSR_CH1_CALIB_GAIN_MASK 0xffffUL
#define FMC_ADC_100MS_CSR_CH1_CALIB_GAIN_SHIFT 0
#define FMC_ADC_100MS_CSR_CH1_CALIB_OFFSET_MASK 0xffff0000UL
#define FMC_ADC_100MS_CSR_CH1_CALIB_OFFSET_SHIFT 16
/* Channel 1 saturation register */
#define FMC_ADC_100MS_CSR_CH1_SAT 0x8cUL
#define FMC_ADC_100MS_CSR_CH1_SAT_VAL_MASK 0x7fffUL
#define FMC_ADC_100MS_CSR_CH1_SAT_VAL_SHIFT 0
/* Channel 1 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES 0x90UL
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_MASK 0xffffUL
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_MASK 0xffff0000UL
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_SHIFT 16
/* Channel 1 trigger delay */
#define FMC_ADC_100MS_CSR_CH1_TRIG_DLY 0x94UL
/* Channel 2 control register */
#define FMC_ADC_100MS_CSR_CH2_CTL 0xc0UL
#define FMC_ADC_100MS_CSR_CH2_CTL_SSR_MASK 0x7fUL
#define FMC_ADC_100MS_CSR_CH2_CTL_SSR_SHIFT 0
/* Channel 2 status register */
#define FMC_ADC_100MS_CSR_CH2_STA 0xc4UL
#define FMC_ADC_100MS_CSR_CH2_STA_VAL_MASK 0xffffUL
#define FMC_ADC_100MS_CSR_CH2_STA_VAL_SHIFT 0
/* Channel 2 calibration register */
#define FMC_ADC_100MS_CSR_CH2_CALIB 0xc8UL
#define FMC_ADC_100MS_CSR_CH2_CALIB_GAIN_MASK 0xffffUL
#define FMC_ADC_100MS_CSR_CH2_CALIB_GAIN_SHIFT 0
#define FMC_ADC_100MS_CSR_CH2_CALIB_OFFSET_MASK 0xffff0000UL
#define FMC_ADC_100MS_CSR_CH2_CALIB_OFFSET_SHIFT 16
/* Channel 2 saturation register */
#define FMC_ADC_100MS_CSR_CH2_SAT 0xccUL
#define FMC_ADC_100MS_CSR_CH2_SAT_VAL_MASK 0x7fffUL
#define FMC_ADC_100MS_CSR_CH2_SAT_VAL_SHIFT 0
/* Channel 2 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES 0xd0UL
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL_MASK 0xffffUL
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_MASK 0xffff0000UL
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_SHIFT 16
/* Channel 2 trigger delay */
#define FMC_ADC_100MS_CSR_CH2_TRIG_DLY 0xd4UL
/* Channel 3 control register */
#define FMC_ADC_100MS_CSR_CH3_CTL 0x100UL
#define FMC_ADC_100MS_CSR_CH3_CTL_SSR_MASK 0x7fUL
#define FMC_ADC_100MS_CSR_CH3_CTL_SSR_SHIFT 0
/* Channel 3 status register */
#define FMC_ADC_100MS_CSR_CH3_STA 0x104UL
#define FMC_ADC_100MS_CSR_CH3_STA_VAL_MASK 0xffffUL
#define FMC_ADC_100MS_CSR_CH3_STA_VAL_SHIFT 0
/* Channel 3 calibration register */
#define FMC_ADC_100MS_CSR_CH3_CALIB 0x108UL
#define FMC_ADC_100MS_CSR_CH3_CALIB_GAIN_MASK 0xffffUL
#define FMC_ADC_100MS_CSR_CH3_CALIB_GAIN_SHIFT 0
#define FMC_ADC_100MS_CSR_CH3_CALIB_OFFSET_MASK 0xffff0000UL
#define FMC_ADC_100MS_CSR_CH3_CALIB_OFFSET_SHIFT 16
/* Channel 3 saturation register */
#define FMC_ADC_100MS_CSR_CH3_SAT 0x10cUL
#define FMC_ADC_100MS_CSR_CH3_SAT_VAL_MASK 0x7fffUL
#define FMC_ADC_100MS_CSR_CH3_SAT_VAL_SHIFT 0
/* Channel 3 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES 0x110UL
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL_MASK 0xffffUL
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_MASK 0xffff0000UL
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_SHIFT 16
/* Channel 3 trigger delay */
#define FMC_ADC_100MS_CSR_CH3_TRIG_DLY 0x114UL
/* Channel 4 control register */
#define FMC_ADC_100MS_CSR_CH4_CTL 0x140UL
#define FMC_ADC_100MS_CSR_CH4_CTL_SSR_MASK 0x7fUL
#define FMC_ADC_100MS_CSR_CH4_CTL_SSR_SHIFT 0
/* Channel 4 status register */
#define FMC_ADC_100MS_CSR_CH4_STA 0x144UL
#define FMC_ADC_100MS_CSR_CH4_STA_VAL_MASK 0xffffUL
#define FMC_ADC_100MS_CSR_CH4_STA_VAL_SHIFT 0
/* Channel 4 gain calibration register */
#define FMC_ADC_100MS_CSR_CH4_CALIB 0x148UL
#define FMC_ADC_100MS_CSR_CH4_CALIB_GAIN_MASK 0xffffUL
#define FMC_ADC_100MS_CSR_CH4_CALIB_GAIN_SHIFT 0
#define FMC_ADC_100MS_CSR_CH4_CALIB_OFFSET_MASK 0xffff0000UL
#define FMC_ADC_100MS_CSR_CH4_CALIB_OFFSET_SHIFT 16
/* Channel 4 saturation register */
#define FMC_ADC_100MS_CSR_CH4_SAT 0x14cUL
#define FMC_ADC_100MS_CSR_CH4_SAT_VAL_MASK 0x7fffUL
#define FMC_ADC_100MS_CSR_CH4_SAT_VAL_SHIFT 0
/* Channel 4 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES 0x150UL
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL_MASK 0xffffUL
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_MASK 0xffff0000UL
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_SHIFT 16
/* Channel 4 trigger delay */
#define FMC_ADC_100MS_CSR_CH4_TRIG_DLY 0x154UL
/* Channel 1 registers */
#define FMC_ADC_100MS_CSR_FMC_ADC_CH1 0x80UL
#define FMC_ADC_100MS_CSR_FMC_ADC_CH1_SIZE 32
/* Channel 2 registers */
#define FMC_ADC_100MS_CSR_FMC_ADC_CH2 0xc0UL
#define FMC_ADC_100MS_CSR_FMC_ADC_CH2_SIZE 32
/* Channel 3 registers */
#define FMC_ADC_100MS_CSR_FMC_ADC_CH3 0x100UL
#define FMC_ADC_100MS_CSR_FMC_ADC_CH3_SIZE 32
/* Channel 4 registers */
#define FMC_ADC_100MS_CSR_FMC_ADC_CH4 0x140UL
#define FMC_ADC_100MS_CSR_FMC_ADC_CH4_SIZE 32
struct fmc_adc_100ms_csr {
/* [0x0]: REG (rw) Control register */
......@@ -266,89 +156,29 @@ struct fmc_adc_100ms_csr {
/* padding to: 32 words */
uint32_t __padding_0[17];
/* [0x80]: REG (rw) Channel 1 control register */
uint32_t ch1_ctl;
/* [0x84]: REG (ro) Channel 1 status register */
uint32_t ch1_sta;
/* [0x88]: REG (rw) Channel 1 calibration register */
uint32_t ch1_calib;
/* [0x8c]: REG (rw) Channel 1 saturation register */
uint32_t ch1_sat;
/* [0x90]: REG (rw) Channel 1 trigger threshold configuration register */
uint32_t ch1_trig_thres;
/* [0x94]: REG (rw) Channel 1 trigger delay */
uint32_t ch1_trig_dly;
/* [0x80]: SUBMAP Channel 1 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch1;
/* padding to: 48 words */
uint32_t __padding_1[10];
/* [0xc0]: REG (rw) Channel 2 control register */
uint32_t ch2_ctl;
/* [0xc4]: REG (ro) Channel 2 status register */
uint32_t ch2_sta;
/* [0xc8]: REG (rw) Channel 2 calibration register */
uint32_t ch2_calib;
/* [0xcc]: REG (rw) Channel 2 saturation register */
uint32_t ch2_sat;
uint32_t __padding_1[8];
/* [0xd0]: REG (rw) Channel 2 trigger threshold configuration register */
uint32_t ch2_trig_thres;
/* [0xd4]: REG (rw) Channel 2 trigger delay */
uint32_t ch2_trig_dly;
/* [0xc0]: SUBMAP Channel 2 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch2;
/* padding to: 64 words */
uint32_t __padding_2[10];
/* [0x100]: REG (rw) Channel 3 control register */
uint32_t ch3_ctl;
/* [0x104]: REG (ro) Channel 3 status register */
uint32_t ch3_sta;
/* [0x108]: REG (rw) Channel 3 calibration register */
uint32_t ch3_calib;
/* [0x10c]: REG (rw) Channel 3 saturation register */
uint32_t ch3_sat;
/* [0x110]: REG (rw) Channel 3 trigger threshold configuration register */
uint32_t ch3_trig_thres;
uint32_t __padding_2[8];
/* [0x114]: REG (rw) Channel 3 trigger delay */
uint32_t ch3_trig_dly;
/* [0x100]: SUBMAP Channel 3 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch3;
/* padding to: 80 words */
uint32_t __padding_3[10];
uint32_t __padding_3[8];
/* [0x140]: REG (rw) Channel 4 control register */
uint32_t ch4_ctl;
/* [0x140]: SUBMAP Channel 4 registers */
struct fmc_adc_100ms_channel_regs fmc_adc_ch4;
/* [0x144]: REG (ro) Channel 4 status register */
uint32_t ch4_sta;
/* [0x148]: REG (rw) Channel 4 gain calibration register */
uint32_t ch4_calib;
/* [0x14c]: REG (rw) Channel 4 saturation register */
uint32_t ch4_sat;
/* [0x150]: REG (rw) Channel 4 trigger threshold configuration register */
uint32_t ch4_trig_thres;
/* [0x154]: REG (rw) Channel 4 trigger delay */
uint32_t ch4_trig_dly;
/* padding to: 85 words */
uint32_t __padding_4[42];
/* padding to: 80 words */
uint32_t __padding_4[40];
};
#endif /* __CHEBY__FMC_ADC_100MS_CSR__H__ */
software/include/hw/fmc_adc_mezzanine_mmap.h
View file @ 162b78cd
#ifndef __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__
#define __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__
#include "timetag_core_regs.h"
#include "fmc_adc_eic_regs.h"
#include "wb_ds182x_regs.h"
#include "fmc_adc_eic_regs.h"
#include "fmc_adc_100ms_csr.h"
#include "timetag_core_regs.h"
#define FMC_ADC_MEZZANINE_MMAP_SIZE 8192
/* FMC ADC 100M CSR */
......
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