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FMC ADC 100M 14b 4cha - Gateware
Commit 12621ca0 authored by mcattin's avatar mcattin
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Add acq_end output to adc_core for irq and time-tag. 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@89 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent e948330f
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Showing with 1528 additions and 44 deletions
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ 12621ca0
......@@ -62,6 +62,7 @@ entity fmc_adc_100Ms_core is
trigger_p_o : out std_logic;
acq_start_p_o : out std_logic;
acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
......@@ -334,6 +335,7 @@ architecture rtl of fmc_adc_100Ms_core is
signal acq_stop : std_logic;
signal acq_trig : std_logic;
signal acq_end : std_logic;
signal acq_end_d : std_logic;
signal acq_in_pre_trig : std_logic;
signal acq_in_post_trig : std_logic;
signal samples_wr_en : std_logic;
......@@ -876,6 +878,20 @@ begin
acq_start_p_o <= acq_start;
acq_stop_p_o <= acq_stop;
-- End of acquisition pulse generation
p_acq_end: process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' then
acq_end_d <= '0';
else
acq_end_d <= acq_end;
end if;
end if;
end process p_acq_end;
acq_end_p_o <= acq_end and not(acq_end_d);
-- FSM commands
acq_start <= '1' when fsm_cmd_wr = '1' and fsm_cmd = "01" else '0';
acq_stop <= '1' when fsm_cmd_wr = '1' and fsm_cmd = "10" else '0';
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ 12621ca0
......@@ -228,6 +228,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
trigger_p_i : in std_logic;
acq_start_p_i : in std_logic;
acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
......@@ -287,6 +288,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
trigger_p_o : out std_logic;
acq_start_p_o : out std_logic;
acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
......@@ -416,6 +418,8 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal wb_ddr_stall : std_logic;
-- Interrupts stuff
signal dma_irq : std_logic_vector(1 downto 0);
signal dma_irq_p : std_logic_vector(1 downto 0);
signal irq_sources : std_logic_vector(31 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_sources_2_led : std_logic_vector(1 downto 0);
......@@ -473,6 +477,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal trigger_p : std_logic;
signal acq_start_p : std_logic;
signal acq_stop_p : std_logic;
signal acq_end_p : std_logic;
-- Tests
signal test_dpram_we : std_logic;
......@@ -594,7 +599,7 @@ begin
tx_error_i => TX_ERROR,
vc_rdy_i => VC_RDY,
-- Interrupt interface
dma_irq_o => irq_sources(1 downto 0),
dma_irq_o => dma_irq,
irq_p_i => irq_to_gn4124,
irq_p_o => GPIO(0),
-- DMA registers wishbone interface (slave classic)
......@@ -714,8 +719,8 @@ begin
owr_i => carrier_owr_i
);
carrier_one_wire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
carrier_owr_i(0) <= carrier_one_wire_b;
carrier_one_wire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
carrier_owr_i(0) <= carrier_one_wire_b;
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_CARRIER_ONE_WIRE) <= '0';
......@@ -782,8 +787,9 @@ begin
trigger_p_i => trigger_p,
acq_start_p_i => acq_start_p,
acq_stop_p_i => acq_stop_p,
acq_end_p_i => acq_end_p,
wb_adr_i => wb_adr(3 downto 0),
wb_adr_i => wb_adr(4 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_UTC_CORE * 32 + 31 downto c_CSR_WB_UTC_CORE * 32),
wb_cyc_i => wb_cyc(c_CSR_WB_UTC_CORE),
......@@ -821,8 +827,14 @@ begin
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_IRQ_CTRL) <= '0';
-- IRQ sources
irq_sources(1 downto 0) <= dma_irq;
irq_sources(2) <= trigger_p;
irq_sources(3) <= acq_end_p;
irq_sources(31 downto 4) <= (others => '0');
-- just forward irq pulses for test
--irq_to_gn4124 <= irq_sources(1) or irq_sources(0);
--irq_to_gn4124 <= dma_irq(1) or dma_irq(0);
------------------------------------------------------------------------------
-- Mezzanine system managment I2C master
......@@ -983,6 +995,7 @@ begin
trigger_p_o => trigger_p,
acq_start_p_o => acq_start_p,
acq_stop_p_o => acq_stop_p,
acq_end_p_o => acq_end_p,
ext_trigger_p_i => ext_trigger_p_i,
ext_trigger_n_i => ext_trigger_n_i,
......
hdl/spec/rtl/utc_core.vhd
View file @ 12621ca0
......@@ -42,9 +42,10 @@ entity utc_core is
trigger_p_i : in std_logic;
acq_start_p_i : in std_logic;
acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic;
-- Wishbone interface
wb_adr_i : in std_logic_vector(3 downto 0);
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -66,7 +67,7 @@ architecture rtl of utc_core is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -91,7 +92,11 @@ architecture rtl of utc_core is
utc_core_acq_stop_tag_meta_i : in std_logic_vector(31 downto 0);
utc_core_acq_stop_tag_seconds_i : in std_logic_vector(31 downto 0);
utc_core_acq_stop_tag_coarse_i : in std_logic_vector(31 downto 0);
utc_core_acq_stop_tag_fine_i : in std_logic_vector(31 downto 0)
utc_core_acq_stop_tag_fine_i : in std_logic_vector(31 downto 0);
utc_core_acq_end_tag_meta_i : in std_logic_vector(31 downto 0);
utc_core_acq_end_tag_seconds_i : in std_logic_vector(31 downto 0);
utc_core_acq_end_tag_coarse_i : in std_logic_vector(31 downto 0);
utc_core_acq_end_tag_fine_i : in std_logic_vector(31 downto 0)
);
end component utc_core_regs;
......@@ -118,6 +123,10 @@ architecture rtl of utc_core is
signal utc_acq_stop_tag_seconds : std_logic_vector(31 downto 0);
signal utc_acq_stop_tag_coarse : std_logic_vector(31 downto 0);
signal utc_acq_stop_tag_fine : std_logic_vector(31 downto 0);
signal utc_acq_end_tag_meta : std_logic_vector(31 downto 0);
signal utc_acq_end_tag_seconds : std_logic_vector(31 downto 0);
signal utc_acq_end_tag_coarse : std_logic_vector(31 downto 0);
signal utc_acq_end_tag_fine : std_logic_vector(31 downto 0);
signal local_pps : std_logic;
......@@ -157,7 +166,11 @@ begin
utc_core_acq_stop_tag_meta_i => utc_acq_stop_tag_meta,
utc_core_acq_stop_tag_seconds_i => utc_acq_stop_tag_seconds,
utc_core_acq_stop_tag_coarse_i => utc_acq_stop_tag_coarse,
utc_core_acq_stop_tag_fine_i => utc_acq_stop_tag_fine
utc_core_acq_stop_tag_fine_i => utc_acq_stop_tag_fine,
utc_core_acq_end_tag_meta_i => utc_acq_end_tag_meta,
utc_core_acq_end_tag_seconds_i => utc_acq_end_tag_seconds,
utc_core_acq_end_tag_coarse_i => utc_acq_end_tag_coarse,
utc_core_acq_end_tag_fine_i => utc_acq_end_tag_fine
);
------------------------------------------------------------------------------
......@@ -186,16 +199,16 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
utc_coarse_cnt <= (others => '0');
local_pps <= '0';
local_pps <= '0';
elsif utc_coarse_load_en = '1' then
utc_coarse_cnt <= unsigned(utc_coarse_load_value);
local_pps <= '0';
elsif utc_coarse_cnt = to_unsigned(1249999999,utc_coarse_cnt'length) then
local_pps <= '0';
elsif utc_coarse_cnt = to_unsigned(1249999999, utc_coarse_cnt'length) then
utc_coarse_cnt <= (others => '0');
local_pps <= '1';
local_pps <= '1';
else
utc_coarse_cnt <= utc_coarse_cnt + 1;
local_pps <= '0';
local_pps <= '0';
end if;
end if;
end process p_utc_coarse_cnt;
......@@ -210,11 +223,11 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
utc_trig_tag_seconds <= (others => '0');
utc_trig_tag_coarse <= (others => '0');
utc_trig_tag_fine <= (others => '0');
utc_trig_tag_coarse <= (others => '0');
utc_trig_tag_fine <= (others => '0');
elsif trigger_p_i = '1' then
utc_trig_tag_seconds <= utc_seconds;
utc_trig_tag_coarse <= utc_coarse;
utc_trig_tag_coarse <= utc_coarse;
end if;
end if;
end process p_trig_tag;
......@@ -229,11 +242,11 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
utc_acq_start_tag_seconds <= (others => '0');
utc_acq_start_tag_coarse <= (others => '0');
utc_acq_start_tag_fine <= (others => '0');
utc_acq_start_tag_coarse <= (others => '0');
utc_acq_start_tag_fine <= (others => '0');
elsif acq_start_p_i = '1' then
utc_acq_start_tag_seconds <= utc_seconds;
utc_acq_start_tag_coarse <= utc_coarse;
utc_acq_start_tag_coarse <= utc_coarse;
end if;
end if;
end process p_acq_start_tag;
......@@ -248,16 +261,35 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
utc_acq_stop_tag_seconds <= (others => '0');
utc_acq_stop_tag_coarse <= (others => '0');
utc_acq_stop_tag_fine <= (others => '0');
utc_acq_stop_tag_coarse <= (others => '0');
utc_acq_stop_tag_fine <= (others => '0');
elsif acq_stop_p_i = '1' then
utc_acq_stop_tag_seconds <= utc_seconds;
utc_acq_stop_tag_coarse <= utc_coarse;
utc_acq_stop_tag_coarse <= utc_coarse;
end if;
end if;
end process p_acq_stop_tag;
utc_acq_stop_tag_meta <= X"00000000";
------------------------------------------------------------------------------
-- Last acquisition end event time-tag
------------------------------------------------------------------------------
p_acq_end_tag : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
utc_acq_end_tag_seconds <= (others => '0');
utc_acq_end_tag_coarse <= (others => '0');
utc_acq_end_tag_fine <= (others => '0');
elsif acq_end_p_i = '1' then
utc_acq_end_tag_seconds <= utc_seconds;
utc_acq_end_tag_coarse <= utc_coarse;
end if;
end if;
end process p_acq_end_tag;
utc_acq_end_tag_meta <= X"00000000";
end rtl;
hdl/spec/rtl/utc_core_regs.vhd
View file @ 12621ca0
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/utc_core_regs.vhd
-- Author : auto-generated by wbgen2 from utc_core_regs.wb
-- Created : Thu Nov 17 14:30:00 2011
-- Created : Tue Nov 22 10:20:36 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE utc_core_regs.wb
......@@ -18,7 +18,7 @@ entity utc_core_regs is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -57,7 +57,15 @@ entity utc_core_regs is
-- Port for std_logic_vector field: 'Acquisition stop time-tag coarse time' in reg: 'Acquisition stop time-tag coarse time (system clock ticks 125MHz) register'
utc_core_acq_stop_tag_coarse_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag fine time' in reg: 'Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)'
utc_core_acq_stop_tag_fine_i : in std_logic_vector(31 downto 0)
utc_core_acq_stop_tag_fine_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition end time-tag metadata' in reg: 'Acquisition end time-tag metadata register'
utc_core_acq_end_tag_meta_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition end time-tag UTC seconds' in reg: 'Acquisition end time-tag UTC seconds register'
utc_core_acq_end_tag_seconds_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition end time-tag coarse time' in reg: 'Acquisition end time-tag coarse time (system clock ticks 125MHz) register'
utc_core_acq_end_tag_coarse_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition end time-tag fine time' in reg: 'Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility)'
utc_core_acq_end_tag_fine_i : in std_logic_vector(31 downto 0)
);
end utc_core_regs;
......@@ -67,7 +75,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -109,8 +117,8 @@ begin
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
utc_core_seconds_load_o <= '1';
else
......@@ -118,7 +126,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
when "00001" =>
if (wb_we_i = '1') then
utc_core_coarse_load_o <= '1';
else
......@@ -126,90 +134,118 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
when "00010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_meta_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
when "00011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_seconds_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
when "00100" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_coarse_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
when "00101" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_fine_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
when "00110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_meta_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
when "00111" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_seconds_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
when "01000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_coarse_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
when "01001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_fine_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
when "01010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_meta_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
when "01011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_seconds_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
when "01100" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_coarse_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1101" =>
when "01101" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_fine_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_meta_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_seconds_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_coarse_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_fine_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -239,6 +275,10 @@ begin
-- Acquisition stop time-tag UTC seconds
-- Acquisition stop time-tag coarse time
-- Acquisition stop time-tag fine time
-- Acquisition end time-tag metadata
-- Acquisition end time-tag UTC seconds
-- Acquisition end time-tag coarse time
-- Acquisition end time-tag fine time
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
......
hdl/spec/syn/spec_fmc_adc_100Ms.xise
View file @ 12621ca0
......@@ -1024,6 +1024,9 @@
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
</files>
<bindings/>
......
hdl/spec/wb_gen/utc_core_regs.h
View file @ 12621ca0
......@@ -3,7 +3,7 @@
* File : utc_core_regs.h
* Author : auto-generated by wbgen2 from utc_core_regs.wb
* Created : Thu Nov 17 14:30:00 2011
* Created : Tue Nov 22 10:20:36 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE utc_core_regs.wb
......@@ -59,6 +59,14 @@
/* definitions for register: Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility) */
/* definitions for register: Acquisition end time-tag metadata register */
/* definitions for register: Acquisition end time-tag UTC seconds register */
/* definitions for register: Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility) */
PACKED struct UTC_CORE_WB {
/* [0x0]: REG UTC seconds register */
uint32_t SECONDS;
......@@ -88,6 +96,14 @@ PACKED struct UTC_CORE_WB {
uint32_t ACQ_STOP_TAG_COARSE;
/* [0x34]: REG Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t ACQ_STOP_TAG_FINE;
/* [0x38]: REG Acquisition end time-tag metadata register */
uint32_t ACQ_END_TAG_META;
/* [0x3c]: REG Acquisition end time-tag UTC seconds register */
uint32_t ACQ_END_TAG_SECONDS;
/* [0x40]: REG Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_END_TAG_COARSE;
/* [0x44]: REG Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t ACQ_END_TAG_FINE;
};
#endif
hdl/spec/wb_gen/utc_core_regs.htm
View file @ 12621ca0
This diff is collapsed.
hdl/spec/wb_gen/utc_core_regs.wb
View file @ 12621ca0
......@@ -203,4 +203,60 @@ peripheral {
};
};
reg {
name = "Acquisition end time-tag metadata register";
prefix = "acq_end_tag_meta";
field {
name = "Acquisition end time-tag metadata";
description = "Holds time-tag metadata of the last acquisition end event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag UTC seconds register";
prefix = "acq_end_tag_seconds";
field {
name = "Acquisition end time-tag UTC seconds";
description = "Holds time-tag UTC seconds of the last acquisition end event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_end_tag_coarse";
field {
name = "Acquisition end time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition end event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility)";
prefix = "acq_end_tag_fine";
field {
name = "Acquisition end time-tag fine time";
description = "Holds time-tag fine time of the last acquisition end event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
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