hdl: update cheby-generated register blocks.

This is a manual edit to add 'X' initial values to the register read vector.

This helps a lot with the Xilinx implementation of the code (wrt timing).

This is automatically done by cheby-1.4, but a) it's not released yet and b) when tested,
it created other timing issues.

So for now we stay with cheby-1.3 and manual edit of the vhd files.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>