Commit 0fb16384 authored by mcattin's avatar mcattin

Add gain/offset calibration, fix pre/post trigger sample number.

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@97 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent 39353cd0
files = ["fmc_adc_100Ms_core.vhd",
"fmc_adc_100Ms_csr.vhd"]
"fmc_adc_100Ms_csr.vhd",
"offset_gain.vhd"]
......@@ -147,7 +147,7 @@ architecture rtl of fmc_adc_100Ms_core is
fmc_adc_core_sta_serdes_synced_i : in std_logic;
fmc_adc_core_sta_reserved_i : in std_logic_vector(26 downto 0);
fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic;
fmc_adc_core_trig_cfg_ext_trig_pol_o : out std_logic;
fmc_adc_core_trig_cfg_hw_trig_pol_o : out std_logic;
fmc_adc_core_trig_cfg_hw_trig_en_o : out std_logic;
fmc_adc_core_trig_cfg_sw_trig_en_o : out std_logic;
fmc_adc_core_trig_cfg_int_trig_sel_o : out std_logic_vector(1 downto 0);
......@@ -159,32 +159,43 @@ architecture rtl of fmc_adc_100Ms_core is
fmc_adc_core_shots_nb_o : out std_logic_vector(15 downto 0);
fmc_adc_core_shots_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0);
fmc_adc_core_gain_cal_o : out std_logic_vector(31 downto 0);
fmc_adc_core_offset_cal_o : out std_logic_vector(31 downto 0);
fmc_adc_core_reserved_0_i : in std_logic_vector(31 downto 0);
fmc_adc_core_reserved_1_i : in std_logic_vector(31 downto 0);
fmc_adc_core_reserved_2_i : in std_logic_vector(31 downto 0);
fmc_adc_core_sr_deci_o : out std_logic_vector(15 downto 0);
fmc_adc_core_sr_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_pre_samples_o : out std_logic_vector(31 downto 0);
fmc_adc_core_post_samples_o : out std_logic_vector(31 downto 0);
fmc_adc_core_samp_cnt_i : in std_logic_vector(31 downto 0);
fmc_adc_core_ch1_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch1_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch1_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch1_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch2_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch2_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch2_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch2_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch3_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch3_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch3_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch3_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch4_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch4_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch4_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch4_reserved_i : in std_logic_vector(15 downto 0)
fmc_adc_core_samples_cnt_i : in std_logic_vector(31 downto 0);
fmc_adc_core_ch1_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch1_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch1_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch1_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch1_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch1_offset_val_o : out std_logic_vector(16 downto 0);
fmc_adc_core_ch1_offset_reserved_o : out std_logic_vector(14 downto 0);
fmc_adc_core_ch2_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch2_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch2_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch2_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch2_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch2_offset_val_o : out std_logic_vector(16 downto 0);
fmc_adc_core_ch2_offset_reserved_o : out std_logic_vector(14 downto 0);
fmc_adc_core_ch3_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch3_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch3_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch3_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch3_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch3_offset_val_o : out std_logic_vector(16 downto 0);
fmc_adc_core_ch3_offset_reserved_o : out std_logic_vector(14 downto 0);
fmc_adc_core_ch4_ctl_ssr_o : out std_logic_vector(6 downto 0);
fmc_adc_core_ch4_ctl_reserved_o : out std_logic_vector(24 downto 0);
fmc_adc_core_ch4_sta_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch4_sta_reserved_i : in std_logic_vector(15 downto 0);
fmc_adc_core_ch4_gain_val_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_gain_reserved_o : out std_logic_vector(15 downto 0);
fmc_adc_core_ch4_offset_val_o : out std_logic_vector(16 downto 0);
fmc_adc_core_ch4_offset_reserved_o : out std_logic_vector(14 downto 0)
);
end component fmc_adc_100Ms_csr;
......@@ -207,6 +218,17 @@ architecture rtl of fmc_adc_100Ms_core is
);
end component ext_pulse_sync;
component offset_gain
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
offset_i : in std_logic_vector(16 downto 0); --! Signed offset input (two's complement)
gain_i : in std_logic_vector(15 downto 0); --! Unsigned gain input
data_i : in std_logic_vector(15 downto 0); --! Unsigned data input
data_o : out std_logic_vector(15 downto 0) --! Unsigned data output
);
end component offset_gain;
component adc_sync_fifo
port (
rst : in std_logic;
......@@ -296,6 +318,7 @@ architecture rtl of fmc_adc_100Ms_core is
signal serdes_in_n : std_logic_vector(8 downto 0);
signal serdes_out_raw : std_logic_vector(71 downto 0);
signal serdes_out_data : std_logic_vector(63 downto 0);
signal serdes_out_data_d : std_logic_vector(63 downto 0);
signal serdes_out_fr : std_logic_vector(7 downto 0);
signal serdes_auto_bitslip : std_logic;
signal serdes_man_bitslip : std_logic;
......@@ -304,24 +327,27 @@ architecture rtl of fmc_adc_100Ms_core is
signal bitslip_sreg : std_logic_vector(7 downto 0);
-- Trigger
signal ext_trig_a : std_logic;
signal ext_trig : std_logic;
signal int_trig : std_logic;
signal int_trig_sel : std_logic_vector(1 downto 0);
signal int_trig_thres : std_logic_vector(15 downto 0);
signal ext_trig_pol : std_logic;
signal hw_trig : std_logic;
signal hw_trig_t : std_logic;
signal hw_trig_sel : std_logic;
signal hw_trig_en : std_logic;
signal sw_trig : std_logic;
signal sw_trig_t : std_logic;
signal sw_trig_en : std_logic;
signal trig : std_logic;
signal trig_delay : std_logic_vector(31 downto 0);
signal trig_delay_cnt : unsigned(31 downto 0);
signal trig_d : std_logic;
signal trig_align : std_logic;
signal ext_trig_a : std_logic;
signal ext_trig : std_logic;
signal int_trig : std_logic;
signal int_trig_over_thres : std_logic;
signal int_trig_over_thres_d : std_logic;
signal int_trig_sel : std_logic_vector(1 downto 0);
signal int_trig_data : std_logic_vector(15 downto 0);
signal int_trig_thres : std_logic_vector(15 downto 0);
signal hw_trig_pol : std_logic;
signal hw_trig : std_logic;
signal hw_trig_t : std_logic;
signal hw_trig_sel : std_logic;
signal hw_trig_en : std_logic;
signal sw_trig : std_logic;
signal sw_trig_t : std_logic;
signal sw_trig_en : std_logic;
signal trig : std_logic;
signal trig_delay : std_logic_vector(31 downto 0);
signal trig_delay_cnt : unsigned(31 downto 0);
signal trig_d : std_logic;
signal trig_align : std_logic;
-- Decimation
signal decim_factor : std_logic_vector(15 downto 0);
......@@ -338,9 +364,11 @@ architecture rtl of fmc_adc_100Ms_core is
signal sync_fifo_valid : std_logic;
signal sync_fifo_dreq : std_logic;
-- Gain/offset calibration values
signal gain_calibr : std_logic_vector(31 downto 0);
signal offset_calibr : std_logic_vector(31 downto 0);
-- Gain/offset calibration
signal gain_calibr : std_logic_vector(63 downto 0);
signal offset_calibr : std_logic_vector(67 downto 0);
signal data_calibr_in : std_logic_vector(63 downto 0);
signal data_calibr_out : std_logic_vector(63 downto 0);
-- Acquisition FSM
signal acq_fsm_current_state : t_acq_fsm_state;
......@@ -364,6 +392,7 @@ architecture rtl of fmc_adc_100Ms_core is
signal post_trig_value : std_logic_vector(31 downto 0);
signal post_trig_cnt : unsigned(31 downto 0);
signal post_trig_done : std_logic;
signal samples_cnt : unsigned(31 downto 0);
signal shots_value : std_logic_vector(15 downto 0);
signal shots_cnt : unsigned(15 downto 0);
signal shots_done : std_logic;
......@@ -543,6 +572,11 @@ begin
IO_RESET => sys_rst
);
--============================================================================
-- Sampling clock domain
--============================================================================
-- serdes inputs forming
serdes_in_p <= adc_fr_p_i
& adc_outa_p_i(3) & adc_outb_p_i(3)
......@@ -647,7 +681,7 @@ begin
fmc_adc_core_sta_serdes_synced_i => serdes_synced,
fmc_adc_core_sta_reserved_i => (others => '0'),
fmc_adc_core_trig_cfg_hw_trig_sel_o => hw_trig_sel,
fmc_adc_core_trig_cfg_ext_trig_pol_o => ext_trig_pol,
fmc_adc_core_trig_cfg_hw_trig_pol_o => hw_trig_pol,
fmc_adc_core_trig_cfg_hw_trig_en_o => hw_trig_en,
fmc_adc_core_trig_cfg_sw_trig_en_o => sw_trig_en,
fmc_adc_core_trig_cfg_int_trig_sel_o => int_trig_sel,
......@@ -659,32 +693,43 @@ begin
fmc_adc_core_shots_nb_o => shots_value,
fmc_adc_core_shots_reserved_o => open,
fmc_adc_core_trig_pos_i => trig_addr,
fmc_adc_core_gain_cal_o => gain_calibr,
fmc_adc_core_offset_cal_o => offset_calibr,
fmc_adc_core_reserved_0_i => (others => '0'),
fmc_adc_core_reserved_1_i => (others => '0'),
fmc_adc_core_reserved_2_i => (others => '0'),
fmc_adc_core_sr_deci_o => decim_factor,
fmc_adc_core_sr_reserved_o => open,
fmc_adc_core_pre_samples_o => pre_trig_value,
fmc_adc_core_post_samples_o => post_trig_value,
fmc_adc_core_samp_cnt_i => X"00000000",
fmc_adc_core_ch1_ssr_o => gpio_ssr_ch1_o,
fmc_adc_core_ch1_reserved_o => open,
fmc_adc_core_ch1_val_i => serdes_out_data(15 downto 0),
fmc_adc_core_ch1_reserved_i => (others => '0'),
fmc_adc_core_ch2_ssr_o => gpio_ssr_ch2_o,
fmc_adc_core_ch2_reserved_o => open,
fmc_adc_core_ch2_val_i => serdes_out_data(31 downto 16),
fmc_adc_core_ch2_reserved_i => (others => '0'),
fmc_adc_core_ch3_ssr_o => gpio_ssr_ch3_o,
fmc_adc_core_ch3_reserved_o => open,
fmc_adc_core_ch3_val_i => serdes_out_data(47 downto 32),
fmc_adc_core_ch3_reserved_i => (others => '0'),
fmc_adc_core_ch4_ssr_o => gpio_ssr_ch4_o,
fmc_adc_core_ch4_reserved_o => open,
fmc_adc_core_ch4_val_i => serdes_out_data(63 downto 48),
fmc_adc_core_ch4_reserved_i => (others => '0')
fmc_adc_core_samples_cnt_i => std_logic_vector(samples_cnt),
fmc_adc_core_ch1_ctl_ssr_o => gpio_ssr_ch1_o,
fmc_adc_core_ch1_ctl_reserved_o => open,
fmc_adc_core_ch1_sta_val_i => serdes_out_data(15 downto 0),
fmc_adc_core_ch1_sta_reserved_i => (others => '0'),
fmc_adc_core_ch1_gain_val_o => gain_calibr(15 downto 0),
fmc_adc_core_ch1_gain_reserved_o => open,
fmc_adc_core_ch1_offset_val_o => offset_calibr(16 downto 0),
fmc_adc_core_ch1_offset_reserved_o => open,
fmc_adc_core_ch2_ctl_ssr_o => gpio_ssr_ch2_o,
fmc_adc_core_ch2_ctl_reserved_o => open,
fmc_adc_core_ch2_sta_val_i => serdes_out_data(31 downto 16),
fmc_adc_core_ch2_sta_reserved_i => (others => '0'),
fmc_adc_core_ch2_gain_val_o => gain_calibr(31 downto 16),
fmc_adc_core_ch2_gain_reserved_o => open,
fmc_adc_core_ch2_offset_val_o => offset_calibr(33 downto 17),
fmc_adc_core_ch2_offset_reserved_o => open,
fmc_adc_core_ch3_ctl_ssr_o => gpio_ssr_ch3_o,
fmc_adc_core_ch3_ctl_reserved_o => open,
fmc_adc_core_ch3_sta_val_i => serdes_out_data(47 downto 32),
fmc_adc_core_ch3_sta_reserved_i => (others => '0'),
fmc_adc_core_ch3_gain_val_o => gain_calibr(47 downto 32),
fmc_adc_core_ch3_gain_reserved_o => open,
fmc_adc_core_ch3_offset_val_o => offset_calibr(50 downto 34),
fmc_adc_core_ch3_offset_reserved_o => open,
fmc_adc_core_ch4_ctl_ssr_o => gpio_ssr_ch4_o,
fmc_adc_core_ch4_ctl_reserved_o => open,
fmc_adc_core_ch4_sta_val_i => serdes_out_data(63 downto 48),
fmc_adc_core_ch4_sta_reserved_i => (others => '0'),
fmc_adc_core_ch4_gain_val_o => gain_calibr(63 downto 48),
fmc_adc_core_ch4_gain_reserved_o => open,
fmc_adc_core_ch4_offset_val_o => offset_calibr(67 downto 51),
fmc_adc_core_ch4_offset_reserved_o => open
);
------------------------------------------------------------------------------
......@@ -711,13 +756,37 @@ begin
port map(
rst_n_i => fs_rst_n,
clk_i => fs_clk,
input_polarity_i => ext_trig_pol,
input_polarity_i => hw_trig_pol,
pulse_i => ext_trig_a,
pulse_o => ext_trig
);
-- Internal hardware trigger
int_trig <= '0';
int_trig_data <= serdes_out_data(15 downto 0) when int_trig_sel = "00" else -- CH1 selected
serdes_out_data(31 downto 16) when int_trig_sel = "01" else -- CH2 selected
serdes_out_data(47 downto 32) when int_trig_sel = "10" else -- CH3 selected
serdes_out_data(63 downto 48) when int_trig_sel = "11" else -- CH4 selected
(others => '0');
p_int_trig : process (fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
int_trig_over_thres <= '0';
int_trig_over_thres_d <= '0';
serdes_out_data_d <= (others => '0');
elsif rising_edge(fs_clk) then
if int_trig_data > int_trig_thres then
int_trig_over_thres <= '1';
else
int_trig_over_thres <= '0';
end if;
int_trig_over_thres_d <= int_trig_over_thres;
serdes_out_data_d <= serdes_out_data; -- delay data to compensate for threshold detection delay
end if;
end process p_int_trig;
int_trig <= int_trig_over_thres and not(int_trig_over_thres_d) when hw_trig_pol = '0' else -- positive slope
not(int_trig_over_thres) and int_trig_over_thres_d; -- negative slope
-- Hardware trigger selection
-- internal = adc data threshold
......@@ -806,6 +875,24 @@ begin
end if;
end process p_trig_align;
------------------------------------------------------------------------------
-- Offset and gain calibration
------------------------------------------------------------------------------
l_offset_gain_calibr : for I in 0 to 3 generate
cmp_offset_gain_calibr : offset_gain
port map(
rst_n_i => fs_rst_n,
clk_i => fs_clk,
offset_i => offset_calibr((I+1)*17-1 downto I*17),
gain_i => gain_calibr((I+1)*16-1 downto I*16),
data_i => data_calibr_in((I+1)*16-1 downto I*16),
data_o => data_calibr_out((I+1)*16-1 downto I*16)
);
end generate l_offset_gain_calibr;
-- An additional 1 fs_clk period delay is added when internal hw trigger is selected
data_calibr_in <= serdes_out_data_d when hw_trig_sel = '0' else serdes_out_data;
------------------------------------------------------------------------------
-- Synchronisation FIFO to system clock domain
------------------------------------------------------------------------------
......@@ -823,7 +910,7 @@ begin
valid => sync_fifo_valid
);
sync_fifo_din <= trig_align & serdes_out_data;
sync_fifo_din <= trig_align & data_calibr_out;
-- FOR DEBUG: FR instead of CH1 and SerDes Synced instead of CH2
--sync_fifo_din <= trig_align & serdes_out_data(63 downto 32) &
-- "000000000000000" & serdes_synced &
......@@ -832,6 +919,11 @@ begin
sync_fifo_wr <= decim_en and serdes_synced and not(sync_fifo_full);
sync_fifo_rd <= sync_fifo_dreq and not(sync_fifo_empty);
--============================================================================
-- System clock domain
--============================================================================
------------------------------------------------------------------------------
-- Shots counter
------------------------------------------------------------------------------
......@@ -867,19 +959,36 @@ begin
begin
if sys_rst_n_i = '0' then
pre_trig_cnt <= to_unsigned(1, pre_trig_cnt'length);
pre_trig_done <= '0';
elsif rising_edge(sys_clk_i) then
if (acq_start = '1' or pre_trig_done = '1') then
pre_trig_cnt <= unsigned(pre_trig_value);
pre_trig_done <= '0';
elsif pre_trig_cnt = to_unsigned(0, pre_trig_cnt'length) then
pre_trig_done <= '1';
if unsigned(pre_trig_value) = to_unsigned(0, pre_trig_value'length) then
pre_trig_cnt <= (others => '0');
else
pre_trig_cnt <= unsigned(pre_trig_value) - 1;
end if;
elsif (acq_in_pre_trig = '1' and sync_fifo_valid = '1') then
pre_trig_cnt <= pre_trig_cnt - 1;
end if;
end if;
end process p_pre_trig_cnt;
pre_trig_done <= '1' when (pre_trig_cnt = to_unsigned(0, pre_trig_cnt'length) and
sync_fifo_valid = '1') else '0';
--p_pre_trig_done : process (sys_clk_i, sys_rst_n_i)
--begin
-- if sys_rst_n_i = '0' then
-- pre_trig_done <= '0';
-- elsif rising_edge(sys_clk_i) then
-- if (acq_start = '1' or pre_trig_done = '1') then
-- pre_trig_done <= '0';
-- elsif (pre_trig_cnt = to_unsigned(0, pre_trig_cnt'length)) then
-- pre_trig_done <= '1';
-- end if;
-- end if;
--end process p_pre_trig_done;
------------------------------------------------------------------------------
-- Post-trigger counter
------------------------------------------------------------------------------
......@@ -887,19 +996,51 @@ begin
begin
if sys_rst_n_i = '0' then
post_trig_cnt <= to_unsigned(1, post_trig_cnt'length);
post_trig_done <= '0';
elsif rising_edge(sys_clk_i) then
if (acq_start = '1' or post_trig_done = '1') then
post_trig_cnt <= unsigned(post_trig_value);
post_trig_done <= '0';
elsif post_trig_cnt = to_unsigned(0, post_trig_cnt'length) then
post_trig_done <= '1';
if unsigned(post_trig_value) = to_unsigned(0, post_trig_value'length) then
post_trig_cnt <= (others => '0');
else
post_trig_cnt <= unsigned(post_trig_value) - 1;
end if;
elsif (acq_in_post_trig = '1' and sync_fifo_valid = '1') then
post_trig_cnt <= post_trig_cnt - 1;
end if;
end if;
end process p_post_trig_cnt;
post_trig_done <= '1' when (post_trig_cnt = to_unsigned(0, post_trig_cnt'length) and
sync_fifo_valid = '1') else '0';
--p_post_trig_done : process (sys_clk_i, sys_rst_n_i)
--begin
-- if sys_rst_n_i = '0' then
-- post_trig_done <= '0';
-- elsif rising_edge(sys_clk_i) then
-- if (acq_start = '1' or post_trig_done = '1') then
-- post_trig_done <= '0';
-- elsif (post_trig_cnt = to_unsigned(0, post_trig_cnt'length)) then
-- post_trig_done <= '1';
-- end if;
-- end if;
--end process p_post_trig_done;
------------------------------------------------------------------------------
-- Samples counter
------------------------------------------------------------------------------
p_samples_cnt : process (sys_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
samples_cnt <= (others => '0');
elsif rising_edge(sys_clk_i) then
if (acq_start = '1') then
samples_cnt <= (others => '0');
elsif ((acq_in_pre_trig = '1' or acq_in_post_trig = '1') and sync_fifo_valid = '1') then
samples_cnt <= samples_cnt + 1;
end if;
end if;
end process p_samples_cnt;
------------------------------------------------------------------------------
-- Aqcuisition FSM
------------------------------------------------------------------------------
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Wed Nov 23 14:38:25 2011
-- Created : Fri Nov 25 16:25:50 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -54,8 +54,8 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_sta_reserved_i : in std_logic_vector(26 downto 0);
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger selection' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'External hardware trigger polarity' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_ext_trig_pol_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger polarity' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_hw_trig_pol_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger enable' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_hw_trig_en_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Software trigger enable' in reg: 'Trigger configuration'
......@@ -77,16 +77,6 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_shots_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Trigger address' in reg: 'Trigger address register'
fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Gain calibration' in reg: 'Gain calibration register'
fmc_adc_core_gain_cal_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Offset calibration' in reg: 'Offset calibration register'
fmc_adc_core_offset_cal_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reserved register'
fmc_adc_core_reserved_0_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reserved register'
fmc_adc_core_reserved_1_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reserved register'
fmc_adc_core_reserved_2_i : in std_logic_vector(31 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Sample rate decimation' in reg: 'Sample rate'
fmc_adc_core_sr_deci_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Sample rate'
......@@ -95,40 +85,72 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_pre_samples_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Post-trigger samples' in reg: 'Post-trigger samples'
fmc_adc_core_post_samples_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Sample counter' in reg: 'Sample counter'
fmc_adc_core_samp_cnt_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 1' in reg: 'Solid state relays control for channel 1'
fmc_adc_core_ch1_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Solid state relays control for channel 1'
fmc_adc_core_ch1_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 1 current value' in reg: 'Channel 1 current value'
fmc_adc_core_ch1_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 1 current value'
fmc_adc_core_ch1_reserved_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 2' in reg: 'Solid state relays control for channel 2'
fmc_adc_core_ch2_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Solid state relays control for channel 2'
fmc_adc_core_ch2_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 2 current value' in reg: 'Channel 2 current value'
fmc_adc_core_ch2_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 2 current value'
fmc_adc_core_ch2_reserved_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 3' in reg: 'Solid state relays control for channel 3'
fmc_adc_core_ch3_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Solid state relays control for channel 3'
fmc_adc_core_ch3_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 3 current value' in reg: 'Channel 3 current value'
fmc_adc_core_ch3_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 3 current value'
fmc_adc_core_ch3_reserved_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 4' in reg: 'Solid state relays control for channel 4'
fmc_adc_core_ch4_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Solid state relays control for channel 4'
fmc_adc_core_ch4_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 4 current value' in reg: 'Channel 4 current value'
fmc_adc_core_ch4_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 4 current value'
fmc_adc_core_ch4_reserved_i : in std_logic_vector(15 downto 0)
-- Port for std_logic_vector field: 'Samples counter' in reg: 'Samples counter'
fmc_adc_core_samples_cnt_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 1' in reg: 'Channel 1 control register'
fmc_adc_core_ch1_ctl_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 1 control register'
fmc_adc_core_ch1_ctl_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 1 current ADC value' in reg: 'Channel 1 status register'
fmc_adc_core_ch1_sta_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 1 status register'
fmc_adc_core_ch1_sta_reserved_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Gain calibration for channel 1' in reg: 'Channel 1 gain calibration register'
fmc_adc_core_ch1_gain_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 1 gain calibration register'
fmc_adc_core_ch1_gain_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Offset calibration for channel 1' in reg: 'Channel 1 offset calibration register'
fmc_adc_core_ch1_offset_val_o : out std_logic_vector(16 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 1 offset calibration register'
fmc_adc_core_ch1_offset_reserved_o : out std_logic_vector(14 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 2' in reg: 'Channel 2 control register'
fmc_adc_core_ch2_ctl_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 2 control register'
fmc_adc_core_ch2_ctl_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 2 current ACD value' in reg: 'Channel 2 status register'
fmc_adc_core_ch2_sta_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 2 status register'
fmc_adc_core_ch2_sta_reserved_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Gain calibration for channel 2' in reg: 'Channel 2 gain calibration register'
fmc_adc_core_ch2_gain_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 2 gain calibration register'
fmc_adc_core_ch2_gain_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Offset calibration for channel 2' in reg: 'Channel 2 offset calibration register'
fmc_adc_core_ch2_offset_val_o : out std_logic_vector(16 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 2 offset calibration register'
fmc_adc_core_ch2_offset_reserved_o : out std_logic_vector(14 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 3' in reg: 'Channel 3 control register'
fmc_adc_core_ch3_ctl_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 3 control register'
fmc_adc_core_ch3_ctl_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 3 current ADC value' in reg: 'Channel 3 status register'
fmc_adc_core_ch3_sta_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 3 status register'
fmc_adc_core_ch3_sta_reserved_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Gain calibration for channel 3' in reg: 'Channel 3 gain calibration register'
fmc_adc_core_ch3_gain_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 3 gain calibration register'
fmc_adc_core_ch3_gain_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Offset calibration for channel 3' in reg: 'Channel 3 offset calibration register'
fmc_adc_core_ch3_offset_val_o : out std_logic_vector(16 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 3 offset calibration register'
fmc_adc_core_ch3_offset_reserved_o : out std_logic_vector(14 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 4' in reg: 'Channel 4 control register'
fmc_adc_core_ch4_ctl_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 4 control register'
fmc_adc_core_ch4_ctl_reserved_o : out std_logic_vector(24 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 4 current ADC value' in reg: 'Channel 4 status register'
fmc_adc_core_ch4_sta_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 4 status register'
fmc_adc_core_ch4_sta_reserved_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Gain calibration for channel 4' in reg: 'Channel 4 gain calibration register'
fmc_adc_core_ch4_gain_val_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 4 gain calibration register'
fmc_adc_core_ch4_gain_reserved_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Offset calibration for channel 4' in reg: 'Channel 4 offset calibration register'
fmc_adc_core_ch4_offset_val_o : out std_logic_vector(16 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Channel 4 offset calibration register'
fmc_adc_core_ch4_offset_reserved_o : out std_logic_vector(14 downto 0)
);
end fmc_adc_100Ms_csr;
......@@ -148,9 +170,9 @@ signal fmc_adc_core_ctl_reserved_int : std_logic_vector(23 downto 0);
signal fmc_adc_core_trig_cfg_hw_trig_sel_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync1 : std_logic ;
signal fmc_adc_core_trig_cfg_ext_trig_pol_int : std_logic ;
signal fmc_adc_core_trig_cfg_ext_trig_pol_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_ext_trig_pol_sync1 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_pol_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_pol_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_pol_sync1 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_en_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_en_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_en_sync1 : std_logic ;
......@@ -178,8 +200,6 @@ signal fmc_adc_core_sw_trig_wr_sync1 : std_logic ;
signal fmc_adc_core_sw_trig_wr_sync2 : std_logic ;
signal fmc_adc_core_shots_nb_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_shots_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_gain_cal_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_offset_cal_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_sr_deci_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_sr_deci_swb : std_logic ;
signal fmc_adc_core_sr_deci_swb_delay : std_logic ;
......@@ -189,42 +209,58 @@ signal fmc_adc_core_sr_deci_swb_s2 : std_logic ;
signal fmc_adc_core_sr_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_pre_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_post_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_ch1_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch1_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch1_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_val_lwb : std_logic ;
signal fmc_adc_core_ch1_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch1_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch1_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch1_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch1_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch2_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch2_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch2_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_val_lwb : std_logic ;
signal fmc_adc_core_ch2_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch2_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch2_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch2_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch2_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch3_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch3_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch3_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_val_lwb : std_logic ;
signal fmc_adc_core_ch3_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch3_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch3_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch3_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch3_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch4_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch4_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch4_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_val_lwb : std_logic ;
signal fmc_adc_core_ch4_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch4_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch4_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch4_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch4_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch1_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch1_ctl_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch1_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_sta_val_lwb : std_logic ;
signal fmc_adc_core_ch1_sta_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch1_sta_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch1_sta_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch1_sta_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch1_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch1_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_gain_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_offset_val_int : std_logic_vector(16 downto 0);
signal fmc_adc_core_ch1_offset_reserved_int : std_logic_vector(14 downto 0);
signal fmc_adc_core_ch2_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch2_ctl_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch2_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_sta_val_lwb : std_logic ;
signal fmc_adc_core_ch2_sta_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch2_sta_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch2_sta_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch2_sta_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch2_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch2_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_gain_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_offset_val_int : std_logic_vector(16 downto 0);
signal fmc_adc_core_ch2_offset_reserved_int : std_logic_vector(14 downto 0);
signal fmc_adc_core_ch3_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch3_ctl_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch3_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_sta_val_lwb : std_logic ;
signal fmc_adc_core_ch3_sta_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch3_sta_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch3_sta_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch3_sta_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch3_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch3_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_gain_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_offset_val_int : std_logic_vector(16 downto 0);
signal fmc_adc_core_ch3_offset_reserved_int : std_logic_vector(14 downto 0);
signal fmc_adc_core_ch4_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch4_ctl_reserved_int : std_logic_vector(24 downto 0);
signal fmc_adc_core_ch4_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_sta_val_lwb : std_logic ;
signal fmc_adc_core_ch4_sta_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch4_sta_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch4_sta_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch4_sta_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch4_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch4_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_gain_reserved_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_offset_val_int : std_logic_vector(16 downto 0);
signal fmc_adc_core_ch4_offset_reserved_int : std_logic_vector(14 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -264,7 +300,7 @@ begin
fmc_adc_core_ctl_acq_led_int <= '0';
fmc_adc_core_ctl_reserved_int <= "000000000000000000000000";
fmc_adc_core_trig_cfg_hw_trig_sel_int <= '0';
fmc_adc_core_trig_cfg_ext_trig_pol_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_pol_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_en_int <= '0';
fmc_adc_core_trig_cfg_sw_trig_en_int <= '0';
fmc_adc_core_trig_cfg_int_trig_sel_int <= "00";
......@@ -279,34 +315,48 @@ begin
fmc_adc_core_sw_trig_wr_int_delay <= '0';
fmc_adc_core_shots_nb_int <= "0000000000000000";
fmc_adc_core_shots_reserved_int <= "0000000000000000";
fmc_adc_core_gain_cal_int <= "00000000000000000000000000000000";
fmc_adc_core_offset_cal_int <= "00000000000000000000000000000000";
fmc_adc_core_sr_deci_int <= "0000000000000000";
fmc_adc_core_sr_deci_swb <= '0';
fmc_adc_core_sr_deci_swb_delay <= '0';
fmc_adc_core_sr_reserved_int <= "0000000000000000";
fmc_adc_core_pre_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_post_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_ch1_ssr_int <= "0000000";
fmc_adc_core_ch1_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch1_val_lwb <= '0';
fmc_adc_core_ch1_val_lwb_delay <= '0';
fmc_adc_core_ch1_val_lwb_in_progress <= '0';
fmc_adc_core_ch2_ssr_int <= "0000000";
fmc_adc_core_ch2_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch2_val_lwb <= '0';
fmc_adc_core_ch2_val_lwb_delay <= '0';
fmc_adc_core_ch2_val_lwb_in_progress <= '0';
fmc_adc_core_ch3_ssr_int <= "0000000";
fmc_adc_core_ch3_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch3_val_lwb <= '0';
fmc_adc_core_ch3_val_lwb_delay <= '0';
fmc_adc_core_ch3_val_lwb_in_progress <= '0';
fmc_adc_core_ch4_ssr_int <= "0000000";
fmc_adc_core_ch4_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch4_val_lwb <= '0';
fmc_adc_core_ch4_val_lwb_delay <= '0';
fmc_adc_core_ch4_val_lwb_in_progress <= '0';
fmc_adc_core_ch1_ctl_ssr_int <= "0000000";
fmc_adc_core_ch1_ctl_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch1_sta_val_lwb <= '0';
fmc_adc_core_ch1_sta_val_lwb_delay <= '0';
fmc_adc_core_ch1_sta_val_lwb_in_progress <= '0';
fmc_adc_core_ch1_gain_val_int <= "0000000000000000";
fmc_adc_core_ch1_gain_reserved_int <= "0000000000000000";
fmc_adc_core_ch1_offset_val_int <= "00000000000000000";
fmc_adc_core_ch1_offset_reserved_int <= "000000000000000";
fmc_adc_core_ch2_ctl_ssr_int <= "0000000";
fmc_adc_core_ch2_ctl_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch2_sta_val_lwb <= '0';
fmc_adc_core_ch2_sta_val_lwb_delay <= '0';
fmc_adc_core_ch2_sta_val_lwb_in_progress <= '0';
fmc_adc_core_ch2_gain_val_int <= "0000000000000000";
fmc_adc_core_ch2_gain_reserved_int <= "0000000000000000";
fmc_adc_core_ch2_offset_val_int <= "00000000000000000";
fmc_adc_core_ch2_offset_reserved_int <= "000000000000000";
fmc_adc_core_ch3_ctl_ssr_int <= "0000000";
fmc_adc_core_ch3_ctl_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch3_sta_val_lwb <= '0';
fmc_adc_core_ch3_sta_val_lwb_delay <= '0';
fmc_adc_core_ch3_sta_val_lwb_in_progress <= '0';
fmc_adc_core_ch3_gain_val_int <= "0000000000000000";
fmc_adc_core_ch3_gain_reserved_int <= "0000000000000000";
fmc_adc_core_ch3_offset_val_int <= "00000000000000000";
fmc_adc_core_ch3_offset_reserved_int <= "000000000000000";
fmc_adc_core_ch4_ctl_ssr_int <= "0000000";
fmc_adc_core_ch4_ctl_reserved_int <= "0000000000000000000000000";
fmc_adc_core_ch4_sta_val_lwb <= '0';
fmc_adc_core_ch4_sta_val_lwb_delay <= '0';
fmc_adc_core_ch4_sta_val_lwb_in_progress <= '0';
fmc_adc_core_ch4_gain_val_int <= "0000000000000000";
fmc_adc_core_ch4_gain_reserved_int <= "0000000000000000";
fmc_adc_core_ch4_offset_val_int <= "00000000000000000";
fmc_adc_core_ch4_offset_reserved_int <= "000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -327,29 +377,29 @@ begin
fmc_adc_core_sw_trig_wr_int_delay <= '0';
fmc_adc_core_sr_deci_swb <= fmc_adc_core_sr_deci_swb_delay;
fmc_adc_core_sr_deci_swb_delay <= '0';
fmc_adc_core_ch1_val_lwb <= fmc_adc_core_ch1_val_lwb_delay;
fmc_adc_core_ch1_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch1_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch1_val_int;
fmc_adc_core_ch1_val_lwb_in_progress <= '0';
fmc_adc_core_ch1_sta_val_lwb <= fmc_adc_core_ch1_sta_val_lwb_delay;
fmc_adc_core_ch1_sta_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch1_sta_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch1_sta_val_int;
fmc_adc_core_ch1_sta_val_lwb_in_progress <= '0';
end if;
fmc_adc_core_ch2_val_lwb <= fmc_adc_core_ch2_val_lwb_delay;
fmc_adc_core_ch2_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch2_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch2_val_int;
fmc_adc_core_ch2_val_lwb_in_progress <= '0';
fmc_adc_core_ch2_sta_val_lwb <= fmc_adc_core_ch2_sta_val_lwb_delay;
fmc_adc_core_ch2_sta_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch2_sta_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch2_sta_val_int;
fmc_adc_core_ch2_sta_val_lwb_in_progress <= '0';
end if;
fmc_adc_core_ch3_val_lwb <= fmc_adc_core_ch3_val_lwb_delay;
fmc_adc_core_ch3_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch3_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch3_val_int;
fmc_adc_core_ch3_val_lwb_in_progress <= '0';
fmc_adc_core_ch3_sta_val_lwb <= fmc_adc_core_ch3_sta_val_lwb_delay;
fmc_adc_core_ch3_sta_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch3_sta_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch3_sta_val_int;
fmc_adc_core_ch3_sta_val_lwb_in_progress <= '0';
end if;
fmc_adc_core_ch4_val_lwb <= fmc_adc_core_ch4_val_lwb_delay;
fmc_adc_core_ch4_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch4_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch4_val_int;
fmc_adc_core_ch4_val_lwb_in_progress <= '0';
fmc_adc_core_ch4_sta_val_lwb <= fmc_adc_core_ch4_sta_val_lwb_delay;
fmc_adc_core_ch4_sta_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch4_sta_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch4_sta_val_int;
fmc_adc_core_ch4_sta_val_lwb_in_progress <= '0';
end if;
end if;
else
......@@ -391,7 +441,7 @@ begin
when "00010" =>
if (wb_we_i = '1') then
fmc_adc_core_trig_cfg_hw_trig_sel_int <= wrdata_reg(0);
fmc_adc_core_trig_cfg_ext_trig_pol_int <= wrdata_reg(1);
fmc_adc_core_trig_cfg_hw_trig_pol_int <= wrdata_reg(1);
fmc_adc_core_trig_cfg_hw_trig_en_int <= wrdata_reg(2);
fmc_adc_core_trig_cfg_sw_trig_en_int <= wrdata_reg(3);
fmc_adc_core_trig_cfg_int_trig_sel_int <= wrdata_reg(5 downto 4);
......@@ -403,7 +453,7 @@ begin
fmc_adc_core_trig_cfg_int_trig_thres_swb_delay <= '1';
else
rddata_reg(0) <= fmc_adc_core_trig_cfg_hw_trig_sel_int;
rddata_reg(1) <= fmc_adc_core_trig_cfg_ext_trig_pol_int;
rddata_reg(1) <= fmc_adc_core_trig_cfg_hw_trig_pol_int;
rddata_reg(2) <= fmc_adc_core_trig_cfg_hw_trig_en_int;
rddata_reg(3) <= fmc_adc_core_trig_cfg_sw_trig_en_int;
rddata_reg(5 downto 4) <= fmc_adc_core_trig_cfg_int_trig_sel_int;
......@@ -479,156 +529,199 @@ begin
ack_in_progress <= '1';
when "00111" =>
if (wb_we_i = '1') then
fmc_adc_core_gain_cal_int <= wrdata_reg(31 downto 0);
fmc_adc_core_sr_deci_int <= wrdata_reg(15 downto 0);
fmc_adc_core_sr_deci_swb <= '1';
fmc_adc_core_sr_deci_swb_delay <= '1';
fmc_adc_core_sr_reserved_int <= wrdata_reg(31 downto 16);
else
rddata_reg(31 downto 0) <= fmc_adc_core_gain_cal_int;
rddata_reg(15 downto 0) <= fmc_adc_core_sr_deci_int;
rddata_reg(31 downto 16) <= fmc_adc_core_sr_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
fmc_adc_core_offset_cal_int <= wrdata_reg(31 downto 0);
fmc_adc_core_pre_samples_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= fmc_adc_core_offset_cal_int;
rddata_reg(31 downto 0) <= fmc_adc_core_pre_samples_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
if (wb_we_i = '1') then
fmc_adc_core_post_samples_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= fmc_adc_core_reserved_0_i;
rddata_reg(31 downto 0) <= fmc_adc_core_post_samples_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= fmc_adc_core_reserved_1_i;
rddata_reg(31 downto 0) <= fmc_adc_core_samples_cnt_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch1_ctl_reserved_int <= wrdata_reg(31 downto 7);
else
rddata_reg(31 downto 0) <= fmc_adc_core_reserved_2_i;
rddata_reg(6 downto 0) <= fmc_adc_core_ch1_ctl_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch1_ctl_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
if (wb_we_i = '1') then
fmc_adc_core_sr_deci_int <= wrdata_reg(15 downto 0);
fmc_adc_core_sr_deci_swb <= '1';
fmc_adc_core_sr_deci_swb_delay <= '1';
fmc_adc_core_sr_reserved_int <= wrdata_reg(31 downto 16);
else
rddata_reg(15 downto 0) <= fmc_adc_core_sr_deci_int;
rddata_reg(31 downto 16) <= fmc_adc_core_sr_reserved_int;
fmc_adc_core_ch1_sta_val_lwb <= '1';
fmc_adc_core_ch1_sta_val_lwb_delay <= '1';
fmc_adc_core_ch1_sta_val_lwb_in_progress <= '1';
rddata_reg(31 downto 16) <= fmc_adc_core_ch1_sta_reserved_i;
end if;
ack_sreg(3) <= '1';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "01101" =>
if (wb_we_i = '1') then
fmc_adc_core_pre_samples_int <= wrdata_reg(31 downto 0);
fmc_adc_core_ch1_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch1_gain_reserved_int <= wrdata_reg(31 downto 16);
else
rddata_reg(31 downto 0) <= fmc_adc_core_pre_samples_int;
rddata_reg(15 downto 0) <= fmc_adc_core_ch1_gain_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch1_gain_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
if (wb_we_i = '1') then
fmc_adc_core_post_samples_int <= wrdata_reg(31 downto 0);
fmc_adc_core_ch1_offset_val_int <= wrdata_reg(16 downto 0);
fmc_adc_core_ch1_offset_reserved_int <= wrdata_reg(31 downto 17);
else
rddata_reg(31 downto 0) <= fmc_adc_core_post_samples_int;
rddata_reg(16 downto 0) <= fmc_adc_core_ch1_offset_val_int;
rddata_reg(31 downto 17) <= fmc_adc_core_ch1_offset_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch2_ctl_reserved_int <= wrdata_reg(31 downto 7);
else
rddata_reg(31 downto 0) <= fmc_adc_core_samp_cnt_i;
rddata_reg(6 downto 0) <= fmc_adc_core_ch2_ctl_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch2_ctl_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
fmc_adc_core_ch1_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch1_reserved_int <= wrdata_reg(31 downto 7);
else
rddata_reg(6 downto 0) <= fmc_adc_core_ch1_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch1_reserved_int;
fmc_adc_core_ch2_sta_val_lwb <= '1';
fmc_adc_core_ch2_sta_val_lwb_delay <= '1';
fmc_adc_core_ch2_sta_val_lwb_in_progress <= '1';
rddata_reg(31 downto 16) <= fmc_adc_core_ch2_sta_reserved_i;
end if;
ack_sreg(0) <= '1';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch2_gain_reserved_int <= wrdata_reg(31 downto 16);
else
fmc_adc_core_ch1_val_lwb <= '1';
fmc_adc_core_ch1_val_lwb_delay <= '1';
fmc_adc_core_ch1_val_lwb_in_progress <= '1';
rddata_reg(31 downto 16) <= fmc_adc_core_ch1_reserved_i;
rddata_reg(15 downto 0) <= fmc_adc_core_ch2_gain_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch2_gain_reserved_int;
end if;
ack_sreg(5) <= '1';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
if (wb_we_i = '1') then
fmc_adc_core_ch2_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch2_reserved_int <= wrdata_reg(31 downto 7);
fmc_adc_core_ch2_offset_val_int <= wrdata_reg(16 downto 0);
fmc_adc_core_ch2_offset_reserved_int <= wrdata_reg(31 downto 17);
else
rddata_reg(6 downto 0) <= fmc_adc_core_ch2_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch2_reserved_int;
rddata_reg(16 downto 0) <= fmc_adc_core_ch2_offset_val_int;
rddata_reg(31 downto 17) <= fmc_adc_core_ch2_offset_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch3_ctl_reserved_int <= wrdata_reg(31 downto 7);
else
fmc_adc_core_ch2_val_lwb <= '1';
fmc_adc_core_ch2_val_lwb_delay <= '1';
fmc_adc_core_ch2_val_lwb_in_progress <= '1';
rddata_reg(31 downto 16) <= fmc_adc_core_ch2_reserved_i;
rddata_reg(6 downto 0) <= fmc_adc_core_ch3_ctl_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch3_ctl_reserved_int;
end if;
ack_sreg(5) <= '1';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch3_reserved_int <= wrdata_reg(31 downto 7);
else
rddata_reg(6 downto 0) <= fmc_adc_core_ch3_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch3_reserved_int;
fmc_adc_core_ch3_sta_val_lwb <= '1';
fmc_adc_core_ch3_sta_val_lwb_delay <= '1';
fmc_adc_core_ch3_sta_val_lwb_in_progress <= '1';
rddata_reg(31 downto 16) <= fmc_adc_core_ch3_sta_reserved_i;
end if;
ack_sreg(0) <= '1';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10101" =>
if (wb_we_i = '1') then
fmc_adc_core_ch3_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch3_gain_reserved_int <= wrdata_reg(31 downto 16);
else
fmc_adc_core_ch3_val_lwb <= '1';
fmc_adc_core_ch3_val_lwb_delay <= '1';
fmc_adc_core_ch3_val_lwb_in_progress <= '1';
rddata_reg(31 downto 16) <= fmc_adc_core_ch3_reserved_i;
rddata_reg(15 downto 0) <= fmc_adc_core_ch3_gain_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch3_gain_reserved_int;
end if;
ack_sreg(5) <= '1';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10110" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch4_reserved_int <= wrdata_reg(31 downto 7);
fmc_adc_core_ch3_offset_val_int <= wrdata_reg(16 downto 0);
fmc_adc_core_ch3_offset_reserved_int <= wrdata_reg(31 downto 17);
else
rddata_reg(6 downto 0) <= fmc_adc_core_ch4_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch4_reserved_int;
rddata_reg(16 downto 0) <= fmc_adc_core_ch3_offset_val_int;
rddata_reg(31 downto 17) <= fmc_adc_core_ch3_offset_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10111" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_ctl_ssr_int <= wrdata_reg(6 downto 0);
fmc_adc_core_ch4_ctl_reserved_int <= wrdata_reg(31 downto 7);
else
fmc_adc_core_ch4_val_lwb <= '1';
fmc_adc_core_ch4_val_lwb_delay <= '1';
fmc_adc_core_ch4_val_lwb_in_progress <= '1';
rddata_reg(31 downto 16) <= fmc_adc_core_ch4_reserved_i;
rddata_reg(6 downto 0) <= fmc_adc_core_ch4_ctl_ssr_int;
rddata_reg(31 downto 7) <= fmc_adc_core_ch4_ctl_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11000" =>
if (wb_we_i = '1') then
else
fmc_adc_core_ch4_sta_val_lwb <= '1';
fmc_adc_core_ch4_sta_val_lwb_delay <= '1';
fmc_adc_core_ch4_sta_val_lwb_in_progress <= '1';
rddata_reg(31 downto 16) <= fmc_adc_core_ch4_sta_reserved_i;
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "11001" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_gain_val_int <= wrdata_reg(15 downto 0);
fmc_adc_core_ch4_gain_reserved_int <= wrdata_reg(31 downto 16);
else
rddata_reg(15 downto 0) <= fmc_adc_core_ch4_gain_val_int;
rddata_reg(31 downto 16) <= fmc_adc_core_ch4_gain_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11010" =>
if (wb_we_i = '1') then
fmc_adc_core_ch4_offset_val_int <= wrdata_reg(16 downto 0);
fmc_adc_core_ch4_offset_reserved_int <= wrdata_reg(31 downto 17);
else
rddata_reg(16 downto 0) <= fmc_adc_core_ch4_offset_val_int;
rddata_reg(31 downto 17) <= fmc_adc_core_ch4_offset_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -694,18 +787,18 @@ begin
end process;
-- External hardware trigger polarity
-- synchronizer chain for field : External hardware trigger polarity (type RW/RO, bus_clock_int <-> fs_clk_i)
-- Hardware trigger polarity
-- synchronizer chain for field : Hardware trigger polarity (type RW/RO, bus_clock_int <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_trig_cfg_ext_trig_pol_o <= '0';
fmc_adc_core_trig_cfg_ext_trig_pol_sync0 <= '0';
fmc_adc_core_trig_cfg_ext_trig_pol_sync1 <= '0';
fmc_adc_core_trig_cfg_hw_trig_pol_o <= '0';
fmc_adc_core_trig_cfg_hw_trig_pol_sync0 <= '0';
fmc_adc_core_trig_cfg_hw_trig_pol_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_core_trig_cfg_ext_trig_pol_sync0 <= fmc_adc_core_trig_cfg_ext_trig_pol_int;
fmc_adc_core_trig_cfg_ext_trig_pol_sync1 <= fmc_adc_core_trig_cfg_ext_trig_pol_sync0;
fmc_adc_core_trig_cfg_ext_trig_pol_o <= fmc_adc_core_trig_cfg_ext_trig_pol_sync1;
fmc_adc_core_trig_cfg_hw_trig_pol_sync0 <= fmc_adc_core_trig_cfg_hw_trig_pol_int;
fmc_adc_core_trig_cfg_hw_trig_pol_sync1 <= fmc_adc_core_trig_cfg_hw_trig_pol_sync0;
fmc_adc_core_trig_cfg_hw_trig_pol_o <= fmc_adc_core_trig_cfg_hw_trig_pol_sync1;
end if;
end process;
......@@ -809,13 +902,6 @@ begin
-- Reserved
fmc_adc_core_shots_reserved_o <= fmc_adc_core_shots_reserved_int;
-- Trigger address
-- Gain calibration
fmc_adc_core_gain_cal_o <= fmc_adc_core_gain_cal_int;
-- Offset calibration
fmc_adc_core_offset_cal_o <= fmc_adc_core_offset_cal_int;
-- Reserved
-- Reserved
-- Reserved
-- Sample rate decimation
-- asynchronous std_logic_vector register : Sample rate decimation (type RW/RO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
......@@ -842,107 +928,139 @@ begin
fmc_adc_core_pre_samples_o <= fmc_adc_core_pre_samples_int;
-- Post-trigger samples
fmc_adc_core_post_samples_o <= fmc_adc_core_post_samples_int;
-- Sample counter
-- Samples counter
-- Solid state relays control for channel 1
fmc_adc_core_ch1_ssr_o <= fmc_adc_core_ch1_ssr_int;
fmc_adc_core_ch1_ctl_ssr_o <= fmc_adc_core_ch1_ctl_ssr_int;
-- Reserved
fmc_adc_core_ch1_reserved_o <= fmc_adc_core_ch1_reserved_int;
-- Channel 1 current value
-- asynchronous std_logic_vector register : Channel 1 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
fmc_adc_core_ch1_ctl_reserved_o <= fmc_adc_core_ch1_ctl_reserved_int;
-- Channel 1 current ADC value
-- asynchronous std_logic_vector register : Channel 1 current ADC value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_ch1_val_lwb_s0 <= '0';
fmc_adc_core_ch1_val_lwb_s1 <= '0';
fmc_adc_core_ch1_val_lwb_s2 <= '0';
fmc_adc_core_ch1_val_int <= "0000000000000000";
fmc_adc_core_ch1_sta_val_lwb_s0 <= '0';
fmc_adc_core_ch1_sta_val_lwb_s1 <= '0';
fmc_adc_core_ch1_sta_val_lwb_s2 <= '0';
fmc_adc_core_ch1_sta_val_int <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_ch1_val_lwb_s0 <= fmc_adc_core_ch1_val_lwb;
fmc_adc_core_ch1_val_lwb_s1 <= fmc_adc_core_ch1_val_lwb_s0;
fmc_adc_core_ch1_val_lwb_s2 <= fmc_adc_core_ch1_val_lwb_s1;
if ((fmc_adc_core_ch1_val_lwb_s1 = '1') and (fmc_adc_core_ch1_val_lwb_s2 = '0')) then
fmc_adc_core_ch1_val_int <= fmc_adc_core_ch1_val_i;
fmc_adc_core_ch1_sta_val_lwb_s0 <= fmc_adc_core_ch1_sta_val_lwb;
fmc_adc_core_ch1_sta_val_lwb_s1 <= fmc_adc_core_ch1_sta_val_lwb_s0;
fmc_adc_core_ch1_sta_val_lwb_s2 <= fmc_adc_core_ch1_sta_val_lwb_s1;
if ((fmc_adc_core_ch1_sta_val_lwb_s1 = '1') and (fmc_adc_core_ch1_sta_val_lwb_s2 = '0')) then
fmc_adc_core_ch1_sta_val_int <= fmc_adc_core_ch1_sta_val_i;
end if;
end if;
end process;
-- Reserved
-- Gain calibration for channel 1
fmc_adc_core_ch1_gain_val_o <= fmc_adc_core_ch1_gain_val_int;
-- Reserved
fmc_adc_core_ch1_gain_reserved_o <= fmc_adc_core_ch1_gain_reserved_int;
-- Offset calibration for channel 1
fmc_adc_core_ch1_offset_val_o <= fmc_adc_core_ch1_offset_val_int;
-- Reserved
fmc_adc_core_ch1_offset_reserved_o <= fmc_adc_core_ch1_offset_reserved_int;
-- Solid state relays control for channel 2
fmc_adc_core_ch2_ssr_o <= fmc_adc_core_ch2_ssr_int;
fmc_adc_core_ch2_ctl_ssr_o <= fmc_adc_core_ch2_ctl_ssr_int;
-- Reserved
fmc_adc_core_ch2_reserved_o <= fmc_adc_core_ch2_reserved_int;
-- Channel 2 current value
-- asynchronous std_logic_vector register : Channel 2 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
fmc_adc_core_ch2_ctl_reserved_o <= fmc_adc_core_ch2_ctl_reserved_int;
-- Channel 2 current ACD value
-- asynchronous std_logic_vector register : Channel 2 current ACD value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_ch2_val_lwb_s0 <= '0';
fmc_adc_core_ch2_val_lwb_s1 <= '0';
fmc_adc_core_ch2_val_lwb_s2 <= '0';
fmc_adc_core_ch2_val_int <= "0000000000000000";
fmc_adc_core_ch2_sta_val_lwb_s0 <= '0';
fmc_adc_core_ch2_sta_val_lwb_s1 <= '0';
fmc_adc_core_ch2_sta_val_lwb_s2 <= '0';
fmc_adc_core_ch2_sta_val_int <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_ch2_val_lwb_s0 <= fmc_adc_core_ch2_val_lwb;
fmc_adc_core_ch2_val_lwb_s1 <= fmc_adc_core_ch2_val_lwb_s0;
fmc_adc_core_ch2_val_lwb_s2 <= fmc_adc_core_ch2_val_lwb_s1;
if ((fmc_adc_core_ch2_val_lwb_s1 = '1') and (fmc_adc_core_ch2_val_lwb_s2 = '0')) then
fmc_adc_core_ch2_val_int <= fmc_adc_core_ch2_val_i;
fmc_adc_core_ch2_sta_val_lwb_s0 <= fmc_adc_core_ch2_sta_val_lwb;
fmc_adc_core_ch2_sta_val_lwb_s1 <= fmc_adc_core_ch2_sta_val_lwb_s0;
fmc_adc_core_ch2_sta_val_lwb_s2 <= fmc_adc_core_ch2_sta_val_lwb_s1;
if ((fmc_adc_core_ch2_sta_val_lwb_s1 = '1') and (fmc_adc_core_ch2_sta_val_lwb_s2 = '0')) then
fmc_adc_core_ch2_sta_val_int <= fmc_adc_core_ch2_sta_val_i;
end if;
end if;
end process;
-- Reserved
-- Gain calibration for channel 2
fmc_adc_core_ch2_gain_val_o <= fmc_adc_core_ch2_gain_val_int;
-- Reserved
fmc_adc_core_ch2_gain_reserved_o <= fmc_adc_core_ch2_gain_reserved_int;
-- Offset calibration for channel 2
fmc_adc_core_ch2_offset_val_o <= fmc_adc_core_ch2_offset_val_int;
-- Reserved
fmc_adc_core_ch2_offset_reserved_o <= fmc_adc_core_ch2_offset_reserved_int;
-- Solid state relays control for channel 3
fmc_adc_core_ch3_ssr_o <= fmc_adc_core_ch3_ssr_int;
fmc_adc_core_ch3_ctl_ssr_o <= fmc_adc_core_ch3_ctl_ssr_int;
-- Reserved
fmc_adc_core_ch3_reserved_o <= fmc_adc_core_ch3_reserved_int;
-- Channel 3 current value
-- asynchronous std_logic_vector register : Channel 3 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
fmc_adc_core_ch3_ctl_reserved_o <= fmc_adc_core_ch3_ctl_reserved_int;
-- Channel 3 current ADC value
-- asynchronous std_logic_vector register : Channel 3 current ADC value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_ch3_val_lwb_s0 <= '0';
fmc_adc_core_ch3_val_lwb_s1 <= '0';
fmc_adc_core_ch3_val_lwb_s2 <= '0';
fmc_adc_core_ch3_val_int <= "0000000000000000";
fmc_adc_core_ch3_sta_val_lwb_s0 <= '0';
fmc_adc_core_ch3_sta_val_lwb_s1 <= '0';
fmc_adc_core_ch3_sta_val_lwb_s2 <= '0';
fmc_adc_core_ch3_sta_val_int <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_ch3_val_lwb_s0 <= fmc_adc_core_ch3_val_lwb;
fmc_adc_core_ch3_val_lwb_s1 <= fmc_adc_core_ch3_val_lwb_s0;
fmc_adc_core_ch3_val_lwb_s2 <= fmc_adc_core_ch3_val_lwb_s1;
if ((fmc_adc_core_ch3_val_lwb_s1 = '1') and (fmc_adc_core_ch3_val_lwb_s2 = '0')) then
fmc_adc_core_ch3_val_int <= fmc_adc_core_ch3_val_i;
fmc_adc_core_ch3_sta_val_lwb_s0 <= fmc_adc_core_ch3_sta_val_lwb;
fmc_adc_core_ch3_sta_val_lwb_s1 <= fmc_adc_core_ch3_sta_val_lwb_s0;
fmc_adc_core_ch3_sta_val_lwb_s2 <= fmc_adc_core_ch3_sta_val_lwb_s1;
if ((fmc_adc_core_ch3_sta_val_lwb_s1 = '1') and (fmc_adc_core_ch3_sta_val_lwb_s2 = '0')) then
fmc_adc_core_ch3_sta_val_int <= fmc_adc_core_ch3_sta_val_i;
end if;
end if;
end process;
-- Reserved
-- Gain calibration for channel 3
fmc_adc_core_ch3_gain_val_o <= fmc_adc_core_ch3_gain_val_int;
-- Reserved
fmc_adc_core_ch3_gain_reserved_o <= fmc_adc_core_ch3_gain_reserved_int;
-- Offset calibration for channel 3
fmc_adc_core_ch3_offset_val_o <= fmc_adc_core_ch3_offset_val_int;
-- Reserved
fmc_adc_core_ch3_offset_reserved_o <= fmc_adc_core_ch3_offset_reserved_int;
-- Solid state relays control for channel 4
fmc_adc_core_ch4_ssr_o <= fmc_adc_core_ch4_ssr_int;
fmc_adc_core_ch4_ctl_ssr_o <= fmc_adc_core_ch4_ctl_ssr_int;
-- Reserved
fmc_adc_core_ch4_reserved_o <= fmc_adc_core_ch4_reserved_int;
-- Channel 4 current value
-- asynchronous std_logic_vector register : Channel 4 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
fmc_adc_core_ch4_ctl_reserved_o <= fmc_adc_core_ch4_ctl_reserved_int;
-- Channel 4 current ADC value
-- asynchronous std_logic_vector register : Channel 4 current ADC value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_ch4_val_lwb_s0 <= '0';
fmc_adc_core_ch4_val_lwb_s1 <= '0';
fmc_adc_core_ch4_val_lwb_s2 <= '0';
fmc_adc_core_ch4_val_int <= "0000000000000000";
fmc_adc_core_ch4_sta_val_lwb_s0 <= '0';
fmc_adc_core_ch4_sta_val_lwb_s1 <= '0';
fmc_adc_core_ch4_sta_val_lwb_s2 <= '0';
fmc_adc_core_ch4_sta_val_int <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_ch4_val_lwb_s0 <= fmc_adc_core_ch4_val_lwb;
fmc_adc_core_ch4_val_lwb_s1 <= fmc_adc_core_ch4_val_lwb_s0;
fmc_adc_core_ch4_val_lwb_s2 <= fmc_adc_core_ch4_val_lwb_s1;
if ((fmc_adc_core_ch4_val_lwb_s1 = '1') and (fmc_adc_core_ch4_val_lwb_s2 = '0')) then
fmc_adc_core_ch4_val_int <= fmc_adc_core_ch4_val_i;
fmc_adc_core_ch4_sta_val_lwb_s0 <= fmc_adc_core_ch4_sta_val_lwb;
fmc_adc_core_ch4_sta_val_lwb_s1 <= fmc_adc_core_ch4_sta_val_lwb_s0;
fmc_adc_core_ch4_sta_val_lwb_s2 <= fmc_adc_core_ch4_sta_val_lwb_s1;
if ((fmc_adc_core_ch4_sta_val_lwb_s1 = '1') and (fmc_adc_core_ch4_sta_val_lwb_s2 = '0')) then
fmc_adc_core_ch4_sta_val_int <= fmc_adc_core_ch4_sta_val_i;
end if;
end if;
end process;
-- Reserved
-- Gain calibration for channel 4
fmc_adc_core_ch4_gain_val_o <= fmc_adc_core_ch4_gain_val_int;
-- Reserved
fmc_adc_core_ch4_gain_reserved_o <= fmc_adc_core_ch4_gain_reserved_int;
-- Offset calibration for channel 4
fmc_adc_core_ch4_offset_val_o <= fmc_adc_core_ch4_offset_val_int;
-- Reserved
fmc_adc_core_ch4_offset_reserved_o <= fmc_adc_core_ch4_offset_reserved_int;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
......
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Wed Nov 23 14:38:25 2011
* Created : Fri Nov 25 16:25:51 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -88,8 +88,8 @@
/* definitions for field: Hardware trigger selection in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_SEL WBGEN2_GEN_MASK(0, 1)
/* definitions for field: External hardware trigger polarity in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_EXT_TRIG_POL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Hardware trigger polarity in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_POL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Hardware trigger enable in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_EN WBGEN2_GEN_MASK(2, 1)
......@@ -135,16 +135,6 @@
/* definitions for register: Trigger address register */
/* definitions for register: Gain calibration register */
/* definitions for register: Offset calibration register */
/* definitions for register: Reserved register */
/* definitions for register: Reserved register */
/* definitions for register: Reserved register */
/* definitions for register: Sample rate */
/* definitions for field: Sample rate decimation in reg: Sample rate */
......@@ -163,119 +153,231 @@
/* definitions for register: Post-trigger samples */
/* definitions for register: Sample counter */
/* definitions for register: Solid state relays control for channel 1 */
/* definitions for field: Solid state relays control for channel 1 in reg: Solid state relays control for channel 1 */
#define FMC_ADC_CORE_CH1_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_CORE_CH1_SSR_SHIFT 0
#define FMC_ADC_CORE_CH1_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH1_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Solid state relays control for channel 1 */
#define FMC_ADC_CORE_CH1_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH1_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH1_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH1_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 1 current value */
/* definitions for field: Channel 1 current value in reg: Channel 1 current value */
#define FMC_ADC_CORE_CH1_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH1_VAL_SHIFT 0
#define FMC_ADC_CORE_CH1_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH1_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 1 current value */
#define FMC_ADC_CORE_CH1_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH1_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH1_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH1_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Solid state relays control for channel 2 */
/* definitions for field: Solid state relays control for channel 2 in reg: Solid state relays control for channel 2 */
#define FMC_ADC_CORE_CH2_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_CORE_CH2_SSR_SHIFT 0
#define FMC_ADC_CORE_CH2_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH2_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Solid state relays control for channel 2 */
#define FMC_ADC_CORE_CH2_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH2_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH2_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH2_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 2 current value */
/* definitions for field: Channel 2 current value in reg: Channel 2 current value */
#define FMC_ADC_CORE_CH2_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH2_VAL_SHIFT 0
#define FMC_ADC_CORE_CH2_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH2_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 2 current value */
#define FMC_ADC_CORE_CH2_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH2_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH2_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH2_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Solid state relays control for channel 3 */
/* definitions for field: Solid state relays control for channel 3 in reg: Solid state relays control for channel 3 */
#define FMC_ADC_CORE_CH3_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_CORE_CH3_SSR_SHIFT 0
#define FMC_ADC_CORE_CH3_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH3_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Solid state relays control for channel 3 */
#define FMC_ADC_CORE_CH3_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH3_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH3_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH3_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 3 current value */
/* definitions for field: Channel 3 current value in reg: Channel 3 current value */
#define FMC_ADC_CORE_CH3_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH3_VAL_SHIFT 0
#define FMC_ADC_CORE_CH3_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH3_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 3 current value */
#define FMC_ADC_CORE_CH3_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH3_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH3_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH3_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Solid state relays control for channel 4 */
/* definitions for field: Solid state relays control for channel 4 in reg: Solid state relays control for channel 4 */
#define FMC_ADC_CORE_CH4_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_CORE_CH4_SSR_SHIFT 0
#define FMC_ADC_CORE_CH4_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH4_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Solid state relays control for channel 4 */
#define FMC_ADC_CORE_CH4_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH4_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH4_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH4_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 4 current value */
/* definitions for field: Channel 4 current value in reg: Channel 4 current value */
#define FMC_ADC_CORE_CH4_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH4_VAL_SHIFT 0
#define FMC_ADC_CORE_CH4_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH4_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 4 current value */
#define FMC_ADC_CORE_CH4_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH4_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH4_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH4_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Samples counter */
/* definitions for register: Channel 1 control register */
/* definitions for field: Solid state relays control for channel 1 in reg: Channel 1 control register */
#define FMC_ADC_CORE_CH1_CTL_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_CORE_CH1_CTL_SSR_SHIFT 0
#define FMC_ADC_CORE_CH1_CTL_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH1_CTL_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Channel 1 control register */
#define FMC_ADC_CORE_CH1_CTL_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH1_CTL_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH1_CTL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH1_CTL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 1 status register */
/* definitions for field: Channel 1 current ADC value in reg: Channel 1 status register */
#define FMC_ADC_CORE_CH1_STA_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH1_STA_VAL_SHIFT 0
#define FMC_ADC_CORE_CH1_STA_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH1_STA_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 1 status register */
#define FMC_ADC_CORE_CH1_STA_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH1_STA_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH1_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH1_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 1 gain calibration register */
/* definitions for field: Gain calibration for channel 1 in reg: Channel 1 gain calibration register */
#define FMC_ADC_CORE_CH1_GAIN_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH1_GAIN_VAL_SHIFT 0
#define FMC_ADC_CORE_CH1_GAIN_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH1_GAIN_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 1 gain calibration register */
#define FMC_ADC_CORE_CH1_GAIN_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH1_GAIN_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH1_GAIN_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH1_GAIN_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 1 offset calibration register */
/* definitions for field: Offset calibration for channel 1 in reg: Channel 1 offset calibration register */
#define FMC_ADC_CORE_CH1_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 17)
#define FMC_ADC_CORE_CH1_OFFSET_VAL_SHIFT 0
#define FMC_ADC_CORE_CH1_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 17)
#define FMC_ADC_CORE_CH1_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 17)
/* definitions for field: Reserved in reg: Channel 1 offset calibration register */
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(17, 15)
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_SHIFT 17
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
#define FMC_ADC_CORE_CH1_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
/* definitions for register: Channel 2 control register */
/* definitions for field: Solid state relays control for channel 2 in reg: Channel 2 control register */
#define FMC_ADC_CORE_CH2_CTL_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_CORE_CH2_CTL_SSR_SHIFT 0
#define FMC_ADC_CORE_CH2_CTL_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH2_CTL_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Channel 2 control register */
#define FMC_ADC_CORE_CH2_CTL_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH2_CTL_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH2_CTL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH2_CTL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 2 status register */
/* definitions for field: Channel 2 current ACD value in reg: Channel 2 status register */
#define FMC_ADC_CORE_CH2_STA_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH2_STA_VAL_SHIFT 0
#define FMC_ADC_CORE_CH2_STA_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH2_STA_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 2 status register */
#define FMC_ADC_CORE_CH2_STA_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH2_STA_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH2_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH2_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 2 gain calibration register */
/* definitions for field: Gain calibration for channel 2 in reg: Channel 2 gain calibration register */
#define FMC_ADC_CORE_CH2_GAIN_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH2_GAIN_VAL_SHIFT 0
#define FMC_ADC_CORE_CH2_GAIN_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH2_GAIN_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 2 gain calibration register */
#define FMC_ADC_CORE_CH2_GAIN_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH2_GAIN_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH2_GAIN_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH2_GAIN_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 2 offset calibration register */
/* definitions for field: Offset calibration for channel 2 in reg: Channel 2 offset calibration register */
#define FMC_ADC_CORE_CH2_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 17)
#define FMC_ADC_CORE_CH2_OFFSET_VAL_SHIFT 0
#define FMC_ADC_CORE_CH2_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 17)
#define FMC_ADC_CORE_CH2_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 17)
/* definitions for field: Reserved in reg: Channel 2 offset calibration register */
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(17, 15)
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_SHIFT 17
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
#define FMC_ADC_CORE_CH2_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
/* definitions for register: Channel 3 control register */
/* definitions for field: Solid state relays control for channel 3 in reg: Channel 3 control register */
#define FMC_ADC_CORE_CH3_CTL_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_CORE_CH3_CTL_SSR_SHIFT 0
#define FMC_ADC_CORE_CH3_CTL_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH3_CTL_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Channel 3 control register */
#define FMC_ADC_CORE_CH3_CTL_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH3_CTL_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH3_CTL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH3_CTL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 3 status register */
/* definitions for field: Channel 3 current ADC value in reg: Channel 3 status register */
#define FMC_ADC_CORE_CH3_STA_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH3_STA_VAL_SHIFT 0
#define FMC_ADC_CORE_CH3_STA_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH3_STA_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 3 status register */
#define FMC_ADC_CORE_CH3_STA_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH3_STA_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH3_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH3_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 3 gain calibration register */
/* definitions for field: Gain calibration for channel 3 in reg: Channel 3 gain calibration register */
#define FMC_ADC_CORE_CH3_GAIN_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH3_GAIN_VAL_SHIFT 0
#define FMC_ADC_CORE_CH3_GAIN_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH3_GAIN_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 3 gain calibration register */
#define FMC_ADC_CORE_CH3_GAIN_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH3_GAIN_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH3_GAIN_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH3_GAIN_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 3 offset calibration register */
/* definitions for field: Offset calibration for channel 3 in reg: Channel 3 offset calibration register */
#define FMC_ADC_CORE_CH3_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 17)
#define FMC_ADC_CORE_CH3_OFFSET_VAL_SHIFT 0
#define FMC_ADC_CORE_CH3_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 17)
#define FMC_ADC_CORE_CH3_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 17)
/* definitions for field: Reserved in reg: Channel 3 offset calibration register */
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(17, 15)
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_SHIFT 17
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
#define FMC_ADC_CORE_CH3_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
/* definitions for register: Channel 4 control register */
/* definitions for field: Solid state relays control for channel 4 in reg: Channel 4 control register */
#define FMC_ADC_CORE_CH4_CTL_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_CORE_CH4_CTL_SSR_SHIFT 0
#define FMC_ADC_CORE_CH4_CTL_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_CORE_CH4_CTL_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for field: Reserved in reg: Channel 4 control register */
#define FMC_ADC_CORE_CH4_CTL_RESERVED_MASK WBGEN2_GEN_MASK(7, 25)
#define FMC_ADC_CORE_CH4_CTL_RESERVED_SHIFT 7
#define FMC_ADC_CORE_CH4_CTL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 7, 25)
#define FMC_ADC_CORE_CH4_CTL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 7, 25)
/* definitions for register: Channel 4 status register */
/* definitions for field: Channel 4 current ADC value in reg: Channel 4 status register */
#define FMC_ADC_CORE_CH4_STA_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH4_STA_VAL_SHIFT 0
#define FMC_ADC_CORE_CH4_STA_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH4_STA_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 4 status register */
#define FMC_ADC_CORE_CH4_STA_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH4_STA_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH4_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH4_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 4 gain calibration register */
/* definitions for field: Gain calibration for channel 4 in reg: Channel 4 gain calibration register */
#define FMC_ADC_CORE_CH4_GAIN_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_CORE_CH4_GAIN_VAL_SHIFT 0
#define FMC_ADC_CORE_CH4_GAIN_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_CORE_CH4_GAIN_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 4 gain calibration register */
#define FMC_ADC_CORE_CH4_GAIN_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_CORE_CH4_GAIN_RESERVED_SHIFT 16
#define FMC_ADC_CORE_CH4_GAIN_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_CORE_CH4_GAIN_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 4 offset calibration register */
/* definitions for field: Offset calibration for channel 4 in reg: Channel 4 offset calibration register */
#define FMC_ADC_CORE_CH4_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 17)
#define FMC_ADC_CORE_CH4_OFFSET_VAL_SHIFT 0
#define FMC_ADC_CORE_CH4_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 17)
#define FMC_ADC_CORE_CH4_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 17)
/* definitions for field: Reserved in reg: Channel 4 offset calibration register */
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_MASK WBGEN2_GEN_MASK(17, 15)
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_SHIFT 17
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
#define FMC_ADC_CORE_CH4_OFFSET_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
PACKED struct FMC_ADC_CORE_WB {
/* [0x0]: REG Control register */
......@@ -292,40 +394,46 @@ PACKED struct FMC_ADC_CORE_WB {
uint32_t SHOTS;
/* [0x18]: REG Trigger address register */
uint32_t TRIG_POS;
/* [0x1c]: REG Gain calibration register */
uint32_t GAIN_CAL;
/* [0x20]: REG Offset calibration register */
uint32_t OFFSET_CAL;
/* [0x24]: REG Reserved register */
uint32_t RESERVED_0;
/* [0x28]: REG Reserved register */
uint32_t RESERVED_1;
/* [0x2c]: REG Reserved register */
uint32_t RESERVED_2;
/* [0x30]: REG Sample rate */
/* [0x1c]: REG Sample rate */
uint32_t SR;
/* [0x34]: REG Pre-trigger samples */
/* [0x20]: REG Pre-trigger samples */
uint32_t PRE_SAMPLES;
/* [0x38]: REG Post-trigger samples */
/* [0x24]: REG Post-trigger samples */
uint32_t POST_SAMPLES;
/* [0x3c]: REG Sample counter */
uint32_t SAMP_CNT;
/* [0x40]: REG Solid state relays control for channel 1 */
uint32_t CH1;
/* [0x44]: REG Channel 1 current value */
uint32_t CH1;
/* [0x48]: REG Solid state relays control for channel 2 */
uint32_t CH2;
/* [0x4c]: REG Channel 2 current value */
uint32_t CH2;
/* [0x50]: REG Solid state relays control for channel 3 */
uint32_t CH3;
/* [0x54]: REG Channel 3 current value */
uint32_t CH3;
/* [0x58]: REG Solid state relays control for channel 4 */
uint32_t CH4;
/* [0x5c]: REG Channel 4 current value */
uint32_t CH4;
/* [0x28]: REG Samples counter */
uint32_t SAMPLES_CNT;
/* [0x2c]: REG Channel 1 control register */
uint32_t CH1_CTL;
/* [0x30]: REG Channel 1 status register */
uint32_t CH1_STA;
/* [0x34]: REG Channel 1 gain calibration register */
uint32_t CH1_GAIN;
/* [0x38]: REG Channel 1 offset calibration register */
uint32_t CH1_OFFSET;
/* [0x3c]: REG Channel 2 control register */
uint32_t CH2_CTL;
/* [0x40]: REG Channel 2 status register */
uint32_t CH2_STA;
/* [0x44]: REG Channel 2 gain calibration register */
uint32_t CH2_GAIN;
/* [0x48]: REG Channel 2 offset calibration register */
uint32_t CH2_OFFSET;
/* [0x4c]: REG Channel 3 control register */
uint32_t CH3_CTL;
/* [0x50]: REG Channel 3 status register */
uint32_t CH3_STA;
/* [0x54]: REG Channel 3 gain calibration register */
uint32_t CH3_GAIN;
/* [0x58]: REG Channel 3 offset calibration register */
uint32_t CH3_OFFSET;
/* [0x5c]: REG Channel 4 control register */
uint32_t CH4_CTL;
/* [0x60]: REG Channel 4 status register */
uint32_t CH4_STA;
/* [0x64]: REG Channel 4 gain calibration register */
uint32_t CH4_GAIN;
/* [0x68]: REG Channel 4 offset calibration register */
uint32_t CH4_OFFSET;
};
#endif
......@@ -41,23 +41,26 @@
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Software trigger</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Number of shots</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Trigger address register</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Reserved register</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">Reserved register</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">Reserved register</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">Sample rate</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">Pre-trigger samples</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">Post-trigger samples</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">Sample counter</a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">Solid state relays control for channel 1</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">Channel 1 current value</a></span><br/>
<span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">Solid state relays control for channel 2</a></span><br/>
<span style="margin-left: 20px; ">3.20. <A href="#sect_3_20">Channel 2 current value</a></span><br/>
<span style="margin-left: 20px; ">3.21. <A href="#sect_3_21">Solid state relays control for channel 3</a></span><br/>
<span style="margin-left: 20px; ">3.22. <A href="#sect_3_22">Channel 3 current value</a></span><br/>
<span style="margin-left: 20px; ">3.23. <A href="#sect_3_23">Solid state relays control for channel 4</a></span><br/>
<span style="margin-left: 20px; ">3.24. <A href="#sect_3_24">Channel 4 current value</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Sample rate</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Pre-trigger samples</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Post-trigger samples</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">Samples counter</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">Channel 1 control register</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">Channel 1 status register</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">Channel 1 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">Channel 1 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">Channel 2 control register</a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">Channel 2 status register</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">Channel 2 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">Channel 2 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.20. <A href="#sect_3_20">Channel 3 control register</a></span><br/>
<span style="margin-left: 20px; ">3.21. <A href="#sect_3_21">Channel 3 status register</a></span><br/>
<span style="margin-left: 20px; ">3.22. <A href="#sect_3_22">Channel 3 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.23. <A href="#sect_3_23">Channel 3 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.24. <A href="#sect_3_24">Channel 4 control register</a></span><br/>
<span style="margin-left: 20px; ">3.25. <A href="#sect_3_25">Channel 4 status register</a></span><br/>
<span style="margin-left: 20px; ">3.26. <A href="#sect_3_26">Channel 4 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.27. <A href="#sect_3_27">Channel 4 offset calibration register</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -204,13 +207,13 @@ TRIG_POS
REG
</td>
<td >
<A href="#GAIN_CAL">Gain calibration register</a>
<A href="#SR">Sample rate</a>
</td>
<td class="td_code">
fmc_adc_core_gain_cal
fmc_adc_core_sr
</td>
<td class="td_code">
GAIN_CAL
SR
</td>
</tr>
<tr class="tr_odd">
......@@ -221,13 +224,13 @@ GAIN_CAL
REG
</td>
<td >
<A href="#OFFSET_CAL">Offset calibration register</a>
<A href="#PRE_SAMPLES">Pre-trigger samples</a>
</td>
<td class="td_code">
fmc_adc_core_offset_cal
fmc_adc_core_pre_samples
</td>
<td class="td_code">
OFFSET_CAL
PRE_SAMPLES
</td>
</tr>
<tr class="tr_even">
......@@ -238,13 +241,13 @@ OFFSET_CAL
REG
</td>
<td >
<A href="#RESERVED_0">Reserved register</a>
<A href="#POST_SAMPLES">Post-trigger samples</a>
</td>
<td class="td_code">
fmc_adc_core_reserved_0
fmc_adc_core_post_samples
</td>
<td class="td_code">
RESERVED_0
POST_SAMPLES
</td>
</tr>
<tr class="tr_odd">
......@@ -255,13 +258,13 @@ RESERVED_0
REG
</td>
<td >
<A href="#RESERVED_1">Reserved register</a>
<A href="#SAMPLES_CNT">Samples counter</a>
</td>
<td class="td_code">
fmc_adc_core_reserved_1
fmc_adc_core_samples_cnt
</td>
<td class="td_code">
RESERVED_1
SAMPLES_CNT
</td>
</tr>
<tr class="tr_even">
......@@ -272,13 +275,13 @@ RESERVED_1
REG
</td>
<td >
<A href="#RESERVED_2">Reserved register</a>
<A href="#CH1_CTL">Channel 1 control register</a>
</td>
<td class="td_code">
fmc_adc_core_reserved_2
fmc_adc_core_ch1_ctl
</td>
<td class="td_code">
RESERVED_2
CH1_CTL
</td>
</tr>
<tr class="tr_odd">
......@@ -289,13 +292,13 @@ RESERVED_2
REG
</td>
<td >
<A href="#SR">Sample rate</a>
<A href="#CH1_STA">Channel 1 status register</a>
</td>
<td class="td_code">
fmc_adc_core_sr
fmc_adc_core_ch1_sta
</td>
<td class="td_code">
SR
CH1_STA
</td>
</tr>
<tr class="tr_even">
......@@ -306,13 +309,13 @@ SR
REG
</td>
<td >
<A href="#PRE_SAMPLES">Pre-trigger samples</a>
<A href="#CH1_GAIN">Channel 1 gain calibration register</a>
</td>
<td class="td_code">
fmc_adc_core_pre_samples
fmc_adc_core_ch1_gain
</td>
<td class="td_code">
PRE_SAMPLES
CH1_GAIN
</td>
</tr>
<tr class="tr_odd">
......@@ -323,13 +326,13 @@ PRE_SAMPLES
REG
</td>
<td >
<A href="#POST_SAMPLES">Post-trigger samples</a>
<A href="#CH1_OFFSET">Channel 1 offset calibration register</a>
</td>
<td class="td_code">
fmc_adc_core_post_samples
fmc_adc_core_ch1_offset
</td>
<td class="td_code">
POST_SAMPLES
CH1_OFFSET
</td>
</tr>
<tr class="tr_even">
......@@ -340,13 +343,13 @@ POST_SAMPLES
REG
</td>
<td >
<A href="#SAMP_CNT">Sample counter</a>
<A href="#CH2_CTL">Channel 2 control register</a>
</td>
<td class="td_code">
fmc_adc_core_samp_cnt
fmc_adc_core_ch2_ctl
</td>
<td class="td_code">
SAMP_CNT
CH2_CTL
</td>
</tr>
<tr class="tr_odd">
......@@ -357,13 +360,13 @@ SAMP_CNT
REG
</td>
<td >
<A href="#CH1">Solid state relays control for channel 1</a>
<A href="#CH2_STA">Channel 2 status register</a>
</td>
<td class="td_code">
fmc_adc_core_ch1
fmc_adc_core_ch2_sta
</td>
<td class="td_code">
CH1
CH2_STA
</td>
</tr>
<tr class="tr_even">
......@@ -374,13 +377,13 @@ CH1
REG
</td>
<td >
<A href="#CH1">Channel 1 current value</a>
<A href="#CH2_GAIN">Channel 2 gain calibration register</a>
</td>
<td class="td_code">
fmc_adc_core_ch1
fmc_adc_core_ch2_gain
</td>
<td class="td_code">
CH1
CH2_GAIN
</td>
</tr>
<tr class="tr_odd">
......@@ -391,13 +394,13 @@ CH1
REG
</td>
<td >
<A href="#CH2">Solid state relays control for channel 2</a>
<A href="#CH2_OFFSET">Channel 2 offset calibration register</a>
</td>
<td class="td_code">
fmc_adc_core_ch2
fmc_adc_core_ch2_offset
</td>
<td class="td_code">
CH2
CH2_OFFSET
</td>
</tr>
<tr class="tr_even">
......@@ -408,13 +411,13 @@ CH2
REG
</td>
<td >
<A href="#CH2">Channel 2 current value</a>
<A href="#CH3_CTL">Channel 3 control register</a>
</td>
<td class="td_code">
fmc_adc_core_ch2
fmc_adc_core_ch3_ctl
</td>
<td class="td_code">
CH2
CH3_CTL
</td>
</tr>
<tr class="tr_odd">
......@@ -425,13 +428,13 @@ CH2
REG
</td>
<td >
<A href="#CH3">Solid state relays control for channel 3</a>
<A href="#CH3_STA">Channel 3 status register</a>
</td>
<td class="td_code">
fmc_adc_core_ch3
fmc_adc_core_ch3_sta
</td>
<td class="td_code">
CH3
CH3_STA
</td>
</tr>
<tr class="tr_even">
......@@ -442,13 +445,13 @@ CH3
REG
</td>
<td >
<A href="#CH3">Channel 3 current value</a>
<A href="#CH3_GAIN">Channel 3 gain calibration register</a>
</td>
<td class="td_code">
fmc_adc_core_ch3
fmc_adc_core_ch3_gain
</td>
<td class="td_code">
CH3
CH3_GAIN
</td>
</tr>
<tr class="tr_odd">
......@@ -459,13 +462,13 @@ CH3
REG
</td>
<td >
<A href="#CH4">Solid state relays control for channel 4</a>
<A href="#CH3_OFFSET">Channel 3 offset calibration register</a>
</td>
<td class="td_code">
fmc_adc_core_ch4
fmc_adc_core_ch3_offset
</td>
<td class="td_code">
CH4
CH3_OFFSET
</td>
</tr>
<tr class="tr_even">
......@@ -476,13 +479,64 @@ CH4
REG
</td>
<td >
<A href="#CH4">Channel 4 current value</a>
<A href="#CH4_CTL">Channel 4 control register</a>
</td>
<td class="td_code">
fmc_adc_core_ch4_ctl
</td>
<td class="td_code">
CH4_CTL
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x18
</td>
<td >
REG
</td>
<td >
<A href="#CH4_STA">Channel 4 status register</a>
</td>
<td class="td_code">
fmc_adc_core_ch4
fmc_adc_core_ch4_sta
</td>
<td class="td_code">
CH4
CH4_STA
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x19
</td>
<td >
REG
</td>
<td >
<A href="#CH4_GAIN">Channel 4 gain calibration register</a>
</td>
<td class="td_code">
fmc_adc_core_ch4_gain
</td>
<td class="td_code">
CH4_GAIN
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x1a
</td>
<td >
REG
</td>
<td >
<A href="#CH4_OFFSET">Channel 4 offset calibration register</a>
</td>
<td class="td_code">
fmc_adc_core_ch4_offset
</td>
<td class="td_code">
CH4_OFFSET
</td>
</tr>
</table>
......@@ -823,7 +877,7 @@ fmc_adc_core_trig_cfg_hw_trig_sel_o
</td>
<td class="td_pblock_right">
fmc_adc_core_trig_cfg_ext_trig_pol_o
fmc_adc_core_trig_cfg_hw_trig_pol_o
</td>
<td class="td_arrow_right">
&rarr;
......@@ -1180,7 +1234,7 @@ fmc_adc_core_trig_pos_i[31:0]
</td>
<td class="td_pblock_right">
<b>Gain calibration register:</b>
<b>Sample rate:</b>
</td>
<td class="td_arrow_right">
......@@ -1197,7 +1251,24 @@ fmc_adc_core_trig_pos_i[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_gain_cal_o[31:0]
fmc_adc_core_sr_deci_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_sr_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1231,7 +1302,7 @@ fmc_adc_core_gain_cal_o[31:0]
</td>
<td class="td_pblock_right">
<b>Offset calibration register:</b>
<b>Pre-trigger samples:</b>
</td>
<td class="td_arrow_right">
......@@ -1248,7 +1319,7 @@ fmc_adc_core_gain_cal_o[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_offset_cal_o[31:0]
fmc_adc_core_pre_samples_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1282,7 +1353,7 @@ fmc_adc_core_offset_cal_o[31:0]
</td>
<td class="td_pblock_right">
<b>Reserved register:</b>
<b>Post-trigger samples:</b>
</td>
<td class="td_arrow_right">
......@@ -1299,10 +1370,10 @@ fmc_adc_core_offset_cal_o[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_reserved_0_i[31:0]
fmc_adc_core_post_samples_o[31:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
<tr>
......@@ -1333,7 +1404,7 @@ fmc_adc_core_reserved_0_i[31:0]
</td>
<td class="td_pblock_right">
<b>Reserved register:</b>
<b>Samples counter:</b>
</td>
<td class="td_arrow_right">
......@@ -1350,7 +1421,7 @@ fmc_adc_core_reserved_0_i[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_reserved_1_i[31:0]
fmc_adc_core_samples_cnt_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1384,7 +1455,7 @@ fmc_adc_core_reserved_1_i[31:0]
</td>
<td class="td_pblock_right">
<b>Reserved register:</b>
<b>Channel 1 control register:</b>
</td>
<td class="td_arrow_right">
......@@ -1401,10 +1472,10 @@ fmc_adc_core_reserved_1_i[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_reserved_2_i[31:0]
fmc_adc_core_ch1_ctl_ssr_o[6:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
<tr>
......@@ -1415,13 +1486,13 @@ fmc_adc_core_reserved_2_i[31:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_ctl_reserved_o[24:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -1432,10 +1503,10 @@ fmc_adc_core_reserved_2_i[31:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
<b>Sample rate:</b>
</td>
<td class="td_arrow_right">
......@@ -1452,10 +1523,10 @@ fmc_adc_core_reserved_2_i[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_sr_deci_o[15:0]
<b>Channel 1 status register:</b>
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -1469,10 +1540,10 @@ fmc_adc_core_sr_deci_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_sr_reserved_o[15:0]
fmc_adc_core_ch1_sta_val_i[15:0]
</td>
<td class="td_arrow_right">
&rArr;
&lArr;
</td>
</tr>
<tr>
......@@ -1483,13 +1554,13 @@ fmc_adc_core_sr_reserved_o[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_sta_reserved_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
......@@ -1500,10 +1571,10 @@ fmc_adc_core_sr_reserved_o[15:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
<b>Pre-trigger samples:</b>
</td>
<td class="td_arrow_right">
......@@ -1520,10 +1591,10 @@ fmc_adc_core_sr_reserved_o[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_pre_samples_o[31:0]
<b>Channel 1 gain calibration register:</b>
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -1534,13 +1605,13 @@ fmc_adc_core_pre_samples_o[31:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_gain_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -1554,10 +1625,10 @@ fmc_adc_core_pre_samples_o[31:0]
</td>
<td class="td_pblock_right">
<b>Post-trigger samples:</b>
fmc_adc_core_ch1_gain_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -1568,13 +1639,13 @@ fmc_adc_core_pre_samples_o[31:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
fmc_adc_core_post_samples_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -1585,10 +1656,10 @@ fmc_adc_core_post_samples_o[31:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
<b>Channel 1 offset calibration register:</b>
</td>
<td class="td_arrow_right">
......@@ -1605,10 +1676,10 @@ fmc_adc_core_post_samples_o[31:0]
</td>
<td class="td_pblock_right">
<b>Sample counter:</b>
fmc_adc_core_ch1_offset_val_o[16:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
......@@ -1622,10 +1693,10 @@ fmc_adc_core_post_samples_o[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_samp_cnt_i[31:0]
fmc_adc_core_ch1_offset_reserved_o[14:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
<tr>
......@@ -1656,7 +1727,7 @@ fmc_adc_core_samp_cnt_i[31:0]
</td>
<td class="td_pblock_right">
<b>Solid state relays control for channel 1:</b>
<b>Channel 2 control register:</b>
</td>
<td class="td_arrow_right">
......@@ -1673,7 +1744,7 @@ fmc_adc_core_samp_cnt_i[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_ssr_o[6:0]
fmc_adc_core_ch2_ctl_ssr_o[6:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1690,7 +1761,7 @@ fmc_adc_core_ch1_ssr_o[6:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_reserved_o[24:0]
fmc_adc_core_ch2_ctl_reserved_o[24:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1724,7 +1795,7 @@ fmc_adc_core_ch1_reserved_o[24:0]
</td>
<td class="td_pblock_right">
<b>Channel 1 current value:</b>
<b>Channel 2 status register:</b>
</td>
<td class="td_arrow_right">
......@@ -1741,7 +1812,7 @@ fmc_adc_core_ch1_reserved_o[24:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_val_i[15:0]
fmc_adc_core_ch2_sta_val_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1758,7 +1829,7 @@ fmc_adc_core_ch1_val_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch1_reserved_i[15:0]
fmc_adc_core_ch2_sta_reserved_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1792,7 +1863,7 @@ fmc_adc_core_ch1_reserved_i[15:0]
</td>
<td class="td_pblock_right">
<b>Solid state relays control for channel 2:</b>
<b>Channel 2 gain calibration register:</b>
</td>
<td class="td_arrow_right">
......@@ -1809,7 +1880,7 @@ fmc_adc_core_ch1_reserved_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_ssr_o[6:0]
fmc_adc_core_ch2_gain_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1826,7 +1897,7 @@ fmc_adc_core_ch2_ssr_o[6:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_reserved_o[24:0]
fmc_adc_core_ch2_gain_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1860,7 +1931,7 @@ fmc_adc_core_ch2_reserved_o[24:0]
</td>
<td class="td_pblock_right">
<b>Channel 2 current value:</b>
<b>Channel 2 offset calibration register:</b>
</td>
<td class="td_arrow_right">
......@@ -1877,10 +1948,10 @@ fmc_adc_core_ch2_reserved_o[24:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_val_i[15:0]
fmc_adc_core_ch2_offset_val_o[16:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
<tr>
......@@ -1894,10 +1965,10 @@ fmc_adc_core_ch2_val_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch2_reserved_i[15:0]
fmc_adc_core_ch2_offset_reserved_o[14:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
<tr>
......@@ -1928,7 +1999,7 @@ fmc_adc_core_ch2_reserved_i[15:0]
</td>
<td class="td_pblock_right">
<b>Solid state relays control for channel 3:</b>
<b>Channel 3 control register:</b>
</td>
<td class="td_arrow_right">
......@@ -1945,7 +2016,7 @@ fmc_adc_core_ch2_reserved_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_ssr_o[6:0]
fmc_adc_core_ch3_ctl_ssr_o[6:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1962,7 +2033,7 @@ fmc_adc_core_ch3_ssr_o[6:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_reserved_o[24:0]
fmc_adc_core_ch3_ctl_reserved_o[24:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1996,7 +2067,7 @@ fmc_adc_core_ch3_reserved_o[24:0]
</td>
<td class="td_pblock_right">
<b>Channel 3 current value:</b>
<b>Channel 3 status register:</b>
</td>
<td class="td_arrow_right">
......@@ -2013,7 +2084,7 @@ fmc_adc_core_ch3_reserved_o[24:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_val_i[15:0]
fmc_adc_core_ch3_sta_val_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -2030,7 +2101,7 @@ fmc_adc_core_ch3_val_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch3_reserved_i[15:0]
fmc_adc_core_ch3_sta_reserved_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -2064,7 +2135,7 @@ fmc_adc_core_ch3_reserved_i[15:0]
</td>
<td class="td_pblock_right">
<b>Solid state relays control for channel 4:</b>
<b>Channel 3 gain calibration register:</b>
</td>
<td class="td_arrow_right">
......@@ -2081,7 +2152,7 @@ fmc_adc_core_ch3_reserved_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_ssr_o[6:0]
fmc_adc_core_ch3_gain_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2098,7 +2169,7 @@ fmc_adc_core_ch4_ssr_o[6:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_reserved_o[24:0]
fmc_adc_core_ch3_gain_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2132,7 +2203,7 @@ fmc_adc_core_ch4_reserved_o[24:0]
</td>
<td class="td_pblock_right">
<b>Channel 4 current value:</b>
<b>Channel 3 offset calibration register:</b>
</td>
<td class="td_arrow_right">
......@@ -2149,10 +2220,10 @@ fmc_adc_core_ch4_reserved_o[24:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_val_i[15:0]
fmc_adc_core_ch3_offset_val_o[16:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
<tr>
......@@ -2166,108 +2237,1214 @@ fmc_adc_core_ch4_val_i[15:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_reserved_i[15:0]
fmc_adc_core_ch3_offset_reserved_o[14:0]
</td>
<td class="td_arrow_right">
&lArr;
&rArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="CTL"></a>
<h3><a name="sect_3_1">3.1. Control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
<td class="td_arrow_left">
</td>
<td class="td_code">
fmc_adc_core_ctl
<td class="td_pblock_left">
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_code">
0x0
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
<td class="td_arrow_left">
</td>
<td class="td_code">
CTL
<td class="td_pblock_left">
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
<td class="td_sym_center">
</td>
<td class="td_code">
0x0
<td class="td_pblock_right">
<b>Channel 4 control register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
<td class="td_arrow_left">
</td>
<td class="td_bit">
30
<td class="td_pblock_left">
</td>
<td class="td_bit">
29
<td class="td_sym_center">
</td>
<td class="td_bit">
28
<td class="td_pblock_right">
fmc_adc_core_ch4_ctl_ssr_o[6:0]
</td>
<td class="td_bit">
27
<td class="td_arrow_right">
&rArr;
</td>
<td class="td_bit">
26
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_bit">
25
<td class="td_pblock_left">
</td>
<td class="td_bit">
24
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_ctl_reserved_o[24:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[23:16]
<td class="td_arrow_left">
</td>
<td >
<td class="td_pblock_left">
</td>
<td >
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td >
<td class="td_arrow_right">
</td>
<td >
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td >
<td class="td_pblock_left">
</td>
<td >
<td class="td_sym_center">
</td>
<td >
<td class="td_pblock_right">
<b>Channel 4 status register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_sta_val_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_sta_reserved_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 4 gain calibration register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_gain_val_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_gain_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 4 offset calibration register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_offset_val_o[16:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_ch4_offset_reserved_o[14:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="CTL"></a>
<h3><a name="sect_3_1">3.1. Control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ctl
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CTL
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ACQ_LED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TRIG_LED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TEST_DATA_EN
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
MAN_BITSLIP
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
OFFSET_DAC_CLR_N
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_CLK_OE
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
FSM_CMD[1:0]
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
FSM_CMD
</b>[<i>read/write</i>]: State machine commands
<br>1: start<br>2: stop
<li><b>
FMC_CLK_OE
</b>[<i>read/write</i>]: FMC Si750 output enable
<li><b>
OFFSET_DAC_CLR_N
</b>[<i>read/write</i>]: Offset DACs clear (active low)
<li><b>
MAN_BITSLIP
</b>[<i>write-only</i>]: Manual serdes bitslip
<li><b>
TEST_DATA_EN
</b>[<i>read/write</i>]: Enable test data
<br>Write the address counter value instead of ADC data to DDR
<li><b>
TRIG_LED
</b>[<i>read/write</i>]: Manual TRIG LED
<br>Manual control of the front panel TRIG LED
<li><b>
ACQ_LED
</b>[<i>read/write</i>]: Manual ACQ LED
<br>Manual control of the front panel ACQ LED
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="STA"></a>
<h3><a name="sect_3_2">3.2. Status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_sta
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
STA
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[26:19]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[18:11]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[10:3]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=3 class="td_field">
RESERVED[2:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SERDES_SYNCED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SERDES_PLL
</td>
<td style="border: solid 1px black;" colspan=3 class="td_field">
FSM[2:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
FSM
</b>[<i>read-only</i>]: State machine status
<br>States:<br>1: IDLE<br>2: PRE_TRIG<br>3: WAIT_TRIG<br>4: POST_TRIG<br>5: DECR_SHOT<br>7: Illegal
<li><b>
SERDES_PLL
</b>[<i>read-only</i>]: SerDes PLL status
<li><b>
SERDES_SYNCED
</b>[<i>read-only</i>]: SerDes synchronization status
<br>0: bitslip in progress<br>1: serdes synchronized
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="TRIG_CFG"></a>
<h3><a name="sect_3_3">3.3. Trigger configuration</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_trig_cfg
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_CFG
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
INT_TRIG_THRES[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
INT_TRIG_THRES[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[9:2]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=2 class="td_field">
RESERVED[1:0]
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
INT_TRIG_SEL[1:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SW_TRIG_EN
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
HW_TRIG_EN
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
HW_TRIG_POL
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
HW_TRIG_SEL
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
HW_TRIG_SEL
</b>[<i>read/write</i>]: Hardware trigger selection
<br>0: internal (data threshold)<br>1: external (front panel trigger input)
<li><b>
HW_TRIG_POL
</b>[<i>read/write</i>]: Hardware trigger polarity
<br>0: positive edge/slope<br>1: negative edge/slope
<li><b>
HW_TRIG_EN
</b>[<i>read/write</i>]: Hardware trigger enable
<br>0: disable<br>1: enable
<li><b>
SW_TRIG_EN
</b>[<i>read/write</i>]: Software trigger enable
<br>0: disable<br>1: enable
<li><b>
INT_TRIG_SEL
</b>[<i>read/write</i>]: Channel selection for internal trigger
<br>00: channel 1<br>01: channel 2<br>10: channel 3<br>11: channel 4
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
<li><b>
INT_TRIG_THRES
</b>[<i>read/write</i>]: Threshold for internal trigger
<br>Treated as offset binary and compared to raw ADC data
</ul>
<a name="TRIG_DLY"></a>
<h3><a name="sect_3_4">3.4. Trigger delay</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_trig_dly
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_DLY
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
......@@ -2294,7 +3471,7 @@ RESERVED[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
TRIG_DLY[23:16]
</td>
<td >
......@@ -2348,7 +3525,7 @@ RESERVED[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
TRIG_DLY[15:8]
</td>
<td >
......@@ -2401,26 +3578,26 @@ RESERVED[7:0]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ACQ_LED
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[7:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TRIG_LED
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TEST_DATA_EN
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
MAN_BITSLIP
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
OFFSET_DAC_CLR_N
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_CLK_OE
<td >
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
FSM_CMD[1:0]
<td >
</td>
<td >
......@@ -2429,44 +3606,19 @@ FSM_CMD[1:0]
</table>
<ul>
<li><b>
FSM_CMD
</b>[<i>read/write</i>]: State machine commands
<br>1: start<br>2: stop
<li><b>
FMC_CLK_OE
</b>[<i>read/write</i>]: FMC Si750 output enable
<li><b>
OFFSET_DAC_CLR_N
</b>[<i>read/write</i>]: Offset DACs clear (active low)
<li><b>
MAN_BITSLIP
</b>[<i>write-only</i>]: Manual serdes bitslip
<li><b>
TEST_DATA_EN
</b>[<i>read/write</i>]: Enable test data
<br>Write the address counter value instead of ADC data to DDR
<li><b>
TRIG_LED
</b>[<i>read/write</i>]: Manual TRIG LED
<br>Manual control of the front panel TRIG LED
<li><b>
ACQ_LED
</b>[<i>read/write</i>]: Manual ACQ LED
<br>Manual control of the front panel ACQ LED
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
TRIG_DLY
</b>[<i>read/write</i>]: Trigger delay value
<br>Delay to apply on the trigger in sampling clock ticks
</ul>
<a name="STA"></a>
<h3><a name="sect_3_2">3.2. Status register</a></h3>
<a name="SW_TRIG"></a>
<h3><a name="sect_3_5">3.5. Software trigger</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_sta
fmc_adc_core_sw_trig
</td>
</tr>
<tr>
......@@ -2474,7 +3626,7 @@ fmc_adc_core_sta
<b>HW address: </b>
</td>
<td class="td_code">
0x1
0x4
</td>
</tr>
<tr>
......@@ -2482,7 +3634,7 @@ fmc_adc_core_sta
<b>C prefix: </b>
</td>
<td class="td_code">
STA
SW_TRIG
</td>
</tr>
<tr>
......@@ -2490,10 +3642,13 @@ STA
<b>C offset: </b>
</td>
<td class="td_code">
0x4
0x10
</td>
</tr>
</table>
<p>
Writing (anything) to this register generates a software trigger
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
......@@ -2523,7 +3678,7 @@ STA
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[26:19]
SW_TRIG[31:24]
</td>
<td >
......@@ -2577,7 +3732,7 @@ RESERVED[26:19]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[18:11]
SW_TRIG[23:16]
</td>
<td >
......@@ -2631,7 +3786,7 @@ RESERVED[18:11]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[10:3]
SW_TRIG[15:8]
</td>
<td >
......@@ -2684,17 +3839,17 @@ RESERVED[10:3]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=3 class="td_field">
RESERVED[2:0]
<td style="border: solid 1px black;" colspan=8 class="td_field">
SW_TRIG[7:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SERDES_SYNCED
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SERDES_PLL
<td >
</td>
<td style="border: solid 1px black;" colspan=3 class="td_field">
FSM[2:0]
<td >
</td>
<td >
......@@ -2712,30 +3867,18 @@ FSM[2:0]
</table>
<ul>
<li><b>
FSM
</b>[<i>read-only</i>]: State machine status
<br>States:<br>1: IDLE<br>2: PRE_TRIG<br>3: WAIT_TRIG<br>4: POST_TRIG<br>5: DECR_SHOT<br>7: Illegal
<li><b>
SERDES_PLL
</b>[<i>read-only</i>]: SerDes PLL status
<li><b>
SERDES_SYNCED
</b>[<i>read-only</i>]: SerDes synchronization status
<br>0: bitslip in progress<br>1: serdes synchronized
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
SW_TRIG
</b>[<i>write-only</i>]: Software trigger
</ul>
<a name="TRIG_CFG"></a>
<h3><a name="sect_3_3">3.3. Trigger configuration</a></h3>
<a name="SHOTS"></a>
<h3><a name="sect_3_6">3.6. Number of shots</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_trig_cfg
fmc_adc_core_shots
</td>
</tr>
<tr>
......@@ -2743,7 +3886,7 @@ fmc_adc_core_trig_cfg
<b>HW address: </b>
</td>
<td class="td_code">
0x2
0x5
</td>
</tr>
<tr>
......@@ -2751,7 +3894,7 @@ fmc_adc_core_trig_cfg
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_CFG
SHOTS
</td>
</tr>
<tr>
......@@ -2759,7 +3902,7 @@ TRIG_CFG
<b>C offset: </b>
</td>
<td class="td_code">
0x8
0x14
</td>
</tr>
</table>
......@@ -2792,7 +3935,7 @@ TRIG_CFG
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
INT_TRIG_THRES[15:8]
RESERVED[15:8]
</td>
<td >
......@@ -2846,7 +3989,7 @@ INT_TRIG_THRES[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
INT_TRIG_THRES[7:0]
RESERVED[7:0]
</td>
<td >
......@@ -2900,7 +4043,7 @@ INT_TRIG_THRES[7:0]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[9:2]
NB[15:8]
</td>
<td >
......@@ -2953,23 +4096,23 @@ RESERVED[9:2]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=2 class="td_field">
RESERVED[1:0]
<td style="border: solid 1px black;" colspan=8 class="td_field">
NB[7:0]
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
INT_TRIG_SEL[1:0]
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SW_TRIG_EN
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
HW_TRIG_EN
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
EXT_TRIG_POL
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
HW_TRIG_SEL
<td >
</td>
<td >
......@@ -2981,43 +4124,23 @@ HW_TRIG_SEL
</table>
<ul>
<li><b>
HW_TRIG_SEL
</b>[<i>read/write</i>]: Hardware trigger selection
<br>0: internal (data threshold)<br>1: external (front panel trigger input)
<li><b>
EXT_TRIG_POL
</b>[<i>read/write</i>]: External hardware trigger polarity
<br>0: positive edge<br>1: negative edge
<li><b>
HW_TRIG_EN
</b>[<i>read/write</i>]: Hardware trigger enable
<br>0: disable<br>1: enable
<li><b>
SW_TRIG_EN
</b>[<i>read/write</i>]: Software trigger enable
<br>0: disable<br>1: enable
<li><b>
INT_TRIG_SEL
</b>[<i>read/write</i>]: Channel selection for internal trigger
<br>00: channel 1<br>01: channel 2<br>10: channel 3<br>11: channel 4
NB
</b>[<i>read/write</i>]: Number of shots
<br>Number of shots required in multi-shot mode, set to one for single-shot mode
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
<li><b>
INT_TRIG_THRES
</b>[<i>read/write</i>]: Threshold for internal trigger
<br>Treated as two's complement and compared to raw ADC data
</ul>
<a name="TRIG_DLY"></a>
<h3><a name="sect_3_4">3.4. Trigger delay</a></h3>
<a name="TRIG_POS"></a>
<h3><a name="sect_3_7">3.7. Trigger address register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_trig_dly
fmc_adc_core_trig_pos
</td>
</tr>
<tr>
......@@ -3025,7 +4148,7 @@ fmc_adc_core_trig_dly
<b>HW address: </b>
</td>
<td class="td_code">
0x3
0x6
</td>
</tr>
<tr>
......@@ -3033,7 +4156,7 @@ fmc_adc_core_trig_dly
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_DLY
TRIG_POS
</td>
</tr>
<tr>
......@@ -3041,7 +4164,7 @@ TRIG_DLY
<b>C offset: </b>
</td>
<td class="td_code">
0xc
0x18
</td>
</tr>
</table>
......@@ -3074,7 +4197,7 @@ TRIG_DLY
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[31:24]
TRIG_POS[31:24]
</td>
<td >
......@@ -3128,7 +4251,7 @@ TRIG_DLY[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[23:16]
TRIG_POS[23:16]
</td>
<td >
......@@ -3182,7 +4305,7 @@ TRIG_DLY[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[15:8]
TRIG_POS[15:8]
</td>
<td >
......@@ -3236,7 +4359,7 @@ TRIG_DLY[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[7:0]
TRIG_POS[7:0]
</td>
<td >
......@@ -3263,19 +4386,19 @@ TRIG_DLY[7:0]
</table>
<ul>
<li><b>
TRIG_DLY
</b>[<i>read/write</i>]: Trigger delay value
<br>Delay to apply on the trigger in sampling clock ticks
TRIG_POS
</b>[<i>read-only</i>]: Trigger address
<br>Trigger address in DDR memory.<br>Only used in single-shot mode
</ul>
<a name="SW_TRIG"></a>
<h3><a name="sect_3_5">3.5. Software trigger</a></h3>
<a name="SR"></a>
<h3><a name="sect_3_8">3.8. Sample rate</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_sw_trig
fmc_adc_core_sr
</td>
</tr>
<tr>
......@@ -3283,7 +4406,7 @@ fmc_adc_core_sw_trig
<b>HW address: </b>
</td>
<td class="td_code">
0x4
0x7
</td>
</tr>
<tr>
......@@ -3291,7 +4414,7 @@ fmc_adc_core_sw_trig
<b>C prefix: </b>
</td>
<td class="td_code">
SW_TRIG
SR
</td>
</tr>
<tr>
......@@ -3299,13 +4422,10 @@ SW_TRIG
<b>C offset: </b>
</td>
<td class="td_code">
0x10
0x1c
</td>
</tr>
</table>
<p>
Writing (anything) to this register generates a software trigger
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
......@@ -3335,7 +4455,7 @@ Writing (anything) to this register generates a software trigger
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SW_TRIG[31:24]
RESERVED[15:8]
</td>
<td >
......@@ -3389,7 +4509,7 @@ SW_TRIG[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SW_TRIG[23:16]
RESERVED[7:0]
</td>
<td >
......@@ -3443,7 +4563,7 @@ SW_TRIG[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SW_TRIG[15:8]
DECI[15:8]
</td>
<td >
......@@ -3497,7 +4617,7 @@ SW_TRIG[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SW_TRIG[7:0]
DECI[7:0]
</td>
<td >
......@@ -3524,18 +4644,23 @@ SW_TRIG[7:0]
</table>
<ul>
<li><b>
SW_TRIG
</b>[<i>write-only</i>]: Software trigger
DECI
</b>[<i>read/write</i>]: Sample rate decimation
<br>Decimation factor
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="SHOTS"></a>
<h3><a name="sect_3_6">3.6. Number of shots</a></h3>
<a name="PRE_SAMPLES"></a>
<h3><a name="sect_3_9">3.9. Pre-trigger samples</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_shots
fmc_adc_core_pre_samples
</td>
</tr>
<tr>
......@@ -3543,7 +4668,7 @@ fmc_adc_core_shots
<b>HW address: </b>
</td>
<td class="td_code">
0x5
0x8
</td>
</tr>
<tr>
......@@ -3551,7 +4676,7 @@ fmc_adc_core_shots
<b>C prefix: </b>
</td>
<td class="td_code">
SHOTS
PRE_SAMPLES
</td>
</tr>
<tr>
......@@ -3559,7 +4684,7 @@ SHOTS
<b>C offset: </b>
</td>
<td class="td_code">
0x14
0x20
</td>
</tr>
</table>
......@@ -3592,7 +4717,7 @@ SHOTS
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
PRE_SAMPLES[31:24]
</td>
<td >
......@@ -3646,7 +4771,7 @@ RESERVED[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
PRE_SAMPLES[23:16]
</td>
<td >
......@@ -3700,7 +4825,7 @@ RESERVED[7:0]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
NB[15:8]
PRE_SAMPLES[15:8]
</td>
<td >
......@@ -3754,7 +4879,7 @@ NB[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
NB[7:0]
PRE_SAMPLES[7:0]
</td>
<td >
......@@ -3781,23 +4906,19 @@ NB[7:0]
</table>
<ul>
<li><b>
NB
</b>[<i>read/write</i>]: Number of shots
<br>Number of shots required in multi-shot mode, set to one for single-shot mode
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
PRE_SAMPLES
</b>[<i>read/write</i>]: Pre-trigger samples
<br>Number of requested pre-trigger samples
</ul>
<a name="TRIG_POS"></a>
<h3><a name="sect_3_7">3.7. Trigger address register</a></h3>
<a name="POST_SAMPLES"></a>
<h3><a name="sect_3_10">3.10. Post-trigger samples</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_trig_pos
fmc_adc_core_post_samples
</td>
</tr>
<tr>
......@@ -3805,7 +4926,7 @@ fmc_adc_core_trig_pos
<b>HW address: </b>
</td>
<td class="td_code">
0x6
0x9
</td>
</tr>
<tr>
......@@ -3813,7 +4934,7 @@ fmc_adc_core_trig_pos
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_POS
POST_SAMPLES
</td>
</tr>
<tr>
......@@ -3821,7 +4942,7 @@ TRIG_POS
<b>C offset: </b>
</td>
<td class="td_code">
0x18
0x24
</td>
</tr>
</table>
......@@ -3854,7 +4975,7 @@ TRIG_POS
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_POS[31:24]
POST_SAMPLES[31:24]
</td>
<td >
......@@ -3908,7 +5029,7 @@ TRIG_POS[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_POS[23:16]
POST_SAMPLES[23:16]
</td>
<td >
......@@ -3962,7 +5083,7 @@ TRIG_POS[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_POS[15:8]
POST_SAMPLES[15:8]
</td>
<td >
......@@ -4016,7 +5137,7 @@ TRIG_POS[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_POS[7:0]
POST_SAMPLES[7:0]
</td>
<td >
......@@ -4043,19 +5164,19 @@ TRIG_POS[7:0]
</table>
<ul>
<li><b>
TRIG_POS
</b>[<i>read-only</i>]: Trigger address
<br>Trigger address in DDR memory.<br>Only used in single-shot mode
POST_SAMPLES
</b>[<i>read/write</i>]: Post-trigger samples
<br>Number of requested post-trigger samples
</ul>
<a name="GAIN_CAL"></a>
<h3><a name="sect_3_8">3.8. Gain calibration register</a></h3>
<a name="SAMPLES_CNT"></a>
<h3><a name="sect_3_11">3.11. Samples counter</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_gain_cal
fmc_adc_core_samples_cnt
</td>
</tr>
<tr>
......@@ -4063,7 +5184,7 @@ fmc_adc_core_gain_cal
<b>HW address: </b>
</td>
<td class="td_code">
0x7
0xa
</td>
</tr>
<tr>
......@@ -4071,7 +5192,7 @@ fmc_adc_core_gain_cal
<b>C prefix: </b>
</td>
<td class="td_code">
GAIN_CAL
SAMPLES_CNT
</td>
</tr>
<tr>
......@@ -4079,7 +5200,7 @@ GAIN_CAL
<b>C offset: </b>
</td>
<td class="td_code">
0x1c
0x28
</td>
</tr>
</table>
......@@ -4112,7 +5233,7 @@ GAIN_CAL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
GAIN_CAL[31:24]
SAMPLES_CNT[31:24]
</td>
<td >
......@@ -4166,7 +5287,7 @@ GAIN_CAL[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
GAIN_CAL[23:16]
SAMPLES_CNT[23:16]
</td>
<td >
......@@ -4220,7 +5341,7 @@ GAIN_CAL[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
GAIN_CAL[15:8]
SAMPLES_CNT[15:8]
</td>
<td >
......@@ -4274,7 +5395,7 @@ GAIN_CAL[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
GAIN_CAL[7:0]
SAMPLES_CNT[7:0]
</td>
<td >
......@@ -4301,19 +5422,19 @@ GAIN_CAL[7:0]
</table>
<ul>
<li><b>
GAIN_CAL
</b>[<i>read/write</i>]: Gain calibration
<br>Gain applied to all data coming from the ADC.
SAMPLES_CNT
</b>[<i>read-only</i>]: Samples counter
<br>Counts the number of samples.<br> It is reset on START and then counts the number of pre-trigger + post-trigger samples
</ul>
<a name="OFFSET_CAL"></a>
<h3><a name="sect_3_9">3.9. Offset calibration register</a></h3>
<a name="CH1_CTL"></a>
<h3><a name="sect_3_12">3.12. Channel 1 control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_offset_cal
fmc_adc_core_ch1_ctl
</td>
</tr>
<tr>
......@@ -4321,7 +5442,7 @@ fmc_adc_core_offset_cal
<b>HW address: </b>
</td>
<td class="td_code">
0x8
0xb
</td>
</tr>
<tr>
......@@ -4329,7 +5450,7 @@ fmc_adc_core_offset_cal
<b>C prefix: </b>
</td>
<td class="td_code">
OFFSET_CAL
CH1_CTL
</td>
</tr>
<tr>
......@@ -4337,7 +5458,7 @@ OFFSET_CAL
<b>C offset: </b>
</td>
<td class="td_code">
0x20
0x2c
</td>
</tr>
</table>
......@@ -4370,7 +5491,7 @@ OFFSET_CAL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
OFFSET_CAL[31:24]
RESERVED[24:17]
</td>
<td >
......@@ -4424,7 +5545,7 @@ OFFSET_CAL[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
OFFSET_CAL[23:16]
RESERVED[16:9]
</td>
<td >
......@@ -4478,7 +5599,7 @@ OFFSET_CAL[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
OFFSET_CAL[15:8]
RESERVED[8:1]
</td>
<td >
......@@ -4531,11 +5652,11 @@ OFFSET_CAL[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
OFFSET_CAL[7:0]
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
</td>
<td >
......@@ -4559,19 +5680,23 @@ OFFSET_CAL[7:0]
</table>
<ul>
<li><b>
OFFSET_CAL
</b>[<i>read/write</i>]: Offset calibration
<br>Offset applied to all data coming from the ADC.
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 1
<br>Controls input voltage range, termination and DC offset error calibration
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="RESERVED_0"></a>
<h3><a name="sect_3_10">3.10. Reserved register</a></h3>
<a name="CH1_STA"></a>
<h3><a name="sect_3_13">3.13. Channel 1 status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_reserved_0
fmc_adc_core_ch1_sta
</td>
</tr>
<tr>
......@@ -4579,7 +5704,7 @@ fmc_adc_core_reserved_0
<b>HW address: </b>
</td>
<td class="td_code">
0x9
0xc
</td>
</tr>
<tr>
......@@ -4587,7 +5712,7 @@ fmc_adc_core_reserved_0
<b>C prefix: </b>
</td>
<td class="td_code">
RESERVED_0
CH1_STA
</td>
</tr>
<tr>
......@@ -4595,7 +5720,7 @@ RESERVED_0
<b>C offset: </b>
</td>
<td class="td_code">
0x24
0x30
</td>
</tr>
</table>
......@@ -4628,7 +5753,7 @@ RESERVED_0
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_0[31:24]
RESERVED[15:8]
</td>
<td >
......@@ -4682,7 +5807,7 @@ RESERVED_0[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_0[23:16]
RESERVED[7:0]
</td>
<td >
......@@ -4736,7 +5861,7 @@ RESERVED_0[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_0[15:8]
VAL[15:8]
</td>
<td >
......@@ -4790,7 +5915,7 @@ RESERVED_0[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_0[7:0]
VAL[7:0]
</td>
<td >
......@@ -4817,19 +5942,23 @@ RESERVED_0[7:0]
</table>
<ul>
<li><b>
RESERVED_0
VAL
</b>[<i>read-only</i>]: Channel 1 current ADC value
<br>Current ADC raw value
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="RESERVED_1"></a>
<h3><a name="sect_3_11">3.11. Reserved register</a></h3>
<a name="CH1_GAIN"></a>
<h3><a name="sect_3_14">3.14. Channel 1 gain calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_reserved_1
fmc_adc_core_ch1_gain
</td>
</tr>
<tr>
......@@ -4837,7 +5966,7 @@ fmc_adc_core_reserved_1
<b>HW address: </b>
</td>
<td class="td_code">
0xa
0xd
</td>
</tr>
<tr>
......@@ -4845,7 +5974,7 @@ fmc_adc_core_reserved_1
<b>C prefix: </b>
</td>
<td class="td_code">
RESERVED_1
CH1_GAIN
</td>
</tr>
<tr>
......@@ -4853,7 +5982,7 @@ RESERVED_1
<b>C offset: </b>
</td>
<td class="td_code">
0x28
0x34
</td>
</tr>
</table>
......@@ -4886,7 +6015,7 @@ RESERVED_1
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_1[31:24]
RESERVED[15:8]
</td>
<td >
......@@ -4940,7 +6069,7 @@ RESERVED_1[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_1[23:16]
RESERVED[7:0]
</td>
<td >
......@@ -4994,7 +6123,7 @@ RESERVED_1[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_1[15:8]
VAL[15:8]
</td>
<td >
......@@ -5048,7 +6177,7 @@ RESERVED_1[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_1[7:0]
VAL[7:0]
</td>
<td >
......@@ -5075,19 +6204,23 @@ RESERVED_1[7:0]
</table>
<ul>
<li><b>
RESERVED_1
</b>[<i>read-only</i>]: Reserved
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 1
<br>Gain applied to all data coming from the ADC.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="RESERVED_2"></a>
<h3><a name="sect_3_12">3.12. Reserved register</a></h3>
<a name="CH1_OFFSET"></a>
<h3><a name="sect_3_15">3.15. Channel 1 offset calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_reserved_2
fmc_adc_core_ch1_offset
</td>
</tr>
<tr>
......@@ -5095,7 +6228,7 @@ fmc_adc_core_reserved_2
<b>HW address: </b>
</td>
<td class="td_code">
0xb
0xe
</td>
</tr>
<tr>
......@@ -5103,7 +6236,7 @@ fmc_adc_core_reserved_2
<b>C prefix: </b>
</td>
<td class="td_code">
RESERVED_2
CH1_OFFSET
</td>
</tr>
<tr>
......@@ -5111,7 +6244,7 @@ RESERVED_2
<b>C offset: </b>
</td>
<td class="td_code">
0x2c
0x38
</td>
</tr>
</table>
......@@ -5144,7 +6277,7 @@ RESERVED_2
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_2[31:24]
RESERVED[14:7]
</td>
<td >
......@@ -5197,11 +6330,11 @@ RESERVED_2[31:24]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_2[23:16]
<td style="border: solid 1px black;" colspan=7 class="td_field">
RESERVED[6:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=1 class="td_field">
VAL[16:16]
</td>
<td >
......@@ -5252,7 +6385,7 @@ RESERVED_2[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_2[15:8]
VAL[15:8]
</td>
<td >
......@@ -5306,7 +6439,7 @@ RESERVED_2[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_2[7:0]
VAL[7:0]
</td>
<td >
......@@ -5333,19 +6466,23 @@ RESERVED_2[7:0]
</table>
<ul>
<li><b>
RESERVED_2
</b>[<i>read-only</i>]: Reserved
VAL
</b>[<i>read/write</i>]: Offset calibration for channel 1
<br>Offset applied to all data coming from the ADC.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="SR"></a>
<h3><a name="sect_3_13">3.13. Sample rate</a></h3>
<a name="CH2_CTL"></a>
<h3><a name="sect_3_16">3.16. Channel 2 control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_sr
fmc_adc_core_ch2_ctl
</td>
</tr>
<tr>
......@@ -5353,7 +6490,7 @@ fmc_adc_core_sr
<b>HW address: </b>
</td>
<td class="td_code">
0xc
0xf
</td>
</tr>
<tr>
......@@ -5361,7 +6498,7 @@ fmc_adc_core_sr
<b>C prefix: </b>
</td>
<td class="td_code">
SR
CH2_CTL
</td>
</tr>
<tr>
......@@ -5369,7 +6506,7 @@ SR
<b>C offset: </b>
</td>
<td class="td_code">
0x30
0x3c
</td>
</tr>
</table>
......@@ -5402,7 +6539,7 @@ SR
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
RESERVED[24:17]
</td>
<td >
......@@ -5456,7 +6593,7 @@ RESERVED[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
RESERVED[16:9]
</td>
<td >
......@@ -5510,7 +6647,7 @@ RESERVED[7:0]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DECI[15:8]
RESERVED[8:1]
</td>
<td >
......@@ -5563,11 +6700,11 @@ DECI[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DECI[7:0]
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
</td>
<td >
......@@ -5591,23 +6728,23 @@ DECI[7:0]
</table>
<ul>
<li><b>
DECI
</b>[<i>read/write</i>]: Sample rate decimation
<br>Decimation factor
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 2
<br>Controls input voltage range, termination and DC offset error calibration
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="PRE_SAMPLES"></a>
<h3><a name="sect_3_14">3.14. Pre-trigger samples</a></h3>
<a name="CH2_STA"></a>
<h3><a name="sect_3_17">3.17. Channel 2 status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_pre_samples
fmc_adc_core_ch2_sta
</td>
</tr>
<tr>
......@@ -5615,7 +6752,7 @@ fmc_adc_core_pre_samples
<b>HW address: </b>
</td>
<td class="td_code">
0xd
0x10
</td>
</tr>
<tr>
......@@ -5623,7 +6760,7 @@ fmc_adc_core_pre_samples
<b>C prefix: </b>
</td>
<td class="td_code">
PRE_SAMPLES
CH2_STA
</td>
</tr>
<tr>
......@@ -5631,7 +6768,7 @@ PRE_SAMPLES
<b>C offset: </b>
</td>
<td class="td_code">
0x34
0x40
</td>
</tr>
</table>
......@@ -5664,7 +6801,7 @@ PRE_SAMPLES
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
PRE_SAMPLES[31:24]
RESERVED[15:8]
</td>
<td >
......@@ -5718,7 +6855,7 @@ PRE_SAMPLES[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
PRE_SAMPLES[23:16]
RESERVED[7:0]
</td>
<td >
......@@ -5772,7 +6909,7 @@ PRE_SAMPLES[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
PRE_SAMPLES[15:8]
VAL[15:8]
</td>
<td >
......@@ -5826,7 +6963,7 @@ PRE_SAMPLES[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
PRE_SAMPLES[7:0]
VAL[7:0]
</td>
<td >
......@@ -5853,19 +6990,23 @@ PRE_SAMPLES[7:0]
</table>
<ul>
<li><b>
PRE_SAMPLES
</b>[<i>read/write</i>]: Pre-trigger samples
<br>Number of requested pre-trigger samples
VAL
</b>[<i>read-only</i>]: Channel 2 current ACD value
<br>Current ADC raw value
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="POST_SAMPLES"></a>
<h3><a name="sect_3_15">3.15. Post-trigger samples</a></h3>
<a name="CH2_GAIN"></a>
<h3><a name="sect_3_18">3.18. Channel 2 gain calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_post_samples
fmc_adc_core_ch2_gain
</td>
</tr>
<tr>
......@@ -5873,7 +7014,7 @@ fmc_adc_core_post_samples
<b>HW address: </b>
</td>
<td class="td_code">
0xe
0x11
</td>
</tr>
<tr>
......@@ -5881,7 +7022,7 @@ fmc_adc_core_post_samples
<b>C prefix: </b>
</td>
<td class="td_code">
POST_SAMPLES
CH2_GAIN
</td>
</tr>
<tr>
......@@ -5889,7 +7030,7 @@ POST_SAMPLES
<b>C offset: </b>
</td>
<td class="td_code">
0x38
0x44
</td>
</tr>
</table>
......@@ -5922,7 +7063,7 @@ POST_SAMPLES
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
POST_SAMPLES[31:24]
RESERVED[15:8]
</td>
<td >
......@@ -5976,7 +7117,7 @@ POST_SAMPLES[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
POST_SAMPLES[23:16]
RESERVED[7:0]
</td>
<td >
......@@ -6030,7 +7171,7 @@ POST_SAMPLES[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
POST_SAMPLES[15:8]
VAL[15:8]
</td>
<td >
......@@ -6084,7 +7225,7 @@ POST_SAMPLES[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
POST_SAMPLES[7:0]
VAL[7:0]
</td>
<td >
......@@ -6111,19 +7252,23 @@ POST_SAMPLES[7:0]
</table>
<ul>
<li><b>
POST_SAMPLES
</b>[<i>read/write</i>]: Post-trigger samples
<br>Number of requested post-trigger samples
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 2
<br>Gain applied to all data coming from the ADC.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="SAMP_CNT"></a>
<h3><a name="sect_3_16">3.16. Sample counter</a></h3>
<a name="CH2_OFFSET"></a>
<h3><a name="sect_3_19">3.19. Channel 2 offset calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_samp_cnt
fmc_adc_core_ch2_offset
</td>
</tr>
<tr>
......@@ -6131,7 +7276,7 @@ fmc_adc_core_samp_cnt
<b>HW address: </b>
</td>
<td class="td_code">
0xf
0x12
</td>
</tr>
<tr>
......@@ -6139,7 +7284,7 @@ fmc_adc_core_samp_cnt
<b>C prefix: </b>
</td>
<td class="td_code">
SAMP_CNT
CH2_OFFSET
</td>
</tr>
<tr>
......@@ -6147,7 +7292,7 @@ SAMP_CNT
<b>C offset: </b>
</td>
<td class="td_code">
0x3c
0x48
</td>
</tr>
</table>
......@@ -6180,7 +7325,7 @@ SAMP_CNT
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SAMP_CNT[31:24]
RESERVED[14:7]
</td>
<td >
......@@ -6233,11 +7378,11 @@ SAMP_CNT[31:24]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SAMP_CNT[23:16]
<td style="border: solid 1px black;" colspan=7 class="td_field">
RESERVED[6:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=1 class="td_field">
VAL[16:16]
</td>
<td >
......@@ -6288,7 +7433,7 @@ SAMP_CNT[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SAMP_CNT[15:8]
VAL[15:8]
</td>
<td >
......@@ -6342,7 +7487,7 @@ SAMP_CNT[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SAMP_CNT[7:0]
VAL[7:0]
</td>
<td >
......@@ -6369,19 +7514,23 @@ SAMP_CNT[7:0]
</table>
<ul>
<li><b>
SAMP_CNT
</b>[<i>read-only</i>]: Sample counter
<br>Counts the number of sample.<br> It is reset on START and then counts the number of pre-trigger + post-trigger samples
VAL
</b>[<i>read/write</i>]: Offset calibration for channel 2
<br>Offset applied to all data coming from the ADC.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH1"></a>
<h3><a name="sect_3_17">3.17. Solid state relays control for channel 1</a></h3>
<a name="CH3_CTL"></a>
<h3><a name="sect_3_20">3.20. Channel 3 control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch1
fmc_adc_core_ch3_ctl
</td>
</tr>
<tr>
......@@ -6389,7 +7538,7 @@ fmc_adc_core_ch1
<b>HW address: </b>
</td>
<td class="td_code">
0x10
0x13
</td>
</tr>
<tr>
......@@ -6397,7 +7546,7 @@ fmc_adc_core_ch1
<b>C prefix: </b>
</td>
<td class="td_code">
CH1
CH3_CTL
</td>
</tr>
<tr>
......@@ -6405,7 +7554,7 @@ CH1
<b>C offset: </b>
</td>
<td class="td_code">
0x40
0x4c
</td>
</tr>
</table>
......@@ -6628,22 +7777,22 @@ SSR[6:0]
<ul>
<li><b>
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 1
</b>[<i>read/write</i>]: Solid state relays control for channel 3
<br>Controls input voltage range, termination and DC offset error calibration
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH1"></a>
<h3><a name="sect_3_18">3.18. Channel 1 current value</a></h3>
<a name="CH3_STA"></a>
<h3><a name="sect_3_21">3.21. Channel 3 status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch1
fmc_adc_core_ch3_sta
</td>
</tr>
<tr>
......@@ -6651,7 +7800,7 @@ fmc_adc_core_ch1
<b>HW address: </b>
</td>
<td class="td_code">
0x11
0x14
</td>
</tr>
<tr>
......@@ -6659,7 +7808,7 @@ fmc_adc_core_ch1
<b>C prefix: </b>
</td>
<td class="td_code">
CH1
CH3_STA
</td>
</tr>
<tr>
......@@ -6667,7 +7816,7 @@ CH1
<b>C offset: </b>
</td>
<td class="td_code">
0x44
0x50
</td>
</tr>
</table>
......@@ -6890,22 +8039,22 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read-only</i>]: Channel 1 current value
</b>[<i>read-only</i>]: Channel 3 current ADC value
<br>Current ADC raw value
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH2"></a>
<h3><a name="sect_3_19">3.19. Solid state relays control for channel 2</a></h3>
<a name="CH3_GAIN"></a>
<h3><a name="sect_3_22">3.22. Channel 3 gain calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch2
fmc_adc_core_ch3_gain
</td>
</tr>
<tr>
......@@ -6913,7 +8062,7 @@ fmc_adc_core_ch2
<b>HW address: </b>
</td>
<td class="td_code">
0x12
0x15
</td>
</tr>
<tr>
......@@ -6921,7 +8070,7 @@ fmc_adc_core_ch2
<b>C prefix: </b>
</td>
<td class="td_code">
CH2
CH3_GAIN
</td>
</tr>
<tr>
......@@ -6929,7 +8078,7 @@ CH2
<b>C offset: </b>
</td>
<td class="td_code">
0x48
0x54
</td>
</tr>
</table>
......@@ -6962,7 +8111,7 @@ CH2
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[24:17]
RESERVED[15:8]
</td>
<td >
......@@ -7016,7 +8165,7 @@ RESERVED[24:17]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
RESERVED[7:0]
</td>
<td >
......@@ -7070,7 +8219,7 @@ RESERVED[16:9]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
VAL[15:8]
</td>
<td >
......@@ -7123,11 +8272,11 @@ RESERVED[8:1]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[7:0]
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
<td >
</td>
<td >
......@@ -7151,23 +8300,23 @@ SSR[6:0]
</table>
<ul>
<li><b>
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 2
<br>Controls input voltage range, termination and DC offset error calibration
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 3
<br>Gain applied to all data coming from the ADC.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH2"></a>
<h3><a name="sect_3_20">3.20. Channel 2 current value</a></h3>
<a name="CH3_OFFSET"></a>
<h3><a name="sect_3_23">3.23. Channel 3 offset calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch2
fmc_adc_core_ch3_offset
</td>
</tr>
<tr>
......@@ -7175,7 +8324,7 @@ fmc_adc_core_ch2
<b>HW address: </b>
</td>
<td class="td_code">
0x13
0x16
</td>
</tr>
<tr>
......@@ -7183,7 +8332,7 @@ fmc_adc_core_ch2
<b>C prefix: </b>
</td>
<td class="td_code">
CH2
CH3_OFFSET
</td>
</tr>
<tr>
......@@ -7191,7 +8340,7 @@ CH2
<b>C offset: </b>
</td>
<td class="td_code">
0x4c
0x58
</td>
</tr>
</table>
......@@ -7224,7 +8373,7 @@ CH2
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
RESERVED[14:7]
</td>
<td >
......@@ -7277,11 +8426,11 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td style="border: solid 1px black;" colspan=7 class="td_field">
RESERVED[6:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=1 class="td_field">
VAL[16:16]
</td>
<td >
......@@ -7414,22 +8563,22 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read-only</i>]: Channel 2 current value
<br>Current ADC raw value
</b>[<i>read/write</i>]: Offset calibration for channel 3
<br>Offset applied to all data coming from the ADC.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH3"></a>
<h3><a name="sect_3_21">3.21. Solid state relays control for channel 3</a></h3>
<a name="CH4_CTL"></a>
<h3><a name="sect_3_24">3.24. Channel 4 control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch3
fmc_adc_core_ch4_ctl
</td>
</tr>
<tr>
......@@ -7437,7 +8586,7 @@ fmc_adc_core_ch3
<b>HW address: </b>
</td>
<td class="td_code">
0x14
0x17
</td>
</tr>
<tr>
......@@ -7445,7 +8594,7 @@ fmc_adc_core_ch3
<b>C prefix: </b>
</td>
<td class="td_code">
CH3
CH4_CTL
</td>
</tr>
<tr>
......@@ -7453,7 +8602,7 @@ CH3
<b>C offset: </b>
</td>
<td class="td_code">
0x50
0x5c
</td>
</tr>
</table>
......@@ -7676,22 +8825,22 @@ SSR[6:0]
<ul>
<li><b>
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 3
</b>[<i>read/write</i>]: Solid state relays control for channel 4
<br>Controls input voltage range, termination and DC offset error calibration
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH3"></a>
<h3><a name="sect_3_22">3.22. Channel 3 current value</a></h3>
<a name="CH4_STA"></a>
<h3><a name="sect_3_25">3.25. Channel 4 status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch3
fmc_adc_core_ch4_sta
</td>
</tr>
<tr>
......@@ -7699,7 +8848,7 @@ fmc_adc_core_ch3
<b>HW address: </b>
</td>
<td class="td_code">
0x15
0x18
</td>
</tr>
<tr>
......@@ -7707,7 +8856,7 @@ fmc_adc_core_ch3
<b>C prefix: </b>
</td>
<td class="td_code">
CH3
CH4_STA
</td>
</tr>
<tr>
......@@ -7715,7 +8864,7 @@ CH3
<b>C offset: </b>
</td>
<td class="td_code">
0x54
0x60
</td>
</tr>
</table>
......@@ -7938,22 +9087,22 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read-only</i>]: Channel 3 current value
</b>[<i>read-only</i>]: Channel 4 current ADC value
<br>Current ADC raw value
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH4"></a>
<h3><a name="sect_3_23">3.23. Solid state relays control for channel 4</a></h3>
<a name="CH4_GAIN"></a>
<h3><a name="sect_3_26">3.26. Channel 4 gain calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch4
fmc_adc_core_ch4_gain
</td>
</tr>
<tr>
......@@ -7961,7 +9110,7 @@ fmc_adc_core_ch4
<b>HW address: </b>
</td>
<td class="td_code">
0x16
0x19
</td>
</tr>
<tr>
......@@ -7969,7 +9118,7 @@ fmc_adc_core_ch4
<b>C prefix: </b>
</td>
<td class="td_code">
CH4
CH4_GAIN
</td>
</tr>
<tr>
......@@ -7977,7 +9126,7 @@ CH4
<b>C offset: </b>
</td>
<td class="td_code">
0x58
0x64
</td>
</tr>
</table>
......@@ -8010,7 +9159,7 @@ CH4
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[24:17]
RESERVED[15:8]
</td>
<td >
......@@ -8064,7 +9213,7 @@ RESERVED[24:17]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[16:9]
RESERVED[7:0]
</td>
<td >
......@@ -8118,7 +9267,7 @@ RESERVED[16:9]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[8:1]
VAL[15:8]
</td>
<td >
......@@ -8171,11 +9320,11 @@ RESERVED[8:1]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED[0:0]
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[7:0]
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
<td >
</td>
<td >
......@@ -8199,23 +9348,23 @@ SSR[6:0]
</table>
<ul>
<li><b>
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 4
<br>Controls input voltage range, termination and DC offset error calibration
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 4
<br>Gain applied to all data coming from the ADC.
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
<a name="CH4"></a>
<h3><a name="sect_3_24">3.24. Channel 4 current value</a></h3>
<a name="CH4_OFFSET"></a>
<h3><a name="sect_3_27">3.27. Channel 4 offset calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_core_ch4
fmc_adc_core_ch4_offset
</td>
</tr>
<tr>
......@@ -8223,7 +9372,7 @@ fmc_adc_core_ch4
<b>HW address: </b>
</td>
<td class="td_code">
0x17
0x1a
</td>
</tr>
<tr>
......@@ -8231,7 +9380,7 @@ fmc_adc_core_ch4
<b>C prefix: </b>
</td>
<td class="td_code">
CH4
CH4_OFFSET
</td>
</tr>
<tr>
......@@ -8239,7 +9388,7 @@ CH4
<b>C offset: </b>
</td>
<td class="td_code">
0x5c
0x68
</td>
</tr>
</table>
......@@ -8272,7 +9421,7 @@ CH4
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
RESERVED[14:7]
</td>
<td >
......@@ -8325,11 +9474,11 @@ RESERVED[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
<td style="border: solid 1px black;" colspan=7 class="td_field">
RESERVED[6:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=1 class="td_field">
VAL[16:16]
</td>
<td >
......@@ -8462,11 +9611,11 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read-only</i>]: Channel 4 current value
<br>Current ADC raw value
</b>[<i>read/write</i>]: Offset calibration for channel 4
<br>Offset applied to all data coming from the ADC.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
......
......@@ -137,9 +137,9 @@ peripheral {
};
field {
name = "External hardware trigger polarity";
description = "0: positive edge\n1: negative edge";
prefix = "ext_trig_pol";
name = "Hardware trigger polarity";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "hw_trig_pol";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -189,7 +189,7 @@ peripheral {
field {
name = "Threshold for internal trigger";
description = "Treated as two's complement and compared to raw ADC data";
description = "Treated as offset binary and compared to raw ADC data";
prefix = "int_trig_thres";
type = SLV;
size = 16;
......@@ -266,26 +266,38 @@ peripheral {
};
reg {
name = "Gain calibration register";
prefix = "gain_cal";
name = "Sample rate";
prefix = "sr";
field {
name = "Gain calibration";
description = "Gain applied to all data coming from the ADC.";
name = "Sample rate decimation";
description = "Decimation factor";
prefix = "deci";
type = SLV;
size = 32;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Offset calibration register";
prefix = "offset_cal";
name = "Pre-trigger samples";
prefix = "pre_samples";
field {
name = "Offset calibration";
description = "Offset applied to all data coming from the ADC.";
name = "Pre-trigger samples";
description = "Number of requested pre-trigger samples";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -294,26 +306,26 @@ peripheral {
};
reg {
name = "Reserved register";
prefix = "reserved_0";
name = "Post-trigger samples";
prefix = "post_samples";
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
name = "Post-trigger samples";
description = "Number of requested post-trigger samples";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reserved register";
prefix = "reserved_1";
name = "Samples counter";
prefix = "samples_cnt";
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
name = "Samples counter";
description = "Counts the number of samples.\n It is reset on START and then counts the number of pre-trigger + post-trigger samples";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -322,31 +334,42 @@ peripheral {
};
reg {
name = "Reserved register";
prefix = "reserved_2";
name = "Channel 1 control register";
prefix = "ch1_ctl";
field {
name = "Solid state relays control for channel 1";
description = "Controls input voltage range, termination and DC offset error calibration";
prefix = "ssr";
type = SLV;
size = 7;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
size = 25;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Sample rate";
prefix = "sr";
name = "Channel 1 status register";
prefix = "ch1_sta";
field {
name = "Sample rate decimation";
description = "Decimation factor";
prefix = "deci";
name = "Channel 1 current ADC value";
description = "Current ADC raw value";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
......@@ -356,59 +379,67 @@ peripheral {
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Pre-trigger samples";
prefix = "pre_samples";
name = "Channel 1 gain calibration register";
prefix = "ch1_gain";
field {
name = "Pre-trigger samples";
description = "Number of requested pre-trigger samples";
name = "Gain calibration for channel 1";
description = "Gain applied to all data coming from the ADC.";
prefix = "val";
type = SLV;
size = 32;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Post-trigger samples";
prefix = "post_samples";
field {
name = "Post-trigger samples";
description = "Number of requested post-trigger samples";
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 32;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Sample counter";
prefix = "samp_cnt";
name = "Channel 1 offset calibration register";
prefix = "ch1_offset";
field {
name = "Sample counter";
description = "Counts the number of sample.\n It is reset on START and then counts the number of pre-trigger + post-trigger samples";
name = "Offset calibration for channel 1";
description = "Offset applied to all data coming from the ADC.";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Solid state relays control for channel 1";
prefix = "ch1";
name = "Channel 2 control register";
prefix = "ch2_ctl";
field {
name = "Solid state relays control for channel 1";
name = "Solid state relays control for channel 2";
description = "Controls input voltage range, termination and DC offset error calibration";
prefix = "ssr";
type = SLV;
......@@ -429,11 +460,11 @@ peripheral {
};
reg {
name = "Channel 1 current value";
prefix = "ch1";
name = "Channel 2 status register";
prefix = "ch2_sta";
field {
name = "Channel 1 current value";
name = "Channel 2 current ACD value";
description = "Current ADC raw value";
prefix = "val";
type = SLV;
......@@ -455,15 +486,15 @@ peripheral {
};
reg {
name = "Solid state relays control for channel 2";
prefix = "ch2";
name = "Channel 2 gain calibration register";
prefix = "ch2_gain";
field {
name = "Solid state relays control for channel 2";
description = "Controls input voltage range, termination and DC offset error calibration";
prefix = "ssr";
name = "Gain calibration for channel 2";
description = "Gain applied to all data coming from the ADC.";
prefix = "val";
type = SLV;
size = 7;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -473,25 +504,24 @@ peripheral {
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 25;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 2 current value";
prefix = "ch2";
name = "Channel 2 offset calibration register";
prefix = "ch2_offset";
field {
name = "Channel 2 current value";
description = "Current ADC raw value";
name = "Offset calibration for channel 2";
description = "Offset applied to all data coming from the ADC.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
......@@ -499,15 +529,15 @@ peripheral {
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Solid state relays control for channel 3";
prefix = "ch3";
name = "Channel 3 control register";
prefix = "ch3_ctl";
field {
name = "Solid state relays control for channel 3";
......@@ -531,11 +561,11 @@ peripheral {
};
reg {
name = "Channel 3 current value";
prefix = "ch3";
name = "Channel 3 status register";
prefix = "ch3_sta";
field {
name = "Channel 3 current value";
name = "Channel 3 current ADC value";
description = "Current ADC raw value";
prefix = "val";
type = SLV;
......@@ -557,8 +587,58 @@ peripheral {
};
reg {
name = "Solid state relays control for channel 4";
prefix = "ch4";
name = "Channel 3 gain calibration register";
prefix = "ch3_gain";
field {
name = "Gain calibration for channel 3";
description = "Gain applied to all data coming from the ADC.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 3 offset calibration register";
prefix = "ch3_offset";
field {
name = "Offset calibration for channel 3";
description = "Offset applied to all data coming from the ADC.";
prefix = "val";
type = SLV;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 4 control register";
prefix = "ch4_ctl";
field {
name = "Solid state relays control for channel 4";
......@@ -582,11 +662,11 @@ peripheral {
};
reg {
name = "Channel 4 current value";
prefix = "ch4";
name = "Channel 4 status register";
prefix = "ch4_sta";
field {
name = "Channel 4 current value";
name = "Channel 4 current ADC value";
description = "Current ADC raw value";
prefix = "val";
type = SLV;
......@@ -607,4 +687,54 @@ peripheral {
};
};
reg {
name = "Channel 4 gain calibration register";
prefix = "ch4_gain";
field {
name = "Gain calibration for channel 4";
description = "Gain applied to all data coming from the ADC.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 4 offset calibration register";
prefix = "ch4_offset";
field {
name = "Offset calibration for channel 4";
description = "Offset applied to all data coming from the ADC.";
prefix = "val";
type = SLV;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
......@@ -748,285 +748,288 @@
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
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</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
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<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
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<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
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<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
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<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
</files>
<bindings/>
......
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