Commit 0d587a34 authored by mcattin's avatar mcattin

Change internal hw trigger to two's complement comparison. Update threshold…

Change internal hw trigger to two's complement comparison. Update threshold register comment for wbgen.

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@114 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent 492231fe
......@@ -775,7 +775,7 @@ begin
int_trig_over_thres_d <= '0';
serdes_out_data_d <= (others => '0');
elsif rising_edge(fs_clk) then
if int_trig_data > int_trig_thres then
if signed(int_trig_data) > signed(int_trig_thres) then
int_trig_over_thres <= '1';
else
int_trig_over_thres <= '0';
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Fri Dec 16 08:44:17 2011
-- Created : Thu Jan 26 10:14:03 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -408,17 +408,24 @@ begin
when "00000" =>
if (wb_we_i = '1') then
fmc_adc_core_ctl_fsm_cmd_wr_o <= '1';
rddata_reg(2) <= 'X';
fmc_adc_core_ctl_fmc_clk_oe_int <= wrdata_reg(2);
rddata_reg(3) <= 'X';
fmc_adc_core_ctl_offset_dac_clr_n_int <= wrdata_reg(3);
rddata_reg(4) <= 'X';
fmc_adc_core_ctl_man_bitslip_int <= wrdata_reg(4);
fmc_adc_core_ctl_man_bitslip_int_delay <= wrdata_reg(4);
rddata_reg(5) <= 'X';
fmc_adc_core_ctl_test_data_en_int <= wrdata_reg(5);
rddata_reg(6) <= 'X';
fmc_adc_core_ctl_trig_led_int <= wrdata_reg(6);
rddata_reg(7) <= 'X';
fmc_adc_core_ctl_acq_led_int <= wrdata_reg(7);
fmc_adc_core_ctl_reserved_int <= wrdata_reg(31 downto 8);
else
rddata_reg(2) <= fmc_adc_core_ctl_fmc_clk_oe_int;
rddata_reg(3) <= fmc_adc_core_ctl_offset_dac_clr_n_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= fmc_adc_core_ctl_test_data_en_int;
rddata_reg(6) <= fmc_adc_core_ctl_trig_led_int;
rddata_reg(7) <= fmc_adc_core_ctl_acq_led_int;
......@@ -430,6 +437,8 @@ begin
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
else
rddata_reg(2 downto 0) <= fmc_adc_core_sta_fsm_i;
rddata_reg(3) <= fmc_adc_core_sta_serdes_pll_i;
......@@ -441,9 +450,13 @@ begin
when "00010" =>
if (wb_we_i = '1') then
fmc_adc_core_trig_cfg_hw_trig_sel_int <= wrdata_reg(0);
rddata_reg(0) <= 'X';
fmc_adc_core_trig_cfg_hw_trig_pol_int <= wrdata_reg(1);
rddata_reg(1) <= 'X';
fmc_adc_core_trig_cfg_hw_trig_en_int <= wrdata_reg(2);
rddata_reg(2) <= 'X';
fmc_adc_core_trig_cfg_sw_trig_en_int <= wrdata_reg(3);
rddata_reg(3) <= 'X';
fmc_adc_core_trig_cfg_int_trig_sel_int <= wrdata_reg(5 downto 4);
fmc_adc_core_trig_cfg_int_trig_sel_swb <= '1';
fmc_adc_core_trig_cfg_int_trig_sel_swb_delay <= '1';
......
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Fri Dec 16 08:44:17 2011
* Created : Thu Jan 26 10:14:03 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......
......@@ -715,10 +715,10 @@ fmc_adc_core_ctl_reserved_o[23:0]
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
fs_clk_i
</td>
<td class="td_sym_center">
&nbsp;
......@@ -3350,7 +3350,7 @@ RESERVED
<li><b>
INT_TRIG_THRES
</b>[<i>read/write</i>]: Threshold for internal trigger
<br>Treated as offset binary and compared to raw ADC data
<br>Treated as two's complement and compared to raw ADC data
</ul>
<a name="TRIG_DLY"></a>
<h3><a name="sect_3_4">3.4. Trigger delay</a></h3>
......
......@@ -189,7 +189,7 @@ peripheral {
field {
name = "Threshold for internal trigger";
description = "Treated as offset binary and compared to raw ADC data";
description = "Treated as two's complement and compared to raw ADC data";
prefix = "int_trig_thres";
type = SLV;
size = 16;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment