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FMC ADC 100M 14b 4cha - Gateware
Commit 0a4be7f6 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] use gc_posedge for ddr_fifo_empty flag 

Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
parent d0407fc2
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Showing with 6 additions and 9 deletions
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ 0a4be7f6
......@@ -172,7 +172,6 @@ architecture rtl of fmc_adc_mezzanine is
signal si570_sda_oe_n : std_logic;
-- Interrupts (eic)
signal ddr_wr_fifo_empty_d : std_logic;
signal ddr_wr_fifo_empty_p : std_logic;
signal acq_end_irq_p : std_logic;
signal acq_end_extend : std_logic;
......@@ -418,14 +417,12 @@ begin
int_o => eic_irq_o);
-- Detects end of adc core writing to ddr
p_ddr_wr_fifo_empty : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
ddr_wr_fifo_empty_d <= ddr_wr_fifo_empty_i;
end if;
end process p_ddr_wr_fifo_empty;
ddr_wr_fifo_empty_p <= ddr_wr_fifo_empty_i and not(ddr_wr_fifo_empty_d);
cmp_ddr_wr_fifo_empty_posedge : entity work.gc_posedge
port map (
clk_i => sys_clk_i,
rst_n_i => '1',
data_i => ddr_wr_fifo_empty_i,
pulse_o => ddr_wr_fifo_empty_p);
-- End of acquisition interrupt generation
p_acq_end_extend : process (sys_clk_i)
......
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