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FMC ADC 100M 14b 4cha - Gateware
Commit 0580effb authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl, doc, sim: Fix sdb bridge offset address, add config ok flag, update doc in progress.

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documentation/figures/adc_core_sys_clk.svg
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documentation/manuals/firmware/fmc_adc_100Ms_csr.tex
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...@@ -180,7 +180,12 @@ SerDes PLL status ...@@ -180,7 +180,12 @@ SerDes PLL status
@code{SERDES_SYNCED} @code{SERDES_SYNCED}
@tab @code{X} @tab @tab @code{X} @tab
SerDes synchronization status SerDes synchronization status
@item @code{31...5} @item @code{5}
@tab R/O @tab
@code{ACQ_CFG}
@tab @code{X} @tab
Acquisition configuration status
@item @code{31...6}
@tab R/O @tab @tab R/O @tab
@code{RESERVED} @code{RESERVED}
@tab @code{X} @tab @tab @code{X} @tab
...@@ -188,9 +193,10 @@ Reserved ...@@ -188,9 +193,10 @@ Reserved
@end multitable @end multitable
@multitable @columnfractions 0.15 0.85 @multitable @columnfractions 0.15 0.85
@headitem Field @tab Description @headitem Field @tab Description
@item @code{fsm} @tab States:@*0: illegal@*1: IDLE@*2: PRE_TRIG@*3: WAIT_TRIG@*4: POST_TRIG@*5: DECR_SHOT@*6: illegal@*7: illegal @item @code{fsm} @tab States:@*0: illegal@*1: IDLE@*2: PRE_TRIG@*3: WAIT_TRIG@*4: POST_TRIG@*5: TRIG_TAG@*6: DECR_SHOT@*7: illegal
@item @code{serdes_pll} @tab Sampling clock recovery PLL.@*0: not locked@*1: locked @item @code{serdes_pll} @tab Sampling clock recovery PLL.@*0: not locked@*1: locked
@item @code{serdes_synced} @tab 0: bitslip in progress@*1: serdes synchronized @item @code{serdes_synced} @tab 0: bitslip in progress@*1: serdes synchronized
@item @code{acq_cfg} @tab 0: Unauthorised acquisition configuration (will prevent acquisition to start)@*1: Valid acquisition configuration@*@bullet{} Shot number > 0@*@bullet{} Post-trigger sample > 0
@item @code{reserved} @tab Ignore on read, write with 0's @item @code{reserved} @tab Ignore on read, write with 0's
@end multitable @end multitable
@regsection @code{trig_cfg} - Trigger configuration @regsection @code{trig_cfg} - Trigger configuration
...@@ -240,7 +246,7 @@ Threshold for internal trigger ...@@ -240,7 +246,7 @@ Threshold for internal trigger
@item @code{sw_trig_en} @tab 0: disable@*1: enable @item @code{sw_trig_en} @tab 0: disable@*1: enable
@item @code{int_trig_sel} @tab 00: channel 1@*01: channel 2@*10: channel 3@*11: channel 4 @item @code{int_trig_sel} @tab 00: channel 1@*01: channel 2@*10: channel 3@*11: channel 4
@item @code{reserved} @tab Ignore on read, write with 0's @item @code{reserved} @tab Ignore on read, write with 0's
@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data @item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data.
@end multitable @end multitable
@regsection @code{trig_dly} - Trigger delay @regsection @code{trig_dly} - Trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55 @multitable @columnfractions .10 .10 .15 .10 .55
...@@ -321,7 +327,7 @@ Pre-trigger samples ...@@ -321,7 +327,7 @@ Pre-trigger samples
@end multitable @end multitable
@multitable @columnfractions 0.15 0.85 @multitable @columnfractions 0.15 0.85
@headitem Field @tab Description @headitem Field @tab Description
@item @code{pre_samples} @tab Number of requested pre-trigger samples @item @code{pre_samples} @tab Number of requested pre-trigger samples (>1).
@end multitable @end multitable
@regsection @code{post_samples} - Post-trigger samples @regsection @code{post_samples} - Post-trigger samples
@multitable @columnfractions .10 .10 .15 .10 .55 @multitable @columnfractions .10 .10 .15 .10 .55
...@@ -334,7 +340,7 @@ Post-trigger samples ...@@ -334,7 +340,7 @@ Post-trigger samples
@end multitable @end multitable
@multitable @columnfractions 0.15 0.85 @multitable @columnfractions 0.15 0.85
@headitem Field @tab Description @headitem Field @tab Description
@item @code{post_samples} @tab Number of requested post-trigger samples @item @code{post_samples} @tab Number of requested post-trigger samples (>1).
@end multitable @end multitable
@regsection @code{samples_cnt} - Samples counter @regsection @code{samples_cnt} - Samples counter
@multitable @columnfractions .10 .10 .15 .10 .55 @multitable @columnfractions .10 .10 .15 .10 .55
......
documentation/manuals/firmware/fmcadc100m14b4cha_firmware_manual.in
View file @ 0580effb
...@@ -420,6 +420,10 @@ Those two counters are accessible in read/write mode via registers. ...@@ -420,6 +420,10 @@ Those two counters are accessible in read/write mode via registers.
To time-tag the events, the ADC core sends pulses to the time-tagging core. To time-tag the events, the ADC core sends pulses to the time-tagging core.
The following events are time-tagged; trigger, acquisition start, acquisition stop and acquisition end. The following events are time-tagged; trigger, acquisition start, acquisition stop and acquisition end.
@quotation Note
The trigger time tag corresponds to the moment when the acquisition FSM leaves the @code{WAIT_TRIG} state.
@end quotation
@quotation Note @quotation Note
In this release, the meta-data register is NOT used, set to zero. In this release, the meta-data register is NOT used, set to zero.
@end quotation @end quotation
...@@ -876,7 +880,11 @@ The LED labeled @code{ACQ} is turned ON when the acquisition state machine is @b ...@@ -876,7 +880,11 @@ The LED labeled @code{ACQ} is turned ON when the acquisition state machine is @b
The LED labeled @code{TRIG} flashes when a valid trigger is detected @b{and} the acquisition state machine is in the @code{WAIT_TRIG} state. The LED labeled @code{TRIG} flashes when a valid trigger is detected @b{and} the acquisition state machine is in the @code{WAIT_TRIG} state.
@quotation Note @quotation Note
In addition to the requested pre/post-trigger samples, an addition sample, corresponding to the trigger, will be recoded. The number of pre-trigger sample can be zero, but there @b{must} be at least one post-trigger sample.
@end quotation
@quotation Note
In addition to the requested pre/post-trigger samples, an additional sample, corresponding to the trigger, will be recoded.
@end quotation @end quotation
@c -------------------------------------------------------------------------- @c --------------------------------------------------------------------------
......
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ 0580effb
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hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
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...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd -- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb -- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Wed Aug 7 17:44:15 2013 -- Created : Tue Dec 17 09:57:20 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
...@@ -51,8 +51,10 @@ entity fmc_adc_100Ms_csr is ...@@ -51,8 +51,10 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_sta_serdes_pll_i : in std_logic; fmc_adc_core_sta_serdes_pll_i : in std_logic;
-- Port for BIT field: 'SerDes synchronization status' in reg: 'Status register' -- Port for BIT field: 'SerDes synchronization status' in reg: 'Status register'
fmc_adc_core_sta_serdes_synced_i : in std_logic; fmc_adc_core_sta_serdes_synced_i : in std_logic;
-- Port for BIT field: 'Acquisition configuration status' in reg: 'Status register'
fmc_adc_core_sta_acq_cfg_i : in std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status register' -- Port for std_logic_vector field: 'Reserved' in reg: 'Status register'
fmc_adc_core_sta_reserved_i : in std_logic_vector(26 downto 0); fmc_adc_core_sta_reserved_i : in std_logic_vector(25 downto 0);
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger selection' in reg: 'Trigger configuration' -- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger selection' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic; fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger polarity' in reg: 'Trigger configuration' -- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger polarity' in reg: 'Trigger configuration'
...@@ -429,7 +431,8 @@ begin ...@@ -429,7 +431,8 @@ begin
rddata_reg(2 downto 0) <= fmc_adc_core_sta_fsm_i; rddata_reg(2 downto 0) <= fmc_adc_core_sta_fsm_i;
rddata_reg(3) <= fmc_adc_core_sta_serdes_pll_i; rddata_reg(3) <= fmc_adc_core_sta_serdes_pll_i;
rddata_reg(4) <= fmc_adc_core_sta_serdes_synced_i; rddata_reg(4) <= fmc_adc_core_sta_serdes_synced_i;
rddata_reg(31 downto 5) <= fmc_adc_core_sta_reserved_i; rddata_reg(5) <= fmc_adc_core_sta_acq_cfg_i;
rddata_reg(31 downto 6) <= fmc_adc_core_sta_reserved_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00010" => when "00010" =>
...@@ -745,6 +748,7 @@ begin ...@@ -745,6 +748,7 @@ begin
-- State machine status -- State machine status
-- SerDes PLL status -- SerDes PLL status
-- SerDes synchronization status -- SerDes synchronization status
-- Acquisition configuration status
-- Reserved -- Reserved
-- Hardware trigger selection -- Hardware trigger selection
-- synchronizer chain for field : Hardware trigger selection (type RW/RO, clk_sys_i <-> fs_clk_i) -- synchronizer chain for field : Hardware trigger selection (type RW/RO, clk_sys_i <-> fs_clk_i)
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @ 0580effb
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h * File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb * Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Wed Aug 7 17:44:15 2013 * Created : Tue Dec 17 09:57:20 2013
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
...@@ -77,11 +77,14 @@ ...@@ -77,11 +77,14 @@
/* definitions for field: SerDes synchronization status in reg: Status register */ /* definitions for field: SerDes synchronization status in reg: Status register */
#define FMC_ADC_CORE_STA_SERDES_SYNCED WBGEN2_GEN_MASK(4, 1) #define FMC_ADC_CORE_STA_SERDES_SYNCED WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Acquisition configuration status in reg: Status register */
#define FMC_ADC_CORE_STA_ACQ_CFG WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Reserved in reg: Status register */ /* definitions for field: Reserved in reg: Status register */
#define FMC_ADC_CORE_STA_RESERVED_MASK WBGEN2_GEN_MASK(5, 27) #define FMC_ADC_CORE_STA_RESERVED_MASK WBGEN2_GEN_MASK(6, 26)
#define FMC_ADC_CORE_STA_RESERVED_SHIFT 5 #define FMC_ADC_CORE_STA_RESERVED_SHIFT 6
#define FMC_ADC_CORE_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 27) #define FMC_ADC_CORE_STA_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 6, 26)
#define FMC_ADC_CORE_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 27) #define FMC_ADC_CORE_STA_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 6, 26)
/* definitions for register: Trigger configuration */ /* definitions for register: Trigger configuration */
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
View file @ 0580effb
...@@ -809,7 +809,24 @@ fmc_adc_core_sta_serdes_synced_i ...@@ -809,7 +809,24 @@ fmc_adc_core_sta_serdes_synced_i
</td> </td>
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fmc_adc_core_sta_reserved_i[26:0] fmc_adc_core_sta_acq_cfg_i
</td>
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&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_sta_reserved_i[25:0]
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&lArr; &lArr;
...@@ -2849,7 +2866,7 @@ STA ...@@ -2849,7 +2866,7 @@ STA
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[26:19] RESERVED[25:18]
</td> </td>
<td > <td >
...@@ -2903,7 +2920,7 @@ RESERVED[26:19] ...@@ -2903,7 +2920,7 @@ RESERVED[26:19]
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[18:11] RESERVED[17:10]
</td> </td>
<td > <td >
...@@ -2957,7 +2974,7 @@ RESERVED[18:11] ...@@ -2957,7 +2974,7 @@ RESERVED[18:11]
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[10:3] RESERVED[9:2]
</td> </td>
<td > <td >
...@@ -3010,8 +3027,11 @@ RESERVED[10:3] ...@@ -3010,8 +3027,11 @@ RESERVED[10:3]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=3 class="td_field"> <td style="border: solid 1px black;" colspan=2 class="td_field">
RESERVED[2:0] RESERVED[1:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ACQ_CFG
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td style="border: solid 1px black;" colspan=1 class="td_field">
SERDES_SYNCED SERDES_SYNCED
...@@ -3030,9 +3050,6 @@ FSM[2:0] ...@@ -3030,9 +3050,6 @@ FSM[2:0]
</td> </td>
<td > <td >
</td>
<td >
</td> </td>
</tr> </tr>
</table> </table>
...@@ -3040,7 +3057,7 @@ FSM[2:0] ...@@ -3040,7 +3057,7 @@ FSM[2:0]
<li><b> <li><b>
FSM FSM
</b>[<i>read-only</i>]: State machine status </b>[<i>read-only</i>]: State machine status
<br>States:<br>0: illegal<br>1: IDLE<br>2: PRE_TRIG<br>3: WAIT_TRIG<br>4: POST_TRIG<br>5: DECR_SHOT<br>6: illegal<br>7: illegal <br>States:<br>0: illegal<br>1: IDLE<br>2: PRE_TRIG<br>3: WAIT_TRIG<br>4: POST_TRIG<br>5: TRIG_TAG<br>6: DECR_SHOT<br>7: illegal
<li><b> <li><b>
SERDES_PLL SERDES_PLL
</b>[<i>read-only</i>]: SerDes PLL status </b>[<i>read-only</i>]: SerDes PLL status
...@@ -3050,6 +3067,10 @@ SERDES_SYNCED ...@@ -3050,6 +3067,10 @@ SERDES_SYNCED
</b>[<i>read-only</i>]: SerDes synchronization status </b>[<i>read-only</i>]: SerDes synchronization status
<br>0: bitslip in progress<br>1: serdes synchronized <br>0: bitslip in progress<br>1: serdes synchronized
<li><b> <li><b>
ACQ_CFG
</b>[<i>read-only</i>]: Acquisition configuration status
<br>0: Unauthorised acquisition configuration (will prevent acquisition to start)<br>1: Valid acquisition configuration<br>- Shot number > 0<br>- Post-trigger sample > 0
<li><b>
RESERVED RESERVED
</b>[<i>read-only</i>]: Reserved </b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's <br>Ignore on read, write with 0's
...@@ -3334,7 +3355,7 @@ RESERVED ...@@ -3334,7 +3355,7 @@ RESERVED
<li><b> <li><b>
INT_TRIG_THRES INT_TRIG_THRES
</b>[<i>read/write</i>]: Threshold for internal trigger </b>[<i>read/write</i>]: Threshold for internal trigger
<br>Treated as binary two's complement and compared to raw ADC data <br>Treated as binary two's complement and compared to raw ADC data.
</ul> </ul>
<a name="TRIG_DLY"></a> <a name="TRIG_DLY"></a>
<h3><a name="sect_3_4">3.4. Trigger delay</a></h3> <h3><a name="sect_3_4">3.4. Trigger delay</a></h3>
...@@ -4888,7 +4909,7 @@ PRE_SAMPLES[7:0] ...@@ -4888,7 +4909,7 @@ PRE_SAMPLES[7:0]
<li><b> <li><b>
PRE_SAMPLES PRE_SAMPLES
</b>[<i>read/write</i>]: Pre-trigger samples </b>[<i>read/write</i>]: Pre-trigger samples
<br>Number of requested pre-trigger samples <br>Number of requested pre-trigger samples (>1).
</ul> </ul>
<a name="POST_SAMPLES"></a> <a name="POST_SAMPLES"></a>
<h3><a name="sect_3_10">3.10. Post-trigger samples</a></h3> <h3><a name="sect_3_10">3.10. Post-trigger samples</a></h3>
...@@ -5146,7 +5167,7 @@ POST_SAMPLES[7:0] ...@@ -5146,7 +5167,7 @@ POST_SAMPLES[7:0]
<li><b> <li><b>
POST_SAMPLES POST_SAMPLES
</b>[<i>read/write</i>]: Post-trigger samples </b>[<i>read/write</i>]: Post-trigger samples
<br>Number of requested post-trigger samples <br>Number of requested post-trigger samples (>1).
</ul> </ul>
<a name="SAMPLES_CNT"></a> <a name="SAMPLES_CNT"></a>
<h3><a name="sect_3_11">3.11. Samples counter</a></h3> <h3><a name="sect_3_11">3.11. Samples counter</a></h3>
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
View file @ 0580effb
...@@ -86,7 +86,7 @@ peripheral { ...@@ -86,7 +86,7 @@ peripheral {
field { field {
name = "State machine status"; name = "State machine status";
description = "States:\n0: illegal\n1: IDLE\n2: PRE_TRIG\n3: WAIT_TRIG\n4: POST_TRIG\n5: DECR_SHOT\n6: illegal\n7: illegal"; description = "States:\n0: illegal\n1: IDLE\n2: PRE_TRIG\n3: WAIT_TRIG\n4: POST_TRIG\n5: TRIG_TAG\n6: DECR_SHOT\n7: illegal";
prefix = "fsm"; prefix = "fsm";
type = SLV; type = SLV;
size = 3; size = 3;
...@@ -112,12 +112,21 @@ peripheral { ...@@ -112,12 +112,21 @@ peripheral {
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
field {
name = "Acquisition configuration status";
description = "0: Unauthorised acquisition configuration (will prevent acquisition to start)\n1: Valid acquisition configuration\n- Shot number > 0\n- Post-trigger sample > 0";
prefix = "acq_cfg";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field { field {
name = "Reserved"; name = "Reserved";
description = "Ignore on read, write with 0's"; description = "Ignore on read, write with 0's";
prefix = "reserved"; prefix = "reserved";
type = SLV; type = SLV;
size = 27; size = 26;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
...@@ -190,7 +199,7 @@ peripheral { ...@@ -190,7 +199,7 @@ peripheral {
field { field {
name = "Threshold for internal trigger"; name = "Threshold for internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data"; description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "int_trig_thres"; prefix = "int_trig_thres";
type = SLV; type = SLV;
size = 16; size = 16;
...@@ -288,7 +297,7 @@ peripheral { ...@@ -288,7 +297,7 @@ peripheral {
field { field {
name = "Pre-trigger samples"; name = "Pre-trigger samples";
description = "Number of requested pre-trigger samples"; description = "Number of requested pre-trigger samples (>1).";
type = SLV; type = SLV;
size = 32; size = 32;
access_bus = READ_WRITE; access_bus = READ_WRITE;
...@@ -302,7 +311,7 @@ peripheral { ...@@ -302,7 +311,7 @@ peripheral {
field { field {
name = "Post-trigger samples"; name = "Post-trigger samples";
description = "Number of requested post-trigger samples"; description = "Number of requested post-trigger samples (>1).";
type = SLV; type = SLV;
size = 32; size = 32;
access_bus = READ_WRITE; access_bus = READ_WRITE;
......
hdl/spec/rtl/carrier_csr.vhd
View file @ 0580effb
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd -- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb -- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Thu Aug 8 14:54:22 2013 -- Created : Wed Dec 11 11:55:04 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ 0580effb
...@@ -347,8 +347,8 @@ architecture rtl of spec_top_fmc_adc_100Ms is ...@@ -347,8 +347,8 @@ architecture rtl of spec_top_fmc_adc_100Ms is
name => "WB-FMC-ADC.EIC "))); name => "WB-FMC-ADC.EIC ")));
-- f_xwb_bridge_manual_sdb(size, sdb_addr) -- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the parent interconnect -- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_fmc0_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00004000"); constant c_fmc0_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
-- sdb header address -- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000"; constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
......
hdl/spec/sim/Makefile
View file @ 0580effb
This diff is collapsed.
hdl/spec/sim/Manifest.py
View file @ 0580effb
...@@ -7,14 +7,21 @@ files = ["testbench/gn412x_bfm.vhd", ...@@ -7,14 +7,21 @@ files = ["testbench/gn412x_bfm.vhd",
"testbench/util.vhd", "testbench/util.vhd",
"testbench/tb_spec.vhd", "testbench/tb_spec.vhd",
"testbench/cmd_router1.vhd", "testbench/cmd_router1.vhd",
"../ip_cores/adc_sync_fifo.vhd", "../../ip_cores/adc_sync_fifo.vhd",
"../ip_cores/multishot_dpram.vhd", "../../ip_cores/multishot_dpram.vhd",
"../ip_cores/wb_ddr_fifo.vhd", "../../ip_cores/wb_ddr_fifo.vhd",
"../ip_cores/adc_serdes.vhd", "../../ip_cores/adc_serdes.vhd",
"../ip_cores/monostable/monostable_rtl.vhd", "../../ip_cores/monostable/monostable_rtl.vhd",
"../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd", "../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd",
"../ip_cores/utils/utils_pkg.vhd"] "../../ip_cores/utils/utils_pkg.vhd"]
modules = { "local" : ["../rtl", modules = { "local" : ["../rtl",
"../../adc/rtl",
"../../ip_cores/timetag_core/rtl",
"testbench", "testbench",
"sim_models/2048Mb_ddr3"]} "sim_models/2048Mb_ddr3"],
"git" : ["git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::spec_bank3_64b_32b",
"git://ohwr.org/hdl-core-lib/gn4124-core.git::master"]}
fetchto="../../ip_cores"
hdl/spec/sim/cmd0.vec
View file @ 0580effb
...@@ -209,86 +209,106 @@ wait %d2000 ...@@ -209,86 +209,106 @@ wait %d2000
-- onewire config -- onewire config
wr FF00000000001A04 F 007C0270 wr FF00000000001104 F 007C0270
wait %d100 wait %d100
wr FF00000000001A00 F 0000000A wr FF00000000001100 F 0000000A
wait %d100 wait %d100
-- irq mask -- fmc eic set irq enable mask
wr FF00000000001508 F 0000000F wr FF00000000002004 F 00000003
-- dma eic set irq enable mask
wr FF00000000001404 F 00000003
-- vic set irq enable mask
wr FF00000000001308 F 00000003
-- vic config
wr FF00000000001300 F 00001777
-- release fmc reset
wr FF0000000000120C F 00000003
-- Set time-tag core seconds
wr FF00000000002100 F 00001234
-- Set time-tag core coarse time
wr FF00000000002104 F 00000000
-- trigger config (sw trig enable) -- trigger config (sw trig enable)
wr FF00000000001908 F 00000008 wr FF00000000005308 F 00000008
-- trigger config (hw int trig enable) -- trigger config (hw int trig enable)
--wr FF00000000001908 F 00000004 --wr FF00000000005308 F 00000004
-- trigger config (int trig) -- trigger config (int trig)
--wr FF00000000001908 F 02600004 --wr FF00000000005308 F 02600004
-- decimation factor = 1 -- decimation factor = 1
wr FF0000000000191C F 00000001 wr FF0000000000531C F 00000001
-- pre-trig samples -- pre-trig samples
wr FF00000000001920 F 00000100 wr FF00000000005320 F 00000000
-- post-trig samples -- post-trig samples
wr FF00000000001924 F 00001000 wr FF00000000005324 F 00000001
-- number of shots -- number of shots
wr FF00000000001914 F 00000001 wr FF00000000005314 F 00000003
-- Channel 1 gain -- Channel 1 gain
wr FF00000000001934 F 00008000 wr FF00000000005334 F 00008000
-- Channel 1 offset -- Channel 1 offset
wr FF00000000001938 F 00000000 wr FF00000000005338 F 00000000
-- Channel 2 gain -- Channel 2 gain
wr FF00000000001944 F 00008000 wr FF00000000005344 F 00008000
-- Channel 2 offset -- Channel 2 offset
wr FF00000000001948 F 00000000 wr FF00000000005348 F 00000000
-- Channel 3 gain -- Channel 3 gain
wr FF00000000001954 F 00008000 wr FF00000000005354 F 00008000
-- Channel 3 offset -- Channel 3 offset
wr FF00000000001958 F 00000000 wr FF00000000005358 F 00000000
-- Channel 4 gain -- Channel 4 gain
wr FF00000000001964 F 00008000 wr FF00000000005364 F 00008000
-- Channel 4 offset -- Channel 4 offset
wr FF00000000001968 F 00000000 wr FF00000000005368 F 00000000
-- Enable test data and sampling clock -- Enable test data and sampling clock
--wr FF00000000001900 F 00000024 --wr FF00000000005300 F 00000024
-- Enable sampling clock -- Enable sampling clock
wr FF00000000001900 F 00000004 wr FF00000000005300 F 00000004
wait %d2000
-- start acquisition -- start acquisition
--wr FF00000000001900 F 00000025 --wr FF00000000005300 F 00000025
wr FF00000000001900 F 00000005 wr FF00000000005300 F 00000005
wait %d800 wait %d800
-- sw trigger -- sw trigger
wr FF00000000001910 F FFFFFFFF wr FF00000000005310 F FFFFFFFF
wait %d800 wait %d800
-- stop acquisition -- stop acquisition
wr FF00000000001900 F 00000006 --wr FF00000000005300 F 00000006
wait %d800 wait %d800
-- sw trigger -- sw trigger
--wr FF00000000001910 F FFFFFFFF wr FF00000000005310 F FFFFFFFF
wait %d800 wait %d800
-- sw trigger -- sw trigger
--wr FF00000000001910 F FFFFFFFF wr FF00000000005310 F FFFFFFFF
wait %d800 wait %d800
-- sw trigger -- sw trigger
--wr FF00000000001910 F FFFFFFFF --wr FF00000000005310 F FFFFFFFF
wait %d800 wait %d800
-- sw trigger -- sw trigger
--wr FF00000000001910 F FFFFFFFF --wr FF00000000005310 F FFFFFFFF
wait %d1000 wait %d1000
...@@ -316,11 +336,11 @@ wait %d3000 ...@@ -316,11 +336,11 @@ wait %d3000
--------------------------------------------- ---------------------------------------------
-- start acquisition -- start acquisition
--wr FF00000000001900 F 00000001 --wr FF00000000005300 F 00000001
wait %d500 wait %d500
-- sw trigger -- sw trigger
--wr FF00000000001910 F FFFFFFFF --wr FF00000000005310 F FFFFFFFF
wait %d400 wait %d400
......
hdl/spec/sim/spec.do
View file @ 0580effb
...@@ -7,8 +7,9 @@ log -r /* ...@@ -7,8 +7,9 @@ log -r /*
##do wave_onewire.do ##do wave_onewire.do
##do wave_adc_core.do ##do wave_adc_core.do
##do wave_gnum.do ##do wave_gnum.do
do wave_end_acq_irq.do ##do wave_end_acq_irq.do
##do wave_ddr_wb.do ##do wave_ddr_wb.do
do wave_trig_tag.do
view wave view wave
view transcript view transcript
......
hdl/spec/sim/testbench/tb_spec.vhd
View file @ 0580effb
...@@ -227,45 +227,45 @@ architecture TEST of TB_SPEC is ...@@ -227,45 +227,45 @@ architecture TEST of TB_SPEC is
DDR3_RZQ : inout std_logic; DDR3_RZQ : inout std_logic;
-- FMC slot -- FMC slot
ext_trigger_p_i : in std_logic; -- External trigger adc0_ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic; adc0_ext_trigger_n_i : in std_logic;
adc_dco_p_i : in std_logic; -- ADC data clock adc0_dco_p_i : in std_logic; -- ADC data clock
adc_dco_n_i : in std_logic; adc0_dco_n_i : in std_logic;
adc_fr_p_i : in std_logic; -- ADC frame start adc0_fr_p_i : in std_logic; -- ADC frame start
adc_fr_n_i : in std_logic; adc0_fr_n_i : in std_logic;
adc_outa_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (odd bits) adc0_outa_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (odd bits)
adc_outa_n_i : in std_logic_vector(3 downto 0); adc0_outa_n_i : in std_logic_vector(3 downto 0);
adc_outb_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (even bits) adc0_outb_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (even bits)
adc_outb_n_i : in std_logic_vector(3 downto 0); adc0_outb_n_i : in std_logic_vector(3 downto 0);
spi_din_i : in std_logic; -- SPI data from FMC adc0_spi_din_i : in std_logic; -- SPI data from FMC
spi_dout_o : out std_logic; -- SPI data to FMC adc0_spi_dout_o : out std_logic; -- SPI data to FMC
spi_sck_o : out std_logic; -- SPI clock adc0_spi_sck_o : out std_logic; -- SPI clock
spi_cs_adc_n_o : out std_logic; -- SPI ADC chip select (active low) adc0_spi_cs_adc_n_o : out std_logic; -- SPI ADC chip select (active low)
spi_cs_dac1_n_o : out std_logic; -- SPI channel 1 offset DAC chip select (active low) adc0_spi_cs_dac1_n_o : out std_logic; -- SPI channel 1 offset DAC chip select (active low)
spi_cs_dac2_n_o : out std_logic; -- SPI channel 2 offset DAC chip select (active low) adc0_spi_cs_dac2_n_o : out std_logic; -- SPI channel 2 offset DAC chip select (active low)
spi_cs_dac3_n_o : out std_logic; -- SPI channel 3 offset DAC chip select (active low) adc0_spi_cs_dac3_n_o : out std_logic; -- SPI channel 3 offset DAC chip select (active low)
spi_cs_dac4_n_o : out std_logic; -- SPI channel 4 offset DAC chip select (active low) adc0_spi_cs_dac4_n_o : out std_logic; -- SPI channel 4 offset DAC chip select (active low)
gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low) adc0_gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low)
gpio_led_acq_o : out std_logic; -- Mezzanine front panel power LED (PWR) adc0_gpio_led_acq_o : out std_logic; -- Mezzanine front panel power LED (PWR)
gpio_led_trig_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG) adc0_gpio_led_trig_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control adc0_gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control
gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control adc0_gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control
gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control adc0_gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control
gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control adc0_gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
gpio_si570_oe_o : out std_logic; -- Si570 (programmable oscillator) output enable adc0_gpio_si570_oe_o : out std_logic; -- Si570 (programmable oscillator) output enable
si570_scl_b : inout std_logic; -- I2C bus clock (Si570) adc0_si570_scl_b : inout std_logic; -- I2C bus clock (Si570)
si570_sda_b : inout std_logic; -- I2C bus data (Si570) adc0_si570_sda_b : inout std_logic; -- I2C bus data (Si570)
mezz_one_wire_b : inout std_logic; -- 1-wire interface (DS18B20 thermometer + unique ID) adc0_one_wire_b : inout std_logic; -- 1-wire interface (DS18B20 thermometer + unique ID)
prsnt_m2c_n_i : in std_logic; -- Mezzanine present (active low) fmc0_prsnt_m2c_n_i : in std_logic; -- Mezzanine present (active low)
sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM) fmc0_sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
sys_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM) fmc0_sys_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM)
); );
end component spec_top_fmc_adc_100Ms; end component spec_top_fmc_adc_100Ms;
...@@ -615,45 +615,45 @@ begin ...@@ -615,45 +615,45 @@ begin
gpio => GPIO(9 downto 8), -- General Purpose Input/Output gpio => GPIO(9 downto 8), -- General Purpose Input/Output
-- FMC slot -- FMC slot
ext_trigger_p_i => ext_trigger_p_i, adc0_ext_trigger_p_i => ext_trigger_p_i,
ext_trigger_n_i => ext_trigger_n_i, adc0_ext_trigger_n_i => ext_trigger_n_i,
adc_dco_p_i => adc_dco_p_i, adc0_dco_p_i => adc_dco_p_i,
adc_dco_n_i => adc_dco_n_i, adc0_dco_n_i => adc_dco_n_i,
adc_fr_p_i => adc_fr_p_i, adc0_fr_p_i => adc_fr_p_i,
adc_fr_n_i => adc_fr_n_i, adc0_fr_n_i => adc_fr_n_i,
adc_outa_p_i => adc_outa_p_i, adc0_outa_p_i => adc_outa_p_i,
adc_outa_n_i => adc_outa_n_i, adc0_outa_n_i => adc_outa_n_i,
adc_outb_p_i => adc_outb_p_i, adc0_outb_p_i => adc_outb_p_i,
adc_outb_n_i => adc_outb_n_i, adc0_outb_n_i => adc_outb_n_i,
spi_din_i => spi_din_i, adc0_spi_din_i => spi_din_i,
spi_dout_o => spi_dout_o, adc0_spi_dout_o => spi_dout_o,
spi_sck_o => spi_sck_o, adc0_spi_sck_o => spi_sck_o,
spi_cs_adc_n_o => spi_cs_adc_n_o , adc0_spi_cs_adc_n_o => spi_cs_adc_n_o ,
spi_cs_dac1_n_o => spi_cs_dac1_n_o, adc0_spi_cs_dac1_n_o => spi_cs_dac1_n_o,
spi_cs_dac2_n_o => spi_cs_dac2_n_o, adc0_spi_cs_dac2_n_o => spi_cs_dac2_n_o,
spi_cs_dac3_n_o => spi_cs_dac3_n_o, adc0_spi_cs_dac3_n_o => spi_cs_dac3_n_o,
spi_cs_dac4_n_o => spi_cs_dac4_n_o, adc0_spi_cs_dac4_n_o => spi_cs_dac4_n_o,
gpio_dac_clr_n_o => gpio_dac_clr_n_o, adc0_gpio_dac_clr_n_o => gpio_dac_clr_n_o,
gpio_led_acq_o => gpio_led_acq_o, adc0_gpio_led_acq_o => gpio_led_acq_o,
gpio_led_trig_o => gpio_led_trig_o, adc0_gpio_led_trig_o => gpio_led_trig_o,
gpio_ssr_ch1_o => gpio_ssr_ch1_o, adc0_gpio_ssr_ch1_o => gpio_ssr_ch1_o,
gpio_ssr_ch2_o => gpio_ssr_ch2_o, adc0_gpio_ssr_ch2_o => gpio_ssr_ch2_o,
gpio_ssr_ch3_o => gpio_ssr_ch3_o, adc0_gpio_ssr_ch3_o => gpio_ssr_ch3_o,
gpio_ssr_ch4_o => gpio_ssr_ch4_o, adc0_gpio_ssr_ch4_o => gpio_ssr_ch4_o,
gpio_si570_oe_o => gpio_si570_oe_o, adc0_gpio_si570_oe_o => gpio_si570_oe_o,
si570_scl_b => si570_scl_b, adc0_si570_scl_b => si570_scl_b,
si570_sda_b => si570_sda_b, adc0_si570_sda_b => si570_sda_b,
mezz_one_wire_b => mezz_one_wire_b, adc0_one_wire_b => mezz_one_wire_b,
prsnt_m2c_n_i => prsnt_m2c_n_i, fmc0_prsnt_m2c_n_i => prsnt_m2c_n_i,
sys_scl_b => sys_scl_b, fmc0_sys_scl_b => sys_scl_b,
sys_sda_b => sys_sda_b, fmc0_sys_sda_b => sys_sda_b,
-- DDR3 interface -- DDR3 interface
ddr3_a => ddr3_a_o, ddr3_a => ddr3_a_o,
......
hdl/spec/wb_gen/carrier_csr.h
View file @ 0580effb
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : carrier_csr.h * File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb * Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Thu Aug 8 14:54:22 2013 * Created : Wed Dec 11 11:55:04 2013
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @ 0580effb
...@@ -321,13 +321,13 @@ architecture rtl of svec_top_fmc_adc_100Ms is ...@@ -321,13 +321,13 @@ architecture rtl of svec_top_fmc_adc_100Ms is
constant c_WB_SLAVE_VIC : integer := 3; -- Vectored interrupt controller constant c_WB_SLAVE_VIC : integer := 3; -- Vectored interrupt controller
constant c_WB_SLAVE_FMC0_EIC : integer := 4; -- FMC slot 1 interrupt controller constant c_WB_SLAVE_FMC0_EIC : integer := 4; -- FMC slot 1 interrupt controller
constant c_WB_SLAVE_FMC0_TIMETAG : integer := 5; -- FMC slot 1 timetag core constant c_WB_SLAVE_FMC0_TIMETAG : integer := 5; -- FMC slot 1 timetag core
constant c_WB_SLAVE_FMC0_DDR_DAT : integer := 6; -- FMC slot 1 DDR data constant c_WB_SLAVE_FMC0_DDR_ADR : integer := 6; -- FMC slot 1 DDR address
constant c_WB_SLAVE_FMC0_DDR_ADR : integer := 7; -- FMC slot 1 DDR address constant c_WB_SLAVE_FMC0_DDR_DAT : integer := 7; -- FMC slot 1 DDR data
constant c_WB_SLAVE_FMC0_ADC : integer := 8; -- FMC slot 1 ADC mezzanine constant c_WB_SLAVE_FMC0_ADC : integer := 8; -- FMC slot 1 ADC mezzanine
constant c_WB_SLAVE_FMC1_EIC : integer := 9; -- FMC slot 2 interrupt controller constant c_WB_SLAVE_FMC1_EIC : integer := 9; -- FMC slot 2 interrupt controller
constant c_WB_SLAVE_FMC1_TIMETAG : integer := 10; -- FMC slot 2 timetag core constant c_WB_SLAVE_FMC1_TIMETAG : integer := 10; -- FMC slot 2 timetag core
constant c_WB_SLAVE_FMC1_DDR_DAT : integer := 11; -- FMC slot 2 DDR data constant c_WB_SLAVE_FMC1_DDR_ADR : integer := 11; -- FMC slot 2 DDR address
constant c_WB_SLAVE_FMC1_DDR_ADR : integer := 12; -- FMC slot 2 DDR address constant c_WB_SLAVE_FMC1_DDR_DAT : integer := 12; -- FMC slot 2 DDR data
constant c_WB_SLAVE_FMC1_ADC : integer := 13; -- FMC slot 2 ADC mezzanine constant c_WB_SLAVE_FMC1_ADC : integer := 13; -- FMC slot 2 ADC mezzanine
...@@ -413,9 +413,9 @@ architecture rtl of svec_top_fmc_adc_100Ms is ...@@ -413,9 +413,9 @@ architecture rtl of svec_top_fmc_adc_100Ms is
name => "WB-DDR-Addr-Access "))); name => "WB-DDR-Addr-Access ")));
-- f_xwb_bridge_manual_sdb(size, sdb_addr) -- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the parent interconnect -- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_fmc0_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00004000"); constant c_fmc0_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
constant c_fmc1_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00008000"); constant c_fmc1_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
-- sdb header address -- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000"; constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
...@@ -552,18 +552,18 @@ architecture rtl of svec_top_fmc_adc_100Ms is ...@@ -552,18 +552,18 @@ architecture rtl of svec_top_fmc_adc_100Ms is
signal led_state_man : std_logic_vector(15 downto 0); signal led_state_man : std_logic_vector(15 downto 0);
-- DDR0 (bank 4) -- DDR0 (bank 4)
signal ddr0_status : std_logic_vector(31 downto 0); signal ddr0_status : std_logic_vector(31 downto 0);
signal ddr0_calib_done : std_logic; signal ddr0_calib_done : std_logic;
signal ddr0_addr_cnt : unsigned(31 downto 0); signal ddr0_addr_cnt : unsigned(31 downto 0);
signal ddr0_wb_cyc_d : std_logic; signal ddr0_dat_cyc_d : std_logic;
signal ddr0_wb_cyc_fe : std_logic; signal ddr0_addr_cnt_en : std_logic;
-- DDR1 (bank 5) -- DDR1 (bank 5)
signal ddr1_status : std_logic_vector(31 downto 0); signal ddr1_status : std_logic_vector(31 downto 0);
signal ddr1_calib_done : std_logic; signal ddr1_calib_done : std_logic;
signal ddr1_addr_cnt : unsigned(31 downto 0); signal ddr1_addr_cnt : unsigned(31 downto 0);
signal ddr1_wb_cyc_d : std_logic; signal ddr1_dat_cyc_d : std_logic;
signal ddr1_wb_cyc_fe : std_logic; signal ddr1_addr_cnt_en : std_logic;
-- Carrier 1-wire -- Carrier 1-wire
signal carrier_owr_en : std_logic_vector(0 downto 0); signal carrier_owr_en : std_logic_vector(0 downto 0);
...@@ -582,6 +582,8 @@ architecture rtl of svec_top_fmc_adc_100Ms is ...@@ -582,6 +582,8 @@ architecture rtl of svec_top_fmc_adc_100Ms is
signal acq_start_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0); signal acq_start_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal acq_stop_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0); signal acq_stop_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal acq_end_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0); signal acq_end_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal fmc0_trigger_tag : t_timetag;
signal fmc1_trigger_tag : t_timetag;
-- led pwm -- led pwm
signal led_pwm_update_cnt : unsigned(9 downto 0); signal led_pwm_update_cnt : unsigned(9 downto 0);
...@@ -936,7 +938,7 @@ begin ...@@ -936,7 +938,7 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_fmc0_eic : fmc_adc_eic cmp_fmc0_eic : fmc_adc_eic
port map( port map(
rst_n_i => sys_rst_n, rst_n_i => fmc0_rst_n,
clk_sys_i => sys_clk_125, clk_sys_i => sys_clk_125,
wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).adr(3 downto 2), -- cnx_master_out.adr is byte address wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).dat, wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).dat,
...@@ -962,7 +964,7 @@ begin ...@@ -962,7 +964,7 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_fmc1_eic : fmc_adc_eic cmp_fmc1_eic : fmc_adc_eic
port map( port map(
rst_n_i => sys_rst_n, rst_n_i => fmc1_rst_n,
clk_sys_i => sys_clk_125, clk_sys_i => sys_clk_125,
wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC1_EIC).adr(3 downto 2), -- cnx_master_out.adr is byte address wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC1_EIC).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC1_EIC).dat, wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC1_EIC).dat,
...@@ -992,7 +994,7 @@ begin ...@@ -992,7 +994,7 @@ begin
p_ddr_wr_fifo_empty : process (sys_clk_125) p_ddr_wr_fifo_empty : process (sys_clk_125)
begin begin
if rising_edge(sys_clk_125) then if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then if fmc0_rst_n = '0' or fmc1_rst_n = '0' then
ddr_wr_fifo_empty_d(I) <= '0'; ddr_wr_fifo_empty_d(I) <= '0';
ddr_wr_fifo_empty_d1(I) <= '0'; ddr_wr_fifo_empty_d1(I) <= '0';
else else
...@@ -1009,7 +1011,7 @@ begin ...@@ -1009,7 +1011,7 @@ begin
p_acq_end_extend : process (sys_clk_125) p_acq_end_extend : process (sys_clk_125)
begin begin
if rising_edge(sys_clk_125) then if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then if fmc0_rst_n = '0' or fmc1_rst_n = '0' then
acq_end_extend(I) <= '0'; acq_end_extend(I) <= '0';
elsif acq_end_p(I) = '1' then elsif acq_end_p(I) = '1' then
acq_end_extend(I) <= '1'; acq_end_extend(I) <= '1';
...@@ -1063,6 +1065,8 @@ begin ...@@ -1063,6 +1065,8 @@ begin
acq_stop_p_o => acq_stop_p(0), acq_stop_p_o => acq_stop_p(0),
acq_end_p_o => acq_end_p(0), acq_end_p_o => acq_end_p(0),
trigger_tag_i => fmc0_trigger_tag,
ext_trigger_p_i => adc0_ext_trigger_p_i, ext_trigger_p_i => adc0_ext_trigger_p_i,
ext_trigger_n_i => adc0_ext_trigger_n_i, ext_trigger_n_i => adc0_ext_trigger_n_i,
...@@ -1149,6 +1153,8 @@ begin ...@@ -1149,6 +1153,8 @@ begin
acq_stop_p_o => acq_stop_p(1), acq_stop_p_o => acq_stop_p(1),
acq_end_p_o => acq_end_p(1), acq_end_p_o => acq_end_p(1),
trigger_tag_i => fmc1_trigger_tag,
ext_trigger_p_i => adc1_ext_trigger_p_i, ext_trigger_p_i => adc1_ext_trigger_p_i,
ext_trigger_n_i => adc1_ext_trigger_n_i, ext_trigger_n_i => adc1_ext_trigger_n_i,
...@@ -1292,19 +1298,18 @@ begin ...@@ -1292,19 +1298,18 @@ begin
-- The counter is incremented on the falling edge of cyc. This is because the ddr controller -- The counter is incremented on the falling edge of cyc. This is because the ddr controller
-- samples the address on (cyc_re and stb)+1 -- samples the address on (cyc_re and stb)+1
-- cyc falling edge detection p_ddr0_dat_cyc: process (sys_clk_125)
p_ddr0_wb_cyc : process (sys_clk_125)
begin begin
if rising_edge(sys_clk_125) then if rising_edge(sys_clk_125) then
if (fmc0_rst_n = '0') then if fmc0_rst_n = '0' then
ddr0_wb_cyc_d <= '0'; ddr0_dat_cyc_d <= '0';
else else
ddr0_wb_cyc_d <= cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc; ddr0_dat_cyc_d <= cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc;
end if; end if;
end if; end if;
end process p_ddr0_wb_cyc; end process p_ddr0_dat_cyc;
ddr0_wb_cyc_fe <= not(cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc) and ddr0_wb_cyc_d; ddr0_addr_cnt_en <= not(cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc) and ddr0_dat_cyc_d;
-- address counter -- address counter
p_ddr0_addr_cnt : process (sys_clk_125) p_ddr0_addr_cnt : process (sys_clk_125)
...@@ -1316,7 +1321,7 @@ begin ...@@ -1316,7 +1321,7 @@ begin
cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).stb = '1' and cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).stb = '1' and
cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).cyc = '1') then cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).cyc = '1') then
ddr0_addr_cnt <= unsigned(cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).dat); ddr0_addr_cnt <= unsigned(cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).dat);
elsif (ddr0_wb_cyc_fe = '1') then elsif (ddr0_addr_cnt_en = '1') then
ddr0_addr_cnt <= ddr0_addr_cnt + 1; ddr0_addr_cnt <= ddr0_addr_cnt + 1;
end if; end if;
end if; end if;
...@@ -1445,19 +1450,18 @@ begin ...@@ -1445,19 +1450,18 @@ begin
-- The counter is incremented on the falling edge of cyc. This is because the ddr controller -- The counter is incremented on the falling edge of cyc. This is because the ddr controller
-- samples the address on (cyc_re and stb)+1 -- samples the address on (cyc_re and stb)+1
-- cyc falling edge detection p_ddr1_dat_cyc: process (sys_clk_125)
p_ddr1_wb_cyc : process (sys_clk_125)
begin begin
if rising_edge(sys_clk_125) then if rising_edge(sys_clk_125) then
if (fmc1_rst_n = '0') then if fmc1_rst_n = '0' then
ddr1_wb_cyc_d <= '0'; ddr1_dat_cyc_d <= '0';
else else
ddr1_wb_cyc_d <= cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc; ddr1_dat_cyc_d <= cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc;
end if; end if;
end if; end if;
end process p_ddr1_wb_cyc; end process p_ddr1_dat_cyc;
ddr1_wb_cyc_fe <= not(cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc) and ddr1_wb_cyc_d; ddr1_addr_cnt_en <= not(cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc) and ddr1_dat_cyc_d;
-- address counter -- address counter
p_ddr1_addr_cnt : process (sys_clk_125) p_ddr1_addr_cnt : process (sys_clk_125)
...@@ -1469,7 +1473,7 @@ begin ...@@ -1469,7 +1473,7 @@ begin
cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).stb = '1' and cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).stb = '1' and
cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).cyc = '1') then cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).cyc = '1') then
ddr1_addr_cnt <= unsigned(cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).dat); ddr1_addr_cnt <= unsigned(cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).dat);
elsif (ddr1_wb_cyc_fe = '1') then elsif (ddr1_addr_cnt_en = '1') then
ddr1_addr_cnt <= ddr1_addr_cnt + 1; ddr1_addr_cnt <= ddr1_addr_cnt + 1;
end if; end if;
end if; end if;
...@@ -1512,6 +1516,8 @@ begin ...@@ -1512,6 +1516,8 @@ begin
acq_stop_p_i => acq_stop_p(0), acq_stop_p_i => acq_stop_p(0),
acq_end_p_i => acq_end_p(0), acq_end_p_i => acq_end_p(0),
trig_tag_o => fmc0_trigger_tag,
wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).dat, wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).dat, wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).dat,
...@@ -1541,6 +1547,8 @@ begin ...@@ -1541,6 +1547,8 @@ begin
acq_stop_p_i => acq_stop_p(1), acq_stop_p_i => acq_stop_p(1),
acq_end_p_i => acq_end_p(1), acq_end_p_i => acq_end_p(1),
trig_tag_o => fmc1_trigger_tag,
wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).dat, wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).dat, wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).dat,
......
hdl/svec/sim/testbench/Makefile
View file @ 0580effb
This diff is collapsed.
hdl/svec/sim/testbench/main.sv
View file @ 0580effb
...@@ -112,6 +112,8 @@ module main; ...@@ -112,6 +112,8 @@ module main;
initial begin initial begin
uint64_t d; uint64_t d;
uint32_t wr_data; uint32_t wr_data;
uint64_t blt_addr[];
uint64_t blt_data[];
int i, result; int i, result;
...@@ -121,12 +123,20 @@ module main; ...@@ -121,12 +123,20 @@ module main;
#20us; #20us;
init_vme64x_core(acc); init_vme64x_core(acc);
$display("Release FMC0/1 reset\n");
acc.write('h120C, 'h3, A32|SINGLE|D32);
// Enable all interrupts // Enable all interrupts
$display("Enable all interrupts\n"); $display("Enable FMC0 and FMC1 interrupt vectors\n");
acc.write('h1304, 'hF, A32|SINGLE|D32); acc.write('h1308, 'h3, A32|SINGLE|D32);
acc.read('h1308, d, A32|SINGLE|D32); acc.read('h1310, d, A32|SINGLE|D32);
$display("Interrupt mask = 0x%x\n",d); $display("VIC interrupt mask = 0x%x\n",d);
acc.write('h1300, 'h3, A32|SINGLE|D32);
$display("Enable TRIGGER and END_ACQ in FMC0/1 EIC\n");
acc.write('h2000, 'h3, A32|SINGLE|D32);
acc.write('h6000, 'h3, A32|SINGLE|D32);
// Trigger setup (sw trigger) // Trigger setup (sw trigger)
$display("Trigger setup\n"); $display("Trigger setup\n");
...@@ -150,12 +160,35 @@ module main; ...@@ -150,12 +160,35 @@ module main;
$display("Software trigger\n"); $display("Software trigger\n");
acc.write('h5310, 'hFF, A32|SINGLE|D32); acc.write('h5310, 'hFF, A32|SINGLE|D32);
/* /*
// Data "FIFO" test
acc.write('h2200, 'h0, A32|SINGLE|D32);
acc.read('h2200, d, A32|SINGLE|D32);
$display("Read DDR_ADR: 0x%x\n", d);
$display("Write data to DDR in BLT\n");
blt_addr = {'h3000};
blt_data = {'h1, 'h2, 'h3, 'h4, 'h5, 'h6, 'h7, 'h8 ,'h9, 'hA};
acc.writem(blt_addr, blt_data, A32|BLT|D32, result);
acc.write('h2200, 'h0, A32|SINGLE|D32);
acc.read('h2200, d, A32|SINGLE|D32);
$display("Read DDR_ADR: 0x%x\n", d);
$display("Read data from DDR in BLT");
blt_data = {};
acc.readm(blt_addr, blt_data, A32|BLT|D32, result);
for(i=0; i<10; i++)
begin
$display("Data %d: 0x%x\n", i, blt_data[i]);
end
*/
acc.write('h2200, 'h0, A32|SINGLE|D32); acc.write('h2200, 'h0, A32|SINGLE|D32);
for(i=0; i<5; i++) for(i=0; i<5; i++)
begin begin
acc.read('h2100, d, A32|SINGLE|D32); acc.read('h3000, d, A32|SINGLE|D32);
$display("Read %d: 0x%x\n", i, d); $display("Read %d: 0x%x\n", i, d);
end end
...@@ -163,17 +196,17 @@ module main; ...@@ -163,17 +196,17 @@ module main;
for(i=0; i<2; i++) for(i=0; i<2; i++)
begin begin
wr_data = i; wr_data = i;
acc.write('h2100, wr_data, A32|SINGLE|D32); acc.write('h3000, wr_data, A32|SINGLE|D32);
$display("Write %d: 0x%x\n", i, wr_data); $display("Write %d: 0x%x\n", i, wr_data);
end end
acc.write('h2200, 'h0, A32|SINGLE|D32); acc.write('h2200, 'h0, A32|SINGLE|D32);
for(i=0; i<5; i++) for(i=0; i<5; i++)
begin begin
acc.read('h2100, d, A32|SINGLE|D32); acc.read('h3000, d, A32|SINGLE|D32);
$display("Read %d: 0x%x\n", i, d); $display("Read %d: 0x%x\n", i, d);
end end
*/
end end
......
hdl/svec/sim/testbench/svec.do
View file @ 0580effb
...@@ -5,7 +5,8 @@ set NumericStdNoWarnings 1 ...@@ -5,7 +5,8 @@ set NumericStdNoWarnings 1
#view wave #view wave
#view transcript #view transcript
do wave_interrupt.do #do wave_interrupt.do
do wave_ddr.do
radix -hexadecimal radix -hexadecimal
run 50 us run 50 us
......
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