# irq_controller_regs

### IRQ controller registers

Wishbone slave for registers related to IRQ controller

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Multiple interrupt register
3.2. Interrupt sources register
3.3. Interrupt enable mask register

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | Multiple interrupt register | irq_ctrl_multi_irq | MULTI_IRQ
0x1 | REG | Interrupt sources register | irq_ctrl_src | SRC
0x2 | REG | Interrupt enable mask register | irq_ctrl_en_mask | EN_MASK

### 2. HDL symbol

→ | rst_n_i |  | Multiple interrupt register: |
→ | clk_sys_i |  | irq_ctrl_multi_irq_o[31:0] | ⇒
⇒ | wb_adr_i[1:0] |  | irq_ctrl_multi_irq_i[31:0] | ⇐
⇒ | wb_dat_i[31:0] |  | irq_ctrl_multi_irq_load_o | →
⇐ | wb_dat_o[31:0] |  |  |
→ | wb_cyc_i |  | Interrupt sources register : |
⇒ | wb_sel_i[3:0] |  | irq_ctrl_src_o[31:0] | ⇒
→ | wb_stb_i |  | irq_ctrl_src_i[31:0] | ⇐
→ | wb_we_i |  | irq_ctrl_src_load_o | →
← | wb_ack_o |  |  |
← | wb_stall_o |  | Interrupt enable mask register: |
|  |  | irq_ctrl_en_mask_o[31:0] | ⇒

### 3. Register description

### 3.1. Multiple interrupt register

HW prefix: | irq_ctrl_multi_irq
HW address: | 0x0
C prefix: | MULTI_IRQ
C offset: | 0x0

Multiple interrupts occurs before irq source is read.
Write '1' to clear a bit.
Bit 0: FMC slot 1 trigger.
Bit 1: FMC slot 1 acquisition end.
Bit 2: FMC slot 2 trigger.
Bit 3: FMC slot 2 acquisition end.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
MULTI_IRQ[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
MULTI_IRQ[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
MULTI_IRQ[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
MULTI_IRQ[7:0] |  |  |  |  |  |  |

- MULTI_IRQ [read/write]: Multiple interrupt

### 3.2. Interrupt sources register

HW prefix: | irq_ctrl_src
HW address: | 0x1
C prefix: | SRC
C offset: | 0x4

Indicates the interrupt source.
Write '1' to clear a bit.
Bit 0: FMC slot 1 trigger.
Bit 1: FMC slot 1 acquisition end.
Bit 2: FMC slot 2 trigger.
Bit 3: FMC slot 2 acquisition end.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SRC[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SRC[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SRC[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SRC[7:0] |  |  |  |  |  |  |

- SRC [read/write]: Interrupt sources

### 3.3. Interrupt enable mask register

HW prefix: | irq_ctrl_en_mask
HW address: | 0x2
C prefix: | EN_MASK
C offset: | 0x8

Bit mask to independently enable interrupt sources.
Bit 0: FMC slot 1 trigger.
Bit 1: FMC slot 1 acquisition end.
Bit 2: FMC slot 2 trigger.
Bit 3: FMC slot 2 acquisition end.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
EN_MASK[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
EN_MASK[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
EN_MASK[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
EN_MASK[7:0] |  |  |  |  |  |  |

- EN_MASK [read/write]: Interrupt enable mask