# fmc_adc_100Ms_csr

### FMC ADC 100MS/s core registers

Wishbone slave for FMC ADC 100MS/s core

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Control register
3.2. Status register
3.3. Trigger configuration
3.4. Trigger delay
3.5. Software trigger
3.6. Number of shots
3.7. Trigger address register
3.8. Gain calibration register
3.9. Offset calibration register
3.10. Reserved register
3.11. Reserved register
3.12. Reserved register
3.13. Sample rate
3.14. Pre-trigger samples
3.15. Post-trigger samples
3.16. Sample counter
3.17. Solid state relays control for channel 1
3.18. Channel 1 current value
3.19. Solid state relays control for channel 2
3.20. Channel 2 current value
3.21. Solid state relays control for channel 3
3.22. Channel 3 current value
3.23. Solid state relays control for channel 4
3.24. Channel 4 current value

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | Control register | fmc_adc_core_ctl | CTL
0x1 | REG | Status register | fmc_adc_core_sta | STA
0x2 | REG | Trigger configuration | fmc_adc_core_trig_cfg | TRIG_CFG
0x3 | REG | Trigger delay | fmc_adc_core_trig_dly | TRIG_DLY
0x4 | REG | Software trigger | fmc_adc_core_sw_trig | SW_TRIG
0x5 | REG | Number of shots | fmc_adc_core_shots | SHOTS
0x6 | REG | Trigger address register | fmc_adc_core_trig_pos | TRIG_POS
0x7 | REG | Gain calibration register | fmc_adc_core_gain_cal | GAIN_CAL
0x8 | REG | Offset calibration register | fmc_adc_core_offset_cal | OFFSET_CAL
0x9 | REG | Reserved register | fmc_adc_core_reserved_0 | RESERVED_0
0xa | REG | Reserved register | fmc_adc_core_reserved_1 | RESERVED_1
0xb | REG | Reserved register | fmc_adc_core_reserved_2 | RESERVED_2
0xc | REG | Sample rate | fmc_adc_core_sr | SR
0xd | REG | Pre-trigger samples | fmc_adc_core_pre_samples | PRE_SAMPLES
0xe | REG | Post-trigger samples | fmc_adc_core_post_samples | POST_SAMPLES
0xf | REG | Sample counter | fmc_adc_core_samp_cnt | SAMP_CNT
0x10 | REG | Solid state relays control for channel 1 | fmc_adc_core_ch1 | CH1
0x11 | REG | Channel 1 current value | fmc_adc_core_ch1 | CH1
0x12 | REG | Solid state relays control for channel 2 | fmc_adc_core_ch2 | CH2
0x13 | REG | Channel 2 current value | fmc_adc_core_ch2 | CH2
0x14 | REG | Solid state relays control for channel 3 | fmc_adc_core_ch3 | CH3
0x15 | REG | Channel 3 current value | fmc_adc_core_ch3 | CH3
0x16 | REG | Solid state relays control for channel 4 | fmc_adc_core_ch4 | CH4
0x17 | REG | Channel 4 current value | fmc_adc_core_ch4 | CH4

### 2. HDL symbol

→ | rst_n_i |  | Control register: |
→ | wb_clk_i |  | fmc_adc_core_ctl_fsm_cmd_o[1:0] | ⇒
⇒ | wb_addr_i[4:0] |  | fmc_adc_core_ctl_fsm_cmd_wr_o | →
⇒ | wb_data_i[31:0] |  | fmc_adc_core_ctl_fmc_clk_oe_o | →
⇐ | wb_data_o[31:0] |  | fmc_adc_core_ctl_offset_dac_clr_n_o | →
→ | wb_cyc_i |  | fmc_adc_core_ctl_man_bitslip_o | →
⇒ | wb_sel_i[3:0] |  | fmc_adc_core_ctl_test_data_en_o | →
→ | wb_stb_i |  | fmc_adc_core_ctl_trig_led_o | →
→ | wb_we_i |  | fmc_adc_core_ctl_acq_led_o | →
← | wb_ack_o |  | fmc_adc_core_ctl_reserved_o[23:0] | ⇒
→ | fs_clk_i |  |  |
|  |  | Status register: |
|  |  | fmc_adc_core_sta_fsm_i[2:0] | ⇐
|  |  | fmc_adc_core_sta_serdes_pll_i | ←
|  |  | fmc_adc_core_sta_serdes_synced_i | ←
|  |  | fmc_adc_core_sta_reserved_i[26:0] | ⇐
|  |  | Trigger configuration: |
|  |  | fmc_adc_core_trig_cfg_hw_trig_sel_o | →
|  |  | fmc_adc_core_trig_cfg_ext_trig_pol_o | →
|  |  | fmc_adc_core_trig_cfg_hw_trig_en_o | →
|  |  | fmc_adc_core_trig_cfg_sw_trig_en_o | →
|  |  | fmc_adc_core_trig_cfg_int_trig_sel_o[1:0] | ⇒
|  |  | fmc_adc_core_trig_cfg_reserved_o[9:0] | ⇒
|  |  | fmc_adc_core_trig_cfg_int_trig_thres_o[15:0] | ⇒
|  |  | Trigger delay: |
|  |  | fmc_adc_core_trig_dly_o[31:0] | ⇒
|  |  | Software trigger: |
|  |  | fmc_adc_core_sw_trig_o[31:0] | ⇒
|  |  | fmc_adc_core_sw_trig_wr_o | →
|  |  | Number of shots: |
|  |  | fmc_adc_core_shots_nb_o[15:0] | ⇒
|  |  | fmc_adc_core_shots_reserved_o[15:0] | ⇒
|  |  | Trigger address register: |
|  |  | fmc_adc_core_trig_pos_i[31:0] | ⇐
|  |  | Gain calibration register: |
|  |  | fmc_adc_core_gain_cal_o[31:0] | ⇒
|  |  | Offset calibration register: |
|  |  | fmc_adc_core_offset_cal_o[31:0] | ⇒
|  |  | Reserved register: |
|  |  | fmc_adc_core_reserved_0_i[31:0] | ⇐
|  |  | Reserved register: |
|  |  | fmc_adc_core_reserved_1_i[31:0] | ⇐
|  |  | Reserved register: |
|  |  | fmc_adc_core_reserved_2_i[31:0] | ⇐
|  |  | Sample rate: |
|  |  | fmc_adc_core_sr_deci_o[15:0] | ⇒
|  |  | fmc_adc_core_sr_reserved_o[15:0] | ⇒
|  |  | Pre-trigger samples: |
|  |  | fmc_adc_core_pre_samples_o[31:0] | ⇒
|  |  | Post-trigger samples: |
|  |  | fmc_adc_core_post_samples_o[31:0] | ⇒
|  |  | Sample counter: |
|  |  | fmc_adc_core_samp_cnt_i[31:0] | ⇐
|  |  | Solid state relays control for channel 1: |
|  |  | fmc_adc_core_ch1_ssr_o[6:0] | ⇒
|  |  | fmc_adc_core_ch1_reserved_o[24:0] | ⇒
|  |  | Channel 1 current value: |
|  |  | fmc_adc_core_ch1_val_i[15:0] | ⇐
|  |  | fmc_adc_core_ch1_reserved_i[15:0] | ⇐
|  |  | Solid state relays control for channel 2: |
|  |  | fmc_adc_core_ch2_ssr_o[6:0] | ⇒
|  |  | fmc_adc_core_ch2_reserved_o[24:0] | ⇒
|  |  | Channel 2 current value: |
|  |  | fmc_adc_core_ch2_val_i[15:0] | ⇐
|  |  | fmc_adc_core_ch2_reserved_i[15:0] | ⇐
|  |  | Solid state relays control for channel 3: |
|  |  | fmc_adc_core_ch3_ssr_o[6:0] | ⇒
|  |  | fmc_adc_core_ch3_reserved_o[24:0] | ⇒
|  |  | Channel 3 current value: |
|  |  | fmc_adc_core_ch3_val_i[15:0] | ⇐
|  |  | fmc_adc_core_ch3_reserved_i[15:0] | ⇐
|  |  | Solid state relays control for channel 4: |
|  |  | fmc_adc_core_ch4_ssr_o[6:0] | ⇒
|  |  | fmc_adc_core_ch4_reserved_o[24:0] | ⇒
|  |  | Channel 4 current value: |
|  |  | fmc_adc_core_ch4_val_i[15:0] | ⇐
|  |  | fmc_adc_core_ch4_reserved_i[15:0] | ⇐

### 3. Register description

### 3.1. Control register

HW prefix: | fmc_adc_core_ctl
HW address: | 0x0
C prefix: | CTL
C offset: | 0x0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[23:16] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[15:8] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ACQ_LED | TRIG_LED | TEST_DATA_EN | MAN_BITSLIP | OFFSET_DAC_CLR_N | FMC_CLK_OE | FSM_CMD[1:0] |

- FSM_CMD [read/write]: State machine commands
  1: start
  2: stop
- FMC_CLK_OE [read/write]: FMC Si750 output enable
- OFFSET_DAC_CLR_N [read/write]: Offset DACs clear (active low)
- MAN_BITSLIP [write-only]: Manual serdes bitslip
- TEST_DATA_EN [read/write]: Enable test data
  Write the address counter value instead of ADC data to DDR
- TRIG_LED [read/write]: Manual TRIG LED
  Manual control of the front panel TRIG LED
- ACQ_LED [read/write]: Manual ACQ LED
  Manual control of the front panel ACQ LED
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's

### 3.2. Status register

HW prefix: | fmc_adc_core_sta
HW address: | 0x1
C prefix: | STA
C offset: | 0x4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[26:19] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[18:11] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[10:3] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[2:0] | SERDES_SYNCED | SERDES_PLL | FSM[2:0] |  |  |  |

- FSM [read-only]: State machine status
  States:
  1: IDLE
  2: PRE_TRIG
  3: WAIT_TRIG
  4: POST_TRIG
  5: DECR_SHOT
  7: Illegal
- SERDES_PLL [read-only]: SerDes PLL status
- SERDES_SYNCED [read-only]: SerDes synchronization status
  0: bitslip in progress
  1: serdes synchronized
- RESERVED [read-only]: Reserved
  Ignore on read, write with 0's

### 3.3. Trigger configuration

HW prefix: | fmc_adc_core_trig_cfg
HW address: | 0x2
C prefix: | TRIG_CFG
C offset: | 0x8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
INT_TRIG_THRES[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
INT_TRIG_THRES[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[9:2] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[1:0] | INT_TRIG_SEL[1:0] | SW_TRIG_EN | HW_TRIG_EN | EXT_TRIG_POL | HW_TRIG_SEL |  |

- HW_TRIG_SEL [read/write]: Hardware trigger selection
  0: internal (data threshold)
  1: external (front panel trigger input)
- EXT_TRIG_POL [read/write]: External hardware trigger polarity
  0: positive edge
  1: negative edge
- HW_TRIG_EN [read/write]: Hardware trigger enable
  0: disable
  1: enable
- SW_TRIG_EN [read/write]: Software trigger enable
  0: disable
  1: enable
- INT_TRIG_SEL [read/write]: Channel selection for internal trigger
  00: channel 1
  01: channel 2
  10: channel 3
  11: channel 4
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's
- INT_TRIG_THRES [read/write]: Threshold for internal trigger
  Treated as two's complement and compared to raw ADC data

### 3.4. Trigger delay

HW prefix: | fmc_adc_core_trig_dly
HW address: | 0x3
C prefix: | TRIG_DLY
C offset: | 0xc

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRIG_DLY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TRIG_DLY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TRIG_DLY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TRIG_DLY[7:0] |  |  |  |  |  |  |

- TRIG_DLY [read/write]: Trigger delay value
  Delay to apply on the trigger in sampling clock ticks

### 3.5. Software trigger

HW prefix: | fmc_adc_core_sw_trig
HW address: | 0x4
C prefix: | SW_TRIG
C offset: | 0x10

Writing (anything) to this register generates a software trigger

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SW_TRIG[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SW_TRIG[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SW_TRIG[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SW_TRIG[7:0] |  |  |  |  |  |  |

- SW_TRIG [write-only]: Software trigger

### 3.6. Number of shots

HW prefix: | fmc_adc_core_shots
HW address: | 0x5
C prefix: | SHOTS
C offset: | 0x14

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NB[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NB[7:0] |  |  |  |  |  |  |

- NB [read/write]: Number of shots
  Number of shots required in multi-shot mode, set to one for single-shot mode
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's

### 3.7. Trigger address register

HW prefix: | fmc_adc_core_trig_pos
HW address: | 0x6
C prefix: | TRIG_POS
C offset: | 0x18

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRIG_POS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TRIG_POS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TRIG_POS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TRIG_POS[7:0] |  |  |  |  |  |  |

- TRIG_POS [read-only]: Trigger address
  Trigger address in DDR memory.
  Only used in single-shot mode

### 3.8. Gain calibration register

HW prefix: | fmc_adc_core_gain_cal
HW address: | 0x7
C prefix: | GAIN_CAL
C offset: | 0x1c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
GAIN_CAL[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
GAIN_CAL[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
GAIN_CAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
GAIN_CAL[7:0] |  |  |  |  |  |  |

- GAIN_CAL [read/write]: Gain calibration
  Gain applied to all data coming from the ADC.

### 3.9. Offset calibration register

HW prefix: | fmc_adc_core_offset_cal
HW address: | 0x8
C prefix: | OFFSET_CAL
C offset: | 0x20

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
OFFSET_CAL[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
OFFSET_CAL[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
OFFSET_CAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
OFFSET_CAL[7:0] |  |  |  |  |  |  |

- OFFSET_CAL [read/write]: Offset calibration
  Offset applied to all data coming from the ADC.

### 3.10. Reserved register

HW prefix: | fmc_adc_core_reserved_0
HW address: | 0x9
C prefix: | RESERVED_0
C offset: | 0x24

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED_0[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED_0[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_0[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_0[7:0] |  |  |  |  |  |  |

- RESERVED_0 [read-only]: Reserved
  Ignore on read, write with 0's

### 3.11. Reserved register

HW prefix: | fmc_adc_core_reserved_1
HW address: | 0xa
C prefix: | RESERVED_1
C offset: | 0x28

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED_1[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED_1[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_1[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_1[7:0] |  |  |  |  |  |  |

- RESERVED_1 [read-only]: Reserved
  Ignore on read, write with 0's

### 3.12. Reserved register

HW prefix: | fmc_adc_core_reserved_2
HW address: | 0xb
C prefix: | RESERVED_2
C offset: | 0x2c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED_2[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED_2[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_2[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_2[7:0] |  |  |  |  |  |  |

- RESERVED_2 [read-only]: Reserved
  Ignore on read, write with 0's

### 3.13. Sample rate

HW prefix: | fmc_adc_core_sr
HW address: | 0xc
C prefix: | SR
C offset: | 0x30

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
DECI[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DECI[7:0] |  |  |  |  |  |  |

- DECI [read/write]: Sample rate decimation
  Decimation factor
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's

### 3.14. Pre-trigger samples

HW prefix: | fmc_adc_core_pre_samples
HW address: | 0xd
C prefix: | PRE_SAMPLES
C offset: | 0x34

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
PRE_SAMPLES[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
PRE_SAMPLES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PRE_SAMPLES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PRE_SAMPLES[7:0] |  |  |  |  |  |  |

- PRE_SAMPLES [read/write]: Pre-trigger samples
  Number of requested pre-trigger samples

### 3.15. Post-trigger samples

HW prefix: | fmc_adc_core_post_samples
HW address: | 0xe
C prefix: | POST_SAMPLES
C offset: | 0x38

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
POST_SAMPLES[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
POST_SAMPLES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
POST_SAMPLES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
POST_SAMPLES[7:0] |  |  |  |  |  |  |

- POST_SAMPLES [read/write]: Post-trigger samples
  Number of requested post-trigger samples

### 3.16. Sample counter

HW prefix: | fmc_adc_core_samp_cnt
HW address: | 0xf
C prefix: | SAMP_CNT
C offset: | 0x3c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SAMP_CNT[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SAMP_CNT[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SAMP_CNT[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SAMP_CNT[7:0] |  |  |  |  |  |  |

- SAMP_CNT [read-only]: Sample counter
  Counts the number of sample.
  It is reset on START and then counts the number of pre-trigger + post-trigger samples

### 3.17. Solid state relays control for channel 1

HW prefix: | fmc_adc_core_ch1
HW address: | 0x10
C prefix: | CH1
C offset: | 0x40

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[24:17] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[16:9] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[8:1] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[0:0] | SSR[6:0] |  |  |  |  |  |

- SSR [read/write]: Solid state relays control for channel 1
  Controls input voltage range, termination and DC offset error calibration
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's

### 3.18. Channel 1 current value

HW prefix: | fmc_adc_core_ch1
HW address: | 0x11
C prefix: | CH1
C offset: | 0x44

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 1 current value
  Current ADC raw value
- RESERVED [read-only]: Reserved
  Ignore on read, write with 0's

### 3.19. Solid state relays control for channel 2

HW prefix: | fmc_adc_core_ch2
HW address: | 0x12
C prefix: | CH2
C offset: | 0x48

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[24:17] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[16:9] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[8:1] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[0:0] | SSR[6:0] |  |  |  |  |  |

- SSR [read/write]: Solid state relays control for channel 2
  Controls input voltage range, termination and DC offset error calibration
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's

### 3.20. Channel 2 current value

HW prefix: | fmc_adc_core_ch2
HW address: | 0x13
C prefix: | CH2
C offset: | 0x4c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 2 current value
  Current ADC raw value
- RESERVED [read-only]: Reserved
  Ignore on read, write with 0's

### 3.21. Solid state relays control for channel 3

HW prefix: | fmc_adc_core_ch3
HW address: | 0x14
C prefix: | CH3
C offset: | 0x50

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[24:17] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[16:9] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[8:1] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[0:0] | SSR[6:0] |  |  |  |  |  |

- SSR [read/write]: Solid state relays control for channel 3
  Controls input voltage range, termination and DC offset error calibration
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's

### 3.22. Channel 3 current value

HW prefix: | fmc_adc_core_ch3
HW address: | 0x15
C prefix: | CH3
C offset: | 0x54

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 3 current value
  Current ADC raw value
- RESERVED [read-only]: Reserved
  Ignore on read, write with 0's

### 3.23. Solid state relays control for channel 4

HW prefix: | fmc_adc_core_ch4
HW address: | 0x16
C prefix: | CH4
C offset: | 0x58

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[24:17] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[16:9] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[8:1] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[0:0] | SSR[6:0] |  |  |  |  |  |

- SSR [read/write]: Solid state relays control for channel 4
  Controls input voltage range, termination and DC offset error calibration
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's

### 3.24. Channel 4 current value

HW prefix: | fmc_adc_core_ch4
HW address: | 0x17
C prefix: | CH4
C offset: | 0x5c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 4 current value
  Current ADC raw value
- RESERVED [read-only]: Reserved
  Ignore on read, write with 0's