# carrier_csr

### SVEC carrier control and status registers

Wishbone slave for control and status registers related to the SVEC FMC carrier

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Carrier type and PCB version
3.2. Status
3.3. Control
3.4. Reset Register

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | Carrier type and PCB version | carrier_csr_carrier | CARRIER
0x1 | REG | Status | carrier_csr_stat | STAT
0x2 | REG | Control | carrier_csr_ctrl | CTRL
0x3 | REG | Reset Register | carrier_csr_rst | RST

### 2. HDL symbol

→ | rst_n_i |  | Carrier type and PCB version: |
→ | clk_sys_i |  | carrier_csr_carrier_pcb_rev_i[4:0] | ⇐
⇒ | wb_adr_i[1:0] |  | carrier_csr_carrier_reserved_i[10:0] | ⇐
⇒ | wb_dat_i[31:0] |  | carrier_csr_carrier_type_i[15:0] | ⇐
⇐ | wb_dat_o[31:0] |  |  |
→ | wb_cyc_i |  | Status: |
⇒ | wb_sel_i[3:0] |  | carrier_csr_stat_fmc0_pres_i | ←
→ | wb_stb_i |  | carrier_csr_stat_fmc1_pres_i | ←
→ | wb_we_i |  | carrier_csr_stat_sys_pll_lck_i | ←
← | wb_ack_o |  | carrier_csr_stat_ddr0_cal_done_i | ←
← | wb_stall_o |  | carrier_csr_stat_ddr1_cal_done_i | ←
|  |  | carrier_csr_stat_reserved_i[26:0] | ⇐
|  |  | Control: |
|  |  | carrier_csr_ctrl_fp_leds_man_o[15:0] | ⇒
|  |  | carrier_csr_ctrl_reserved_o[15:0] | ⇒
|  |  | Reset Register: |
|  |  | carrier_csr_rst_fmc0_n_o | →
|  |  | carrier_csr_rst_fmc1_n_o | →
|  |  | carrier_csr_rst_reserved_o[29:0] | ⇒

### 3. Register description

### 3.1. Carrier type and PCB version

HW prefix: | carrier_csr_carrier
HW address: | 0x0
C prefix: | CARRIER
C offset: | 0x0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TYPE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TYPE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[10:3] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[2:0] | PCB_REV[4:0] |  |  |  |  |  |

- PCB_REV [read-only]: PCB revision
  Binary coded PCB layout revision.
- RESERVED [read-only]: Reserved register
  Ignore on read, write with 0's.
- TYPE [read-only]: Carrier type
  Carrier type identifier
  1 = SPEC
  2 = SVEC
  3 = VFC
  4 = SPEXI

### 3.2. Status

HW prefix: | carrier_csr_stat
HW address: | 0x1
C prefix: | STAT
C offset: | 0x4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[26:19] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[18:11] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[10:3] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[2:0] | DDR1_CAL_DONE | DDR0_CAL_DONE | SYS_PLL_LCK | FMC1_PRES | FMC0_PRES |  |

- FMC0_PRES [read-only]: FMC 1 presence
  0: FMC slot 1 is populated
  1: FMC slot 1 is not populated.
- FMC1_PRES [read-only]: FMC 2 presence
  0: FMC slot 2 is populated
  1: FMC slot 2 is not populated.
- SYS_PLL_LCK [read-only]: System clock PLL status
  0: not locked
  1: locked.
- DDR0_CAL_DONE [read-only]: DDR3 bank 4 calibration status
  0: not done
  1: done.
- DDR1_CAL_DONE [read-only]: DDR3 bank 5 calibration status
  0: not done
  1: done.
- RESERVED [read-only]: Reserved
  Ignore on read, write with 0's.

### 3.3. Control

HW prefix: | carrier_csr_ctrl
HW address: | 0x2
C prefix: | CTRL
C offset: | 0x8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
FP_LEDS_MAN[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
FP_LEDS_MAN[7:0] |  |  |  |  |  |  |

- FP_LEDS_MAN [read/write]: Front panel LED manual control
  Height front panel LED, two bits per LED.
  00 = OFF
  01 = Green
  10 = Red
  11 = Orange
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's

### 3.4. Reset Register

HW prefix: | carrier_csr_rst
HW address: | 0x3
C prefix: | RST
C offset: | 0xc

Controls software reset of the mezzanines including the ddr interface and the time-tagging core.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[29:22] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[21:14] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[13:6] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[5:0] | FMC1_N | FMC0_N |  |  |  |  |

- FMC0_N [read/write]: State of the FMC 1 reset line
  write 0: FMC is held in reset
  write 1: Normal FMC operation
- FMC1_N [read/write]: State of the FMC 2 reset line
  write 0: FMC is held in reset
  write 1: Normal FMC operation
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's