
- Remove carrier SPI master -> shift other slaves base addresses.
- Add WR core
    1)for time-tags
    2)for sampling clock control
- Remove mutli-irq register from interrupt controller.
    -> perhaps add counters instead
- Update interface of wbgen2 generated cores (name change).
- Remove unused 250MHz clock signals, buffer
- Unify address inferfaces: put all in bytes (wishbone addr, trig pointer, ...)
    -> Change GN4142-core WB bus(es) to byte address.
    -> Change DDR-core WB bus(es) to byte address??
- Add error flags (interrupt?): - instead of overwriting memory for a given acquisition.
                                - if read during acquisition (or even block read during acq?).
- Rename decimation (and "sample rate" register) in under-sampling.
- Use 200MHz clock for WB from ddr-ctrl to gn4124-core.
- Clean-up adc core WB interface to DDR -> use only one clk (=> sys_clk)
- Replace all Xilinx FIFO by generic ones from general-cores lib (! last time I tried, it broke the DMA.).
- License header in every file -> check
- Take data for threshold trigger after offset/gain correction.
- Rename UTC core in time-tagging core or something like that.
- Test sampling clocks from 10MHz to 105MHz.
- Add sampling clock presence flag. Or better a sampling clock frequence register.
- Over-heat and input over-load interrupts??
- Time-tag for every trigger in multi-shot.
- Review reset logic.
- Add Etherbone.
- End acq interrupt generation after a acq stop command ???
- Remove huge files from git repo.
- Make the project ucfgen friendly (if anything has to be done, not sure).
- Include the git tree in a .tar.gz along with the .bin file (in the files section) for each release.
- Remove meta-info field in time-tags?
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