# wb_slave_vic

### Vectored Interrupt Controller (VIC)

Module implementing a 2 to 32-input prioritized interrupt controller with internal interrupt vector storage support.

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. VIC Control Register
3.2. Raw Interrupt Status Register
3.3. Interrupt Enable Register
3.4. Interrupt Disable Register
3.5. Interrupt Mask Register
3.6. Vector Address Register
3.7. Software Interrupt Register
3.8. End Of Interrupt Acknowledge Register
4. Memory blocks
4.1. Interrupt Vector Table

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | VIC Control Register | vic_ctl | CTL
0x1 | REG | Raw Interrupt Status Register | vic_risr | RISR
0x2 | REG | Interrupt Enable Register | vic_ier | IER
0x3 | REG | Interrupt Disable Register | vic_idr | IDR
0x4 | REG | Interrupt Mask Register | vic_imr | IMR
0x5 | REG | Vector Address Register | vic_var | VAR
0x6 | REG | Software Interrupt Register | vic_swir | SWIR
0x7 | REG | End Of Interrupt Acknowledge Register | vic_eoir | EOIR
0x20 - 0x3f | MEM | Interrupt Vector Table | vic_ivt_ram | IVT_RAM

### 2. HDL symbol

→ | rst_n_i |  | VIC Control Register: |
→ | clk_sys_i |  | vic_ctl_enable_o | →
⇒ | wb_adr_i[5:0] |  | vic_ctl_pol_o | →
⇒ | wb_dat_i[31:0] |  | vic_ctl_emu_edge_o | →
⇐ | wb_dat_o[31:0] |  | vic_ctl_emu_len_o[15:0] | ⇒
→ | wb_cyc_i |  |  |
⇒ | wb_sel_i[3:0] |  | Raw Interrupt Status Register: |
→ | wb_stb_i |  | vic_risr_i[31:0] | ⇐
→ | wb_we_i |  |  |
← | wb_ack_o |  | Interrupt Enable Register: |
← | wb_stall_o |  | vic_ier_o[31:0] | ⇒
|  |  | vic_ier_wr_o | →
|  |  | Interrupt Disable Register: |
|  |  | vic_idr_o[31:0] | ⇒
|  |  | vic_idr_wr_o | →
|  |  | Interrupt Mask Register: |
|  |  | vic_imr_i[31:0] | ⇐
|  |  | Vector Address Register: |
|  |  | vic_var_i[31:0] | ⇐
|  |  | Software Interrupt Register: |
|  |  | vic_swir_o[31:0] | ⇒
|  |  | vic_swir_wr_o | →
|  |  | End Of Interrupt Acknowledge Register: |
|  |  | vic_eoir_o[31:0] | ⇒
|  |  | vic_eoir_wr_o | →
|  |  | Interrupt Vector Table: |
|  |  | vic_ivt_ram_addr_i[4:0] | ⇐
|  |  | vic_ivt_ram_data_o[31:0] | ⇒
|  |  | vic_ivt_ram_rd_i | ←

### 3. Register description

### 3.1. VIC Control Register

HW prefix: | vic_ctl
HW address: | 0x0
C prefix: | CTL
C offset: | 0x0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | EMU_LEN[15:13] |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
EMU_LEN[12:5] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
EMU_LEN[4:0] | EMU_EDGE | POL | ENABLE |  |  |  |

- ENABLE [read/write]: VIC Enable
  - 1: enables VIC operation
  - 0: disables VIC operation
- POL [read/write]: VIC output polarity
  - 1: IRQ output is active high
  - 0: IRQ output is active low
- EMU_EDGE [read/write]: Emulate Edge sensitive output
  - 1: Forces a low pulse of `EMU_LEN` clock cycles at each write to `EOIR`. Useful for edge-only IRQ controllers such as Gennum.
  - 0: Normal IRQ master line behavior
- EMU_LEN [read/write]: Emulated Edge pulse timer
  Length of the delay (in `clk_sys_i` cycles) between write to `EOIR` and re-assertion of `irq_master_o`.

### 3.2. Raw Interrupt Status Register

HW prefix: | vic_risr
HW address: | 0x1
C prefix: | RISR
C offset: | 0x4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RISR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RISR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RISR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RISR[7:0] |  |  |  |  |  |  |

- RISR [read-only]: Raw interrupt status
  Each bit reflects the current state of corresponding IRQ input line.
  - read 1: interrupt line is currently active
  - read 0: interrupt line is inactive

### 3.3. Interrupt Enable Register

HW prefix: | vic_ier
HW address: | 0x2
C prefix: | IER
C offset: | 0x8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
IER[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
IER[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
IER[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
IER[7:0] |  |  |  |  |  |  |

- IER [write-only]: Enable IRQ
  - write 1: enables interrupt associated with written bit
  - write 0: no effect

### 3.4. Interrupt Disable Register

HW prefix: | vic_idr
HW address: | 0x3
C prefix: | IDR
C offset: | 0xc

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
IDR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
IDR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
IDR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
IDR[7:0] |  |  |  |  |  |  |

- IDR [write-only]: Disable IRQ
  - write 1: enables interrupt associated with written bit
  - write 0: no effect

### 3.5. Interrupt Mask Register

HW prefix: | vic_imr
HW address: | 0x4
C prefix: | IMR
C offset: | 0x10

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
IMR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
IMR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
IMR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
IMR[7:0] |  |  |  |  |  |  |

- IMR [read-only]: IRQ disabled/enabled
  - read 1: interrupt associated with read bit is enabled
  - read 0: interrupt is disabled

### 3.6. Vector Address Register

HW prefix: | vic_var
HW address: | 0x5
C prefix: | VAR
C offset: | 0x14

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
VAR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
VAR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAR[7:0] |  |  |  |  |  |  |

- VAR [read-only]: Vector Address
  Address of pending interrupt vector, read from Interrupt Vector Table

### 3.7. Software Interrupt Register

HW prefix: | vic_swir
HW address: | 0x6
C prefix: | SWIR
C offset: | 0x18

Writing 1 to one of bits of this register causes a software emulation of the respective interrupt.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SWIR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SWIR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SWIR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SWIR[7:0] |  |  |  |  |  |  |

- SWIR [write-only]: SWI interrupt mask

### 3.8. End Of Interrupt Acknowledge Register

HW prefix: | vic_eoir
HW address: | 0x7
C prefix: | EOIR
C offset: | 0x1c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
EOIR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
EOIR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
EOIR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
EOIR[7:0] |  |  |  |  |  |  |

- EOIR [write-only]: End of Interrupt
  Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s) or releases the master interrupt output.

### 4.1. Interrupt Vector Table

HW prefix: | vic_ivt_ram
HW address: | 0x20
C prefix: | IVT_RAM
C offset: | 0x80
Size: | 32 32-bit words
Data width: | 32
Access (bus): | read/write
Access (device): | read-only
Mirrored: | no
Byte-addressable: | no
Peripheral port: | bus-synchronous

⇒ | vic_ivt_ram_addr_i[4:0] |  |  |
⇐ | vic_ivt_ram_data_o[31:0] |  |  |
→ | vic_ivt_ram_rd_i |  |  |

Vector Address Table. Word at offset N stores the vector address of IRQ N. When interrupt is requested, VIC reads it's vector address from this memory and stores it in VAR register. The contents of this table can be pre-initialized during synthesis through `g_init_vectors` generic parameter. This is used to auto-enumerate interrupts in SDB-based designs.