diff --git a/FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc b/FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc
index 11ce94c01db2d111e637f8b61fce96158fa5367d..1f7079d120b44989b5e562bd25c2c5158957cf72 100644
--- a/FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc
+++ b/FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc
@@ -19,11 +19,6 @@ set_property IOSTANDARD LVCMOS18 [get_ports eeprom_scl]
set_property IOSTANDARD LVCMOS18 [get_ports eeprom_sda]
set_property SLEW FAST [get_ports eeprom_scl]
set_property SLEW FAST [get_ports eeprom_sda]
-set_property PACKAGE_PIN AD20 [get_ports fmcx_scl]
-set_property PACKAGE_PIN AD21 [get_ports fmcx_sda]
-set_property IOSTANDARD LVCMOS25 [get_ports fmcx_scl]
-set_property IOSTANDARD LVCMOS25 [get_ports fmcx_sda]
-set_property SLEW FAST [get_ports fmcx_sda]
## FMC1 positive (differential)
# 4 lines per pin, all but PACKAGE_PIN can be grouped though
@@ -273,8 +268,8 @@ set_property PACKAGE_PIN AC24 [get_ports {dig_outs_i[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dig_outs_i[3]}]
set_property PACKAGE_PIN W14 [get_ports dig_out5_n]
set_property IOSTANDARD LVCMOS25 [get_ports dig_out5_n]
-set_property PACKAGE_PIN W17 [get_ports dig_out6_n]
-set_property IOSTANDARD LVCMOS25 [get_ports dig_out6_n]
+set_property PACKAGE_PIN W17 [get_ports {dig_out6_n[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {dig_out6_n[0]}]
set_property PACKAGE_PIN W16 [get_ports dig_in2_i]
set_property IOSTANDARD LVCMOS25 [get_ports dig_in2_i]
set_property PACKAGE_PIN AE20 [get_ports dig_in3_n_i]
@@ -352,3 +347,8 @@ set_property ASYNC_REG true [get_cells system_design_i/wrc_1p_kintex7_0/U0/U_GTP
set_clock_groups -asynchronous -group [get_clocks I_1] -group [get_clocks wr_125M_sfp]
set_false_path -from [get_clocks clk_fpga_1] -to [get_clocks I_1]
set_false_path -from [get_clocks cmp_dmtd_clk_pll_n_4] -to [get_clocks I_1]
+
+set_property PACKAGE_PIN AD20 [get_ports i2c_master_fmcx_scl_io]
+set_property PACKAGE_PIN AD21 [get_ports i2c_master_fmcx_sda_io]
+set_property IOSTANDARD LVCMOS25 [get_ports i2c_master_fmcx_scl_io]
+set_property IOSTANDARD LVCMOS25 [get_ports i2c_master_fmcx_sda_io]
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef
index 6054691335c453ce11b209c33da828b63213d0d2..ac89b4d3f784dcfbd5d2b04f86df2cd32795c493 100644
Binary files a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef and b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef differ
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
index 56688d53849dbaf9c20b5df88c9a48e21a062986..113209b10dd6560d28fdc1a97d44787cbb245737 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
@@ -1,7 +1,7 @@
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
---Date : Wed Oct 11 14:50:45 2017
+--Date : Wed Oct 11 14:54:59 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.2
--Command : generate_target system_design.bd
--Design : system_design
@@ -3621,8 +3621,6 @@ entity system_design is
dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
eeprom_scl : inout STD_LOGIC;
eeprom_sda : inout STD_LOGIC;
- fmcx_scl : inout STD_LOGIC;
- fmcx_sda : inout STD_LOGIC;
gtp0_rate_select_b : inout STD_LOGIC;
gtp_dedicated_clk_n_i : in STD_LOGIC;
gtp_dedicated_clk_p_i : in STD_LOGIC;
@@ -3636,6 +3634,12 @@ entity system_design is
gtp_wr_tx_fault : in STD_LOGIC;
gtp_wr_txn : out STD_LOGIC;
gtp_wr_txp : out STD_LOGIC;
+ i2c_master_fmcx_scl_i : in STD_LOGIC;
+ i2c_master_fmcx_scl_o : out STD_LOGIC;
+ i2c_master_fmcx_scl_t : out STD_LOGIC;
+ i2c_master_fmcx_sda_i : in STD_LOGIC;
+ i2c_master_fmcx_sda_o : out STD_LOGIC;
+ i2c_master_fmcx_sda_t : out STD_LOGIC;
led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_line_en_pl_o : out STD_LOGIC;
led_line_pl_o : out STD_LOGIC;
@@ -4205,8 +4209,6 @@ architecture STRUCTURE of system_design is
signal FMC2_CLK0M2C_N_i_1 : STD_LOGIC;
signal FMC2_CLK0M2C_P_i_1 : STD_LOGIC;
signal FMC2_PRSNTM2C_n_i_1 : STD_LOGIC;
- signal Net : STD_LOGIC;
- signal Net1 : STD_LOGIC;
signal Net10 : STD_LOGIC;
signal Net11 : STD_LOGIC;
signal Net2 : STD_LOGIC;
@@ -4325,6 +4327,12 @@ architecture STRUCTURE of system_design is
signal axi_uartlite_0_tx : STD_LOGIC;
signal axi_wb_i2c_master_0_axi_int_o : STD_LOGIC;
signal axi_wb_i2c_master_2_axi_int_o : STD_LOGIC;
+ signal axi_wb_i2c_master_2_i2c_master_SCL_I : STD_LOGIC;
+ signal axi_wb_i2c_master_2_i2c_master_SCL_O : STD_LOGIC;
+ signal axi_wb_i2c_master_2_i2c_master_SCL_T : STD_LOGIC;
+ signal axi_wb_i2c_master_2_i2c_master_SDA_I : STD_LOGIC;
+ signal axi_wb_i2c_master_2_i2c_master_SDA_O : STD_LOGIC;
+ signal axi_wb_i2c_master_2_i2c_master_SDA_T : STD_LOGIC;
signal clk_25m_vcxo_i_1 : STD_LOGIC;
signal dig_in1_i_1 : STD_LOGIC;
signal dig_in2_i_1 : STD_LOGIC;
@@ -4575,10 +4583,6 @@ architecture STRUCTURE of system_design is
signal NLW_axi_wb_i2c_master_0_i2c_scl_t_UNCONNECTED : STD_LOGIC;
signal NLW_axi_wb_i2c_master_0_i2c_sda_o_UNCONNECTED : STD_LOGIC;
signal NLW_axi_wb_i2c_master_0_i2c_sda_t_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_wb_i2c_master_2_i2c_scl_o_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_wb_i2c_master_2_i2c_scl_t_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_wb_i2c_master_2_i2c_sda_o_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_wb_i2c_master_2_i2c_sda_t_UNCONNECTED : STD_LOGIC;
signal NLW_fasec_hwtest_0_FMC1_GP3_b_UNCONNECTED : STD_LOGIC;
signal NLW_fasec_hwtest_0_FMC2_GP3_b_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
@@ -4649,6 +4653,8 @@ begin
Vaux9_1_V_P <= Vaux9_v_p;
Vp_Vn_1_V_N <= Vp_Vn_v_n;
Vp_Vn_1_V_P <= Vp_Vn_v_p;
+ axi_wb_i2c_master_2_i2c_master_SCL_I <= i2c_master_fmcx_scl_i;
+ axi_wb_i2c_master_2_i2c_master_SDA_I <= i2c_master_fmcx_sda_i;
clk_25m_vcxo_i_1 <= clk_25m_vcxo_i;
dac_cs1_n_o <= wrc_1p_kintex7_0_dac_cs1_n_o;
dac_cs2_n_o <= wrc_1p_kintex7_0_dac_cs2_n_o;
@@ -4666,6 +4672,10 @@ begin
gtp_wr_tx_disable <= wrc_1p_kintex7_0_gtp_wr_TX_DISABLE;
gtp_wr_txn <= wrc_1p_kintex7_0_gtp_wr_TXN;
gtp_wr_txp <= wrc_1p_kintex7_0_gtp_wr_TXP;
+ i2c_master_fmcx_scl_o <= axi_wb_i2c_master_2_i2c_master_SCL_O;
+ i2c_master_fmcx_scl_t <= axi_wb_i2c_master_2_i2c_master_SCL_T;
+ i2c_master_fmcx_sda_o <= axi_wb_i2c_master_2_i2c_master_SDA_O;
+ i2c_master_fmcx_sda_t <= axi_wb_i2c_master_2_i2c_master_SDA_T;
led_col_pl_o(3 downto 0) <= fasec_hwtest_0_led_col_pl_o(3 downto 0);
led_line_en_pl_o <= fasec_hwtest_0_led_line_en_pl_o;
led_line_pl_o <= fasec_hwtest_0_led_line_pl_o;
@@ -4890,12 +4900,12 @@ axi_wb_i2c_master_0: component system_design_axi_wb_i2c_master_0_1
axi_wb_i2c_master_2: component system_design_axi_wb_i2c_master_2_0
port map (
axi_int_o => axi_wb_i2c_master_2_axi_int_o,
- i2c_scl_i => '0',
- i2c_scl_o => NLW_axi_wb_i2c_master_2_i2c_scl_o_UNCONNECTED,
- i2c_scl_t => NLW_axi_wb_i2c_master_2_i2c_scl_t_UNCONNECTED,
- i2c_sda_i => '0',
- i2c_sda_o => NLW_axi_wb_i2c_master_2_i2c_sda_o_UNCONNECTED,
- i2c_sda_t => NLW_axi_wb_i2c_master_2_i2c_sda_t_UNCONNECTED,
+ i2c_scl_i => axi_wb_i2c_master_2_i2c_master_SCL_I,
+ i2c_scl_o => axi_wb_i2c_master_2_i2c_master_SCL_O,
+ i2c_scl_t => axi_wb_i2c_master_2_i2c_master_SCL_T,
+ i2c_sda_i => axi_wb_i2c_master_2_i2c_master_SDA_I,
+ i2c_sda_o => axi_wb_i2c_master_2_i2c_master_SDA_O,
+ i2c_sda_t => axi_wb_i2c_master_2_i2c_master_SDA_T,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
index 8c5533a9503dae69061666e785b63cd642bf390b..a7e17e51667181bcd8be5857fcd7c0a4816717df 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
@@ -1,7 +1,7 @@
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
---Date : Wed Oct 11 14:50:46 2017
+--Date : Wed Oct 11 14:54:59 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.2
--Command : generate_target system_design_wrapper.bd
--Design : system_design_wrapper
@@ -76,8 +76,6 @@ entity system_design_wrapper is
dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
eeprom_scl : inout STD_LOGIC;
eeprom_sda : inout STD_LOGIC;
- fmcx_scl : inout STD_LOGIC;
- fmcx_sda : inout STD_LOGIC;
gtp0_rate_select_b : inout STD_LOGIC;
gtp_dedicated_clk_n_i : in STD_LOGIC;
gtp_dedicated_clk_p_i : in STD_LOGIC;
@@ -91,6 +89,8 @@ entity system_design_wrapper is
gtp_wr_tx_fault : in STD_LOGIC;
gtp_wr_txn : out STD_LOGIC;
gtp_wr_txp : out STD_LOGIC;
+ i2c_master_fmcx_scl_io : inout STD_LOGIC;
+ i2c_master_fmcx_sda_io : inout STD_LOGIC;
led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_line_en_pl_o : out STD_LOGIC;
led_line_pl_o : out STD_LOGIC;
@@ -153,8 +153,6 @@ architecture STRUCTURE of system_design_wrapper is
led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_line_en_pl_o : out STD_LOGIC;
led_line_pl_o : out STD_LOGIC;
- fmcx_scl : inout STD_LOGIC;
- fmcx_sda : inout STD_LOGIC;
FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
@@ -188,10 +186,44 @@ architecture STRUCTURE of system_design_wrapper is
eeprom_sda : inout STD_LOGIC;
gtp_dedicated_clk_p_i : in STD_LOGIC;
gtp_dedicated_clk_n_i : in STD_LOGIC;
- dig_out6_n : out STD_LOGIC_VECTOR ( 0 to 0 )
+ dig_out6_n : out STD_LOGIC_VECTOR ( 0 to 0 );
+ i2c_master_fmcx_scl_i : in STD_LOGIC;
+ i2c_master_fmcx_scl_o : out STD_LOGIC;
+ i2c_master_fmcx_scl_t : out STD_LOGIC;
+ i2c_master_fmcx_sda_o : out STD_LOGIC;
+ i2c_master_fmcx_sda_i : in STD_LOGIC;
+ i2c_master_fmcx_sda_t : out STD_LOGIC
);
end component system_design;
+ component IOBUF is
+ port (
+ I : in STD_LOGIC;
+ O : out STD_LOGIC;
+ T : in STD_LOGIC;
+ IO : inout STD_LOGIC
+ );
+ end component IOBUF;
+ signal i2c_master_fmcx_scl_i : STD_LOGIC;
+ signal i2c_master_fmcx_scl_o : STD_LOGIC;
+ signal i2c_master_fmcx_scl_t : STD_LOGIC;
+ signal i2c_master_fmcx_sda_i : STD_LOGIC;
+ signal i2c_master_fmcx_sda_o : STD_LOGIC;
+ signal i2c_master_fmcx_sda_t : STD_LOGIC;
begin
+i2c_master_fmcx_scl_iobuf: component IOBUF
+ port map (
+ I => i2c_master_fmcx_scl_o,
+ IO => i2c_master_fmcx_scl_io,
+ O => i2c_master_fmcx_scl_i,
+ T => i2c_master_fmcx_scl_t
+ );
+i2c_master_fmcx_sda_iobuf: component IOBUF
+ port map (
+ I => i2c_master_fmcx_sda_o,
+ IO => i2c_master_fmcx_sda_io,
+ O => i2c_master_fmcx_sda_i,
+ T => i2c_master_fmcx_sda_t
+ );
system_design_i: component system_design
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
@@ -257,8 +289,6 @@ system_design_i: component system_design
dig_outs_i(3 downto 0) => dig_outs_i(3 downto 0),
eeprom_scl => eeprom_scl,
eeprom_sda => eeprom_sda,
- fmcx_scl => fmcx_scl,
- fmcx_sda => fmcx_sda,
gtp0_rate_select_b => gtp0_rate_select_b,
gtp_dedicated_clk_n_i => gtp_dedicated_clk_n_i,
gtp_dedicated_clk_p_i => gtp_dedicated_clk_p_i,
@@ -272,6 +302,12 @@ system_design_i: component system_design
gtp_wr_tx_fault => gtp_wr_tx_fault,
gtp_wr_txn => gtp_wr_txn,
gtp_wr_txp => gtp_wr_txp,
+ i2c_master_fmcx_scl_i => i2c_master_fmcx_scl_i,
+ i2c_master_fmcx_scl_o => i2c_master_fmcx_scl_o,
+ i2c_master_fmcx_scl_t => i2c_master_fmcx_scl_t,
+ i2c_master_fmcx_sda_i => i2c_master_fmcx_sda_i,
+ i2c_master_fmcx_sda_o => i2c_master_fmcx_sda_o,
+ i2c_master_fmcx_sda_t => i2c_master_fmcx_sda_t,
led_col_pl_o(3 downto 0) => led_col_pl_o(3 downto 0),
led_line_en_pl_o => led_line_en_pl_o,
led_line_pl_o => led_line_pl_o,
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
index 23831ba2f0002087a1c9ee17823e33b8785a5080..a6df6822214eba8674b08977bd72d51f49585af0 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Wed Oct 11 14:50:47 2017" VIVADOVERSION="2016.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Wed Oct 11 14:55:00 2017" VIVADOVERSION="2016.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z030" NAME="system_design" PACKAGE="ffg676" SPEEDGRADE="-2"/>
@@ -70,8 +70,6 @@
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="led_line_pl_o"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="IO" NAME="fmcx_scl" SIGIS="undef"/>
- <PORT DIR="IO" NAME="fmcx_sda" SIGIS="undef"/>
<PORT DIR="IO" LEFT="33" NAME="FMC2_LA_P_b" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_FMC2_LA_P_b">
<CONNECTIONS>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="FMC2_LA_P_b"/>
@@ -243,6 +241,12 @@
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="dig_out6_n"/>
</CONNECTIONS>
</PORT>
+ <PORT DIR="I" NAME="i2c_master_fmcx_scl_i" SIGIS="undef"/>
+ <PORT DIR="O" NAME="i2c_master_fmcx_scl_o" SIGIS="undef"/>
+ <PORT DIR="O" NAME="i2c_master_fmcx_scl_t" SIGIS="undef"/>
+ <PORT DIR="O" NAME="i2c_master_fmcx_sda_o" SIGIS="undef"/>
+ <PORT DIR="I" NAME="i2c_master_fmcx_sda_i" SIGIS="undef"/>
+ <PORT DIR="O" NAME="i2c_master_fmcx_sda_t" SIGIS="undef"/>
</EXTERNALPORTS>
<EXTERNALINTERFACES>
@@ -344,6 +348,16 @@
<PORTMAP LOGICAL="SCL" PHYSICAL="gtp_wr_scl"/>
</PORTMAPS>
</BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="axi_wb_i2c_master_2_i2c_master" NAME="i2c_master_fmcx" TYPE="INITIATOR">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="SCL_I" PHYSICAL="i2c_master_fmcx_scl_i"/>
+ <PORTMAP LOGICAL="SCL_O" PHYSICAL="i2c_master_fmcx_scl_o"/>
+ <PORTMAP LOGICAL="SCL_T" PHYSICAL="i2c_master_fmcx_scl_t"/>
+ <PORTMAP LOGICAL="SDA_O" PHYSICAL="i2c_master_fmcx_sda_o"/>
+ <PORTMAP LOGICAL="SDA_I" PHYSICAL="i2c_master_fmcx_sda_i"/>
+ <PORTMAP LOGICAL="SDA_T" PHYSICAL="i2c_master_fmcx_sda_t"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
</EXTERNALINTERFACES>
<MODULES>
@@ -3685,7 +3699,7 @@
<PORTMAP LOGICAL="RREADY" PHYSICAL="s00_axi_rready"/>
</PORTMAPS>
</BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" NAME="i2c_master" TYPE="INITIATOR" VLNV="xilinx.com:interface:iic:1.0">
+ <BUSINTERFACE BUSNAME="axi_wb_i2c_master_2_i2c_master" NAME="i2c_master" TYPE="INITIATOR" VLNV="xilinx.com:interface:iic:1.0">
<PORTMAPS>
<PORTMAP LOGICAL="SCL_I" PHYSICAL="i2c_scl_i"/>
<PORTMAP LOGICAL="SCL_O" PHYSICAL="i2c_scl_o"/>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
index 130ab16f7cf704aa362504829a6830bc5f74ed26..6ba479c06dbf474048fdf2fc3368927d65954ad9 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
@@ -163,6 +163,7 @@ proc create_root_design { parentCell } {
set Vaux10 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux10 ]
set Vp_Vn [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn ]
set gtp_wr [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sfp_rtl:1.0 gtp_wr ]
+ set i2c_master_fmcx [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 i2c_master_fmcx ]
# Create ports
set FMC1_CLK0C2M_N_o [ create_bd_port -dir O FMC1_CLK0C2M_N_o ]
@@ -193,8 +194,6 @@ proc create_root_design { parentCell } {
set dig_outs_i [ create_bd_port -dir O -from 3 -to 0 dig_outs_i ]
set eeprom_scl [ create_bd_port -dir IO eeprom_scl ]
set eeprom_sda [ create_bd_port -dir IO eeprom_sda ]
- set fmcx_scl [ create_bd_port -dir IO fmcx_scl ]
- set fmcx_sda [ create_bd_port -dir IO fmcx_sda ]
set gtp0_rate_select_b [ create_bd_port -dir IO gtp0_rate_select_b ]
set gtp_dedicated_clk_n_i [ create_bd_port -dir I gtp_dedicated_clk_n_i ]
set gtp_dedicated_clk_p_i [ create_bd_port -dir I gtp_dedicated_clk_p_i ]
@@ -1546,6 +1545,7 @@ CONFIG.CONST_WIDTH {1} \
connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_0/M_AXI_S2MM] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_GP0]
connect_bd_intf_net -intf_net axi_interconnect_1_M00_AXI [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins wrc_1p_kintex7_0/s00_axi]
+ connect_bd_intf_net -intf_net axi_wb_i2c_master_2_i2c_master [get_bd_intf_ports i2c_master_fmcx] [get_bd_intf_pins axi_wb_i2c_master_2/i2c_master]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins processing_system7_0_axi_periph/S00_AXI]
@@ -1567,8 +1567,6 @@ CONFIG.CONST_WIDTH {1} \
connect_bd_net -net FMC2_CLK0M2C_N_i_1 [get_bd_ports FMC2_CLK0M2C_N_i] [get_bd_pins fasec_hwtest_0/FMC2_CLK0M2C_N_i]
connect_bd_net -net FMC2_CLK0M2C_P_i_1 [get_bd_ports FMC2_CLK0M2C_P_i] [get_bd_pins fasec_hwtest_0/FMC2_CLK0M2C_P_i]
connect_bd_net -net FMC2_PRSNTM2C_n_i_1 [get_bd_ports FMC2_PRSNTM2C_n_i] [get_bd_pins fasec_hwtest_0/FMC2_PRSNTM2C_n_i]
- connect_bd_net -net Net [get_bd_ports fmcx_scl]
- connect_bd_net -net Net1 [get_bd_ports fmcx_sda]
connect_bd_net -net Net2 [get_bd_ports eeprom_scl] [get_bd_pins wrc_1p_kintex7_0/fpga_scl_b]
connect_bd_net -net Net3 [get_bd_ports eeprom_sda] [get_bd_pins wrc_1p_kintex7_0/fpga_sda_b]
connect_bd_net -net Net4 [get_bd_ports FMC2_LA_P_b] [get_bd_pins fasec_hwtest_0/FMC2_LA_P_b]
@@ -1644,234 +1642,161 @@ CONFIG.CONST_WIDTH {1} \
regenerate_bd_layout -layout_string {
guistr: "# # String gsaved with Nlview 6.5.12 2016-01-29 bk=1.3547 VDI=39 GEI=35 GUI=JA:1.6
# -string -flagsOSRD
-preplace port FMC1_CLK0M2C_N_i -pg 1 -y 960 -defaultsOSRD
-preplace port led_line_en_pl_o -pg 1 -y 940 -defaultsOSRD
-preplace port DDR -pg 1 -y 340 -defaultsOSRD
-preplace port clk_25m_vcxo_i -pg 1 -y 1420 -defaultsOSRD
-preplace port dig_in3_n_i -pg 1 -y 1040 -defaultsOSRD
-preplace port dig_in1_i -pg 1 -y 1000 -defaultsOSRD
-preplace port led_line_pl_o -pg 1 -y 960 -defaultsOSRD
-preplace port Vp_Vn -pg 1 -y 550 -defaultsOSRD
-preplace port eeprom_sda -pg 1 -y 1560 -defaultsOSRD
-preplace port gtp_dedicated_clk_n_i -pg 1 -y 1460 -defaultsOSRD
-preplace port osc100_clk_i -pg 1 -y 880 -defaultsOSRD
-preplace port fmcx_sda -pg 1 -y 430 -defaultsOSRD
-preplace port Vaux0 -pg 1 -y 370 -defaultsOSRD
-preplace port FMC1_CLK0M2C_P_i -pg 1 -y 940 -defaultsOSRD
-preplace port Vaux1 -pg 1 -y 390 -defaultsOSRD
-preplace port thermo_id -pg 1 -y 1580 -defaultsOSRD
-preplace port dac_cs2_n_o -pg 1 -y 1520 -defaultsOSRD
-preplace port FMC2_CLK0M2C_N_i -pg 1 -y 730 -defaultsOSRD
-preplace port Vaux2 -pg 1 -y 570 -defaultsOSRD
-preplace port FMC1_CLK0C2M_P_o -pg 1 -y 860 -defaultsOSRD
-preplace port FMC2_CLK0M2C_P_i -pg 1 -y 900 -defaultsOSRD
-preplace port FMC2_PRSNTM2C_n_i -pg 1 -y 750 -defaultsOSRD
-preplace port Vaux10 -pg 1 -y 630 -defaultsOSRD
-preplace port dac_din_o -pg 1 -y 1480 -defaultsOSRD
-preplace port FMC1_PRSNTM2C_n_i -pg 1 -y 920 -defaultsOSRD
-preplace port gtp_wr -pg 1 -y 1300 -defaultsOSRD
-preplace port gtp0_rate_select_b -pg 1 -y 1600 -defaultsOSRD
-preplace port fmcx_scl -pg 1 -y 410 -defaultsOSRD
-preplace port FIXED_IO -pg 1 -y 390 -defaultsOSRD
-preplace port eeprom_scl -pg 1 -y 1540 -defaultsOSRD
-preplace port dac_cs1_n_o -pg 1 -y 1500 -defaultsOSRD
-preplace port dig_in4_n_i -pg 1 -y 1060 -defaultsOSRD
-preplace port dig_in2_i -pg 1 -y 1020 -defaultsOSRD
-preplace port watchdog_pl_o -pg 1 -y 980 -defaultsOSRD
-preplace port gtp_dedicated_clk_p_i -pg 1 -y 1440 -defaultsOSRD
-preplace port FMC1_CLK0C2M_N_o -pg 1 -y 880 -defaultsOSRD
-preplace port pb_gp_i -pg 1 -y 980 -defaultsOSRD
-preplace port dig_out5_n -pg 1 -y 1020 -defaultsOSRD
-preplace port Vaux8 -pg 1 -y 590 -defaultsOSRD
-preplace port dac_sclk_o -pg 1 -y 1460 -defaultsOSRD
-preplace port FMC2_CLK0C2M_N_o -pg 1 -y 820 -defaultsOSRD
-preplace port FMC2_CLK0C2M_P_o -pg 1 -y 800 -defaultsOSRD
-preplace port Vaux9 -pg 1 -y 610 -defaultsOSRD
-preplace portBus FMC1_LA_P_b -pg 1 -y 760 -defaultsOSRD
-preplace portBus FMC2_LA_N_b -pg 1 -y 740 -defaultsOSRD
-preplace portBus dig_outs_i -pg 1 -y 1000 -defaultsOSRD
-preplace portBus dig_out6_n -pg 1 -y 1040 -defaultsOSRD
-preplace portBus FMC2_LA_P_b -pg 1 -y 720 -defaultsOSRD
-preplace portBus led_col_pl_o -pg 1 -y 920 -defaultsOSRD
-preplace portBus FMC1_LA_N_b -pg 1 -y 780 -defaultsOSRD
-preplace inst processing_system7_0_axi_periph|s00_couplers|auto_pc -pg 1 -lvl 1 -y 572 -defaultsOSRD
-preplace inst processing_system7_0_axi_periph|s00_couplers -pg 1 -lvl 1 -y 582 -defaultsOSRD
-preplace inst fasec_hwtest_0 -pg 1 -lvl 9 -y 900 -defaultsOSRD
-preplace inst processing_system7_0_axi_periph|m00_couplers -pg 1 -lvl 3 -y 152 -defaultsOSRD
-preplace inst axi_dma_0 -pg 1 -lvl 5 -y 370 -defaultsOSRD
-preplace inst processing_system7_0_axi_periph|m02_couplers -pg 1 -lvl 3 -y 512 -defaultsOSRD
-preplace inst processing_system7_0_axi_periph|xbar -pg 1 -lvl 2 -y 662 -defaultsOSRD
-preplace inst xadc_axis_fifo_adapter_0 -pg 1 -lvl 4 -y 460 -defaultsOSRD
-preplace inst rst_processing_system7_0_100M -pg 1 -lvl 1 -y 470 -defaultsOSRD
-preplace inst wrc_1p_kintex7_0 -pg 1 -lvl 9 -y 1480 -defaultsOSRD
-preplace inst xadc_wiz_0 -pg 1 -lvl 3 -y 590 -defaultsOSRD
-preplace inst processing_system7_0_axi_periph|m04_couplers -pg 1 -lvl 3 -y 872 -defaultsOSRD
-preplace inst processing_system7_0_axi_periph|m03_couplers -pg 1 -lvl 3 -y 692 -defaultsOSRD
-preplace inst xlconcat_0 -pg 1 -lvl 6 -y 430 -defaultsOSRD
-preplace inst axi_wb_i2c_master_0 -pg 1 -lvl 3 -y 190 -defaultsOSRD
-preplace inst processing_system7_0_axi_periph|m06_couplers -pg 1 -lvl 3 -y 1232 -defaultsOSRD
-preplace inst processing_system7_0_axi_periph|m05_couplers -pg 1 -lvl 3 -y 1052 -defaultsOSRD
-preplace inst axi_wb_i2c_master_2 -pg 1 -lvl 9 -y 430 -defaultsOSRD
-preplace inst xlconstant_6 -pg 1 -lvl 8 -y 1110 -defaultsOSRD
-preplace inst xlconstant_7 -pg 1 -lvl 8 -y 1520 -defaultsOSRD
-preplace inst axi_uartlite_0 -pg 1 -lvl 3 -y 830 -defaultsOSRD
-preplace inst axi_interconnect_0 -pg 1 -lvl 6 -y 110 -defaultsOSRD
-preplace inst processing_system7_0_axi_periph|m01_couplers -pg 1 -lvl 3 -y 332 -defaultsOSRD
-preplace inst axi_interconnect_1 -pg 1 -lvl 8 -y 780 -defaultsOSRD
-preplace inst processing_system7_0_axi_periph|m07_couplers -pg 1 -lvl 3 -y 1412 -defaultsOSRD
-preplace inst rst_wrc_1p_kintex7_0_62M -pg 1 -lvl 7 -y 860 -defaultsOSRD
-preplace inst processing_system7_0_axi_periph -pg 1 -lvl 2 -y 282 -defaultsOSRD
-preplace inst processing_system7_0 -pg 1 -lvl 7 -y 490 -defaultsOSRD
-preplace netloc processing_system7_0_axi_periph|m05_couplers|m05_couplers_to_m05_couplers 1 0 1 N
-preplace netloc processing_system7_0_axi_periph|m07_couplers_to_processing_system7_0_axi_periph 1 3 1 N
-preplace netloc osc100_clk_i_1 1 0 9 NJ 880 NJ 1730 NJ 750 NJ 660 NJ 660 NJ 660 NJ 660 NJ 660 NJ
-preplace netloc processing_system7_0_axi_periph|s00_couplers|s00_couplers_to_auto_pc 1 0 1 N
-preplace netloc processing_system7_0_axi_periph|xbar_to_m01_couplers 1 2 1 1580
-preplace netloc processing_system7_0_axi_periph|processing_system7_0_axi_periph_ARESETN_net 1 0 3 730 482 1280 482 1610
+preplace port FMC1_CLK0M2C_N_i -pg 1 -y 1040 -defaultsOSRD
+preplace port led_line_en_pl_o -pg 1 -y 1080 -defaultsOSRD
+preplace port DDR -pg 1 -y 430 -defaultsOSRD
+preplace port clk_25m_vcxo_i -pg 1 -y 1610 -defaultsOSRD
+preplace port dig_in3_n_i -pg 1 -y 1180 -defaultsOSRD
+preplace port dig_in1_i -pg 1 -y 1140 -defaultsOSRD
+preplace port led_line_pl_o -pg 1 -y 1100 -defaultsOSRD
+preplace port Vp_Vn -pg 1 -y 760 -defaultsOSRD
+preplace port eeprom_sda -pg 1 -y 1750 -defaultsOSRD
+preplace port gtp_dedicated_clk_n_i -pg 1 -y 1650 -defaultsOSRD
+preplace port osc100_clk_i -pg 1 -y 1000 -defaultsOSRD
+preplace port Vaux0 -pg 1 -y 780 -defaultsOSRD
+preplace port FMC1_CLK0M2C_P_i -pg 1 -y 1020 -defaultsOSRD
+preplace port Vaux1 -pg 1 -y 800 -defaultsOSRD
+preplace port thermo_id -pg 1 -y 1770 -defaultsOSRD
+preplace port dac_cs2_n_o -pg 1 -y 1710 -defaultsOSRD
+preplace port FMC2_CLK0M2C_N_i -pg 1 -y 690 -defaultsOSRD
+preplace port Vaux2 -pg 1 -y 820 -defaultsOSRD
+preplace port FMC1_CLK0C2M_P_o -pg 1 -y 1000 -defaultsOSRD
+preplace port FMC2_CLK0M2C_P_i -pg 1 -y 670 -defaultsOSRD
+preplace port FMC2_PRSNTM2C_n_i -pg 1 -y 650 -defaultsOSRD
+preplace port Vaux10 -pg 1 -y 880 -defaultsOSRD
+preplace port dac_din_o -pg 1 -y 1670 -defaultsOSRD
+preplace port FMC1_PRSNTM2C_n_i -pg 1 -y 710 -defaultsOSRD
+preplace port gtp_wr -pg 1 -y 1490 -defaultsOSRD
+preplace port gtp0_rate_select_b -pg 1 -y 1790 -defaultsOSRD
+preplace port i2c_master_fmcx -pg 1 -y 510 -defaultsOSRD
+preplace port FIXED_IO -pg 1 -y 450 -defaultsOSRD
+preplace port eeprom_scl -pg 1 -y 1730 -defaultsOSRD
+preplace port dac_cs1_n_o -pg 1 -y 1690 -defaultsOSRD
+preplace port dig_in4_n_i -pg 1 -y 1200 -defaultsOSRD
+preplace port dig_in2_i -pg 1 -y 1160 -defaultsOSRD
+preplace port watchdog_pl_o -pg 1 -y 1120 -defaultsOSRD
+preplace port gtp_dedicated_clk_p_i -pg 1 -y 1630 -defaultsOSRD
+preplace port FMC1_CLK0C2M_N_o -pg 1 -y 1020 -defaultsOSRD
+preplace port pb_gp_i -pg 1 -y 1670 -defaultsOSRD
+preplace port dig_out5_n -pg 1 -y 1160 -defaultsOSRD
+preplace port Vaux8 -pg 1 -y 840 -defaultsOSRD
+preplace port dac_sclk_o -pg 1 -y 1650 -defaultsOSRD
+preplace port FMC2_CLK0C2M_N_o -pg 1 -y 960 -defaultsOSRD
+preplace port FMC2_CLK0C2M_P_o -pg 1 -y 940 -defaultsOSRD
+preplace port Vaux9 -pg 1 -y 860 -defaultsOSRD
+preplace portBus FMC1_LA_P_b -pg 1 -y 900 -defaultsOSRD
+preplace portBus FMC2_LA_N_b -pg 1 -y 880 -defaultsOSRD
+preplace portBus dig_outs_i -pg 1 -y 1140 -defaultsOSRD
+preplace portBus dig_out6_n -pg 1 -y 1180 -defaultsOSRD
+preplace portBus FMC2_LA_P_b -pg 1 -y 860 -defaultsOSRD
+preplace portBus led_col_pl_o -pg 1 -y 1060 -defaultsOSRD
+preplace portBus FMC1_LA_N_b -pg 1 -y 920 -defaultsOSRD
+preplace inst fasec_hwtest_0 -pg 1 -lvl 9 -y 1040 -defaultsOSRD
+preplace inst axi_dma_0 -pg 1 -lvl 5 -y 320 -defaultsOSRD
+preplace inst xadc_axis_fifo_adapter_0 -pg 1 -lvl 4 -y 370 -defaultsOSRD
+preplace inst rst_processing_system7_0_100M -pg 1 -lvl 1 -y 110 -defaultsOSRD
+preplace inst wrc_1p_kintex7_0 -pg 1 -lvl 9 -y 1660 -defaultsOSRD
+preplace inst xadc_wiz_0 -pg 1 -lvl 3 -y 840 -defaultsOSRD
+preplace inst xlconcat_0 -pg 1 -lvl 6 -y 580 -defaultsOSRD
+preplace inst axi_wb_i2c_master_0 -pg 1 -lvl 3 -y 390 -defaultsOSRD
+preplace inst axi_wb_i2c_master_2 -pg 1 -lvl 9 -y 520 -defaultsOSRD
+preplace inst xlconstant_6 -pg 1 -lvl 8 -y 1250 -defaultsOSRD
+preplace inst xlconstant_7 -pg 1 -lvl 8 -y 1710 -defaultsOSRD
+preplace inst axi_uartlite_0 -pg 1 -lvl 3 -y 580 -defaultsOSRD
+preplace inst axi_interconnect_0 -pg 1 -lvl 6 -y 240 -defaultsOSRD
+preplace inst axi_interconnect_1 -pg 1 -lvl 8 -y 870 -defaultsOSRD
+preplace inst rst_wrc_1p_kintex7_0_62M -pg 1 -lvl 7 -y 850 -defaultsOSRD
+preplace inst processing_system7_0_axi_periph -pg 1 -lvl 2 -y 280 -defaultsOSRD
+preplace inst processing_system7_0 -pg 1 -lvl 7 -y 520 -defaultsOSRD
+preplace netloc osc100_clk_i_1 1 0 9 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ
preplace netloc fasec_hwtest_0_led_col_pl_o 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph|m04_couplers|m04_couplers_to_m04_couplers 1 0 1 N
-preplace netloc dig_in4_n_i_1 1 0 9 NJ 1060 NJ 1700 NJ 1060 NJ 1060 NJ 1060 NJ 1060 NJ 1060 NJ 1060 NJ
-preplace netloc processing_system7_0_axi_periph|s00_couplers_to_xbar 1 1 1 1290
-preplace netloc processing_system7_0_FIXED_IO 1 7 3 NJ 360 NJ 360 NJ
+preplace netloc dig_in4_n_i_1 1 0 9 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ
+preplace netloc processing_system7_0_FIXED_IO 1 7 3 NJ 450 NJ 450 NJ
preplace netloc fasec_hwtest_0_dig_outs_i 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph|M02_ARESETN_1 1 0 3 NJ 422 NJ 422 1640
-preplace netloc processing_system7_0_axi_periph|M02_ACLK_1 1 0 3 NJ 412 NJ 412 1650
-preplace netloc gtp_dedicated_clk_n_i_1 1 0 9 NJ 1460 NJ 1710 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ
+preplace netloc gtp_dedicated_clk_n_i_1 1 0 9 NJ 1650 NJ 1650 NJ 1650 NJ 1650 NJ 1650 NJ 1650 NJ 1650 NJ 1650 NJ
preplace netloc wrc_1p_kintex7_0_dac_din_o 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph|xbar_to_m05_couplers 1 2 1 1570
-preplace netloc processing_system7_0_axi_periph|m02_couplers_to_processing_system7_0_axi_periph 1 3 1 N
-preplace netloc processing_system7_0_axi_periph|m04_couplers_to_processing_system7_0_axi_periph 1 3 1 N
-preplace netloc gtp_dedicated_clk_p_i_1 1 0 9 NJ 1440 NJ 1720 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ
-preplace netloc wrc_1p_kintex7_0_clk_rx_rbclk_o 1 8 2 5020 1180 5420
-preplace netloc wrc_1p_kintex7_0_pps_o 1 8 2 5010 1190 5440
-preplace netloc axi_uartlite_0_tx 1 3 7 NJ 630 NJ 630 NJ 630 NJ 630 NJ 630 NJ 630 5410
-preplace netloc dig_in3_n_i_1 1 0 9 NJ 1040 NJ 1680 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ
-preplace netloc FMC1_PRSNTM2C_n_i_1 1 0 9 NJ 920 NJ 1620 NJ 960 NJ 960 NJ 960 NJ 960 NJ 960 NJ 960 NJ
-preplace netloc processing_system7_0_axi_periph|xbar_to_m04_couplers 1 2 1 1580
-preplace netloc dig_in1_i_1 1 0 9 NJ 1000 NJ 1660 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ
-preplace netloc processing_system7_0_axi_periph|xbar_to_m03_couplers 1 2 1 N
-preplace netloc xlconcat_0_dout 1 6 1 3760
+preplace netloc gtp_dedicated_clk_p_i_1 1 0 9 NJ 1630 NJ 1630 NJ 1630 NJ 1630 NJ 1630 NJ 1630 NJ 1630 NJ 1630 NJ
+preplace netloc wrc_1p_kintex7_0_clk_rx_rbclk_o 1 8 2 2880 1330 3270
+preplace netloc wrc_1p_kintex7_0_pps_o 1 8 2 2850 1370 3230
+preplace netloc axi_uartlite_0_tx 1 3 7 NJ 650 NJ 650 NJ 710 NJ 710 NJ 710 NJ 710 3300
+preplace netloc dig_in3_n_i_1 1 0 9 NJ 1180 NJ 1180 NJ 1180 NJ 1180 NJ 1180 NJ 1180 NJ 1180 NJ 1180 NJ
+preplace netloc FMC1_PRSNTM2C_n_i_1 1 0 9 NJ 710 NJ 700 NJ 690 NJ 690 NJ 690 NJ 750 NJ 750 NJ 750 NJ
+preplace netloc dig_in1_i_1 1 0 9 NJ 1140 NJ 1140 NJ 1140 NJ 1140 NJ 1140 NJ 1140 NJ 1140 NJ 1140 NJ
+preplace netloc xlconcat_0_dout 1 6 1 2030
preplace netloc fasec_hwtest_0_FMC1_CLK0C2M_P_o 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph|m03_couplers|m03_couplers_to_m03_couplers 1 0 1 N
-preplace netloc processing_system7_0_axi_periph|s00_couplers|S_ACLK_1 1 0 1 920
-preplace netloc processing_system7_0_axi_periph|M07_ARESETN_1 1 0 3 NJ 1412 NJ 1412 N
-preplace netloc pb_gp_i_1 1 0 9 NJ 980 NJ 1740 NJ 1470 NJ 1470 NJ 1470 NJ 1470 NJ 1470 NJ 1470 4990
+preplace netloc pb_gp_i_1 1 0 9 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 2820
preplace netloc wrc_1p_kintex7_0_dac_sclk_o 1 9 1 NJ
preplace netloc fasec_hwtest_0_led_line_pl_o 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph_M06_AXI 1 2 3 2120 330 NJ 330 NJ
-preplace netloc axi_wb_i2c_master_2_axi_int_o 1 5 5 3340 290 NJ 290 NJ 290 NJ 290 5450
-preplace netloc processing_system7_0_axi_periph|xbar_to_m00_couplers 1 2 1 1570
-preplace netloc processing_system7_0_DDR 1 7 3 NJ 340 NJ 340 NJ
-preplace netloc FMC1_CLK0M2C_N_i_1 1 0 9 NJ 960 NJ 1610 NJ 740 NJ 650 NJ 650 NJ 650 NJ 650 NJ 650 NJ
+preplace netloc processing_system7_0_axi_periph_M06_AXI 1 2 3 670 320 NJ 260 NJ
+preplace netloc axi_wb_i2c_master_2_axi_int_o 1 5 5 1690 470 NJ 680 NJ 680 NJ 680 3320
+preplace netloc processing_system7_0_DDR 1 7 3 NJ 430 NJ 430 NJ
+preplace netloc FMC1_CLK0M2C_N_i_1 1 0 9 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ
preplace netloc wrc_1p_kintex7_0_dac_cs2_n_o 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph|m07_couplers|m07_couplers_to_m07_couplers 1 0 1 N
-preplace netloc processing_system7_0_axi_periph|M05_ACLK_1 1 0 3 NJ 1032 NJ 1032 N
-preplace netloc axi_interconnect_1_M00_AXI 1 8 1 4890
-preplace netloc FMC2_CLK0M2C_N_i_1 1 0 9 NJ 730 NJ 1630 NJ 950 NJ 950 NJ 950 NJ 950 NJ 950 NJ 950 NJ
-preplace netloc processing_system7_0_axi_periph|s00_couplers|auto_pc_to_s00_couplers 1 1 1 N
-preplace netloc processing_system7_0_axi_periph|processing_system7_0_axi_periph_ACLK_net 1 0 3 750 472 1300 472 1600
-preplace netloc processing_system7_0_axi_periph_M05_AXI 1 2 2 2130 400 NJ
+preplace netloc axi_wb_i2c_master_2_i2c_master 1 9 1 NJ
+preplace netloc axi_interconnect_1_M00_AXI 1 8 1 2740
+preplace netloc FMC2_CLK0M2C_N_i_1 1 0 9 NJ 690 NJ 690 NJ 680 NJ 680 NJ 680 NJ 740 NJ 740 NJ 740 NJ
+preplace netloc processing_system7_0_axi_periph_M05_AXI 1 2 2 N 310 NJ
preplace netloc fasec_hwtest_0_dig_out6_n 1 9 1 NJ
-preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 8 -40 1770 NJ 1770 NJ 920 NJ 840 NJ 840 NJ 840 3770 670 4300
-preplace netloc FMC2_PRSNTM2C_n_i_1 1 0 9 NJ 750 NJ 1600 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ
-preplace netloc xadc_wiz_0_M_AXIS 1 3 1 2660
-preplace netloc rst_wrc_1p_kintex7_0_62M_interconnect_aresetn 1 7 1 4350
-preplace netloc processing_system7_0_axi_periph_M02_AXI 1 2 7 NJ 320 NJ 320 NJ 540 NJ 540 NJ 350 NJ 350 4970
-preplace netloc xadc_axis_fifo_adapter_0_M_AXIS 1 4 1 2940
-preplace netloc processing_system7_0_axi_periph|m01_couplers|m01_couplers_to_m01_couplers 1 0 1 N
-preplace netloc processing_system7_0_axi_periph|M03_ACLK_1 1 0 3 NJ 442 NJ 442 1630
-preplace netloc processing_system7_0_axi_periph_M07_AXI 1 2 1 2190
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-preplace netloc axi_dma_0_M_AXI_S2MM 1 5 1 3280
-preplace netloc wrc_1p_kintex7_0_gtp0_link_led_o 1 8 2 5010 590 5490
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-preplace netloc Vp_Vn_1 1 0 3 NJ 1580 NJ 1580 NJ
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preplace netloc fasec_hwtest_0_watchdog_pl_o 1 9 1 NJ
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-preplace netloc processing_system7_0_axi_periph|m00_couplers_to_processing_system7_0_axi_periph 1 3 1 N
-preplace netloc processing_system7_0_axi_periph_M01_AXI 1 2 1 2110
+preplace netloc processing_system7_0_axi_periph_M01_AXI 1 2 1 740
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-preplace netloc processing_system7_0_axi_periph|m02_couplers|m02_couplers_to_m02_couplers 1 0 1 N
-preplace netloc Vaux0_1 1 0 3 NJ 360 NJ 1540 NJ
-preplace netloc Net 1 9 1 NJ
+preplace netloc FMC1_CLK0M2C_P_i_1 1 0 9 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ
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preplace netloc Net10 1 9 1 NJ
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-preplace netloc processing_system7_0_axi_periph|m00_couplers|m00_couplers_to_m00_couplers 1 0 1 N
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preplace netloc Net2 1 9 1 NJ
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+preplace netloc fasec_hwtest_0_intr_o 1 5 5 1680 690 NJ 690 NJ 690 NJ 690 3320
preplace netloc Net3 1 9 1 NJ
-preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 1 290
-preplace netloc processing_system7_0_axi_periph|M01_ACLK_1 1 0 3 NJ 312 NJ 312 N
-preplace netloc processing_system7_0_axi_periph_M00_AXI 1 2 7 NJ 110 NJ 110 NJ 110 NJ 230 NJ 230 NJ 230 4980
+preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 1 350
+preplace netloc processing_system7_0_axi_periph_M00_AXI 1 2 7 N 210 NJ 210 NJ 210 NJ 360 NJ 360 NJ 360 NJ
preplace netloc fasec_hwtest_0_led_line_en_pl_o 1 9 1 NJ
-preplace netloc wrc_1p_kintex7_0_s00_axi_aclk_o 1 6 4 3800 740 4340 1170 NJ 1170 5450
+preplace netloc wrc_1p_kintex7_0_s00_axi_aclk_o 1 6 4 2040 760 2430 1380 NJ 1380 3220
preplace netloc Net4 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph|S00_ARESETN_1 1 0 1 690
-preplace netloc Vaux8_1 1 0 3 NJ 20 NJ 20 NJ
-preplace netloc wrc_1p_kintex7_0_gtp0_activity_led_o 1 8 2 5000 580 5480
+preplace netloc Vaux8_1 1 0 3 NJ 840 NJ 840 NJ
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preplace netloc Net5 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph|m06_couplers_to_processing_system7_0_axi_periph 1 3 1 N
-preplace netloc processing_system7_0_axi_periph|M01_ARESETN_1 1 0 3 NJ 332 NJ 332 N
-preplace netloc xadc_wiz_0_ip2intc_irpt 1 3 3 2660 590 NJ 590 NJ
+preplace netloc xadc_wiz_0_ip2intc_irpt 1 3 3 NJ 770 NJ 770 1670
preplace netloc Net6 1 9 1 NJ
preplace netloc xlconstant_6_dout 1 8 1 NJ
preplace netloc Net7 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph|processing_system7_0_axi_periph_to_s00_couplers 1 0 1 770
-preplace netloc processing_system7_0_axi_periph|M06_ARESETN_1 1 0 3 NJ 1232 NJ 1232 N
-preplace netloc processing_system7_0_axi_periph|M03_ARESETN_1 1 0 3 NJ 462 NJ 462 1590
-preplace netloc processing_system7_0_axi_periph|M07_ACLK_1 1 0 3 NJ 1392 NJ 1392 N
-preplace netloc dig_in2_i_1 1 0 9 NJ 1020 NJ 1670 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ
-preplace netloc axi_uartlite_0_interrupt 1 3 3 2670 580 NJ 580 NJ
-preplace netloc processing_system7_0_axi_periph|M04_ACLK_1 1 0 3 NJ 852 NJ 852 N
-preplace netloc Vaux10_1 1 0 3 NJ 630 NJ 1560 NJ
-preplace netloc processing_system7_0_M_AXI_GP0 1 1 7 490 1570 NJ 1570 NJ 1570 NJ 1570 NJ 1570 NJ 1570 4310
-preplace netloc processing_system7_0_axi_periph|M06_ACLK_1 1 0 3 NJ 1212 NJ 1212 N
-preplace netloc wrc_1p_kintex7_0_clk_ref_o 1 8 2 5000 1200 5400
-preplace netloc Vaux1_1 1 0 3 NJ 380 NJ 1550 NJ
-preplace netloc processing_system7_0_axi_periph|xbar_to_m07_couplers 1 2 1 1550
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-preplace netloc processing_system7_0_axi_periph|m05_couplers_to_processing_system7_0_axi_periph 1 3 1 N
-preplace netloc processing_system7_0_axi_periph|M05_ARESETN_1 1 0 3 NJ 1052 NJ 1052 N
-preplace netloc Vaux9_1 1 0 3 NJ 1590 NJ 1590 NJ
-preplace netloc axi_dma_0_s2mm_introut 1 5 1 3310
-preplace netloc processing_system7_0_axi_periph_M04_AXI 1 2 1 2140
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-preplace netloc FMC2_CLK0M2C_P_i_1 1 0 9 NJ 900 NJ 1640 NJ 970 NJ 970 NJ 970 NJ 970 NJ 970 NJ 970 NJ
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preplace netloc wrc_1p_kintex7_0_dac_cs1_n_o 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph|M00_ARESETN_1 1 0 3 NJ 152 NJ 152 N
preplace netloc wrc_1p_kintex7_0_gtp_wr 1 9 1 NJ
-preplace netloc S00_AXI_1 1 7 1 4340
-preplace netloc axi_interconnect_0_M00_AXI 1 6 1 3800
+preplace netloc S00_AXI_1 1 7 1 2440
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preplace netloc xlconstant_7_dout 1 8 1 NJ
-preplace netloc axi_wb_i2c_master_0_axi_int_o 1 3 3 NJ 200 NJ 200 3290
-levelinfo -pg 1 -100 130 790 2530 2820 3120 3610 4110 4720 5227 5530 -top 0 -bot 2470
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-levelinfo -hier processing_system7_0_axi_periph|m07_couplers * *
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",
}
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.dcp b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.dcp
index 7366bb9b468b597bf5feadbcce13fed4862e91f4..a6cb00b5a111bae29ac2d86b6cafb5559fbd0be6 100644
Binary files a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.dcp and b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.dcp differ
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
index 018eb8703c66d804505520107f7ea99e550117bd..7d0e39e422d78b7de0922964896a82e6a8ea5c96 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1223,7 +1223,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:53:04 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:56:48 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v
index d620f004b544a0a72178428776770c6cd043ecfd..056d9449dad5a1a11cd595208cf91f3823eae5f2 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Oct 11 14:53:04 2017
+// Date : Wed Oct 11 14:56:47 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode funcsim
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl
index 7c2bfab2141439e26c9407d5ba6c70c351fef796..5439030d2d79dfad0be8ea2730fade0ed42625d8 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Oct 11 14:53:04 2017
+-- Date : Wed Oct 11 14:56:47 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode funcsim
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v
index 7c4da24b168273202bad533f4c1bb101798688dd..53bf4f2e922f55445f7524605e8aadf5b76d4556 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Oct 11 14:53:04 2017
+// Date : Wed Oct 11 14:56:47 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode synth_stub
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl
index fff56b5f4ab7fb8b850750105966eb8f1db0eb76..d7010ae79faa1e504765030349dafdbb98b2d9da 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Oct 11 14:53:04 2017
+-- Date : Wed Oct 11 14:56:47 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode synth_stub
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.dcp b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.dcp
index feaaf01edd19d05b45b91ff8efc8dad5c5d0630b..b4fa8b32da7ac521d4ee723a82251930a2cf6e1d 100644
Binary files a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.dcp and b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.dcp differ
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
index 863107faa951b39a049e43b62864d87c9f60f34e..84877b699520ef0f867a1ec8e24baee59ff192e3 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1223,7 +1223,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:53:07 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:56:45 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v
index a0c5b4ad0273af6bb855f0658681b735af14b01f..795246d64c92eac7cc55fdeda10993f3ea9ae107 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Oct 11 14:53:07 2017
+// Date : Wed Oct 11 14:56:45 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode funcsim
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl
index 4e7593054a25d631955421e7c53147704ede6de4..7dd8f70d473added6c565bdf86f3c594176ab2a7 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Oct 11 14:53:07 2017
+-- Date : Wed Oct 11 14:56:45 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode funcsim
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v
index 02654daaf213bae05acc210679fa796ad1d4e267..7b0baf39c3dd43b216fc0f615b6078eb3ec3d2c8 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Oct 11 14:53:07 2017
+// Date : Wed Oct 11 14:56:45 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode synth_stub
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl
index 2cda0cb2eb31c703414cb72f02c479877fc2f223..883775f86ac1b2a00ec02050569ca75c827f9953 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Oct 11 14:53:07 2017
+-- Date : Wed Oct 11 14:56:45 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode synth_stub
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.dcp b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.dcp
index a50adc3b12b28e32793eebf1119d28b9378ec83d..f33a4465d16aa130ff5bd845bdb9615c1aae805f 100644
Binary files a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.dcp and b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.dcp differ
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
index 2292534a9a88970eafe0c95a8746a0a4efcbb854..81e401c3fb0868f0ebac1ce9a67a563467b9aa7f 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:50:47 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1223,7 +1223,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:53:52 UTC 2017</spirit:value>
+ <spirit:value>Wed Oct 11 12:56:45 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v
index 7971625436cdc09d86fd8ce28350ebd833585865..8adcda0879077e3135587f16c4f23507612213b4 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Oct 11 14:53:52 2017
+// Date : Wed Oct 11 14:56:44 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode funcsim
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl
index 121b9db63639d1c77c12d6cae32703cd7d77f3fa..bc6e750de6d712ebd41ce2dbcfbc2bac07cc8855 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Oct 11 14:53:52 2017
+-- Date : Wed Oct 11 14:56:45 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode funcsim
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v
index 22d02876c7108cb01b58acf97874272f4552431a..d369b145e2ef5937262305fb4a7dc9234deac9ea 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Oct 11 14:53:52 2017
+// Date : Wed Oct 11 14:56:44 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode synth_stub
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl
index 0fbcbadc2ce9d0570ea08f7ead1b300871824d0b..62a392ada93b45e9ad8119606c9fe6248532f920 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Oct 11 14:53:52 2017
+-- Date : Wed Oct 11 14:56:44 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode synth_stub
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
index 1571b557011d28f738be9050f38474dc0cc611a3..32a5f6aad1986f078eae4668b8c265f222a213a4 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<bd:repository xmlns:bd="http://www.xilinx.com/bd" bd:synthFlowMode="Hierarchical" bd:tool_version="2016.2" bd:top="system_design" bd:version="1.00.a">
+<bd:repository xmlns:bd="http://www.xilinx.com/bd" bd:isValidated="true" bd:synthFlowMode="Hierarchical" bd:tool_version="2016.2" bd:top="system_design" bd:version="1.00.a">
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>xilinx.com</spirit:vendor>
@@ -18,7 +18,107 @@
<spirit:master/>
<spirit:busType spirit:library="interface" spirit:name="ddrx" spirit:vendor="xilinx.com" spirit:version="1.0"/>
<spirit:abstractionType spirit:library="interface" spirit:name="ddrx_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
- <spirit:parameters/>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>TIMEPERIOD_PS</spirit:name>
+ <spirit:value>1250</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="default"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MEMORY_TYPE</spirit:name>
+ <spirit:value>COMPONENTS</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="default"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DATA_WIDTH</spirit:name>
+ <spirit:value>8</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="default"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CS_ENABLED</spirit:name>
+ <spirit:value>true</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="default"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DATA_MASK_ENABLED</spirit:name>
+ <spirit:value>true</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="default"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SLOT</spirit:name>
+ <spirit:value>Single</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="default"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MEM_ADDR_MAP</spirit:name>
+ <spirit:value>ROW_COLUMN_BANK</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="default"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>BURST_LENGTH</spirit:name>
+ <spirit:value>8</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="default"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
+ <spirit:value>TDM</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="default"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CAS_LATENCY</spirit:name>
+ <spirit:value>11</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="default"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CAS_WRITE_LATENCY</spirit:name>
+ <spirit:value>11</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="default"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ </spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>FIXED_IO</spirit:name>
@@ -1185,10 +1285,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>S00_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>S00_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -1231,10 +1341,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M00_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M00_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -1401,10 +1521,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -1447,10 +1577,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>S_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>S_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -1674,10 +1814,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>S00_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>S00_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -1720,10 +1870,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M00_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M00_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -1766,10 +1926,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M01_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M01_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -1812,10 +1982,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M02_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M02_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -1858,10 +2038,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M03_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M03_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -1904,10 +2094,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M04_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M04_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -1950,10 +2150,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M05_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M05_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -1996,10 +2206,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M06_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M06_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -2042,10 +2262,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M07_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M07_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -2531,10 +2761,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -2577,10 +2817,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>S_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>S_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -2701,10 +2951,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -2747,10 +3007,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>S_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>S_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -2871,10 +3141,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -2917,10 +3197,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>S_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>S_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -3041,10 +3331,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -3087,10 +3387,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>S_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>S_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -3211,10 +3521,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -3257,10 +3577,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>S_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>S_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -3381,10 +3711,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -3427,10 +3767,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>S_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>S_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -3551,10 +3901,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -3597,10 +3957,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>S_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>S_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -3721,10 +4091,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -3767,10 +4147,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>S_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>S_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -3891,10 +4281,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -3937,10 +4337,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>S_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>S_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -4122,10 +4532,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>S00_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>S00_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -4168,10 +4588,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M00_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M00_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -4338,10 +4768,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>M_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>M_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
@@ -4384,10 +4824,20 @@
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value>S_AXI</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value>S_ARESETN</spirit:value>
+ <spirit:vendorExtensions>
+ <bd:configElementInfos>
+ <bd:configElementInfo bd:valueSource="user"/>
+ </bd:configElementInfos>
+ </spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
index b956d514a3029550167e89589dd549eea7ec5128..e4e486a0eace8d60c04930279b0514a52e288fb1 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
@@ -2,9 +2,9 @@
<Root MajorVersion="0" MinorVersion="33">
<CompositeFile CompositeFileTopName="system_design" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
- <Generation Name="SYNTHESIS" State="STALE" Timestamp="1507726370"/>
- <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1507726370"/>
- <Generation Name="SIMULATION" State="STALE" Timestamp="1507726370"/>
+ <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1507726504"/>
+ <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1507726504"/>
+ <Generation Name="SIMULATION" State="GENERATED" Timestamp="1507726504"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci" Type="IP">
<Instance HierarchyPath="processing_system7_0"/>
diff --git a/FASEC_prototype.xpr b/FASEC_prototype.xpr
index 5616f4a350a600df5afa826d3c66fdb72935bb1a..67db2ce76f64723ff9265a0094b13d751e419073 100644
--- a/FASEC_prototype.xpr
+++ b/FASEC_prototype.xpr
@@ -102,15 +102,19 @@
<Proxy FileSetName="system_design_fasec_hwtest_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci"/>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_2/system_design_auto_pc_2.xci">
- <Proxy FileSetName="system_design_auto_pc_2"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_0/system_design_auto_pc_0.xci">
+ <Proxy FileSetName="system_design_auto_pc_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_1/system_design_auto_pc_1.xci">
<Proxy FileSetName="system_design_auto_pc_1"/>
</CompFileExtendedInfo>
- <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_0/system_design_auto_pc_0.xci">
- <Proxy FileSetName="system_design_auto_pc_0"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_2/system_design_auto_pc_2.xci">
+ <Proxy FileSetName="system_design_auto_pc_2"/>
</CompFileExtendedInfo>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="system_design_ooc.xdc"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hw_handoff/system_design.hwh"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.hwdef"/>
+ <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hw_handoff/system_design_bd.tcl"/>
</File>
<File Path="$PSRCDIR/sources_1/bd/system_design/hdl/system_design_wrapper.vhd">
<FileInfo>
@@ -281,11 +285,12 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
- <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" IncludeInArchive="true">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
<Step Id="synth_design"/>
</Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="system_design_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_design_processing_system7_0_0" Part="xc7z030ffg676-2" ConstrsSet="system_design_processing_system7_0_0" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/system_design_processing_system7_0_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">