diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
index d33a39aeeac421e3483cde3e95e120cab827354d..6acfea81578dfb6fb8fc1b050d27cfa76568084d 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
@@ -1,7 +1,7 @@
--Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018
---Date : Tue Jun 26 19:07:23 2018
+--Date : Tue Jun 26 20:45:41 2018
--Host : lapte24154 running 64-bit openSUSE Leap 42.3
--Command : generate_target system_design_wrapper.bd
--Design : system_design_wrapper
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci
index e9f56f4b42c27d29bd901c5acc2b82c1261b9a46..072ab0c2298987648e3c7885c8e673867977c867 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci
@@ -7,7 +7,7 @@
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>system_design_fasec_hwtest_0_0</spirit:instanceName>
- <spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="fasec_hwtest" spirit:version="3.2.7"/>
+ <spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="fasec_hwtest" spirit:version="3.2.8"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
@@ -65,7 +65,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">35</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">37</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
index 329532a5d73b0d7946415ba54ba98602440f8fb4..807f646a1a4eaf7ea0a7f6d21273378e7ff4452e 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
@@ -1399,7 +1399,7 @@
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>fasec_hwtest</xilinx:displayName>
- <xilinx:coreRevision>35</xilinx:coreRevision>
+ <xilinx:coreRevision>37</xilinx:coreRevision>
<xilinx:tags>
<xilinx:tag xilinx:name="user.org:user:fasec_hwtest:1.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
<xilinx:tag xilinx:name="user.org:user:fasec_hwtest:2.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
@@ -1432,7 +1432,8 @@
<xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.2.4_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
<xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.2.5_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
<xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.2.6_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
- <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.2.7_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
+ <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.2.7_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/FASEC_prototype/ip_cores/cores/FASEC_hwtest</xilinx:tag>
+ <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.2.8_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/FASEC_prototype/ip_cores/cores/FASEC_hwtest</xilinx:tag>
</xilinx:tags>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
@@ -1467,13 +1468,13 @@
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
- <xilinx:xilinxVersion>2016.2</xilinx:xilinxVersion>
- <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="92ed6682"/>
- <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="6bf44be4"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="85b35840"/>
- <xilinx:checksum xilinx:scope="ports" xilinx:value="fe85f838"/>
- <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="455aa684"/>
- <xilinx:checksum xilinx:scope="parameters" xilinx:value="f383f867"/>
+ <xilinx:xilinxVersion>2018.1</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="e26110fd"/>
+ <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="e4009ebe"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="bc4d2a4c"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="4d3e81cb"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="2668e947"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="985a3c93"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
index 091046466d8b9dcde8a463d26373c9f397136f78..3960ed66a6e97071c510d7def372268616f27cd3 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
@@ -1217,7 +1217,7 @@
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>fasec_hwtest_0</spirit:instanceName>
- <spirit:componentRef spirit:library="user" spirit:name="fasec_hwtest" spirit:vendor="user.org" spirit:version="3.2.7"/>
+ <spirit:componentRef spirit:library="user" spirit:name="fasec_hwtest" spirit:vendor="user.org" spirit:version="3.2.8"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_fasec_hwtest_0_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="g_FMC1">EDA-03287</spirit:configurableElementValue>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
index b459611d11233a2751af52f0050582b46e3a31e0..a58ecc9b29334efeb19de528bf0a8f38e4e496bf 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="35">
<CompositeFile CompositeFileTopName="system_design" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
- <Generation Name="SYNTHESIS" State="RESET" Timestamp="1530033539"/>
- <Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1530033539"/>
- <Generation Name="SIMULATION" State="RESET" Timestamp="1530033539"/>
- <Generation Name="HW_HANDOFF" State="RESET" Timestamp="1530033539"/>
+ <Generation Name="SYNTHESIS" State="RESET" Timestamp="1530039884"/>
+ <Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1530039884"/>
+ <Generation Name="SIMULATION" State="RESET" Timestamp="1530039884"/>
+ <Generation Name="HW_HANDOFF" State="RESET" Timestamp="1530039884"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci" Type="IP">
<Instance HierarchyPath="processing_system7_0"/>
diff --git a/FASEC_prototype.srcs/tcl/set_registers.tcl b/FASEC_prototype.srcs/tcl/set_registers.tcl
index 857e33092b93932aa36b96610c8f22c15ee0a7e7..ae4ad730202caf2ba06621c1ca1972845b282967 100644
--- a/FASEC_prototype.srcs/tcl/set_registers.tcl
+++ b/FASEC_prototype.srcs/tcl/set_registers.tcl
@@ -73,8 +73,14 @@ reset_run $runname
# it's using VHDL-2008, fileset property is not persisent
set_property vhdl_version vhdl_2008 [get_filesets $ipname]
eval launch_runs $runname -jobs 4 $_remote
-# after BD IP update, the below run also might need rerunning..
-if {[get_property PROGRESS [get_runs system_design_auto_pc_0_synth_1]] != "100%"} { eval launch_runs system_design_auto_pc_0_synth_1 -jobs 4 $_remote }
+# after BD IP update, the below runs also need rerunning..
+foreach a [get_runs *auto_pc_?_synth_1] {
+ if {[get_property PROGRESS [get_runs $a]] != "100%"} {
+ reset_run $a
+ eval launch_runs $a -jobs 4 $_remote
+ }
+}
+
wait_on_run $runname
# eval concatenates its arguments in the same fashion as concat, and hands them to the interpreter to be evaluated as a Tcl script
diff --git a/FASEC_prototype.xpr b/FASEC_prototype.xpr
index 8d46324c7fea2fbf11e276a1b2fb5a2af1f956d1..2fde94740e87260697d1b5fd65116e9c78ee0760 100644
--- a/FASEC_prototype.xpr
+++ b/FASEC_prototype.xpr
@@ -41,13 +41,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
- <Option Name="WTXSimExportSim" Val="93"/>
- <Option Name="WTModelSimExportSim" Val="93"/>
- <Option Name="WTQuestaExportSim" Val="93"/>
- <Option Name="WTIesExportSim" Val="93"/>
- <Option Name="WTVcsExportSim" Val="93"/>
- <Option Name="WTRivieraExportSim" Val="93"/>
- <Option Name="WTActivehdlExportSim" Val="93"/>
+ <Option Name="WTXSimExportSim" Val="96"/>
+ <Option Name="WTModelSimExportSim" Val="96"/>
+ <Option Name="WTQuestaExportSim" Val="96"/>
+ <Option Name="WTIesExportSim" Val="96"/>
+ <Option Name="WTVcsExportSim" Val="96"/>
+ <Option Name="WTRivieraExportSim" Val="96"/>
+ <Option Name="WTActivehdlExportSim" Val="96"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -131,7 +131,9 @@
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -140,7 +142,9 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design">
<Option Id="Verbose">1</Option>
diff --git a/firmware/system_design_wrapper.bit b/firmware/system_design_wrapper.bit
index efe49b9d0a1f620782e0efe0aed0bc1b56ec4818..2075ab87293326f6b950b48448b1e0270424dbfc 100644
Binary files a/firmware/system_design_wrapper.bit and b/firmware/system_design_wrapper.bit differ
diff --git a/ip_cores/cores b/ip_cores/cores
index 0e406a2e84dc8f47a06e85430288b375ab560c04..55810b7d4b7efda486cb66cfe30c943547f47b45 160000
--- a/ip_cores/cores
+++ b/ip_cores/cores
@@ -1 +1 @@
-Subproject commit 0e406a2e84dc8f47a06e85430288b375ab560c04
+Subproject commit 55810b7d4b7efda486cb66cfe30c943547f47b45
diff --git a/ip_upgrade.log b/ip_upgrade.log
index 1f6b479158c7e36a18f5998d0a48ecea4a4b74f6..707c4fcd6b5148976ca9e0e874ae8e958140aa2d 100644
--- a/ip_upgrade.log
+++ b/ip_upgrade.log
@@ -1,3 +1,45 @@
+Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018
+| Date : Tue Jun 26 20:33:30 2018
+| Host : lapte24154 running 64-bit openSUSE Leap 42.3
+| Command : upgrade_ip
+| Device : xc7z030ffg676-2
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_design_fasec_hwtest_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 (user.org:user:fasec_hwtest:3.2.8) from (Rev. 36) to (Rev. 37)
+
+
+
+
+
+
+Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018
+| Date : Tue Jun 26 20:26:05 2018
+| Host : lapte24154 running 64-bit openSUSE Leap 42.3
+| Command : upgrade_ip
+| Device : xc7z030ffg676-2
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_design_fasec_hwtest_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.2.7 (Rev. 35) to user.org:user:fasec_hwtest:3.2.8 (Rev. 36)
+
+
+
+
+
+
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018
diff --git a/petalinux_hw_export/system_design_wrapper.hdf b/petalinux_hw_export/system_design_wrapper.hdf
index 1ec38669c884e6e044bbf77241a05214caf78c06..be559b8d9411ed794bb6e8bf01caee2e42dad2b6 100644
Binary files a/petalinux_hw_export/system_design_wrapper.hdf and b/petalinux_hw_export/system_design_wrapper.hdf differ
diff --git a/syn/fasec_prototype_project-generation.tcl b/syn/fasec_prototype_project-generation.tcl
index 99faf50ada3399e44af87015d52f8c315507cc24..c9bbeeaa1d95258a5070373f6ea3b0dbfa198b27 100644
--- a/syn/fasec_prototype_project-generation.tcl
+++ b/syn/fasec_prototype_project-generation.tcl
@@ -1,10 +1,10 @@
+#*****************************************************************************************
+# Vivado (TM) v2018.1 (64-bit)
#
-# Vivado (TM) v2016.2 (64-bit)
-#
-# fasec_prototype_fmcs_sfp-gig-eth_xadc_dma.tcl: Tcl script for re-creating project 'FASEC_prototype'
+# fasec_prototype_project-generation.tcl: Tcl script for re-creating project 'FASEC_prototype'
#
-# Generated by Vivado on Wed May 31 14:28:19 CEST 2017
-# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
+# Generated by Vivado on Tue Jun 26 20:45:25 CEST 2018
+# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
@@ -18,18 +18,17 @@
# NOTE: In order to use this script for source control purposes, please make sure that the
# following files are added to the source control system:-
#
-# 1. This project restoration tcl script (fasec_prototype_fmcs_sfp-gig-eth_xadc_dma.tcl) that was generated.
+# 1. This project restoration tcl script (fasec_prototype_project-generation.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
-# <none>
+# "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd"
+# "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc"
#
# 3. The following remote source files that were added to the original project:-
#
-# "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd"
-# "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd"
-# "/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc"
+# <none>
#
#*****************************************************************************************
@@ -41,8 +40,16 @@ if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc
}
+# Set the project name
+set _xil_proj_name_ "FASEC_prototype"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+ set _xil_proj_name_ $::user_project_name
+}
+
variable script_file
-set script_file "fasec_prototype_fmcs_sfp-gig-eth_xadc_dma.tcl"
+set script_file "fasec_prototype_project-generation.tcl"
# Help information for this script
proc help {} {
@@ -55,6 +62,7 @@ proc help {} {
puts "Syntax:"
puts "$script_file"
puts "$script_file -tclargs \[--origin_dir <path>\]"
+ puts "$script_file -tclargs \[--project_name <name>\]"
puts "$script_file -tclargs \[--help\]\n"
puts "Usage:"
puts "Name Description"
@@ -63,17 +71,21 @@ proc help {} {
puts " origin_dir path value is \".\", otherwise, the value"
puts " that was set with the \"-paths_relative_to\" switch"
puts " when this script was generated.\n"
+ puts "\[--project_name <name>\] Create project with the specified name. Default"
+ puts " name is the name of the project from where this"
+ puts " script was generated.\n"
puts "\[--help\] Print help information for this script"
puts "-------------------------------------------------------------------------\n"
exit 0
}
if { $::argc > 0 } {
- for {set i 0} {$i < [llength $::argc]} {incr i} {
+ for {set i 0} {$i < $::argc} {incr i} {
set option [string trim [lindex $::argv $i]]
switch -regexp -- $option {
- "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
- "--help" { help }
+ "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
+ "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+ "--help" { help }
default {
if { [regexp {^-} $option] } {
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
@@ -88,7 +100,7 @@ if { $::argc > 0 } {
set orig_proj_dir "[file normalize "$origin_dir/../"]"
# Create project
-create_project FASEC_prototype ./FASEC_prototype -part xc7z030ffg676-2
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z030ffg676-2
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
@@ -97,14 +109,15 @@ set proj_dir [get_property directory [current_project]]
# None
# Set project properties
-set obj [get_projects FASEC_prototype]
-set_property "default_lib" "xil_defaultlib" $obj
-set_property "generate_ip_upgrade_log" "0" $obj
-set_property "part" "xc7z030ffg676-2" $obj
-set_property "sim.ip.auto_export_scripts" "1" $obj
-set_property "simulator_language" "Mixed" $obj
-set_property "target_language" "VHDL" $obj
-set_property "xpm_libraries" "XPM_CDC XPM_MEMORY" $obj
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "ip_cache_permissions" -value "disable" -objects $obj
+set_property -name "part" -value "xc7z030ffg676-2" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "target_language" -value "VHDL" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj
+set_property -name "xsim.array_display_limit" -value "64" -objects $obj
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
@@ -120,32 +133,24 @@ update_ip_catalog -rebuild
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
+# Import local files from the original project
set files [list \
- "[file normalize "$origin_dir/../FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd"]"\
- "[file normalize "$origin_dir/../FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd"]"\
+ [file normalize "${origin_dir}/../FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd" ]\
]
-add_files -norecurse -fileset $obj $files
+set imported_files [import_files -fileset sources_1 $files]
# Set 'sources_1' fileset file properties for remote files
-set file "$origin_dir/../FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd"
-set file [file normalize $file]
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-if { ![get_property "is_locked" $file_obj] } {
- set_property "generate_synth_checkpoint" "0" $file_obj
-}
+# None
-set file "$origin_dir/../FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd"
-set file [file normalize $file]
+# Set 'sources_1' fileset file properties for local files
+set file "hdl/system_design_wrapper.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
+set_property -name "file_type" -value "VHDL" -objects $file_obj
-# Set 'sources_1' fileset file properties for local files
-# None
-
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
-set_property "top" "system_design_wrapper" $obj
+set_property -name "top" -value "system_design_wrapper" -objects $obj
# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
@@ -157,15 +162,14 @@ set obj [get_filesets constrs_1]
# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/../FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc"]"
-set file_added [add_files -norecurse -fileset $obj $file]
-set file "$origin_dir/../FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc"
-set file [file normalize $file]
+set file_imported [import_files -fileset constrs_1 [list $file]]
+set file "new/fasec_constraints_synth.xdc"
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
-set_property "file_type" "XDC" $file_obj
+set_property -name "file_type" -value "XDC" -objects $file_obj
# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
-set_property "target_constrs_file" "$orig_proj_dir/FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc" $obj
+set_property -name "target_constrs_file" -value "[get_files *new/fasec_constraints_synth.xdc]" -objects $obj
# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
@@ -178,39 +182,1230 @@ set obj [get_filesets sim_1]
# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
-set_property "top" "system_design_wrapper" $obj
-set_property "transport_int_delay" "0" $obj
-set_property "transport_path_delay" "0" $obj
-set_property "xelab.nosort" "1" $obj
-set_property "xelab.unifast" "" $obj
+set_property -name "top" -value "system_design_wrapper" -objects $obj
+
+
+# Adding sources referenced in BDs, if not already added
+
+
+# Proc to create BD system_design
+proc cr_bd_system_design { parentCell } {
+
+ # CHANGE DESIGN NAME HERE
+ set design_name system_design
+
+ common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+ create_bd_design $design_name
+
+ set bCheckIPsPassed 1
+ ##################################################################
+ # CHECK IPs
+ ##################################################################
+ set bCheckIPs 1
+ if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+ xilinx.com:ip:axi_dma:7.1\
+ xilinx.com:ip:axi_uartlite:2.0\
+ cern.ch:ip:axi_wb_i2c_master:3.2.0\
+ user.org:user:fasec_hwtest:3.2.8\
+ xilinx.com:ip:processing_system7:5.5\
+ xilinx.com:ip:proc_sys_reset:5.0\
+ CERN:wrc:wrc_1p_kintex7:3.2.1\
+ xilinx.com:user:xadc_axis_fifo_adapter:1.0\
+ xilinx.com:ip:xadc_wiz:3.3\
+ xilinx.com:ip:xlconcat:2.1\
+ xilinx.com:ip:xlconstant:1.1\
+ "
+
+ set list_ips_missing ""
+ common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+ }
+
+ if { $bCheckIPsPassed != 1 } {
+ common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+ }
+
+ variable script_folder
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+ set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+ set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+ set Vaux0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 ]
+ set Vaux1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux1 ]
+ set Vaux2 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux2 ]
+ set Vaux8 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8 ]
+ set Vaux9 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux9 ]
+ set Vaux10 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux10 ]
+ set Vp_Vn [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn ]
+ set gtp_wr [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sfp_rtl:1.0 gtp_wr ]
+ set i2c_master_fmcx [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 i2c_master_fmcx ]
+ set i2c_master_mdio [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 i2c_master_mdio ]
+
+ # Create ports
+ set FMC1_CLK0C2M_N_o [ create_bd_port -dir O FMC1_CLK0C2M_N_o ]
+ set FMC1_CLK0C2M_P_o [ create_bd_port -dir O FMC1_CLK0C2M_P_o ]
+ set FMC1_CLK0M2C_N_i [ create_bd_port -dir I FMC1_CLK0M2C_N_i ]
+ set FMC1_CLK0M2C_P_i [ create_bd_port -dir I FMC1_CLK0M2C_P_i ]
+ set FMC1_LA_N_b [ create_bd_port -dir IO -from 33 -to 0 FMC1_LA_N_b ]
+ set FMC1_LA_P_b [ create_bd_port -dir IO -from 33 -to 0 FMC1_LA_P_b ]
+ set FMC1_PRSNTM2C_n_i [ create_bd_port -dir I FMC1_PRSNTM2C_n_i ]
+ set FMC2_CLK0C2M_N_o [ create_bd_port -dir O FMC2_CLK0C2M_N_o ]
+ set FMC2_CLK0C2M_P_o [ create_bd_port -dir O FMC2_CLK0C2M_P_o ]
+ set FMC2_CLK0M2C_N_i [ create_bd_port -dir I FMC2_CLK0M2C_N_i ]
+ set FMC2_CLK0M2C_P_i [ create_bd_port -dir I FMC2_CLK0M2C_P_i ]
+ set FMC2_LA_N_b [ create_bd_port -dir IO -from 33 -to 0 FMC2_LA_N_b ]
+ set FMC2_LA_P_b [ create_bd_port -dir IO -from 33 -to 0 FMC2_LA_P_b ]
+ set FMC2_PRSNTM2C_n_i [ create_bd_port -dir I FMC2_PRSNTM2C_n_i ]
+ set clk_25m_vcxo_i [ create_bd_port -dir I clk_25m_vcxo_i ]
+ set dac_cs1_n_o [ create_bd_port -dir O dac_cs1_n_o ]
+ set dac_cs2_n_o [ create_bd_port -dir O dac_cs2_n_o ]
+ set dac_din_o [ create_bd_port -dir O dac_din_o ]
+ set dac_sclk_o [ create_bd_port -dir O dac_sclk_o ]
+ set dig_in1_i [ create_bd_port -dir I dig_in1_i ]
+ set dig_in2_i [ create_bd_port -dir I dig_in2_i ]
+ set dig_in3_n_i [ create_bd_port -dir I dig_in3_n_i ]
+ set dig_in4_n_i [ create_bd_port -dir I dig_in4_n_i ]
+ set dig_out5_n [ create_bd_port -dir O dig_out5_n ]
+ set dig_out6_n [ create_bd_port -dir O -from 0 -to 0 dig_out6_n ]
+ set dig_outs_i [ create_bd_port -dir O -from 3 -to 0 dig_outs_i ]
+ set eeprom_scl [ create_bd_port -dir IO eeprom_scl ]
+ set eeprom_sda [ create_bd_port -dir IO eeprom_sda ]
+ set gtp0_rate_select_b [ create_bd_port -dir IO gtp0_rate_select_b ]
+ set gtp_dedicated_clk_n_i [ create_bd_port -dir I gtp_dedicated_clk_n_i ]
+ set gtp_dedicated_clk_p_i [ create_bd_port -dir I gtp_dedicated_clk_p_i ]
+ set led_col_pl_o [ create_bd_port -dir O -from 3 -to 0 led_col_pl_o ]
+ set led_line_en_pl_o [ create_bd_port -dir O led_line_en_pl_o ]
+ set led_line_pl_o [ create_bd_port -dir O led_line_pl_o ]
+ set osc100_clk_i [ create_bd_port -dir I osc100_clk_i ]
+ set pb_gp_i [ create_bd_port -dir I pb_gp_i ]
+ set thermo_id [ create_bd_port -dir IO thermo_id ]
+ set watchdog_pl_o [ create_bd_port -dir O watchdog_pl_o ]
+
+ # Create instance: axi_dma_0, and set properties
+ set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ]
+ set_property -dict [ list \
+ CONFIG.c_include_mm2s {0} \
+ CONFIG.c_include_s2mm_dre {1} \
+ CONFIG.c_include_sg {0} \
+ CONFIG.c_sg_include_stscntrl_strm {0} \
+ CONFIG.c_sg_use_stsapp_length {0} \
+ ] $axi_dma_0
+
+ # Create instance: axi_interconnect_0, and set properties
+ set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {1} \
+ CONFIG.SYNCHRONIZATION_STAGES {2} \
+ ] $axi_interconnect_0
+
+ # Create instance: axi_interconnect_1, and set properties
+ set axi_interconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {2} \
+ CONFIG.SYNCHRONIZATION_STAGES {2} \
+ ] $axi_interconnect_1
+
+ # Create instance: axi_uartlite_0, and set properties
+ set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
+ set_property -dict [ list \
+ CONFIG.C_BAUDRATE {115200} \
+ ] $axi_uartlite_0
+
+ # Create instance: axi_wb_i2c_master_0, and set properties
+ set axi_wb_i2c_master_0 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.2.0 axi_wb_i2c_master_0 ]
+
+ set_property -dict [ list \
+ CONFIG.NUM_READ_OUTSTANDING {1} \
+ CONFIG.NUM_WRITE_OUTSTANDING {1} \
+ ] [get_bd_intf_pins /axi_wb_i2c_master_0/s00_axi]
+
+ # Create instance: axi_wb_i2c_master_1, and set properties
+ set axi_wb_i2c_master_1 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.2.0 axi_wb_i2c_master_1 ]
+
+ set_property -dict [ list \
+ CONFIG.NUM_READ_OUTSTANDING {1} \
+ CONFIG.NUM_WRITE_OUTSTANDING {1} \
+ ] [get_bd_intf_pins /axi_wb_i2c_master_1/s00_axi]
+
+ # Create instance: axi_wb_i2c_master_2, and set properties
+ set axi_wb_i2c_master_2 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.2.0 axi_wb_i2c_master_2 ]
+
+ set_property -dict [ list \
+ CONFIG.NUM_READ_OUTSTANDING {1} \
+ CONFIG.NUM_WRITE_OUTSTANDING {1} \
+ ] [get_bd_intf_pins /axi_wb_i2c_master_2/s00_axi]
+
+ # Create instance: fasec_hwtest_0, and set properties
+ set fasec_hwtest_0 [ create_bd_cell -type ip -vlnv user.org:user:fasec_hwtest:3.2.8 fasec_hwtest_0 ]
+ set_property -dict [ list \
+ CONFIG.g_FMC1 {EDA-03287} \
+ CONFIG.g_FMC2 {EDA-03287} \
+ ] $fasec_hwtest_0
+
+ set_property -dict [ list \
+ CONFIG.NUM_READ_OUTSTANDING {1} \
+ CONFIG.NUM_WRITE_OUTSTANDING {1} \
+ ] [get_bd_intf_pins /fasec_hwtest_0/S00_AXI]
+
+ # Create instance: processing_system7_0, and set properties
+ set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+ set_property -dict [ list \
+ CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
+ CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \
+ CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \
+ CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
+ CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
+ CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {25.000000} \
+ CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \
+ CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \
+ CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
+ CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666666} \
+ CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
+ CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
+ CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \
+ CONFIG.PCW_CLK0_FREQ {100000000} \
+ CONFIG.PCW_CLK1_FREQ {10000000} \
+ CONFIG.PCW_CLK2_FREQ {10000000} \
+ CONFIG.PCW_CLK3_FREQ {10000000} \
+ CONFIG.PCW_CORE0_FIQ_INTR {0} \
+ CONFIG.PCW_CORE0_IRQ_INTR {0} \
+ CONFIG.PCW_CORE1_FIQ_INTR {0} \
+ CONFIG.PCW_CORE1_IRQ_INTR {0} \
+ CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {800} \
+ CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
+ CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
+ CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
+ CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
+ CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
+ CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
+ CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
+ CONFIG.PCW_DM_WIDTH {4} \
+ CONFIG.PCW_DQS_WIDTH {4} \
+ CONFIG.PCW_DQ_WIDTH {32} \
+ CONFIG.PCW_DUAL_PARALLEL_QSPI_DATA_MODE {x8} \
+ CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \
+ CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
+ CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
+ CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
+ CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \
+ CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+ CONFIG.PCW_ENET0_RESET_ENABLE {0} \
+ CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {External} \
+ CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_ENET_RESET_ENABLE {1} \
+ CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
+ CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
+ CONFIG.PCW_EN_4K_TIMER {0} \
+ CONFIG.PCW_EN_CAN0 {0} \
+ CONFIG.PCW_EN_CAN1 {0} \
+ CONFIG.PCW_EN_CLK0_PORT {1} \
+ CONFIG.PCW_EN_CLK1_PORT {1} \
+ CONFIG.PCW_EN_CLK2_PORT {0} \
+ CONFIG.PCW_EN_CLK3_PORT {0} \
+ CONFIG.PCW_EN_CLKTRIG0_PORT {0} \
+ CONFIG.PCW_EN_CLKTRIG1_PORT {0} \
+ CONFIG.PCW_EN_CLKTRIG2_PORT {0} \
+ CONFIG.PCW_EN_CLKTRIG3_PORT {0} \
+ CONFIG.PCW_EN_DDR {1} \
+ CONFIG.PCW_EN_EMIO_CAN0 {0} \
+ CONFIG.PCW_EN_EMIO_CAN1 {0} \
+ CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
+ CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
+ CONFIG.PCW_EN_EMIO_ENET0 {0} \
+ CONFIG.PCW_EN_EMIO_ENET1 {0} \
+ CONFIG.PCW_EN_EMIO_GPIO {0} \
+ CONFIG.PCW_EN_EMIO_I2C0 {0} \
+ CONFIG.PCW_EN_EMIO_I2C1 {0} \
+ CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
+ CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \
+ CONFIG.PCW_EN_EMIO_PJTAG {0} \
+ CONFIG.PCW_EN_EMIO_SDIO0 {0} \
+ CONFIG.PCW_EN_EMIO_SDIO1 {0} \
+ CONFIG.PCW_EN_EMIO_SPI0 {0} \
+ CONFIG.PCW_EN_EMIO_SPI1 {0} \
+ CONFIG.PCW_EN_EMIO_SRAM_INT {0} \
+ CONFIG.PCW_EN_EMIO_TRACE {0} \
+ CONFIG.PCW_EN_EMIO_TTC0 {1} \
+ CONFIG.PCW_EN_EMIO_TTC1 {0} \
+ CONFIG.PCW_EN_EMIO_UART0 {0} \
+ CONFIG.PCW_EN_EMIO_UART1 {0} \
+ CONFIG.PCW_EN_EMIO_WDT {0} \
+ CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \
+ CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
+ CONFIG.PCW_EN_ENET0 {1} \
+ CONFIG.PCW_EN_ENET1 {0} \
+ CONFIG.PCW_EN_GPIO {1} \
+ CONFIG.PCW_EN_I2C0 {1} \
+ CONFIG.PCW_EN_I2C1 {1} \
+ CONFIG.PCW_EN_MODEM_UART0 {0} \
+ CONFIG.PCW_EN_MODEM_UART1 {0} \
+ CONFIG.PCW_EN_PJTAG {0} \
+ CONFIG.PCW_EN_PTP_ENET0 {0} \
+ CONFIG.PCW_EN_PTP_ENET1 {0} \
+ CONFIG.PCW_EN_QSPI {1} \
+ CONFIG.PCW_EN_RST0_PORT {1} \
+ CONFIG.PCW_EN_RST1_PORT {0} \
+ CONFIG.PCW_EN_RST2_PORT {0} \
+ CONFIG.PCW_EN_RST3_PORT {0} \
+ CONFIG.PCW_EN_SDIO0 {1} \
+ CONFIG.PCW_EN_SDIO1 {0} \
+ CONFIG.PCW_EN_SMC {0} \
+ CONFIG.PCW_EN_SPI0 {0} \
+ CONFIG.PCW_EN_SPI1 {0} \
+ CONFIG.PCW_EN_TRACE {0} \
+ CONFIG.PCW_EN_TTC0 {1} \
+ CONFIG.PCW_EN_TTC1 {0} \
+ CONFIG.PCW_EN_UART0 {0} \
+ CONFIG.PCW_EN_UART1 {0} \
+ CONFIG.PCW_EN_USB0 {0} \
+ CONFIG.PCW_EN_USB1 {0} \
+ CONFIG.PCW_EN_WDT {0} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
+ CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \
+ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {10} \
+ CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200} \
+ CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {125} \
+ CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+ CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \
+ CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {0} \
+ CONFIG.PCW_GP0_NUM_READ_THREADS {4} \
+ CONFIG.PCW_GP0_NUM_WRITE_THREADS {4} \
+ CONFIG.PCW_GP1_EN_MODIFIABLE_TXN {0} \
+ CONFIG.PCW_GP1_NUM_READ_THREADS {4} \
+ CONFIG.PCW_GP1_NUM_WRITE_THREADS {4} \
+ CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \
+ CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
+ CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \
+ CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+ CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
+ CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \
+ CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
+ CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \
+ CONFIG.PCW_I2C0_I2C0_IO {MIO 38 .. 39} \
+ CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_I2C0_RESET_ENABLE {0} \
+ CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \
+ CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
+ CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \
+ CONFIG.PCW_I2C1_I2C1_IO {MIO 28 .. 29} \
+ CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_I2C_RESET_ENABLE {1} \
+ CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
+ CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
+ CONFIG.PCW_IMPORT_BOARD_PRESET {None} \
+ CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
+ CONFIG.PCW_IRQ_F2P_INTR {1} \
+ CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
+ CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_0_PULLUP {disabled} \
+ CONFIG.PCW_MIO_0_SLEW {slow} \
+ CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_10_PULLUP {disabled} \
+ CONFIG.PCW_MIO_10_SLEW {slow} \
+ CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_11_PULLUP {disabled} \
+ CONFIG.PCW_MIO_11_SLEW {slow} \
+ CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_12_PULLUP {disabled} \
+ CONFIG.PCW_MIO_12_SLEW {slow} \
+ CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_13_PULLUP {disabled} \
+ CONFIG.PCW_MIO_13_SLEW {slow} \
+ CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_14_PULLUP {enabled} \
+ CONFIG.PCW_MIO_14_SLEW {slow} \
+ CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_15_PULLUP {enabled} \
+ CONFIG.PCW_MIO_15_SLEW {slow} \
+ CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_16_PULLUP {disabled} \
+ CONFIG.PCW_MIO_16_SLEW {fast} \
+ CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_17_PULLUP {disabled} \
+ CONFIG.PCW_MIO_17_SLEW {fast} \
+ CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_18_PULLUP {disabled} \
+ CONFIG.PCW_MIO_18_SLEW {fast} \
+ CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_19_PULLUP {disabled} \
+ CONFIG.PCW_MIO_19_SLEW {fast} \
+ CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_1_PULLUP {disabled} \
+ CONFIG.PCW_MIO_1_SLEW {slow} \
+ CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_20_PULLUP {disabled} \
+ CONFIG.PCW_MIO_20_SLEW {fast} \
+ CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_21_PULLUP {disabled} \
+ CONFIG.PCW_MIO_21_SLEW {fast} \
+ CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_22_PULLUP {disabled} \
+ CONFIG.PCW_MIO_22_SLEW {fast} \
+ CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_23_PULLUP {disabled} \
+ CONFIG.PCW_MIO_23_SLEW {fast} \
+ CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_24_PULLUP {disabled} \
+ CONFIG.PCW_MIO_24_SLEW {fast} \
+ CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_25_PULLUP {disabled} \
+ CONFIG.PCW_MIO_25_SLEW {fast} \
+ CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_26_PULLUP {disabled} \
+ CONFIG.PCW_MIO_26_SLEW {fast} \
+ CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_27_PULLUP {disabled} \
+ CONFIG.PCW_MIO_27_SLEW {fast} \
+ CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_28_PULLUP {disabled} \
+ CONFIG.PCW_MIO_28_SLEW {fast} \
+ CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_29_PULLUP {disabled} \
+ CONFIG.PCW_MIO_29_SLEW {fast} \
+ CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_2_SLEW {slow} \
+ CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_30_PULLUP {enabled} \
+ CONFIG.PCW_MIO_30_SLEW {fast} \
+ CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_31_PULLUP {enabled} \
+ CONFIG.PCW_MIO_31_SLEW {fast} \
+ CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_32_PULLUP {enabled} \
+ CONFIG.PCW_MIO_32_SLEW {slow} \
+ CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_33_PULLUP {enabled} \
+ CONFIG.PCW_MIO_33_SLEW {slow} \
+ CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_34_PULLUP {enabled} \
+ CONFIG.PCW_MIO_34_SLEW {slow} \
+ CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_35_PULLUP {enabled} \
+ CONFIG.PCW_MIO_35_SLEW {slow} \
+ CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_36_PULLUP {enabled} \
+ CONFIG.PCW_MIO_36_SLEW {slow} \
+ CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_37_PULLUP {enabled} \
+ CONFIG.PCW_MIO_37_SLEW {slow} \
+ CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_38_PULLUP {disabled} \
+ CONFIG.PCW_MIO_38_SLEW {fast} \
+ CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_39_PULLUP {disabled} \
+ CONFIG.PCW_MIO_39_SLEW {fast} \
+ CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_3_SLEW {slow} \
+ CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_40_PULLUP {disabled} \
+ CONFIG.PCW_MIO_40_SLEW {slow} \
+ CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_41_PULLUP {disabled} \
+ CONFIG.PCW_MIO_41_SLEW {slow} \
+ CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_42_PULLUP {disabled} \
+ CONFIG.PCW_MIO_42_SLEW {slow} \
+ CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_43_PULLUP {disabled} \
+ CONFIG.PCW_MIO_43_SLEW {slow} \
+ CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_44_PULLUP {disabled} \
+ CONFIG.PCW_MIO_44_SLEW {slow} \
+ CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_45_PULLUP {disabled} \
+ CONFIG.PCW_MIO_45_SLEW {slow} \
+ CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_46_PULLUP {enabled} \
+ CONFIG.PCW_MIO_46_SLEW {slow} \
+ CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_47_PULLUP {enabled} \
+ CONFIG.PCW_MIO_47_SLEW {slow} \
+ CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_48_PULLUP {disabled} \
+ CONFIG.PCW_MIO_48_SLEW {slow} \
+ CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_49_PULLUP {disabled} \
+ CONFIG.PCW_MIO_49_SLEW {slow} \
+ CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_4_SLEW {slow} \
+ CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_50_PULLUP {enabled} \
+ CONFIG.PCW_MIO_50_SLEW {slow} \
+ CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_51_PULLUP {enabled} \
+ CONFIG.PCW_MIO_51_SLEW {slow} \
+ CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_52_PULLUP {disabled} \
+ CONFIG.PCW_MIO_52_SLEW {slow} \
+ CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
+ CONFIG.PCW_MIO_53_PULLUP {enabled} \
+ CONFIG.PCW_MIO_53_SLEW {slow} \
+ CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_5_SLEW {slow} \
+ CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_6_SLEW {slow} \
+ CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_7_SLEW {slow} \
+ CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_8_SLEW {slow} \
+ CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_9_PULLUP {disabled} \
+ CONFIG.PCW_MIO_9_SLEW {slow} \
+ CONFIG.PCW_MIO_PRIMITIVE {54} \
+ CONFIG.PCW_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#I2C 1#I2C 1#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#I2C 0#I2C 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \
+ CONFIG.PCW_MIO_TREE_SIGNALS {qspi1_ss_b#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#qspi1_sclk#qspi1_io[0]#qspi1_io[1]#qspi1_io[2]#qspi1_io[3]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#scl#sda#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#scl#sda#clk#cmd#data[0]#data[1]#data[2]#data[3]#cd#wp#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \
+ CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \
+ CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \
+ CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \
+ CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \
+ CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \
+ CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \
+ CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \
+ CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \
+ CONFIG.PCW_NAND_CYCLES_T_AR {1} \
+ CONFIG.PCW_NAND_CYCLES_T_CLR {1} \
+ CONFIG.PCW_NAND_CYCLES_T_RC {11} \
+ CONFIG.PCW_NAND_CYCLES_T_REA {1} \
+ CONFIG.PCW_NAND_CYCLES_T_RR {1} \
+ CONFIG.PCW_NAND_CYCLES_T_WC {11} \
+ CONFIG.PCW_NAND_CYCLES_T_WP {1} \
+ CONFIG.PCW_NOR_CS0_T_CEOE {1} \
+ CONFIG.PCW_NOR_CS0_T_PC {1} \
+ CONFIG.PCW_NOR_CS0_T_RC {11} \
+ CONFIG.PCW_NOR_CS0_T_TR {1} \
+ CONFIG.PCW_NOR_CS0_T_WC {11} \
+ CONFIG.PCW_NOR_CS0_T_WP {1} \
+ CONFIG.PCW_NOR_CS0_WE_TIME {0} \
+ CONFIG.PCW_NOR_CS1_T_CEOE {1} \
+ CONFIG.PCW_NOR_CS1_T_PC {1} \
+ CONFIG.PCW_NOR_CS1_T_RC {11} \
+ CONFIG.PCW_NOR_CS1_T_TR {1} \
+ CONFIG.PCW_NOR_CS1_T_WC {11} \
+ CONFIG.PCW_NOR_CS1_T_WP {1} \
+ CONFIG.PCW_NOR_CS1_WE_TIME {0} \
+ CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
+ CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
+ CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \
+ CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \
+ CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \
+ CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \
+ CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \
+ CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \
+ CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \
+ CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \
+ CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \
+ CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \
+ CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
+ CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \
+ CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
+ CONFIG.PCW_P2F_ENET0_INTR {0} \
+ CONFIG.PCW_P2F_GPIO_INTR {0} \
+ CONFIG.PCW_P2F_I2C0_INTR {0} \
+ CONFIG.PCW_P2F_I2C1_INTR {0} \
+ CONFIG.PCW_P2F_QSPI_INTR {0} \
+ CONFIG.PCW_P2F_SDIO0_INTR {0} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.109} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.098} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.100} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.106} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.022} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.007} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.008} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.015} \
+ CONFIG.PCW_PACKAGE_NAME {ffg676} \
+ CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
+ CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \
+ CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
+ CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
+ CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
+ CONFIG.PCW_PS7_SI_REV {PRODUCTION} \
+ CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
+ CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
+ CONFIG.PCW_QSPI_GRP_IO1_ENABLE {1} \
+ CONFIG.PCW_QSPI_GRP_IO1_IO {MIO 0 9 .. 13} \
+ CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {0} \
+ CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
+ CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFDFFFFFF} \
+ CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {125} \
+ CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
+ CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
+ CONFIG.PCW_SD0_GRP_CD_IO {MIO 46} \
+ CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
+ CONFIG.PCW_SD0_GRP_WP_ENABLE {1} \
+ CONFIG.PCW_SD0_GRP_WP_IO {MIO 47} \
+ CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
+ CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \
+ CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \
+ CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {25} \
+ CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_SMC_CYCLE_T0 {NA} \
+ CONFIG.PCW_SMC_CYCLE_T1 {NA} \
+ CONFIG.PCW_SMC_CYCLE_T2 {NA} \
+ CONFIG.PCW_SMC_CYCLE_T3 {NA} \
+ CONFIG.PCW_SMC_CYCLE_T4 {NA} \
+ CONFIG.PCW_SMC_CYCLE_T5 {NA} \
+ CONFIG.PCW_SMC_CYCLE_T6 {NA} \
+ CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \
+ CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \
+ CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \
+ CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
+ CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \
+ CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \
+ CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \
+ CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_TTC0_TTC0_IO {EMIO} \
+ CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_UART_PERIPHERAL_VALID {0} \
+ CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
+ CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
+ CONFIG.PCW_UIPARAM_DDR_AL {0} \
+ CONFIG.PCW_UIPARAM_DDR_BL {8} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.310} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.310} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.368} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.368} \
+ CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {97.8165} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {97.8165} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {97.8165} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {97.8165} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {119.765} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {90.906} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {106.248} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.2035} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.069} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.069} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.186} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.185} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {120.1555} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {97.811} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {102.5285} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {113.5445} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
+ CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \
+ CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
+ CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
+ CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
+ CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
+ CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
+ CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
+ CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NONE} \
+ CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_USB_RESET_ENABLE {0} \
+ CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
+ CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \
+ CONFIG.PCW_USE_AXI_NONSECURE {0} \
+ CONFIG.PCW_USE_CORESIGHT {0} \
+ CONFIG.PCW_USE_CROSS_TRIGGER {0} \
+ CONFIG.PCW_USE_CR_FABRIC {1} \
+ CONFIG.PCW_USE_DDR_BYPASS {0} \
+ CONFIG.PCW_USE_DEBUG {0} \
+ CONFIG.PCW_USE_DMA0 {0} \
+ CONFIG.PCW_USE_DMA1 {0} \
+ CONFIG.PCW_USE_DMA2 {0} \
+ CONFIG.PCW_USE_DMA3 {0} \
+ CONFIG.PCW_USE_EXPANDED_IOP {0} \
+ CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
+ CONFIG.PCW_USE_HIGH_OCM {0} \
+ CONFIG.PCW_USE_M_AXI_GP0 {1} \
+ CONFIG.PCW_USE_M_AXI_GP1 {1} \
+ CONFIG.PCW_USE_PROC_EVENT_BUS {0} \
+ CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \
+ CONFIG.PCW_USE_S_AXI_ACP {0} \
+ CONFIG.PCW_USE_S_AXI_GP0 {1} \
+ CONFIG.PCW_USE_S_AXI_GP1 {0} \
+ CONFIG.PCW_USE_S_AXI_HP0 {0} \
+ CONFIG.PCW_USE_S_AXI_HP1 {0} \
+ CONFIG.PCW_USE_S_AXI_HP2 {0} \
+ CONFIG.PCW_USE_S_AXI_HP3 {0} \
+ CONFIG.PCW_USE_TRACE {0} \
+ CONFIG.PCW_VALUE_SILVERSION {3} \
+ CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
+ ] $processing_system7_0
+
+ # Create instance: processing_system7_0_axi_periph, and set properties
+ set processing_system7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 processing_system7_0_axi_periph ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {8} \
+ CONFIG.NUM_SI {1} \
+ CONFIG.SYNCHRONIZATION_STAGES {2} \
+ ] $processing_system7_0_axi_periph
+
+ # Create instance: rst_processing_system7_0_100M, and set properties
+ set rst_processing_system7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_processing_system7_0_100M ]
+
+ # Create instance: rst_wrc_1p_kintex7_0_62M, and set properties
+ set rst_wrc_1p_kintex7_0_62M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_wrc_1p_kintex7_0_62M ]
+
+ # Create instance: wrc_1p_kintex7_0, and set properties
+ set wrc_1p_kintex7_0 [ create_bd_cell -type ip -vlnv CERN:wrc:wrc_1p_kintex7:3.2.1 wrc_1p_kintex7_0 ]
+
+ set_property -dict [ list \
+ CONFIG.NUM_READ_OUTSTANDING {1} \
+ CONFIG.NUM_WRITE_OUTSTANDING {1} \
+ ] [get_bd_intf_pins /wrc_1p_kintex7_0/s00_axi]
+
+ # Create instance: xadc_axis_fifo_adapter_0, and set properties
+ set xadc_axis_fifo_adapter_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:xadc_axis_fifo_adapter:1.0 xadc_axis_fifo_adapter_0 ]
+ set_property -dict [ list \
+ CONFIG.C_BASEADDR {0x43C40000} \
+ CONFIG.C_HIGHADDR {0x43C4FFFF} \
+ ] $xadc_axis_fifo_adapter_0
+
+ set_property -dict [ list \
+ CONFIG.SUPPORTS_NARROW_BURST {0} \
+ CONFIG.NUM_READ_OUTSTANDING {1} \
+ CONFIG.NUM_WRITE_OUTSTANDING {1} \
+ CONFIG.MAX_BURST_LENGTH {1} \
+ ] [get_bd_intf_pins /xadc_axis_fifo_adapter_0/S_AXI]
+
+ # Create instance: xadc_wiz_0, and set properties
+ set xadc_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_wiz_0 ]
+ set_property -dict [ list \
+ CONFIG.BIPOLAR_VAUXP0_VAUXN0 {true} \
+ CONFIG.BIPOLAR_VAUXP10_VAUXN10 {true} \
+ CONFIG.BIPOLAR_VAUXP1_VAUXN1 {true} \
+ CONFIG.BIPOLAR_VAUXP2_VAUXN2 {true} \
+ CONFIG.BIPOLAR_VAUXP8_VAUXN8 {true} \
+ CONFIG.BIPOLAR_VAUXP9_VAUXN9 {true} \
+ CONFIG.CHANNEL_ENABLE_TEMPERATURE {true} \
+ CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} \
+ CONFIG.CHANNEL_ENABLE_VAUXP10_VAUXN10 {true} \
+ CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 {true} \
+ CONFIG.CHANNEL_ENABLE_VAUXP2_VAUXN2 {true} \
+ CONFIG.CHANNEL_ENABLE_VAUXP8_VAUXN8 {true} \
+ CONFIG.CHANNEL_ENABLE_VAUXP9_VAUXN9 {true} \
+ CONFIG.CHANNEL_ENABLE_VCCINT {true} \
+ CONFIG.CHANNEL_ENABLE_VP_VN {false} \
+ CONFIG.ENABLE_AXI4STREAM {true} \
+ CONFIG.ENABLE_RESET {false} \
+ CONFIG.ENABLE_VCCDDRO_ALARM {true} \
+ CONFIG.ENABLE_VCCPAUX_ALARM {true} \
+ CONFIG.ENABLE_VCCPINT_ALARM {true} \
+ CONFIG.EXTERNAL_MUX_CHANNEL {VP_VN} \
+ CONFIG.FIFO_DEPTH {1017} \
+ CONFIG.INTERFACE_SELECTION {Enable_AXI} \
+ CONFIG.OT_ALARM {false} \
+ CONFIG.SEQUENCER_MODE {Off} \
+ CONFIG.SINGLE_CHANNEL_SELECTION {TEMPERATURE} \
+ CONFIG.USER_TEMP_ALARM {false} \
+ CONFIG.VCCAUX_ALARM {false} \
+ CONFIG.VCCINT_ALARM {false} \
+ CONFIG.VCCINT_ALARM_LOWER {0.97} \
+ CONFIG.VCCINT_ALARM_UPPER {1.03} \
+ CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} \
+ ] $xadc_wiz_0
+
+ set_property -dict [ list \
+ CONFIG.TDATA_NUM_BYTES {2} \
+ CONFIG.TID_WIDTH {5} \
+ CONFIG.HAS_TREADY {1} \
+ ] [get_bd_intf_pins /xadc_wiz_0/M_AXIS]
+
+ set_property -dict [ list \
+ CONFIG.NUM_READ_OUTSTANDING {1} \
+ CONFIG.NUM_WRITE_OUTSTANDING {1} \
+ ] [get_bd_intf_pins /xadc_wiz_0/s_axi_lite]
+
+ # Create instance: xlconcat_0, and set properties
+ set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {7} \
+ ] $xlconcat_0
+
+ # Create instance: xlconstant_0, and set properties
+ set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+ set_property -dict [ list \
+ CONFIG.CONST_WIDTH {16} \
+ ] $xlconstant_0
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ CONFIG.CONST_WIDTH {1} \
+ ] $xlconstant_1
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect_1/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP1]
+ connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_ports Vaux0] [get_bd_intf_pins xadc_wiz_0/Vaux0]
+ connect_bd_intf_net -intf_net Vaux10_1 [get_bd_intf_ports Vaux10] [get_bd_intf_pins xadc_wiz_0/Vaux10]
+ connect_bd_intf_net -intf_net Vaux1_1 [get_bd_intf_ports Vaux1] [get_bd_intf_pins xadc_wiz_0/Vaux1]
+ connect_bd_intf_net -intf_net Vaux2_1 [get_bd_intf_ports Vaux2] [get_bd_intf_pins xadc_wiz_0/Vaux2]
+ connect_bd_intf_net -intf_net Vaux8_1 [get_bd_intf_ports Vaux8] [get_bd_intf_pins xadc_wiz_0/Vaux8]
+ connect_bd_intf_net -intf_net Vaux9_1 [get_bd_intf_ports Vaux9] [get_bd_intf_pins xadc_wiz_0/Vaux9]
+ connect_bd_intf_net -intf_net Vp_Vn_1 [get_bd_intf_ports Vp_Vn] [get_bd_intf_pins xadc_wiz_0/Vp_Vn]
+ connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_0/M_AXI_S2MM] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
+ connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_GP0]
+ connect_bd_intf_net -intf_net axi_interconnect_1_M00_AXI [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins wrc_1p_kintex7_0/s00_axi]
+ connect_bd_intf_net -intf_net axi_wb_i2c_master_1_i2c_master [get_bd_intf_ports i2c_master_mdio] [get_bd_intf_pins axi_wb_i2c_master_1/i2c_master]
+ connect_bd_intf_net -intf_net axi_wb_i2c_master_2_i2c_master [get_bd_intf_ports i2c_master_fmcx] [get_bd_intf_pins axi_wb_i2c_master_2/i2c_master]
+ connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
+ connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
+ connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins processing_system7_0_axi_periph/S00_AXI]
+ connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_wb_i2c_master_2/s00_axi] [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI]
+ connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_wb_i2c_master_0/s00_axi] [get_bd_intf_pins processing_system7_0_axi_periph/M01_AXI]
+ connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M02_AXI [get_bd_intf_pins fasec_hwtest_0/S00_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M02_AXI]
+ connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M03_AXI [get_bd_intf_pins axi_wb_i2c_master_1/s00_axi] [get_bd_intf_pins processing_system7_0_axi_periph/M03_AXI]
+ connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M04_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M04_AXI] [get_bd_intf_pins xadc_wiz_0/s_axi_lite]
+ connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M05_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M05_AXI] [get_bd_intf_pins xadc_axis_fifo_adapter_0/S_AXI]
+ connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M06_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins processing_system7_0_axi_periph/M06_AXI]
+ connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M07_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M07_AXI]
+ connect_bd_intf_net -intf_net wrc_1p_kintex7_0_gtp_wr [get_bd_intf_ports gtp_wr] [get_bd_intf_pins wrc_1p_kintex7_0/gtp_wr]
+ connect_bd_intf_net -intf_net xadc_axis_fifo_adapter_0_M_AXIS [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] [get_bd_intf_pins xadc_axis_fifo_adapter_0/M_AXIS]
+ connect_bd_intf_net -intf_net xadc_wiz_0_M_AXIS [get_bd_intf_pins xadc_axis_fifo_adapter_0/S_AXIS] [get_bd_intf_pins xadc_wiz_0/M_AXIS]
+
+ # Create port connections
+ connect_bd_net -net FMC1_CLK0M2C_N_i_1 [get_bd_ports FMC1_CLK0M2C_N_i] [get_bd_pins fasec_hwtest_0/FMC1_CLK0M2C_N_i]
+ connect_bd_net -net FMC1_CLK0M2C_P_i_1 [get_bd_ports FMC1_CLK0M2C_P_i] [get_bd_pins fasec_hwtest_0/FMC1_CLK0M2C_P_i]
+ connect_bd_net -net FMC1_PRSNTM2C_n_i_1 [get_bd_ports FMC1_PRSNTM2C_n_i] [get_bd_pins fasec_hwtest_0/FMC1_PRSNTM2C_n_i]
+ connect_bd_net -net FMC2_CLK0M2C_N_i_1 [get_bd_ports FMC2_CLK0M2C_N_i] [get_bd_pins fasec_hwtest_0/FMC2_CLK0M2C_N_i]
+ connect_bd_net -net FMC2_CLK0M2C_P_i_1 [get_bd_ports FMC2_CLK0M2C_P_i] [get_bd_pins fasec_hwtest_0/FMC2_CLK0M2C_P_i]
+ connect_bd_net -net FMC2_PRSNTM2C_n_i_1 [get_bd_ports FMC2_PRSNTM2C_n_i] [get_bd_pins fasec_hwtest_0/FMC2_PRSNTM2C_n_i]
+ connect_bd_net -net Net2 [get_bd_ports eeprom_scl] [get_bd_pins wrc_1p_kintex7_0/fpga_scl_b]
+ connect_bd_net -net Net3 [get_bd_ports eeprom_sda] [get_bd_pins wrc_1p_kintex7_0/fpga_sda_b]
+ connect_bd_net -net Net4 [get_bd_ports FMC2_LA_P_b] [get_bd_pins fasec_hwtest_0/FMC2_LA_P_b]
+ connect_bd_net -net Net5 [get_bd_ports FMC2_LA_N_b] [get_bd_pins fasec_hwtest_0/FMC2_LA_N_b]
+ connect_bd_net -net Net6 [get_bd_ports FMC1_LA_P_b] [get_bd_pins fasec_hwtest_0/FMC1_LA_P_b]
+ connect_bd_net -net Net7 [get_bd_ports FMC1_LA_N_b] [get_bd_pins fasec_hwtest_0/FMC1_LA_N_b]
+ connect_bd_net -net Net10 [get_bd_ports thermo_id] [get_bd_pins wrc_1p_kintex7_0/thermo_id]
+ connect_bd_net -net Net11 [get_bd_ports gtp0_rate_select_b] [get_bd_pins wrc_1p_kintex7_0/gtp0_rate_select_b]
+ connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins axi_dma_0/s2mm_introut] [get_bd_pins xlconcat_0/In0]
+ connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins xlconcat_0/In4]
+ connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins wrc_1p_kintex7_0/uart_rxd_i]
+ connect_bd_net -net axi_wb_i2c_master_0_axi_int_o [get_bd_pins axi_wb_i2c_master_0/axi_int_o] [get_bd_pins xlconcat_0/In3]
+ connect_bd_net -net axi_wb_i2c_master_2_axi_int_o [get_bd_pins axi_wb_i2c_master_2/axi_int_o] [get_bd_pins xlconcat_0/In2]
+ connect_bd_net -net clk_25m_vcxo_i_1 [get_bd_ports clk_25m_vcxo_i] [get_bd_pins wrc_1p_kintex7_0/clk_20m_vcxo_i] [get_bd_pins wrc_1p_kintex7_0/ext_clk_i]
+ connect_bd_net -net dig_in1_i_1 [get_bd_ports dig_in1_i] [get_bd_pins fasec_hwtest_0/dig_in1_i]
+ connect_bd_net -net dig_in2_i_1 [get_bd_ports dig_in2_i] [get_bd_pins fasec_hwtest_0/dig_in2_i]
+ connect_bd_net -net dig_in3_n_i_1 [get_bd_ports dig_in3_n_i] [get_bd_pins fasec_hwtest_0/dig_in3_n_i]
+ connect_bd_net -net dig_in4_n_i_1 [get_bd_ports dig_in4_n_i] [get_bd_pins fasec_hwtest_0/dig_in4_n_i]
+ connect_bd_net -net fasec_hwtest_0_FMC1_CLK0C2M_N_o [get_bd_ports FMC1_CLK0C2M_N_o] [get_bd_pins fasec_hwtest_0/FMC1_CLK0C2M_N_o]
+ connect_bd_net -net fasec_hwtest_0_FMC1_CLK0C2M_P_o [get_bd_ports FMC1_CLK0C2M_P_o] [get_bd_pins fasec_hwtest_0/FMC1_CLK0C2M_P_o]
+ connect_bd_net -net fasec_hwtest_0_FMC2_CLK0C2M_N_o [get_bd_ports FMC2_CLK0C2M_N_o] [get_bd_pins fasec_hwtest_0/FMC2_CLK0C2M_N_o]
+ connect_bd_net -net fasec_hwtest_0_FMC2_CLK0C2M_P_o [get_bd_ports FMC2_CLK0C2M_P_o] [get_bd_pins fasec_hwtest_0/FMC2_CLK0C2M_P_o]
+ connect_bd_net -net fasec_hwtest_0_dig_out5_n [get_bd_ports dig_out5_n] [get_bd_pins fasec_hwtest_0/dig_out5_n]
+ connect_bd_net -net fasec_hwtest_0_dig_out6_n [get_bd_ports dig_out6_n] [get_bd_pins fasec_hwtest_0/dig_out6_n]
+ connect_bd_net -net fasec_hwtest_0_dig_outs_i [get_bd_ports dig_outs_i] [get_bd_pins fasec_hwtest_0/dig_outs_i]
+ connect_bd_net -net fasec_hwtest_0_intr_led_o [get_bd_pins fasec_hwtest_0/intr_led_o] [get_bd_pins xlconcat_0/In6]
+ connect_bd_net -net fasec_hwtest_0_intr_o [get_bd_pins fasec_hwtest_0/intr_o] [get_bd_pins xlconcat_0/In5]
+ connect_bd_net -net fasec_hwtest_0_led_col_pl_o [get_bd_ports led_col_pl_o] [get_bd_pins fasec_hwtest_0/led_col_pl_o]
+ connect_bd_net -net fasec_hwtest_0_led_line_en_pl_o [get_bd_ports led_line_en_pl_o] [get_bd_pins fasec_hwtest_0/led_line_en_pl_o]
+ connect_bd_net -net fasec_hwtest_0_led_line_pl_o [get_bd_ports led_line_pl_o] [get_bd_pins fasec_hwtest_0/led_line_pl_o]
+ connect_bd_net -net fasec_hwtest_0_watchdog_pl_o [get_bd_ports watchdog_pl_o] [get_bd_pins fasec_hwtest_0/watchdog_pl_o]
+ connect_bd_net -net gtp_dedicated_clk_n_i_1 [get_bd_ports gtp_dedicated_clk_n_i] [get_bd_pins wrc_1p_kintex7_0/gtp_dedicated_clk_n_i]
+ connect_bd_net -net gtp_dedicated_clk_p_i_1 [get_bd_ports gtp_dedicated_clk_p_i] [get_bd_pins wrc_1p_kintex7_0/gtp_dedicated_clk_p_i]
+ connect_bd_net -net osc100_clk_i_1 [get_bd_ports osc100_clk_i] [get_bd_pins fasec_hwtest_0/osc100_clk_i]
+ connect_bd_net -net pb_gp_i_1 [get_bd_ports pb_gp_i] [get_bd_pins fasec_hwtest_0/pb_gp_n_i] [get_bd_pins wrc_1p_kintex7_0/button_rst_n_i]
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_1/M01_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_wb_i2c_master_0/s00_axi_aclk] [get_bd_pins axi_wb_i2c_master_1/s00_axi_aclk] [get_bd_pins axi_wb_i2c_master_2/s00_axi_aclk] [get_bd_pins fasec_hwtest_0/ps_clk_i] [get_bd_pins fasec_hwtest_0/s00_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/M01_ACLK] [get_bd_pins processing_system7_0_axi_periph/M02_ACLK] [get_bd_pins processing_system7_0_axi_periph/M03_ACLK] [get_bd_pins processing_system7_0_axi_periph/M04_ACLK] [get_bd_pins processing_system7_0_axi_periph/M05_ACLK] [get_bd_pins processing_system7_0_axi_periph/M06_ACLK] [get_bd_pins processing_system7_0_axi_periph/M07_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK] [get_bd_pins rst_processing_system7_0_100M/slowest_sync_clk] [get_bd_pins xadc_axis_fifo_adapter_0/M_AXIS_ACLK] [get_bd_pins xadc_axis_fifo_adapter_0/S_AXIS_ACLK] [get_bd_pins xadc_axis_fifo_adapter_0/S_AXI_ACLK] [get_bd_pins xadc_wiz_0/s_axi_aclk] [get_bd_pins xadc_wiz_0/s_axis_aclk]
+ connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_processing_system7_0_100M/ext_reset_in] [get_bd_pins rst_wrc_1p_kintex7_0_62M/ext_reset_in]
+ connect_bd_net -net rst_processing_system7_0_100M_interconnect_aresetn [get_bd_pins processing_system7_0_axi_periph/ARESETN] [get_bd_pins rst_processing_system7_0_100M/interconnect_aresetn]
+ connect_bd_net -net rst_processing_system7_0_100M_peripheral_aresetn [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_1/M01_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_wb_i2c_master_0/s00_axi_aresetn] [get_bd_pins axi_wb_i2c_master_1/s00_axi_aresetn] [get_bd_pins axi_wb_i2c_master_2/s00_axi_aresetn] [get_bd_pins fasec_hwtest_0/s00_axi_aresetn] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M01_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M02_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M03_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M04_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M05_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M06_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M07_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_processing_system7_0_100M/peripheral_aresetn] [get_bd_pins xadc_axis_fifo_adapter_0/AXIS_RESET_N] [get_bd_pins xadc_axis_fifo_adapter_0/S_AXI_ARESETN] [get_bd_pins xadc_wiz_0/s_axi_aresetn]
+ connect_bd_net -net rst_wrc_1p_kintex7_0_62M_interconnect_aresetn [get_bd_pins axi_interconnect_1/ARESETN] [get_bd_pins rst_wrc_1p_kintex7_0_62M/interconnect_aresetn]
+ connect_bd_net -net rst_wrc_1p_kintex7_0_62M_peripheral_aresetn [get_bd_pins axi_interconnect_1/M00_ARESETN] [get_bd_pins axi_interconnect_1/S00_ARESETN] [get_bd_pins rst_wrc_1p_kintex7_0_62M/peripheral_aresetn] [get_bd_pins wrc_1p_kintex7_0/s00_axi_aresetn]
+ connect_bd_net -net wrc_1p_kintex7_0_clk_ref_o [get_bd_pins fasec_hwtest_0/FMC1_GP0_i] [get_bd_pins wrc_1p_kintex7_0/clk_ref_o]
+ connect_bd_net -net wrc_1p_kintex7_0_clk_rx_rbclk_o [get_bd_pins fasec_hwtest_0/FMC1_GP2_i] [get_bd_pins wrc_1p_kintex7_0/clk_rx_rbclk_o]
+ connect_bd_net -net wrc_1p_kintex7_0_dac_cs1_n_o [get_bd_ports dac_cs1_n_o] [get_bd_pins wrc_1p_kintex7_0/dac_cs1_n_o]
+ connect_bd_net -net wrc_1p_kintex7_0_dac_cs2_n_o [get_bd_ports dac_cs2_n_o] [get_bd_pins wrc_1p_kintex7_0/dac_cs2_n_o]
+ connect_bd_net -net wrc_1p_kintex7_0_dac_din_o [get_bd_ports dac_din_o] [get_bd_pins wrc_1p_kintex7_0/dac_din_o]
+ connect_bd_net -net wrc_1p_kintex7_0_dac_sclk_o [get_bd_ports dac_sclk_o] [get_bd_pins wrc_1p_kintex7_0/dac_sclk_o]
+ connect_bd_net -net wrc_1p_kintex7_0_gtp0_activity_led_o [get_bd_pins fasec_hwtest_0/FMC2_GP2_i] [get_bd_pins wrc_1p_kintex7_0/gtp0_activity_led_o]
+ connect_bd_net -net wrc_1p_kintex7_0_gtp0_link_led_o [get_bd_pins fasec_hwtest_0/FMC2_GP0_i] [get_bd_pins wrc_1p_kintex7_0/gtp0_link_led_o]
+ connect_bd_net -net wrc_1p_kintex7_0_gtp0_synced_led_o [get_bd_pins fasec_hwtest_0/FMC2_GP1_i] [get_bd_pins wrc_1p_kintex7_0/gtp0_synced_led_o]
+ connect_bd_net -net wrc_1p_kintex7_0_pps_o [get_bd_pins fasec_hwtest_0/FMC1_GP1_i] [get_bd_pins wrc_1p_kintex7_0/pps_o]
+ connect_bd_net -net wrc_1p_kintex7_0_s00_axi_aclk_o [get_bd_pins axi_interconnect_1/ACLK] [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins rst_wrc_1p_kintex7_0_62M/slowest_sync_clk] [get_bd_pins wrc_1p_kintex7_0/s00_axi_aclk_o]
+ connect_bd_net -net wrc_1p_kintex7_0_uart_txd_o [get_bd_pins axi_uartlite_0/rx] [get_bd_pins wrc_1p_kintex7_0/uart_txd_o]
+ connect_bd_net -net xadc_wiz_0_ip2intc_irpt [get_bd_pins xadc_wiz_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In1]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout]
+ connect_bd_net -net xlconstant_0_dout [get_bd_pins fasec_hwtest_0/gem_status_vector_i] [get_bd_pins xlconstant_0/dout]
+ connect_bd_net -net xlconstant_1_dout [get_bd_pins wrc_1p_kintex7_0/pps_i] [get_bd_pins xlconstant_1/dout]
+
+ # Create address segments
+ create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_DDR_LOWOCM] SEG_processing_system7_0_GP0_DDR_LOWOCM
+ create_bd_addr_seg -range 0x00020000 -offset 0xE0000000 [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_IOP] SEG_processing_system7_0_GP0_IOP
+ create_bd_addr_seg -range 0x00020000 -offset 0xFC000000 [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_QSPI_LINEAR] SEG_processing_system7_0_GP0_QSPI_LINEAR
+ create_bd_addr_seg -range 0x00010000 -offset 0x40400000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] SEG_axi_dma_0_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x42C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_wb_i2c_master_0/s00_axi/Reg] SEG_axi_wb_i2c_master_0_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_wb_i2c_master_1/s00_axi/Reg] SEG_axi_wb_i2c_master_1_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_wb_i2c_master_2/s00_axi/Reg] SEG_axi_wb_i2c_master_2_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs fasec_hwtest_0/S00_AXI/S00_AXI_reg] SEG_fasec_hwtest_0_S00_AXI_reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x80000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs wrc_1p_kintex7_0/s00_axi/Reg] SEG_wrc_1p_kintex7_0_Reg
+ create_bd_addr_seg -range 0x00010000 -offset 0x43C40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs xadc_axis_fifo_adapter_0/S_AXI/reg0] SEG_xadc_axis_fifo_adapter_0_reg0
+ create_bd_addr_seg -range 0x00010000 -offset 0x43C50000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs xadc_wiz_0/s_axi_lite/Reg] SEG_xadc_wiz_0_Reg
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+ save_bd_design
+ close_bd_design $design_name
+}
+# End of cr_bd_system_design()
+cr_bd_system_design ""
+set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files system_design.bd ]
# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
- create_run -name synth_1 -part xc7z030ffg676-2 -flow {Vivado Synthesis 2016} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
+ create_run -name synth_1 -part xc7z030ffg676-2 -flow {Vivado Synthesis 2016} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
} else {
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
set_property flow "Vivado Synthesis 2016" [get_runs synth_1]
}
set obj [get_runs synth_1]
-set_property "part" "xc7z030ffg676-2" $obj
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+ create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "needs_refresh" -value "1" -objects $obj
+set_property -name "part" -value "xc7z030ffg676-2" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
# set the current synth run
current_run -synthesis [get_runs synth_1]
# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
- create_run -name impl_1 -part xc7z030ffg676-2 -flow {Vivado Implementation 2016} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
+ create_run -name impl_1 -part xc7z030ffg676-2 -flow {Vivado Implementation 2016} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
} else {
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
set_property flow "Vivado Implementation 2016" [get_runs impl_1]
}
set obj [get_runs impl_1]
-set_property "part" "xc7z030ffg676-2" $obj
-set_property "steps.write_bitstream.tcl.post" "$proj_dir/FASEC_prototype.srcs/tcl/copy_bitstream.tcl" $obj
-set_property "steps.write_bitstream.args.readback_file" "0" $obj
-set_property "steps.write_bitstream.args.verbose" "0" $obj
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+ create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+ create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+ create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+ create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+ create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+ create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+ create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+ create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+ create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+ create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+ create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+ create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+ create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+ create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+ create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+ create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+ create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+ create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+ create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+ create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+ create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+ create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs impl_1]
+set_property -name "part" -value "xc7z030ffg676-2" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.opt_design.args.verbose" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.tcl.post" -value "$proj_dir/FASEC_prototype.srcs/tcl/copy_bitstream.tcl" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
# set the current impl run
current_run -implementation [get_runs impl_1]
-puts "INFO: Project created:FASEC_prototype"
+puts "INFO: Project created:${_xil_proj_name_}"