diff --git a/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd b/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd
index 9ca0a5c7f7535f90251e5e1d43ae3658716bf6ca..2e691d93a743187fcb9361ddc3a192aa7c5b5efc 100644
--- a/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd
@@ -1,7 +1,7 @@
 --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------
 --Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
---Date        : Thu Mar 23 21:34:22 2017
+--Date        : Mon Mar 27 12:41:35 2017
 --Host        : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
 --Command     : generate_target system_design.bd
 --Design      : system_design
@@ -3608,8 +3608,6 @@ entity system_design is
     Vp_Vn_v_n : in STD_LOGIC;
     Vp_Vn_v_p : in STD_LOGIC;
     clk_25m_vcxo_i : in STD_LOGIC;
-    clk_aux_n_i : in STD_LOGIC;
-    clk_aux_p_i : in STD_LOGIC;
     dac_cs1_n_o : out STD_LOGIC;
     dac_cs2_n_o : out STD_LOGIC;
     dac_din_o : out STD_LOGIC;
@@ -3646,10 +3644,10 @@ entity system_design is
     thermo_id : inout STD_LOGIC;
     watchdog_pl_o : out STD_LOGIC
   );
-  attribute CORE_GENERATION_INFO : string;
-  attribute CORE_GENERATION_INFO of system_design : entity is "system_design,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system_design,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=32,numReposBlks=18,numNonXlnxBlks=4,numHierBlks=14,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=14,da_board_cnt=5,da_ps7_cnt=1,synth_mode=Global}";
   attribute HW_HANDOFF : string;
   attribute HW_HANDOFF of system_design : entity is "system_design.hwdef";
+  attribute core_generation_info : string;
+  attribute core_generation_info of system_design : entity is "system_design,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system_design,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=32,numReposBlks=18,numNonXlnxBlks=4,numHierBlks=14,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=14,da_board_cnt=5,da_ps7_cnt=1,synth_mode=Global}";
 end system_design;
 
 architecture STRUCTURE of system_design is
@@ -4130,10 +4128,11 @@ architecture STRUCTURE of system_design is
   component system_design_wrc_1p_kintex7_0_0 is
   port (
     clk_20m_vcxo_i : in STD_LOGIC;
-    clk_aux_p_i : in STD_LOGIC;
-    clk_aux_n_i : in STD_LOGIC;
     gtp_dedicated_clk_p_i : in STD_LOGIC;
     gtp_dedicated_clk_n_i : in STD_LOGIC;
+    clk_dmtd_b : inout STD_LOGIC;
+    clk_ref_b : inout STD_LOGIC;
+    clk_rx_rbclk_b : inout STD_LOGIC;
     gtp0_activity_led_o : out STD_LOGIC;
     gtp0_synced_led_o : out STD_LOGIC;
     gtp0_link_led_o : out STD_LOGIC;
@@ -4315,8 +4314,6 @@ architecture STRUCTURE of system_design is
   signal axi_wb_i2c_master_0_axi_int_o : STD_LOGIC;
   signal axi_wb_i2c_master_2_axi_int_o : STD_LOGIC;
   signal clk_25m_vcxo_i_1 : STD_LOGIC;
-  signal clk_aux_n_i_1 : STD_LOGIC;
-  signal clk_aux_p_i_1 : STD_LOGIC;
   signal dig_in1_i_1 : STD_LOGIC;
   signal dig_in2_i_1 : STD_LOGIC;
   signal dig_in3_n_i_1 : STD_LOGIC;
@@ -4593,6 +4590,9 @@ architecture STRUCTURE of system_design is
   signal NLW_rst_wrc_1p_kintex7_0_62M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
   signal NLW_rst_wrc_1p_kintex7_0_62M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
   signal NLW_wrc_1p_kintex7_0_axi_int_o_UNCONNECTED : STD_LOGIC;
+  signal NLW_wrc_1p_kintex7_0_clk_dmtd_b_UNCONNECTED : STD_LOGIC;
+  signal NLW_wrc_1p_kintex7_0_clk_ref_b_UNCONNECTED : STD_LOGIC;
+  signal NLW_wrc_1p_kintex7_0_clk_rx_rbclk_b_UNCONNECTED : STD_LOGIC;
   signal NLW_wrc_1p_kintex7_0_gtp0_activity_led_o_UNCONNECTED : STD_LOGIC;
   signal NLW_wrc_1p_kintex7_0_gtp0_link_led_o_UNCONNECTED : STD_LOGIC;
   signal NLW_wrc_1p_kintex7_0_gtp0_synced_led_o_UNCONNECTED : STD_LOGIC;
@@ -4636,8 +4636,6 @@ begin
   Vp_Vn_1_V_N <= Vp_Vn_v_n;
   Vp_Vn_1_V_P <= Vp_Vn_v_p;
   clk_25m_vcxo_i_1 <= clk_25m_vcxo_i;
-  clk_aux_n_i_1 <= clk_aux_n_i;
-  clk_aux_p_i_1 <= clk_aux_p_i;
   dac_cs1_n_o <= wrc_1p_kintex7_0_dac_cs1_n_o;
   dac_cs2_n_o <= wrc_1p_kintex7_0_dac_cs2_n_o;
   dac_din_o <= wrc_1p_kintex7_0_dac_din_o;
@@ -5342,8 +5340,9 @@ wrc_1p_kintex7_0: component system_design_wrc_1p_kintex7_0_0
       axi_int_o => NLW_wrc_1p_kintex7_0_axi_int_o_UNCONNECTED,
       button_rst_n_i => pb_gp_i_1,
       clk_20m_vcxo_i => clk_25m_vcxo_i_1,
-      clk_aux_n_i => clk_aux_n_i_1,
-      clk_aux_p_i => clk_aux_p_i_1,
+      clk_dmtd_b => NLW_wrc_1p_kintex7_0_clk_dmtd_b_UNCONNECTED,
+      clk_ref_b => NLW_wrc_1p_kintex7_0_clk_ref_b_UNCONNECTED,
+      clk_rx_rbclk_b => NLW_wrc_1p_kintex7_0_clk_rx_rbclk_b_UNCONNECTED,
       dac_cs1_n_o => wrc_1p_kintex7_0_dac_cs1_n_o,
       dac_cs2_n_o => wrc_1p_kintex7_0_dac_cs2_n_o,
       dac_din_o => wrc_1p_kintex7_0_dac_din_o,
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
index 24bd7a13951bfa3a0f5ed1e5dd19f0549c21b2a7..0518f1cbd6241d2e19ba4d8905aaafc030dba40f 100644
--- a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
@@ -46,8 +46,8 @@
 -- 
 -- DO NOT MODIFY THIS FILE.
 
--- IP VLNV: user.org:user:fasec_hwtest:3.0.1
--- IP Revision: 25
+-- IP VLNV: user.org:user:fasec_hwtest:3.1.0
+-- IP Revision: 26
 
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd
index dec12ff1a6467f38e297b1bab355c1e0441a8c84..a198a68b987ecc81e98b2f627d20a89078881243 100644
--- a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd
@@ -46,8 +46,8 @@
 -- 
 -- DO NOT MODIFY THIS FILE.
 
--- IP VLNV: CERN:wrc:wrc_1p_kintex7:2.3.1
--- IP Revision: 13
+-- IP VLNV: CERN:wrc:wrc_1p_kintex7:3.1.0
+-- IP Revision: 15
 
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
@@ -56,10 +56,11 @@ USE ieee.numeric_std.ALL;
 ENTITY system_design_wrc_1p_kintex7_0_0 IS
   PORT (
     clk_20m_vcxo_i : IN STD_LOGIC;
-    clk_aux_p_i : IN STD_LOGIC;
-    clk_aux_n_i : IN STD_LOGIC;
     gtp_dedicated_clk_p_i : IN STD_LOGIC;
     gtp_dedicated_clk_n_i : IN STD_LOGIC;
+    clk_dmtd_b : INOUT STD_LOGIC;
+    clk_ref_b : INOUT STD_LOGIC;
+    clk_rx_rbclk_b : INOUT STD_LOGIC;
     gtp0_activity_led_o : OUT STD_LOGIC;
     gtp0_synced_led_o : OUT STD_LOGIC;
     gtp0_link_led_o : OUT STD_LOGIC;
@@ -124,10 +125,11 @@ ARCHITECTURE system_design_wrc_1p_kintex7_0_0_arch OF system_design_wrc_1p_kinte
     );
     PORT (
       clk_20m_vcxo_i : IN STD_LOGIC;
-      clk_aux_p_i : IN STD_LOGIC;
-      clk_aux_n_i : IN STD_LOGIC;
       gtp_dedicated_clk_p_i : IN STD_LOGIC;
       gtp_dedicated_clk_n_i : IN STD_LOGIC;
+      clk_dmtd_b : INOUT STD_LOGIC;
+      clk_ref_b : INOUT STD_LOGIC;
+      clk_rx_rbclk_b : INOUT STD_LOGIC;
       gtp0_activity_led_o : OUT STD_LOGIC;
       gtp0_synced_led_o : OUT STD_LOGIC;
       gtp0_link_led_o : OUT STD_LOGIC;
@@ -223,10 +225,11 @@ BEGIN
     )
     PORT MAP (
       clk_20m_vcxo_i => clk_20m_vcxo_i,
-      clk_aux_p_i => clk_aux_p_i,
-      clk_aux_n_i => clk_aux_n_i,
       gtp_dedicated_clk_p_i => gtp_dedicated_clk_p_i,
       gtp_dedicated_clk_n_i => gtp_dedicated_clk_n_i,
+      clk_dmtd_b => clk_dmtd_b,
+      clk_ref_b => clk_ref_b,
+      clk_rx_rbclk_b => clk_rx_rbclk_b,
       gtp0_activity_led_o => gtp0_activity_led_o,
       gtp0_synced_led_o => gtp0_synced_led_o,
       gtp0_link_led_o => gtp0_link_led_o,
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
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diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
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rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/main_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/main_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
similarity index 93%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
index 3c85238fbd0451d3e9a279a4efb98c075a431b27..fb2e12e9d4d019fd727177684ccdb7ae1383d477 100755
--- a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
@@ -93,9 +93,18 @@ architecture behavioral of gtp_bitslide is
     end if;
   end f_eval_pause_tics;
 
+  function f_max_bts return integer is
+  begin
+    if(g_target = "spartan6") then
+      return 10;
+    else
+      return 20;
+    end if;
+  end f_max_bts;
 
   constant c_pause_tics            : integer := f_eval_pause_tics;
   constant c_sync_detect_threshold : integer := f_eval_sync_detect_threshold;
+  constant c_max_bts               : integer := f_max_bts;
 
 
   type t_bitslide_fsm_state is (S_SYNC_LOST, S_STABILIZE, S_SLIDE, S_PAUSE, S_GOT_SYNC, S_RESET_CDR);
@@ -162,7 +171,11 @@ begin  -- behavioral
           end if;
 
         when S_SLIDE =>
-          cur_slide      <= cur_slide + 1;
+          if (cur_slide < c_max_bts-1) then
+            cur_slide <= cur_slide + 1;
+          else
+            cur_slide <= (others=>'0');
+          end if;
           gtp_rx_slide_o <= '1';
           counter        <= (others => '0');
 
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd
similarity index 100%
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rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd
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diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd
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rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd
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rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd
similarity index 92%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd
index 8169e7685a953e902a49af2b14d8fcbca13f8e9d..6b77e45a17bb65635b2ae385d65720b3eea45c71 100755
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd
@@ -27,26 +27,23 @@ use work.gen7s_cores_pkg.all;
 entity wrc_1p_kintex7 is
   generic
     (
-      TAR_ADDR_WDTH : integer := 13     -- not used for this project
+      TAR_ADDR_WDTH : integer := 13          -- not used for this project
       );
   port
     (
-      --Clocks
-      clk_20m_vcxo_i : in std_logic;    -- 25MHz VCXO clock
-
-      clk_aux_p_i : in std_logic;       -- 125 PLL auxiliary clock.
-      clk_aux_n_i : in std_logic;
-
-      gtp_dedicated_clk_p_i : in std_logic;  -- Dedicated clock for Xilinx GTP transceiver
+      -------------------------------------------------------------------------
+      -- clocks
+      -------------------------------------------------------------------------      
+      clk_20m_vcxo_i        : in std_logic;  -- 25MHz VCXO clock
+      gtp_dedicated_clk_p_i : in std_logic;  -- GTP transceiver & internal 125
+                                             -- MHz PLL clock
       gtp_dedicated_clk_n_i : in std_logic;
 
-      --Dedicated CLK to configure the AD9516 PLL (100MHz by default)
-      -- clk_100mhz_i : in std_logic;
-      -- clk_100mhz_n_i : in std_logic;
-
-      --SERDES CLK. AD9516 OUT 5.
---      clk_serdes_p_i : in std_logic;
---      clk_serdes_n_i : in std_logic;
+      -- FASEC clock outputs for debugging
+      -- inouts to match existing fasec_hwtest module
+      clk_dmtd_b     : inout std_logic;
+      clk_ref_b      : inout std_logic;
+      clk_rx_rbclk_b : inout std_logic;
 
       -- Front panel LEDs
       -- GTP0
@@ -55,12 +52,6 @@ entity wrc_1p_kintex7 is
       gtp0_link_led_o     : out std_logic;
       gtp0_wrmode_led_o   : out std_logic;  -- Not used
 
-      -- GTP1
-      -- gtp1_activity_led_o : out std_logic;
-      -- gtp1_synced_led_o   : out std_logic;  -- Not used
-      -- gtp1_link_led_o     : out std_logic;
-      -- gtp1_wrmode_led_o   : out std_logic;  -- Not used
-
       -- DAC Signals
       dac_sclk_o  : out std_logic;
       dac_din_o   : out std_logic;
@@ -154,8 +145,8 @@ entity wrc_1p_kintex7 is
       -- Axi Slave Bus Interface S00_AXI
       ------------------------------------------
       -- aclk provided by this IP, wire to master!
-      axi_int_o       : out   std_logic;  -- axi interrupt signal
-      s00_axi_aclk_o  : out  std_logic;
+      axi_int_o       : out std_logic;  -- axi interrupt signal
+      s00_axi_aclk_o  : out std_logic;
       s00_axi_aresetn : in  std_logic;
       s00_axi_awaddr  : in  std_logic_vector(c_wishbone_address_width-1 downto 0);
       s00_axi_awprot  : in  std_logic_vector(2 downto 0);
@@ -229,10 +220,8 @@ architecture rtl of wrc_1p_kintex7 is
 
   -- Dedicated clock for GTP transceiver
   --GTP dedicated clock.
-  signal gtp_dedicated_clk : std_logic;
-
-  -- Reference clock disciplined by WR. 62.5 MHz
-  signal wr_ref_clk : std_logic;
+  signal clk_gtx      : std_logic;
+  signal clk_125m_ref : std_logic;
 
   signal pllout_clk_sys     : std_logic;
   signal pllout_clk_dmtd    : std_logic;
@@ -240,12 +229,11 @@ architecture rtl of wrc_1p_kintex7 is
   signal pllout_clk_fb_dmtd : std_logic;
 
   signal clk_20m_vcxo_buf : std_logic;
-  signal clk_aux          : std_logic;
   signal clk_sys          : std_logic;
   signal clk_dmtd         : std_logic;
+  signal clk_125m_pllref  : std_logic;
 
-  signal dac_rst_n : std_logic;
-
+  signal dac_rst_n  : std_logic;
   signal wrc_scl_o  : std_logic;
   signal wrc_scl_i  : std_logic;
   signal wrc_sda_o  : std_logic;
@@ -337,11 +325,14 @@ architecture rtl of wrc_1p_kintex7 is
   signal phy_rdy          : std_logic;
 
 begin
+  -- FASEC clock outputs for debugging
+  clk_dmtd_b     <= clk_dmtd;           --62,5 MHz, from 20 MHz
+  clk_ref_b      <= clk_125m_ref;       --125 MHz, GTP tx clock
+  clk_rx_rbclk_b <= phy_rx_rbclk;       -- GTP rx clock
 
   -- PLL stuff
   --PLL_BASE(S6) ---> MMCME2_ADV(A7)
   -- 125 MHz -> 62,5 MHz. Generate the sys clk
-
   cmp_sys_clk_pll : MMCME2_ADV
     generic map
     (BANDWIDTH            => "OPTIMIZED",
@@ -377,7 +368,7 @@ begin
      CLKOUT6      => open,
      -- Input clock control
      CLKFBIN      => pllout_clk_fb_aux,
-     CLKIN1       => clk_aux,
+     CLKIN1       => clk_125m_pllref,
      CLKIN2       => '0',
      -- Tied to always select the primary input clock
      CLKINSEL     => '1',
@@ -491,37 +482,18 @@ begin
       O => clk_20m_vcxo_buf,
       I => clk_20m_vcxo_i);
 
-  cmp_auxclk_buf : IBUFGDS
-    generic map (
-      DIFF_TERM    => false,            -- Differential Termination
-      IBUF_LOW_PWR => true,  -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-      IOSTANDARD   => "DEFAULT")
-    port map (
-      O  => clk_aux,                    -- Buffer output
-      I  => clk_aux_p_i,  -- Diff_p buffer input (connect directly to top-level port)
-      IB => clk_aux_n_i  -- Diff_n buffer input (connect directly to top-level port)
-      );
-
---------------------------------------------------------------------------------------------------------
-  -- The SERDES CLOCK is used as WR CLK (62.5MHz)
---   cmp_pllserdes_buf : IBUFGDS
---   generic map (
---     DIFF_TERM    => false,      -- Differential Termination
---     IBUF_LOW_PWR => true,      -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
---     IOSTANDARD   => "DEFAULT")
---   port map (
---     O  => open,     -- Buffer output
---     I  => clk_serdes_p_i,  -- Diff_p buffer input (connect directly to top-level port)
---     IB => clk_serdes_n_i   -- Diff_n buffer input (connect directly to top-level port)
---     );
+  cmp_clk_125m_pllref_buf : BUFG
+    port map(
+      O => clk_125m_pllref,
+      I => clk_gtx);
 
   -----------------------------------------------------------------------------
   -- The infamous registering process to ensure the PPS & 10 MHz stability strikes again.
   -----------------------------------------------------------------------------
 
-  p_latch_pps : process(wr_ref_clk)
+  p_latch_pps : process(clk_125m_ref)
   begin
-    if rising_edge(wr_ref_clk) then
+    if rising_edge(clk_125m_ref) then
       pps_o <= pps;
     end if;
   end process;
@@ -530,8 +502,12 @@ begin
   -- Dedicated clocks for GTP.
   ------------------------------------------------------------------------------
   cmp_gtp_dedicated_clk : IBUFDS_GTE2
+    generic map(
+      CLKCM_CFG    => true,
+      CLKRCV_TRST  => true,
+      CLKSWING_CFG => "11")
     port map (
-      O     => gtp_dedicated_clk,
+      O     => clk_gtx,
       ODIV2 => open,
       CEB   => '0',
       I     => gtp_dedicated_clk_p_i,
@@ -626,7 +602,7 @@ begin
     port map (
       clk_sys_i            => clk_sys,
       clk_dmtd_i           => clk_dmtd,
-      clk_ref_i            => wr_ref_clk,
+      clk_ref_i            => clk_125m_ref,
       clk_aux_i            => (others => '0'),
       clk_ext_i            => s_ext_clk,
       rst_n_i              => local_reset_n,
@@ -642,7 +618,7 @@ begin
       dac_dpll_load_p1_o => dac_dpll_load_p1,
       dac_dpll_data_o    => dac_dpll_data,
 
-      phy_ref_clk_i        => wr_ref_clk,
+      phy_ref_clk_i        => clk_125m_ref,
       phy_tx_data_o        => phy_tx_data,
       phy_tx_k_o           => phy_tx_k,
       phy_tx_disparity_i   => phy_tx_disparity,
@@ -874,7 +850,7 @@ begin
     generic map(
       g_simulation => 0)
     port map(
-      clk_gtx_i      => gtp_dedicated_clk,
+      clk_gtx_i      => clk_gtx,
       tx_data_i      => phy_tx_data,
       tx_k_i         => phy_tx_k,
       tx_disparity_o => phy_tx_disparity,
@@ -892,7 +868,7 @@ begin
       pad_rxn_i => gtp0_rxn_i,
       pad_rxp_i => gtp0_rxp_i,
 
-      tx_out_clk_o  => wr_ref_clk,
+      tx_out_clk_o  => clk_125m_ref,
       tx_locked_o   => open,
       tx_prbs_sel_i => phy_prbs_sel,
       rdy_o         => phy_rdy);
@@ -1003,10 +979,10 @@ begin
   s00_axi_aclk_o <= clk_sys;
   u_axis_wbm_bridge : axis_wbm_bridge
     generic map (
-      g_AXI_AWIDTH => c_wishbone_address_width,
-      g_WB_AWIDTH  => c_wishbone_address_width,
-      g_AXI_DWIDTH => c_wishbone_data_width,
-      g_WB_DWIDTH  => c_wishbone_data_width,
+      g_AXI_AWIDTH  => c_wishbone_address_width,
+      g_WB_AWIDTH   => c_wishbone_address_width,
+      g_AXI_DWIDTH  => c_wishbone_data_width,
+      g_WB_DWIDTH   => c_wishbone_data_width,
       g_WB_BYTEADDR => false)
     port map (
       wb_clk_o      => open,
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
similarity index 97%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
index 5238245800aa8873782d748a4b580390154b5c12..b3561fa4e4d364edef73d60b8e3001b41ee88e6b 100755
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
@@ -6,7 +6,7 @@
 -- Author     : Pieter Van Trappen  <pvantrap@cern.ch>
 -- Company    : CERN
 -- Created    : 2016-11-22
--- Last update: 2017-03-21
+-- Last update: 2017-03-27
 -- Platform   : 
 -- Standard   : VHDL'93/02
 -------------------------------------------------------------------------------
@@ -81,6 +81,7 @@ architecture rtl of general_fmc is
   -- EDA-03287 constants
   constant c_COMP            : positive := 20;  -- 20 comparators on EDA-03287
   constant c_DOUTS           : positive := 8;  -- 8 outputs
+  constant c_DOUTSGP : positive := 4; -- first 4 outputs will be linked to GP signals (for white rabbit debugging)
   constant c_OUTFBD          : positive := 4;  -- of which 4 with feedback
   constant c_NODAC           : positive := 5;
   constant c_NOCHANNELS      : positive := 4;
@@ -243,6 +244,11 @@ begin
         );
   end generate gen_spi;
 
+  -- for white rabbit debugging, link some FMC outputs directly to GP inputs
+  gen_clkouts : if g_FMC = "EDA-03287" generate
+    s_diffouts_o(c_DOUTSGP-1 downto 0) <= FMC_GP3_b & FMC_GP2_b & FMC_GP1_b & FMC_GP0_b;
+  end generate gen_clkouts;
+  
   p_fmc_03287_io : process(clk_i)
     variable v_cmp  : std_logic_vector(c_COMP-1 downto 0);
     variable v_dout : std_logic_vector(c_DOUTS-1 downto 0);
@@ -251,7 +257,7 @@ begin
     if g_FMC = "EDA-03287" and rising_edge(clk_i) then
       -- in/outputs
       data_o(1)                        <= resize(unsigned(v_fbd(c_OUTFBD-1 downto 0)), data_o(1)'length);
-      s_diffouts_o(c_DOUTS-1 downto 0) <= v_dout(c_DOUTS-1 downto 0);
+      s_diffouts_o(c_DOUTS-1 downto c_DOUTSGP) <= v_dout(c_DOUTS-1 downto c_DOUTSGP);
       -- using the variables to clock-in/out data
       v_dout(c_DOUTS-1 downto 0)       := std_logic_vector(data_rw_i(2)(c_DOUTS-1 downto 0));
       v_fbd                            := FMC_LA_P_b(31) & FMC_LA_N_b(31) & FMC_LA_P_b(32) & FMC_LA_N_b(32);
@@ -263,7 +269,7 @@ begin
   --=============================================================================
   -- EDA-02327: FMC user lines - clock in for AXI register read by Zynq PS
   --=============================================================================  
-  p_i2c_fmc_02327 : process(FMC_GP0_b, FMC_GP1_b, FMC_LA_P_b(2), FMC_LA_N_b(2))
+  p_i2c_fmc_02327 : process(FMC_LA_P_b(2), FMC_LA_N_b(2))
   begin
     if g_FMC = "EDA-02327" then
       FMC_LA_P_b(2) <= 'Z';             -- scl_vadj, disconnect in xdc
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt
index 81da9d7b7246e326db4f3d40ab6fca37dd46de99..b6111e2287fef43e1c453321676307cba73b3cee 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Mar 23 21:34:31 CET 2017
+# Generated by export_simulation on Mon Mar 27 12:41:43 CEST 2017
 #
 ################################################################################
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do
index d81995189d07d547e6f17917174a21d5f7da2e49..0dde0363a4ca37acb7c37e72e1101e84310ec9ef 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do
@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1
 "../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
 
 vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd" \
 
 vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
 "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
 
 vcom -work lib_cdc_v1_0_2 -93 \
@@ -348,206 +348,206 @@ vlog -work fifo_generator_v13_1_1 -v2k5 "+incdir+../../../ipstatic/axi_infrastru
 "../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/sim/mux_buffering_fifo.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd" \
 
 vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd" \
 
 vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd" \
 "../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd" \
 
 vcom -work axi_lite_ipif_v3_0_4 -93 \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt
index dcd8fa3991c71ca9531966a241dff23909d6d13d..555238e6b6f7bd024ee5dbcce3dc02a0521f85a5 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
 processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -232,152 +232,152 @@ system_design_axi_dma_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/s
 xlconcat.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/xilinx.com/xlconcat_v2_1/xlconcat.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_xlconcat_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_xlconcat_0_0/sim/system_design_xlconcat_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 mux_buffering_fifo.v,verilog,fifo_generator_v13_1_1,../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/sim/mux_buffering_fifo.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-genram_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-memory_loader_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wishbone_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_fabric_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram_dualclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-endpoint_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gencores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-endpoint_private_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-inferred_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-inferred_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_crc32_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_sync_detect.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_sync_detect_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_crc_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_extend_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_sync_ffs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_pulse_synchronizer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_shiftreg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_uart_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dmtd_with_deglitcher.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-minic_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_autonegotiation.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_pcs_tbi_mdio_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_wb_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_oob_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_early_address_match.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_clock_alignment_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_packet_filter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_ts_counter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_status_reg_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rtu_header_extract.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_buffer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_crc_size_check.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_header_processor.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_crc_inserter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_inject_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_packet_injection.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_shiftreg_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_simple_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-sockit_owm.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_async_rx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_async_tx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_baud_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_uart_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_addsub.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_slave_adapter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_eic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_fifo_sync.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-jtag_tap.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_syscon_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_pulse_synchronizer2.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dmtd_phase_meas.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-softpll_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_1000basex_pcs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_timestamping_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_leds_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_wishbone_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pps_gen_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-jtag_cores.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_adder.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_dp_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_logic_op.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_shifter.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-minic_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_multiplier.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_aligner.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_frequency_meter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gen7s_cores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-sdb_rom.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_allprofiles.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrcore_2p_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwrf_mux.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_clgen.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_shift.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_sdb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_lm32.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_periph.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrcore_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-disparity_gen_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spec_serial_dac.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_top.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-PLL_SPI_ctrl_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp_bitslide.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-whiterabbit_gtxe2_channel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spec_serial_dac_arb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_a7_gtps_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ext_pll_10_to_62_compensated.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_gtx_phy_kintex7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBuffer.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferVector.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-shiftRegister.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_defines.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-si570_if_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-eca_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_wbm_bridge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_irq_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_cores_pkg_gsi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_pwm_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xloader_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_sync_block.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_gtrxreset_seq.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp2p_wizard_sync_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_channel_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp2p_wizard_tx_manual_phase_align.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_gtp_phy_artix7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_include.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-timescale.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_1p_kintex7_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+genram_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+memory_loader_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wishbone_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_fabric_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram_dualclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+endpoint_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gencores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+endpoint_private_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+inferred_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+inferred_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_crc32_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_sync_detect.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_sync_detect_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_crc_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_extend_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_sync_ffs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_pulse_synchronizer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_shiftreg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_uart_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dmtd_with_deglitcher.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+minic_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_autonegotiation.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_pcs_tbi_mdio_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_wb_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_oob_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_early_address_match.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_clock_alignment_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_packet_filter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_ts_counter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_status_reg_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rtu_header_extract.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_buffer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_crc_size_check.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_header_processor.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_crc_inserter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_inject_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_packet_injection.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_shiftreg_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_simple_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+sockit_owm.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_async_rx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_async_tx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_baud_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_uart_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_addsub.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_slave_adapter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_eic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_fifo_sync.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+jtag_tap.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_syscon_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_pulse_synchronizer2.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dmtd_phase_meas.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+softpll_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_1000basex_pcs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_timestamping_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_leds_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_wishbone_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pps_gen_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+jtag_cores.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_adder.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_dp_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_logic_op.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_shifter.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+minic_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_multiplier.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_aligner.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_frequency_meter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gen7s_cores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+sdb_rom.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_allprofiles.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrcore_2p_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwrf_mux.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_clgen.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_shift.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_sdb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_lm32.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_periph.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrcore_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+disparity_gen_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spec_serial_dac.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_top.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+PLL_SPI_ctrl_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+whiterabbit_gtxe2_channel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spec_serial_dac_arb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_a7_gtps_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ext_pll_10_to_62_compensated.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_gtx_phy_kintex7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBuffer.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferVector.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+shiftRegister.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_defines.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+si570_if_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+eca_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_wbm_bridge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_irq_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_cores_pkg_gsi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_pwm_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xloader_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_sync_block.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_gtrxreset_seq.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp2p_wizard_sync_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_channel_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp2p_wizard_tx_manual_phase_align.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_gtp_phy_artix7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_include.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+timescale.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp_bitslide.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_1p_kintex7_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_wrc_1p_kintex7_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 ipif_pkg.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/ipif_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 pselect_f.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/pselect_f.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh
index adcf550c21e4f7aca269a99df9ab15d6d96ee976..c6435ab94e3d18a9689851253c7cbdeb672044ca 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh
@@ -8,7 +8,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 23 21:34:31 CET 2017
+# Generated by Vivado on Mon Mar 27 12:41:43 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016 
 #
 # usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt
index 81da9d7b7246e326db4f3d40ab6fca37dd46de99..b6111e2287fef43e1c453321676307cba73b3cee 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Mar 23 21:34:31 CET 2017
+# Generated by export_simulation on Mon Mar 27 12:41:43 CEST 2017
 #
 ################################################################################
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt
index 23502fe7e040613b444afdcf973e47f1476239c5..0f25994269e41affba8c14d42771980744ab176b 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
 processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -232,152 +232,152 @@ system_design_axi_dma_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/s
 xlconcat.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/xilinx.com/xlconcat_v2_1/xlconcat.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_xlconcat_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_xlconcat_0_0/sim/system_design_xlconcat_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 mux_buffering_fifo.v,verilog,fifo_generator_v13_1_1,../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/sim/mux_buffering_fifo.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-genram_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-memory_loader_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wishbone_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_fabric_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram_dualclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-endpoint_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gencores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-endpoint_private_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-inferred_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-inferred_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_crc32_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_sync_detect.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_sync_detect_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_crc_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_extend_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_sync_ffs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_pulse_synchronizer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_shiftreg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_uart_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dmtd_with_deglitcher.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-minic_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_autonegotiation.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_pcs_tbi_mdio_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_wb_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_oob_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_early_address_match.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_clock_alignment_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_packet_filter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_ts_counter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_status_reg_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rtu_header_extract.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_buffer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_crc_size_check.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_header_processor.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_crc_inserter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_inject_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_packet_injection.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_shiftreg_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_simple_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-sockit_owm.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_async_rx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_async_tx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_baud_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_uart_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_addsub.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_slave_adapter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_eic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_fifo_sync.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-jtag_tap.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_syscon_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_pulse_synchronizer2.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dmtd_phase_meas.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-softpll_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_1000basex_pcs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_timestamping_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_leds_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_wishbone_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pps_gen_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-jtag_cores.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_adder.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_dp_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_logic_op.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_shifter.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-minic_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_multiplier.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_aligner.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_frequency_meter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gen7s_cores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-sdb_rom.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_allprofiles.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrcore_2p_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwrf_mux.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_clgen.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_shift.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_sdb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_lm32.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_periph.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrcore_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-disparity_gen_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spec_serial_dac.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_top.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-PLL_SPI_ctrl_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp_bitslide.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-whiterabbit_gtxe2_channel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spec_serial_dac_arb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_a7_gtps_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ext_pll_10_to_62_compensated.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_gtx_phy_kintex7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBuffer.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferVector.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-shiftRegister.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_defines.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-si570_if_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-eca_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_wbm_bridge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_irq_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_cores_pkg_gsi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_pwm_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xloader_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_sync_block.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_gtrxreset_seq.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp2p_wizard_sync_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_channel_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp2p_wizard_tx_manual_phase_align.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_gtp_phy_artix7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_include.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-timescale.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_1p_kintex7_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+genram_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+memory_loader_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wishbone_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_fabric_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram_dualclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+endpoint_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gencores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+endpoint_private_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+inferred_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+inferred_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_crc32_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_sync_detect.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_sync_detect_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_crc_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_extend_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_sync_ffs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_pulse_synchronizer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_shiftreg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_uart_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dmtd_with_deglitcher.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+minic_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_autonegotiation.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_pcs_tbi_mdio_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_wb_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_oob_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_early_address_match.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_clock_alignment_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_packet_filter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_ts_counter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_status_reg_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rtu_header_extract.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_buffer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_crc_size_check.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_header_processor.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_crc_inserter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_inject_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_packet_injection.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_shiftreg_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_simple_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+sockit_owm.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_async_rx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_async_tx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_baud_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_uart_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_addsub.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_slave_adapter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_eic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_fifo_sync.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+jtag_tap.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_syscon_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_pulse_synchronizer2.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dmtd_phase_meas.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+softpll_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_1000basex_pcs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_timestamping_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_leds_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_wishbone_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pps_gen_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+jtag_cores.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_adder.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_dp_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_logic_op.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_shifter.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+minic_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_multiplier.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_aligner.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_frequency_meter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gen7s_cores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+sdb_rom.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_allprofiles.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrcore_2p_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwrf_mux.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_clgen.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_shift.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_sdb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_lm32.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_periph.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrcore_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+disparity_gen_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spec_serial_dac.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_top.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+PLL_SPI_ctrl_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+whiterabbit_gtxe2_channel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spec_serial_dac_arb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_a7_gtps_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ext_pll_10_to_62_compensated.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_gtx_phy_kintex7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBuffer.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferVector.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+shiftRegister.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_defines.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+si570_if_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+eca_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_wbm_bridge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_irq_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_cores_pkg_gsi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_pwm_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xloader_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_sync_block.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_gtrxreset_seq.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp2p_wizard_sync_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_channel_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp2p_wizard_tx_manual_phase_align.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_gtp_phy_artix7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_include.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+timescale.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp_bitslide.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_1p_kintex7_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_wrc_1p_kintex7_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 ipif_pkg.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/ipif_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 pselect_f.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/pselect_f.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f
index bc013f76cde22437d5472863925253dcec5e3ec9..025f70b8e346230909b41b8031860f7150cc1f5d 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f
@@ -40,22 +40,22 @@
   "../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
 -endlib
 -makelib ies/hdl_lib \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
 -endlib
 -makelib ies/xil_defaultlib \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd" \
 -endlib
 -makelib ies/hdl_lib \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
 -endlib
 -makelib ies/xil_defaultlib \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
   "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
 -endlib
 -makelib ies/lib_cdc_v1_0_2 \
@@ -297,206 +297,206 @@
   "../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/sim/mux_buffering_fifo.v" \
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 -makelib ies/xil_defaultlib \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" \
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+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" \
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+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd" \
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+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd" \
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+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" \
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-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" \
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+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" \
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+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v" \
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-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd" \
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-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd" \
 -endlib
 -makelib ies/xil_defaultlib \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" \
 -endlib
 -makelib ies/xil_defaultlib \
-  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" \
+  "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd" \
   "../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd" \
 -endlib
 -makelib ies/axi_lite_ipif_v3_0_4 \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh
index eb858387e18620a40c3fc01b0be874bba72de09a..9259d9a3f41c7214f0031c1fe7989acbe8e1cb88 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh
@@ -8,7 +8,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 23 21:34:31 CET 2017
+# Generated by Vivado on Mon Mar 27 12:41:43 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016 
 #
 # usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt
index 81da9d7b7246e326db4f3d40ab6fca37dd46de99..b6111e2287fef43e1c453321676307cba73b3cee 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Mar 23 21:34:31 CET 2017
+# Generated by export_simulation on Mon Mar 27 12:41:43 CEST 2017
 #
 ################################################################################
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do
index 649cba45bf10ef25215a92f950ef0036dbc6804b..a5fee5bf2a59fe031195e258a235cf3e3e616180 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do
@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructur
 "../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
 
 vcom -work hdl_lib -64 -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd" \
 
 vcom -work hdl_lib -64 -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
 "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
 
 vcom -work lib_cdc_v1_0_2 -64 -93 \
@@ -348,206 +348,206 @@ vlog -work fifo_generator_v13_1_1 -64 -incr "+incdir+../../../ipstatic/axi_infra
 "../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/sim/mux_buffering_fifo.v" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" \
 
 vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" \
 
 vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" \
 
 vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" \
 
 vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" \
 
 vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" \
 
 vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd" \
 
 vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd" \
 
 vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" \
 
 vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd" \
 
 vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd" \
 
 vcom -work hdl_lib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd" \
 
 vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd" \
 
 vcom -work hdl_lib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd" \
 
 vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd" \
 "../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd" \
 
 vcom -work axi_lite_ipif_v3_0_4 -64 -93 \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt
index dcd8fa3991c71ca9531966a241dff23909d6d13d..555238e6b6f7bd024ee5dbcce3dc02a0521f85a5 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
 processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -232,152 +232,152 @@ system_design_axi_dma_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/s
 xlconcat.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/xilinx.com/xlconcat_v2_1/xlconcat.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_xlconcat_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_xlconcat_0_0/sim/system_design_xlconcat_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 mux_buffering_fifo.v,verilog,fifo_generator_v13_1_1,../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/sim/mux_buffering_fifo.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-genram_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-memory_loader_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wishbone_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_fabric_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram_dualclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-endpoint_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gencores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-endpoint_private_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-inferred_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-inferred_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_crc32_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_sync_detect.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_sync_detect_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_crc_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_extend_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_sync_ffs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_pulse_synchronizer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_shiftreg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_uart_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dmtd_with_deglitcher.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-minic_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_autonegotiation.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_pcs_tbi_mdio_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_wb_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_oob_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_early_address_match.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_clock_alignment_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_packet_filter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_ts_counter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_status_reg_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rtu_header_extract.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_buffer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_crc_size_check.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_header_processor.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_crc_inserter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_inject_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_packet_injection.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_shiftreg_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_simple_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-sockit_owm.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_async_rx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_async_tx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_baud_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_uart_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_addsub.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_slave_adapter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_eic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_fifo_sync.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-jtag_tap.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_syscon_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_pulse_synchronizer2.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dmtd_phase_meas.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-softpll_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_1000basex_pcs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_timestamping_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_leds_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_wishbone_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pps_gen_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-jtag_cores.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_adder.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_dp_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_logic_op.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_shifter.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-minic_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_multiplier.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_aligner.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_frequency_meter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gen7s_cores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-sdb_rom.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_allprofiles.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrcore_2p_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwrf_mux.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_clgen.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_shift.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_sdb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_lm32.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_periph.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrcore_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-disparity_gen_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spec_serial_dac.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_top.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-PLL_SPI_ctrl_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp_bitslide.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-whiterabbit_gtxe2_channel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spec_serial_dac_arb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_a7_gtps_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ext_pll_10_to_62_compensated.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_gtx_phy_kintex7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBuffer.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferVector.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-shiftRegister.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_defines.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-si570_if_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-eca_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_wbm_bridge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_irq_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_cores_pkg_gsi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_pwm_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xloader_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_sync_block.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_gtrxreset_seq.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp2p_wizard_sync_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_channel_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp2p_wizard_tx_manual_phase_align.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_gtp_phy_artix7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_include.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-timescale.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_1p_kintex7_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+genram_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+memory_loader_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wishbone_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_fabric_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram_dualclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+endpoint_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gencores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+endpoint_private_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+inferred_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+inferred_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_crc32_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_sync_detect.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_sync_detect_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_crc_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_extend_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_sync_ffs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_pulse_synchronizer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_shiftreg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_uart_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dmtd_with_deglitcher.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+minic_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_autonegotiation.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_pcs_tbi_mdio_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_wb_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_oob_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_early_address_match.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_clock_alignment_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_packet_filter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_ts_counter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_status_reg_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rtu_header_extract.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_buffer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_crc_size_check.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_header_processor.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_crc_inserter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_inject_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_packet_injection.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_shiftreg_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_simple_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+sockit_owm.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_async_rx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_async_tx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_baud_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_uart_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_addsub.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_slave_adapter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_eic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_fifo_sync.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+jtag_tap.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_syscon_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_pulse_synchronizer2.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dmtd_phase_meas.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+softpll_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_1000basex_pcs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_timestamping_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_leds_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_wishbone_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pps_gen_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+jtag_cores.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_adder.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_dp_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_logic_op.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_shifter.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+minic_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_multiplier.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_aligner.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_frequency_meter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gen7s_cores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+sdb_rom.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_allprofiles.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrcore_2p_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwrf_mux.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_clgen.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_shift.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_sdb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_lm32.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_periph.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrcore_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+disparity_gen_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spec_serial_dac.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_top.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+PLL_SPI_ctrl_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+whiterabbit_gtxe2_channel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spec_serial_dac_arb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_a7_gtps_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ext_pll_10_to_62_compensated.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_gtx_phy_kintex7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBuffer.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferVector.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+shiftRegister.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_defines.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+si570_if_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+eca_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_wbm_bridge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_irq_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_cores_pkg_gsi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_pwm_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xloader_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_sync_block.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_gtrxreset_seq.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp2p_wizard_sync_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_channel_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp2p_wizard_tx_manual_phase_align.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_gtp_phy_artix7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_include.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+timescale.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp_bitslide.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_1p_kintex7_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_wrc_1p_kintex7_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 ipif_pkg.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/ipif_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 pselect_f.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/pselect_f.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh
index 707529b5b4ab75ef38956ae8d50357f7633b78b6..86deb9c77998686d6c69a02f66a7131d9624d4d9 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh
@@ -8,7 +8,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 23 21:34:31 CET 2017
+# Generated by Vivado on Mon Mar 27 12:41:43 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016 
 #
 # usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt
index 81da9d7b7246e326db4f3d40ab6fca37dd46de99..b6111e2287fef43e1c453321676307cba73b3cee 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Mar 23 21:34:31 CET 2017
+# Generated by export_simulation on Mon Mar 27 12:41:43 CEST 2017
 #
 ################################################################################
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do
index ead46fafcade65b3b3a65a1372f554c91ae72036..34095196ad9e5f10db81870c16259aefd8411860 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do
@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1
 "../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
 
 vcom -work hdl_lib -64 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd" \
 
 vcom -work hdl_lib -64 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
 "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
 
 vcom -work lib_cdc_v1_0_2 -64 \
@@ -348,206 +348,206 @@ vlog -work fifo_generator_v13_1_1 -64 "+incdir+../../../ipstatic/axi_infrastruct
 "../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/sim/mux_buffering_fifo.v" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" \
 
 vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" \
 
 vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" \
 
 vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" \
 
 vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" \
 
 vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" \
 
 vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd" \
 
 vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd" \
 
 vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" \
 
 vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd" \
 
 vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd" \
 
 vcom -work hdl_lib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd" \
 
 vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd" \
 
 vcom -work hdl_lib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd" \
 
 vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd" \
 "../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd" \
 
 vcom -work axi_lite_ipif_v3_0_4 -64 \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt
index dcd8fa3991c71ca9531966a241dff23909d6d13d..555238e6b6f7bd024ee5dbcce3dc02a0521f85a5 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
 processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -232,152 +232,152 @@ system_design_axi_dma_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/s
 xlconcat.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/xilinx.com/xlconcat_v2_1/xlconcat.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_xlconcat_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_xlconcat_0_0/sim/system_design_xlconcat_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 mux_buffering_fifo.v,verilog,fifo_generator_v13_1_1,../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/sim/mux_buffering_fifo.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-genram_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-memory_loader_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wishbone_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_fabric_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram_dualclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-endpoint_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gencores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-endpoint_private_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-inferred_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-inferred_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_crc32_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_sync_detect.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_sync_detect_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_crc_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_extend_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_sync_ffs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_pulse_synchronizer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_shiftreg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_uart_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dmtd_with_deglitcher.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-minic_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_autonegotiation.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_pcs_tbi_mdio_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_wb_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_oob_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_early_address_match.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_clock_alignment_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_packet_filter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_ts_counter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_status_reg_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rtu_header_extract.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_buffer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_crc_size_check.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_header_processor.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_crc_inserter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_inject_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_packet_injection.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_shiftreg_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_simple_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-sockit_owm.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_async_rx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_async_tx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_baud_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_uart_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_addsub.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_slave_adapter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_eic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_fifo_sync.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-jtag_tap.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_syscon_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_pulse_synchronizer2.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dmtd_phase_meas.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-softpll_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_1000basex_pcs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_timestamping_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_leds_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_wishbone_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pps_gen_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-jtag_cores.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_adder.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_dp_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_logic_op.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_shifter.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-minic_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_multiplier.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_aligner.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_frequency_meter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gen7s_cores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-sdb_rom.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_allprofiles.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrcore_2p_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwrf_mux.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_clgen.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_shift.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_sdb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_lm32.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_periph.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrcore_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-disparity_gen_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spec_serial_dac.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_top.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-PLL_SPI_ctrl_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp_bitslide.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-whiterabbit_gtxe2_channel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spec_serial_dac_arb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_a7_gtps_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ext_pll_10_to_62_compensated.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_gtx_phy_kintex7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBuffer.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferVector.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-shiftRegister.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_defines.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-si570_if_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-eca_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_wbm_bridge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_irq_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_cores_pkg_gsi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_pwm_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xloader_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_sync_block.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_gtrxreset_seq.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp2p_wizard_sync_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_channel_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp2p_wizard_tx_manual_phase_align.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_gtp_phy_artix7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_include.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-timescale.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_1p_kintex7_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+genram_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+memory_loader_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wishbone_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_fabric_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram_dualclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+endpoint_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gencores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+endpoint_private_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+inferred_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+inferred_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_crc32_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_sync_detect.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_sync_detect_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_crc_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_extend_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_sync_ffs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_pulse_synchronizer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_shiftreg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_uart_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dmtd_with_deglitcher.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+minic_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_autonegotiation.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_pcs_tbi_mdio_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_wb_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_oob_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_early_address_match.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_clock_alignment_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_packet_filter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_ts_counter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_status_reg_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rtu_header_extract.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_buffer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_crc_size_check.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_header_processor.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_crc_inserter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_inject_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_packet_injection.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_shiftreg_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_simple_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+sockit_owm.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_async_rx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_async_tx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_baud_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_uart_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_addsub.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_slave_adapter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_eic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_fifo_sync.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+jtag_tap.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_syscon_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_pulse_synchronizer2.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dmtd_phase_meas.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+softpll_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_1000basex_pcs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_timestamping_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_leds_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_wishbone_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pps_gen_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+jtag_cores.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_adder.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_dp_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_logic_op.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_shifter.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+minic_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_multiplier.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_aligner.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_frequency_meter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gen7s_cores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+sdb_rom.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_allprofiles.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrcore_2p_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwrf_mux.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_clgen.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_shift.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_sdb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_lm32.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_periph.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrcore_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+disparity_gen_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spec_serial_dac.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_top.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+PLL_SPI_ctrl_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+whiterabbit_gtxe2_channel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spec_serial_dac_arb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_a7_gtps_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ext_pll_10_to_62_compensated.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_gtx_phy_kintex7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBuffer.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferVector.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+shiftRegister.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_defines.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+si570_if_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+eca_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_wbm_bridge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_irq_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_cores_pkg_gsi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_pwm_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xloader_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_sync_block.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_gtrxreset_seq.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp2p_wizard_sync_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_channel_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp2p_wizard_tx_manual_phase_align.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_gtp_phy_artix7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_include.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+timescale.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp_bitslide.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_1p_kintex7_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_wrc_1p_kintex7_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 ipif_pkg.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/ipif_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 pselect_f.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/pselect_f.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh
index 7b2b565ad9673ef7de5deba7a566f86d3f5a1fb6..ed1b2ea922b461e88d986dfeeb5f7f4f75f323e4 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh
@@ -8,7 +8,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 23 21:34:31 CET 2017
+# Generated by Vivado on Mon Mar 27 12:41:43 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016 
 #
 # usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt
index 81da9d7b7246e326db4f3d40ab6fca37dd46de99..b6111e2287fef43e1c453321676307cba73b3cee 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Mar 23 21:34:31 CET 2017
+# Generated by export_simulation on Mon Mar 27 12:41:43 CEST 2017
 #
 ################################################################################
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do
index d56da0363b3ddd3a231a8b23942d7a8e9c63c2df..5f3e53aeeedcbdcf42ea0a079e8feafcf2d5115b 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do
@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1
 "../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
 
 vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd" \
 
 vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
 "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
 
 vcom -work lib_cdc_v1_0_2 -93 \
@@ -348,206 +348,206 @@ vlog -work fifo_generator_v13_1_1 -v2k5 "+incdir+../../../ipstatic/axi_infrastru
 "../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/sim/mux_buffering_fifo.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd" \
 
 vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd" \
 
 vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd" \
 
 vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" \
+"../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd" \
 "../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd" \
 
 vcom -work axi_lite_ipif_v3_0_4 -93 \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt
index dcd8fa3991c71ca9531966a241dff23909d6d13d..555238e6b6f7bd024ee5dbcce3dc02a0521f85a5 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
 processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -232,152 +232,152 @@ system_design_axi_dma_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/s
 xlconcat.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/xilinx.com/xlconcat_v2_1/xlconcat.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_xlconcat_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_xlconcat_0_0/sim/system_design_xlconcat_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 mux_buffering_fifo.v,verilog,fifo_generator_v13_1_1,../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/sim/mux_buffering_fifo.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-genram_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-memory_loader_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wishbone_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_fabric_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram_dualclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-endpoint_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gencores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-endpoint_private_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-inferred_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-inferred_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_crc32_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_sync_detect.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_sync_detect_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_crc_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_extend_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_sync_ffs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_pulse_synchronizer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_shiftreg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_uart_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dmtd_with_deglitcher.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-minic_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_autonegotiation.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_pcs_tbi_mdio_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_wb_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_oob_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_early_address_match.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_clock_alignment_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_packet_filter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_ts_counter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_status_reg_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rtu_header_extract.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_buffer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_crc_size_check.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_header_processor.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_crc_inserter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_inject_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_packet_injection.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_shiftreg_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_simple_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-sockit_owm.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_async_rx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_async_tx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_baud_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_uart_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_addsub.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_slave_adapter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_eic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_fifo_sync.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-jtag_tap.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_syscon_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_pulse_synchronizer2.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dmtd_phase_meas.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-softpll_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_1000basex_pcs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_timestamping_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_leds_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_wishbone_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pps_gen_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-jtag_cores.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_adder.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_dp_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_logic_op.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_shifter.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-minic_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_multiplier.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_aligner.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_frequency_meter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gen7s_cores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-sdb_rom.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_allprofiles.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrcore_2p_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwrf_mux.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_clgen.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_shift.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_sdb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_lm32.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_periph.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrcore_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-disparity_gen_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spec_serial_dac.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_top.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-PLL_SPI_ctrl_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp_bitslide.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-whiterabbit_gtxe2_channel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spec_serial_dac_arb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_a7_gtps_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ext_pll_10_to_62_compensated.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_gtx_phy_kintex7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBuffer.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferVector.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-shiftRegister.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_defines.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-si570_if_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-eca_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_wbm_bridge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_irq_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_cores_pkg_gsi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_pwm_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xloader_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_sync_block.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_gtrxreset_seq.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp2p_wizard_sync_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_channel_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp2p_wizard_tx_manual_phase_align.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_gtp_phy_artix7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_include.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-timescale.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_1p_kintex7_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+genram_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+memory_loader_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wishbone_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_fabric_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram_dualclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+endpoint_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gencores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+endpoint_private_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+inferred_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+inferred_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_crc32_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_sync_detect.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_sync_detect_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_crc_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_extend_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_sync_ffs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_pulse_synchronizer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_shiftreg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_uart_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dmtd_with_deglitcher.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+minic_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_autonegotiation.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_pcs_tbi_mdio_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_wb_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_oob_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_early_address_match.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_clock_alignment_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_packet_filter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_ts_counter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_status_reg_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rtu_header_extract.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_buffer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_crc_size_check.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_header_processor.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_crc_inserter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_inject_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_packet_injection.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_shiftreg_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_simple_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+sockit_owm.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_async_rx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_async_tx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_baud_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_uart_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_addsub.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_slave_adapter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_eic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_fifo_sync.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+jtag_tap.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_syscon_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_pulse_synchronizer2.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dmtd_phase_meas.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+softpll_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_1000basex_pcs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_timestamping_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_leds_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_wishbone_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pps_gen_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+jtag_cores.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_adder.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_dp_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_logic_op.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_shifter.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+minic_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_multiplier.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_aligner.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_frequency_meter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gen7s_cores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+sdb_rom.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_allprofiles.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrcore_2p_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwrf_mux.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_clgen.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_shift.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_sdb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_lm32.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_periph.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrcore_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+disparity_gen_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spec_serial_dac.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_top.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+PLL_SPI_ctrl_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+whiterabbit_gtxe2_channel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spec_serial_dac_arb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_a7_gtps_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ext_pll_10_to_62_compensated.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_gtx_phy_kintex7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBuffer.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferVector.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+shiftRegister.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_defines.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+si570_if_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+eca_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_wbm_bridge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_irq_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_cores_pkg_gsi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_pwm_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xloader_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_sync_block.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_gtrxreset_seq.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp2p_wizard_sync_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_channel_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp2p_wizard_tx_manual_phase_align.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_gtp_phy_artix7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_include.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+timescale.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp_bitslide.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_1p_kintex7_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_wrc_1p_kintex7_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 ipif_pkg.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/ipif_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 pselect_f.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/pselect_f.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh
index 0bf585dda1266b8b201cafa0a7ec25a1c1439b19..432891589a088f39dc5b44dbc7c65d8750f258e8 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh
@@ -8,7 +8,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 23 21:34:31 CET 2017
+# Generated by Vivado on Mon Mar 27 12:41:43 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016 
 #
 # usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt
index 81da9d7b7246e326db4f3d40ab6fca37dd46de99..b6111e2287fef43e1c453321676307cba73b3cee 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Mar 23 21:34:31 CET 2017
+# Generated by export_simulation on Mon Mar 27 12:41:43 CEST 2017
 #
 ################################################################################
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt
index 23502fe7e040613b444afdcf973e47f1476239c5..0f25994269e41affba8c14d42771980744ab176b 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
 processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -232,152 +232,152 @@ system_design_axi_dma_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/s
 xlconcat.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/xilinx.com/xlconcat_v2_1/xlconcat.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_xlconcat_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_xlconcat_0_0/sim/system_design_xlconcat_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 mux_buffering_fifo.v,verilog,fifo_generator_v13_1_1,../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/sim/mux_buffering_fifo.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-genram_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-memory_loader_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wishbone_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_fabric_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram_dualclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-endpoint_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gencores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-endpoint_private_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-inferred_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-inferred_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_crc32_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_sync_detect.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_sync_detect_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_crc_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_extend_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_sync_ffs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_pulse_synchronizer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_shiftreg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_uart_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dmtd_with_deglitcher.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-minic_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_autonegotiation.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_pcs_tbi_mdio_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_wb_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_oob_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_early_address_match.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_clock_alignment_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_packet_filter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_ts_counter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_status_reg_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rtu_header_extract.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_buffer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_crc_size_check.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_header_processor.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_crc_inserter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_inject_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_packet_injection.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_shiftreg_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_simple_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-sockit_owm.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_async_rx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_async_tx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_baud_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_uart_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_addsub.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_slave_adapter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_eic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_fifo_sync.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-jtag_tap.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_syscon_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_pulse_synchronizer2.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dmtd_phase_meas.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-softpll_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_1000basex_pcs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_timestamping_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_leds_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_wishbone_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pps_gen_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-jtag_cores.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_adder.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_dp_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_logic_op.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_shifter.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-minic_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_multiplier.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_aligner.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_frequency_meter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gen7s_cores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-sdb_rom.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_allprofiles.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrcore_2p_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwrf_mux.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_clgen.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_shift.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_sdb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_lm32.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_periph.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrcore_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-disparity_gen_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spec_serial_dac.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_top.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-PLL_SPI_ctrl_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp_bitslide.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-whiterabbit_gtxe2_channel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spec_serial_dac_arb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_a7_gtps_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ext_pll_10_to_62_compensated.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_gtx_phy_kintex7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBuffer.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferVector.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-shiftRegister.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_defines.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-si570_if_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-eca_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_wbm_bridge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_irq_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_cores_pkg_gsi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_pwm_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xloader_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_sync_block.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_gtrxreset_seq.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp2p_wizard_sync_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_channel_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp2p_wizard_tx_manual_phase_align.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_gtp_phy_artix7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_include.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-timescale.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_1p_kintex7_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+genram_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+memory_loader_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wishbone_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_fabric_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram_dualclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+endpoint_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gencores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+endpoint_private_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+inferred_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+inferred_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_crc32_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_sync_detect.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_sync_detect_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_crc_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_extend_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_sync_ffs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_pulse_synchronizer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_shiftreg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_uart_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dmtd_with_deglitcher.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+minic_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_autonegotiation.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_pcs_tbi_mdio_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_wb_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_oob_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_early_address_match.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_clock_alignment_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_packet_filter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_ts_counter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_status_reg_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rtu_header_extract.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_buffer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_crc_size_check.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_header_processor.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_crc_inserter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_inject_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_packet_injection.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_shiftreg_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_simple_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+sockit_owm.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_async_rx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_async_tx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_baud_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_uart_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_addsub.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_slave_adapter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_eic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_fifo_sync.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+jtag_tap.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_syscon_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_pulse_synchronizer2.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dmtd_phase_meas.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+softpll_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_1000basex_pcs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_timestamping_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_leds_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_wishbone_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pps_gen_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+jtag_cores.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_adder.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_dp_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_logic_op.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_shifter.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+minic_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_multiplier.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_aligner.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_frequency_meter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gen7s_cores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+sdb_rom.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_allprofiles.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrcore_2p_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwrf_mux.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_clgen.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_shift.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_sdb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_lm32.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_periph.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrcore_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+disparity_gen_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spec_serial_dac.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_top.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+PLL_SPI_ctrl_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+whiterabbit_gtxe2_channel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spec_serial_dac_arb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_a7_gtps_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ext_pll_10_to_62_compensated.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_gtx_phy_kintex7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBuffer.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferVector.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+shiftRegister.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_defines.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+si570_if_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+eca_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_wbm_bridge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_irq_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_cores_pkg_gsi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_pwm_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xloader_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_sync_block.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_gtrxreset_seq.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp2p_wizard_sync_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_channel_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp2p_wizard_tx_manual_phase_align.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_gtp_phy_artix7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_include.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+timescale.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp_bitslide.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_1p_kintex7_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_wrc_1p_kintex7_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 ipif_pkg.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/ipif_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 pselect_f.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/pselect_f.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh
index c2e9e127e11569e5356b01937461e71b6b240f12..6681be8b5a7ada96c7451697d3b547766efcf39c 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh
@@ -8,7 +8,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 23 21:34:31 CET 2017
+# Generated by Vivado on Mon Mar 27 12:41:43 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016 
 #
 # usage: system_design.sh [-help]
@@ -113,25 +113,25 @@ compile()
   2>&1 | tee -a vlogan.log
 
   vhdlan -work hdl_lib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vhdlan -work hdl_lib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
     "$ref_dir/../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
   2>&1 | tee -a vhdlan.log
 
@@ -398,233 +398,233 @@ compile()
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" +incdir+"$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" \
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" +incdir+"$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" \
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" +incdir+"$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v" \
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" +incdir+"$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" \
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" +incdir+"$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" \
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" +incdir+"$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" \
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" +incdir+"$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v" \
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" +incdir+"$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" \
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" +incdir+"$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" \
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" +incdir+"$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" \
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vhdlan -work hdl_lib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" +incdir+"$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" \
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vhdlan -work hdl_lib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" +incdir+"$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" \
   2>&1 | tee -a vlogan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd" \
     "$ref_dir/../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd" \
   2>&1 | tee -a vhdlan.log
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt
index 81da9d7b7246e326db4f3d40ab6fca37dd46de99..b6111e2287fef43e1c453321676307cba73b3cee 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Mar 23 21:34:31 CET 2017
+# Generated by export_simulation on Mon Mar 27 12:41:43 CEST 2017
 #
 ################################################################################
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt
index 23502fe7e040613b444afdcf973e47f1476239c5..0f25994269e41affba8c14d42771980744ab176b 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
 processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -232,152 +232,152 @@ system_design_axi_dma_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/s
 xlconcat.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/xilinx.com/xlconcat_v2_1/xlconcat.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_xlconcat_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_xlconcat_0_0/sim/system_design_xlconcat_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 mux_buffering_fifo.v,verilog,fifo_generator_v13_1_1,../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/sim/mux_buffering_fifo.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-genram_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-memory_loader_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wishbone_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_fabric_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram_dualclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-endpoint_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gencores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-endpoint_private_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-inferred_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-inferred_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_crc32_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_sync_detect.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_sync_detect_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_crc_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_extend_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_sync_ffs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_pulse_synchronizer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_shiftreg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_uart_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dmtd_with_deglitcher.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-minic_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_autonegotiation.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_pcs_tbi_mdio_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_wb_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_oob_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_early_address_match.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_clock_alignment_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_packet_filter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_ts_counter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_status_reg_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rtu_header_extract.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_buffer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_crc_size_check.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_header_processor.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_crc_inserter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_inject_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_packet_injection.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_shiftreg_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-generic_simple_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-sockit_owm.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_async_rx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_async_tx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-uart_baud_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_uart_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_addsub.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_slave_adapter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_eic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wbgen2_fifo_sync.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-jtag_tap.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_syscon_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_pulse_synchronizer2.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dmtd_phase_meas.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-softpll_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_1000basex_pcs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_rx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_timestamping_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_leds_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_wishbone_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pps_gen_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ep_tx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-jtag_cores.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_adder.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_dp_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_logic_op.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_shifter.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-minic_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_multiplier.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spll_aligner.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gc_frequency_meter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gen7s_cores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-sdb_rom.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_allprofiles.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrcore_2p_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwrf_mux.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_clgen.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_shift.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_sdb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwb_lm32.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_periph.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrcore_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-disparity_gen_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spec_serial_dac.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_top.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-PLL_SPI_ctrl_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp_bitslide.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-whiterabbit_gtxe2_channel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spec_serial_dac_arb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_a7_gtps_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-ext_pll_10_to_62_compensated.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xwr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_gtx_phy_kintex7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBuffer.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferVector.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-shiftRegister.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_defines.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-si570_if_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-eca_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axis_wbm_bridge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_irq_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wb_cores_pkg_gsi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-simple_pwm_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xloader_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_sync_block.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_gtrxreset_seq.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp2p_wizard_sync_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtpe_channel_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-gtp2p_wizard_tx_manual_phase_align.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wr_gtp_phy_artix7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-lm32_include.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-timescale.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-wrc_1p_kintex7_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+genram_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+memory_loader_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wishbone_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_fabric_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram_dualclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_dpram_sameclock.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+endpoint_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gencores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+endpoint_private_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+inferred_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+inferred_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_crc32_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_sync_detect.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_sync_detect_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_crc_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_extend_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_sync_ffs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_pulse_synchronizer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_shiftreg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_async_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_sync_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_uart_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dmtd_with_deglitcher.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+minic_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_pcs_16bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_autonegotiation.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_pcs_tbi_mdio_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_wb_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_oob_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_early_address_match.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_clock_alignment_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_packet_filter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_ts_counter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_status_reg_insert.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rtu_header_extract.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_buffer.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_pcs_8bit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_crc_size_check.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_header_processor.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_crc_inserter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_inject_ctrl.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_packet_injection.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_vlan_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_shiftreg_fifo.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+generic_simple_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+sockit_owm.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_async_rx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_async_tx.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+uart_baud_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_uart_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_addsub.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_slave_adapter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_eic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wbgen2_fifo_sync.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+jtag_tap.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_syscon_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_pulse_synchronizer2.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dmtd_phase_meas.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+softpll_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_1000basex_pcs.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_rx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_timestamping_unit.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_leds_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_wishbone_controller.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pps_gen_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ep_tx_path.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+jtag_cores.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_adder.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_dp_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_logic_op.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_ram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_shifter.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+minic_wb_slave.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_multiplier.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spll_aligner.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gc_frequency_meter.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gen7s_cores_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_onewire_master.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_simple_uart.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+sdb_rom.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_syscon_wb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_allprofiles.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrcore_2p_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwrf_mux.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_mini_nic.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_softpll_ng.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_endpoint.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_pps_gen.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_dpram.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_clgen.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_shift.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_sdb_crossbar.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwb_lm32.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_periph.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrcore_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+disparity_gen_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spec_serial_dac.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_top.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+PLL_SPI_ctrl_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+whiterabbit_gtxe2_channel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spec_serial_dac_arb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_a7_gtps_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+ext_pll_10_to_62_compensated.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xwr_core.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_gtx_phy_kintex7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBuffer.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferVector.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+shiftRegister.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_defines.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+si570_if_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+eca_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axis_wbm_bridge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_irq_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wb_cores_pkg_gsi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+simple_pwm_wbgen2_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xloader_registers_pkg.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_sync_block.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_gtrxreset_seq.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp2p_wizard_sync_pulse.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtpe_channel_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp2p_wizard_tx_manual_phase_align.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wr_gtp_phy_artix7.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+lm32_include.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+timescale.v,verilog,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+gtp_bitslide.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+wrc_1p_kintex7_top.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_wrc_1p_kintex7_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 ipif_pkg.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/ipif_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 pselect_f.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/pselect_f.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh
index 5e2f35485de46bd83035033f39fbfa3bcde39dea..f8734cd3d00705f65cb1fabbac39f1ecb1dd5806 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh
@@ -8,7 +8,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Mar 23 21:34:31 CET 2017
+# Generated by Vivado on Mon Mar 27 12:41:43 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016 
 #
 # usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj
index f97e8b4bfe2469041d113c2a3feb3c22b4b1c13f..8ae6e01f5074b725f2571e937c45b752918206af 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj
@@ -1,14 +1,14 @@
 vhdl xpm "/local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" 
 vhdl xil_defaultlib "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" 
 vhdl lib_cdc_v1_0_2 "../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd" 
 vhdl proc_sys_reset_v5_0_9 "../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd" 
@@ -156,137 +156,137 @@ vhdl axi_dma_v7_1_10 "../../../ipstatic/axi_dma_v7_1/hdl/src/vhdl/axi_dma.vhd"
 vhdl xil_defaultlib "../../../bd/system_design/ip/system_design_axi_dma_0_0/sim/system_design_axi_dma_0_0.vhd" 
 vhdl xil_defaultlib "../../../bd/system_design/ipshared/xilinx.com/xlconcat_v2_1/xlconcat.vhd" 
 vhdl xil_defaultlib "../../../bd/system_design/ip/system_design_xlconcat_0_0/sim/system_design_xlconcat_0_0.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" 
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+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" 
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+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" 
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+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" 
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+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd" 
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+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" 
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+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" 
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+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" 
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+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" 
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+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" 
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+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd" 
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+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd" 
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+vhdl hdl_lib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd" 
 vhdl xil_defaultlib "../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd" 
 vhdl axi_lite_ipif_v3_0_4 "../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/ipif_pkg.vhd" 
 vhdl axi_lite_ipif_v3_0_4 "../../../ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/pselect_f.vhd" 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vlog.prj b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vlog.prj
index 1e68646a0bbdb401f48d34fa77e09901129e0705..cacc3d8d6341097b4281e8aa0a9f97ea66c02d77 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vlog.prj
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vlog.prj
@@ -74,21 +74,21 @@ verilog axi_crossbar_v2_1_10 "../../../ipstatic/axi_crossbar_v2_1/hdl/verilog/ax
 verilog axi_crossbar_v2_1_10 "../../../ipstatic/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_axi_crossbar.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 verilog xil_defaultlib "../../../bd/system_design/ip/system_design_xbar_0/sim/system_design_xbar_0.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 verilog fifo_generator_v13_1_1 "../../../bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/sim/mux_buffering_fifo.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+verilog xil_defaultlib "../../../bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 verilog axi_protocol_converter_v2_1_9 "../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 verilog axi_protocol_converter_v2_1_9 "../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 verilog axi_protocol_converter_v2_1_9 "../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v" --include "../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" --include "../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc b/FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc
index 7d50ebc2abf5439f91152e63226dd177b3f71939..11ce94c01db2d111e637f8b61fce96158fa5367d 100644
--- a/FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc
+++ b/FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc
@@ -306,9 +306,6 @@ set_property IOSTANDARD LVCMOS18 [get_ports clk_25m_vcxo_i]
 set_property PACKAGE_PIN G14 [get_ports gtp0_rate_select_b]
 set_property IOSTANDARD LVCMOS18 [get_ports gtp0_rate_select_b]
 
-set_property PACKAGE_PIN G7 [get_ports clk_aux_p_i]
-set_property IOSTANDARD LVDS [get_ports clk_aux_p_i]
-set_property IOSTANDARD LVDS [get_ports clk_aux_n_i]
 set_property PACKAGE_PIN K7 [get_ports dac_cs1_n_o]
 set_property PACKAGE_PIN N7 [get_ports dac_cs2_n_o]
 set_property PACKAGE_PIN K8 [get_ports dac_din_o]
@@ -334,7 +331,6 @@ set_property IOSTANDARD LVCMOS18 [get_ports gtp_wr_tx_fault]
 set_property IOSTANDARD LVCMOS18 [get_ports gtp_wr_rx_los]
 set_property IOSTANDARD LVCMOS18 [get_ports gtp_wr_mod_abs]
 create_clock -period 50.000 -name wr_25m -waveform {0.000 25.000} [get_ports clk_25m_vcxo_i]
-create_clock -period 8.000 -name wr_125M_fpga -waveform {0.000 4.000} [get_ports clk_aux_p_i]
 create_clock -period 8.000 -name wr_125M_sfp -waveform {0.000 4.000} [get_ports gtp_dedicated_clk_p_i]
 
 
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef
index 6f8d472acc200ef862282385a67857a46462a937..70a01ec080c2bb3322177982bfda409baca18c3d 100644
Binary files a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef and b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef differ
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
index 9ca0a5c7f7535f90251e5e1d43ae3658716bf6ca..2e691d93a743187fcb9361ddc3a192aa7c5b5efc 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
@@ -1,7 +1,7 @@
 --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------
 --Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
---Date        : Thu Mar 23 21:34:22 2017
+--Date        : Mon Mar 27 12:41:35 2017
 --Host        : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
 --Command     : generate_target system_design.bd
 --Design      : system_design
@@ -3608,8 +3608,6 @@ entity system_design is
     Vp_Vn_v_n : in STD_LOGIC;
     Vp_Vn_v_p : in STD_LOGIC;
     clk_25m_vcxo_i : in STD_LOGIC;
-    clk_aux_n_i : in STD_LOGIC;
-    clk_aux_p_i : in STD_LOGIC;
     dac_cs1_n_o : out STD_LOGIC;
     dac_cs2_n_o : out STD_LOGIC;
     dac_din_o : out STD_LOGIC;
@@ -3646,10 +3644,10 @@ entity system_design is
     thermo_id : inout STD_LOGIC;
     watchdog_pl_o : out STD_LOGIC
   );
-  attribute CORE_GENERATION_INFO : string;
-  attribute CORE_GENERATION_INFO of system_design : entity is "system_design,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system_design,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=32,numReposBlks=18,numNonXlnxBlks=4,numHierBlks=14,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=14,da_board_cnt=5,da_ps7_cnt=1,synth_mode=Global}";
   attribute HW_HANDOFF : string;
   attribute HW_HANDOFF of system_design : entity is "system_design.hwdef";
+  attribute core_generation_info : string;
+  attribute core_generation_info of system_design : entity is "system_design,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system_design,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=32,numReposBlks=18,numNonXlnxBlks=4,numHierBlks=14,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=14,da_board_cnt=5,da_ps7_cnt=1,synth_mode=Global}";
 end system_design;
 
 architecture STRUCTURE of system_design is
@@ -4130,10 +4128,11 @@ architecture STRUCTURE of system_design is
   component system_design_wrc_1p_kintex7_0_0 is
   port (
     clk_20m_vcxo_i : in STD_LOGIC;
-    clk_aux_p_i : in STD_LOGIC;
-    clk_aux_n_i : in STD_LOGIC;
     gtp_dedicated_clk_p_i : in STD_LOGIC;
     gtp_dedicated_clk_n_i : in STD_LOGIC;
+    clk_dmtd_b : inout STD_LOGIC;
+    clk_ref_b : inout STD_LOGIC;
+    clk_rx_rbclk_b : inout STD_LOGIC;
     gtp0_activity_led_o : out STD_LOGIC;
     gtp0_synced_led_o : out STD_LOGIC;
     gtp0_link_led_o : out STD_LOGIC;
@@ -4315,8 +4314,6 @@ architecture STRUCTURE of system_design is
   signal axi_wb_i2c_master_0_axi_int_o : STD_LOGIC;
   signal axi_wb_i2c_master_2_axi_int_o : STD_LOGIC;
   signal clk_25m_vcxo_i_1 : STD_LOGIC;
-  signal clk_aux_n_i_1 : STD_LOGIC;
-  signal clk_aux_p_i_1 : STD_LOGIC;
   signal dig_in1_i_1 : STD_LOGIC;
   signal dig_in2_i_1 : STD_LOGIC;
   signal dig_in3_n_i_1 : STD_LOGIC;
@@ -4593,6 +4590,9 @@ architecture STRUCTURE of system_design is
   signal NLW_rst_wrc_1p_kintex7_0_62M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
   signal NLW_rst_wrc_1p_kintex7_0_62M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
   signal NLW_wrc_1p_kintex7_0_axi_int_o_UNCONNECTED : STD_LOGIC;
+  signal NLW_wrc_1p_kintex7_0_clk_dmtd_b_UNCONNECTED : STD_LOGIC;
+  signal NLW_wrc_1p_kintex7_0_clk_ref_b_UNCONNECTED : STD_LOGIC;
+  signal NLW_wrc_1p_kintex7_0_clk_rx_rbclk_b_UNCONNECTED : STD_LOGIC;
   signal NLW_wrc_1p_kintex7_0_gtp0_activity_led_o_UNCONNECTED : STD_LOGIC;
   signal NLW_wrc_1p_kintex7_0_gtp0_link_led_o_UNCONNECTED : STD_LOGIC;
   signal NLW_wrc_1p_kintex7_0_gtp0_synced_led_o_UNCONNECTED : STD_LOGIC;
@@ -4636,8 +4636,6 @@ begin
   Vp_Vn_1_V_N <= Vp_Vn_v_n;
   Vp_Vn_1_V_P <= Vp_Vn_v_p;
   clk_25m_vcxo_i_1 <= clk_25m_vcxo_i;
-  clk_aux_n_i_1 <= clk_aux_n_i;
-  clk_aux_p_i_1 <= clk_aux_p_i;
   dac_cs1_n_o <= wrc_1p_kintex7_0_dac_cs1_n_o;
   dac_cs2_n_o <= wrc_1p_kintex7_0_dac_cs2_n_o;
   dac_din_o <= wrc_1p_kintex7_0_dac_din_o;
@@ -5342,8 +5340,9 @@ wrc_1p_kintex7_0: component system_design_wrc_1p_kintex7_0_0
       axi_int_o => NLW_wrc_1p_kintex7_0_axi_int_o_UNCONNECTED,
       button_rst_n_i => pb_gp_i_1,
       clk_20m_vcxo_i => clk_25m_vcxo_i_1,
-      clk_aux_n_i => clk_aux_n_i_1,
-      clk_aux_p_i => clk_aux_p_i_1,
+      clk_dmtd_b => NLW_wrc_1p_kintex7_0_clk_dmtd_b_UNCONNECTED,
+      clk_ref_b => NLW_wrc_1p_kintex7_0_clk_ref_b_UNCONNECTED,
+      clk_rx_rbclk_b => NLW_wrc_1p_kintex7_0_clk_rx_rbclk_b_UNCONNECTED,
       dac_cs1_n_o => wrc_1p_kintex7_0_dac_cs1_n_o,
       dac_cs2_n_o => wrc_1p_kintex7_0_dac_cs2_n_o,
       dac_din_o => wrc_1p_kintex7_0_dac_din_o,
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
index 7c40387d0983ff57b552d4a088dc1879589bc29e..cf25eee6b79cb5daff365f5d7b78012df656e551 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
@@ -1,7 +1,7 @@
 --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------
 --Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
---Date        : Thu Mar 23 21:34:22 2017
+--Date        : Mon Mar 27 12:41:36 2017
 --Host        : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
 --Command     : generate_target system_design_wrapper.bd
 --Design      : system_design_wrapper
@@ -63,8 +63,6 @@ entity system_design_wrapper is
     Vp_Vn_v_n : in STD_LOGIC;
     Vp_Vn_v_p : in STD_LOGIC;
     clk_25m_vcxo_i : in STD_LOGIC;
-    clk_aux_n_i : in STD_LOGIC;
-    clk_aux_p_i : in STD_LOGIC;
     dac_cs1_n_o : out STD_LOGIC;
     dac_cs2_n_o : out STD_LOGIC;
     dac_din_o : out STD_LOGIC;
@@ -188,8 +186,6 @@ architecture STRUCTURE of system_design_wrapper is
     gtp0_rate_select_b : inout STD_LOGIC;
     eeprom_scl : inout STD_LOGIC;
     eeprom_sda : inout STD_LOGIC;
-    clk_aux_p_i : in STD_LOGIC;
-    clk_aux_n_i : in STD_LOGIC;
     gtp_dedicated_clk_p_i : in STD_LOGIC;
     gtp_dedicated_clk_n_i : in STD_LOGIC;
     dig_out6_n : out STD_LOGIC_VECTOR ( 0 to 0 )
@@ -248,8 +244,6 @@ system_design_i: component system_design
       Vp_Vn_v_n => Vp_Vn_v_n,
       Vp_Vn_v_p => Vp_Vn_v_p,
       clk_25m_vcxo_i => clk_25m_vcxo_i,
-      clk_aux_n_i => clk_aux_n_i,
-      clk_aux_p_i => clk_aux_p_i,
       dac_cs1_n_o => dac_cs1_n_o,
       dac_cs2_n_o => dac_cs2_n_o,
       dac_din_o => dac_din_o,
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
index 04e163758102f9a5ad50b414b93cd2737ba78548..258b33d80c0b59fb831d48f925bad1e981eb8875 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu Mar 23 21:34:26 2017" VIVADOVERSION="2016.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Mon Mar 27 12:41:39 2017" VIVADOVERSION="2016.2">
 
   <SYSTEMINFO ARCH="zynq" DEVICE="7z030" NAME="system_design" PACKAGE="ffg676" SPEEDGRADE="-2"/>
 
@@ -235,16 +235,6 @@
         <CONNECTION INSTANCE="wrc_1p_kintex7_0" PORT="fpga_sda_b"/>
       </CONNECTIONS>
     </PORT>
-    <PORT DIR="I" NAME="clk_aux_p_i" SIGIS="undef" SIGNAME="External_Ports_clk_aux_p_i">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="wrc_1p_kintex7_0" PORT="clk_aux_p_i"/>
-      </CONNECTIONS>
-    </PORT>
-    <PORT DIR="I" NAME="clk_aux_n_i" SIGIS="undef" SIGNAME="External_Ports_clk_aux_n_i">
-      <CONNECTIONS>
-        <CONNECTION INSTANCE="wrc_1p_kintex7_0" PORT="clk_aux_n_i"/>
-      </CONNECTIONS>
-    </PORT>
     <PORT DIR="I" NAME="gtp_dedicated_clk_p_i" SIGIS="undef" SIGNAME="External_Ports_gtp_dedicated_clk_p_i">
       <CONNECTIONS>
         <CONNECTION INSTANCE="wrc_1p_kintex7_0" PORT="gtp_dedicated_clk_p_i"/>
@@ -3694,7 +3684,7 @@
         </BUSINTERFACE>
       </BUSINTERFACES>
     </MODULE>
-    <MODULE FULLNAME="/fasec_hwtest_0" HWVERSION="3.0.1" INSTANCE="fasec_hwtest_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="fasec_hwtest" VLNV="user.org:user:fasec_hwtest:3.0.1">
+    <MODULE FULLNAME="/fasec_hwtest_0" HWVERSION="3.1.0" INSTANCE="fasec_hwtest_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="fasec_hwtest" VLNV="user.org:user:fasec_hwtest:3.1.0">
       <DOCUMENTS/>
       <ADDRESSBLOCKS>
         <ADDRESSBLOCK ACCESS="" INTERFACE="S00_AXI" NAME="S00_AXI_reg" RANGE="4096" USAGE=""/>
@@ -5560,6 +5550,8 @@
             <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_aclk"/>
             <CONNECTION INSTANCE="xadc_wiz_0" PORT="s_axis_aclk"/>
             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aclk"/>
+            <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aclk"/>
+            <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aclk"/>
             <CONNECTION INSTANCE="axi_interconnect_0" PORT="ACLK"/>
             <CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="ACLK"/>
             <CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M06_ACLK"/>
@@ -5573,8 +5565,6 @@
             <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_ACLK"/>
             <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_ACLK"/>
             <CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M07_ACLK"/>
-            <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aclk"/>
-            <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aclk"/>
             <CONNECTION INSTANCE="fasec_hwtest_0" PORT="ps_clk_i"/>
             <CONNECTION INSTANCE="fasec_hwtest_0" PORT="s00_axi_aclk"/>
           </CONNECTIONS>
@@ -7402,6 +7392,8 @@
             <CONNECTION INSTANCE="axi_dma_0" PORT="axi_resetn"/>
             <CONNECTION INSTANCE="xadc_axis_fifo_adapter_0" PORT="AXIS_RESET_N"/>
             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aresetn"/>
+            <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aresetn"/>
+            <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aresetn"/>
             <CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="S00_ARESETN"/>
             <CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M06_ARESETN"/>
             <CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M05_ARESETN"/>
@@ -7414,8 +7406,6 @@
             <CONNECTION INSTANCE="axi_interconnect_0" PORT="ARESETN"/>
             <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_ARESETN"/>
             <CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M07_ARESETN"/>
-            <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aresetn"/>
-            <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aresetn"/>
             <CONNECTION INSTANCE="fasec_hwtest_0" PORT="s00_axi_aresetn"/>
           </CONNECTIONS>
         </PORT>
@@ -7473,7 +7463,7 @@
       </PORTS>
       <BUSINTERFACES/>
     </MODULE>
-    <MODULE FULLNAME="/wrc_1p_kintex7_0" HWVERSION="2.3.1" INSTANCE="wrc_1p_kintex7_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="wrc_1p_kintex7" VLNV="CERN:wrc:wrc_1p_kintex7:2.3.1">
+    <MODULE FULLNAME="/wrc_1p_kintex7_0" HWVERSION="3.1.0" INSTANCE="wrc_1p_kintex7_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="wrc_1p_kintex7" VLNV="CERN:wrc:wrc_1p_kintex7:3.1.0">
       <DOCUMENTS/>
       <PARAMETERS>
         <PARAMETER NAME="TAR_ADDR_WDTH" VALUE="13"/>
@@ -7488,16 +7478,6 @@
             <CONNECTION INSTANCE="External_Ports" PORT="clk_25m_vcxo_i"/>
           </CONNECTIONS>
         </PORT>
-        <PORT DIR="I" NAME="clk_aux_p_i" SIGIS="undef" SIGNAME="External_Ports_clk_aux_p_i">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External_Ports" PORT="clk_aux_p_i"/>
-          </CONNECTIONS>
-        </PORT>
-        <PORT DIR="I" NAME="clk_aux_n_i" SIGIS="undef" SIGNAME="External_Ports_clk_aux_n_i">
-          <CONNECTIONS>
-            <CONNECTION INSTANCE="External_Ports" PORT="clk_aux_n_i"/>
-          </CONNECTIONS>
-        </PORT>
         <PORT DIR="I" NAME="gtp_dedicated_clk_p_i" SIGIS="undef" SIGNAME="External_Ports_gtp_dedicated_clk_p_i">
           <CONNECTIONS>
             <CONNECTION INSTANCE="External_Ports" PORT="gtp_dedicated_clk_p_i"/>
@@ -7508,6 +7488,9 @@
             <CONNECTION INSTANCE="External_Ports" PORT="gtp_dedicated_clk_n_i"/>
           </CONNECTIONS>
         </PORT>
+        <PORT DIR="IO" NAME="clk_dmtd_b" SIGIS="undef"/>
+        <PORT DIR="IO" NAME="clk_ref_b" SIGIS="undef"/>
+        <PORT DIR="IO" NAME="clk_rx_rbclk_b" SIGIS="undef"/>
         <PORT DIR="O" NAME="gtp0_activity_led_o" SIGIS="undef"/>
         <PORT DIR="O" NAME="gtp0_synced_led_o" SIGIS="undef"/>
         <PORT DIR="O" NAME="gtp0_link_led_o" SIGIS="undef"/>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
index c508903fa1008a5fd78eb69252b5745943cc2e7a..cc3f4a7e18f6e1c10c786d1a826a2e24be3d3180 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
@@ -180,8 +180,6 @@ proc create_root_design { parentCell } {
   set FMC2_LA_P_b [ create_bd_port -dir IO -from 33 -to 0 FMC2_LA_P_b ]
   set FMC2_PRSNTM2C_n_i [ create_bd_port -dir I FMC2_PRSNTM2C_n_i ]
   set clk_25m_vcxo_i [ create_bd_port -dir I clk_25m_vcxo_i ]
-  set clk_aux_n_i [ create_bd_port -dir I clk_aux_n_i ]
-  set clk_aux_p_i [ create_bd_port -dir I clk_aux_p_i ]
   set dac_cs1_n_o [ create_bd_port -dir O dac_cs1_n_o ]
   set dac_cs2_n_o [ create_bd_port -dir O dac_cs2_n_o ]
   set dac_din_o [ create_bd_port -dir O dac_din_o ]
@@ -249,7 +247,7 @@ CONFIG.C_S_AXI_ACLK_FREQ_HZ.VALUE_SRC {DEFAULT} \
   set axi_wb_i2c_master_2 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.1.1 axi_wb_i2c_master_2 ]
 
   # Create instance: fasec_hwtest_0, and set properties
-  set fasec_hwtest_0 [ create_bd_cell -type ip -vlnv user.org:user:fasec_hwtest:3.0.1 fasec_hwtest_0 ]
+  set fasec_hwtest_0 [ create_bd_cell -type ip -vlnv user.org:user:fasec_hwtest:3.1.0 fasec_hwtest_0 ]
   set_property -dict [ list \
 CONFIG.g_FMC1 {EDA-03287} \
 CONFIG.g_FMC2 {EDA-03287} \
@@ -1458,7 +1456,7 @@ CONFIG.NUM_SI {1} \
   set rst_wrc_1p_kintex7_0_62M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_wrc_1p_kintex7_0_62M ]
 
   # Create instance: wrc_1p_kintex7_0, and set properties
-  set wrc_1p_kintex7_0 [ create_bd_cell -type ip -vlnv CERN:wrc:wrc_1p_kintex7:2.3.1 wrc_1p_kintex7_0 ]
+  set wrc_1p_kintex7_0 [ create_bd_cell -type ip -vlnv CERN:wrc:wrc_1p_kintex7:3.1.0 wrc_1p_kintex7_0 ]
 
   # Create instance: xadc_axis_fifo_adapter_0, and set properties
   set xadc_axis_fifo_adapter_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:xadc_axis_fifo_adapter:1.0 xadc_axis_fifo_adapter_0 ]
@@ -1585,8 +1583,6 @@ CONFIG.CONST_WIDTH {1} \
   connect_bd_net -net axi_wb_i2c_master_0_axi_int_o [get_bd_pins axi_wb_i2c_master_0/axi_int_o] [get_bd_pins xlconcat_0/In3]
   connect_bd_net -net axi_wb_i2c_master_2_axi_int_o [get_bd_pins axi_wb_i2c_master_2/axi_int_o] [get_bd_pins xlconcat_0/In2]
   connect_bd_net -net clk_25m_vcxo_i_1 [get_bd_ports clk_25m_vcxo_i] [get_bd_pins wrc_1p_kintex7_0/clk_20m_vcxo_i]
-  connect_bd_net -net clk_aux_n_i_1 [get_bd_ports clk_aux_n_i] [get_bd_pins wrc_1p_kintex7_0/clk_aux_n_i]
-  connect_bd_net -net clk_aux_p_i_1 [get_bd_ports clk_aux_p_i] [get_bd_pins wrc_1p_kintex7_0/clk_aux_p_i]
   connect_bd_net -net dig_in1_i_1 [get_bd_ports dig_in1_i] [get_bd_pins fasec_hwtest_0/dig_in1_i]
   connect_bd_net -net dig_in2_i_1 [get_bd_ports dig_in2_i] [get_bd_pins fasec_hwtest_0/dig_in2_i]
   connect_bd_net -net dig_in3_n_i_1 [get_bd_ports dig_in3_n_i] [get_bd_pins fasec_hwtest_0/dig_in3_n_i]
@@ -1664,7 +1660,6 @@ preplace port FMC1_CLK0C2M_P_o -pg 1 -y 240 -defaultsOSRD
 preplace port FMC2_CLK0M2C_P_i -pg 1 -y 180 -defaultsOSRD
 preplace port FMC2_PRSNTM2C_n_i -pg 1 -y 160 -defaultsOSRD
 preplace port Vaux10 -pg 1 -y 1010 -defaultsOSRD
-preplace port clk_aux_p_i -pg 1 -y 1240 -defaultsOSRD
 preplace port dac_din_o -pg 1 -y 1270 -defaultsOSRD
 preplace port FMC1_PRSNTM2C_n_i -pg 1 -y 220 -defaultsOSRD
 preplace port gtp_wr -pg 1 -y 1150 -defaultsOSRD
@@ -1681,7 +1676,6 @@ preplace port FMC1_CLK0C2M_N_o -pg 1 -y 260 -defaultsOSRD
 preplace port pb_gp_i -pg 1 -y 1200 -defaultsOSRD
 preplace port dig_out5_n -pg 1 -y 460 -defaultsOSRD
 preplace port Vaux8 -pg 1 -y 970 -defaultsOSRD
-preplace port clk_aux_n_i -pg 1 -y 1260 -defaultsOSRD
 preplace port dac_sclk_o -pg 1 -y 1250 -defaultsOSRD
 preplace port FMC2_CLK0C2M_N_o -pg 1 -y 140 -defaultsOSRD
 preplace port FMC2_CLK0C2M_P_o -pg 1 -y 120 -defaultsOSRD
@@ -1715,39 +1709,38 @@ preplace netloc fasec_hwtest_0_led_col_pl_o 1 9 1 NJ
 preplace netloc dig_in4_n_i_1 1 0 9 NJ 160 NJ 160 NJ 160 NJ 160 NJ 160 NJ 160 NJ 160 NJ 160 NJ
 preplace netloc processing_system7_0_FIXED_IO 1 7 3 NJ 740 NJ 740 NJ
 preplace netloc fasec_hwtest_0_dig_outs_i 1 9 1 NJ
-preplace netloc gtp_dedicated_clk_n_i_1 1 0 9 NJ 1300 NJ 1300 NJ 1300 NJ 1300 NJ 1300 NJ 1300 NJ 1300 NJ 1300 NJ
+preplace netloc gtp_dedicated_clk_n_i_1 1 0 9 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ
 preplace netloc wrc_1p_kintex7_0_dac_din_o 1 9 1 NJ
-preplace netloc gtp_dedicated_clk_p_i_1 1 0 9 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ
-preplace netloc axi_uartlite_0_tx 1 3 7 N 690 NJ 690 NJ 750 NJ 660 NJ 660 NJ 660 3170
-preplace netloc dig_in3_n_i_1 1 0 9 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 NJ
-preplace netloc FMC1_PRSNTM2C_n_i_1 1 0 9 NJ 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ
-preplace netloc dig_in1_i_1 1 0 9 NJ 250 NJ 250 NJ 250 NJ 250 NJ 250 NJ 250 NJ 250 NJ 250 NJ
-preplace netloc xlconcat_0_dout 1 6 1 1970
+preplace netloc gtp_dedicated_clk_p_i_1 1 0 9 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ
+preplace netloc axi_uartlite_0_tx 1 3 7 1030 700 NJ 700 NJ 750 NJ 660 NJ 660 NJ 660 3180
+preplace netloc dig_in3_n_i_1 1 0 9 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ
+preplace netloc FMC1_PRSNTM2C_n_i_1 1 0 9 NJ 220 NJ 220 NJ 220 NJ 220 NJ 220 NJ 220 NJ 220 NJ 220 NJ
+preplace netloc dig_in1_i_1 1 0 9 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 NJ
+preplace netloc xlconcat_0_dout 1 6 1 1990
 preplace netloc fasec_hwtest_0_FMC1_CLK0C2M_P_o 1 9 1 NJ
-preplace netloc pb_gp_i_1 1 0 9 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 2780
+preplace netloc pb_gp_i_1 1 0 9 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 2810
 preplace netloc wrc_1p_kintex7_0_dac_sclk_o 1 9 1 NJ
 preplace netloc fasec_hwtest_0_led_line_pl_o 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph_M06_AXI 1 2 3 700 760 NJ 760 NJ
-preplace netloc axi_wb_i2c_master_2_axi_int_o 1 5 5 1670 550 NJ 550 NJ 550 NJ 650 3170
+preplace netloc processing_system7_0_axi_periph_M06_AXI 1 2 3 760 590 NJ 590 NJ
+preplace netloc axi_wb_i2c_master_2_axi_int_o 1 5 5 1690 560 NJ 560 NJ 560 NJ 650 3160
 preplace netloc processing_system7_0_DDR 1 7 3 NJ 720 NJ 720 NJ
-preplace netloc FMC1_CLK0M2C_N_i_1 1 0 9 NJ 260 NJ 260 NJ 260 NJ 260 NJ 260 NJ 260 NJ 260 NJ 260 NJ
+preplace netloc FMC1_CLK0M2C_N_i_1 1 0 9 NJ 250 NJ 250 NJ 250 NJ 250 NJ 250 NJ 250 NJ 250 NJ 250 NJ
 preplace netloc wrc_1p_kintex7_0_dac_cs2_n_o 1 9 1 NJ
-preplace netloc axi_interconnect_1_M00_AXI 1 8 1 2790
+preplace netloc axi_interconnect_1_M00_AXI 1 8 1 2780
 preplace netloc FMC2_CLK0M2C_N_i_1 1 0 9 NJ 210 NJ 210 NJ 210 NJ 210 NJ 210 NJ 210 NJ 210 NJ 210 NJ
 preplace netloc processing_system7_0_axi_periph_M05_AXI 1 2 2 720 600 NJ
 preplace netloc fasec_hwtest_0_dig_out6_n 1 9 1 NJ
-preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 8 60 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 1980 1130 2380
+preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 8 60 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 2000 1130 2400
 preplace netloc FMC2_PRSNTM2C_n_i_1 1 0 9 NJ 150 NJ 150 NJ 150 NJ 150 NJ 150 NJ 150 NJ 150 NJ 150 NJ
-preplace netloc rst_wrc_1p_kintex7_0_62M_interconnect_aresetn 1 7 1 2400
-preplace netloc xadc_wiz_0_M_AXIS 1 3 1 1050
-preplace netloc clk_aux_n_i_1 1 0 9 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ
+preplace netloc rst_wrc_1p_kintex7_0_62M_interconnect_aresetn 1 7 1 2420
+preplace netloc xadc_wiz_0_M_AXIS 1 3 1 1060
 preplace netloc processing_system7_0_axi_periph_M02_AXI 1 2 7 710 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ
 preplace netloc xadc_axis_fifo_adapter_0_M_AXIS 1 4 1 1280
-preplace netloc processing_system7_0_axi_periph_M07_AXI 1 2 1 740
+preplace netloc processing_system7_0_axi_periph_M07_AXI 1 2 1 730
 preplace netloc fasec_hwtest_0_FMC2_CLK0C2M_N_o 1 9 1 NJ
-preplace netloc rst_wrc_1p_kintex7_0_62M_peripheral_aresetn 1 7 2 2410 1130 NJ
+preplace netloc rst_wrc_1p_kintex7_0_62M_peripheral_aresetn 1 7 2 2430 1130 NJ
 preplace netloc clk_25m_vcxo_i_1 1 0 9 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ
-preplace netloc axi_dma_0_M_AXI_S2MM 1 5 1 1630
+preplace netloc axi_dma_0_M_AXI_S2MM 1 5 1 1650
 preplace netloc fasec_hwtest_0_FMC2_CLK0C2M_P_o 1 9 1 NJ
 preplace netloc Vaux2_1 1 0 3 NJ 950 NJ 950 NJ
 preplace netloc Vp_Vn_1 1 0 3 NJ 890 NJ 890 NJ
@@ -1755,21 +1748,21 @@ preplace netloc fasec_hwtest_0_FMC1_CLK0C2M_N_o 1 9 1 NJ
 preplace netloc fasec_hwtest_0_watchdog_pl_o 1 9 1 NJ
 preplace netloc processing_system7_0_axi_periph_M01_AXI 1 2 1 720
 preplace netloc fasec_hwtest_0_dig_out5_n 1 9 1 NJ
-preplace netloc FMC1_CLK0M2C_P_i_1 1 0 9 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ
+preplace netloc FMC1_CLK0M2C_P_i_1 1 0 9 NJ 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ
 preplace netloc Vaux0_1 1 0 3 NJ 910 NJ 910 NJ
 preplace netloc Net 1 9 1 NJ
 preplace netloc Net10 1 9 1 NJ
-preplace netloc wrc_1p_kintex7_0_uart_txd_o 1 3 7 N 670 NJ 670 NJ 760 NJ 670 NJ 670 NJ 670 3160
+preplace netloc wrc_1p_kintex7_0_uart_txd_o 1 3 7 N 670 NJ 670 NJ 760 NJ 670 NJ 670 NJ 670 3170
 preplace netloc Net1 1 9 1 NJ
-preplace netloc processing_system7_0_FCLK_CLK0 1 0 9 60 450 380 360 730 820 1020 980 1290 900 1620 1000 1990 950 2390 580 2740
+preplace netloc processing_system7_0_FCLK_CLK0 1 0 9 60 450 400 370 770 810 1040 980 1290 900 1630 1000 2010 950 2410 580 2760
 preplace netloc Net11 1 9 1 NJ
 preplace netloc processing_system7_0_FCLK_CLK1 1 7 2 NJ 880 2760
 preplace netloc Net2 1 9 1 NJ
 preplace netloc Net3 1 9 1 NJ
-preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 1 400
-preplace netloc processing_system7_0_axi_periph_M00_AXI 1 2 7 N 560 NJ 560 NJ 560 NJ 560 NJ 560 NJ 560 NJ
+preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 1 390
+preplace netloc processing_system7_0_axi_periph_M00_AXI 1 2 7 N 560 NJ 560 NJ 560 NJ 570 NJ 570 NJ 570 NJ
 preplace netloc fasec_hwtest_0_led_line_en_pl_o 1 9 1 NJ
-preplace netloc wrc_1p_kintex7_0_s00_axi_aclk_o 1 6 4 2000 1140 2390 1120 NJ 1040 3150
+preplace netloc wrc_1p_kintex7_0_s00_axi_aclk_o 1 6 4 2020 1140 2410 1120 NJ 1010 3160
 preplace netloc Net4 1 9 1 NJ
 preplace netloc Vaux8_1 1 0 3 NJ 970 NJ 970 NJ
 preplace netloc Net5 1 9 1 NJ
@@ -1777,24 +1770,23 @@ preplace netloc xadc_wiz_0_ip2intc_irpt 1 3 3 NJ 640 NJ 640 N
 preplace netloc Net6 1 9 1 NJ
 preplace netloc xlconstant_6_dout 1 8 1 NJ
 preplace netloc Net7 1 9 1 NJ
-preplace netloc dig_in2_i_1 1 0 9 NJ 220 NJ 220 NJ 220 NJ 220 NJ 220 NJ 220 NJ 220 NJ 220 NJ
-preplace netloc clk_aux_p_i_1 1 0 9 NJ 1240 NJ 1240 NJ 1240 NJ 1240 NJ 1240 NJ 1240 NJ 1240 NJ 1240 NJ
-preplace netloc axi_uartlite_0_interrupt 1 3 3 1030 700 NJ 700 NJ
+preplace netloc dig_in2_i_1 1 0 9 NJ 260 NJ 260 NJ 260 NJ 260 NJ 260 NJ 260 NJ 260 NJ 260 NJ
+preplace netloc axi_uartlite_0_interrupt 1 3 3 1040 690 NJ 690 NJ
 preplace netloc Vaux10_1 1 0 3 NJ 1010 NJ 1010 NJ
-preplace netloc processing_system7_0_M_AXI_GP0 1 1 7 400 180 NJ 180 NJ 180 NJ 180 NJ 180 NJ 180 2380
+preplace netloc processing_system7_0_M_AXI_GP0 1 1 7 410 180 NJ 180 NJ 180 NJ 180 NJ 180 NJ 180 2400
 preplace netloc Vaux1_1 1 0 3 NJ 930 NJ 930 NJ
 preplace netloc Vaux9_1 1 0 3 NJ 990 NJ 990 NJ
-preplace netloc axi_dma_0_s2mm_introut 1 5 1 1620
-preplace netloc processing_system7_0_axi_periph_M04_AXI 1 2 1 710
-preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 1 8 390 370 750 800 1030 990 1300 890 1650 570 NJ 570 NJ 570 2790
+preplace netloc axi_dma_0_s2mm_introut 1 5 1 1640
+preplace netloc processing_system7_0_axi_periph_M04_AXI 1 2 1 750
+preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 1 8 380 350 740 820 1030 990 1300 890 1660 540 NJ 540 NJ 540 2820
 preplace netloc FMC2_CLK0M2C_P_i_1 1 0 9 NJ 170 NJ 170 NJ 170 NJ 170 NJ 170 NJ 170 NJ 170 NJ 170 NJ
 preplace netloc wrc_1p_kintex7_0_dac_cs1_n_o 1 9 1 NJ
 preplace netloc wrc_1p_kintex7_0_gtp_wr 1 9 1 NJ
-preplace netloc S00_AXI_1 1 7 1 2410
-preplace netloc axi_interconnect_0_M00_AXI 1 6 1 1980
+preplace netloc S00_AXI_1 1 7 1 2430
+preplace netloc axi_interconnect_0_M00_AXI 1 6 1 2000
 preplace netloc xlconstant_7_dout 1 8 1 NJ
 preplace netloc axi_wb_i2c_master_0_axi_int_o 1 3 3 N 350 NJ 350 NJ
-levelinfo -pg 1 -30 220 550 890 1170 1460 1820 2190 2560 2980 3190 -top 0 -bot 1550
+levelinfo -pg 1 -40 220 560 900 1170 1460 1840 2210 2580 2990 3260 -top 0 -bot 1570
 ",
 }
 
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/sim/system_design_auto_pc_0.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/sim/system_design_auto_pc_0.v
deleted file mode 100644
index 097365a97137a163334a46e1a605d0cfa8004107..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/sim/system_design_auto_pc_0.v
+++ /dev/null
@@ -1,288 +0,0 @@
-// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
-// 
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-// 
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-// 
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-// 
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-// 
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
-// IP Revision: 9
-
-`timescale 1ns/1ps
-
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module system_design_auto_pc_0 (
-  aclk,
-  aresetn,
-  s_axi_awaddr,
-  s_axi_awlen,
-  s_axi_awsize,
-  s_axi_awburst,
-  s_axi_awlock,
-  s_axi_awcache,
-  s_axi_awprot,
-  s_axi_awregion,
-  s_axi_awqos,
-  s_axi_awvalid,
-  s_axi_awready,
-  s_axi_wdata,
-  s_axi_wstrb,
-  s_axi_wlast,
-  s_axi_wvalid,
-  s_axi_wready,
-  s_axi_bresp,
-  s_axi_bvalid,
-  s_axi_bready,
-  m_axi_awaddr,
-  m_axi_awlen,
-  m_axi_awsize,
-  m_axi_awburst,
-  m_axi_awlock,
-  m_axi_awcache,
-  m_axi_awprot,
-  m_axi_awqos,
-  m_axi_awvalid,
-  m_axi_awready,
-  m_axi_wdata,
-  m_axi_wstrb,
-  m_axi_wlast,
-  m_axi_wvalid,
-  m_axi_wready,
-  m_axi_bresp,
-  m_axi_bvalid,
-  m_axi_bready
-);
-
-(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
-input wire aclk;
-(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
-input wire aresetn;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
-input wire [31 : 0] s_axi_awaddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
-input wire [7 : 0] s_axi_awlen;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
-input wire [2 : 0] s_axi_awsize;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
-input wire [1 : 0] s_axi_awburst;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
-input wire [0 : 0] s_axi_awlock;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
-input wire [3 : 0] s_axi_awcache;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
-input wire [2 : 0] s_axi_awprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
-input wire [3 : 0] s_axi_awregion;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
-input wire [3 : 0] s_axi_awqos;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
-input wire s_axi_awvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
-output wire s_axi_awready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
-input wire [31 : 0] s_axi_wdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
-input wire [3 : 0] s_axi_wstrb;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
-input wire s_axi_wlast;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
-input wire s_axi_wvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
-output wire s_axi_wready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
-output wire [1 : 0] s_axi_bresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
-output wire s_axi_bvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
-input wire s_axi_bready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
-output wire [31 : 0] m_axi_awaddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
-output wire [3 : 0] m_axi_awlen;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
-output wire [2 : 0] m_axi_awsize;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
-output wire [1 : 0] m_axi_awburst;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
-output wire [1 : 0] m_axi_awlock;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
-output wire [3 : 0] m_axi_awcache;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
-output wire [2 : 0] m_axi_awprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
-output wire [3 : 0] m_axi_awqos;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
-output wire m_axi_awvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
-input wire m_axi_awready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
-output wire [31 : 0] m_axi_wdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
-output wire [3 : 0] m_axi_wstrb;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
-output wire m_axi_wlast;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
-output wire m_axi_wvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
-input wire m_axi_wready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
-input wire [1 : 0] m_axi_bresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
-input wire m_axi_bvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
-output wire m_axi_bready;
-
-  axi_protocol_converter_v2_1_9_axi_protocol_converter #(
-    .C_FAMILY("zynq"),
-    .C_M_AXI_PROTOCOL(1),
-    .C_S_AXI_PROTOCOL(0),
-    .C_IGNORE_ID(1),
-    .C_AXI_ID_WIDTH(1),
-    .C_AXI_ADDR_WIDTH(32),
-    .C_AXI_DATA_WIDTH(32),
-    .C_AXI_SUPPORTS_WRITE(1),
-    .C_AXI_SUPPORTS_READ(0),
-    .C_AXI_SUPPORTS_USER_SIGNALS(0),
-    .C_AXI_AWUSER_WIDTH(1),
-    .C_AXI_ARUSER_WIDTH(1),
-    .C_AXI_WUSER_WIDTH(1),
-    .C_AXI_RUSER_WIDTH(1),
-    .C_AXI_BUSER_WIDTH(1),
-    .C_TRANSLATION_MODE(2)
-  ) inst (
-    .aclk(aclk),
-    .aresetn(aresetn),
-    .s_axi_awid(1'H0),
-    .s_axi_awaddr(s_axi_awaddr),
-    .s_axi_awlen(s_axi_awlen),
-    .s_axi_awsize(s_axi_awsize),
-    .s_axi_awburst(s_axi_awburst),
-    .s_axi_awlock(s_axi_awlock),
-    .s_axi_awcache(s_axi_awcache),
-    .s_axi_awprot(s_axi_awprot),
-    .s_axi_awregion(s_axi_awregion),
-    .s_axi_awqos(s_axi_awqos),
-    .s_axi_awuser(1'H0),
-    .s_axi_awvalid(s_axi_awvalid),
-    .s_axi_awready(s_axi_awready),
-    .s_axi_wid(1'H0),
-    .s_axi_wdata(s_axi_wdata),
-    .s_axi_wstrb(s_axi_wstrb),
-    .s_axi_wlast(s_axi_wlast),
-    .s_axi_wuser(1'H0),
-    .s_axi_wvalid(s_axi_wvalid),
-    .s_axi_wready(s_axi_wready),
-    .s_axi_bid(),
-    .s_axi_bresp(s_axi_bresp),
-    .s_axi_buser(),
-    .s_axi_bvalid(s_axi_bvalid),
-    .s_axi_bready(s_axi_bready),
-    .s_axi_arid(1'H0),
-    .s_axi_araddr(32'H00000000),
-    .s_axi_arlen(8'H00),
-    .s_axi_arsize(3'H0),
-    .s_axi_arburst(2'H1),
-    .s_axi_arlock(1'H0),
-    .s_axi_arcache(4'H0),
-    .s_axi_arprot(3'H0),
-    .s_axi_arregion(4'H0),
-    .s_axi_arqos(4'H0),
-    .s_axi_aruser(1'H0),
-    .s_axi_arvalid(1'H0),
-    .s_axi_arready(),
-    .s_axi_rid(),
-    .s_axi_rdata(),
-    .s_axi_rresp(),
-    .s_axi_rlast(),
-    .s_axi_ruser(),
-    .s_axi_rvalid(),
-    .s_axi_rready(1'H0),
-    .m_axi_awid(),
-    .m_axi_awaddr(m_axi_awaddr),
-    .m_axi_awlen(m_axi_awlen),
-    .m_axi_awsize(m_axi_awsize),
-    .m_axi_awburst(m_axi_awburst),
-    .m_axi_awlock(m_axi_awlock),
-    .m_axi_awcache(m_axi_awcache),
-    .m_axi_awprot(m_axi_awprot),
-    .m_axi_awregion(),
-    .m_axi_awqos(m_axi_awqos),
-    .m_axi_awuser(),
-    .m_axi_awvalid(m_axi_awvalid),
-    .m_axi_awready(m_axi_awready),
-    .m_axi_wid(),
-    .m_axi_wdata(m_axi_wdata),
-    .m_axi_wstrb(m_axi_wstrb),
-    .m_axi_wlast(m_axi_wlast),
-    .m_axi_wuser(),
-    .m_axi_wvalid(m_axi_wvalid),
-    .m_axi_wready(m_axi_wready),
-    .m_axi_bid(1'H0),
-    .m_axi_bresp(m_axi_bresp),
-    .m_axi_buser(1'H0),
-    .m_axi_bvalid(m_axi_bvalid),
-    .m_axi_bready(m_axi_bready),
-    .m_axi_arid(),
-    .m_axi_araddr(),
-    .m_axi_arlen(),
-    .m_axi_arsize(),
-    .m_axi_arburst(),
-    .m_axi_arlock(),
-    .m_axi_arcache(),
-    .m_axi_arprot(),
-    .m_axi_arregion(),
-    .m_axi_arqos(),
-    .m_axi_aruser(),
-    .m_axi_arvalid(),
-    .m_axi_arready(1'H0),
-    .m_axi_rid(1'H0),
-    .m_axi_rdata(32'H00000000),
-    .m_axi_rresp(2'H0),
-    .m_axi_rlast(1'H1),
-    .m_axi_ruser(1'H0),
-    .m_axi_rvalid(1'H0),
-    .m_axi_rready()
-  );
-endmodule
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/synth/system_design_auto_pc_0.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/synth/system_design_auto_pc_0.v
deleted file mode 100644
index 7b78b0aab94d7f6be5637d87ee33090a3a9e03d2..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/synth/system_design_auto_pc_0.v
+++ /dev/null
@@ -1,290 +0,0 @@
-// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
-// 
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-// 
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-// 
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-// 
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-// 
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
-// IP Revision: 9
-
-(* X_CORE_INFO = "axi_protocol_converter_v2_1_9_axi_protocol_converter,Vivado 2016.2" *)
-(* CHECK_LICENSE_TYPE = "system_design_auto_pc_0,axi_protocol_converter_v2_1_9_axi_protocol_converter,{}" *)
-(* CORE_GENERATION_INFO = "system_design_auto_pc_0,axi_protocol_converter_v2_1_9_axi_protocol_converter,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=1,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=0,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_\
-WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module system_design_auto_pc_0 (
-  aclk,
-  aresetn,
-  s_axi_awaddr,
-  s_axi_awlen,
-  s_axi_awsize,
-  s_axi_awburst,
-  s_axi_awlock,
-  s_axi_awcache,
-  s_axi_awprot,
-  s_axi_awregion,
-  s_axi_awqos,
-  s_axi_awvalid,
-  s_axi_awready,
-  s_axi_wdata,
-  s_axi_wstrb,
-  s_axi_wlast,
-  s_axi_wvalid,
-  s_axi_wready,
-  s_axi_bresp,
-  s_axi_bvalid,
-  s_axi_bready,
-  m_axi_awaddr,
-  m_axi_awlen,
-  m_axi_awsize,
-  m_axi_awburst,
-  m_axi_awlock,
-  m_axi_awcache,
-  m_axi_awprot,
-  m_axi_awqos,
-  m_axi_awvalid,
-  m_axi_awready,
-  m_axi_wdata,
-  m_axi_wstrb,
-  m_axi_wlast,
-  m_axi_wvalid,
-  m_axi_wready,
-  m_axi_bresp,
-  m_axi_bvalid,
-  m_axi_bready
-);
-
-(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
-input wire aclk;
-(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
-input wire aresetn;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
-input wire [31 : 0] s_axi_awaddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
-input wire [7 : 0] s_axi_awlen;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
-input wire [2 : 0] s_axi_awsize;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
-input wire [1 : 0] s_axi_awburst;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
-input wire [0 : 0] s_axi_awlock;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
-input wire [3 : 0] s_axi_awcache;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
-input wire [2 : 0] s_axi_awprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
-input wire [3 : 0] s_axi_awregion;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
-input wire [3 : 0] s_axi_awqos;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
-input wire s_axi_awvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
-output wire s_axi_awready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
-input wire [31 : 0] s_axi_wdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
-input wire [3 : 0] s_axi_wstrb;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
-input wire s_axi_wlast;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
-input wire s_axi_wvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
-output wire s_axi_wready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
-output wire [1 : 0] s_axi_bresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
-output wire s_axi_bvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
-input wire s_axi_bready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
-output wire [31 : 0] m_axi_awaddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
-output wire [3 : 0] m_axi_awlen;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
-output wire [2 : 0] m_axi_awsize;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
-output wire [1 : 0] m_axi_awburst;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
-output wire [1 : 0] m_axi_awlock;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
-output wire [3 : 0] m_axi_awcache;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
-output wire [2 : 0] m_axi_awprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
-output wire [3 : 0] m_axi_awqos;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
-output wire m_axi_awvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
-input wire m_axi_awready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
-output wire [31 : 0] m_axi_wdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
-output wire [3 : 0] m_axi_wstrb;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
-output wire m_axi_wlast;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
-output wire m_axi_wvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
-input wire m_axi_wready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
-input wire [1 : 0] m_axi_bresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
-input wire m_axi_bvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
-output wire m_axi_bready;
-
-  axi_protocol_converter_v2_1_9_axi_protocol_converter #(
-    .C_FAMILY("zynq"),
-    .C_M_AXI_PROTOCOL(1),
-    .C_S_AXI_PROTOCOL(0),
-    .C_IGNORE_ID(1),
-    .C_AXI_ID_WIDTH(1),
-    .C_AXI_ADDR_WIDTH(32),
-    .C_AXI_DATA_WIDTH(32),
-    .C_AXI_SUPPORTS_WRITE(1),
-    .C_AXI_SUPPORTS_READ(0),
-    .C_AXI_SUPPORTS_USER_SIGNALS(0),
-    .C_AXI_AWUSER_WIDTH(1),
-    .C_AXI_ARUSER_WIDTH(1),
-    .C_AXI_WUSER_WIDTH(1),
-    .C_AXI_RUSER_WIDTH(1),
-    .C_AXI_BUSER_WIDTH(1),
-    .C_TRANSLATION_MODE(2)
-  ) inst (
-    .aclk(aclk),
-    .aresetn(aresetn),
-    .s_axi_awid(1'H0),
-    .s_axi_awaddr(s_axi_awaddr),
-    .s_axi_awlen(s_axi_awlen),
-    .s_axi_awsize(s_axi_awsize),
-    .s_axi_awburst(s_axi_awburst),
-    .s_axi_awlock(s_axi_awlock),
-    .s_axi_awcache(s_axi_awcache),
-    .s_axi_awprot(s_axi_awprot),
-    .s_axi_awregion(s_axi_awregion),
-    .s_axi_awqos(s_axi_awqos),
-    .s_axi_awuser(1'H0),
-    .s_axi_awvalid(s_axi_awvalid),
-    .s_axi_awready(s_axi_awready),
-    .s_axi_wid(1'H0),
-    .s_axi_wdata(s_axi_wdata),
-    .s_axi_wstrb(s_axi_wstrb),
-    .s_axi_wlast(s_axi_wlast),
-    .s_axi_wuser(1'H0),
-    .s_axi_wvalid(s_axi_wvalid),
-    .s_axi_wready(s_axi_wready),
-    .s_axi_bid(),
-    .s_axi_bresp(s_axi_bresp),
-    .s_axi_buser(),
-    .s_axi_bvalid(s_axi_bvalid),
-    .s_axi_bready(s_axi_bready),
-    .s_axi_arid(1'H0),
-    .s_axi_araddr(32'H00000000),
-    .s_axi_arlen(8'H00),
-    .s_axi_arsize(3'H0),
-    .s_axi_arburst(2'H1),
-    .s_axi_arlock(1'H0),
-    .s_axi_arcache(4'H0),
-    .s_axi_arprot(3'H0),
-    .s_axi_arregion(4'H0),
-    .s_axi_arqos(4'H0),
-    .s_axi_aruser(1'H0),
-    .s_axi_arvalid(1'H0),
-    .s_axi_arready(),
-    .s_axi_rid(),
-    .s_axi_rdata(),
-    .s_axi_rresp(),
-    .s_axi_rlast(),
-    .s_axi_ruser(),
-    .s_axi_rvalid(),
-    .s_axi_rready(1'H0),
-    .m_axi_awid(),
-    .m_axi_awaddr(m_axi_awaddr),
-    .m_axi_awlen(m_axi_awlen),
-    .m_axi_awsize(m_axi_awsize),
-    .m_axi_awburst(m_axi_awburst),
-    .m_axi_awlock(m_axi_awlock),
-    .m_axi_awcache(m_axi_awcache),
-    .m_axi_awprot(m_axi_awprot),
-    .m_axi_awregion(),
-    .m_axi_awqos(m_axi_awqos),
-    .m_axi_awuser(),
-    .m_axi_awvalid(m_axi_awvalid),
-    .m_axi_awready(m_axi_awready),
-    .m_axi_wid(),
-    .m_axi_wdata(m_axi_wdata),
-    .m_axi_wstrb(m_axi_wstrb),
-    .m_axi_wlast(m_axi_wlast),
-    .m_axi_wuser(),
-    .m_axi_wvalid(m_axi_wvalid),
-    .m_axi_wready(m_axi_wready),
-    .m_axi_bid(1'H0),
-    .m_axi_bresp(m_axi_bresp),
-    .m_axi_buser(1'H0),
-    .m_axi_bvalid(m_axi_bvalid),
-    .m_axi_bready(m_axi_bready),
-    .m_axi_arid(),
-    .m_axi_araddr(),
-    .m_axi_arlen(),
-    .m_axi_arsize(),
-    .m_axi_arburst(),
-    .m_axi_arlock(),
-    .m_axi_arcache(),
-    .m_axi_arprot(),
-    .m_axi_arregion(),
-    .m_axi_arqos(),
-    .m_axi_aruser(),
-    .m_axi_arvalid(),
-    .m_axi_arready(1'H0),
-    .m_axi_rid(1'H0),
-    .m_axi_rdata(32'H00000000),
-    .m_axi_rresp(2'H0),
-    .m_axi_rlast(1'H1),
-    .m_axi_ruser(1'H0),
-    .m_axi_rvalid(1'H0),
-    .m_axi_rready()
-  );
-endmodule
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
index 7a88302e6ee7fd182c92675dfd72b103f0713d5f..2890639e65ab2a38b26e1512b82dd413285c8bc1 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
@@ -1025,195 +1025,6 @@
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   </spirit:busInterfaces>
   <spirit:model>
-    <spirit:views>
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-        <spirit:language>verilog</spirit:language>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:fileSetRef>
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-        </spirit:fileSetRef>
-        <spirit:fileSetRef>
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-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset</spirit:localName>
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-      <spirit:view>
-        <spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
-        <spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
-        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
-        <spirit:language>verilog</spirit:language>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
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-            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
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-          <spirit:parameter>
-            <spirit:name>boundaryCRC</spirit:name>
-            <spirit:value>f63b8bf0</spirit:value>
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-            <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>0d9f9518</spirit:value>
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-          <spirit:parameter>
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-            <spirit:value>6</spirit:value>
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@@ -1222,8 +1033,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1235,8 +1045,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1252,8 +1061,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1279,8 +1087,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1306,8 +1113,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1333,8 +1139,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1360,8 +1165,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1387,8 +1191,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1414,8 +1217,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1441,8 +1243,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1468,8 +1269,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1495,8 +1295,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1522,8 +1321,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1545,8 +1343,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1568,8 +1365,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1592,8 +1388,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1619,8 +1414,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1646,8 +1440,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1669,8 +1462,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1696,8 +1488,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1719,8 +1510,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1742,8 +1532,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1766,8 +1555,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1790,8 +1578,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1814,8 +1601,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1834,8 +1620,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1854,8 +1639,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1881,8 +1665,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1908,8 +1691,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1935,8 +1717,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -1962,8 +1743,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
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@@ -1989,8 +1769,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2016,8 +1795,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2043,8 +1821,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2070,8 +1847,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2097,8 +1873,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2124,8 +1899,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2151,8 +1925,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2174,8 +1947,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2197,8 +1969,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2221,8 +1992,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2245,8 +2015,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2269,8 +2038,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2289,8 +2057,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2313,8 +2080,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2333,8 +2099,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2353,8 +2118,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2380,8 +2144,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2404,8 +2167,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2428,8 +2190,7 @@
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-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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@@ -2452,8 +2213,7 @@
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2476,8 +2236,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2500,8 +2259,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2524,8 +2282,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2548,8 +2305,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2572,8 +2328,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2596,8 +2351,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2620,8 +2374,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2640,8 +2393,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2660,8 +2412,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2687,8 +2438,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2711,8 +2461,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2735,8 +2484,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2755,8 +2503,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2779,8 +2526,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2799,8 +2545,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2819,8 +2564,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2846,8 +2590,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2873,8 +2616,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2900,8 +2642,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2923,8 +2664,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2946,8 +2686,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2970,8 +2709,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2994,8 +2732,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3018,8 +2755,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3042,8 +2778,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3066,8 +2801,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3090,8 +2824,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3114,8 +2847,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3138,8 +2870,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3162,8 +2893,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3186,8 +2916,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3210,8 +2939,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3230,8 +2958,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3250,8 +2977,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3277,8 +3003,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3304,8 +3029,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3331,8 +3055,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3354,8 +3077,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3381,8 +3103,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3404,8 +3125,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3427,8 +3147,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3541,726 +3260,6 @@
       <spirit:enumeration spirit:text="Unprotected: Master must be well-behaved">0</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
-  <spirit:fileSets>
-    <spirit:fileSet>
-      <spirit:name>xilinx_verilogsynthesis_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset</spirit:name>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_and.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_latch_and.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_latch_or.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_or.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
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-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_command_fifo.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
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-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_comparator_mask_static.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
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-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_comparator_mask.v</spirit:name>
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-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
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-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_comparator_sel_mask_static.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
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-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_comparator_sel_mask.v</spirit:name>
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-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
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diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_ooc.xdc b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_ooc.xdc
deleted file mode 100644
index c81fa5589d5f7ec1e396a1e8f8063289fc0d4efd..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_ooc.xdc
+++ /dev/null
@@ -1,57 +0,0 @@
-# (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-# 
-# DO NOT MODIFY THIS FILE.
-# #########################################################
-#
-# This XDC is used only in OOC mode for synthesis, implementation
-#
-# #########################################################
-
-
-create_clock -period 10 -name aclk [get_ports aclk]
-
-
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v
deleted file mode 100644
index 899d551a0738d80f02315409d022e1bcef538e33..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v
+++ /dev/null
@@ -1,348 +0,0 @@
-// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
-// 
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-// 
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-// 
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-// 
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-// 
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
-// IP Revision: 9
-
-`timescale 1ns/1ps
-
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module system_design_auto_pc_1 (
-  aclk,
-  aresetn,
-  s_axi_awid,
-  s_axi_awaddr,
-  s_axi_awlen,
-  s_axi_awsize,
-  s_axi_awburst,
-  s_axi_awlock,
-  s_axi_awcache,
-  s_axi_awprot,
-  s_axi_awqos,
-  s_axi_awvalid,
-  s_axi_awready,
-  s_axi_wid,
-  s_axi_wdata,
-  s_axi_wstrb,
-  s_axi_wlast,
-  s_axi_wvalid,
-  s_axi_wready,
-  s_axi_bid,
-  s_axi_bresp,
-  s_axi_bvalid,
-  s_axi_bready,
-  s_axi_arid,
-  s_axi_araddr,
-  s_axi_arlen,
-  s_axi_arsize,
-  s_axi_arburst,
-  s_axi_arlock,
-  s_axi_arcache,
-  s_axi_arprot,
-  s_axi_arqos,
-  s_axi_arvalid,
-  s_axi_arready,
-  s_axi_rid,
-  s_axi_rdata,
-  s_axi_rresp,
-  s_axi_rlast,
-  s_axi_rvalid,
-  s_axi_rready,
-  m_axi_awaddr,
-  m_axi_awprot,
-  m_axi_awvalid,
-  m_axi_awready,
-  m_axi_wdata,
-  m_axi_wstrb,
-  m_axi_wvalid,
-  m_axi_wready,
-  m_axi_bresp,
-  m_axi_bvalid,
-  m_axi_bready,
-  m_axi_araddr,
-  m_axi_arprot,
-  m_axi_arvalid,
-  m_axi_arready,
-  m_axi_rdata,
-  m_axi_rresp,
-  m_axi_rvalid,
-  m_axi_rready
-);
-
-(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
-input wire aclk;
-(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
-input wire aresetn;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
-input wire [11 : 0] s_axi_awid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
-input wire [31 : 0] s_axi_awaddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
-input wire [3 : 0] s_axi_awlen;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
-input wire [2 : 0] s_axi_awsize;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
-input wire [1 : 0] s_axi_awburst;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
-input wire [1 : 0] s_axi_awlock;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
-input wire [3 : 0] s_axi_awcache;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
-input wire [2 : 0] s_axi_awprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
-input wire [3 : 0] s_axi_awqos;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
-input wire s_axi_awvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
-output wire s_axi_awready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
-input wire [11 : 0] s_axi_wid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
-input wire [31 : 0] s_axi_wdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
-input wire [3 : 0] s_axi_wstrb;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
-input wire s_axi_wlast;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
-input wire s_axi_wvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
-output wire s_axi_wready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
-output wire [11 : 0] s_axi_bid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
-output wire [1 : 0] s_axi_bresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
-output wire s_axi_bvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
-input wire s_axi_bready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
-input wire [11 : 0] s_axi_arid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
-input wire [31 : 0] s_axi_araddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
-input wire [3 : 0] s_axi_arlen;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
-input wire [2 : 0] s_axi_arsize;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
-input wire [1 : 0] s_axi_arburst;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
-input wire [1 : 0] s_axi_arlock;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
-input wire [3 : 0] s_axi_arcache;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
-input wire [2 : 0] s_axi_arprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
-input wire [3 : 0] s_axi_arqos;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
-input wire s_axi_arvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
-output wire s_axi_arready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
-output wire [11 : 0] s_axi_rid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
-output wire [31 : 0] s_axi_rdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
-output wire [1 : 0] s_axi_rresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
-output wire s_axi_rlast;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
-output wire s_axi_rvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
-input wire s_axi_rready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
-output wire [31 : 0] m_axi_awaddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
-output wire [2 : 0] m_axi_awprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
-output wire m_axi_awvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
-input wire m_axi_awready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
-output wire [31 : 0] m_axi_wdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
-output wire [3 : 0] m_axi_wstrb;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
-output wire m_axi_wvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
-input wire m_axi_wready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
-input wire [1 : 0] m_axi_bresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
-input wire m_axi_bvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
-output wire m_axi_bready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
-output wire [31 : 0] m_axi_araddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
-output wire [2 : 0] m_axi_arprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
-output wire m_axi_arvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
-input wire m_axi_arready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
-input wire [31 : 0] m_axi_rdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
-input wire [1 : 0] m_axi_rresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
-input wire m_axi_rvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
-output wire m_axi_rready;
-
-  axi_protocol_converter_v2_1_9_axi_protocol_converter #(
-    .C_FAMILY("zynq"),
-    .C_M_AXI_PROTOCOL(2),
-    .C_S_AXI_PROTOCOL(1),
-    .C_IGNORE_ID(0),
-    .C_AXI_ID_WIDTH(12),
-    .C_AXI_ADDR_WIDTH(32),
-    .C_AXI_DATA_WIDTH(32),
-    .C_AXI_SUPPORTS_WRITE(1),
-    .C_AXI_SUPPORTS_READ(1),
-    .C_AXI_SUPPORTS_USER_SIGNALS(0),
-    .C_AXI_AWUSER_WIDTH(1),
-    .C_AXI_ARUSER_WIDTH(1),
-    .C_AXI_WUSER_WIDTH(1),
-    .C_AXI_RUSER_WIDTH(1),
-    .C_AXI_BUSER_WIDTH(1),
-    .C_TRANSLATION_MODE(2)
-  ) inst (
-    .aclk(aclk),
-    .aresetn(aresetn),
-    .s_axi_awid(s_axi_awid),
-    .s_axi_awaddr(s_axi_awaddr),
-    .s_axi_awlen(s_axi_awlen),
-    .s_axi_awsize(s_axi_awsize),
-    .s_axi_awburst(s_axi_awburst),
-    .s_axi_awlock(s_axi_awlock),
-    .s_axi_awcache(s_axi_awcache),
-    .s_axi_awprot(s_axi_awprot),
-    .s_axi_awregion(4'H0),
-    .s_axi_awqos(s_axi_awqos),
-    .s_axi_awuser(1'H0),
-    .s_axi_awvalid(s_axi_awvalid),
-    .s_axi_awready(s_axi_awready),
-    .s_axi_wid(s_axi_wid),
-    .s_axi_wdata(s_axi_wdata),
-    .s_axi_wstrb(s_axi_wstrb),
-    .s_axi_wlast(s_axi_wlast),
-    .s_axi_wuser(1'H0),
-    .s_axi_wvalid(s_axi_wvalid),
-    .s_axi_wready(s_axi_wready),
-    .s_axi_bid(s_axi_bid),
-    .s_axi_bresp(s_axi_bresp),
-    .s_axi_buser(),
-    .s_axi_bvalid(s_axi_bvalid),
-    .s_axi_bready(s_axi_bready),
-    .s_axi_arid(s_axi_arid),
-    .s_axi_araddr(s_axi_araddr),
-    .s_axi_arlen(s_axi_arlen),
-    .s_axi_arsize(s_axi_arsize),
-    .s_axi_arburst(s_axi_arburst),
-    .s_axi_arlock(s_axi_arlock),
-    .s_axi_arcache(s_axi_arcache),
-    .s_axi_arprot(s_axi_arprot),
-    .s_axi_arregion(4'H0),
-    .s_axi_arqos(s_axi_arqos),
-    .s_axi_aruser(1'H0),
-    .s_axi_arvalid(s_axi_arvalid),
-    .s_axi_arready(s_axi_arready),
-    .s_axi_rid(s_axi_rid),
-    .s_axi_rdata(s_axi_rdata),
-    .s_axi_rresp(s_axi_rresp),
-    .s_axi_rlast(s_axi_rlast),
-    .s_axi_ruser(),
-    .s_axi_rvalid(s_axi_rvalid),
-    .s_axi_rready(s_axi_rready),
-    .m_axi_awid(),
-    .m_axi_awaddr(m_axi_awaddr),
-    .m_axi_awlen(),
-    .m_axi_awsize(),
-    .m_axi_awburst(),
-    .m_axi_awlock(),
-    .m_axi_awcache(),
-    .m_axi_awprot(m_axi_awprot),
-    .m_axi_awregion(),
-    .m_axi_awqos(),
-    .m_axi_awuser(),
-    .m_axi_awvalid(m_axi_awvalid),
-    .m_axi_awready(m_axi_awready),
-    .m_axi_wid(),
-    .m_axi_wdata(m_axi_wdata),
-    .m_axi_wstrb(m_axi_wstrb),
-    .m_axi_wlast(),
-    .m_axi_wuser(),
-    .m_axi_wvalid(m_axi_wvalid),
-    .m_axi_wready(m_axi_wready),
-    .m_axi_bid(12'H000),
-    .m_axi_bresp(m_axi_bresp),
-    .m_axi_buser(1'H0),
-    .m_axi_bvalid(m_axi_bvalid),
-    .m_axi_bready(m_axi_bready),
-    .m_axi_arid(),
-    .m_axi_araddr(m_axi_araddr),
-    .m_axi_arlen(),
-    .m_axi_arsize(),
-    .m_axi_arburst(),
-    .m_axi_arlock(),
-    .m_axi_arcache(),
-    .m_axi_arprot(m_axi_arprot),
-    .m_axi_arregion(),
-    .m_axi_arqos(),
-    .m_axi_aruser(),
-    .m_axi_arvalid(m_axi_arvalid),
-    .m_axi_arready(m_axi_arready),
-    .m_axi_rid(12'H000),
-    .m_axi_rdata(m_axi_rdata),
-    .m_axi_rresp(m_axi_rresp),
-    .m_axi_rlast(1'H1),
-    .m_axi_ruser(1'H0),
-    .m_axi_rvalid(m_axi_rvalid),
-    .m_axi_rready(m_axi_rready)
-  );
-endmodule
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/synth/system_design_auto_pc_1.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/synth/system_design_auto_pc_1.v
deleted file mode 100644
index 8ad2257cc33db4f5c8b49654f81c46cd4049efe6..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/synth/system_design_auto_pc_1.v
+++ /dev/null
@@ -1,350 +0,0 @@
-// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
-// 
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-// 
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-// 
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-// 
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-// 
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
-// IP Revision: 9
-
-(* X_CORE_INFO = "axi_protocol_converter_v2_1_9_axi_protocol_converter,Vivado 2016.2" *)
-(* CHECK_LICENSE_TYPE = "system_design_auto_pc_1,axi_protocol_converter_v2_1_9_axi_protocol_converter,{}" *)
-(* CORE_GENERATION_INFO = "system_design_auto_pc_1,axi_protocol_converter_v2_1_9_axi_protocol_converter,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER\
-_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module system_design_auto_pc_1 (
-  aclk,
-  aresetn,
-  s_axi_awid,
-  s_axi_awaddr,
-  s_axi_awlen,
-  s_axi_awsize,
-  s_axi_awburst,
-  s_axi_awlock,
-  s_axi_awcache,
-  s_axi_awprot,
-  s_axi_awqos,
-  s_axi_awvalid,
-  s_axi_awready,
-  s_axi_wid,
-  s_axi_wdata,
-  s_axi_wstrb,
-  s_axi_wlast,
-  s_axi_wvalid,
-  s_axi_wready,
-  s_axi_bid,
-  s_axi_bresp,
-  s_axi_bvalid,
-  s_axi_bready,
-  s_axi_arid,
-  s_axi_araddr,
-  s_axi_arlen,
-  s_axi_arsize,
-  s_axi_arburst,
-  s_axi_arlock,
-  s_axi_arcache,
-  s_axi_arprot,
-  s_axi_arqos,
-  s_axi_arvalid,
-  s_axi_arready,
-  s_axi_rid,
-  s_axi_rdata,
-  s_axi_rresp,
-  s_axi_rlast,
-  s_axi_rvalid,
-  s_axi_rready,
-  m_axi_awaddr,
-  m_axi_awprot,
-  m_axi_awvalid,
-  m_axi_awready,
-  m_axi_wdata,
-  m_axi_wstrb,
-  m_axi_wvalid,
-  m_axi_wready,
-  m_axi_bresp,
-  m_axi_bvalid,
-  m_axi_bready,
-  m_axi_araddr,
-  m_axi_arprot,
-  m_axi_arvalid,
-  m_axi_arready,
-  m_axi_rdata,
-  m_axi_rresp,
-  m_axi_rvalid,
-  m_axi_rready
-);
-
-(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
-input wire aclk;
-(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
-input wire aresetn;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
-input wire [11 : 0] s_axi_awid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
-input wire [31 : 0] s_axi_awaddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
-input wire [3 : 0] s_axi_awlen;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
-input wire [2 : 0] s_axi_awsize;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
-input wire [1 : 0] s_axi_awburst;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
-input wire [1 : 0] s_axi_awlock;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
-input wire [3 : 0] s_axi_awcache;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
-input wire [2 : 0] s_axi_awprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
-input wire [3 : 0] s_axi_awqos;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
-input wire s_axi_awvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
-output wire s_axi_awready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
-input wire [11 : 0] s_axi_wid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
-input wire [31 : 0] s_axi_wdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
-input wire [3 : 0] s_axi_wstrb;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
-input wire s_axi_wlast;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
-input wire s_axi_wvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
-output wire s_axi_wready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
-output wire [11 : 0] s_axi_bid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
-output wire [1 : 0] s_axi_bresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
-output wire s_axi_bvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
-input wire s_axi_bready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
-input wire [11 : 0] s_axi_arid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
-input wire [31 : 0] s_axi_araddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
-input wire [3 : 0] s_axi_arlen;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
-input wire [2 : 0] s_axi_arsize;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
-input wire [1 : 0] s_axi_arburst;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
-input wire [1 : 0] s_axi_arlock;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
-input wire [3 : 0] s_axi_arcache;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
-input wire [2 : 0] s_axi_arprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
-input wire [3 : 0] s_axi_arqos;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
-input wire s_axi_arvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
-output wire s_axi_arready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
-output wire [11 : 0] s_axi_rid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
-output wire [31 : 0] s_axi_rdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
-output wire [1 : 0] s_axi_rresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
-output wire s_axi_rlast;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
-output wire s_axi_rvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
-input wire s_axi_rready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
-output wire [31 : 0] m_axi_awaddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
-output wire [2 : 0] m_axi_awprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
-output wire m_axi_awvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
-input wire m_axi_awready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
-output wire [31 : 0] m_axi_wdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
-output wire [3 : 0] m_axi_wstrb;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
-output wire m_axi_wvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
-input wire m_axi_wready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
-input wire [1 : 0] m_axi_bresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
-input wire m_axi_bvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
-output wire m_axi_bready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
-output wire [31 : 0] m_axi_araddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
-output wire [2 : 0] m_axi_arprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
-output wire m_axi_arvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
-input wire m_axi_arready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
-input wire [31 : 0] m_axi_rdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
-input wire [1 : 0] m_axi_rresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
-input wire m_axi_rvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
-output wire m_axi_rready;
-
-  axi_protocol_converter_v2_1_9_axi_protocol_converter #(
-    .C_FAMILY("zynq"),
-    .C_M_AXI_PROTOCOL(2),
-    .C_S_AXI_PROTOCOL(1),
-    .C_IGNORE_ID(0),
-    .C_AXI_ID_WIDTH(12),
-    .C_AXI_ADDR_WIDTH(32),
-    .C_AXI_DATA_WIDTH(32),
-    .C_AXI_SUPPORTS_WRITE(1),
-    .C_AXI_SUPPORTS_READ(1),
-    .C_AXI_SUPPORTS_USER_SIGNALS(0),
-    .C_AXI_AWUSER_WIDTH(1),
-    .C_AXI_ARUSER_WIDTH(1),
-    .C_AXI_WUSER_WIDTH(1),
-    .C_AXI_RUSER_WIDTH(1),
-    .C_AXI_BUSER_WIDTH(1),
-    .C_TRANSLATION_MODE(2)
-  ) inst (
-    .aclk(aclk),
-    .aresetn(aresetn),
-    .s_axi_awid(s_axi_awid),
-    .s_axi_awaddr(s_axi_awaddr),
-    .s_axi_awlen(s_axi_awlen),
-    .s_axi_awsize(s_axi_awsize),
-    .s_axi_awburst(s_axi_awburst),
-    .s_axi_awlock(s_axi_awlock),
-    .s_axi_awcache(s_axi_awcache),
-    .s_axi_awprot(s_axi_awprot),
-    .s_axi_awregion(4'H0),
-    .s_axi_awqos(s_axi_awqos),
-    .s_axi_awuser(1'H0),
-    .s_axi_awvalid(s_axi_awvalid),
-    .s_axi_awready(s_axi_awready),
-    .s_axi_wid(s_axi_wid),
-    .s_axi_wdata(s_axi_wdata),
-    .s_axi_wstrb(s_axi_wstrb),
-    .s_axi_wlast(s_axi_wlast),
-    .s_axi_wuser(1'H0),
-    .s_axi_wvalid(s_axi_wvalid),
-    .s_axi_wready(s_axi_wready),
-    .s_axi_bid(s_axi_bid),
-    .s_axi_bresp(s_axi_bresp),
-    .s_axi_buser(),
-    .s_axi_bvalid(s_axi_bvalid),
-    .s_axi_bready(s_axi_bready),
-    .s_axi_arid(s_axi_arid),
-    .s_axi_araddr(s_axi_araddr),
-    .s_axi_arlen(s_axi_arlen),
-    .s_axi_arsize(s_axi_arsize),
-    .s_axi_arburst(s_axi_arburst),
-    .s_axi_arlock(s_axi_arlock),
-    .s_axi_arcache(s_axi_arcache),
-    .s_axi_arprot(s_axi_arprot),
-    .s_axi_arregion(4'H0),
-    .s_axi_arqos(s_axi_arqos),
-    .s_axi_aruser(1'H0),
-    .s_axi_arvalid(s_axi_arvalid),
-    .s_axi_arready(s_axi_arready),
-    .s_axi_rid(s_axi_rid),
-    .s_axi_rdata(s_axi_rdata),
-    .s_axi_rresp(s_axi_rresp),
-    .s_axi_rlast(s_axi_rlast),
-    .s_axi_ruser(),
-    .s_axi_rvalid(s_axi_rvalid),
-    .s_axi_rready(s_axi_rready),
-    .m_axi_awid(),
-    .m_axi_awaddr(m_axi_awaddr),
-    .m_axi_awlen(),
-    .m_axi_awsize(),
-    .m_axi_awburst(),
-    .m_axi_awlock(),
-    .m_axi_awcache(),
-    .m_axi_awprot(m_axi_awprot),
-    .m_axi_awregion(),
-    .m_axi_awqos(),
-    .m_axi_awuser(),
-    .m_axi_awvalid(m_axi_awvalid),
-    .m_axi_awready(m_axi_awready),
-    .m_axi_wid(),
-    .m_axi_wdata(m_axi_wdata),
-    .m_axi_wstrb(m_axi_wstrb),
-    .m_axi_wlast(),
-    .m_axi_wuser(),
-    .m_axi_wvalid(m_axi_wvalid),
-    .m_axi_wready(m_axi_wready),
-    .m_axi_bid(12'H000),
-    .m_axi_bresp(m_axi_bresp),
-    .m_axi_buser(1'H0),
-    .m_axi_bvalid(m_axi_bvalid),
-    .m_axi_bready(m_axi_bready),
-    .m_axi_arid(),
-    .m_axi_araddr(m_axi_araddr),
-    .m_axi_arlen(),
-    .m_axi_arsize(),
-    .m_axi_arburst(),
-    .m_axi_arlock(),
-    .m_axi_arcache(),
-    .m_axi_arprot(m_axi_arprot),
-    .m_axi_arregion(),
-    .m_axi_arqos(),
-    .m_axi_aruser(),
-    .m_axi_arvalid(m_axi_arvalid),
-    .m_axi_arready(m_axi_arready),
-    .m_axi_rid(12'H000),
-    .m_axi_rdata(m_axi_rdata),
-    .m_axi_rresp(m_axi_rresp),
-    .m_axi_rlast(1'H1),
-    .m_axi_ruser(1'H0),
-    .m_axi_rvalid(m_axi_rvalid),
-    .m_axi_rready(m_axi_rready)
-  );
-endmodule
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
index fd0100376b816c7b4c5da18bd5aad0a1ee87b127..35aba6cf5f6ec0c7122bd9ccef041b6ef85ba4f2 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
@@ -1025,195 +1025,6 @@
     </spirit:busInterface>
   </spirit:busInterfaces>
   <spirit:model>
-    <spirit:views>
-      <spirit:view>
-        <spirit:name>xilinx_verilogsynthesis</spirit:name>
-        <spirit:displayName>Verilog Synthesis</spirit:displayName>
-        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
-        <spirit:language>verilog</spirit:language>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_blk_mem_gen_8_3__ref_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_fifo_generator_13_1__ref_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_register_slice_2_1__ref_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>boundaryCRC</spirit:name>
-            <spirit:value>5e31c176</spirit:value>
-          </spirit:parameter>
-          <spirit:parameter>
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-            <spirit:value>1</spirit:value>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>3af11c64</spirit:value>
-          </spirit:parameter>
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-            <spirit:value>6</spirit:value>
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-      </spirit:view>
-      <spirit:view>
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-        <spirit:displayName>Synthesis Constraints</spirit:displayName>
-        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_synthesisconstraints_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
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-          <spirit:parameter>
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-          <spirit:parameter>
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-            <spirit:value>1</spirit:value>
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-          <spirit:parameter>
-            <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>3af11c64</spirit:value>
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-            <spirit:value>6</spirit:value>
-          </spirit:parameter>
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-      </spirit:view>
-      <spirit:view>
-        <spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
-        <spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
-        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
-        <spirit:language>verilog</spirit:language>
-        <spirit:fileSetRef>
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-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2333,8 +2099,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2353,8 +2118,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2380,8 +2144,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2404,8 +2167,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2428,8 +2190,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2452,8 +2213,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2476,8 +2236,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2500,8 +2259,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2524,8 +2282,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2548,8 +2305,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2572,8 +2328,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2596,8 +2351,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2620,8 +2374,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2640,8 +2393,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2660,8 +2412,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2687,8 +2438,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2711,8 +2461,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2735,8 +2484,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2755,8 +2503,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2779,8 +2526,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2799,8 +2545,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2819,8 +2564,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2846,8 +2590,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2873,8 +2616,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2900,8 +2642,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2923,8 +2664,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2946,8 +2686,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2970,8 +2709,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2994,8 +2732,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3018,8 +2755,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3042,8 +2778,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3066,8 +2801,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3090,8 +2824,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3114,8 +2847,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3138,8 +2870,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3162,8 +2893,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3186,8 +2916,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3210,8 +2939,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3230,8 +2958,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3250,8 +2977,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3277,8 +3003,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3304,8 +3029,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3331,8 +3055,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3354,8 +3077,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3381,8 +3103,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3404,8 +3125,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3427,8 +3147,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3537,726 +3256,6 @@
       <spirit:enumeration spirit:text="Unprotected: Master must be well-behaved">0</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
-  <spirit:fileSets>
-    <spirit:fileSet>
-      <spirit:name>xilinx_verilogsynthesis_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset</spirit:name>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_and.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_latch_and.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_latch_or.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_or.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_command_fifo.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>generic_baseblocks_v2_1_0</spirit:logicalName>
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-        <spirit:name>../../ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
-        <spirit:logicalName>axi_protocol_converter_v2_1_9</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
-        <spirit:logicalName>axi_protocol_converter_v2_1_9</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
-        <spirit:logicalName>axi_protocol_converter_v2_1_9</spirit:logicalName>
-      </spirit:file>
-    </spirit:fileSet>
-    <spirit:fileSet>
-      <spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
-      <spirit:file>
-        <spirit:name>sim/system_design_auto_pc_1.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
-      </spirit:file>
-    </spirit:fileSet>
-  </spirit:fileSets>
   <spirit:description>The AXI Protocol Converter IP provides the facility to change the protocol of the connection between an AXI4/AXI3/AXI4-Lite master and slave. It will convert between AXI4->AXI3/AXI4-Lite, AXI3->AXI4/AXI4-Lite, AXI4-Lite->AXI4/AXI3.</spirit:description>
   <spirit:parameters>
     <spirit:parameter>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_ooc.xdc b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_ooc.xdc
deleted file mode 100644
index c81fa5589d5f7ec1e396a1e8f8063289fc0d4efd..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_ooc.xdc
+++ /dev/null
@@ -1,57 +0,0 @@
-# (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-# 
-# DO NOT MODIFY THIS FILE.
-# #########################################################
-#
-# This XDC is used only in OOC mode for synthesis, implementation
-#
-# #########################################################
-
-
-create_clock -period 10 -name aclk [get_ports aclk]
-
-
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v
deleted file mode 100644
index 05ac26f48cdb001311489e69d2599256737b290d..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v
+++ /dev/null
@@ -1,348 +0,0 @@
-// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
-// 
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-// 
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-// 
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-// 
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-// 
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
-// IP Revision: 9
-
-`timescale 1ns/1ps
-
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module system_design_auto_pc_2 (
-  aclk,
-  aresetn,
-  s_axi_awid,
-  s_axi_awaddr,
-  s_axi_awlen,
-  s_axi_awsize,
-  s_axi_awburst,
-  s_axi_awlock,
-  s_axi_awcache,
-  s_axi_awprot,
-  s_axi_awqos,
-  s_axi_awvalid,
-  s_axi_awready,
-  s_axi_wid,
-  s_axi_wdata,
-  s_axi_wstrb,
-  s_axi_wlast,
-  s_axi_wvalid,
-  s_axi_wready,
-  s_axi_bid,
-  s_axi_bresp,
-  s_axi_bvalid,
-  s_axi_bready,
-  s_axi_arid,
-  s_axi_araddr,
-  s_axi_arlen,
-  s_axi_arsize,
-  s_axi_arburst,
-  s_axi_arlock,
-  s_axi_arcache,
-  s_axi_arprot,
-  s_axi_arqos,
-  s_axi_arvalid,
-  s_axi_arready,
-  s_axi_rid,
-  s_axi_rdata,
-  s_axi_rresp,
-  s_axi_rlast,
-  s_axi_rvalid,
-  s_axi_rready,
-  m_axi_awaddr,
-  m_axi_awprot,
-  m_axi_awvalid,
-  m_axi_awready,
-  m_axi_wdata,
-  m_axi_wstrb,
-  m_axi_wvalid,
-  m_axi_wready,
-  m_axi_bresp,
-  m_axi_bvalid,
-  m_axi_bready,
-  m_axi_araddr,
-  m_axi_arprot,
-  m_axi_arvalid,
-  m_axi_arready,
-  m_axi_rdata,
-  m_axi_rresp,
-  m_axi_rvalid,
-  m_axi_rready
-);
-
-(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
-input wire aclk;
-(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
-input wire aresetn;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
-input wire [11 : 0] s_axi_awid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
-input wire [31 : 0] s_axi_awaddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
-input wire [3 : 0] s_axi_awlen;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
-input wire [2 : 0] s_axi_awsize;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
-input wire [1 : 0] s_axi_awburst;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
-input wire [1 : 0] s_axi_awlock;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
-input wire [3 : 0] s_axi_awcache;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
-input wire [2 : 0] s_axi_awprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
-input wire [3 : 0] s_axi_awqos;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
-input wire s_axi_awvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
-output wire s_axi_awready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
-input wire [11 : 0] s_axi_wid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
-input wire [31 : 0] s_axi_wdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
-input wire [3 : 0] s_axi_wstrb;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
-input wire s_axi_wlast;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
-input wire s_axi_wvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
-output wire s_axi_wready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
-output wire [11 : 0] s_axi_bid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
-output wire [1 : 0] s_axi_bresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
-output wire s_axi_bvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
-input wire s_axi_bready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
-input wire [11 : 0] s_axi_arid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
-input wire [31 : 0] s_axi_araddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
-input wire [3 : 0] s_axi_arlen;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
-input wire [2 : 0] s_axi_arsize;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
-input wire [1 : 0] s_axi_arburst;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
-input wire [1 : 0] s_axi_arlock;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
-input wire [3 : 0] s_axi_arcache;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
-input wire [2 : 0] s_axi_arprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
-input wire [3 : 0] s_axi_arqos;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
-input wire s_axi_arvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
-output wire s_axi_arready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
-output wire [11 : 0] s_axi_rid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
-output wire [31 : 0] s_axi_rdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
-output wire [1 : 0] s_axi_rresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
-output wire s_axi_rlast;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
-output wire s_axi_rvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
-input wire s_axi_rready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
-output wire [31 : 0] m_axi_awaddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
-output wire [2 : 0] m_axi_awprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
-output wire m_axi_awvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
-input wire m_axi_awready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
-output wire [31 : 0] m_axi_wdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
-output wire [3 : 0] m_axi_wstrb;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
-output wire m_axi_wvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
-input wire m_axi_wready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
-input wire [1 : 0] m_axi_bresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
-input wire m_axi_bvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
-output wire m_axi_bready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
-output wire [31 : 0] m_axi_araddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
-output wire [2 : 0] m_axi_arprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
-output wire m_axi_arvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
-input wire m_axi_arready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
-input wire [31 : 0] m_axi_rdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
-input wire [1 : 0] m_axi_rresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
-input wire m_axi_rvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
-output wire m_axi_rready;
-
-  axi_protocol_converter_v2_1_9_axi_protocol_converter #(
-    .C_FAMILY("zynq"),
-    .C_M_AXI_PROTOCOL(2),
-    .C_S_AXI_PROTOCOL(1),
-    .C_IGNORE_ID(0),
-    .C_AXI_ID_WIDTH(12),
-    .C_AXI_ADDR_WIDTH(32),
-    .C_AXI_DATA_WIDTH(32),
-    .C_AXI_SUPPORTS_WRITE(1),
-    .C_AXI_SUPPORTS_READ(1),
-    .C_AXI_SUPPORTS_USER_SIGNALS(0),
-    .C_AXI_AWUSER_WIDTH(1),
-    .C_AXI_ARUSER_WIDTH(1),
-    .C_AXI_WUSER_WIDTH(1),
-    .C_AXI_RUSER_WIDTH(1),
-    .C_AXI_BUSER_WIDTH(1),
-    .C_TRANSLATION_MODE(2)
-  ) inst (
-    .aclk(aclk),
-    .aresetn(aresetn),
-    .s_axi_awid(s_axi_awid),
-    .s_axi_awaddr(s_axi_awaddr),
-    .s_axi_awlen(s_axi_awlen),
-    .s_axi_awsize(s_axi_awsize),
-    .s_axi_awburst(s_axi_awburst),
-    .s_axi_awlock(s_axi_awlock),
-    .s_axi_awcache(s_axi_awcache),
-    .s_axi_awprot(s_axi_awprot),
-    .s_axi_awregion(4'H0),
-    .s_axi_awqos(s_axi_awqos),
-    .s_axi_awuser(1'H0),
-    .s_axi_awvalid(s_axi_awvalid),
-    .s_axi_awready(s_axi_awready),
-    .s_axi_wid(s_axi_wid),
-    .s_axi_wdata(s_axi_wdata),
-    .s_axi_wstrb(s_axi_wstrb),
-    .s_axi_wlast(s_axi_wlast),
-    .s_axi_wuser(1'H0),
-    .s_axi_wvalid(s_axi_wvalid),
-    .s_axi_wready(s_axi_wready),
-    .s_axi_bid(s_axi_bid),
-    .s_axi_bresp(s_axi_bresp),
-    .s_axi_buser(),
-    .s_axi_bvalid(s_axi_bvalid),
-    .s_axi_bready(s_axi_bready),
-    .s_axi_arid(s_axi_arid),
-    .s_axi_araddr(s_axi_araddr),
-    .s_axi_arlen(s_axi_arlen),
-    .s_axi_arsize(s_axi_arsize),
-    .s_axi_arburst(s_axi_arburst),
-    .s_axi_arlock(s_axi_arlock),
-    .s_axi_arcache(s_axi_arcache),
-    .s_axi_arprot(s_axi_arprot),
-    .s_axi_arregion(4'H0),
-    .s_axi_arqos(s_axi_arqos),
-    .s_axi_aruser(1'H0),
-    .s_axi_arvalid(s_axi_arvalid),
-    .s_axi_arready(s_axi_arready),
-    .s_axi_rid(s_axi_rid),
-    .s_axi_rdata(s_axi_rdata),
-    .s_axi_rresp(s_axi_rresp),
-    .s_axi_rlast(s_axi_rlast),
-    .s_axi_ruser(),
-    .s_axi_rvalid(s_axi_rvalid),
-    .s_axi_rready(s_axi_rready),
-    .m_axi_awid(),
-    .m_axi_awaddr(m_axi_awaddr),
-    .m_axi_awlen(),
-    .m_axi_awsize(),
-    .m_axi_awburst(),
-    .m_axi_awlock(),
-    .m_axi_awcache(),
-    .m_axi_awprot(m_axi_awprot),
-    .m_axi_awregion(),
-    .m_axi_awqos(),
-    .m_axi_awuser(),
-    .m_axi_awvalid(m_axi_awvalid),
-    .m_axi_awready(m_axi_awready),
-    .m_axi_wid(),
-    .m_axi_wdata(m_axi_wdata),
-    .m_axi_wstrb(m_axi_wstrb),
-    .m_axi_wlast(),
-    .m_axi_wuser(),
-    .m_axi_wvalid(m_axi_wvalid),
-    .m_axi_wready(m_axi_wready),
-    .m_axi_bid(12'H000),
-    .m_axi_bresp(m_axi_bresp),
-    .m_axi_buser(1'H0),
-    .m_axi_bvalid(m_axi_bvalid),
-    .m_axi_bready(m_axi_bready),
-    .m_axi_arid(),
-    .m_axi_araddr(m_axi_araddr),
-    .m_axi_arlen(),
-    .m_axi_arsize(),
-    .m_axi_arburst(),
-    .m_axi_arlock(),
-    .m_axi_arcache(),
-    .m_axi_arprot(m_axi_arprot),
-    .m_axi_arregion(),
-    .m_axi_arqos(),
-    .m_axi_aruser(),
-    .m_axi_arvalid(m_axi_arvalid),
-    .m_axi_arready(m_axi_arready),
-    .m_axi_rid(12'H000),
-    .m_axi_rdata(m_axi_rdata),
-    .m_axi_rresp(m_axi_rresp),
-    .m_axi_rlast(1'H1),
-    .m_axi_ruser(1'H0),
-    .m_axi_rvalid(m_axi_rvalid),
-    .m_axi_rready(m_axi_rready)
-  );
-endmodule
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/synth/system_design_auto_pc_2.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/synth/system_design_auto_pc_2.v
deleted file mode 100644
index c7b8a5d187ee353bc510c346d359f46b036fd181..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/synth/system_design_auto_pc_2.v
+++ /dev/null
@@ -1,350 +0,0 @@
-// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
-// 
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-// 
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-// 
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-// 
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-// 
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
-// IP Revision: 9
-
-(* X_CORE_INFO = "axi_protocol_converter_v2_1_9_axi_protocol_converter,Vivado 2016.2" *)
-(* CHECK_LICENSE_TYPE = "system_design_auto_pc_2,axi_protocol_converter_v2_1_9_axi_protocol_converter,{}" *)
-(* CORE_GENERATION_INFO = "system_design_auto_pc_2,axi_protocol_converter_v2_1_9_axi_protocol_converter,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER\
-_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module system_design_auto_pc_2 (
-  aclk,
-  aresetn,
-  s_axi_awid,
-  s_axi_awaddr,
-  s_axi_awlen,
-  s_axi_awsize,
-  s_axi_awburst,
-  s_axi_awlock,
-  s_axi_awcache,
-  s_axi_awprot,
-  s_axi_awqos,
-  s_axi_awvalid,
-  s_axi_awready,
-  s_axi_wid,
-  s_axi_wdata,
-  s_axi_wstrb,
-  s_axi_wlast,
-  s_axi_wvalid,
-  s_axi_wready,
-  s_axi_bid,
-  s_axi_bresp,
-  s_axi_bvalid,
-  s_axi_bready,
-  s_axi_arid,
-  s_axi_araddr,
-  s_axi_arlen,
-  s_axi_arsize,
-  s_axi_arburst,
-  s_axi_arlock,
-  s_axi_arcache,
-  s_axi_arprot,
-  s_axi_arqos,
-  s_axi_arvalid,
-  s_axi_arready,
-  s_axi_rid,
-  s_axi_rdata,
-  s_axi_rresp,
-  s_axi_rlast,
-  s_axi_rvalid,
-  s_axi_rready,
-  m_axi_awaddr,
-  m_axi_awprot,
-  m_axi_awvalid,
-  m_axi_awready,
-  m_axi_wdata,
-  m_axi_wstrb,
-  m_axi_wvalid,
-  m_axi_wready,
-  m_axi_bresp,
-  m_axi_bvalid,
-  m_axi_bready,
-  m_axi_araddr,
-  m_axi_arprot,
-  m_axi_arvalid,
-  m_axi_arready,
-  m_axi_rdata,
-  m_axi_rresp,
-  m_axi_rvalid,
-  m_axi_rready
-);
-
-(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
-input wire aclk;
-(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
-input wire aresetn;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
-input wire [11 : 0] s_axi_awid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
-input wire [31 : 0] s_axi_awaddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
-input wire [3 : 0] s_axi_awlen;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
-input wire [2 : 0] s_axi_awsize;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
-input wire [1 : 0] s_axi_awburst;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
-input wire [1 : 0] s_axi_awlock;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
-input wire [3 : 0] s_axi_awcache;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
-input wire [2 : 0] s_axi_awprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
-input wire [3 : 0] s_axi_awqos;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
-input wire s_axi_awvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
-output wire s_axi_awready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
-input wire [11 : 0] s_axi_wid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
-input wire [31 : 0] s_axi_wdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
-input wire [3 : 0] s_axi_wstrb;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
-input wire s_axi_wlast;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
-input wire s_axi_wvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
-output wire s_axi_wready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
-output wire [11 : 0] s_axi_bid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
-output wire [1 : 0] s_axi_bresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
-output wire s_axi_bvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
-input wire s_axi_bready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
-input wire [11 : 0] s_axi_arid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
-input wire [31 : 0] s_axi_araddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
-input wire [3 : 0] s_axi_arlen;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
-input wire [2 : 0] s_axi_arsize;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
-input wire [1 : 0] s_axi_arburst;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
-input wire [1 : 0] s_axi_arlock;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
-input wire [3 : 0] s_axi_arcache;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
-input wire [2 : 0] s_axi_arprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
-input wire [3 : 0] s_axi_arqos;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
-input wire s_axi_arvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
-output wire s_axi_arready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
-output wire [11 : 0] s_axi_rid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
-output wire [31 : 0] s_axi_rdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
-output wire [1 : 0] s_axi_rresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
-output wire s_axi_rlast;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
-output wire s_axi_rvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
-input wire s_axi_rready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
-output wire [31 : 0] m_axi_awaddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
-output wire [2 : 0] m_axi_awprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
-output wire m_axi_awvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
-input wire m_axi_awready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
-output wire [31 : 0] m_axi_wdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
-output wire [3 : 0] m_axi_wstrb;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
-output wire m_axi_wvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
-input wire m_axi_wready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
-input wire [1 : 0] m_axi_bresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
-input wire m_axi_bvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
-output wire m_axi_bready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
-output wire [31 : 0] m_axi_araddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
-output wire [2 : 0] m_axi_arprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
-output wire m_axi_arvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
-input wire m_axi_arready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
-input wire [31 : 0] m_axi_rdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
-input wire [1 : 0] m_axi_rresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
-input wire m_axi_rvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
-output wire m_axi_rready;
-
-  axi_protocol_converter_v2_1_9_axi_protocol_converter #(
-    .C_FAMILY("zynq"),
-    .C_M_AXI_PROTOCOL(2),
-    .C_S_AXI_PROTOCOL(1),
-    .C_IGNORE_ID(0),
-    .C_AXI_ID_WIDTH(12),
-    .C_AXI_ADDR_WIDTH(32),
-    .C_AXI_DATA_WIDTH(32),
-    .C_AXI_SUPPORTS_WRITE(1),
-    .C_AXI_SUPPORTS_READ(1),
-    .C_AXI_SUPPORTS_USER_SIGNALS(0),
-    .C_AXI_AWUSER_WIDTH(1),
-    .C_AXI_ARUSER_WIDTH(1),
-    .C_AXI_WUSER_WIDTH(1),
-    .C_AXI_RUSER_WIDTH(1),
-    .C_AXI_BUSER_WIDTH(1),
-    .C_TRANSLATION_MODE(2)
-  ) inst (
-    .aclk(aclk),
-    .aresetn(aresetn),
-    .s_axi_awid(s_axi_awid),
-    .s_axi_awaddr(s_axi_awaddr),
-    .s_axi_awlen(s_axi_awlen),
-    .s_axi_awsize(s_axi_awsize),
-    .s_axi_awburst(s_axi_awburst),
-    .s_axi_awlock(s_axi_awlock),
-    .s_axi_awcache(s_axi_awcache),
-    .s_axi_awprot(s_axi_awprot),
-    .s_axi_awregion(4'H0),
-    .s_axi_awqos(s_axi_awqos),
-    .s_axi_awuser(1'H0),
-    .s_axi_awvalid(s_axi_awvalid),
-    .s_axi_awready(s_axi_awready),
-    .s_axi_wid(s_axi_wid),
-    .s_axi_wdata(s_axi_wdata),
-    .s_axi_wstrb(s_axi_wstrb),
-    .s_axi_wlast(s_axi_wlast),
-    .s_axi_wuser(1'H0),
-    .s_axi_wvalid(s_axi_wvalid),
-    .s_axi_wready(s_axi_wready),
-    .s_axi_bid(s_axi_bid),
-    .s_axi_bresp(s_axi_bresp),
-    .s_axi_buser(),
-    .s_axi_bvalid(s_axi_bvalid),
-    .s_axi_bready(s_axi_bready),
-    .s_axi_arid(s_axi_arid),
-    .s_axi_araddr(s_axi_araddr),
-    .s_axi_arlen(s_axi_arlen),
-    .s_axi_arsize(s_axi_arsize),
-    .s_axi_arburst(s_axi_arburst),
-    .s_axi_arlock(s_axi_arlock),
-    .s_axi_arcache(s_axi_arcache),
-    .s_axi_arprot(s_axi_arprot),
-    .s_axi_arregion(4'H0),
-    .s_axi_arqos(s_axi_arqos),
-    .s_axi_aruser(1'H0),
-    .s_axi_arvalid(s_axi_arvalid),
-    .s_axi_arready(s_axi_arready),
-    .s_axi_rid(s_axi_rid),
-    .s_axi_rdata(s_axi_rdata),
-    .s_axi_rresp(s_axi_rresp),
-    .s_axi_rlast(s_axi_rlast),
-    .s_axi_ruser(),
-    .s_axi_rvalid(s_axi_rvalid),
-    .s_axi_rready(s_axi_rready),
-    .m_axi_awid(),
-    .m_axi_awaddr(m_axi_awaddr),
-    .m_axi_awlen(),
-    .m_axi_awsize(),
-    .m_axi_awburst(),
-    .m_axi_awlock(),
-    .m_axi_awcache(),
-    .m_axi_awprot(m_axi_awprot),
-    .m_axi_awregion(),
-    .m_axi_awqos(),
-    .m_axi_awuser(),
-    .m_axi_awvalid(m_axi_awvalid),
-    .m_axi_awready(m_axi_awready),
-    .m_axi_wid(),
-    .m_axi_wdata(m_axi_wdata),
-    .m_axi_wstrb(m_axi_wstrb),
-    .m_axi_wlast(),
-    .m_axi_wuser(),
-    .m_axi_wvalid(m_axi_wvalid),
-    .m_axi_wready(m_axi_wready),
-    .m_axi_bid(12'H000),
-    .m_axi_bresp(m_axi_bresp),
-    .m_axi_buser(1'H0),
-    .m_axi_bvalid(m_axi_bvalid),
-    .m_axi_bready(m_axi_bready),
-    .m_axi_arid(),
-    .m_axi_araddr(m_axi_araddr),
-    .m_axi_arlen(),
-    .m_axi_arsize(),
-    .m_axi_arburst(),
-    .m_axi_arlock(),
-    .m_axi_arcache(),
-    .m_axi_arprot(m_axi_arprot),
-    .m_axi_arregion(),
-    .m_axi_arqos(),
-    .m_axi_aruser(),
-    .m_axi_arvalid(m_axi_arvalid),
-    .m_axi_arready(m_axi_arready),
-    .m_axi_rid(12'H000),
-    .m_axi_rdata(m_axi_rdata),
-    .m_axi_rresp(m_axi_rresp),
-    .m_axi_rlast(1'H1),
-    .m_axi_ruser(1'H0),
-    .m_axi_rvalid(m_axi_rvalid),
-    .m_axi_rready(m_axi_rready)
-  );
-endmodule
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
index e1fec52672fde887220fab56b17da12e94278d6d..86dbd6f275957dc57e49b6f70963b27ec8b25769 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
@@ -1025,195 +1025,6 @@
     </spirit:busInterface>
   </spirit:busInterfaces>
   <spirit:model>
-    <spirit:views>
-      <spirit:view>
-        <spirit:name>xilinx_verilogsynthesis</spirit:name>
-        <spirit:displayName>Verilog Synthesis</spirit:displayName>
-        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
-        <spirit:language>verilog</spirit:language>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_generic_baseblocks_2_1__ref_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_blk_mem_gen_8_3__ref_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_fifo_generator_13_1__ref_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_data_fifo_2_1__ref_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_infrastructure_1_1__ref_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_xilinx_com_ip_axi_register_slice_2_1__ref_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:fileSetRef>
-          <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
-        </spirit:fileSetRef>
-        <spirit:parameters>
-          <spirit:parameter>
-            <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>boundaryCRC</spirit:name>
-            <spirit:value>a68a03f3</spirit:value>
-          </spirit:parameter>
-          <spirit:parameter>
-            <spirit:name>boundaryCRCversion</spirit:name>
-            <spirit:value>1</spirit:value>
-          </spirit:parameter>
-          <spirit:parameter>
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               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2197,8 +1969,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2221,8 +1992,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2245,8 +2015,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2269,8 +2038,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2289,8 +2057,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2313,8 +2080,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2333,8 +2099,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2353,8 +2118,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2380,8 +2144,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2404,8 +2167,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2428,8 +2190,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2452,8 +2213,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2476,8 +2236,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2500,8 +2259,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2524,8 +2282,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2548,8 +2305,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2572,8 +2328,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2596,8 +2351,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2620,8 +2374,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2640,8 +2393,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2660,8 +2412,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2687,8 +2438,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2711,8 +2461,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2735,8 +2484,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2755,8 +2503,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2779,8 +2526,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2799,8 +2545,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2819,8 +2564,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2846,8 +2590,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2873,8 +2616,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2900,8 +2642,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2923,8 +2664,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -2946,8 +2686,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2970,8 +2709,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -2994,8 +2732,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3018,8 +2755,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3042,8 +2778,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3066,8 +2801,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3090,8 +2824,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3114,8 +2847,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3138,8 +2870,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3162,8 +2893,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3186,8 +2916,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3210,8 +2939,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3230,8 +2958,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -3250,8 +2977,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3277,8 +3003,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3304,8 +3029,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3331,8 +3055,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3354,8 +3077,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3381,8 +3103,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3404,8 +3125,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -3427,8 +3147,7 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>wire</spirit:typeName>
-              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
-              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
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-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
-        <spirit:logicalName>axi_protocol_converter_v2_1_9</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
-        <spirit:logicalName>axi_protocol_converter_v2_1_9</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_cmd_translator.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
-        <spirit:logicalName>axi_protocol_converter_v2_1_9</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
-        <spirit:logicalName>axi_protocol_converter_v2_1_9</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_r_channel.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
-        <spirit:logicalName>axi_protocol_converter_v2_1_9</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_aw_channel.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
-        <spirit:logicalName>axi_protocol_converter_v2_1_9</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
-        <spirit:logicalName>axi_protocol_converter_v2_1_9</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
-        <spirit:logicalName>axi_protocol_converter_v2_1_9</spirit:logicalName>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
-        <spirit:logicalName>axi_protocol_converter_v2_1_9</spirit:logicalName>
-      </spirit:file>
-    </spirit:fileSet>
-    <spirit:fileSet>
-      <spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
-      <spirit:file>
-        <spirit:name>sim/system_design_auto_pc_2.v</spirit:name>
-        <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
-      </spirit:file>
-    </spirit:fileSet>
-  </spirit:fileSets>
   <spirit:description>The AXI Protocol Converter IP provides the facility to change the protocol of the connection between an AXI4/AXI3/AXI4-Lite master and slave. It will convert between AXI4->AXI3/AXI4-Lite, AXI3->AXI4/AXI4-Lite, AXI4-Lite->AXI4/AXI3.</spirit:description>
   <spirit:parameters>
     <spirit:parameter>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_ooc.xdc b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_ooc.xdc
deleted file mode 100644
index 8808ceb4aec5c51eb9acf25ab851e7d7e942ea6a..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_ooc.xdc
+++ /dev/null
@@ -1,57 +0,0 @@
-# (c) Copyright 2012-2017 Xilinx, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-# 
-# DO NOT MODIFY THIS FILE.
-# #########################################################
-#
-# This XDC is used only in OOC mode for synthesis, implementation
-#
-# #########################################################
-
-
-create_clock -period 16 -name aclk [get_ports aclk]
-
-
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xml
index 6cb57c91ffafe2e3f4a87d33d39f845318925c3f..33b938d6e4da770e89553494df48d91151ae0124 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xml
@@ -3378,7 +3378,7 @@ Note: This value must be greater than or equal to the largest expected packet to
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:18 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:14 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -3409,7 +3409,7 @@ Note: This value must be greater than or equal to the largest expected packet to
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:18 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:14 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -3461,7 +3461,7 @@ Note: This value must be greater than or equal to the largest expected packet to
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:18 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:14 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -3492,7 +3492,7 @@ Note: This value must be greater than or equal to the largest expected packet to
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:18 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:14 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xml
index 9eeeedc6c474c06995de99ab31047112cb1cfd27..55a0a644c2130d4d5fc96b467160b4011186a92b 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xml
@@ -687,7 +687,7 @@ Writing a 1 to this bit position clears the receive FIFO
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:20 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:15 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -718,7 +718,7 @@ Writing a 1 to this bit position clears the receive FIFO
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:20 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:15 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -761,7 +761,7 @@ Writing a 1 to this bit position clears the receive FIFO
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:20 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:15 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -792,7 +792,7 @@ Writing a 1 to this bit position clears the receive FIFO
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:20 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:15 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -822,7 +822,7 @@ Writing a 1 to this bit position clears the receive FIFO
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:20 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:15 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xml
index 332727bf01474de2d74861a7d372747ca819a947..4a8be210c6c6280d8846936bf74847c2cf728d8c 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xml
@@ -344,7 +344,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:16 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -375,7 +375,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:16 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -405,7 +405,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:16 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -436,7 +436,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:16 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xml
index 6200299607ca640583de29fc33bd8ac2189b4880..a8f8d761a2fa2eff50cd7000cfb0134fa44c761f 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xml
@@ -344,7 +344,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:16 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -375,7 +375,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:16 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -405,7 +405,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:16 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -436,7 +436,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:16 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
index 24bd7a13951bfa3a0f5ed1e5dd19f0549c21b2a7..0518f1cbd6241d2e19ba4d8905aaafc030dba40f 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
@@ -46,8 +46,8 @@
 -- 
 -- DO NOT MODIFY THIS FILE.
 
--- IP VLNV: user.org:user:fasec_hwtest:3.0.1
--- IP Revision: 25
+-- IP VLNV: user.org:user:fasec_hwtest:3.1.0
+-- IP Revision: 26
 
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/synth/system_design_fasec_hwtest_0_0.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/synth/system_design_fasec_hwtest_0_0.vhd
index edc4c959891eb2c0f1562c8bf0ba779907c37f8a..313714e3bc6d5f935d08d8cd99a2434b6501954f 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/synth/system_design_fasec_hwtest_0_0.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/synth/system_design_fasec_hwtest_0_0.vhd
@@ -46,8 +46,8 @@
 -- 
 -- DO NOT MODIFY THIS FILE.
 
--- IP VLNV: user.org:user:fasec_hwtest:3.0.1
--- IP Revision: 25
+-- IP VLNV: user.org:user:fasec_hwtest:3.1.0
+-- IP Revision: 26
 
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci
index c16d8eb89f261e4ee9b0029dd6370e6ecf8b3378..62ab93f2dd11c4aa02afa77ed0cf2315f72aba25 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci
@@ -7,7 +7,7 @@
   <spirit:componentInstances>
     <spirit:componentInstance>
       <spirit:instanceName>system_design_fasec_hwtest_0_0</spirit:instanceName>
-      <spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="fasec_hwtest" spirit:version="3.0.1"/>
+      <spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="fasec_hwtest" spirit:version="3.1.0"/>
       <spirit:configurableElementValues>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
@@ -61,7 +61,7 @@
         <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">25</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">26</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
index 5a5ded9fb03f9c5c226f10c3f1f0c5ee61c3e843..1a7a966903e26e2f02c5750716bd6984ba8fcda7 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
@@ -358,7 +358,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:23 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -370,7 +370,7 @@
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>e217fff0</spirit:value>
+            <spirit:value>1734b949</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRCversion</spirit:name>
@@ -389,7 +389,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:23 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -401,7 +401,7 @@
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>e217fff0</spirit:value>
+            <spirit:value>1734b949</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRCversion</spirit:name>
@@ -419,7 +419,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:23 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -431,7 +431,7 @@
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>33292e2a</spirit:value>
+            <spirit:value>c94f1ed1</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRCversion</spirit:name>
@@ -450,7 +450,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:23 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -462,7 +462,7 @@
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>33292e2a</spirit:value>
+            <spirit:value>c94f1ed1</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRCversion</spirit:name>
@@ -1351,49 +1351,49 @@
         <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
     </spirit:fileSet>
@@ -1408,49 +1408,49 @@
     <spirit:fileSet>
       <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
     </spirit:fileSet>
@@ -1498,7 +1498,7 @@
   <spirit:vendorExtensions>
     <xilinx:coreExtensions>
       <xilinx:displayName>fasec_hwtest</xilinx:displayName>
-      <xilinx:coreRevision>25</xilinx:coreRevision>
+      <xilinx:coreRevision>26</xilinx:coreRevision>
       <xilinx:tags>
         <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:1.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
         <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:2.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
@@ -1523,6 +1523,7 @@
         <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:2.9_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
         <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
         <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.0.1_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
+        <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.1.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
       </xilinx:tags>
       <xilinx:configElementInfos>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valueSource="user"/>
@@ -1560,7 +1561,7 @@
       <xilinx:xilinxVersion>2016.2</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="92ed6682"/>
       <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="6bf44be4"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ab630095"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="503ca184"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="3ad5aecc"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="455aa684"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="f383f867"/>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/hdl/verilog/system_design_processing_system7_0_0.hwdef b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/hdl/verilog/system_design_processing_system7_0_0.hwdef
index 87b507282f5205167fa3cb881912abc3a9c3de7f..809769a6a0865de630dac6821cee526e3d6b4002 100644
Binary files a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/hdl/verilog/system_design_processing_system7_0_0.hwdef and b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/hdl/verilog/system_design_processing_system7_0_0.hwdef differ
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xml
index c920c902528cdfa9fdb7b6f16afa22c563434d50..568188db2f22fba33b9d6809bae7af0c5c95abdc 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xml
@@ -10243,7 +10243,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:13 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -10274,7 +10274,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:13 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -10330,7 +10330,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2.xml
index 99c8d159a180c9845123cba42c7ed441520aa66e..b756ffced7d5012765a335a339b71f04cd722922 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2.xml
@@ -278,7 +278,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -308,7 +308,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -339,7 +339,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -373,7 +373,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -404,7 +404,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -434,7 +434,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/system_design_rst_wrc_1p_kintex7_0_62M_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/system_design_rst_wrc_1p_kintex7_0_62M_0.xml
index 10f924c1c85951ce6c025e24a44025c7ef1a4934..259ef6b70569b6eb3e6900fe09c28ab85834a268 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/system_design_rst_wrc_1p_kintex7_0_62M_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/system_design_rst_wrc_1p_kintex7_0_62M_0.xml
@@ -278,7 +278,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:20 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:16 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -308,7 +308,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:20 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:16 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -339,7 +339,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:20 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:16 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -373,7 +373,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -404,7 +404,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:20 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:16 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -434,7 +434,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:20 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:16 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/mux_buffering_fifo.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/mux_buffering_fifo.xml
index 99a20db9a2f8c3c692f5a781e061a8eb1fccbb7c..cd1ae1cbe74471b3cba553251e5507d85e2df07f 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/mux_buffering_fifo.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/ip_cores/xilinx_ip/mux_buffering_fifo/mux_buffering_fifo.xml
@@ -1246,7 +1246,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:41:38 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1276,7 +1276,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:41:38 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1307,7 +1307,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:41:38 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1337,7 +1337,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:41:38 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1368,7 +1368,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:25 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:41:38 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd
index dec12ff1a6467f38e297b1bab355c1e0441a8c84..a198a68b987ecc81e98b2f627d20a89078881243 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/sim/system_design_wrc_1p_kintex7_0_0.vhd
@@ -46,8 +46,8 @@
 -- 
 -- DO NOT MODIFY THIS FILE.
 
--- IP VLNV: CERN:wrc:wrc_1p_kintex7:2.3.1
--- IP Revision: 13
+-- IP VLNV: CERN:wrc:wrc_1p_kintex7:3.1.0
+-- IP Revision: 15
 
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
@@ -56,10 +56,11 @@ USE ieee.numeric_std.ALL;
 ENTITY system_design_wrc_1p_kintex7_0_0 IS
   PORT (
     clk_20m_vcxo_i : IN STD_LOGIC;
-    clk_aux_p_i : IN STD_LOGIC;
-    clk_aux_n_i : IN STD_LOGIC;
     gtp_dedicated_clk_p_i : IN STD_LOGIC;
     gtp_dedicated_clk_n_i : IN STD_LOGIC;
+    clk_dmtd_b : INOUT STD_LOGIC;
+    clk_ref_b : INOUT STD_LOGIC;
+    clk_rx_rbclk_b : INOUT STD_LOGIC;
     gtp0_activity_led_o : OUT STD_LOGIC;
     gtp0_synced_led_o : OUT STD_LOGIC;
     gtp0_link_led_o : OUT STD_LOGIC;
@@ -124,10 +125,11 @@ ARCHITECTURE system_design_wrc_1p_kintex7_0_0_arch OF system_design_wrc_1p_kinte
     );
     PORT (
       clk_20m_vcxo_i : IN STD_LOGIC;
-      clk_aux_p_i : IN STD_LOGIC;
-      clk_aux_n_i : IN STD_LOGIC;
       gtp_dedicated_clk_p_i : IN STD_LOGIC;
       gtp_dedicated_clk_n_i : IN STD_LOGIC;
+      clk_dmtd_b : INOUT STD_LOGIC;
+      clk_ref_b : INOUT STD_LOGIC;
+      clk_rx_rbclk_b : INOUT STD_LOGIC;
       gtp0_activity_led_o : OUT STD_LOGIC;
       gtp0_synced_led_o : OUT STD_LOGIC;
       gtp0_link_led_o : OUT STD_LOGIC;
@@ -223,10 +225,11 @@ BEGIN
     )
     PORT MAP (
       clk_20m_vcxo_i => clk_20m_vcxo_i,
-      clk_aux_p_i => clk_aux_p_i,
-      clk_aux_n_i => clk_aux_n_i,
       gtp_dedicated_clk_p_i => gtp_dedicated_clk_p_i,
       gtp_dedicated_clk_n_i => gtp_dedicated_clk_n_i,
+      clk_dmtd_b => clk_dmtd_b,
+      clk_ref_b => clk_ref_b,
+      clk_rx_rbclk_b => clk_rx_rbclk_b,
       gtp0_activity_led_o => gtp0_activity_led_o,
       gtp0_synced_led_o => gtp0_synced_led_o,
       gtp0_link_led_o => gtp0_link_led_o,
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/syn/constraints/timing_constraints.xdc b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/syn/constraints/timing_constraints.xdc
new file mode 100755
index 0000000000000000000000000000000000000000..7e157e21e8f2df3ca91454317e3564bd1de648ba
--- /dev/null
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/syn/constraints/timing_constraints.xdc
@@ -0,0 +1,11 @@
+create_clock -period 8.000 -name U_GTP/U_GTX_INST/I -waveform {0.000 4.000} [get_pins U_GTP/U_GTX_INST/gtxe2_i/TXOUTCLK]
+create_clock -period 8.000 -name U_GTP/U_GTX_INST/rx_rec_clk_bufin -waveform {0.000 4.000} [get_pins U_GTP/U_GTX_INST/gtxe2_i/RXOUTCLK]
+create_clock -period 50.000 -name clk_20m_vcxo_i -waveform {0.000 25.000} [get_ports clk_20m_vcxo_i]
+create_clock -period 8.000 -name gtp_dedicated_clk_p_i -waveform {0.000 4.000} [get_ports gtp_dedicated_clk_p_i]
+set_property ASYNC_REG true [get_cells {U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_straight.clk_i_d0_reg}]
+set_property ASYNC_REG true [get_cells {U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_straight.clk_i_d3_reg}]
+set_clock_groups -asynchronous -group [get_clocks U_GTP/U_GTX_INST/I] -group [get_clocks cmp_dmtd_clk_pll_n_4]
+set_property ASYNC_REG true [get_cells {U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/gen_straight.clk_i_d0_reg}]
+set_property ASYNC_REG true [get_cells {U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/gen_straight.clk_i_d3_reg}]
+set_clock_groups -asynchronous -group [get_clocks U_GTP/U_GTX_INST/rx_rec_clk_bufin] -group [get_clocks cmp_dmtd_clk_pll_n_4]
+set_false_path -from [get_clocks cmp_dmtd_clk_pll_n_4] -to [get_clocks I]
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/synth/system_design_wrc_1p_kintex7_0_0.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/synth/system_design_wrc_1p_kintex7_0_0.vhd
index 3205b9d9b7c85a787e66a42d1bf83511675137e9..a1622155427639c952738ebcd8311f1d02523610 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/synth/system_design_wrc_1p_kintex7_0_0.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/synth/system_design_wrc_1p_kintex7_0_0.vhd
@@ -46,8 +46,8 @@
 -- 
 -- DO NOT MODIFY THIS FILE.
 
--- IP VLNV: CERN:wrc:wrc_1p_kintex7:2.3.1
--- IP Revision: 13
+-- IP VLNV: CERN:wrc:wrc_1p_kintex7:3.1.0
+-- IP Revision: 15
 
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
@@ -56,10 +56,11 @@ USE ieee.numeric_std.ALL;
 ENTITY system_design_wrc_1p_kintex7_0_0 IS
   PORT (
     clk_20m_vcxo_i : IN STD_LOGIC;
-    clk_aux_p_i : IN STD_LOGIC;
-    clk_aux_n_i : IN STD_LOGIC;
     gtp_dedicated_clk_p_i : IN STD_LOGIC;
     gtp_dedicated_clk_n_i : IN STD_LOGIC;
+    clk_dmtd_b : INOUT STD_LOGIC;
+    clk_ref_b : INOUT STD_LOGIC;
+    clk_rx_rbclk_b : INOUT STD_LOGIC;
     gtp0_activity_led_o : OUT STD_LOGIC;
     gtp0_synced_led_o : OUT STD_LOGIC;
     gtp0_link_led_o : OUT STD_LOGIC;
@@ -124,10 +125,11 @@ ARCHITECTURE system_design_wrc_1p_kintex7_0_0_arch OF system_design_wrc_1p_kinte
     );
     PORT (
       clk_20m_vcxo_i : IN STD_LOGIC;
-      clk_aux_p_i : IN STD_LOGIC;
-      clk_aux_n_i : IN STD_LOGIC;
       gtp_dedicated_clk_p_i : IN STD_LOGIC;
       gtp_dedicated_clk_n_i : IN STD_LOGIC;
+      clk_dmtd_b : INOUT STD_LOGIC;
+      clk_ref_b : INOUT STD_LOGIC;
+      clk_rx_rbclk_b : INOUT STD_LOGIC;
       gtp0_activity_led_o : OUT STD_LOGIC;
       gtp0_synced_led_o : OUT STD_LOGIC;
       gtp0_link_led_o : OUT STD_LOGIC;
@@ -227,10 +229,11 @@ BEGIN
     )
     PORT MAP (
       clk_20m_vcxo_i => clk_20m_vcxo_i,
-      clk_aux_p_i => clk_aux_p_i,
-      clk_aux_n_i => clk_aux_n_i,
       gtp_dedicated_clk_p_i => gtp_dedicated_clk_p_i,
       gtp_dedicated_clk_n_i => gtp_dedicated_clk_n_i,
+      clk_dmtd_b => clk_dmtd_b,
+      clk_ref_b => clk_ref_b,
+      clk_rx_rbclk_b => clk_rx_rbclk_b,
       gtp0_activity_led_o => gtp0_activity_led_o,
       gtp0_synced_led_o => gtp0_synced_led_o,
       gtp0_link_led_o => gtp0_link_led_o,
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci
index 0731144157c6caef17e421d662491541e0e83120..1e424ba7f88a348813ee487356a2628b6d4ca115 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci
@@ -7,7 +7,7 @@
   <spirit:componentInstances>
     <spirit:componentInstance>
       <spirit:instanceName>system_design_wrc_1p_kintex7_0_0</spirit:instanceName>
-      <spirit:componentRef spirit:vendor="CERN" spirit:library="wrc" spirit:name="wrc_1p_kintex7" spirit:version="2.3.1"/>
+      <spirit:componentRef spirit:vendor="CERN" spirit:library="wrc" spirit:name="wrc_1p_kintex7" spirit:version="3.1.0"/>
       <spirit:configurableElementValues>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
@@ -52,7 +52,7 @@
         <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">13</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xml
index 3df553c684a6603bc4e331d2a095f574f4168b51..8026d8b256911d8bb2bae2fa984872408184544d 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xml
@@ -457,11 +457,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:24 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:41:36 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
-            <spirit:value>93ab2dfb</spirit:value>
+            <spirit:value>f9413ac0</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRCversion</spirit:name>
@@ -469,7 +469,7 @@
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>b22bb64e</spirit:value>
+            <spirit:value>1098cdbd</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRCversion</spirit:name>
@@ -488,11 +488,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:24 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:41:36 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
-            <spirit:value>93ab2dfb</spirit:value>
+            <spirit:value>f9413ac0</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRCversion</spirit:name>
@@ -500,7 +500,7 @@
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>b22bb64e</spirit:value>
+            <spirit:value>1098cdbd</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRCversion</spirit:name>
@@ -518,11 +518,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:24 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:41:36 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
-            <spirit:value>93ab2dfb</spirit:value>
+            <spirit:value>f9413ac0</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRCversion</spirit:name>
@@ -530,7 +530,7 @@
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>030cf076</spirit:value>
+            <spirit:value>9caca4d5</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRCversion</spirit:name>
@@ -549,11 +549,11 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Mar 23 20:34:24 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:41:37 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
-            <spirit:value>93ab2dfb</spirit:value>
+            <spirit:value>f9413ac0</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRCversion</spirit:name>
@@ -561,7 +561,7 @@
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>030cf076</spirit:value>
+            <spirit:value>9caca4d5</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRCversion</spirit:name>
@@ -585,7 +585,7 @@
         </spirit:wire>
       </spirit:port>
       <spirit:port>
-        <spirit:name>clk_aux_p_i</spirit:name>
+        <spirit:name>gtp_dedicated_clk_p_i</spirit:name>
         <spirit:wire>
           <spirit:direction>in</spirit:direction>
           <spirit:wireTypeDefs>
@@ -598,7 +598,7 @@
         </spirit:wire>
       </spirit:port>
       <spirit:port>
-        <spirit:name>clk_aux_n_i</spirit:name>
+        <spirit:name>gtp_dedicated_clk_n_i</spirit:name>
         <spirit:wire>
           <spirit:direction>in</spirit:direction>
           <spirit:wireTypeDefs>
@@ -611,9 +611,9 @@
         </spirit:wire>
       </spirit:port>
       <spirit:port>
-        <spirit:name>gtp_dedicated_clk_p_i</spirit:name>
+        <spirit:name>clk_dmtd_b</spirit:name>
         <spirit:wire>
-          <spirit:direction>in</spirit:direction>
+          <spirit:direction>inout</spirit:direction>
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic</spirit:typeName>
@@ -624,9 +624,22 @@
         </spirit:wire>
       </spirit:port>
       <spirit:port>
-        <spirit:name>gtp_dedicated_clk_n_i</spirit:name>
+        <spirit:name>clk_ref_b</spirit:name>
         <spirit:wire>
-          <spirit:direction>in</spirit:direction>
+          <spirit:direction>inout</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clk_rx_rbclk_b</spirit:name>
+        <spirit:wire>
+          <spirit:direction>inout</spirit:direction>
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic</spirit:typeName>
@@ -1400,589 +1413,591 @@
     <spirit:fileSet>
       <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd</spirit:name>
+        <spirit:name>syn/constraints/timing_constraints.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd</spirit:name>
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+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd</spirit:name>
-        <spirit:fileType>vhdlSource</spirit:fileType>
-      </spirit:file>
-      <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
@@ -1990,35 +2005,39 @@
         <spirit:userFileType>xci</spirit:userFileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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@@ -2033,609 +2052,605 @@
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       <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
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+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
@@ -2643,15 +2658,19 @@
         <spirit:userFileType>xci</spirit:userFileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd</spirit:name>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../../ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
     </spirit:fileSet>
@@ -2679,7 +2698,7 @@
   <spirit:vendorExtensions>
     <xilinx:coreExtensions>
       <xilinx:displayName>wrc_1p_kintex7</xilinx:displayName>
-      <xilinx:coreRevision>13</xilinx:coreRevision>
+      <xilinx:coreRevision>15</xilinx:coreRevision>
       <xilinx:tags>
         <xilinx:tag xilinx:name="user.org:user:wrc_1p_kintex7:1.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/sevensols/wrc-2p</xilinx:tag>
         <xilinx:tag xilinx:name="CERN:user:wrc_1p_kintex7:1.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/sevensols/wrc-2p</xilinx:tag>
@@ -2697,6 +2716,8 @@
         <xilinx:tag xilinx:name="CERN:wrc:wrc_1p_kintex7:2.2_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/sevensols/wrc-2p</xilinx:tag>
         <xilinx:tag xilinx:name="CERN:wrc:wrc_1p_kintex7:2.3_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/sevensols/wrc-2p</xilinx:tag>
         <xilinx:tag xilinx:name="CERN:wrc:wrc_1p_kintex7:2.3.1_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/sevensols/wrc-2p</xilinx:tag>
+        <xilinx:tag xilinx:name="CERN:wrc:wrc_1p_kintex7:3.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/sevensols/wrc-2p</xilinx:tag>
+        <xilinx:tag xilinx:name="CERN:wrc:wrc_1p_kintex7:3.1.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/sevensols/wrc-2p</xilinx:tag>
       </xilinx:tags>
       <xilinx:configElementInfos>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valueSource="constant"/>
@@ -2727,8 +2748,8 @@
     <xilinx:packagingInfo>
       <xilinx:xilinxVersion>2016.2</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="ae8f394d"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b032e087"/>
-      <xilinx:checksum xilinx:scope="ports" xilinx:value="499a3f98"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d6a6a5db"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="073d0e30"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="6e43cfbd"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="240f2302"/>
     </xilinx:packagingInfo>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xml
index 7ea518ed48f2dd4b7a5cb90fdfd346c04c4c926b..cfa2451bda891f1b0f37cdb4071f41df3d310bf6 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xml
@@ -607,7 +607,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:18 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:13 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -638,7 +638,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:18 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:13 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -669,7 +669,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:18 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:13 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -700,7 +700,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:18 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:13 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xml
index 37c1215a32cb2d1a2567b7e8b00a17646eec5bb6..b114d8fa694cd7a1d2e6885b93ba75d695876cfe 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xml
@@ -1213,7 +1213,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:17 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:13 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1244,7 +1244,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:17 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:13 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1274,7 +1274,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:17 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:13 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1305,7 +1305,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:17 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:13 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xbar_0/system_design_xbar_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xbar_0/system_design_xbar_0.xml
index ed6b6403b743437650c3be6579aec8c2d2d267f6..0122d55275aba0aa9ad62f9d04ab680c775dd20a 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xbar_0/system_design_xbar_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xbar_0/system_design_xbar_0.xml
@@ -18573,7 +18573,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -18603,7 +18603,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -18634,7 +18634,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -18680,7 +18680,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -18711,7 +18711,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:09 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xml
index 5700c07b14b11e0d899c7e82716a3132872315f1..0f99b32a6b38aaa06d00ed29e21c71aea43c5725 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xml
@@ -17,7 +17,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:18 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:14 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -48,7 +48,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:18 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:14 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -79,7 +79,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:18 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:14 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -110,7 +110,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:18 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:14 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xml
index dc4c842b5cd0fb3b45a8b41468d52278742c27a9..0c7a021f2807d0ed16734f3c1b5a5389f5108132 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xml
@@ -17,7 +17,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:10 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -48,7 +48,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:10 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -79,7 +79,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:10 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -110,7 +110,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:10 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconstant_6_0/system_design_xlconstant_6_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconstant_6_0/system_design_xlconstant_6_0.xml
index 426b8c42ddf346e50fedee3a0e6501934f8fccc1..ba1a7963ea6091edc162e4c69d3a9dc04d135be4 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconstant_6_0/system_design_xlconstant_6_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconstant_6_0/system_design_xlconstant_6_0.xml
@@ -17,7 +17,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:10 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -48,7 +48,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:20 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:15 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -79,7 +79,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:14 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:10 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -110,7 +110,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 21 10:10:20 UTC 2017</spirit:value>
+            <spirit:value>Mon Mar 27 10:11:15 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/common/ext_pll_10_to_62_compensated.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/gen7s_cores_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/gen7s-cores/modules/pll_ad9516_spi/PLL_SPI_ctrl_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/common/gencores_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/common/gencores_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/genrams/xilinx/lm32_dpram_sameclock.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
similarity index 100%
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diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
similarity index 100%
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diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd
similarity index 100%
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diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/jtag_tap.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/artix7/lm32_multiplier.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
similarity index 100%
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rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
similarity index 100%
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diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
similarity index 100%
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diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/axi4/axis_wbm_bridge.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBuffer.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/shiftRegister.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/shiftRegister.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/main_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/hdl_lib/modules/main_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
similarity index 93%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
index 3c85238fbd0451d3e9a279a4efb98c075a431b27..fb2e12e9d4d019fd727177684ccdb7ae1383d477 100755
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
@@ -93,9 +93,18 @@ architecture behavioral of gtp_bitslide is
     end if;
   end f_eval_pause_tics;
 
+  function f_max_bts return integer is
+  begin
+    if(g_target = "spartan6") then
+      return 10;
+    else
+      return 20;
+    end if;
+  end f_max_bts;
 
   constant c_pause_tics            : integer := f_eval_pause_tics;
   constant c_sync_detect_threshold : integer := f_eval_sync_detect_threshold;
+  constant c_max_bts               : integer := f_max_bts;
 
 
   type t_bitslide_fsm_state is (S_SYNC_LOST, S_STABILIZE, S_SLIDE, S_PAUSE, S_GOT_SYNC, S_RESET_CDR);
@@ -162,7 +171,11 @@ begin  -- behavioral
           end if;
 
         when S_SLIDE =>
-          cur_slide      <= cur_slide + 1;
+          if (cur_slide < c_max_bts-1) then
+            cur_slide <= cur_slide + 1;
+          else
+            cur_slide <= (others=>'0');
+          end if;
           gtp_rx_slide_o <= '1';
           counter        <= (others => '0');
 
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/lm32_sw/wrc.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/lm32_sw/wrc.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/wr_fabric_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/wr_fabric_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/fabric/xwrf_mux.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/fabric/xwrf_mux.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_phase_meas.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_phase_meas.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/timing/dmtd_with_deglitcher.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/timing/dmtd_with_deglitcher.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_dacs/spec_serial_dac_arb.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_dacs/spec_serial_dac_arb.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_eca/eca_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_eca/eca_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/endpoint_private_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/endpoint_private_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_1000basex_pcs.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_1000basex_pcs.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_autonegotiation.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_autonegotiation.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_crc32_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_crc32_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_leds_controller.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_leds_controller.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_packet_filter.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_packet_filter.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_registers_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_registers_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rtu_header_extract.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rtu_header_extract.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_buffer.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_buffer.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_crc_size_check.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_crc_size_check.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_early_address_match.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_early_address_match.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_oob_insert.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_oob_insert.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_path.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_path.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_vlan_unit.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_vlan_unit.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_rx_wb_master.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_rx_wb_master.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_sync_detect_16bit.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_sync_detect_16bit.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_timestamping_unit.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_timestamping_unit.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_ts_counter.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_ts_counter.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_crc_inserter.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_crc_inserter.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_header_processor.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_header_processor.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_packet_injection.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_packet_injection.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_path.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_path.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_tx_vlan_unit.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_tx_vlan_unit.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/ep_wishbone_controller.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/ep_wishbone_controller.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/wr_endpoint.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/wr_endpoint.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_endpoint/xwr_endpoint.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_endpoint/xwr_endpoint.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wb_slave.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wb_slave.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/wr_mini_nic.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/wr_mini_nic.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_mini_nic/xwr_mini_nic.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_mini_nic/xwr_mini_nic.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/pps_gen_wb.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/pps_gen_wb.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/wr_pps_gen.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/wr_pps_gen.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_pps_gen/xwr_pps_gen.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_pps_gen/xwr_pps_gen.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/softpll_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/softpll_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_aligner.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_aligner.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wb_slave.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wb_slave.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/wr_softpll_ng.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/wr_softpll_ng.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_softpll_ng/xwr_softpll_ng.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_softpll_ng/xwr_softpll_ng.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tbi_phy/disparity_gen_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tbi_phy/disparity_gen_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wr_tlu/wb_cores_pkg_gsi.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wr_tlu/wb_cores_pkg_gsi.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core/wr_core.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core/wr_core.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_periph.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_periph.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrc_syscon_wb.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrc_syscon_wb.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/wrcore_2p_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/wrcore_2p_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/modules/wrc_core_2p/xwr_syscon_wb.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/modules/wrc_core_2p/xwr_syscon_wb.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_sync_pulse.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtp2p_wizard_tx_manual_phase_align.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_channel_gt.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_gtrxreset_seq.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/gtpe_sync_block.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/whiterabbit_gtpe_2pchannel_wrapper_gt.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/gtp_serie7_wrapper/wr_gtp_phy_artix7.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/platform/xilinx/wr_gtp_phy_artix7/wr_a7_gtps_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd
similarity index 92%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd
index 8169e7685a953e902a49af2b14d8fcbca13f8e9d..6b77e45a17bb65635b2ae385d65720b3eea45c71 100755
--- a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern/wrc_1p_kintex7_v2_3_1/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/cern/wrc_1p_kintex7_v3_1_0/top/wrc-1p-kintex7/wrc_1p_kintex7_top.vhd
@@ -27,26 +27,23 @@ use work.gen7s_cores_pkg.all;
 entity wrc_1p_kintex7 is
   generic
     (
-      TAR_ADDR_WDTH : integer := 13     -- not used for this project
+      TAR_ADDR_WDTH : integer := 13          -- not used for this project
       );
   port
     (
-      --Clocks
-      clk_20m_vcxo_i : in std_logic;    -- 25MHz VCXO clock
-
-      clk_aux_p_i : in std_logic;       -- 125 PLL auxiliary clock.
-      clk_aux_n_i : in std_logic;
-
-      gtp_dedicated_clk_p_i : in std_logic;  -- Dedicated clock for Xilinx GTP transceiver
+      -------------------------------------------------------------------------
+      -- clocks
+      -------------------------------------------------------------------------      
+      clk_20m_vcxo_i        : in std_logic;  -- 25MHz VCXO clock
+      gtp_dedicated_clk_p_i : in std_logic;  -- GTP transceiver & internal 125
+                                             -- MHz PLL clock
       gtp_dedicated_clk_n_i : in std_logic;
 
-      --Dedicated CLK to configure the AD9516 PLL (100MHz by default)
-      -- clk_100mhz_i : in std_logic;
-      -- clk_100mhz_n_i : in std_logic;
-
-      --SERDES CLK. AD9516 OUT 5.
---      clk_serdes_p_i : in std_logic;
---      clk_serdes_n_i : in std_logic;
+      -- FASEC clock outputs for debugging
+      -- inouts to match existing fasec_hwtest module
+      clk_dmtd_b     : inout std_logic;
+      clk_ref_b      : inout std_logic;
+      clk_rx_rbclk_b : inout std_logic;
 
       -- Front panel LEDs
       -- GTP0
@@ -55,12 +52,6 @@ entity wrc_1p_kintex7 is
       gtp0_link_led_o     : out std_logic;
       gtp0_wrmode_led_o   : out std_logic;  -- Not used
 
-      -- GTP1
-      -- gtp1_activity_led_o : out std_logic;
-      -- gtp1_synced_led_o   : out std_logic;  -- Not used
-      -- gtp1_link_led_o     : out std_logic;
-      -- gtp1_wrmode_led_o   : out std_logic;  -- Not used
-
       -- DAC Signals
       dac_sclk_o  : out std_logic;
       dac_din_o   : out std_logic;
@@ -154,8 +145,8 @@ entity wrc_1p_kintex7 is
       -- Axi Slave Bus Interface S00_AXI
       ------------------------------------------
       -- aclk provided by this IP, wire to master!
-      axi_int_o       : out   std_logic;  -- axi interrupt signal
-      s00_axi_aclk_o  : out  std_logic;
+      axi_int_o       : out std_logic;  -- axi interrupt signal
+      s00_axi_aclk_o  : out std_logic;
       s00_axi_aresetn : in  std_logic;
       s00_axi_awaddr  : in  std_logic_vector(c_wishbone_address_width-1 downto 0);
       s00_axi_awprot  : in  std_logic_vector(2 downto 0);
@@ -229,10 +220,8 @@ architecture rtl of wrc_1p_kintex7 is
 
   -- Dedicated clock for GTP transceiver
   --GTP dedicated clock.
-  signal gtp_dedicated_clk : std_logic;
-
-  -- Reference clock disciplined by WR. 62.5 MHz
-  signal wr_ref_clk : std_logic;
+  signal clk_gtx      : std_logic;
+  signal clk_125m_ref : std_logic;
 
   signal pllout_clk_sys     : std_logic;
   signal pllout_clk_dmtd    : std_logic;
@@ -240,12 +229,11 @@ architecture rtl of wrc_1p_kintex7 is
   signal pllout_clk_fb_dmtd : std_logic;
 
   signal clk_20m_vcxo_buf : std_logic;
-  signal clk_aux          : std_logic;
   signal clk_sys          : std_logic;
   signal clk_dmtd         : std_logic;
+  signal clk_125m_pllref  : std_logic;
 
-  signal dac_rst_n : std_logic;
-
+  signal dac_rst_n  : std_logic;
   signal wrc_scl_o  : std_logic;
   signal wrc_scl_i  : std_logic;
   signal wrc_sda_o  : std_logic;
@@ -337,11 +325,14 @@ architecture rtl of wrc_1p_kintex7 is
   signal phy_rdy          : std_logic;
 
 begin
+  -- FASEC clock outputs for debugging
+  clk_dmtd_b     <= clk_dmtd;           --62,5 MHz, from 20 MHz
+  clk_ref_b      <= clk_125m_ref;       --125 MHz, GTP tx clock
+  clk_rx_rbclk_b <= phy_rx_rbclk;       -- GTP rx clock
 
   -- PLL stuff
   --PLL_BASE(S6) ---> MMCME2_ADV(A7)
   -- 125 MHz -> 62,5 MHz. Generate the sys clk
-
   cmp_sys_clk_pll : MMCME2_ADV
     generic map
     (BANDWIDTH            => "OPTIMIZED",
@@ -377,7 +368,7 @@ begin
      CLKOUT6      => open,
      -- Input clock control
      CLKFBIN      => pllout_clk_fb_aux,
-     CLKIN1       => clk_aux,
+     CLKIN1       => clk_125m_pllref,
      CLKIN2       => '0',
      -- Tied to always select the primary input clock
      CLKINSEL     => '1',
@@ -491,37 +482,18 @@ begin
       O => clk_20m_vcxo_buf,
       I => clk_20m_vcxo_i);
 
-  cmp_auxclk_buf : IBUFGDS
-    generic map (
-      DIFF_TERM    => false,            -- Differential Termination
-      IBUF_LOW_PWR => true,  -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-      IOSTANDARD   => "DEFAULT")
-    port map (
-      O  => clk_aux,                    -- Buffer output
-      I  => clk_aux_p_i,  -- Diff_p buffer input (connect directly to top-level port)
-      IB => clk_aux_n_i  -- Diff_n buffer input (connect directly to top-level port)
-      );
-
---------------------------------------------------------------------------------------------------------
-  -- The SERDES CLOCK is used as WR CLK (62.5MHz)
---   cmp_pllserdes_buf : IBUFGDS
---   generic map (
---     DIFF_TERM    => false,      -- Differential Termination
---     IBUF_LOW_PWR => true,      -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
---     IOSTANDARD   => "DEFAULT")
---   port map (
---     O  => open,     -- Buffer output
---     I  => clk_serdes_p_i,  -- Diff_p buffer input (connect directly to top-level port)
---     IB => clk_serdes_n_i   -- Diff_n buffer input (connect directly to top-level port)
---     );
+  cmp_clk_125m_pllref_buf : BUFG
+    port map(
+      O => clk_125m_pllref,
+      I => clk_gtx);
 
   -----------------------------------------------------------------------------
   -- The infamous registering process to ensure the PPS & 10 MHz stability strikes again.
   -----------------------------------------------------------------------------
 
-  p_latch_pps : process(wr_ref_clk)
+  p_latch_pps : process(clk_125m_ref)
   begin
-    if rising_edge(wr_ref_clk) then
+    if rising_edge(clk_125m_ref) then
       pps_o <= pps;
     end if;
   end process;
@@ -530,8 +502,12 @@ begin
   -- Dedicated clocks for GTP.
   ------------------------------------------------------------------------------
   cmp_gtp_dedicated_clk : IBUFDS_GTE2
+    generic map(
+      CLKCM_CFG    => true,
+      CLKRCV_TRST  => true,
+      CLKSWING_CFG => "11")
     port map (
-      O     => gtp_dedicated_clk,
+      O     => clk_gtx,
       ODIV2 => open,
       CEB   => '0',
       I     => gtp_dedicated_clk_p_i,
@@ -626,7 +602,7 @@ begin
     port map (
       clk_sys_i            => clk_sys,
       clk_dmtd_i           => clk_dmtd,
-      clk_ref_i            => wr_ref_clk,
+      clk_ref_i            => clk_125m_ref,
       clk_aux_i            => (others => '0'),
       clk_ext_i            => s_ext_clk,
       rst_n_i              => local_reset_n,
@@ -642,7 +618,7 @@ begin
       dac_dpll_load_p1_o => dac_dpll_load_p1,
       dac_dpll_data_o    => dac_dpll_data,
 
-      phy_ref_clk_i        => wr_ref_clk,
+      phy_ref_clk_i        => clk_125m_ref,
       phy_tx_data_o        => phy_tx_data,
       phy_tx_k_o           => phy_tx_k,
       phy_tx_disparity_i   => phy_tx_disparity,
@@ -874,7 +850,7 @@ begin
     generic map(
       g_simulation => 0)
     port map(
-      clk_gtx_i      => gtp_dedicated_clk,
+      clk_gtx_i      => clk_gtx,
       tx_data_i      => phy_tx_data,
       tx_k_i         => phy_tx_k,
       tx_disparity_o => phy_tx_disparity,
@@ -892,7 +868,7 @@ begin
       pad_rxn_i => gtp0_rxn_i,
       pad_rxp_i => gtp0_rxp_i,
 
-      tx_out_clk_o  => wr_ref_clk,
+      tx_out_clk_o  => clk_125m_ref,
       tx_locked_o   => open,
       tx_prbs_sel_i => phy_prbs_sel,
       rdy_o         => phy_rdy);
@@ -1003,10 +979,10 @@ begin
   s00_axi_aclk_o <= clk_sys;
   u_axis_wbm_bridge : axis_wbm_bridge
     generic map (
-      g_AXI_AWIDTH => c_wishbone_address_width,
-      g_WB_AWIDTH  => c_wishbone_address_width,
-      g_AXI_DWIDTH => c_wishbone_data_width,
-      g_WB_DWIDTH  => c_wishbone_data_width,
+      g_AXI_AWIDTH  => c_wishbone_address_width,
+      g_WB_AWIDTH   => c_wishbone_address_width,
+      g_AXI_DWIDTH  => c_wishbone_data_width,
+      g_WB_DWIDTH   => c_wishbone_data_width,
       g_WB_BYTEADDR => false)
     port map (
       wb_clk_o      => open,
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
similarity index 97%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
index 5238245800aa8873782d748a4b580390154b5c12..b3561fa4e4d364edef73d60b8e3001b41ee88e6b 100755
--- a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
@@ -6,7 +6,7 @@
 -- Author     : Pieter Van Trappen  <pvantrap@cern.ch>
 -- Company    : CERN
 -- Created    : 2016-11-22
--- Last update: 2017-03-21
+-- Last update: 2017-03-27
 -- Platform   : 
 -- Standard   : VHDL'93/02
 -------------------------------------------------------------------------------
@@ -81,6 +81,7 @@ architecture rtl of general_fmc is
   -- EDA-03287 constants
   constant c_COMP            : positive := 20;  -- 20 comparators on EDA-03287
   constant c_DOUTS           : positive := 8;  -- 8 outputs
+  constant c_DOUTSGP : positive := 4; -- first 4 outputs will be linked to GP signals (for white rabbit debugging)
   constant c_OUTFBD          : positive := 4;  -- of which 4 with feedback
   constant c_NODAC           : positive := 5;
   constant c_NOCHANNELS      : positive := 4;
@@ -243,6 +244,11 @@ begin
         );
   end generate gen_spi;
 
+  -- for white rabbit debugging, link some FMC outputs directly to GP inputs
+  gen_clkouts : if g_FMC = "EDA-03287" generate
+    s_diffouts_o(c_DOUTSGP-1 downto 0) <= FMC_GP3_b & FMC_GP2_b & FMC_GP1_b & FMC_GP0_b;
+  end generate gen_clkouts;
+  
   p_fmc_03287_io : process(clk_i)
     variable v_cmp  : std_logic_vector(c_COMP-1 downto 0);
     variable v_dout : std_logic_vector(c_DOUTS-1 downto 0);
@@ -251,7 +257,7 @@ begin
     if g_FMC = "EDA-03287" and rising_edge(clk_i) then
       -- in/outputs
       data_o(1)                        <= resize(unsigned(v_fbd(c_OUTFBD-1 downto 0)), data_o(1)'length);
-      s_diffouts_o(c_DOUTS-1 downto 0) <= v_dout(c_DOUTS-1 downto 0);
+      s_diffouts_o(c_DOUTS-1 downto c_DOUTSGP) <= v_dout(c_DOUTS-1 downto c_DOUTSGP);
       -- using the variables to clock-in/out data
       v_dout(c_DOUTS-1 downto 0)       := std_logic_vector(data_rw_i(2)(c_DOUTS-1 downto 0));
       v_fbd                            := FMC_LA_P_b(31) & FMC_LA_N_b(31) & FMC_LA_P_b(32) & FMC_LA_N_b(32);
@@ -263,7 +269,7 @@ begin
   --=============================================================================
   -- EDA-02327: FMC user lines - clock in for AXI register read by Zynq PS
   --=============================================================================  
-  p_i2c_fmc_02327 : process(FMC_GP0_b, FMC_GP1_b, FMC_LA_P_b(2), FMC_LA_N_b(2))
+  p_i2c_fmc_02327 : process(FMC_LA_P_b(2), FMC_LA_N_b(2))
   begin
     if g_FMC = "EDA-02327" then
       FMC_LA_P_b(2) <= 'Z';             -- scl_vadj, disconnect in xdc
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
similarity index 99%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
index 58a6a224131005b04f97a58454ad8c51f1e973a2..8b3dd7d9357aa89331fb39c12c813a331d9708ea 100755
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
@@ -277,8 +277,8 @@ begin
   s_data(c_FASEC_BASE+1) <= resize(unsigned(s_ins), g_S00_AXI_DATA_WIDTH);
   s_data(c_FASEC_BASE+2) <= resize(unsigned(gem_status_vector_i), g_S00_AXI_DATA_WIDTH);
   -- s_data(c_FASEC_BASE+3).data used in p_fasec_dio
-  s_data(c_FASEC_BASE+6) <= x"58D43193";  -- tcl-script will put unix build time
-  s_data(c_FASEC_BASE+7) <= x"30e4b1a2";  -- tcl-script will put git commit id
+  s_data(c_FASEC_BASE+6) <= x"DEADBEE1";  -- tcl-script will put unix build time
+  s_data(c_FASEC_BASE+7) <= x"DEADBEE2";  -- tcl-script will put git commit id
   -- copy in rw data, 'for generate' only possible with constants!
   gen_data_readwrite : for i in 0 to c_MEMMAX-1 generate
     gen_fasec : if c_FASECMEM(i).ro = '0' generate
@@ -435,4 +435,3 @@ begin
       S_AXI_RVALID  => s00_axi_rvalid,
       S_AXI_RREADY  => s00_axi_rready);
 end rtl;
-
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_0_1/ip_cores/hdl_lib/modules/main_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v
deleted file mode 100755
index f05db4ace3584b676b590940188c0b33e30b6b3c..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v
+++ /dev/null
@@ -1,883 +0,0 @@
-// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
-// --
-// -- This file contains confidential and proprietary information
-// -- of Xilinx, Inc. and is protected under U.S. and 
-// -- international copyright and other intellectual property
-// -- laws.
-// --
-// -- DISCLAIMER
-// -- This disclaimer is not a license and does not grant any
-// -- rights to the materials distributed herewith. Except as
-// -- otherwise provided in a valid license issued to you by
-// -- Xilinx, and to the maximum extent permitted by applicable
-// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// -- (2) Xilinx shall not be liable (whether in contract or tort,
-// -- including negligence, or under any other theory of
-// -- liability) for any loss or damage of any kind or nature
-// -- related to, arising under or in connection with these
-// -- materials, including for any direct, or any indirect,
-// -- special, incidental, or consequential loss or damage
-// -- (including loss of data, profits, goodwill, or any type of
-// -- loss or damage suffered as a result of any action brought
-// -- by a third party) even if such damage or loss was
-// -- reasonably foreseeable or Xilinx had been advised of the
-// -- possibility of the same.
-// --
-// -- CRITICAL APPLICATIONS
-// -- Xilinx products are not designed or intended to be fail-
-// -- safe, or for use in any application requiring fail-safe
-// -- performance, such as life-support or safety devices or
-// -- systems, Class III medical devices, nuclear facilities,
-// -- applications related to the deployment of airbags, or any
-// -- other applications that could lead to death, personal
-// -- injury, or severe property or environmental damage
-// -- (individually and collectively, "Critical
-// -- Applications"). Customer assumes the sole risk and
-// -- liability of any use of Xilinx products in Critical
-// -- Applications, subject only to applicable laws and
-// -- regulations governing limitations on product liability.
-// --
-// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// -- PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-//
-// Description: Address AXI3 Slave Converter
-//
-//
-// Verilog-standard:  Verilog 2001
-//--------------------------------------------------------------------------
-//
-// Structure:
-//   a_axi3_conv
-//     axic_fifo
-//
-//--------------------------------------------------------------------------
-`timescale 1ps/1ps
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_a_axi3_conv #
-  (
-   parameter C_FAMILY                            = "none",
-   parameter integer C_AXI_ID_WIDTH              = 1,
-   parameter integer C_AXI_ADDR_WIDTH            = 32,
-   parameter integer C_AXI_DATA_WIDTH            = 32,
-   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
-   parameter integer C_AXI_AUSER_WIDTH           = 1,
-   parameter integer C_AXI_CHANNEL                    = 0,
-                       // 0 = AXI AW Channel.
-                       // 1 = AXI AR Channel.
-   parameter integer C_SUPPORT_SPLITTING              = 1,
-                       // Implement transaction splitting logic.
-                       // Disabled whan all connected masters are AXI3 and have same or narrower data width.
-   parameter integer C_SUPPORT_BURSTS                 = 1,
-                       // Disabled when all connected masters are AxiLite,
-                       //   allowing logic to be simplified.
-   parameter integer C_SINGLE_THREAD                  = 1
-                       // 0 = Ignore ID when propagating transactions (assume all responses are in order).
-                       // 1 = Enforce single-threading (one ID at a time) when any outstanding or 
-                       //     requested transaction requires splitting.
-                       //     While no split is ongoing any new non-split transaction will pass immediately regardless
-                       //     off ID.
-                       //     A split transaction will stall if there are multiple ID (non-split) transactions
-                       //     ongoing, once it has been forwarded only transactions with the same ID is allowed
-                       //     (split or not) until all ongoing split transactios has been completed.
-   )
-  (
-   // System Signals
-   input wire ACLK,
-   input wire ARESET,
-
-   // Command Interface (W/R)
-   output wire                              cmd_valid,
-   output wire                              cmd_split,
-   output wire [C_AXI_ID_WIDTH-1:0]         cmd_id,
-   output wire [4-1:0]                      cmd_length,
-   input  wire                              cmd_ready,
-   
-   // Command Interface (B)
-   output wire                              cmd_b_valid,
-   output wire                              cmd_b_split,
-   output wire [4-1:0]                      cmd_b_repeat,
-   input  wire                              cmd_b_ready,
-   
-   // Slave Interface Write Address Ports
-   input  wire [C_AXI_ID_WIDTH-1:0]     S_AXI_AID,
-   input  wire [C_AXI_ADDR_WIDTH-1:0]   S_AXI_AADDR,
-   input  wire [8-1:0]                  S_AXI_ALEN,
-   input  wire [3-1:0]                  S_AXI_ASIZE,
-   input  wire [2-1:0]                  S_AXI_ABURST,
-   input  wire [1-1:0]                  S_AXI_ALOCK,
-   input  wire [4-1:0]                  S_AXI_ACACHE,
-   input  wire [3-1:0]                  S_AXI_APROT,
-   input  wire [4-1:0]                  S_AXI_AQOS,
-   input  wire [C_AXI_AUSER_WIDTH-1:0]  S_AXI_AUSER,
-   input  wire                          S_AXI_AVALID,
-   output wire                          S_AXI_AREADY,
-
-   // Master Interface Write Address Port
-   output wire [C_AXI_ID_WIDTH-1:0]     M_AXI_AID,
-   output wire [C_AXI_ADDR_WIDTH-1:0]   M_AXI_AADDR,
-   output wire [4-1:0]                  M_AXI_ALEN,
-   output wire [3-1:0]                  M_AXI_ASIZE,
-   output wire [2-1:0]                  M_AXI_ABURST,
-   output wire [2-1:0]                  M_AXI_ALOCK,
-   output wire [4-1:0]                  M_AXI_ACACHE,
-   output wire [3-1:0]                  M_AXI_APROT,
-   output wire [4-1:0]                  M_AXI_AQOS,
-   output wire [C_AXI_AUSER_WIDTH-1:0]  M_AXI_AUSER,
-   output wire                          M_AXI_AVALID,
-   input  wire                          M_AXI_AREADY
-   );
-
-   
-  /////////////////////////////////////////////////////////////////////////////
-  // Variables for generating parameter controlled instances.
-  /////////////////////////////////////////////////////////////////////////////
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Local params
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Constants for burst types.
-  localparam [2-1:0] C_FIX_BURST         = 2'b00;
-  localparam [2-1:0] C_INCR_BURST        = 2'b01;
-  localparam [2-1:0] C_WRAP_BURST        = 2'b10;
-  
-  // Depth for command FIFO.
-  localparam integer C_FIFO_DEPTH_LOG    = 5;
-  
-  // Constants used to generate size mask.
-  localparam [C_AXI_ADDR_WIDTH+8-1:0] C_SIZE_MASK = {{C_AXI_ADDR_WIDTH{1'b1}}, 8'b0000_0000};
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Functions
-  /////////////////////////////////////////////////////////////////////////////
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Internal signals
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Access decoding related signals.
-  wire                                access_is_incr;
-  wire [4-1:0]                        num_transactions;
-  wire                                incr_need_to_split;
-  reg  [C_AXI_ADDR_WIDTH-1:0]         next_mi_addr;
-  reg                                 split_ongoing;
-  reg  [4-1:0]                        pushed_commands;
-  reg  [16-1:0]                       addr_step;
-  reg  [16-1:0]                       first_step;
-  wire [8-1:0]                        first_beats;
-  reg  [C_AXI_ADDR_WIDTH-1:0]         size_mask;
-  
-  // Access decoding related signals for internal pipestage.
-  reg                                 access_is_incr_q;
-  reg                                 incr_need_to_split_q;
-  wire                                need_to_split_q;
-  reg  [4-1:0]                        num_transactions_q;
-  reg  [16-1:0]                       addr_step_q;
-  reg  [16-1:0]                       first_step_q;
-  reg  [C_AXI_ADDR_WIDTH-1:0]         size_mask_q;
-  
-  // Command buffer help signals.
-  reg  [C_FIFO_DEPTH_LOG:0]           cmd_depth;
-  reg                                 cmd_empty;
-  reg  [C_AXI_ID_WIDTH-1:0]           queue_id;
-  wire                                id_match;
-  wire                                cmd_id_check;
-  wire                                s_ready;
-  wire                                cmd_full;
-  wire                                allow_this_cmd;
-  wire                                allow_new_cmd;
-  wire                                cmd_push;
-  reg                                 cmd_push_block;
-  reg  [C_FIFO_DEPTH_LOG:0]           cmd_b_depth;
-  reg                                 cmd_b_empty;
-  wire                                cmd_b_full;
-  wire                                cmd_b_push;
-  reg                                 cmd_b_push_block;
-  wire                                pushed_new_cmd;
-  wire                                last_incr_split;
-  wire                                last_split;
-  wire                                first_split;
-  wire                                no_cmd;
-  wire                                allow_split_cmd;
-  wire                                almost_empty;
-  wire                                no_b_cmd;
-  wire                                allow_non_split_cmd;
-  wire                                almost_b_empty;
-  reg                                 multiple_id_non_split;
-  reg                                 split_in_progress;
-  
-  // Internal Command Interface signals (W/R).
-  wire                                cmd_split_i;
-  wire [C_AXI_ID_WIDTH-1:0]           cmd_id_i;
-  reg  [4-1:0]                        cmd_length_i;
-  
-  // Internal Command Interface signals (B).
-  wire                                cmd_b_split_i;
-  wire [4-1:0]                        cmd_b_repeat_i;
-  
-  // Throttling help signals.
-  wire                                mi_stalling;
-  reg                                 command_ongoing;
-   
-  // Internal SI-side signals.
-  reg  [C_AXI_ID_WIDTH-1:0]           S_AXI_AID_Q;
-  reg  [C_AXI_ADDR_WIDTH-1:0]         S_AXI_AADDR_Q;
-  reg  [8-1:0]                        S_AXI_ALEN_Q;
-  reg  [3-1:0]                        S_AXI_ASIZE_Q;
-  reg  [2-1:0]                        S_AXI_ABURST_Q;
-  reg  [2-1:0]                        S_AXI_ALOCK_Q;
-  reg  [4-1:0]                        S_AXI_ACACHE_Q;
-  reg  [3-1:0]                        S_AXI_APROT_Q;
-  reg  [4-1:0]                        S_AXI_AQOS_Q;
-  reg  [C_AXI_AUSER_WIDTH-1:0]        S_AXI_AUSER_Q;
-  reg                                 S_AXI_AREADY_I;
-  
-  // Internal MI-side signals.
-  wire [C_AXI_ID_WIDTH-1:0]           M_AXI_AID_I;
-  reg  [C_AXI_ADDR_WIDTH-1:0]         M_AXI_AADDR_I;
-  reg  [8-1:0]                        M_AXI_ALEN_I;
-  wire [3-1:0]                        M_AXI_ASIZE_I;
-  wire [2-1:0]                        M_AXI_ABURST_I;
-  reg  [2-1:0]                        M_AXI_ALOCK_I;
-  wire [4-1:0]                        M_AXI_ACACHE_I;
-  wire [3-1:0]                        M_AXI_APROT_I;
-  wire [4-1:0]                        M_AXI_AQOS_I;
-  wire [C_AXI_AUSER_WIDTH-1:0]        M_AXI_AUSER_I;
-  wire                                M_AXI_AVALID_I;
-  wire                                M_AXI_AREADY_I;
-  
-  reg [1:0] areset_d; // Reset delay register
-  always @(posedge ACLK) begin
-    areset_d <= {areset_d[0], ARESET};
-  end
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Capture SI-Side signals.
-  //
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Register SI-Side signals.
-  always @ (posedge ACLK) begin
-    if ( ARESET ) begin
-      S_AXI_AID_Q     <= {C_AXI_ID_WIDTH{1'b0}};
-      S_AXI_AADDR_Q   <= {C_AXI_ADDR_WIDTH{1'b0}};
-      S_AXI_ALEN_Q    <= 8'b0;
-      S_AXI_ASIZE_Q   <= 3'b0;
-      S_AXI_ABURST_Q  <= 2'b0;
-      S_AXI_ALOCK_Q   <= 2'b0;
-      S_AXI_ACACHE_Q  <= 4'b0;
-      S_AXI_APROT_Q   <= 3'b0;
-      S_AXI_AQOS_Q    <= 4'b0;
-      S_AXI_AUSER_Q   <= {C_AXI_AUSER_WIDTH{1'b0}};
-    end else begin
-      if ( S_AXI_AREADY_I ) begin
-        S_AXI_AID_Q     <= S_AXI_AID;
-        S_AXI_AADDR_Q   <= S_AXI_AADDR;
-        S_AXI_ALEN_Q    <= S_AXI_ALEN;
-        S_AXI_ASIZE_Q   <= S_AXI_ASIZE;
-        S_AXI_ABURST_Q  <= S_AXI_ABURST;
-        S_AXI_ALOCK_Q   <= S_AXI_ALOCK;
-        S_AXI_ACACHE_Q  <= S_AXI_ACACHE;
-        S_AXI_APROT_Q   <= S_AXI_APROT;
-        S_AXI_AQOS_Q    <= S_AXI_AQOS;
-        S_AXI_AUSER_Q   <= S_AXI_AUSER;
-      end
-    end
-  end
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Decode the Incoming Transaction.
-  // 
-  // Extract transaction type and the number of splits that may be needed.
-  // 
-  // Calculate the step size so that the address for each part of a split can
-  // can be calculated. 
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Transaction burst type.
-  assign access_is_incr   = ( S_AXI_ABURST == C_INCR_BURST );
-  
-  // Get number of transactions for split INCR.
-  assign num_transactions = S_AXI_ALEN[4 +: 4];
-  assign first_beats = {3'b0, S_AXI_ALEN[0 +: 4]} + 7'b01;
-  
-  // Generate address increment of first split transaction.
-  always @ *
-  begin
-    case (S_AXI_ASIZE)
-      3'b000: first_step = first_beats << 0;
-      3'b001: first_step = first_beats << 1;
-      3'b010: first_step = first_beats << 2;
-      3'b011: first_step = first_beats << 3;
-      3'b100: first_step = first_beats << 4;
-      3'b101: first_step = first_beats << 5;
-      3'b110: first_step = first_beats << 6;
-      3'b111: first_step = first_beats << 7;
-    endcase
-  end
-  
-  // Generate address increment for remaining split transactions.
-  always @ *
-  begin
-    case (S_AXI_ASIZE)
-      3'b000: addr_step = 16'h0010;
-      3'b001: addr_step = 16'h0020;
-      3'b010: addr_step = 16'h0040;
-      3'b011: addr_step = 16'h0080;
-      3'b100: addr_step = 16'h0100;
-      3'b101: addr_step = 16'h0200;
-      3'b110: addr_step = 16'h0400;
-      3'b111: addr_step = 16'h0800;
-    endcase
-  end
-  
-  // Generate address mask bits to remove split transaction unalignment.
-  always @ *
-  begin
-    case (S_AXI_ASIZE)
-      3'b000: size_mask = C_SIZE_MASK[8 +: C_AXI_ADDR_WIDTH];
-      3'b001: size_mask = C_SIZE_MASK[7 +: C_AXI_ADDR_WIDTH];
-      3'b010: size_mask = C_SIZE_MASK[6 +: C_AXI_ADDR_WIDTH];
-      3'b011: size_mask = C_SIZE_MASK[5 +: C_AXI_ADDR_WIDTH];
-      3'b100: size_mask = C_SIZE_MASK[4 +: C_AXI_ADDR_WIDTH];
-      3'b101: size_mask = C_SIZE_MASK[3 +: C_AXI_ADDR_WIDTH];
-      3'b110: size_mask = C_SIZE_MASK[2 +: C_AXI_ADDR_WIDTH];
-      3'b111: size_mask = C_SIZE_MASK[1 +: C_AXI_ADDR_WIDTH];
-    endcase
-  end
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Transfer SI-Side signals to internal Pipeline Stage.
-  //
-  /////////////////////////////////////////////////////////////////////////////
-  
-  always @ (posedge ACLK) begin
-    if ( ARESET ) begin
-      access_is_incr_q      <= 1'b0;
-      incr_need_to_split_q  <= 1'b0;
-      num_transactions_q    <= 4'b0;
-      addr_step_q           <= 16'b0;
-      first_step_q           <= 16'b0;
-      size_mask_q           <= {C_AXI_ADDR_WIDTH{1'b0}};
-    end else begin
-      if ( S_AXI_AREADY_I ) begin
-        access_is_incr_q      <= access_is_incr;
-        incr_need_to_split_q  <= incr_need_to_split;
-        num_transactions_q    <= num_transactions;
-        addr_step_q           <= addr_step;
-        first_step_q          <= first_step;
-        size_mask_q           <= size_mask;
-      end
-    end
-  end
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Generate Command Information.
-  // 
-  // Detect if current transation needs to be split, and keep track of all
-  // the generated split transactions.
-  // 
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Detect when INCR must be split.
-  assign incr_need_to_split = access_is_incr & ( num_transactions != 0 ) &
-                              ( C_SUPPORT_SPLITTING == 1 ) &
-                              ( C_SUPPORT_BURSTS == 1 );
-  
-  // Detect when a command has to be split.
-  assign need_to_split_q    = incr_need_to_split_q;
-  
-  // Handle progress of split transactions.
-  always @ (posedge ACLK) begin
-    if ( ARESET ) begin
-      split_ongoing     <= 1'b0;
-    end else begin
-      if ( pushed_new_cmd ) begin
-        split_ongoing     <= need_to_split_q & ~last_split;
-      end
-    end
-  end
-  
-  // Keep track of number of transactions generated.
-  always @ (posedge ACLK) begin
-    if ( ARESET ) begin
-      pushed_commands <= 4'b0;
-    end else begin
-      if ( S_AXI_AREADY_I ) begin
-        pushed_commands <= 4'b0;
-      end else if ( pushed_new_cmd ) begin
-        pushed_commands <= pushed_commands + 4'b1;
-      end
-    end
-  end
-  
-  // Detect last part of a command, split or not.
-  assign last_incr_split    = access_is_incr_q & ( num_transactions_q   == pushed_commands );
-  assign last_split         = last_incr_split | ~access_is_incr_q | 
-                              ( C_SUPPORT_SPLITTING == 0 ) |
-                              ( C_SUPPORT_BURSTS == 0 );
-  assign first_split = (pushed_commands == 4'b0);
-  
-  // Calculate base for next address.
-  always @ (posedge ACLK) begin
-    if ( ARESET ) begin
-      next_mi_addr  = {C_AXI_ADDR_WIDTH{1'b0}};
-    end else if ( pushed_new_cmd ) begin
-      next_mi_addr  = M_AXI_AADDR_I + (first_split ? first_step_q : addr_step_q);
-    end
-  end
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Translating Transaction.
-  // 
-  // Set Split transaction information on all part except last for a transaction 
-  // that needs splitting.
-  // The B Channel will only get one command for a Split transaction and in 
-  // the Split bflag will be set in that case.
-  // 
-  // The AWID is extracted and applied to all commands generated for the current 
-  // incomming SI-Side transaction.
-  // 
-  // The address is increased for each part of a Split transaction, the amount
-  // depends on the siSIZE for the transaction.
-  // 
-  // The length has to be changed for Split transactions. All part except tha 
-  // last one will have 0xF, the last one uses the 4 lsb bits from the SI-side
-  // transaction as length.
-  // 
-  // Non-Split has untouched address and length information.
-  // 
-  // Exclusive access are diasabled for a Split transaction because it is not 
-  // possible to guarantee concistency between all the parts.
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Assign Split signals.
-  assign cmd_split_i        = need_to_split_q & ~last_split;
-  assign cmd_b_split_i      = need_to_split_q & ~last_split;
-  
-  // Copy AW ID to W.
-  assign cmd_id_i           = S_AXI_AID_Q;
-  
-  // Set B Responses to merge.
-  assign cmd_b_repeat_i     = num_transactions_q;
-  
-  // Select new size or remaining size.
-  always @ *
-  begin
-    if ( split_ongoing & access_is_incr_q ) begin
-      M_AXI_AADDR_I = next_mi_addr & size_mask_q;
-    end else begin
-      M_AXI_AADDR_I = S_AXI_AADDR_Q;
-    end
-  end
-  
-  // Generate the base length for each transaction.
-  always @ *
-  begin
-    if ( first_split | ~need_to_split_q ) begin
-      M_AXI_ALEN_I = S_AXI_ALEN_Q[0 +: 4];
-      cmd_length_i = S_AXI_ALEN_Q[0 +: 4];
-    end else begin
-      M_AXI_ALEN_I = 4'hF;
-      cmd_length_i = 4'hF;
-    end
-  end
-  
-  // Kill Exclusive for Split transactions.
-  always @ *
-  begin
-    if ( need_to_split_q ) begin
-      M_AXI_ALOCK_I = 2'b00;
-    end else begin
-      M_AXI_ALOCK_I = {1'b0, S_AXI_ALOCK_Q};
-    end
-  end
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Forward the command to the MI-side interface.
-  // 
-  // It is determined that this is an allowed command/access when there is 
-  // room in the command queue (and it passes ID and Split checks as required).
-  //
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Move SI-side transaction to internal pipe stage.
-  always @ (posedge ACLK) begin
-    if (ARESET) begin
-      command_ongoing <= 1'b0;
-      S_AXI_AREADY_I <= 1'b0;
-    end else begin
-      if (areset_d == 2'b10) begin
-        S_AXI_AREADY_I <= 1'b1;
-      end else begin
-        if ( S_AXI_AVALID & S_AXI_AREADY_I ) begin
-          command_ongoing <= 1'b1;
-          S_AXI_AREADY_I <= 1'b0;
-        end else if ( pushed_new_cmd & last_split ) begin
-          command_ongoing <= 1'b0;
-          S_AXI_AREADY_I <= 1'b1;
-        end 
-      end
-    end
-  end
-  
-  // Generate ready signal.
-  assign S_AXI_AREADY   = S_AXI_AREADY_I;
-  
-  // Only allowed to forward translated command when command queue is ok with it.
-  assign M_AXI_AVALID_I = allow_new_cmd & command_ongoing;
-  
-  // Detect when MI-side is stalling.
-  assign mi_stalling    = M_AXI_AVALID_I & ~M_AXI_AREADY_I;
-                          
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Simple transfer of paramters that doesn't need to be adjusted.
-  // 
-  // ID     - Transaction still recognized with the same ID.
-  // CACHE  - No need to change the chache features. Even if the modyfiable
-  //          bit is overridden (forcefully) there is no need to let downstream
-  //          component beleive it is ok to modify it further.
-  // PROT   - Security level of access is not changed when upsizing.
-  // QOS    - Quality of Service is static 0.
-  // USER   - User bits remains the same.
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-  
-  assign M_AXI_AID_I      = S_AXI_AID_Q;
-  assign M_AXI_ASIZE_I    = S_AXI_ASIZE_Q;
-  assign M_AXI_ABURST_I   = S_AXI_ABURST_Q;
-  assign M_AXI_ACACHE_I   = S_AXI_ACACHE_Q;
-  assign M_AXI_APROT_I    = S_AXI_APROT_Q;
-  assign M_AXI_AQOS_I     = S_AXI_AQOS_Q;
-  assign M_AXI_AUSER_I    = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_AUSER_Q : {C_AXI_AUSER_WIDTH{1'b0}};
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Control command queue to W/R channel.
-  //
-  // Commands can be pushed into the Cmd FIFO even if MI-side is stalling.
-  // A flag is set if MI-side is stalling when Command is pushed to the 
-  // Cmd FIFO. This will prevent multiple push of the same Command as well as
-  // keeping the MI-side Valid signal if the Allow Cmd requirement has been 
-  // updated to disable furter Commands (I.e. it is made sure that the SI-side 
-  // Command has been forwarded to both Cmd FIFO and MI-side).
-  // 
-  // It is allowed to continue pushing new commands as long as
-  // * There is room in the queue(s)
-  // * The ID is the same as previously queued. Since data is not reordered
-  //   for the same ID it is always OK to let them proceed.
-  //   Or, if no split transaction is ongoing any ID can be allowed.
-  //
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Keep track of current ID in queue.
-  always @ (posedge ACLK) begin
-    if (ARESET) begin
-      queue_id              <= {C_AXI_ID_WIDTH{1'b0}};
-      multiple_id_non_split <= 1'b0;
-      split_in_progress     <= 1'b0;
-    end else begin
-      if ( cmd_push ) begin
-        // Store ID (it will be matching ID or a "new beginning").
-        queue_id              <= S_AXI_AID_Q;
-      end
-      
-      if ( no_cmd & no_b_cmd ) begin
-        multiple_id_non_split <= 1'b0;
-      end else if ( cmd_push & allow_non_split_cmd & ~id_match ) begin
-        multiple_id_non_split <= 1'b1;
-      end
-      
-      if ( no_cmd & no_b_cmd ) begin
-        split_in_progress     <= 1'b0;
-      end else if ( cmd_push & allow_split_cmd ) begin
-        split_in_progress     <= 1'b1;
-      end
-    end
-  end
-  
-  // Determine if the command FIFOs are empty.
-  assign no_cmd               = almost_empty   & cmd_ready   | cmd_empty;
-  assign no_b_cmd             = almost_b_empty & cmd_b_ready | cmd_b_empty;
-  
-  // Check ID to make sure this command is allowed.
-  assign id_match             = ( C_SINGLE_THREAD == 0 ) | ( queue_id == S_AXI_AID_Q);
-  assign cmd_id_check         = (cmd_empty & cmd_b_empty) | ( id_match & (~cmd_empty | ~cmd_b_empty) );
-  
-  // Command type affects possibility to push immediately or wait.
-  assign allow_split_cmd      = need_to_split_q & cmd_id_check & ~multiple_id_non_split;
-  assign allow_non_split_cmd  = ~need_to_split_q & (cmd_id_check | ~split_in_progress);
-  assign allow_this_cmd       = allow_split_cmd | allow_non_split_cmd | ( C_SINGLE_THREAD == 0 );
-  
-  // Check if it is allowed to push more commands.
-  assign allow_new_cmd        = (~cmd_full & ~cmd_b_full & allow_this_cmd) | 
-                                cmd_push_block;
-  
-  // Push new command when allowed and MI-side is able to receive the command.
-  assign cmd_push             = M_AXI_AVALID_I & ~cmd_push_block;
-  assign cmd_b_push           = M_AXI_AVALID_I & ~cmd_b_push_block & (C_AXI_CHANNEL == 0);
-  
-  // Block furter push until command has been forwarded to MI-side.
-  always @ (posedge ACLK) begin
-    if (ARESET) begin
-      cmd_push_block <= 1'b0;
-    end else begin
-      if ( pushed_new_cmd ) begin
-        cmd_push_block <= 1'b0;
-      end else if ( cmd_push & mi_stalling ) begin
-        cmd_push_block <= 1'b1;
-      end 
-    end
-  end
-  
-  // Block furter push until command has been forwarded to MI-side.
-  always @ (posedge ACLK) begin
-    if (ARESET) begin
-      cmd_b_push_block <= 1'b0;
-    end else begin
-      if ( S_AXI_AREADY_I ) begin
-        cmd_b_push_block <= 1'b0;
-      end else if ( cmd_b_push ) begin
-        cmd_b_push_block <= 1'b1;
-      end 
-    end
-  end
-  
-  // Acknowledge command when we can push it into queue (and forward it).
-  assign pushed_new_cmd = M_AXI_AVALID_I & M_AXI_AREADY_I;
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Command Queue (W/R):
-  // 
-  // Instantiate a FIFO as the queue and adjust the control signals.
-  // 
-  // The features from Command FIFO can be reduced depending on configuration:
-  // Read Channel only need the split information.
-  // Write Channel always require ID information. When bursts are supported 
-  // Split and Length information is also used.
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Instantiated queue.
-  generate
-    if ( C_AXI_CHANNEL == 1 && C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_R_CHANNEL
-      axi_data_fifo_v2_1_8_axic_fifo #
-      (
-       .C_FAMILY(C_FAMILY),
-       .C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
-       .C_FIFO_WIDTH(1),
-       .C_FIFO_TYPE("lut")
-       ) 
-       cmd_queue
-      (
-       .ACLK(ACLK),
-       .ARESET(ARESET),
-       .S_MESG({cmd_split_i}),
-       .S_VALID(cmd_push),
-       .S_READY(s_ready),
-       .M_MESG({cmd_split}),
-       .M_VALID(cmd_valid),
-       .M_READY(cmd_ready)
-       );
-       
-       assign cmd_id            = {C_AXI_ID_WIDTH{1'b0}};
-       assign cmd_length        = 4'b0;
-       
-    end else if (C_SUPPORT_BURSTS == 1) begin : USE_BURSTS
-      axi_data_fifo_v2_1_8_axic_fifo #
-      (
-       .C_FAMILY(C_FAMILY),
-       .C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
-       .C_FIFO_WIDTH(C_AXI_ID_WIDTH+4),
-       .C_FIFO_TYPE("lut")
-       ) 
-       cmd_queue
-      (
-       .ACLK(ACLK),
-       .ARESET(ARESET),
-       .S_MESG({cmd_id_i, cmd_length_i}),
-       .S_VALID(cmd_push),
-       .S_READY(s_ready),
-       .M_MESG({cmd_id, cmd_length}),
-       .M_VALID(cmd_valid),
-       .M_READY(cmd_ready)
-       );
-       
-       assign cmd_split         = 1'b0;
-       
-    end else begin : NO_BURSTS
-      axi_data_fifo_v2_1_8_axic_fifo #
-      (
-       .C_FAMILY(C_FAMILY),
-       .C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
-       .C_FIFO_WIDTH(C_AXI_ID_WIDTH),
-       .C_FIFO_TYPE("lut")
-       ) 
-       cmd_queue
-      (
-       .ACLK(ACLK),
-       .ARESET(ARESET),
-       .S_MESG({cmd_id_i}),
-       .S_VALID(cmd_push),
-       .S_READY(s_ready),
-       .M_MESG({cmd_id}),
-       .M_VALID(cmd_valid),
-       .M_READY(cmd_ready)
-       );
-       
-       assign cmd_split         = 1'b0;
-       assign cmd_length        = 4'b0;
-       
-    end
-  endgenerate
-
-  // Queue is concidered full when not ready.
-  assign cmd_full   = ~s_ready;
-  
-  // Queue is empty when no data at output port.
-  always @ (posedge ACLK) begin
-    if (ARESET) begin
-      cmd_empty <= 1'b1;
-      cmd_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
-    end else begin
-      if ( cmd_push & ~cmd_ready ) begin
-        // Push only => Increase depth.
-        cmd_depth <= cmd_depth + 1'b1;
-        cmd_empty <= 1'b0;
-      end else if ( ~cmd_push & cmd_ready ) begin
-        // Pop only => Decrease depth.
-        cmd_depth <= cmd_depth - 1'b1;
-        cmd_empty <= almost_empty;
-      end
-    end
-  end
-  
-  assign almost_empty = ( cmd_depth == 1 );
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Command Queue (B):
-  // 
-  // Add command queue for B channel only when it is AW channel and both burst
-  // and splitting is supported.
-  //
-  // When turned off the command appears always empty.
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Instantiated queue.
-  generate
-    if ( C_AXI_CHANNEL == 0 && C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_B_CHANNEL
-      
-      wire                                cmd_b_valid_i;
-      wire                                s_b_ready;
-      
-      axi_data_fifo_v2_1_8_axic_fifo #
-      (
-       .C_FAMILY(C_FAMILY),
-       .C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
-       .C_FIFO_WIDTH(1+4),
-       .C_FIFO_TYPE("lut")
-       ) 
-       cmd_b_queue
-      (
-       .ACLK(ACLK),
-       .ARESET(ARESET),
-       .S_MESG({cmd_b_split_i, cmd_b_repeat_i}),
-       .S_VALID(cmd_b_push),
-       .S_READY(s_b_ready),
-       .M_MESG({cmd_b_split, cmd_b_repeat}),
-       .M_VALID(cmd_b_valid_i),
-       .M_READY(cmd_b_ready)
-       );
-    
-      // Queue is concidered full when not ready.
-      assign cmd_b_full   = ~s_b_ready;
-      
-      // Queue is empty when no data at output port.
-      always @ (posedge ACLK) begin
-        if (ARESET) begin
-          cmd_b_empty <= 1'b1;
-          cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
-        end else begin
-          if ( cmd_b_push & ~cmd_b_ready ) begin
-            // Push only => Increase depth.
-            cmd_b_depth <= cmd_b_depth + 1'b1;
-            cmd_b_empty <= 1'b0;
-          end else if ( ~cmd_b_push & cmd_b_ready ) begin
-            // Pop only => Decrease depth.
-            cmd_b_depth <= cmd_b_depth - 1'b1;
-            cmd_b_empty <= ( cmd_b_depth == 1 );
-          end
-        end
-      end
-  
-      assign almost_b_empty = ( cmd_b_depth == 1 );
-      
-      // Assign external signal.
-      assign cmd_b_valid  = cmd_b_valid_i;
-      
-    end else begin : NO_B_CHANNEL
-      
-      // Assign external command signals.
-      assign cmd_b_valid    = 1'b0;
-      assign cmd_b_split    = 1'b0;
-      assign cmd_b_repeat   = 4'b0;
-   
-      // Assign internal command FIFO signals.
-      assign cmd_b_full     = 1'b0;
-      assign almost_b_empty = 1'b0;
-      always @ (posedge ACLK) begin
-        if (ARESET) begin
-          cmd_b_empty <= 1'b1;
-          cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
-        end else begin
-          // Constant FF due to ModelSim behavior.
-          cmd_b_empty <= 1'b1;
-          cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
-        end
-      end
-      
-    end
-  endgenerate
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // MI-side output handling
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-  assign M_AXI_AID      = M_AXI_AID_I;
-  assign M_AXI_AADDR    = M_AXI_AADDR_I;
-  assign M_AXI_ALEN     = M_AXI_ALEN_I;
-  assign M_AXI_ASIZE    = M_AXI_ASIZE_I;
-  assign M_AXI_ABURST   = M_AXI_ABURST_I;
-  assign M_AXI_ALOCK    = M_AXI_ALOCK_I;
-  assign M_AXI_ACACHE   = M_AXI_ACACHE_I;
-  assign M_AXI_APROT    = M_AXI_APROT_I;
-  assign M_AXI_AQOS     = M_AXI_AQOS_I;
-  assign M_AXI_AUSER    = M_AXI_AUSER_I;
-  assign M_AXI_AVALID   = M_AXI_AVALID_I;
-  assign M_AXI_AREADY_I = M_AXI_AREADY;
-  
-  
-endmodule
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v
deleted file mode 100755
index 2f593139d459bbe8c86bb90eeb33bd8e8e8e50ac..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v
+++ /dev/null
@@ -1,606 +0,0 @@
-// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
-// --
-// -- This file contains confidential and proprietary information
-// -- of Xilinx, Inc. and is protected under U.S. and 
-// -- international copyright and other intellectual property
-// -- laws.
-// --
-// -- DISCLAIMER
-// -- This disclaimer is not a license and does not grant any
-// -- rights to the materials distributed herewith. Except as
-// -- otherwise provided in a valid license issued to you by
-// -- Xilinx, and to the maximum extent permitted by applicable
-// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// -- (2) Xilinx shall not be liable (whether in contract or tort,
-// -- including negligence, or under any other theory of
-// -- liability) for any loss or damage of any kind or nature
-// -- related to, arising under or in connection with these
-// -- materials, including for any direct, or any indirect,
-// -- special, incidental, or consequential loss or damage
-// -- (including loss of data, profits, goodwill, or any type of
-// -- loss or damage suffered as a result of any action brought
-// -- by a third party) even if such damage or loss was
-// -- reasonably foreseeable or Xilinx had been advised of the
-// -- possibility of the same.
-// --
-// -- CRITICAL APPLICATIONS
-// -- Xilinx products are not designed or intended to be fail-
-// -- safe, or for use in any application requiring fail-safe
-// -- performance, such as life-support or safety devices or
-// -- systems, Class III medical devices, nuclear facilities,
-// -- applications related to the deployment of airbags, or any
-// -- other applications that could lead to death, personal
-// -- injury, or severe property or environmental damage
-// -- (individually and collectively, "Critical
-// -- Applications"). Customer assumes the sole risk and
-// -- liability of any use of Xilinx products in Critical
-// -- Applications, subject only to applicable laws and
-// -- regulations governing limitations on product liability.
-// --
-// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// -- PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-//
-// Description: AXI3 Slave Converter
-// This module instantiates Address, Write Data and Read Data AXI3 Converter 
-// modules, each one taking care of the channel specific tasks.
-// The Address AXI3 converter can handle both AR and AW channels.
-// The Write Respons Channel is reused from the Down-Sizer.
-//
-// Verilog-standard:  Verilog 2001
-//--------------------------------------------------------------------------
-//
-// Structure:
-//    axi3_conv
-//      a_axi3_conv
-//        axic_fifo
-//      w_axi3_conv
-//      b_downsizer
-//      r_axi3_conv
-//
-//--------------------------------------------------------------------------
-`timescale 1ps/1ps
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_axi3_conv #
-  (
-   parameter C_FAMILY                            = "none",
-   parameter integer C_AXI_ID_WIDTH              = 1,
-   parameter integer C_AXI_ADDR_WIDTH            = 32,
-   parameter integer C_AXI_DATA_WIDTH            = 32,
-   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
-   parameter integer C_AXI_AWUSER_WIDTH          = 1,
-   parameter integer C_AXI_ARUSER_WIDTH          = 1,
-   parameter integer C_AXI_WUSER_WIDTH           = 1,
-   parameter integer C_AXI_RUSER_WIDTH           = 1,
-   parameter integer C_AXI_BUSER_WIDTH           = 1,
-   parameter integer C_AXI_SUPPORTS_WRITE             = 1,
-   parameter integer C_AXI_SUPPORTS_READ              = 1,
-   parameter integer C_SUPPORT_SPLITTING              = 1,
-                       // Implement transaction splitting logic.
-                       // Disabled whan all connected masters are AXI3 and have same or narrower data width.
-   parameter integer C_SUPPORT_BURSTS                 = 1,
-                       // Disabled when all connected masters are AxiLite,
-                       //   allowing logic to be simplified.
-   parameter integer C_SINGLE_THREAD                  = 1
-                       // 0 = Ignore ID when propagating transactions (assume all responses are in order).
-                       // 1 = Enforce single-threading (one ID at a time) when any outstanding or 
-                       //     requested transaction requires splitting.
-                       //     While no split is ongoing any new non-split transaction will pass immediately regardless
-                       //     off ID.
-                       //     A split transaction will stall if there are multiple ID (non-split) transactions
-                       //     ongoing, once it has been forwarded only transactions with the same ID is allowed
-                       //     (split or not) until all ongoing split transactios has been completed.
-   )
-  (
-   // System Signals
-   input wire ACLK,
-   input wire ARESETN,
-
-   // Slave Interface Write Address Ports
-   input  wire [C_AXI_ID_WIDTH-1:0]     S_AXI_AWID,
-   input  wire [C_AXI_ADDR_WIDTH-1:0]   S_AXI_AWADDR,
-   input  wire [8-1:0]                  S_AXI_AWLEN,
-   input  wire [3-1:0]                  S_AXI_AWSIZE,
-   input  wire [2-1:0]                  S_AXI_AWBURST,
-   input  wire [1-1:0]                  S_AXI_AWLOCK,
-   input  wire [4-1:0]                  S_AXI_AWCACHE,
-   input  wire [3-1:0]                  S_AXI_AWPROT,
-   input  wire [4-1:0]                  S_AXI_AWQOS,
-   input  wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
-   input  wire                          S_AXI_AWVALID,
-   output wire                          S_AXI_AWREADY,
-
-   // Slave Interface Write Data Ports
-   input  wire [C_AXI_DATA_WIDTH-1:0]   S_AXI_WDATA,
-   input  wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
-   input  wire                          S_AXI_WLAST,
-   input  wire [C_AXI_WUSER_WIDTH-1:0]  S_AXI_WUSER,
-   input  wire                          S_AXI_WVALID,
-   output wire                          S_AXI_WREADY,
-
-   // Slave Interface Write Response Ports
-   output wire [C_AXI_ID_WIDTH-1:0]    S_AXI_BID,
-   output wire [2-1:0]                 S_AXI_BRESP,
-   output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
-   output wire                         S_AXI_BVALID,
-   input  wire                         S_AXI_BREADY,
-
-   // Slave Interface Read Address Ports
-   input  wire [C_AXI_ID_WIDTH-1:0]     S_AXI_ARID,
-   input  wire [C_AXI_ADDR_WIDTH-1:0]   S_AXI_ARADDR,
-   input  wire [8-1:0]                  S_AXI_ARLEN,
-   input  wire [3-1:0]                  S_AXI_ARSIZE,
-   input  wire [2-1:0]                  S_AXI_ARBURST,
-   input  wire [1-1:0]                  S_AXI_ARLOCK,
-   input  wire [4-1:0]                  S_AXI_ARCACHE,
-   input  wire [3-1:0]                  S_AXI_ARPROT,
-   input  wire [4-1:0]                  S_AXI_ARQOS,
-   input  wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
-   input  wire                          S_AXI_ARVALID,
-   output wire                          S_AXI_ARREADY,
-
-   // Slave Interface Read Data Ports
-   output wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID,
-   output wire [C_AXI_DATA_WIDTH-1:0]  S_AXI_RDATA,
-   output wire [2-1:0]                 S_AXI_RRESP,
-   output wire                         S_AXI_RLAST,
-   output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
-   output wire                         S_AXI_RVALID,
-   input  wire                         S_AXI_RREADY,
-   
-   // Master Interface Write Address Port
-   output wire [C_AXI_ID_WIDTH-1:0]     M_AXI_AWID,
-   output wire [C_AXI_ADDR_WIDTH-1:0]   M_AXI_AWADDR,
-   output wire [4-1:0]                  M_AXI_AWLEN,
-   output wire [3-1:0]                  M_AXI_AWSIZE,
-   output wire [2-1:0]                  M_AXI_AWBURST,
-   output wire [2-1:0]                  M_AXI_AWLOCK,
-   output wire [4-1:0]                  M_AXI_AWCACHE,
-   output wire [3-1:0]                  M_AXI_AWPROT,
-   output wire [4-1:0]                  M_AXI_AWQOS,
-   output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
-   output wire                          M_AXI_AWVALID,
-   input  wire                          M_AXI_AWREADY,
-   
-   // Master Interface Write Data Ports
-   output wire [C_AXI_ID_WIDTH-1:0]     M_AXI_WID,
-   output wire [C_AXI_DATA_WIDTH-1:0]   M_AXI_WDATA,
-   output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
-   output wire                          M_AXI_WLAST,
-   output wire [C_AXI_WUSER_WIDTH-1:0]  M_AXI_WUSER,
-   output wire                          M_AXI_WVALID,
-   input  wire                          M_AXI_WREADY,
-   
-   // Master Interface Write Response Ports
-   input  wire [C_AXI_ID_WIDTH-1:0]    M_AXI_BID,
-   input  wire [2-1:0]                 M_AXI_BRESP,
-   input  wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
-   input  wire                         M_AXI_BVALID,
-   output wire                         M_AXI_BREADY,
-   
-   // Master Interface Read Address Port
-   output wire [C_AXI_ID_WIDTH-1:0]     M_AXI_ARID,
-   output wire [C_AXI_ADDR_WIDTH-1:0]   M_AXI_ARADDR,
-   output wire [4-1:0]                  M_AXI_ARLEN,
-   output wire [3-1:0]                  M_AXI_ARSIZE,
-   output wire [2-1:0]                  M_AXI_ARBURST,
-   output wire [2-1:0]                  M_AXI_ARLOCK,
-   output wire [4-1:0]                  M_AXI_ARCACHE,
-   output wire [3-1:0]                  M_AXI_ARPROT,
-   output wire [4-1:0]                  M_AXI_ARQOS,
-   output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
-   output wire                          M_AXI_ARVALID,
-   input  wire                          M_AXI_ARREADY,
-   
-   // Master Interface Read Data Ports
-   input  wire [C_AXI_ID_WIDTH-1:0]    M_AXI_RID,
-   input  wire [C_AXI_DATA_WIDTH-1:0]  M_AXI_RDATA,
-   input  wire [2-1:0]                 M_AXI_RRESP,
-   input  wire                         M_AXI_RLAST,
-   input  wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
-   input  wire                         M_AXI_RVALID,
-   output wire                         M_AXI_RREADY
-   );
-
-   
-  /////////////////////////////////////////////////////////////////////////////
-  // Functions
-  /////////////////////////////////////////////////////////////////////////////
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Local params
-  /////////////////////////////////////////////////////////////////////////////
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Variables for generating parameter controlled instances.
-  /////////////////////////////////////////////////////////////////////////////
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Internal signals
-  /////////////////////////////////////////////////////////////////////////////
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Handle Write Channels (AW/W/B)
-  /////////////////////////////////////////////////////////////////////////////
-  generate
-    if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE
-    
-      // Write Channel Signals for Commands Queue Interface.
-      wire                              wr_cmd_valid;
-      wire [C_AXI_ID_WIDTH-1:0]         wr_cmd_id;
-      wire [4-1:0]                      wr_cmd_length;
-      wire                              wr_cmd_ready;
-      
-      wire                              wr_cmd_b_valid;
-      wire                              wr_cmd_b_split;
-      wire [4-1:0]                      wr_cmd_b_repeat;
-      wire                              wr_cmd_b_ready;
-      
-      // Write Address Channel.
-      axi_protocol_converter_v2_1_9_a_axi3_conv #
-      (
-       .C_FAMILY                    (C_FAMILY),
-       .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
-       .C_AXI_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),
-       .C_AXI_DATA_WIDTH            (C_AXI_DATA_WIDTH),
-       .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
-       .C_AXI_AUSER_WIDTH           (C_AXI_AWUSER_WIDTH),
-       .C_AXI_CHANNEL               (0),
-       .C_SUPPORT_SPLITTING         (C_SUPPORT_SPLITTING),
-       .C_SUPPORT_BURSTS            (C_SUPPORT_BURSTS),
-       .C_SINGLE_THREAD             (C_SINGLE_THREAD)
-        ) write_addr_inst
-       (
-        // Global Signals
-        .ARESET                     (~ARESETN),
-        .ACLK                       (ACLK),
-    
-        // Command Interface (W)
-        .cmd_valid                  (wr_cmd_valid),
-        .cmd_split                  (),
-        .cmd_id                     (wr_cmd_id),
-        .cmd_length                 (wr_cmd_length),
-        .cmd_ready                  (wr_cmd_ready),
-       
-        // Command Interface (B)
-        .cmd_b_valid                (wr_cmd_b_valid),
-        .cmd_b_split                (wr_cmd_b_split),
-        .cmd_b_repeat               (wr_cmd_b_repeat),
-        .cmd_b_ready                (wr_cmd_b_ready),
-       
-        // Slave Interface Write Address Ports
-        .S_AXI_AID                  (S_AXI_AWID),
-        .S_AXI_AADDR                (S_AXI_AWADDR),
-        .S_AXI_ALEN                 (S_AXI_AWLEN),
-        .S_AXI_ASIZE                (S_AXI_AWSIZE),
-        .S_AXI_ABURST               (S_AXI_AWBURST),
-        .S_AXI_ALOCK                (S_AXI_AWLOCK),
-        .S_AXI_ACACHE               (S_AXI_AWCACHE),
-        .S_AXI_APROT                (S_AXI_AWPROT),
-        .S_AXI_AQOS                 (S_AXI_AWQOS),
-        .S_AXI_AUSER                (S_AXI_AWUSER),
-        .S_AXI_AVALID               (S_AXI_AWVALID),
-        .S_AXI_AREADY               (S_AXI_AWREADY),
-        
-        // Master Interface Write Address Port
-        .M_AXI_AID                  (M_AXI_AWID),
-        .M_AXI_AADDR                (M_AXI_AWADDR),
-        .M_AXI_ALEN                 (M_AXI_AWLEN),
-        .M_AXI_ASIZE                (M_AXI_AWSIZE),
-        .M_AXI_ABURST               (M_AXI_AWBURST),
-        .M_AXI_ALOCK                (M_AXI_AWLOCK),
-        .M_AXI_ACACHE               (M_AXI_AWCACHE),
-        .M_AXI_APROT                (M_AXI_AWPROT),
-        .M_AXI_AQOS                 (M_AXI_AWQOS),
-        .M_AXI_AUSER                (M_AXI_AWUSER),
-        .M_AXI_AVALID               (M_AXI_AWVALID),
-        .M_AXI_AREADY               (M_AXI_AWREADY)
-       );
-       
-      // Write Data Channel.
-      axi_protocol_converter_v2_1_9_w_axi3_conv #
-      (
-       .C_FAMILY                    (C_FAMILY),
-       .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
-       .C_AXI_DATA_WIDTH            (C_AXI_DATA_WIDTH),
-       .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
-       .C_AXI_WUSER_WIDTH           (C_AXI_WUSER_WIDTH),
-       .C_SUPPORT_SPLITTING         (C_SUPPORT_SPLITTING),
-       .C_SUPPORT_BURSTS            (C_SUPPORT_BURSTS)
-        ) write_data_inst
-       (
-        // Global Signals
-        .ARESET                     (~ARESETN),
-        .ACLK                       (ACLK),
-    
-        // Command Interface
-        .cmd_valid                  (wr_cmd_valid),
-        .cmd_id                     (wr_cmd_id),
-        .cmd_length                 (wr_cmd_length),
-        .cmd_ready                  (wr_cmd_ready),
-       
-        // Slave Interface Write Data Ports
-        .S_AXI_WDATA                (S_AXI_WDATA),
-        .S_AXI_WSTRB                (S_AXI_WSTRB),
-        .S_AXI_WLAST                (S_AXI_WLAST),
-        .S_AXI_WUSER                (S_AXI_WUSER),
-        .S_AXI_WVALID               (S_AXI_WVALID),
-        .S_AXI_WREADY               (S_AXI_WREADY),
-        
-        // Master Interface Write Data Ports
-        .M_AXI_WID                  (M_AXI_WID),
-        .M_AXI_WDATA                (M_AXI_WDATA),
-        .M_AXI_WSTRB                (M_AXI_WSTRB),
-        .M_AXI_WLAST                (M_AXI_WLAST),
-        .M_AXI_WUSER                (M_AXI_WUSER),
-        .M_AXI_WVALID               (M_AXI_WVALID),
-        .M_AXI_WREADY               (M_AXI_WREADY)
-       );
-      
-      if ( C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_SPLIT_W
-      
-        // Write Data Response Channel.
-        axi_protocol_converter_v2_1_9_b_downsizer #
-        (
-         .C_FAMILY                    (C_FAMILY),
-         .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
-         .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
-         .C_AXI_BUSER_WIDTH           (C_AXI_BUSER_WIDTH)
-          ) write_resp_inst
-         (
-          // Global Signals
-          .ARESET                     (~ARESETN),
-          .ACLK                       (ACLK),
-      
-          // Command Interface
-          .cmd_valid                  (wr_cmd_b_valid),
-          .cmd_split                  (wr_cmd_b_split),
-          .cmd_repeat                 (wr_cmd_b_repeat),
-          .cmd_ready                  (wr_cmd_b_ready),
-          
-          // Slave Interface Write Response Ports
-          .S_AXI_BID                  (S_AXI_BID),
-          .S_AXI_BRESP                (S_AXI_BRESP),
-          .S_AXI_BUSER                (S_AXI_BUSER),
-          .S_AXI_BVALID               (S_AXI_BVALID),
-          .S_AXI_BREADY               (S_AXI_BREADY),
-          
-          // Master Interface Write Response Ports
-          .M_AXI_BID                  (M_AXI_BID),
-          .M_AXI_BRESP                (M_AXI_BRESP),
-          .M_AXI_BUSER                (M_AXI_BUSER),
-          .M_AXI_BVALID               (M_AXI_BVALID),
-          .M_AXI_BREADY               (M_AXI_BREADY)
-         );
-        
-      end else begin : NO_SPLIT_W
-      
-        // MI -> SI Interface Write Response Ports
-        assign S_AXI_BID      = M_AXI_BID;
-        assign S_AXI_BRESP    = M_AXI_BRESP;
-        assign S_AXI_BUSER    = M_AXI_BUSER;
-        assign S_AXI_BVALID   = M_AXI_BVALID;
-        assign M_AXI_BREADY   = S_AXI_BREADY;
-        
-      end
-      
-    end else begin : NO_WRITE
-    
-      // Slave Interface Write Address Ports
-      assign S_AXI_AWREADY = 1'b0;
-      // Slave Interface Write Data Ports
-      assign S_AXI_WREADY  = 1'b0;
-      // Slave Interface Write Response Ports
-      assign S_AXI_BID     = {C_AXI_ID_WIDTH{1'b0}};
-      assign S_AXI_BRESP   = 2'b0;
-      assign S_AXI_BUSER   = {C_AXI_BUSER_WIDTH{1'b0}};
-      assign S_AXI_BVALID  = 1'b0;
-      
-      // Master Interface Write Address Port
-      assign M_AXI_AWID    = {C_AXI_ID_WIDTH{1'b0}};
-      assign M_AXI_AWADDR  = {C_AXI_ADDR_WIDTH{1'b0}};
-      assign M_AXI_AWLEN   = 4'b0;
-      assign M_AXI_AWSIZE  = 3'b0;
-      assign M_AXI_AWBURST = 2'b0;
-      assign M_AXI_AWLOCK  = 2'b0;
-      assign M_AXI_AWCACHE = 4'b0;
-      assign M_AXI_AWPROT  = 3'b0;
-      assign M_AXI_AWQOS   = 4'b0;
-      assign M_AXI_AWUSER  = {C_AXI_AWUSER_WIDTH{1'b0}};
-      assign M_AXI_AWVALID = 1'b0;
-      // Master Interface Write Data Ports
-      assign M_AXI_WDATA   = {C_AXI_DATA_WIDTH{1'b0}};
-      assign M_AXI_WSTRB   = {C_AXI_DATA_WIDTH/8{1'b0}};
-      assign M_AXI_WLAST   = 1'b0;
-      assign M_AXI_WUSER   = {C_AXI_WUSER_WIDTH{1'b0}};
-      assign M_AXI_WVALID  = 1'b0;
-      // Master Interface Write Response Ports
-      assign M_AXI_BREADY  = 1'b0;
-      
-    end
-  endgenerate
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Handle Read Channels (AR/R)
-  /////////////////////////////////////////////////////////////////////////////
-  generate
-    if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ
-    
-      // Write Response channel.
-      if ( C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_SPLIT_R
-      
-        // Read Channel Signals for Commands Queue Interface.
-        wire                              rd_cmd_valid;
-        wire                              rd_cmd_split;
-        wire                              rd_cmd_ready;
-        
-        // Write Address Channel.
-        axi_protocol_converter_v2_1_9_a_axi3_conv #
-        (
-         .C_FAMILY                    (C_FAMILY),
-         .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
-         .C_AXI_ADDR_WIDTH            (C_AXI_ADDR_WIDTH),
-         .C_AXI_DATA_WIDTH            (C_AXI_DATA_WIDTH),
-         .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
-         .C_AXI_AUSER_WIDTH           (C_AXI_ARUSER_WIDTH),
-         .C_AXI_CHANNEL               (1),
-         .C_SUPPORT_SPLITTING         (C_SUPPORT_SPLITTING),
-         .C_SUPPORT_BURSTS            (C_SUPPORT_BURSTS),
-         .C_SINGLE_THREAD             (C_SINGLE_THREAD)
-          ) read_addr_inst
-         (
-          // Global Signals
-          .ARESET                     (~ARESETN),
-          .ACLK                       (ACLK),
-      
-          // Command Interface (R)
-          .cmd_valid                  (rd_cmd_valid),
-          .cmd_split                  (rd_cmd_split),
-          .cmd_id                     (),
-          .cmd_length                 (),
-          .cmd_ready                  (rd_cmd_ready),
-         
-          // Command Interface (B)
-          .cmd_b_valid                (),
-          .cmd_b_split                (),
-          .cmd_b_repeat               (),
-          .cmd_b_ready                (1'b0),
-         
-          // Slave Interface Write Address Ports
-          .S_AXI_AID                  (S_AXI_ARID),
-          .S_AXI_AADDR                (S_AXI_ARADDR),
-          .S_AXI_ALEN                 (S_AXI_ARLEN),
-          .S_AXI_ASIZE                (S_AXI_ARSIZE),
-          .S_AXI_ABURST               (S_AXI_ARBURST),
-          .S_AXI_ALOCK                (S_AXI_ARLOCK),
-          .S_AXI_ACACHE               (S_AXI_ARCACHE),
-          .S_AXI_APROT                (S_AXI_ARPROT),
-          .S_AXI_AQOS                 (S_AXI_ARQOS),
-          .S_AXI_AUSER                (S_AXI_ARUSER),
-          .S_AXI_AVALID               (S_AXI_ARVALID),
-          .S_AXI_AREADY               (S_AXI_ARREADY),
-          
-          // Master Interface Write Address Port
-          .M_AXI_AID                  (M_AXI_ARID),
-          .M_AXI_AADDR                (M_AXI_ARADDR),
-          .M_AXI_ALEN                 (M_AXI_ARLEN),
-          .M_AXI_ASIZE                (M_AXI_ARSIZE),
-          .M_AXI_ABURST               (M_AXI_ARBURST),
-          .M_AXI_ALOCK                (M_AXI_ARLOCK),
-          .M_AXI_ACACHE               (M_AXI_ARCACHE),
-          .M_AXI_APROT                (M_AXI_ARPROT),
-          .M_AXI_AQOS                 (M_AXI_ARQOS),
-          .M_AXI_AUSER                (M_AXI_ARUSER),
-          .M_AXI_AVALID               (M_AXI_ARVALID),
-          .M_AXI_AREADY               (M_AXI_ARREADY)
-         );
-         
-        // Read Data Channel.
-        axi_protocol_converter_v2_1_9_r_axi3_conv #
-        (
-         .C_FAMILY                    (C_FAMILY),
-         .C_AXI_ID_WIDTH              (C_AXI_ID_WIDTH),
-         .C_AXI_DATA_WIDTH            (C_AXI_DATA_WIDTH),
-         .C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
-         .C_AXI_RUSER_WIDTH           (C_AXI_RUSER_WIDTH),
-         .C_SUPPORT_SPLITTING         (C_SUPPORT_SPLITTING),
-         .C_SUPPORT_BURSTS            (C_SUPPORT_BURSTS)
-          ) read_data_inst
-         (
-          // Global Signals
-          .ARESET                     (~ARESETN),
-          .ACLK                       (ACLK),
-      
-          // Command Interface
-          .cmd_valid                  (rd_cmd_valid),
-          .cmd_split                  (rd_cmd_split),
-          .cmd_ready                  (rd_cmd_ready),
-         
-          // Slave Interface Read Data Ports
-          .S_AXI_RID                  (S_AXI_RID),
-          .S_AXI_RDATA                (S_AXI_RDATA),
-          .S_AXI_RRESP                (S_AXI_RRESP),
-          .S_AXI_RLAST                (S_AXI_RLAST),
-          .S_AXI_RUSER                (S_AXI_RUSER),
-          .S_AXI_RVALID               (S_AXI_RVALID),
-          .S_AXI_RREADY               (S_AXI_RREADY),
-          
-          // Master Interface Read Data Ports
-          .M_AXI_RID                  (M_AXI_RID),
-          .M_AXI_RDATA                (M_AXI_RDATA),
-          .M_AXI_RRESP                (M_AXI_RRESP),
-          .M_AXI_RLAST                (M_AXI_RLAST),
-          .M_AXI_RUSER                (M_AXI_RUSER),
-          .M_AXI_RVALID               (M_AXI_RVALID),
-          .M_AXI_RREADY               (M_AXI_RREADY)
-         );
-       
-      end else begin : NO_SPLIT_R
-      
-        // SI -> MI Interface Write Address Port
-        assign M_AXI_ARID     = S_AXI_ARID;
-        assign M_AXI_ARADDR   = S_AXI_ARADDR;
-        assign M_AXI_ARLEN    = S_AXI_ARLEN;
-        assign M_AXI_ARSIZE   = S_AXI_ARSIZE;
-        assign M_AXI_ARBURST  = S_AXI_ARBURST;
-        assign M_AXI_ARLOCK   = S_AXI_ARLOCK;
-        assign M_AXI_ARCACHE  = S_AXI_ARCACHE;
-        assign M_AXI_ARPROT   = S_AXI_ARPROT;
-        assign M_AXI_ARQOS    = S_AXI_ARQOS;
-        assign M_AXI_ARUSER   = S_AXI_ARUSER;
-        assign M_AXI_ARVALID  = S_AXI_ARVALID;
-        assign S_AXI_ARREADY  = M_AXI_ARREADY;
-        
-        // MI -> SI Interface Read Data Ports
-        assign S_AXI_RID      = M_AXI_RID;
-        assign S_AXI_RDATA    = M_AXI_RDATA;
-        assign S_AXI_RRESP    = M_AXI_RRESP;
-        assign S_AXI_RLAST    = M_AXI_RLAST;
-        assign S_AXI_RUSER    = M_AXI_RUSER;
-        assign S_AXI_RVALID   = M_AXI_RVALID;
-        assign M_AXI_RREADY   = S_AXI_RREADY;
-        
-      end
-      
-    end else begin : NO_READ
-    
-      // Slave Interface Read Address Ports
-      assign S_AXI_ARREADY = 1'b0;
-      // Slave Interface Read Data Ports
-      assign S_AXI_RID     = {C_AXI_ID_WIDTH{1'b0}};
-      assign S_AXI_RDATA   = {C_AXI_DATA_WIDTH{1'b0}};
-      assign S_AXI_RRESP   = 2'b0;
-      assign S_AXI_RLAST   = 1'b0;
-      assign S_AXI_RUSER   = {C_AXI_RUSER_WIDTH{1'b0}};
-      assign S_AXI_RVALID  = 1'b0;
-      
-      // Master Interface Read Address Port
-      assign M_AXI_ARID    = {C_AXI_ID_WIDTH{1'b0}};
-      assign M_AXI_ARADDR  = {C_AXI_ADDR_WIDTH{1'b0}};
-      assign M_AXI_ARLEN   = 4'b0;
-      assign M_AXI_ARSIZE  = 3'b0;
-      assign M_AXI_ARBURST = 2'b0;
-      assign M_AXI_ARLOCK  = 2'b0;
-      assign M_AXI_ARCACHE = 4'b0;
-      assign M_AXI_ARPROT  = 3'b0;
-      assign M_AXI_ARQOS   = 4'b0;
-      assign M_AXI_ARUSER  = {C_AXI_ARUSER_WIDTH{1'b0}};
-      assign M_AXI_ARVALID = 1'b0;
-      // Master Interface Read Data Ports
-      assign M_AXI_RREADY  = 1'b0;
-      
-    end
-  endgenerate
-  
-  
-endmodule
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v
deleted file mode 100755
index cd614cea539bc74b9864e2fa4aef321039e68b68..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v
+++ /dev/null
@@ -1,840 +0,0 @@
-// -- (c) Copyright 2012 -2013 Xilinx, Inc. All rights reserved.
-// --
-// -- This file contains confidential and proprietary information
-// -- of Xilinx, Inc. and is protected under U.S. and 
-// -- international copyright and other intellectual property
-// -- laws.
-// --
-// -- DISCLAIMER
-// -- This disclaimer is not a license and does not grant any
-// -- rights to the materials distributed herewith. Except as
-// -- otherwise provided in a valid license issued to you by
-// -- Xilinx, and to the maximum extent permitted by applicable
-// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// -- (2) Xilinx shall not be liable (whether in contract or tort,
-// -- including negligence, or under any other theory of
-// -- liability) for any loss or damage of any kind or nature
-// -- related to, arising under or in connection with these
-// -- materials, including for any direct, or any indirect,
-// -- special, incidental, or consequential loss or damage
-// -- (including loss of data, profits, goodwill, or any type of
-// -- loss or damage suffered as a result of any action brought
-// -- by a third party) even if such damage or loss was
-// -- reasonably foreseeable or Xilinx had been advised of the
-// -- possibility of the same.
-// --
-// -- CRITICAL APPLICATIONS
-// -- Xilinx products are not designed or intended to be fail-
-// -- safe, or for use in any application requiring fail-safe
-// -- performance, such as life-support or safety devices or
-// -- systems, Class III medical devices, nuclear facilities,
-// -- applications related to the deployment of airbags, or any
-// -- other applications that could lead to death, personal
-// -- injury, or severe property or environmental damage
-// -- (individually and collectively, "Critical
-// -- Applications"). Customer assumes the sole risk and
-// -- liability of any use of Xilinx products in Critical
-// -- Applications, subject only to applicable laws and
-// -- regulations governing limitations on product liability.
-// --
-// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// -- PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-//
-// File name: axi_protocol_converter.v
-//
-// Description: 
-//   This module is a bank of AXI4-Lite and AXI3 protocol converters for a vectored AXI interface.
-//   The interface of this module consists of a vectored slave and master interface
-//     which are each concatenations of upper-level AXI pathways,
-//     plus various vectored parameters.
-//   This module instantiates a set of individual protocol converter modules.
-//
-//-----------------------------------------------------------------------------
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_axi_protocol_converter #(
-  parameter         C_FAMILY                    = "virtex6",
-  parameter integer C_M_AXI_PROTOCOL            = 0, 
-  parameter integer C_S_AXI_PROTOCOL            = 0, 
-  parameter integer C_IGNORE_ID                = 0,
-                     // 0 = RID/BID are stored by axilite_conv.
-                     // 1 = RID/BID have already been stored in an upstream device, like SASD crossbar.
-  parameter integer C_AXI_ID_WIDTH              = 4,
-  parameter integer C_AXI_ADDR_WIDTH            = 32,
-  parameter integer C_AXI_DATA_WIDTH            = 32,
-  parameter integer C_AXI_SUPPORTS_WRITE        = 1,
-  parameter integer C_AXI_SUPPORTS_READ         = 1,
-  parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
-                     // 1 = Propagate all USER signals, 0 = Don’t propagate.
-  parameter integer C_AXI_AWUSER_WIDTH          = 1,
-  parameter integer C_AXI_ARUSER_WIDTH          = 1,
-  parameter integer C_AXI_WUSER_WIDTH           = 1,
-  parameter integer C_AXI_RUSER_WIDTH           = 1,
-  parameter integer C_AXI_BUSER_WIDTH           = 1,
-  parameter integer C_TRANSLATION_MODE                  = 1
-                     // 0 (Unprotected) = Disable all error checking; master is well-behaved.
-                     // 1 (Protection) = Detect SI transaction violations, but perform no splitting.
-                     //     AXI4 -> AXI3 must be <= 16 beats; AXI4/3 -> AXI4LITE must be single.
-                     // 2 (Conversion) = Include transaction splitting logic
-) (
-  // Global Signals
-   input wire aclk,
-   input wire aresetn,
-
-   // Slave Interface Write Address Ports
-   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_awid,
-   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_awaddr,
-   input  wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,
-   input  wire [3-1:0]                  s_axi_awsize,
-   input  wire [2-1:0]                  s_axi_awburst,
-   input  wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_awlock,
-   input  wire [4-1:0]                  s_axi_awcache,
-   input  wire [3-1:0]                  s_axi_awprot,
-   input  wire [4-1:0]                  s_axi_awregion,
-   input  wire [4-1:0]                  s_axi_awqos,
-   input  wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
-   input  wire                          s_axi_awvalid,
-   output wire                          s_axi_awready,
-
-   // Slave Interface Write Data Ports
-   input wire [C_AXI_ID_WIDTH-1:0]      s_axi_wid,
-   input  wire [C_AXI_DATA_WIDTH-1:0]   s_axi_wdata,
-   input  wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
-   input  wire                          s_axi_wlast,
-   input  wire [C_AXI_WUSER_WIDTH-1:0]  s_axi_wuser,
-   input  wire                          s_axi_wvalid,
-   output wire                          s_axi_wready,
-
-   // Slave Interface Write Response Ports
-   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_bid,
-   output wire [2-1:0]                 s_axi_bresp,
-   output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
-   output wire                         s_axi_bvalid,
-   input  wire                         s_axi_bready,
-
-   // Slave Interface Read Address Ports
-   input  wire [C_AXI_ID_WIDTH-1:0]     s_axi_arid,
-   input  wire [C_AXI_ADDR_WIDTH-1:0]   s_axi_araddr,
-   input  wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,
-   input  wire [3-1:0]                  s_axi_arsize,
-   input  wire [2-1:0]                  s_axi_arburst,
-   input  wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  s_axi_arlock,
-   input  wire [4-1:0]                  s_axi_arcache,
-   input  wire [3-1:0]                  s_axi_arprot,
-   input  wire [4-1:0]                  s_axi_arregion,
-   input  wire [4-1:0]                  s_axi_arqos,
-   input  wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
-   input  wire                          s_axi_arvalid,
-   output wire                          s_axi_arready,
-
-   // Slave Interface Read Data Ports
-   output wire [C_AXI_ID_WIDTH-1:0]    s_axi_rid,
-   output wire [C_AXI_DATA_WIDTH-1:0]  s_axi_rdata,
-   output wire [2-1:0]                 s_axi_rresp,
-   output wire                         s_axi_rlast,
-   output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
-   output wire                         s_axi_rvalid,
-   input  wire                         s_axi_rready,
-   
-   // Master Interface Write Address Port
-   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_awid,
-   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_awaddr,
-   output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_awlen,
-   output wire [3-1:0]                  m_axi_awsize,
-   output wire [2-1:0]                  m_axi_awburst,
-   output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_awlock,
-   output wire [4-1:0]                  m_axi_awcache,
-   output wire [3-1:0]                  m_axi_awprot,
-   output wire [4-1:0]                  m_axi_awregion,
-   output wire [4-1:0]                  m_axi_awqos,
-   output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
-   output wire                          m_axi_awvalid,
-   input  wire                          m_axi_awready,
-   
-   // Master Interface Write Data Ports
-   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_wid,
-   output wire [C_AXI_DATA_WIDTH-1:0]   m_axi_wdata,
-   output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
-   output wire                          m_axi_wlast,
-   output wire [C_AXI_WUSER_WIDTH-1:0]  m_axi_wuser,
-   output wire                          m_axi_wvalid,
-   input  wire                          m_axi_wready,
-   
-   // Master Interface Write Response Ports
-   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_bid,
-   input  wire [2-1:0]                 m_axi_bresp,
-   input  wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
-   input  wire                         m_axi_bvalid,
-   output wire                         m_axi_bready,
-   
-   // Master Interface Read Address Port
-   output wire [C_AXI_ID_WIDTH-1:0]     m_axi_arid,
-   output wire [C_AXI_ADDR_WIDTH-1:0]   m_axi_araddr,
-   output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  m_axi_arlen,
-   output wire [3-1:0]                  m_axi_arsize,
-   output wire [2-1:0]                  m_axi_arburst,
-   output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0]  m_axi_arlock,
-   output wire [4-1:0]                  m_axi_arcache,
-   output wire [3-1:0]                  m_axi_arprot,
-   output wire [4-1:0]                  m_axi_arregion,
-   output wire [4-1:0]                  m_axi_arqos,
-   output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
-   output wire                          m_axi_arvalid,
-   input  wire                          m_axi_arready,
-   
-   // Master Interface Read Data Ports
-   input  wire [C_AXI_ID_WIDTH-1:0]    m_axi_rid,
-   input  wire [C_AXI_DATA_WIDTH-1:0]  m_axi_rdata,
-   input  wire [2-1:0]                 m_axi_rresp,
-   input  wire                         m_axi_rlast,
-   input  wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
-   input  wire                         m_axi_rvalid,
-   output wire                         m_axi_rready
-);
-
-localparam P_AXI4 = 32'h0;
-localparam P_AXI3 = 32'h1;
-localparam P_AXILITE = 32'h2;
-localparam P_AXILITE_SIZE = (C_AXI_DATA_WIDTH == 32) ? 3'b010 : 3'b011;
-localparam P_INCR = 2'b01;
-localparam P_DECERR = 2'b11;
-localparam P_SLVERR = 2'b10;
-localparam integer P_PROTECTION = 1;
-localparam integer P_CONVERSION = 2;
-
-wire                          s_awvalid_i;
-wire                          s_arvalid_i;
-wire                          s_wvalid_i ;
-wire                          s_bready_i ;
-wire                          s_rready_i ;
-wire                          s_awready_i; 
-wire                          s_wready_i;
-wire                          s_bvalid_i;
-wire [C_AXI_ID_WIDTH-1:0]     s_bid_i;
-wire [1:0]                    s_bresp_i;
-wire [C_AXI_BUSER_WIDTH-1:0]  s_buser_i;
-wire                          s_arready_i; 
-wire                          s_rvalid_i;
-wire [C_AXI_ID_WIDTH-1:0]     s_rid_i;
-wire [1:0]                    s_rresp_i;
-wire [C_AXI_RUSER_WIDTH-1:0]  s_ruser_i;
-wire [C_AXI_DATA_WIDTH-1:0]   s_rdata_i;
-wire                          s_rlast_i;
-
-generate
-  if ((C_M_AXI_PROTOCOL == P_AXILITE)  || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite
-    assign m_axi_awid         = 0;
-    assign m_axi_awlen        = 0;
-    assign m_axi_awsize       = P_AXILITE_SIZE;
-    assign m_axi_awburst      = P_INCR;
-    assign m_axi_awlock       = 0;
-    assign m_axi_awcache      = 0;
-    assign m_axi_awregion     = 0;
-    assign m_axi_awqos        = 0;
-    assign m_axi_awuser       = 0;
-    assign m_axi_wid          = 0;
-    assign m_axi_wlast        = 1'b1;
-    assign m_axi_wuser        = 0;
-    assign m_axi_arid         = 0;
-    assign m_axi_arlen        = 0;
-    assign m_axi_arsize       = P_AXILITE_SIZE;
-    assign m_axi_arburst      = P_INCR;
-    assign m_axi_arlock       = 0;
-    assign m_axi_arcache      = 0;
-    assign m_axi_arregion     = 0;
-    assign m_axi_arqos        = 0;
-    assign m_axi_aruser       = 0;
-    
-    if (((C_IGNORE_ID == 1) && (C_TRANSLATION_MODE != P_CONVERSION)) || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite_passthru
-      assign m_axi_awaddr       = s_axi_awaddr;
-      assign m_axi_awprot       = s_axi_awprot;
-      assign m_axi_awvalid      = s_awvalid_i;
-      assign s_awready_i        = m_axi_awready;
-      assign m_axi_wdata        = s_axi_wdata;
-      assign m_axi_wstrb        = s_axi_wstrb;
-      assign m_axi_wvalid       = s_wvalid_i;
-      assign s_wready_i         = m_axi_wready;
-      assign s_bid_i            = 0;
-      assign s_bresp_i          = m_axi_bresp;
-      assign s_buser_i          = 0;
-      assign s_bvalid_i         = m_axi_bvalid;
-      assign m_axi_bready       = s_bready_i;
-      assign m_axi_araddr       = s_axi_araddr;
-      assign m_axi_arprot       = s_axi_arprot;
-      assign m_axi_arvalid      = s_arvalid_i;
-      assign s_arready_i        = m_axi_arready;
-      assign s_rid_i            = 0;
-      assign s_rdata_i          = m_axi_rdata;
-      assign s_rresp_i          = m_axi_rresp;
-      assign s_rlast_i          = 1'b1;
-      assign s_ruser_i          = 0;
-      assign s_rvalid_i         = m_axi_rvalid;
-      assign m_axi_rready       = s_rready_i;
-      
-    end else if (C_TRANSLATION_MODE == P_CONVERSION) begin : gen_b2s_conv
-      assign s_buser_i = {C_AXI_BUSER_WIDTH{1'b0}};
-      assign s_ruser_i = {C_AXI_RUSER_WIDTH{1'b0}};
-
-      axi_protocol_converter_v2_1_9_b2s #(
-        .C_S_AXI_PROTOCOL                 (C_S_AXI_PROTOCOL),
-        .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),
-        .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),
-        .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),
-        .C_AXI_SUPPORTS_WRITE             (C_AXI_SUPPORTS_WRITE),
-        .C_AXI_SUPPORTS_READ              (C_AXI_SUPPORTS_READ)
-      ) axilite_b2s (
-        .aresetn                          (aresetn),
-        .aclk                             (aclk),
-        .s_axi_awid                       (s_axi_awid),
-        .s_axi_awaddr                     (s_axi_awaddr),
-        .s_axi_awlen                      (s_axi_awlen),
-        .s_axi_awsize                     (s_axi_awsize),
-        .s_axi_awburst                    (s_axi_awburst),
-        .s_axi_awprot                     (s_axi_awprot),
-        .s_axi_awvalid                    (s_awvalid_i),
-        .s_axi_awready                    (s_awready_i),
-        .s_axi_wdata                      (s_axi_wdata),
-        .s_axi_wstrb                      (s_axi_wstrb),
-        .s_axi_wlast                      (s_axi_wlast),
-        .s_axi_wvalid                     (s_wvalid_i),
-        .s_axi_wready                     (s_wready_i),
-        .s_axi_bid                        (s_bid_i),
-        .s_axi_bresp                      (s_bresp_i),
-        .s_axi_bvalid                     (s_bvalid_i),
-        .s_axi_bready                     (s_bready_i),
-        .s_axi_arid                       (s_axi_arid),
-        .s_axi_araddr                     (s_axi_araddr),
-        .s_axi_arlen                      (s_axi_arlen),
-        .s_axi_arsize                     (s_axi_arsize),
-        .s_axi_arburst                    (s_axi_arburst),
-        .s_axi_arprot                     (s_axi_arprot),
-        .s_axi_arvalid                    (s_arvalid_i),
-        .s_axi_arready                    (s_arready_i),
-        .s_axi_rid                        (s_rid_i),
-        .s_axi_rdata                      (s_rdata_i),
-        .s_axi_rresp                      (s_rresp_i),
-        .s_axi_rlast                      (s_rlast_i),
-        .s_axi_rvalid                     (s_rvalid_i),
-        .s_axi_rready                     (s_rready_i),
-        .m_axi_awaddr                     (m_axi_awaddr),
-        .m_axi_awprot                     (m_axi_awprot),
-        .m_axi_awvalid                    (m_axi_awvalid),
-        .m_axi_awready                    (m_axi_awready),
-        .m_axi_wdata                      (m_axi_wdata),
-        .m_axi_wstrb                      (m_axi_wstrb),
-        .m_axi_wvalid                     (m_axi_wvalid),
-        .m_axi_wready                     (m_axi_wready),
-        .m_axi_bresp                      (m_axi_bresp),
-        .m_axi_bvalid                     (m_axi_bvalid),
-        .m_axi_bready                     (m_axi_bready),
-        .m_axi_araddr                     (m_axi_araddr),
-        .m_axi_arprot                     (m_axi_arprot),
-        .m_axi_arvalid                    (m_axi_arvalid),
-        .m_axi_arready                    (m_axi_arready),
-        .m_axi_rdata                      (m_axi_rdata),
-        .m_axi_rresp                      (m_axi_rresp),
-        .m_axi_rvalid                     (m_axi_rvalid),
-        .m_axi_rready                     (m_axi_rready)
-      );
-    end else begin : gen_axilite_conv
-      axi_protocol_converter_v2_1_9_axilite_conv #(
-        .C_FAMILY                         (C_FAMILY),
-        .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),
-        .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),
-        .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),
-        .C_AXI_SUPPORTS_WRITE             (C_AXI_SUPPORTS_WRITE),
-        .C_AXI_SUPPORTS_READ              (C_AXI_SUPPORTS_READ),
-        .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),
-        .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH)
-      ) axilite_conv_inst (
-        .ARESETN                          (aresetn),
-        .ACLK                             (aclk),
-        .S_AXI_AWID                       (s_axi_awid),
-        .S_AXI_AWADDR                     (s_axi_awaddr),
-        .S_AXI_AWPROT                     (s_axi_awprot),
-        .S_AXI_AWVALID                    (s_awvalid_i),
-        .S_AXI_AWREADY                    (s_awready_i),
-        .S_AXI_WDATA                      (s_axi_wdata),
-        .S_AXI_WSTRB                      (s_axi_wstrb),
-        .S_AXI_WVALID                     (s_wvalid_i),
-        .S_AXI_WREADY                     (s_wready_i),
-        .S_AXI_BID                        (s_bid_i),
-        .S_AXI_BRESP                      (s_bresp_i),
-        .S_AXI_BUSER                      (s_buser_i),
-        .S_AXI_BVALID                     (s_bvalid_i),
-        .S_AXI_BREADY                     (s_bready_i),
-        .S_AXI_ARID                       (s_axi_arid),
-        .S_AXI_ARADDR                     (s_axi_araddr),
-        .S_AXI_ARPROT                     (s_axi_arprot),
-        .S_AXI_ARVALID                    (s_arvalid_i),
-        .S_AXI_ARREADY                    (s_arready_i),
-        .S_AXI_RID                        (s_rid_i),
-        .S_AXI_RDATA                      (s_rdata_i),
-        .S_AXI_RRESP                      (s_rresp_i),
-        .S_AXI_RLAST                      (s_rlast_i),
-        .S_AXI_RUSER                      (s_ruser_i),
-        .S_AXI_RVALID                     (s_rvalid_i),
-        .S_AXI_RREADY                     (s_rready_i),
-        .M_AXI_AWADDR                     (m_axi_awaddr),
-        .M_AXI_AWPROT                     (m_axi_awprot),
-        .M_AXI_AWVALID                    (m_axi_awvalid),
-        .M_AXI_AWREADY                    (m_axi_awready),
-        .M_AXI_WDATA                      (m_axi_wdata),
-        .M_AXI_WSTRB                      (m_axi_wstrb),
-        .M_AXI_WVALID                     (m_axi_wvalid),
-        .M_AXI_WREADY                     (m_axi_wready),
-        .M_AXI_BRESP                      (m_axi_bresp),
-        .M_AXI_BVALID                     (m_axi_bvalid),
-        .M_AXI_BREADY                     (m_axi_bready),
-        .M_AXI_ARADDR                     (m_axi_araddr),
-        .M_AXI_ARPROT                     (m_axi_arprot),
-        .M_AXI_ARVALID                    (m_axi_arvalid),
-        .M_AXI_ARREADY                    (m_axi_arready),
-        .M_AXI_RDATA                      (m_axi_rdata),
-        .M_AXI_RRESP                      (m_axi_rresp),
-        .M_AXI_RVALID                     (m_axi_rvalid),
-        .M_AXI_RREADY                     (m_axi_rready)
-      );
-    end
-  end else if ((C_M_AXI_PROTOCOL == P_AXI3) && (C_S_AXI_PROTOCOL == P_AXI4)) begin : gen_axi4_axi3
-    axi_protocol_converter_v2_1_9_axi3_conv #(
-      .C_FAMILY                         (C_FAMILY),
-      .C_AXI_ID_WIDTH                   (C_AXI_ID_WIDTH),
-      .C_AXI_ADDR_WIDTH                 (C_AXI_ADDR_WIDTH),
-      .C_AXI_DATA_WIDTH                 (C_AXI_DATA_WIDTH),
-      .C_AXI_SUPPORTS_USER_SIGNALS      (C_AXI_SUPPORTS_USER_SIGNALS),
-      .C_AXI_AWUSER_WIDTH               (C_AXI_AWUSER_WIDTH),
-      .C_AXI_ARUSER_WIDTH               (C_AXI_ARUSER_WIDTH),
-      .C_AXI_WUSER_WIDTH                (C_AXI_WUSER_WIDTH),
-      .C_AXI_RUSER_WIDTH                (C_AXI_RUSER_WIDTH),
-      .C_AXI_BUSER_WIDTH                (C_AXI_BUSER_WIDTH),
-      .C_AXI_SUPPORTS_WRITE             (C_AXI_SUPPORTS_WRITE),
-      .C_AXI_SUPPORTS_READ              (C_AXI_SUPPORTS_READ),
-      .C_SUPPORT_SPLITTING              ((C_TRANSLATION_MODE == P_CONVERSION) ? 1 : 0)
-    ) axi3_conv_inst (
-      .ARESETN                          (aresetn),
-      .ACLK                             (aclk),
-      .S_AXI_AWID                       (s_axi_awid),
-      .S_AXI_AWADDR                     (s_axi_awaddr),
-      .S_AXI_AWLEN                      (s_axi_awlen),
-      .S_AXI_AWSIZE                     (s_axi_awsize),
-      .S_AXI_AWBURST                    (s_axi_awburst),
-      .S_AXI_AWLOCK                     (s_axi_awlock),
-      .S_AXI_AWCACHE                    (s_axi_awcache),
-      .S_AXI_AWPROT                     (s_axi_awprot),
-      .S_AXI_AWQOS                      (s_axi_awqos),
-      .S_AXI_AWUSER                     (s_axi_awuser),
-      .S_AXI_AWVALID                    (s_awvalid_i),
-      .S_AXI_AWREADY                    (s_awready_i),
-      .S_AXI_WDATA                      (s_axi_wdata),
-      .S_AXI_WSTRB                      (s_axi_wstrb),
-      .S_AXI_WLAST                      (s_axi_wlast),
-      .S_AXI_WUSER                      (s_axi_wuser),
-      .S_AXI_WVALID                     (s_wvalid_i),
-      .S_AXI_WREADY                     (s_wready_i),
-      .S_AXI_BID                        (s_bid_i),
-      .S_AXI_BRESP                      (s_bresp_i),
-      .S_AXI_BUSER                      (s_buser_i),
-      .S_AXI_BVALID                     (s_bvalid_i),
-      .S_AXI_BREADY                     (s_bready_i),
-      .S_AXI_ARID                       (s_axi_arid),
-      .S_AXI_ARADDR                     (s_axi_araddr),
-      .S_AXI_ARLEN                      (s_axi_arlen),
-      .S_AXI_ARSIZE                     (s_axi_arsize),
-      .S_AXI_ARBURST                    (s_axi_arburst),
-      .S_AXI_ARLOCK                     (s_axi_arlock),
-      .S_AXI_ARCACHE                    (s_axi_arcache),
-      .S_AXI_ARPROT                     (s_axi_arprot),
-      .S_AXI_ARQOS                      (s_axi_arqos),
-      .S_AXI_ARUSER                     (s_axi_aruser),
-      .S_AXI_ARVALID                    (s_arvalid_i),
-      .S_AXI_ARREADY                    (s_arready_i),
-      .S_AXI_RID                        (s_rid_i),
-      .S_AXI_RDATA                      (s_rdata_i),
-      .S_AXI_RRESP                      (s_rresp_i),
-      .S_AXI_RLAST                      (s_rlast_i),
-      .S_AXI_RUSER                      (s_ruser_i),
-      .S_AXI_RVALID                     (s_rvalid_i),
-      .S_AXI_RREADY                     (s_rready_i),
-      .M_AXI_AWID                       (m_axi_awid),
-      .M_AXI_AWADDR                     (m_axi_awaddr),
-      .M_AXI_AWLEN                      (m_axi_awlen),
-      .M_AXI_AWSIZE                     (m_axi_awsize),
-      .M_AXI_AWBURST                    (m_axi_awburst),
-      .M_AXI_AWLOCK                     (m_axi_awlock),
-      .M_AXI_AWCACHE                    (m_axi_awcache),
-      .M_AXI_AWPROT                     (m_axi_awprot),
-      .M_AXI_AWQOS                      (m_axi_awqos),
-      .M_AXI_AWUSER                     (m_axi_awuser),
-      .M_AXI_AWVALID                    (m_axi_awvalid),
-      .M_AXI_AWREADY                    (m_axi_awready),
-      .M_AXI_WID                        (m_axi_wid),
-      .M_AXI_WDATA                      (m_axi_wdata),
-      .M_AXI_WSTRB                      (m_axi_wstrb),
-      .M_AXI_WLAST                      (m_axi_wlast),
-      .M_AXI_WUSER                      (m_axi_wuser),
-      .M_AXI_WVALID                     (m_axi_wvalid),
-      .M_AXI_WREADY                     (m_axi_wready),
-      .M_AXI_BID                        (m_axi_bid),
-      .M_AXI_BRESP                      (m_axi_bresp),
-      .M_AXI_BUSER                      (m_axi_buser),
-      .M_AXI_BVALID                     (m_axi_bvalid),
-      .M_AXI_BREADY                     (m_axi_bready),
-      .M_AXI_ARID                       (m_axi_arid),
-      .M_AXI_ARADDR                     (m_axi_araddr),
-      .M_AXI_ARLEN                      (m_axi_arlen),
-      .M_AXI_ARSIZE                     (m_axi_arsize),
-      .M_AXI_ARBURST                    (m_axi_arburst),
-      .M_AXI_ARLOCK                     (m_axi_arlock),
-      .M_AXI_ARCACHE                    (m_axi_arcache),
-      .M_AXI_ARPROT                     (m_axi_arprot),
-      .M_AXI_ARQOS                      (m_axi_arqos),
-      .M_AXI_ARUSER                     (m_axi_aruser),
-      .M_AXI_ARVALID                    (m_axi_arvalid),
-      .M_AXI_ARREADY                    (m_axi_arready),
-      .M_AXI_RID                        (m_axi_rid),
-      .M_AXI_RDATA                      (m_axi_rdata),
-      .M_AXI_RRESP                      (m_axi_rresp),
-      .M_AXI_RLAST                      (m_axi_rlast),
-      .M_AXI_RUSER                      (m_axi_ruser),
-      .M_AXI_RVALID                     (m_axi_rvalid),
-      .M_AXI_RREADY                     (m_axi_rready)
-    );
-    assign m_axi_awregion     = 0;
-    assign m_axi_arregion     = 0;
-    
-  end else if ((C_S_AXI_PROTOCOL == P_AXI3) && (C_M_AXI_PROTOCOL == P_AXI4)) begin : gen_axi3_axi4
-    assign m_axi_awid                = s_axi_awid;
-    assign m_axi_awaddr              = s_axi_awaddr;
-    assign m_axi_awlen               = {4'h0, s_axi_awlen[3:0]};
-    assign m_axi_awsize              = s_axi_awsize;
-    assign m_axi_awburst             = s_axi_awburst;
-    assign m_axi_awlock              = s_axi_awlock[0];
-    assign m_axi_awcache             = s_axi_awcache;
-    assign m_axi_awprot              = s_axi_awprot;
-    assign m_axi_awregion            = 4'h0;
-    assign m_axi_awqos               = s_axi_awqos;
-    assign m_axi_awuser              = s_axi_awuser;
-    assign m_axi_awvalid             = s_awvalid_i;
-    assign s_awready_i               = m_axi_awready;
-    assign m_axi_wid                 = {C_AXI_ID_WIDTH{1'b0}} ;
-    assign m_axi_wdata               = s_axi_wdata;
-    assign m_axi_wstrb               = s_axi_wstrb;
-    assign m_axi_wlast               = s_axi_wlast;
-    assign m_axi_wuser               = s_axi_wuser;
-    assign m_axi_wvalid              = s_wvalid_i;
-    assign s_wready_i                = m_axi_wready;
-    assign s_bid_i                   = m_axi_bid;
-    assign s_bresp_i                 = m_axi_bresp;
-    assign s_buser_i                 = m_axi_buser;
-    assign s_bvalid_i                = m_axi_bvalid;
-    assign m_axi_bready              = s_bready_i;
-    assign m_axi_arid                = s_axi_arid;
-    assign m_axi_araddr              = s_axi_araddr;
-    assign m_axi_arlen               = {4'h0, s_axi_arlen[3:0]};
-    assign m_axi_arsize              = s_axi_arsize;
-    assign m_axi_arburst             = s_axi_arburst;
-    assign m_axi_arlock              = s_axi_arlock[0];
-    assign m_axi_arcache             = s_axi_arcache;
-    assign m_axi_arprot              = s_axi_arprot;
-    assign m_axi_arregion            = 4'h0;
-    assign m_axi_arqos               = s_axi_arqos;
-    assign m_axi_aruser              = s_axi_aruser;
-    assign m_axi_arvalid             = s_arvalid_i;
-    assign s_arready_i               = m_axi_arready;
-    assign s_rid_i                   = m_axi_rid;
-    assign s_rdata_i                 = m_axi_rdata;
-    assign s_rresp_i                 = m_axi_rresp;
-    assign s_rlast_i                 = m_axi_rlast;
-    assign s_ruser_i                 = m_axi_ruser;
-    assign s_rvalid_i                = m_axi_rvalid;
-    assign m_axi_rready              = s_rready_i;
-    
-  end else begin :gen_no_conv
-    assign m_axi_awid                = s_axi_awid;
-    assign m_axi_awaddr              = s_axi_awaddr;
-    assign m_axi_awlen               = s_axi_awlen;
-    assign m_axi_awsize              = s_axi_awsize;
-    assign m_axi_awburst             = s_axi_awburst;
-    assign m_axi_awlock              = s_axi_awlock;
-    assign m_axi_awcache             = s_axi_awcache;
-    assign m_axi_awprot              = s_axi_awprot;
-    assign m_axi_awregion            = s_axi_awregion;
-    assign m_axi_awqos               = s_axi_awqos;
-    assign m_axi_awuser              = s_axi_awuser;
-    assign m_axi_awvalid             = s_awvalid_i;
-    assign s_awready_i               = m_axi_awready;
-    assign m_axi_wid                 = s_axi_wid;
-    assign m_axi_wdata               = s_axi_wdata;
-    assign m_axi_wstrb               = s_axi_wstrb;
-    assign m_axi_wlast               = s_axi_wlast;
-    assign m_axi_wuser               = s_axi_wuser;
-    assign m_axi_wvalid              = s_wvalid_i;
-    assign s_wready_i                = m_axi_wready;
-    assign s_bid_i                   = m_axi_bid;
-    assign s_bresp_i                 = m_axi_bresp;
-    assign s_buser_i                 = m_axi_buser;
-    assign s_bvalid_i                = m_axi_bvalid;
-    assign m_axi_bready              = s_bready_i;
-    assign m_axi_arid                = s_axi_arid;
-    assign m_axi_araddr              = s_axi_araddr;
-    assign m_axi_arlen               = s_axi_arlen;
-    assign m_axi_arsize              = s_axi_arsize;
-    assign m_axi_arburst             = s_axi_arburst;
-    assign m_axi_arlock              = s_axi_arlock;
-    assign m_axi_arcache             = s_axi_arcache;
-    assign m_axi_arprot              = s_axi_arprot;
-    assign m_axi_arregion            = s_axi_arregion;
-    assign m_axi_arqos               = s_axi_arqos;
-    assign m_axi_aruser              = s_axi_aruser;
-    assign m_axi_arvalid             = s_arvalid_i;
-    assign s_arready_i               = m_axi_arready;
-    assign s_rid_i                   = m_axi_rid;
-    assign s_rdata_i                 = m_axi_rdata;
-    assign s_rresp_i                 = m_axi_rresp;
-    assign s_rlast_i                 = m_axi_rlast;
-    assign s_ruser_i                 = m_axi_ruser;
-    assign s_rvalid_i                = m_axi_rvalid;
-    assign m_axi_rready              = s_rready_i;
-  end
-  
-    if ((C_TRANSLATION_MODE == P_PROTECTION) && 
-        (((C_S_AXI_PROTOCOL != P_AXILITE) && (C_M_AXI_PROTOCOL == P_AXILITE)) ||
-        ((C_S_AXI_PROTOCOL == P_AXI4) && (C_M_AXI_PROTOCOL == P_AXI3)))) begin : gen_err_detect
-
-      wire                           e_awvalid;
-      reg                            e_awvalid_r;
-      wire                           e_arvalid;
-      reg                            e_arvalid_r;
-      wire                           e_wvalid;
-      wire                           e_bvalid;
-      wire                           e_rvalid;
-      reg                            e_awready;
-      reg                            e_arready;
-      wire                           e_wready;
-      reg  [C_AXI_ID_WIDTH-1:0]      e_awid;
-      reg  [C_AXI_ID_WIDTH-1:0]      e_arid;
-      reg  [8-1:0]                   e_arlen;
-      wire [C_AXI_ID_WIDTH-1:0]      e_bid;
-      wire [C_AXI_ID_WIDTH-1:0]      e_rid;
-      wire                           e_rlast;
-      wire                           w_err;
-      wire                           r_err;
-      wire                           busy_aw;
-      wire                           busy_w;
-      wire                           busy_ar;
-      wire                           aw_push;
-      wire                           aw_pop;
-      wire                           w_pop;
-      wire                           ar_push;
-      wire                           ar_pop;
-      reg                            s_awvalid_pending;
-      reg                            s_awvalid_en;
-      reg                            s_arvalid_en;
-      reg                            s_awready_en;
-      reg                            s_arready_en;
-      reg  [4:0]                     aw_cnt;
-      reg  [4:0]                     ar_cnt;
-      reg  [4:0]                     w_cnt;
-      reg                            w_borrow;
-      reg                            err_busy_w;
-      reg                            err_busy_r;
-
-      assign w_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_awlen != 0) : ((s_axi_awlen>>4) != 0);
-      assign r_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_arlen != 0) : ((s_axi_arlen>>4) != 0);
-      assign s_awvalid_i = s_axi_awvalid & s_awvalid_en & ~w_err;
-      assign e_awvalid   = e_awvalid_r & ~busy_aw & ~busy_w;
-      assign s_arvalid_i = s_axi_arvalid & s_arvalid_en & ~r_err;
-      assign e_arvalid   = e_arvalid_r & ~busy_ar ;
-      assign s_wvalid_i = s_axi_wvalid & (busy_w | (s_awvalid_pending & ~w_borrow));
-      assign e_wvalid   = s_axi_wvalid & err_busy_w;
-      assign s_bready_i = s_axi_bready & busy_aw;
-      assign s_rready_i = s_axi_rready & busy_ar;
-      assign s_axi_awready = (s_awready_i & s_awready_en) | e_awready; 
-      assign s_axi_wready = (s_wready_i & (busy_w | (s_awvalid_pending & ~w_borrow))) | e_wready;
-      assign s_axi_bvalid = (s_bvalid_i & busy_aw) | e_bvalid;
-      assign s_axi_bid = err_busy_w ? e_bid : s_bid_i;
-      assign s_axi_bresp = err_busy_w ? P_SLVERR : s_bresp_i;
-      assign s_axi_buser = err_busy_w ? {C_AXI_BUSER_WIDTH{1'b0}} : s_buser_i;
-      assign s_axi_arready = (s_arready_i & s_arready_en) | e_arready; 
-      assign s_axi_rvalid = (s_rvalid_i & busy_ar) | e_rvalid;
-      assign s_axi_rid = err_busy_r ? e_rid : s_rid_i;
-      assign s_axi_rresp = err_busy_r ? P_SLVERR : s_rresp_i;
-      assign s_axi_ruser = err_busy_r ? {C_AXI_RUSER_WIDTH{1'b0}} : s_ruser_i;
-      assign s_axi_rdata = err_busy_r ? {C_AXI_DATA_WIDTH{1'b0}} : s_rdata_i;
-      assign s_axi_rlast = err_busy_r ? e_rlast : s_rlast_i;
-      assign busy_aw = (aw_cnt != 0);
-      assign busy_w  = (w_cnt != 0);
-      assign busy_ar = (ar_cnt != 0);
-      assign aw_push = s_awvalid_i & s_awready_i & s_awready_en;
-      assign aw_pop  = s_bvalid_i & s_bready_i;
-      assign w_pop   = s_wvalid_i & s_wready_i & s_axi_wlast;
-      assign ar_push = s_arvalid_i & s_arready_i & s_arready_en;
-      assign ar_pop  = s_rvalid_i & s_rready_i & s_rlast_i;
-      
-      always @(posedge aclk) begin
-        if (~aresetn) begin
-          s_awvalid_en <= 1'b0;
-          s_arvalid_en <= 1'b0;
-          s_awready_en <= 1'b0;
-          s_arready_en <= 1'b0;
-          e_awvalid_r <= 1'b0;
-          e_arvalid_r <= 1'b0;
-          e_awready <= 1'b0;
-          e_arready <= 1'b0;
-          aw_cnt <= 0;
-          w_cnt <= 0;
-          ar_cnt <= 0;
-          err_busy_w <= 1'b0;
-          err_busy_r <= 1'b0;
-          w_borrow <= 1'b0;
-          s_awvalid_pending <= 1'b0;
-        end else begin
-          e_awready <= 1'b0;  // One-cycle pulse
-          if (e_bvalid & s_axi_bready) begin
-            s_awvalid_en <= 1'b1;
-            s_awready_en <= 1'b1;
-            err_busy_w <= 1'b0;
-          end else if (e_awvalid) begin
-            e_awvalid_r <= 1'b0;
-            err_busy_w <= 1'b1;
-          end else if (s_axi_awvalid & w_err & ~e_awvalid_r & ~err_busy_w) begin
-            e_awvalid_r <= 1'b1;
-            e_awready <= ~(s_awready_i & s_awvalid_en);  // 1-cycle pulse if awready not already asserted
-            s_awvalid_en <= 1'b0;
-            s_awready_en <= 1'b0;
-          end else if ((&aw_cnt) | (&w_cnt) | aw_push) begin
-            s_awvalid_en <= 1'b0;
-            s_awready_en <= 1'b0;
-          end else if (~err_busy_w & ~e_awvalid_r & ~(s_axi_awvalid & w_err)) begin
-            s_awvalid_en <= 1'b1;
-            s_awready_en <= 1'b1;
-          end
-          
-          if (aw_push & ~aw_pop) begin
-            aw_cnt <= aw_cnt + 1;
-          end else if (~aw_push & aw_pop & (|aw_cnt)) begin
-            aw_cnt <= aw_cnt - 1;
-          end
-          if (aw_push) begin
-            if (~w_pop & ~w_borrow) begin
-              w_cnt <= w_cnt + 1;
-            end
-            w_borrow <= 1'b0;
-          end else if (~aw_push & w_pop) begin
-            if (|w_cnt) begin
-              w_cnt <= w_cnt - 1;
-            end else begin
-              w_borrow <= 1'b1;
-            end
-          end
-          s_awvalid_pending <= s_awvalid_i & ~s_awready_i;
-          
-          e_arready <= 1'b0;  // One-cycle pulse
-          if (e_rvalid & s_axi_rready & e_rlast) begin
-            s_arvalid_en <= 1'b1;
-            s_arready_en <= 1'b1;
-            err_busy_r <= 1'b0;
-          end else if (e_arvalid) begin
-            e_arvalid_r <= 1'b0;
-            err_busy_r <= 1'b1;
-          end else if (s_axi_arvalid & r_err & ~e_arvalid_r & ~err_busy_r) begin
-            e_arvalid_r <= 1'b1;
-            e_arready <= ~(s_arready_i & s_arvalid_en);  // 1-cycle pulse if arready not already asserted
-            s_arvalid_en <= 1'b0;
-            s_arready_en <= 1'b0;
-          end else if ((&ar_cnt) | ar_push) begin
-            s_arvalid_en <= 1'b0;
-            s_arready_en <= 1'b0;
-          end else if (~err_busy_r & ~e_arvalid_r & ~(s_axi_arvalid & r_err)) begin
-            s_arvalid_en <= 1'b1;
-            s_arready_en <= 1'b1;
-          end
-          
-          if (ar_push & ~ar_pop) begin
-            ar_cnt <= ar_cnt + 1;
-          end else if (~ar_push & ar_pop & (|ar_cnt)) begin
-            ar_cnt <= ar_cnt - 1;
-          end
-        end
-      end
-      
-      always @(posedge aclk) begin
-        if (s_axi_awvalid & ~err_busy_w & ~e_awvalid_r ) begin
-          e_awid <= s_axi_awid;
-        end
-        if (s_axi_arvalid & ~err_busy_r & ~e_arvalid_r ) begin
-          e_arid <= s_axi_arid;
-          e_arlen <= s_axi_arlen;
-        end
-      end
-      
-      axi_protocol_converter_v2_1_9_decerr_slave #
-        (
-         .C_AXI_ID_WIDTH                 (C_AXI_ID_WIDTH),
-         .C_AXI_DATA_WIDTH               (C_AXI_DATA_WIDTH),
-         .C_AXI_RUSER_WIDTH              (C_AXI_RUSER_WIDTH),
-         .C_AXI_BUSER_WIDTH              (C_AXI_BUSER_WIDTH),
-         .C_AXI_PROTOCOL                 (C_S_AXI_PROTOCOL),
-         .C_RESP                         (P_SLVERR),
-         .C_IGNORE_ID                    (C_IGNORE_ID)
-        )
-        decerr_slave_inst
-          (
-           .ACLK (aclk),
-           .ARESETN (aresetn),
-           .S_AXI_AWID (e_awid),
-           .S_AXI_AWVALID (e_awvalid),
-           .S_AXI_AWREADY (),
-           .S_AXI_WLAST (s_axi_wlast),
-           .S_AXI_WVALID (e_wvalid),
-           .S_AXI_WREADY (e_wready),
-           .S_AXI_BID (e_bid),
-           .S_AXI_BRESP (),
-           .S_AXI_BUSER (),
-           .S_AXI_BVALID (e_bvalid),
-           .S_AXI_BREADY (s_axi_bready),
-           .S_AXI_ARID (e_arid),
-           .S_AXI_ARLEN (e_arlen),
-           .S_AXI_ARVALID (e_arvalid),
-           .S_AXI_ARREADY (),
-           .S_AXI_RID (e_rid),
-           .S_AXI_RDATA (),
-           .S_AXI_RRESP (),
-           .S_AXI_RUSER (),
-           .S_AXI_RLAST (e_rlast),
-           .S_AXI_RVALID (e_rvalid),
-           .S_AXI_RREADY (s_axi_rready)
-         );
-    end else begin : gen_no_err_detect
-      assign s_awvalid_i = s_axi_awvalid;
-      assign s_arvalid_i = s_axi_arvalid;
-      assign s_wvalid_i = s_axi_wvalid;
-      assign s_bready_i = s_axi_bready;
-      assign s_rready_i = s_axi_rready;
-      assign s_axi_awready = s_awready_i; 
-      assign s_axi_wready = s_wready_i;
-      assign s_axi_bvalid = s_bvalid_i;
-      assign s_axi_bid = s_bid_i;
-      assign s_axi_bresp = s_bresp_i;
-      assign s_axi_buser = s_buser_i;
-      assign s_axi_arready = s_arready_i; 
-      assign s_axi_rvalid = s_rvalid_i;
-      assign s_axi_rid = s_rid_i;
-      assign s_axi_rresp = s_rresp_i;
-      assign s_axi_ruser = s_ruser_i;
-      assign s_axi_rdata = s_rdata_i;
-      assign s_axi_rlast = s_rlast_i;
-    end  // gen_err_detect
-endgenerate
-
-endmodule
-
-`default_nettype wire
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v
deleted file mode 100755
index 8874e002a24438e74981c36af474a72d0955191f..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v
+++ /dev/null
@@ -1,233 +0,0 @@
-// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
-// --
-// -- This file contains confidential and proprietary information
-// -- of Xilinx, Inc. and is protected under U.S. and 
-// -- international copyright and other intellectual property
-// -- laws.
-// --
-// -- DISCLAIMER
-// -- This disclaimer is not a license and does not grant any
-// -- rights to the materials distributed herewith. Except as
-// -- otherwise provided in a valid license issued to you by
-// -- Xilinx, and to the maximum extent permitted by applicable
-// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// -- (2) Xilinx shall not be liable (whether in contract or tort,
-// -- including negligence, or under any other theory of
-// -- liability) for any loss or damage of any kind or nature
-// -- related to, arising under or in connection with these
-// -- materials, including for any direct, or any indirect,
-// -- special, incidental, or consequential loss or damage
-// -- (including loss of data, profits, goodwill, or any type of
-// -- loss or damage suffered as a result of any action brought
-// -- by a third party) even if such damage or loss was
-// -- reasonably foreseeable or Xilinx had been advised of the
-// -- possibility of the same.
-// --
-// -- CRITICAL APPLICATIONS
-// -- Xilinx products are not designed or intended to be fail-
-// -- safe, or for use in any application requiring fail-safe
-// -- performance, such as life-support or safety devices or
-// -- systems, Class III medical devices, nuclear facilities,
-// -- applications related to the deployment of airbags, or any
-// -- other applications that could lead to death, personal
-// -- injury, or severe property or environmental damage
-// -- (individually and collectively, "Critical
-// -- Applications"). Customer assumes the sole risk and
-// -- liability of any use of Xilinx products in Critical
-// -- Applications, subject only to applicable laws and
-// -- regulations governing limitations on product liability.
-// --
-// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// -- PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-//
-// Description: AxiLite Slave Conversion
-//
-// Verilog-standard:  Verilog 2001
-//--------------------------------------------------------------------------
-//
-// Structure:
-//   axilite_conv
-//
-//--------------------------------------------------------------------------
-`timescale 1ps/1ps
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_axilite_conv #
-  (
-   parameter         C_FAMILY                    = "virtex6",
-   parameter integer C_AXI_ID_WIDTH              = 1,
-   parameter integer C_AXI_ADDR_WIDTH            = 32,
-   parameter integer C_AXI_DATA_WIDTH            = 32,
-   parameter integer C_AXI_SUPPORTS_WRITE        = 1,
-   parameter integer C_AXI_SUPPORTS_READ         = 1,
-   parameter integer C_AXI_RUSER_WIDTH                = 1,
-   parameter integer C_AXI_BUSER_WIDTH                = 1
-   )
-  (
-   // System Signals
-   input  wire                          ACLK,
-   input  wire                          ARESETN,
-   // Slave Interface Write Address Ports
-   input  wire [C_AXI_ID_WIDTH-1:0]     S_AXI_AWID,
-   input  wire [C_AXI_ADDR_WIDTH-1:0]   S_AXI_AWADDR,
-   input  wire [3-1:0]                  S_AXI_AWPROT,
-   input  wire                          S_AXI_AWVALID,
-   output wire                          S_AXI_AWREADY,
-   // Slave Interface Write Data Ports
-   input  wire [C_AXI_DATA_WIDTH-1:0]   S_AXI_WDATA,
-   input  wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
-   input  wire                          S_AXI_WVALID,
-   output wire                          S_AXI_WREADY,
-   // Slave Interface Write Response Ports
-   output wire [C_AXI_ID_WIDTH-1:0]     S_AXI_BID,
-   output wire [2-1:0]                  S_AXI_BRESP,
-   output wire [C_AXI_BUSER_WIDTH-1:0]  S_AXI_BUSER,    // Constant =0
-   output wire                          S_AXI_BVALID,
-   input  wire                          S_AXI_BREADY,
-   // Slave Interface Read Address Ports
-   input  wire [C_AXI_ID_WIDTH-1:0]     S_AXI_ARID,
-   input  wire [C_AXI_ADDR_WIDTH-1:0]   S_AXI_ARADDR,
-   input  wire [3-1:0]                  S_AXI_ARPROT,
-   input  wire                          S_AXI_ARVALID,
-   output wire                          S_AXI_ARREADY,
-   // Slave Interface Read Data Ports
-   output wire [C_AXI_ID_WIDTH-1:0]     S_AXI_RID,
-   output wire [C_AXI_DATA_WIDTH-1:0]   S_AXI_RDATA,
-   output wire [2-1:0]                  S_AXI_RRESP,
-   output wire                          S_AXI_RLAST,    // Constant =1
-   output wire [C_AXI_RUSER_WIDTH-1:0]  S_AXI_RUSER,    // Constant =0
-   output wire                          S_AXI_RVALID,
-   input  wire                          S_AXI_RREADY,
-   
-   // Master Interface Write Address Port
-   output wire [C_AXI_ADDR_WIDTH-1:0]   M_AXI_AWADDR,
-   output wire [3-1:0]                  M_AXI_AWPROT,
-   output wire                          M_AXI_AWVALID,
-   input  wire                          M_AXI_AWREADY,
-   // Master Interface Write Data Ports
-   output wire [C_AXI_DATA_WIDTH-1:0]   M_AXI_WDATA,
-   output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
-   output wire                          M_AXI_WVALID,
-   input  wire                          M_AXI_WREADY,
-   // Master Interface Write Response Ports
-   input  wire [2-1:0]                  M_AXI_BRESP,
-   input  wire                          M_AXI_BVALID,
-   output wire                          M_AXI_BREADY,
-   // Master Interface Read Address Port
-   output wire [C_AXI_ADDR_WIDTH-1:0]   M_AXI_ARADDR,
-   output wire [3-1:0]                  M_AXI_ARPROT,
-   output wire                          M_AXI_ARVALID,
-   input  wire                          M_AXI_ARREADY,
-   // Master Interface Read Data Ports
-   input  wire [C_AXI_DATA_WIDTH-1:0]   M_AXI_RDATA,
-   input  wire [2-1:0]                  M_AXI_RRESP,
-   input  wire                          M_AXI_RVALID,
-   output wire                          M_AXI_RREADY
-  );
-
-  wire s_awvalid_i;
-  wire s_arvalid_i;
-  wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr;
-
-  // Arbiter
-  reg read_active;
-  reg write_active;
-  reg busy;
-
-  wire read_req;
-  wire write_req;
-  wire read_complete;
-  wire write_complete;
-  
-  reg [1:0] areset_d; // Reset delay register
-  always @(posedge ACLK) begin
-    areset_d <= {areset_d[0], ~ARESETN};
-  end
-  
-  assign s_awvalid_i = S_AXI_AWVALID & (C_AXI_SUPPORTS_WRITE != 0);
-  assign s_arvalid_i = S_AXI_ARVALID & (C_AXI_SUPPORTS_READ != 0);
-
-  assign read_req  = s_arvalid_i & ~busy & ~|areset_d & ~write_active;
-  assign write_req = s_awvalid_i & ~busy & ~|areset_d & ((~read_active & ~s_arvalid_i) | write_active);
-
-  assign read_complete  = M_AXI_RVALID & S_AXI_RREADY;
-  assign write_complete = M_AXI_BVALID & S_AXI_BREADY;
-
-  always @(posedge ACLK) begin : arbiter_read_ff
-    if (|areset_d)
-      read_active <= 1'b0;
-    else if (read_complete)
-      read_active <= 1'b0;
-    else if (read_req)
-      read_active <= 1'b1;
-  end
-
-  always @(posedge ACLK) begin : arbiter_write_ff
-    if (|areset_d)
-      write_active <= 1'b0;
-    else if (write_complete)
-      write_active <= 1'b0;
-    else if (write_req)
-      write_active <= 1'b1;
-  end
-
-  always @(posedge ACLK) begin : arbiter_busy_ff
-    if (|areset_d)
-      busy <= 1'b0;
-    else if (read_complete | write_complete)
-      busy <= 1'b0;
-    else if ((write_req & M_AXI_AWREADY) | (read_req & M_AXI_ARREADY))
-      busy <= 1'b1;
-  end
-
-  assign M_AXI_ARVALID = read_req;
-  assign S_AXI_ARREADY = M_AXI_ARREADY & read_req;
-
-  assign M_AXI_AWVALID = write_req;
-  assign S_AXI_AWREADY = M_AXI_AWREADY & write_req;
-
-  assign M_AXI_RREADY  = S_AXI_RREADY & read_active;
-  assign S_AXI_RVALID  = M_AXI_RVALID & read_active;
-
-  assign M_AXI_BREADY  = S_AXI_BREADY & write_active;
-  assign S_AXI_BVALID  = M_AXI_BVALID & write_active;
-
-  // Address multiplexer
-  assign m_axaddr = (read_req | (C_AXI_SUPPORTS_WRITE == 0)) ? S_AXI_ARADDR : S_AXI_AWADDR;
-
-  // Id multiplexer and flip-flop
-  reg [C_AXI_ID_WIDTH-1:0] s_axid;
-
-  always @(posedge ACLK) begin : axid
-    if      (read_req)  s_axid <= S_AXI_ARID;
-    else if (write_req) s_axid <= S_AXI_AWID;
-  end
-
-  assign S_AXI_BID = s_axid;
-  assign S_AXI_RID = s_axid;
-
-  assign M_AXI_AWADDR = m_axaddr;
-  assign M_AXI_ARADDR = m_axaddr;
-
-
-  // Feed-through signals
-  assign S_AXI_WREADY   = M_AXI_WREADY & ~|areset_d;
-  assign S_AXI_BRESP    = M_AXI_BRESP;
-  assign S_AXI_RDATA    = M_AXI_RDATA;
-  assign S_AXI_RRESP    = M_AXI_RRESP;
-  assign S_AXI_RLAST    = 1'b1;
-  assign S_AXI_BUSER    = {C_AXI_BUSER_WIDTH{1'b0}};
-  assign S_AXI_RUSER    = {C_AXI_RUSER_WIDTH{1'b0}};
-
-  assign M_AXI_AWPROT   = S_AXI_AWPROT;
-  assign M_AXI_WVALID   = S_AXI_WVALID & ~|areset_d;
-  assign M_AXI_WDATA    = S_AXI_WDATA;
-  assign M_AXI_WSTRB    = S_AXI_WSTRB;
-  assign M_AXI_ARPROT   = S_AXI_ARPROT;
-
-endmodule
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v
deleted file mode 100755
index 18d806d0e75a23da062d330fef7348bb6849dafd..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v
+++ /dev/null
@@ -1,557 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//
-// File name: axi_protocol_converter_v2_1_9_b2s.v
-//
-// Description:
-// To handle AXI4 transactions to external memory on Virtex-6 architectures
-// requires a bridge to convert the AXI4 transactions to the memory
-// controller(MC) user interface.  The MC user interface has bidirectional
-// data path and supports data width of 256/128/64/32 bits.
-// The bridge is designed to allow AXI4 IP masters to communicate with
-// the MC user interface.
-//
-//
-// Specifications:
-// AXI4 Slave Side:
-// Configurable data width of 32, 64, 128, 256
-// Read acceptance depth is:
-// Write acceptance depth is:
-//
-// Structure:
-// axi_protocol_converter_v2_1_9_b2s
-//   WRITE_BUNDLE
-//     aw_channel_0
-//       cmd_translator_0
-//       rd_cmd_fsm_0
-//     w_channel_0
-//     b_channel_0
-//   READ_BUNDLE
-//     ar_channel_0
-//       cmd_translator_0
-//       rd_cmd_fsm_0
-//     r_channel_0
-//
-///////////////////////////////////////////////////////////////////////////////
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_b2s #(
-  parameter C_S_AXI_PROTOCOL                      = 0,
-                    // Width of all master and slave ID signals.
-                    // Range: >= 1.
-  parameter integer C_AXI_ID_WIDTH                = 4,
-  parameter integer C_AXI_ADDR_WIDTH              = 30,
-  parameter integer C_AXI_DATA_WIDTH              = 32,
-  parameter integer C_AXI_SUPPORTS_WRITE          = 1,
-  parameter integer C_AXI_SUPPORTS_READ           = 1
-)
-(
-///////////////////////////////////////////////////////////////////////////////
-// Port Declarations
-///////////////////////////////////////////////////////////////////////////////
-  // AXI Slave Interface
-  // Slave Interface System Signals
-  input  wire                               aclk              ,
-  input  wire                               aresetn           ,
-  // Slave Interface Write Address Ports
-  input  wire [C_AXI_ID_WIDTH-1:0]          s_axi_awid        ,
-  input  wire [C_AXI_ADDR_WIDTH-1:0]        s_axi_awaddr      ,
-  input  wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_awlen,
-  input  wire [2:0]                         s_axi_awsize      ,
-  input  wire [1:0]                         s_axi_awburst     ,
-  input  wire [2:0]                         s_axi_awprot      ,
-  input  wire                               s_axi_awvalid     ,
-  output wire                               s_axi_awready     ,
-  // Slave Interface Write Data Ports
-  input  wire [C_AXI_DATA_WIDTH-1:0]        s_axi_wdata       ,
-  input  wire [C_AXI_DATA_WIDTH/8-1:0]      s_axi_wstrb       ,
-  input  wire                               s_axi_wlast       ,
-  input  wire                               s_axi_wvalid      ,
-  output wire                               s_axi_wready      ,
-  // Slave Interface Write Response Ports
-  output wire [C_AXI_ID_WIDTH-1:0]          s_axi_bid         ,
-  output wire [1:0]                         s_axi_bresp       ,
-  output wire                               s_axi_bvalid      ,
-  input  wire                               s_axi_bready      ,
-  // Slave Interface Read Address Ports
-  input  wire [C_AXI_ID_WIDTH-1:0]          s_axi_arid        ,
-  input  wire [C_AXI_ADDR_WIDTH-1:0]        s_axi_araddr      ,
-  input  wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]  s_axi_arlen,
-  input  wire [2:0]                         s_axi_arsize      ,
-  input  wire [1:0]                         s_axi_arburst     ,
-  input  wire [2:0]                         s_axi_arprot      ,
-  input  wire                               s_axi_arvalid     ,
-  output wire                               s_axi_arready     ,
-  // Slave Interface Read Data Ports
-  output wire [C_AXI_ID_WIDTH-1:0]          s_axi_rid         ,
-  output wire [C_AXI_DATA_WIDTH-1:0]        s_axi_rdata       ,
-  output wire [1:0]                         s_axi_rresp       ,
-  output wire                               s_axi_rlast       ,
-  output wire                               s_axi_rvalid      ,
-  input  wire                               s_axi_rready      ,
-
-  // Slave Interface Write Address Ports
-  output wire [C_AXI_ADDR_WIDTH-1:0]        m_axi_awaddr      ,
-  output wire [2:0]                         m_axi_awprot      ,
-  output wire                               m_axi_awvalid     ,
-  input  wire                               m_axi_awready     ,
-  // Slave Interface Write Data Ports
-  output wire [C_AXI_DATA_WIDTH-1:0]        m_axi_wdata       ,
-  output wire [C_AXI_DATA_WIDTH/8-1:0]      m_axi_wstrb       ,
-  output wire                               m_axi_wvalid      ,
-  input  wire                               m_axi_wready      ,
-  // Slave Interface Write Response Ports
-  input  wire [1:0]                         m_axi_bresp       ,
-  input  wire                               m_axi_bvalid      ,
-  output wire                               m_axi_bready      ,
-  // Slave Interface Read Address Ports
-  output wire [C_AXI_ADDR_WIDTH-1:0]        m_axi_araddr      ,
-  output wire [2:0]                         m_axi_arprot      ,
-  output wire                               m_axi_arvalid     ,
-  input  wire                               m_axi_arready     ,
-  // Slave Interface Read Data Ports
-  input  wire [C_AXI_DATA_WIDTH-1:0]        m_axi_rdata       ,
-  input  wire [1:0]                         m_axi_rresp       ,
-  input  wire                               m_axi_rvalid      ,
-  output wire                               m_axi_rready
-);
-
-////////////////////////////////////////////////////////////////////////////////
-// Wires/Reg declarations
-////////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////////
-// BEGIN RTL
-reg                            areset_d1;
-
-always @(posedge aclk)
-  areset_d1 <= ~aresetn;
-
-
-// AW/W/B channel internal communication
-wire                                b_push;
-wire [C_AXI_ID_WIDTH-1:0]           b_awid;
-wire [7:0]                          b_awlen;
-wire                                b_full;
-
-wire [C_AXI_ID_WIDTH-1:0]                   si_rs_awid;
-wire [C_AXI_ADDR_WIDTH-1:0]                 si_rs_awaddr;
-wire [8-1:0]                                si_rs_awlen;
-wire [3-1:0]                                si_rs_awsize;
-wire [2-1:0]                                si_rs_awburst;
-wire [3-1:0]                                si_rs_awprot;
-wire                                        si_rs_awvalid;
-wire                                        si_rs_awready;
-wire [C_AXI_DATA_WIDTH-1:0]                 si_rs_wdata;
-wire [C_AXI_DATA_WIDTH/8-1:0]               si_rs_wstrb;
-wire                                        si_rs_wlast;
-wire                                        si_rs_wvalid;
-wire                                        si_rs_wready;
-wire [C_AXI_ID_WIDTH-1:0]                   si_rs_bid;
-wire [2-1:0]                                si_rs_bresp;
-wire                                        si_rs_bvalid;
-wire                                        si_rs_bready;
-wire [C_AXI_ID_WIDTH-1:0]                   si_rs_arid;
-wire [C_AXI_ADDR_WIDTH-1:0]                 si_rs_araddr;
-wire [8-1:0]                                si_rs_arlen;
-wire [3-1:0]                                si_rs_arsize;
-wire [2-1:0]                                si_rs_arburst;
-wire [3-1:0]                                si_rs_arprot;
-wire                                        si_rs_arvalid;
-wire                                        si_rs_arready;
-wire [C_AXI_ID_WIDTH-1:0]                   si_rs_rid;
-wire [C_AXI_DATA_WIDTH-1:0]                 si_rs_rdata;
-wire [2-1:0]                                si_rs_rresp;
-wire                                        si_rs_rlast;
-wire                                        si_rs_rvalid;
-wire                                        si_rs_rready;
-
-wire [C_AXI_ADDR_WIDTH-1:0]                 rs_mi_awaddr;
-wire                                        rs_mi_awvalid;
-wire                                        rs_mi_awready;
-wire [C_AXI_DATA_WIDTH-1:0]                 rs_mi_wdata;
-wire [C_AXI_DATA_WIDTH/8-1:0]               rs_mi_wstrb;
-wire                                        rs_mi_wvalid;
-wire                                        rs_mi_wready;
-wire [2-1:0]                                rs_mi_bresp;
-wire                                        rs_mi_bvalid;
-wire                                        rs_mi_bready;
-wire [C_AXI_ADDR_WIDTH-1:0]                 rs_mi_araddr;
-wire                                        rs_mi_arvalid;
-wire                                        rs_mi_arready;
-wire [C_AXI_DATA_WIDTH-1:0]                 rs_mi_rdata;
-wire [2-1:0]                                rs_mi_rresp;
-wire                                        rs_mi_rvalid;
-wire                                        rs_mi_rready;
-
-
-axi_register_slice_v2_1_9_axi_register_slice #(
-  .C_AXI_PROTOCOL              ( C_S_AXI_PROTOCOL            ) ,
-  .C_AXI_ID_WIDTH              ( C_AXI_ID_WIDTH              ) ,
-  .C_AXI_ADDR_WIDTH            ( C_AXI_ADDR_WIDTH            ) ,
-  .C_AXI_DATA_WIDTH            ( C_AXI_DATA_WIDTH            ) ,
-  .C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
-  .C_AXI_AWUSER_WIDTH          ( 1 ) ,
-  .C_AXI_ARUSER_WIDTH          ( 1 ) ,
-  .C_AXI_WUSER_WIDTH           ( 1 ) ,
-  .C_AXI_RUSER_WIDTH           ( 1 ) ,
-  .C_AXI_BUSER_WIDTH           ( 1 ) ,
-  .C_REG_CONFIG_AW             ( 1 ) ,
-  .C_REG_CONFIG_AR             ( 1 ) ,
-  .C_REG_CONFIG_W              ( 0 ) ,
-  .C_REG_CONFIG_R              ( 1 ) ,
-  .C_REG_CONFIG_B              ( 1 )
-) SI_REG (
-  .aresetn                    ( aresetn     ) ,
-  .aclk                       ( aclk          ) ,
-  .s_axi_awid                 ( s_axi_awid    ) ,
-  .s_axi_awaddr               ( s_axi_awaddr  ) ,
-  .s_axi_awlen                ( s_axi_awlen   ) ,
-  .s_axi_awsize               ( s_axi_awsize  ) ,
-  .s_axi_awburst              ( s_axi_awburst ) ,
-  .s_axi_awlock               ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}}  ) ,
-  .s_axi_awcache              ( 4'h0 ) ,
-  .s_axi_awprot               ( s_axi_awprot  ) ,
-  .s_axi_awqos                ( 4'h0 ) ,
-  .s_axi_awuser               ( 1'b0  ) ,
-  .s_axi_awvalid              ( s_axi_awvalid ) ,
-  .s_axi_awready              ( s_axi_awready ) ,
-  .s_axi_awregion             ( 4'h0 ) ,
-  .s_axi_wid                  ( {C_AXI_ID_WIDTH{1'b0}} ) ,
-  .s_axi_wdata                ( s_axi_wdata   ) ,
-  .s_axi_wstrb                ( s_axi_wstrb   ) ,
-  .s_axi_wlast                ( s_axi_wlast   ) ,
-  .s_axi_wuser                ( 1'b0  ) ,
-  .s_axi_wvalid               ( s_axi_wvalid  ) ,
-  .s_axi_wready               ( s_axi_wready  ) ,
-  .s_axi_bid                  ( s_axi_bid     ) ,
-  .s_axi_bresp                ( s_axi_bresp   ) ,
-  .s_axi_buser                ( ) ,
-  .s_axi_bvalid               ( s_axi_bvalid  ) ,
-  .s_axi_bready               ( s_axi_bready  ) ,
-  .s_axi_arid                 ( s_axi_arid    ) ,
-  .s_axi_araddr               ( s_axi_araddr  ) ,
-  .s_axi_arlen                ( s_axi_arlen   ) ,
-  .s_axi_arsize               ( s_axi_arsize  ) ,
-  .s_axi_arburst              ( s_axi_arburst ) ,
-  .s_axi_arlock               ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}}  ) ,
-  .s_axi_arcache              ( 4'h0 ) ,
-  .s_axi_arprot               ( s_axi_arprot  ) ,
-  .s_axi_arqos                ( 4'h0 ) ,
-  .s_axi_aruser               ( 1'b0  ) ,
-  .s_axi_arvalid              ( s_axi_arvalid ) ,
-  .s_axi_arready              ( s_axi_arready ) ,
-  .s_axi_arregion             ( 4'h0 ) ,
-  .s_axi_rid                  ( s_axi_rid     ) ,
-  .s_axi_rdata                ( s_axi_rdata   ) ,
-  .s_axi_rresp                ( s_axi_rresp   ) ,
-  .s_axi_rlast                ( s_axi_rlast   ) ,
-  .s_axi_ruser                ( ) ,
-  .s_axi_rvalid               ( s_axi_rvalid  ) ,
-  .s_axi_rready               ( s_axi_rready  ) ,
-  .m_axi_awid                 ( si_rs_awid    ) ,
-  .m_axi_awaddr               ( si_rs_awaddr  ) ,
-  .m_axi_awlen                ( si_rs_awlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
-  .m_axi_awsize               ( si_rs_awsize  ) ,
-  .m_axi_awburst              ( si_rs_awburst ) ,
-  .m_axi_awlock               ( ) ,
-  .m_axi_awcache              ( ) ,
-  .m_axi_awprot               ( si_rs_awprot  ) ,
-  .m_axi_awqos                ( ) ,
-  .m_axi_awuser               ( ) ,
-  .m_axi_awvalid              ( si_rs_awvalid ) ,
-  .m_axi_awready              ( si_rs_awready ) ,
-  .m_axi_awregion             ( ) ,
-  .m_axi_wid                  ( ) ,
-  .m_axi_wdata                ( si_rs_wdata   ) ,
-  .m_axi_wstrb                ( si_rs_wstrb   ) ,
-  .m_axi_wlast                ( si_rs_wlast   ) ,
-  .m_axi_wuser                ( ) ,
-  .m_axi_wvalid               ( si_rs_wvalid  ) ,
-  .m_axi_wready               ( si_rs_wready  ) ,
-  .m_axi_bid                  ( si_rs_bid     ) ,
-  .m_axi_bresp                ( si_rs_bresp   ) ,
-  .m_axi_buser                ( 1'b0 ) ,
-  .m_axi_bvalid               ( si_rs_bvalid  ) ,
-  .m_axi_bready               ( si_rs_bready  ) ,
-  .m_axi_arid                 ( si_rs_arid    ) ,
-  .m_axi_araddr               ( si_rs_araddr  ) ,
-  .m_axi_arlen                ( si_rs_arlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
-  .m_axi_arsize               ( si_rs_arsize  ) ,
-  .m_axi_arburst              ( si_rs_arburst ) ,
-  .m_axi_arlock               ( ) ,
-  .m_axi_arcache              ( ) ,
-  .m_axi_arprot               ( si_rs_arprot  ) ,
-  .m_axi_arqos                ( ) ,
-  .m_axi_aruser               ( ) ,
-  .m_axi_arvalid              ( si_rs_arvalid ) ,
-  .m_axi_arready              ( si_rs_arready ) ,
-  .m_axi_arregion             ( ) ,
-  .m_axi_rid                  ( si_rs_rid     ) ,
-  .m_axi_rdata                ( si_rs_rdata   ) ,
-  .m_axi_rresp                ( si_rs_rresp   ) ,
-  .m_axi_rlast                ( si_rs_rlast   ) ,
-  .m_axi_ruser                ( 1'b0 ) ,
-  .m_axi_rvalid               ( si_rs_rvalid  ) ,
-  .m_axi_rready               ( si_rs_rready  )
-);
-
-generate
-  if (C_AXI_SUPPORTS_WRITE == 1) begin : WR
-    axi_protocol_converter_v2_1_9_b2s_aw_channel #
-    (
-      .C_ID_WIDTH                       ( C_AXI_ID_WIDTH   ),
-      .C_AXI_ADDR_WIDTH                 ( C_AXI_ADDR_WIDTH )
-    )
-    aw_channel_0
-    (
-      .clk                              ( aclk              ) ,
-      .reset                            ( areset_d1         ) ,
-      .s_awid                           ( si_rs_awid        ) ,
-      .s_awaddr                         ( si_rs_awaddr      ) ,
-      .s_awlen                          ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_awlen[3:0]} : si_rs_awlen),
-      .s_awsize                         ( si_rs_awsize      ) ,
-      .s_awburst                        ( si_rs_awburst     ) ,
-      .s_awvalid                        ( si_rs_awvalid     ) ,
-      .s_awready                        ( si_rs_awready     ) ,
-      .m_awvalid                        ( rs_mi_awvalid     ) ,
-      .m_awaddr                         ( rs_mi_awaddr      ) ,
-      .m_awready                        ( rs_mi_awready     ) ,
-      .b_push                           ( b_push            ) ,
-      .b_awid                           ( b_awid            ) ,
-      .b_awlen                          ( b_awlen           ) ,
-      .b_full                           ( b_full            )
-    );
-
-    axi_protocol_converter_v2_1_9_b2s_b_channel #
-    (
-      .C_ID_WIDTH                       ( C_AXI_ID_WIDTH   )
-    )
-    b_channel_0
-    (
-      .clk                              ( aclk            ) ,
-      .reset                            ( areset_d1       ) ,
-      .s_bid                            ( si_rs_bid       ) ,
-      .s_bresp                          ( si_rs_bresp     ) ,
-      .s_bvalid                         ( si_rs_bvalid    ) ,
-      .s_bready                         ( si_rs_bready    ) ,
-      .m_bready                         ( rs_mi_bready    ) ,
-      .m_bvalid                         ( rs_mi_bvalid    ) ,
-      .m_bresp                          ( rs_mi_bresp     ) ,
-      .b_push                           ( b_push          ) ,
-      .b_awid                           ( b_awid          ) ,
-      .b_awlen                          ( b_awlen         ) ,
-      .b_full                           ( b_full          ) ,
-      .b_resp_rdy                       ( si_rs_awready   )
-    );
-    
-    assign rs_mi_wdata        = si_rs_wdata;
-    assign rs_mi_wstrb        = si_rs_wstrb;
-    assign rs_mi_wvalid       = si_rs_wvalid;
-    assign si_rs_wready       = rs_mi_wready;
-
-  end else begin : NO_WR
-    assign rs_mi_awaddr       = {C_AXI_ADDR_WIDTH{1'b0}};
-    assign rs_mi_awvalid      = 1'b0;
-    assign si_rs_awready      = 1'b0;
-
-    assign rs_mi_wdata        = {C_AXI_DATA_WIDTH{1'b0}};
-    assign rs_mi_wstrb        = {C_AXI_DATA_WIDTH/8{1'b0}};
-    assign rs_mi_wvalid       = 1'b0;
-    assign si_rs_wready       = 1'b0;
-
-    assign rs_mi_bready    = 1'b0;
-    assign si_rs_bvalid       = 1'b0;
-    assign si_rs_bresp        = 2'b00;
-    assign si_rs_bid          = {C_AXI_ID_WIDTH{1'b0}};
-  end
-endgenerate
-
-
-// AR/R channel communication
-wire                                r_push        ;
-wire [C_AXI_ID_WIDTH-1:0]           r_arid        ;
-wire                                r_rlast       ;
-wire                                r_full        ;
-
-generate
-  if (C_AXI_SUPPORTS_READ == 1) begin : RD
-    axi_protocol_converter_v2_1_9_b2s_ar_channel #
-    (
-      .C_ID_WIDTH                       ( C_AXI_ID_WIDTH   ),
-      .C_AXI_ADDR_WIDTH                 ( C_AXI_ADDR_WIDTH )
-    
-    )
-    ar_channel_0
-    (
-      .clk                              ( aclk              ) ,
-      .reset                            ( areset_d1         ) ,
-      .s_arid                           ( si_rs_arid        ) ,
-      .s_araddr                         ( si_rs_araddr      ) ,
-      .s_arlen                          ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_arlen[3:0]} : si_rs_arlen),
-      .s_arsize                         ( si_rs_arsize      ) ,
-      .s_arburst                        ( si_rs_arburst     ) ,
-      .s_arvalid                        ( si_rs_arvalid     ) ,
-      .s_arready                        ( si_rs_arready     ) ,
-      .m_arvalid                        ( rs_mi_arvalid     ) ,
-      .m_araddr                         ( rs_mi_araddr      ) ,
-      .m_arready                        ( rs_mi_arready     ) ,
-      .r_push                           ( r_push            ) ,
-      .r_arid                           ( r_arid            ) ,
-      .r_rlast                          ( r_rlast           ) ,
-      .r_full                           ( r_full            )
-    );
-    
-    axi_protocol_converter_v2_1_9_b2s_r_channel #
-    (
-      .C_ID_WIDTH                       ( C_AXI_ID_WIDTH   ),
-      .C_DATA_WIDTH                     ( C_AXI_DATA_WIDTH )
-    )
-    r_channel_0
-    (
-      .clk                              ( aclk            ) ,
-      .reset                            ( areset_d1       ) ,
-      .s_rid                            ( si_rs_rid       ) ,
-      .s_rdata                          ( si_rs_rdata     ) ,
-      .s_rresp                          ( si_rs_rresp     ) ,
-      .s_rlast                          ( si_rs_rlast     ) ,
-      .s_rvalid                         ( si_rs_rvalid    ) ,
-      .s_rready                         ( si_rs_rready    ) ,
-      .m_rvalid                         ( rs_mi_rvalid    ) ,
-      .m_rready                         ( rs_mi_rready    ) ,
-      .m_rdata                          ( rs_mi_rdata     ) ,
-      .m_rresp                          ( rs_mi_rresp     ) ,
-      .r_push                           ( r_push          ) ,
-      .r_full                           ( r_full          ) ,
-      .r_arid                           ( r_arid          ) ,
-      .r_rlast                          ( r_rlast         )
-    );
-  end else begin : NO_RD
-    assign rs_mi_araddr       = {C_AXI_ADDR_WIDTH{1'b0}};
-    assign rs_mi_arvalid      = 1'b0;
-    assign si_rs_arready      = 1'b0;
-    assign si_rs_rlast        = 1'b1;
-
-    assign si_rs_rdata        = {C_AXI_DATA_WIDTH{1'b0}};
-    assign si_rs_rvalid       = 1'b0;
-    assign si_rs_rresp        = 2'b00;
-    assign si_rs_rid          = {C_AXI_ID_WIDTH{1'b0}};
-    assign rs_mi_rready       = 1'b0;
-  end
-endgenerate
-
-axi_register_slice_v2_1_9_axi_register_slice #(
-  .C_AXI_PROTOCOL              ( 2 ) ,
-  .C_AXI_ID_WIDTH              ( 1 ) ,
-  .C_AXI_ADDR_WIDTH            ( C_AXI_ADDR_WIDTH            ) ,
-  .C_AXI_DATA_WIDTH            ( C_AXI_DATA_WIDTH            ) ,
-  .C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
-  .C_AXI_AWUSER_WIDTH          ( 1 ) ,
-  .C_AXI_ARUSER_WIDTH          ( 1 ) ,
-  .C_AXI_WUSER_WIDTH           ( 1 ) ,
-  .C_AXI_RUSER_WIDTH           ( 1 ) ,
-  .C_AXI_BUSER_WIDTH           ( 1 ) ,
-  .C_REG_CONFIG_AW             ( 0 ) ,
-  .C_REG_CONFIG_AR             ( 0 ) ,
-  .C_REG_CONFIG_W              ( 0 ) ,
-  .C_REG_CONFIG_R              ( 0 ) ,
-  .C_REG_CONFIG_B              ( 0 )
-) MI_REG (
-  .aresetn                    ( aresetn       ) ,
-  .aclk                       ( aclk          ) ,
-  .s_axi_awid                 ( 1'b0          ) ,
-  .s_axi_awaddr               ( rs_mi_awaddr  ) ,
-  .s_axi_awlen                ( 8'h00         ) ,
-  .s_axi_awsize               ( 3'b000        ) ,
-  .s_axi_awburst              ( 2'b01         ) ,
-  .s_axi_awlock               ( 1'b0          ) ,
-  .s_axi_awcache              ( 4'h0          ) ,
-  .s_axi_awprot               ( si_rs_awprot  ) ,
-  .s_axi_awqos                ( 4'h0          ) ,
-  .s_axi_awuser               ( 1'b0          ) ,
-  .s_axi_awvalid              ( rs_mi_awvalid ) ,
-  .s_axi_awready              ( rs_mi_awready ) ,
-  .s_axi_awregion             ( 4'h0          ) ,
-  .s_axi_wid                  ( 1'b0          ) ,
-  .s_axi_wdata                ( rs_mi_wdata   ) ,
-  .s_axi_wstrb                ( rs_mi_wstrb   ) ,
-  .s_axi_wlast                ( 1'b1          ) ,
-  .s_axi_wuser                ( 1'b0          ) ,
-  .s_axi_wvalid               ( rs_mi_wvalid  ) ,
-  .s_axi_wready               ( rs_mi_wready  ) ,
-  .s_axi_bid                  (               ) ,
-  .s_axi_bresp                ( rs_mi_bresp   ) ,
-  .s_axi_buser                (               ) ,
-  .s_axi_bvalid               ( rs_mi_bvalid  ) ,
-  .s_axi_bready               ( rs_mi_bready  ) ,
-  .s_axi_arid                 ( 1'b0          ) ,
-  .s_axi_araddr               ( rs_mi_araddr  ) ,
-  .s_axi_arlen                ( 8'h00         ) ,
-  .s_axi_arsize               ( 3'b000        ) ,
-  .s_axi_arburst              ( 2'b01         ) ,
-  .s_axi_arlock               ( 1'b0          ) ,
-  .s_axi_arcache              ( 4'h0          ) ,
-  .s_axi_arprot               ( si_rs_arprot  ) ,
-  .s_axi_arqos                ( 4'h0          ) ,
-  .s_axi_aruser               ( 1'b0          ) ,
-  .s_axi_arvalid              ( rs_mi_arvalid ) ,
-  .s_axi_arready              ( rs_mi_arready ) ,
-  .s_axi_arregion             ( 4'h0          ) ,
-  .s_axi_rid                  (               ) ,
-  .s_axi_rdata                ( rs_mi_rdata   ) ,
-  .s_axi_rresp                ( rs_mi_rresp   ) ,
-  .s_axi_rlast                (               ) ,
-  .s_axi_ruser                (               ) ,
-  .s_axi_rvalid               ( rs_mi_rvalid  ) ,
-  .s_axi_rready               ( rs_mi_rready  ) ,
-  .m_axi_awid                 (               ) ,
-  .m_axi_awaddr               ( m_axi_awaddr  ) ,
-  .m_axi_awlen                (               ) ,
-  .m_axi_awsize               (               ) ,
-  .m_axi_awburst              (               ) ,
-  .m_axi_awlock               (               ) ,
-  .m_axi_awcache              (               ) ,
-  .m_axi_awprot               ( m_axi_awprot  ) ,
-  .m_axi_awqos                (               ) ,
-  .m_axi_awuser               (               ) ,
-  .m_axi_awvalid              ( m_axi_awvalid ) ,
-  .m_axi_awready              ( m_axi_awready ) ,
-  .m_axi_awregion             (               ) ,
-  .m_axi_wid                  (               ) ,
-  .m_axi_wdata                ( m_axi_wdata   ) ,
-  .m_axi_wstrb                ( m_axi_wstrb   ) ,
-  .m_axi_wlast                (               ) ,
-  .m_axi_wuser                (               ) ,
-  .m_axi_wvalid               ( m_axi_wvalid  ) ,
-  .m_axi_wready               ( m_axi_wready  ) ,
-  .m_axi_bid                  ( 1'b0          ) ,
-  .m_axi_bresp                ( m_axi_bresp   ) ,
-  .m_axi_buser                ( 1'b0          ) ,
-  .m_axi_bvalid               ( m_axi_bvalid  ) ,
-  .m_axi_bready               ( m_axi_bready  ) ,
-  .m_axi_arid                 (               ) ,
-  .m_axi_araddr               ( m_axi_araddr  ) ,
-  .m_axi_arlen                (               ) ,
-  .m_axi_arsize               (               ) ,
-  .m_axi_arburst              (               ) ,
-  .m_axi_arlock               (               ) ,
-  .m_axi_arcache              (               ) ,
-  .m_axi_arprot               ( m_axi_arprot  ) ,
-  .m_axi_arqos                (               ) ,
-  .m_axi_aruser               (               ) ,
-  .m_axi_arvalid              ( m_axi_arvalid ) ,
-  .m_axi_arready              ( m_axi_arready ) ,
-  .m_axi_arregion             (               ) ,
-  .m_axi_rid                  ( 1'b0          ) ,
-  .m_axi_rdata                ( m_axi_rdata   ) ,
-  .m_axi_rresp                ( m_axi_rresp   ) ,
-  .m_axi_rlast                ( 1'b1          ) ,
-  .m_axi_ruser                ( 1'b0          ) ,
-  .m_axi_rvalid               ( m_axi_rvalid  ) ,
-  .m_axi_rready               ( m_axi_rready  )
-);
-
-endmodule
-
-`default_nettype wire
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v
deleted file mode 100755
index ddf7c3f8b1366bfdddbbdae570365a25eae1786b..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v
+++ /dev/null
@@ -1,108 +0,0 @@
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_b2s_ar_channel #
-(
-///////////////////////////////////////////////////////////////////////////////
-// Parameter Definitions
-///////////////////////////////////////////////////////////////////////////////
-                    // Width of ID signals.
-                    // Range: >= 1.
-  parameter integer C_ID_WIDTH          = 4,
-                    // Width of AxADDR
-                    // Range: 32.
-  parameter integer C_AXI_ADDR_WIDTH    = 32
-)
-(
-///////////////////////////////////////////////////////////////////////////////
-// Port Declarations
-///////////////////////////////////////////////////////////////////////////////
-  // AXI Slave Interface
-  // Slave Interface System Signals
-  input  wire                                 clk             ,
-  input  wire                                 reset           ,
-
-  // Slave Interface Read Address Ports
-  input  wire [C_ID_WIDTH-1:0]                s_arid            ,
-  input  wire [C_AXI_ADDR_WIDTH-1:0]          s_araddr          ,
-  input  wire [7:0]                           s_arlen           ,
-  input  wire [2:0]                           s_arsize          ,
-  input  wire [1:0]                           s_arburst         ,
-  input  wire                                 s_arvalid         ,
-  output wire                                 s_arready         ,
-
-  output wire                                 m_arvalid         ,
-  output wire [C_AXI_ADDR_WIDTH-1:0]          m_araddr          ,
-  input  wire                                 m_arready         ,
-
-  // Connections to/from axi_protocol_converter_v2_1_9_b2s_r_channel module
-  output wire [C_ID_WIDTH-1:0]                r_arid            ,
-  output wire                                 r_push            ,
-  output wire                                 r_rlast           ,
-  input  wire                                 r_full
-
-);
-
-////////////////////////////////////////////////////////////////////////////////
-// Wires/Reg declarations
-////////////////////////////////////////////////////////////////////////////////
-wire                        next      ;
-wire                        next_pending ;
-wire                        a_push;
-wire                        incr_burst;
-reg [C_ID_WIDTH-1:0]        s_arid_r;
-
-
-////////////////////////////////////////////////////////////////////////////////
-// BEGIN RTL
-////////////////////////////////////////////////////////////////////////////////
-
-
-// Translate the AXI transaction to the MC transaction(s)
-axi_protocol_converter_v2_1_9_b2s_cmd_translator #
-(
-  .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
-)
-cmd_translator_0
-(
-  .clk           ( clk                   ) ,
-  .reset         ( reset                 ) ,
-  .s_axaddr      ( s_araddr              ) ,
-  .s_axlen       ( s_arlen               ) ,
-  .s_axsize      ( s_arsize              ) ,
-  .s_axburst     ( s_arburst             ) ,
-  .s_axhandshake ( s_arvalid & a_push    ) ,
-  .incr_burst    ( incr_burst            ) ,
-  .m_axaddr      ( m_araddr              ) ,
-  .next          ( next                  ) ,
-  .next_pending  ( next_pending          )
-);
-
-axi_protocol_converter_v2_1_9_b2s_rd_cmd_fsm ar_cmd_fsm_0
-(
-  .clk          ( clk            ) ,
-  .reset        ( reset          ) ,
-  .s_arready    ( s_arready      ) ,
-  .s_arvalid    ( s_arvalid      ) ,
-  .s_arlen      ( s_arlen        ) ,
-  .m_arvalid    ( m_arvalid      ) ,
-  .m_arready    ( m_arready      ) ,
-  .next         ( next           ) ,
-  .next_pending ( next_pending   ) ,
-  .data_ready   ( ~r_full        ) ,
-  .a_push       ( a_push         ) ,
-  .r_push       ( r_push         )
-);
-
-// these signals can be moved out of this block to the top level.
-assign r_arid  = s_arid_r;
-assign r_rlast = ~next_pending;
-
-always @(posedge clk) begin
-  s_arid_r <= s_arid ;
-end
-
-endmodule
-
-`default_nettype wire
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_aw_channel.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_aw_channel.v
deleted file mode 100755
index 3f2de008b2c47d2acd65b0ce89d0a088a8e18895..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_aw_channel.v
+++ /dev/null
@@ -1,109 +0,0 @@
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_b2s_aw_channel #
-(
-///////////////////////////////////////////////////////////////////////////////
-// Parameter Definitions
-///////////////////////////////////////////////////////////////////////////////
-                    // Width of ID signals.
-                    // Range: >= 1.
-  parameter integer C_ID_WIDTH          = 4,
-                    // Width of AxADDR
-                    // Range: 32.
-  parameter integer C_AXI_ADDR_WIDTH    = 32
-
-)
-(
-///////////////////////////////////////////////////////////////////////////////
-// Port Declarations
-///////////////////////////////////////////////////////////////////////////////
-  // AXI Slave Interface
-  // Slave Interface System Signals
-  input  wire                                 clk             ,
-  input  wire                                 reset           ,
-
-  // Slave Interface Write Address Ports
-  input  wire [C_ID_WIDTH-1:0]                s_awid            ,
-  input  wire [C_AXI_ADDR_WIDTH-1:0]          s_awaddr          ,
-  input  wire [7:0]                           s_awlen           ,
-  input  wire [2:0]                           s_awsize          ,
-  input  wire [1:0]                           s_awburst         ,
-  input  wire                                 s_awvalid         ,
-  output wire                                 s_awready         ,
-
-  output wire                                 m_awvalid         ,
-  output wire [C_AXI_ADDR_WIDTH-1:0]          m_awaddr          ,
-  input  wire                                 m_awready         ,
-
-  // Connections to/from axi_protocol_converter_v2_1_9_b2s_b_channel module
-  output wire                                 b_push           ,
-  output wire [C_ID_WIDTH-1:0]                b_awid           ,
-  output wire [7:0]                           b_awlen          ,
-  input  wire                                 b_full
-
-);
-
-////////////////////////////////////////////////////////////////////////////////
-// Wires/Reg declarations
-////////////////////////////////////////////////////////////////////////////////
-
-wire                        next         ;
-wire                        next_pending ;
-wire                        a_push;
-wire                        incr_burst;
-reg  [C_ID_WIDTH-1:0]       s_awid_r;
-reg  [7:0]                  s_awlen_r;
-
-////////////////////////////////////////////////////////////////////////////////
-// BEGIN RTL
-////////////////////////////////////////////////////////////////////////////////
-
-// Translate the AXI transaction to the MC transaction(s)
-axi_protocol_converter_v2_1_9_b2s_cmd_translator #
-(
-  .C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
-)
-cmd_translator_0
-(
-  .clk           ( clk                   ) ,
-  .reset         ( reset                 ) ,
-  .s_axaddr      ( s_awaddr              ) ,
-  .s_axlen       ( s_awlen               ) ,
-  .s_axsize      ( s_awsize              ) ,
-  .s_axburst     ( s_awburst             ) ,
-  .s_axhandshake ( s_awvalid & a_push    ) ,
-  .m_axaddr      ( m_awaddr              ) ,
-  .incr_burst    ( incr_burst            ) ,
-  .next          ( next                  ) ,
-  .next_pending  ( next_pending          )
-);
-
-
-axi_protocol_converter_v2_1_9_b2s_wr_cmd_fsm aw_cmd_fsm_0
-(
-  .clk          ( clk            ) ,
-  .reset        ( reset          ) ,
-  .s_awready    ( s_awready      ) ,
-  .s_awvalid    ( s_awvalid      ) ,
-  .m_awvalid    ( m_awvalid      ) ,
-  .m_awready    ( m_awready      ) ,
-  .next         ( next           ) ,
-  .next_pending ( next_pending   ) ,
-  .b_push       ( b_push         ) ,
-  .b_full       ( b_full         ) ,
-  .a_push       ( a_push         )
-);
-
-assign b_awid = s_awid_r;
-assign b_awlen = s_awlen_r;
-
-always @(posedge clk) begin
-  s_awid_r <= s_awid ;
-  s_awlen_r <= s_awlen ;
-end
-
-endmodule
-
-`default_nettype wire
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v
deleted file mode 100755
index 8c047d1686ed7b29a4ffc7173062facba70cac9e..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v
+++ /dev/null
@@ -1,187 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//
-// File name: axi_protocol_converter_v2_1_9_b2s_b_channel.v
-//
-///////////////////////////////////////////////////////////////////////////////
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_b2s_b_channel #
-(
-///////////////////////////////////////////////////////////////////////////////
-// Parameter Definitions
-///////////////////////////////////////////////////////////////////////////////
-                    // Width of ID signals.
-                    // Range: >= 1.
-  parameter integer C_ID_WIDTH                = 4
-)
-(
-///////////////////////////////////////////////////////////////////////////////
-// Port Declarations
-///////////////////////////////////////////////////////////////////////////////
-  input  wire                                 clk,
-  input  wire                                 reset,
-
-  // AXI signals
-  output wire [C_ID_WIDTH-1:0]                s_bid,
-  output wire [1:0]                           s_bresp,
-  output wire                                 s_bvalid,
-  input  wire                                 s_bready,
-
-  input  wire [1:0]                           m_bresp,
-  input  wire                                 m_bvalid,
-  output wire                                 m_bready,
-
-
-  // Signals to/from the axi_protocol_converter_v2_1_9_b2s_aw_channel modules
-  input  wire                                 b_push,
-  input  wire [C_ID_WIDTH-1:0]                b_awid,
-  input  wire [7:0]                           b_awlen,
-  input  wire                                 b_resp_rdy,
-  output wire                                 b_full
-
-);
-
-////////////////////////////////////////////////////////////////////////////////
-// Local parameters
-////////////////////////////////////////////////////////////////////////////////
-// AXI protocol responses:
-localparam [1:0] LP_RESP_OKAY        = 2'b00;
-localparam [1:0] LP_RESP_EXOKAY      = 2'b01;
-localparam [1:0] LP_RESP_SLVERROR    = 2'b10;
-localparam [1:0] LP_RESP_DECERR      = 2'b11;
-
-// FIFO settings
-localparam P_WIDTH  = C_ID_WIDTH + 8;
-localparam P_DEPTH  = 4;
-localparam P_AWIDTH = 2;
-
-localparam P_RWIDTH  = 2;
-localparam P_RDEPTH  = 4;
-localparam P_RAWIDTH = 2;
-
-////////////////////////////////////////////////////////////////////////////////
-// Wire and register declarations
-////////////////////////////////////////////////////////////////////////////////
-reg                     bvalid_i;
-wire [C_ID_WIDTH-1:0]   bid_i;
-wire                    shandshake;
-reg                     shandshake_r;
-wire                    mhandshake;
-reg                     mhandshake_r;
-
-wire                    b_empty;
-wire                    bresp_full;
-wire                    bresp_empty;
-wire [7:0]              b_awlen_i;
-reg  [7:0]              bresp_cnt;
-
-reg  [1:0]              s_bresp_acc;
-wire [1:0]              s_bresp_acc_r;
-reg  [1:0]              s_bresp_i;
-wire                    need_to_update_bresp;
-wire                    bresp_push;
-
-
-////////////////////////////////////////////////////////////////////////////////
-// BEGIN RTL
-////////////////////////////////////////////////////////////////////////////////
-
-// assign AXI outputs
-assign s_bid      = bid_i;
-assign s_bresp    = s_bresp_acc_r;
-assign s_bvalid   = bvalid_i;
-assign shandshake = s_bvalid & s_bready;
-assign mhandshake = m_bvalid & m_bready;
-
-always @(posedge clk) begin
-  if (reset | shandshake) begin
-    bvalid_i <= 1'b0;
-  end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin
-    bvalid_i <= 1'b1;
-  end
-end
-
-always @(posedge clk) begin
-  shandshake_r <= shandshake;
-  mhandshake_r <= mhandshake;
-end
-
-axi_protocol_converter_v2_1_9_b2s_simple_fifo #(
-  .C_WIDTH                  (P_WIDTH),
-  .C_AWIDTH                 (P_AWIDTH),
-  .C_DEPTH                  (P_DEPTH)
-)
-bid_fifo_0
-(
-  .clk     ( clk          ) ,
-  .rst     ( reset        ) ,
-  .wr_en   ( b_push       ) ,
-  .rd_en   ( shandshake_r ) ,
-  .din     ( {b_awid, b_awlen} ) ,
-  .dout    ( {bid_i, b_awlen_i}) ,
-  .a_full  (              ) ,
-  .full    ( b_full       ) ,
-  .a_empty (              ) ,
-  .empty   ( b_empty        )
-);
-
-assign m_bready = ~mhandshake_r & bresp_empty;
-
-/////////////////////////////////////////////////////////////////////////////
-// Update if more critical.
-assign need_to_update_bresp = ( m_bresp > s_bresp_acc );
-
-// Select accumultated or direct depending on setting.
-always @( * ) begin
-  if ( need_to_update_bresp ) begin
-    s_bresp_i = m_bresp;
-  end else begin
-    s_bresp_i = s_bresp_acc;
-  end
-end
-
-/////////////////////////////////////////////////////////////////////////////
-// Accumulate MI-side BRESP.
-always @ (posedge clk) begin
-  if (reset | bresp_push ) begin
-    s_bresp_acc <= LP_RESP_OKAY;
-  end else if ( mhandshake ) begin
-    s_bresp_acc <= s_bresp_i;
-  end
-end
-
-assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty;
-
-always @ (posedge clk) begin
-  if (reset | bresp_push ) begin
-    bresp_cnt <= 8'h00;
-  end else if ( mhandshake_r ) begin
-    bresp_cnt <= bresp_cnt + 1'b1;
-  end
-end
-
-axi_protocol_converter_v2_1_9_b2s_simple_fifo #(
-  .C_WIDTH                  (P_RWIDTH),
-  .C_AWIDTH                 (P_RAWIDTH),
-  .C_DEPTH                  (P_RDEPTH)
-)
-bresp_fifo_0
-(
-  .clk     ( clk          ) ,
-  .rst     ( reset        ) ,
-  .wr_en   ( bresp_push   ) ,
-  .rd_en   ( shandshake_r ) ,
-  .din     ( s_bresp_acc  ) ,
-  .dout    ( s_bresp_acc_r) ,
-  .a_full  (              ) ,
-  .full    ( bresp_full   ) ,
-  .a_empty (              ) ,
-  .empty   ( bresp_empty  )
-);
-
-
-endmodule
-
-`default_nettype wire
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_cmd_translator.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_cmd_translator.v
deleted file mode 100755
index 63a90fea1e7362dd3656ac8156dc530a55451b17..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_cmd_translator.v
+++ /dev/null
@@ -1,147 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//
-// File name: axi_protocol_converter_v2_1_9_b2s_cmd_translator.v
-//
-// Description: 
-// INCR and WRAP burst modes are decoded in parallel and then the output is
-// chosen based on the AxBURST value.  FIXED burst mode is not supported and
-// is mapped to the INCR command instead.  
-//
-// Specifications:
-//
-///////////////////////////////////////////////////////////////////////////////
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_b2s_cmd_translator #
-(
-///////////////////////////////////////////////////////////////////////////////
-// Parameter Definitions
-///////////////////////////////////////////////////////////////////////////////
-                    // Width of AxADDR
-                    // Range: 32.
-  parameter integer C_AXI_ADDR_WIDTH            = 32
-)
-(
-///////////////////////////////////////////////////////////////////////////////
-// Port Declarations     
-///////////////////////////////////////////////////////////////////////////////
-  input  wire                                 clk           , 
-  input  wire                                 reset         , 
-  input  wire [C_AXI_ADDR_WIDTH-1:0]          s_axaddr        , 
-  input  wire [7:0]                           s_axlen         , 
-  input  wire [2:0]                           s_axsize        , 
-  input  wire [1:0]                           s_axburst       , 
-  input  wire                                 s_axhandshake   , 
-  output wire [C_AXI_ADDR_WIDTH-1:0]          m_axaddr , 
-  output wire                                 incr_burst    , 
-
-  // Connections to/from fsm module
-  // signal to increment to the next mc transaction 
-  input  wire                                 next          , 
-  // signal to the fsm there is another transaction required
-  output wire                                 next_pending
-);
-
-////////////////////////////////////////////////////////////////////////////////
-// Local parameters
-////////////////////////////////////////////////////////////////////////////////
-// AXBURST decodes
-localparam P_AXBURST_FIXED = 2'b00;
-localparam P_AXBURST_INCR  = 2'b01;
-localparam P_AXBURST_WRAP  = 2'b10;
-////////////////////////////////////////////////////////////////////////////////
-// Wires/Reg declarations
-////////////////////////////////////////////////////////////////////////////////
-wire [C_AXI_ADDR_WIDTH-1:0]     incr_cmd_byte_addr;
-wire                            incr_next_pending;
-wire [C_AXI_ADDR_WIDTH-1:0]     wrap_cmd_byte_addr;
-wire                            wrap_next_pending;
-reg                             sel_first;
-reg                             s_axburst_eq1;
-reg                             s_axburst_eq0;
-reg                             sel_first_i;   
-
-////////////////////////////////////////////////////////////////////////////////
-// BEGIN RTL
-////////////////////////////////////////////////////////////////////////////////
-
-// INCR and WRAP translations are calcuated in independently, select the one
-// for our transactions
-// right shift by the UI width to the DRAM width ratio 
- 
-assign m_axaddr         = (s_axburst == P_AXBURST_FIXED) ?  s_axaddr : 
-                          (s_axburst == P_AXBURST_INCR)  ?  incr_cmd_byte_addr : 
-                                                            wrap_cmd_byte_addr;
-assign incr_burst       = (s_axburst[1]) ? 1'b0 : 1'b1;
-
-// Indicates if we are on the first transaction of a mc translation with more
-// than 1 transaction.
-always @(posedge clk) begin
-  if (reset | s_axhandshake) begin
-    sel_first <= 1'b1;
-  end else if (next) begin
-    sel_first <= 1'b0;
-  end
-end
-
-always @( * ) begin
-  if (reset | s_axhandshake) begin
-    sel_first_i = 1'b1;
-  end else if (next) begin
-    sel_first_i = 1'b0;
-  end else begin
-    sel_first_i = sel_first;
-  end
-end
-
-assign next_pending = s_axburst[1] ? s_axburst_eq1 : s_axburst_eq0;
-
-always @(posedge clk) begin
-  if (sel_first_i || s_axburst[1]) begin
-    s_axburst_eq1 <= wrap_next_pending;
-  end else begin
-    s_axburst_eq1 <= incr_next_pending;
-  end
-  if (sel_first_i || !s_axburst[1]) begin
-    s_axburst_eq0 <= incr_next_pending;
-  end else begin
-    s_axburst_eq0 <= wrap_next_pending;
-  end
-end
-
-axi_protocol_converter_v2_1_9_b2s_incr_cmd #(
-  .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
-)
-incr_cmd_0
-(
-  .clk           ( clk                ) ,
-  .reset         ( reset              ) ,
-  .axaddr        ( s_axaddr           ) ,
-  .axlen         ( s_axlen            ) ,
-  .axsize        ( s_axsize           ) ,
-  .axhandshake   ( s_axhandshake      ) ,
-  .cmd_byte_addr ( incr_cmd_byte_addr ) ,
-  .next          ( next               ) ,
-  .next_pending  ( incr_next_pending  ) 
-);
-
-axi_protocol_converter_v2_1_9_b2s_wrap_cmd #(
-  .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
-)
-wrap_cmd_0
-(
-  .clk           ( clk                ) ,
-  .reset         ( reset              ) ,
-  .axaddr        ( s_axaddr           ) ,
-  .axlen         ( s_axlen            ) ,
-  .axsize        ( s_axsize           ) ,
-  .axhandshake   ( s_axhandshake      ) ,
-  .cmd_byte_addr ( wrap_cmd_byte_addr ) ,
-  .next          ( next               ) ,
-  .next_pending  ( wrap_next_pending  ) 
-);
-
-endmodule
-`default_nettype wire
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_incr_cmd.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_incr_cmd.v
deleted file mode 100755
index 8a50f22faf92bc12a33691a07838144dc240e400..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_incr_cmd.v
+++ /dev/null
@@ -1,131 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//
-// File name: axi_protocol_converter_v2_1_9_b2s_incr_cmd.v
-//
-///////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_b2s_incr_cmd #
-(
-///////////////////////////////////////////////////////////////////////////////
-// Parameter Definitions
-///////////////////////////////////////////////////////////////////////////////
-                    // Width of AxADDR
-                    // Range: 32.
-  parameter integer C_AXI_ADDR_WIDTH            = 32
-)
-(
-///////////////////////////////////////////////////////////////////////////////
-// Port Declarations
-///////////////////////////////////////////////////////////////////////////////
-  input  wire                                 clk           ,
-  input  wire                                 reset         ,
-  input  wire [C_AXI_ADDR_WIDTH-1:0]          axaddr        ,
-  input  wire [7:0]                           axlen         ,
-  input  wire [2:0]                           axsize        ,
-  // axhandshake = axvalid & axready
-  input  wire                                 axhandshake   ,
-  output wire [C_AXI_ADDR_WIDTH-1:0]          cmd_byte_addr ,
-  // Connections to/from fsm module
-  // signal to increment to the next mc transaction
-  input  wire                                 next          ,
-  // signal to the fsm there is another transaction required
-  output reg                                  next_pending
-
-);
-////////////////////////////////////////////////////////////////////////////////
-// Wire and register declarations
-////////////////////////////////////////////////////////////////////////////////
-reg                           sel_first;
-reg  [11:0]                   axaddr_incr;
-reg  [8:0]                    axlen_cnt;
-reg                           next_pending_r;
-wire [3:0]                    axsize_shift;
-wire [11:0]                   axsize_mask;
-
-localparam    L_AXI_ADDR_LOW_BIT = (C_AXI_ADDR_WIDTH >= 12) ? 12 : 11;
-
-////////////////////////////////////////////////////////////////////////////////
-// BEGIN RTL
-////////////////////////////////////////////////////////////////////////////////
-
-// calculate cmd_byte_addr
-generate
-  if (C_AXI_ADDR_WIDTH > 12) begin : ADDR_GT_4K
-    assign cmd_byte_addr = (sel_first) ? axaddr : {axaddr[C_AXI_ADDR_WIDTH-1:L_AXI_ADDR_LOW_BIT],axaddr_incr[11:0]};
-  end else begin : ADDR_4K
-    assign cmd_byte_addr = (sel_first) ? axaddr : axaddr_incr[11:0];
-  end
-endgenerate
-
-assign axsize_shift = (1 << axsize[1:0]);
-assign axsize_mask  = ~(axsize_shift - 1'b1);
-
-// Incremented version of axaddr
-always @(posedge clk) begin
-  if (sel_first) begin
-    if(~next) begin
-      axaddr_incr <= axaddr[11:0] & axsize_mask;
-    end else begin
-      axaddr_incr <= (axaddr[11:0] & axsize_mask) + axsize_shift;
-    end
-  end else if (next) begin
-    axaddr_incr <= axaddr_incr + axsize_shift;
-  end
-end
-
-always @(posedge clk) begin
-  if (axhandshake)begin
-     axlen_cnt <= axlen;
-     next_pending_r <= (axlen >= 1);
-  end else if (next) begin
-    if (axlen_cnt > 1) begin
-      axlen_cnt <= axlen_cnt - 1;
-      next_pending_r <= ((axlen_cnt - 1) >= 1);
-    end else begin
-      axlen_cnt <= 9'd0;
-      next_pending_r <= 1'b0;
-    end
-  end
-end
-
-always @( * ) begin
-  if (axhandshake)begin
-     next_pending = (axlen >= 1);
-  end else if (next) begin
-    if (axlen_cnt > 1) begin
-      next_pending = ((axlen_cnt - 1) >= 1);
-    end else begin
-      next_pending = 1'b0;
-    end
-  end else begin
-    next_pending = next_pending_r;
-  end
-end
-
-// last and ignore signals to data channel. These signals are used for
-// BL8 to ignore and insert data for even len transactions with offset
-// and odd len transactions
-// For odd len transactions with no offset the last read is ignored and
-// last write is masked
-// For odd len transactions with offset the first read is ignored and
-// first write is masked
-// For even len transactions with offset the last & first read is ignored and
-// last& first  write is masked
-// For even len transactions no ingnores or masks.
-
-// Indicates if we are on the first transaction of a mc translation with more
-// than 1 transaction.
-always @(posedge clk) begin
-  if (reset | axhandshake) begin
-    sel_first <= 1'b1;
-  end else if (next) begin
-    sel_first <= 1'b0;
-  end
-end
-
-endmodule
-`default_nettype wire
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_r_channel.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_r_channel.v
deleted file mode 100755
index 4eacdf381976524aa37399ea321e17fdd9921051..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_r_channel.v
+++ /dev/null
@@ -1,174 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//
-// File name: axi_protocol_converter_v2_1_9_b2s_r_channel.v
-//
-// Description:
-// Read data channel module to buffer read data from MC, ignore
-// extra data in case of BL8 and send the data to AXI.
-// The MC will send out the read data as it is ready and it has to be
-// accepted. The read data FIFO in the axi_protocol_converter_v2_1_9_b2s_r_channel module will buffer
-// the data before being sent to AXI. The address channel module will
-// send the transaction information for every command that is sent to the
-// MC. The transaction information will be buffered in a transaction FIFO.
-// Based on the transaction FIFO information data will be ignored in
-// BL8 mode and the last signal to the AXI will be asserted.
-
-///////////////////////////////////////////////////////////////////////////////
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_b2s_r_channel #
-(
-///////////////////////////////////////////////////////////////////////////////
-// Parameter Definitions
-///////////////////////////////////////////////////////////////////////////////
-                    // Width of ID signals.
-                    // Range: >= 1.
-  parameter integer C_ID_WIDTH                = 4,
-                    // Width of AXI xDATA and MCB xx_data
-                    // Range: 32, 64, 128.
-  parameter integer C_DATA_WIDTH              = 32
-)
-(
-///////////////////////////////////////////////////////////////////////////////
-// Port Declarations
-///////////////////////////////////////////////////////////////////////////////
-  input  wire                                 clk              ,
-  input  wire                                 reset            ,
-
-  output wire  [C_ID_WIDTH-1:0]               s_rid              ,
-  output wire  [C_DATA_WIDTH-1:0]             s_rdata            ,
-  output wire [1:0]                           s_rresp            ,
-  output wire                                 s_rlast            ,
-  output wire                                 s_rvalid           ,
-  input  wire                                 s_rready           ,
-
-  input  wire [C_DATA_WIDTH-1:0]              m_rdata   ,
-  input  wire [1:0]                           m_rresp   ,
-  input  wire                                 m_rvalid  ,
-  output wire                                 m_rready  ,
-
-  // Connections to/from axi_protocol_converter_v2_1_9_b2s_ar_channel module
-  input  wire                                 r_push           ,
-  output wire                                 r_full           ,
-  // length not needed. Can be removed.
-  input  wire [C_ID_WIDTH-1:0]                r_arid           ,
-  input  wire                                 r_rlast
-
-);
-
-////////////////////////////////////////////////////////////////////////////////
-// Local parameters
-////////////////////////////////////////////////////////////////////////////////
-localparam P_WIDTH = 1+C_ID_WIDTH;
-localparam P_DEPTH = 32;
-localparam P_AWIDTH = 5;
-localparam P_D_WIDTH = C_DATA_WIDTH + 2;
-// rd data FIFO depth varies based on burst length.
-// For Bl8 it is two times the size of transaction FIFO.
-// Only in 2:1 mode BL8 transactions will happen which results in
-// two beats of read data per read transaction.
-localparam P_D_DEPTH  = 32;
-localparam P_D_AWIDTH = 5;
-
-////////////////////////////////////////////////////////////////////////////////
-// Wire and register declarations
-////////////////////////////////////////////////////////////////////////////////
-
-wire [C_ID_WIDTH+1-1:0]    trans_in;
-wire [C_ID_WIDTH+1-1:0]    trans_out;
-wire                       tr_empty;
-
-wire                       rhandshake;
-wire                       r_valid_i;
-wire [P_D_WIDTH-1:0]       rd_data_fifo_in;
-wire [P_D_WIDTH-1:0]       rd_data_fifo_out;
-wire                       rd_en;
-wire                       rd_full;
-wire                       rd_empty;
-wire                       rd_a_full;
-wire                       fifo_a_full;
-
-reg [C_ID_WIDTH-1:0]       r_arid_r;
-reg                        r_rlast_r;
-reg                        r_push_r;
-
-wire                       fifo_full;
-
-
-////////////////////////////////////////////////////////////////////////////////
-// BEGIN RTL
-////////////////////////////////////////////////////////////////////////////////
-
-assign s_rresp  = rd_data_fifo_out[P_D_WIDTH-1:C_DATA_WIDTH];
-assign s_rid    = trans_out[1+:C_ID_WIDTH];
-assign s_rdata  = rd_data_fifo_out[C_DATA_WIDTH-1:0];
-assign s_rlast  = trans_out[0];
-assign s_rvalid = ~rd_empty & ~tr_empty;
-
-
-// assign MCB outputs
-assign rd_en      = rhandshake & (~rd_empty);
-
-assign rhandshake =(s_rvalid & s_rready);
-
-// register for timing
-
-always @(posedge clk) begin
-  r_arid_r <= r_arid;
-  r_rlast_r <= r_rlast;
-  r_push_r <= r_push;
-end
-
-assign trans_in[0]  = r_rlast_r;
-assign trans_in[1+:C_ID_WIDTH]  = r_arid_r;
-
-
-// rd data fifo
-axi_protocol_converter_v2_1_9_b2s_simple_fifo #(
-  .C_WIDTH                (P_D_WIDTH),
-  .C_AWIDTH               (P_D_AWIDTH),
-  .C_DEPTH                (P_D_DEPTH)
-)
-rd_data_fifo_0
-(
-  .clk     ( clk              ) ,
-  .rst     ( reset            ) ,
-  .wr_en   ( m_rvalid & m_rready ) ,
-  .rd_en   ( rd_en            ) ,
-  .din     ( rd_data_fifo_in  ) ,
-  .dout    ( rd_data_fifo_out ) ,
-  .a_full  ( rd_a_full        ) ,
-  .full    ( rd_full          ) ,
-  .a_empty (                  ) ,
-  .empty   ( rd_empty         )
-);
-
-assign rd_data_fifo_in = {m_rresp, m_rdata};
-
-axi_protocol_converter_v2_1_9_b2s_simple_fifo #(
-  .C_WIDTH                  (P_WIDTH),
-  .C_AWIDTH                 (P_AWIDTH),
-  .C_DEPTH                  (P_DEPTH)
-)
-transaction_fifo_0
-(
-  .clk     ( clk         ) ,
-  .rst     ( reset       ) ,
-  .wr_en   ( r_push_r    ) ,
-  .rd_en   ( rd_en       ) ,
-  .din     ( trans_in    ) ,
-  .dout    ( trans_out   ) ,
-  .a_full  ( fifo_a_full ) ,
-  .full    (             ) ,
-  .a_empty (             ) ,
-  .empty   ( tr_empty    )
-);
-
-assign fifo_full = fifo_a_full | rd_a_full ;
-assign r_full = fifo_full ;
-assign m_rready = ~rd_a_full;
-
-endmodule
-`default_nettype wire
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v
deleted file mode 100755
index 3c89a844583fefc466bda7c45fb3d0c55945c7fa..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v
+++ /dev/null
@@ -1,122 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//
-// File name: axi_protocol_converter_v2_1_9_b2s_rd_cmd_fsm.v
-//
-///////////////////////////////////////////////////////////////////////////////
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_b2s_rd_cmd_fsm (
-///////////////////////////////////////////////////////////////////////////////
-// Port Declarations
-///////////////////////////////////////////////////////////////////////////////
-  input  wire                                 clk           ,
-  input  wire                                 reset         ,
-  output wire                                 s_arready       ,
-  input  wire                                 s_arvalid       ,
-  input  wire [7:0]                           s_arlen         ,
-  output wire                                 m_arvalid        ,
-  input  wire                                 m_arready      ,
-  // signal to increment to the next mc transaction
-  output wire                                 next          ,
-  // signal to the fsm there is another transaction required
-  input  wire                                 next_pending  ,
-  // Write Data portion has completed or Read FIFO has a slot available (not
-  // full)
-  input  wire                                 data_ready    ,
-  // status signal for w_channel when command is written.
-  output wire                                 a_push        ,
-  output wire                                 r_push
-);
-
-////////////////////////////////////////////////////////////////////////////////
-// Local parameters
-////////////////////////////////////////////////////////////////////////////////
-// States
-localparam SM_IDLE                = 2'b00;
-localparam SM_CMD_EN              = 2'b01;
-localparam SM_CMD_ACCEPTED        = 2'b10;
-localparam SM_DONE                = 2'b11;
-
-////////////////////////////////////////////////////////////////////////////////
-// Wires/Reg declarations
-////////////////////////////////////////////////////////////////////////////////
-reg [1:0]       state;
-// synthesis attribute MAX_FANOUT of state is 20;
-reg [1:0]       state_r1;
-reg [1:0]       next_state;
-reg [7:0]       s_arlen_r;
-
-////////////////////////////////////////////////////////////////////////////////
-// BEGIN RTL
-///////////////////////////////////////////////////////////////////////////////
-
-
-// register for timing
-always @(posedge clk) begin
-  if (reset) begin
-    state <= SM_IDLE;
-    state_r1 <= SM_IDLE;
-    s_arlen_r  <= 0;
-  end else begin
-    state <= next_state;
-    state_r1 <= state;
-    s_arlen_r  <= s_arlen;
-  end
-end
-
-// Next state transitions.
-always @( * ) begin
-  next_state = state;
-  case (state)
-    SM_IDLE:
-      if (s_arvalid & data_ready) begin
-        next_state = SM_CMD_EN;
-      end else begin
-        next_state = state;
-      end
-    SM_CMD_EN:
-    ///////////////////////////////////////////////////////////////////
-    // Drive m_arvalid downstream in this state
-      ///////////////////////////////////////////////////////////////////
-      //If there is no fifo space
-      if (~data_ready & m_arready & next_pending) begin
-        ///////////////////////////////////////////////////////////////////
-        //There is more to do, wait until data space is available drop valid
-        next_state = SM_CMD_ACCEPTED;
-      end else if (m_arready & ~next_pending)begin
-         next_state = SM_DONE;
-      end else if (m_arready & next_pending) begin
-        next_state = SM_CMD_EN;
-      end else begin
-        next_state = state;
-      end
-
-    SM_CMD_ACCEPTED:
-      if (data_ready) begin
-        next_state = SM_CMD_EN;
-      end else begin
-        next_state = state;
-      end
-
-    SM_DONE:
-        next_state = SM_IDLE;
-
-      default:
-        next_state = SM_IDLE;
-  endcase
-end
-
-// Assign outputs based on current state.
-
-assign m_arvalid  = (state == SM_CMD_EN);
-assign next    = m_arready && (state == SM_CMD_EN);
-assign         r_push  = next;
-assign a_push  = (state == SM_IDLE);
-assign s_arready = ((state == SM_CMD_EN) || (state == SM_DONE))  && (next_state == SM_IDLE);
-
-endmodule
-`default_nettype wire
-
-
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v
deleted file mode 100755
index 60fdc78cc050c33bb429e8db673226d095c1ed6e..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v
+++ /dev/null
@@ -1,83 +0,0 @@
-//-----------------------------------------------
-// This is the simplest form of inferring the
-// simple/SRL(16/32)CE in a Xilinx FPGA.
-//-----------------------------------------------
-`timescale 1ns / 100ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_b2s_simple_fifo #
-(
-  parameter C_WIDTH  = 8,
-  parameter C_AWIDTH = 4,
-  parameter C_DEPTH  = 16
-)
-(
-  input  wire               clk,       // Main System Clock  (Sync FIFO)
-  input  wire               rst,       // FIFO Counter Reset (Clk
-  input  wire               wr_en,     // FIFO Write Enable  (Clk)
-  input  wire               rd_en,     // FIFO Read Enable   (Clk)
-  input  wire [C_WIDTH-1:0] din,       // FIFO Data Input    (Clk)
-  output wire [C_WIDTH-1:0] dout,      // FIFO Data Output   (Clk)
-  output wire               a_full,
-  output wire               full,      // FIFO FULL Status   (Clk)
-  output wire               a_empty,
-  output wire               empty      // FIFO EMPTY Status  (Clk)
-);
-
-///////////////////////////////////////
-// FIFO Local Parameters
-///////////////////////////////////////
-localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
-localparam [C_AWIDTH-1:0] C_EMPTY_PRE =  (0);
-localparam [C_AWIDTH-1:0] C_FULL  = C_EMPTY-1;
-localparam [C_AWIDTH-1:0] C_FULL_PRE  = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
- 
-///////////////////////////////////////
-// FIFO Internal Signals
-///////////////////////////////////////
-reg [C_WIDTH-1:0]  memory [C_DEPTH-1:0];
-reg [C_AWIDTH-1:0] cnt_read;
-  // synthesis attribute MAX_FANOUT of cnt_read is 10; 
-
-///////////////////////////////////////
-// Main simple FIFO Array
-///////////////////////////////////////
-always @(posedge clk) begin : BLKSRL
-integer i;
-  if (wr_en) begin
-    for (i = 0; i < C_DEPTH-1; i = i + 1) begin
-      memory[i+1] <= memory[i];
-    end
-    memory[0] <= din;
-  end
-end
-
-///////////////////////////////////////
-// Read Index Counter
-// Up/Down Counter
-//  *** Notice that there is no ***
-//  *** OVERRUN protection.     ***
-///////////////////////////////////////
-always @(posedge clk) begin
-  if (rst) cnt_read <= C_EMPTY;
-  else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
-  else if (!wr_en &  rd_en) cnt_read <= cnt_read - 1'b1;
-end
-
-///////////////////////////////////////
-// Status Flags / Outputs
-// These could be registered, but would
-// increase logic in order to pre-decode
-// FULL/EMPTY status.
-///////////////////////////////////////
-assign full  = (cnt_read == C_FULL);
-assign empty = (cnt_read == C_EMPTY);
-assign a_full  = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
-assign a_empty = (cnt_read == C_EMPTY_PRE);
-
-assign dout  = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
-
-endmodule // axi_protocol_converter_v2_1_9_b2s_simple_fifo
-
-`default_nettype wire
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v
deleted file mode 100755
index 26073c61edef88aa6cc89b5c7eb025f390ef1613..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v
+++ /dev/null
@@ -1,109 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//
-// File name: axi_protocol_converter_v2_1_9_b2s_wr_cmd_fsm.v
-//
-///////////////////////////////////////////////////////////////////////////////
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_b2s_wr_cmd_fsm (
-///////////////////////////////////////////////////////////////////////////////
-// Port Declarations
-///////////////////////////////////////////////////////////////////////////////
-  input  wire                                 clk           ,
-  input  wire                                 reset         ,
-  output wire                                 s_awready       ,
-  input  wire                                 s_awvalid       ,
-  output wire                                 m_awvalid        ,
-  input  wire                                 m_awready      ,
-  // signal to increment to the next mc transaction
-  output wire                                 next          ,
-  // signal to the fsm there is another transaction required
-  input  wire                                 next_pending  ,
-  // Write Data portion has completed or Read FIFO has a slot available (not
-  // full)
-  output wire                                 b_push        ,
-  input  wire                                 b_full        ,
-  output wire                                 a_push
-);
-
-////////////////////////////////////////////////////////////////////////////////
-// Local parameters
-////////////////////////////////////////////////////////////////////////////////
-// States
-localparam SM_IDLE                = 2'b00;
-localparam SM_CMD_EN              = 2'b01;
-localparam SM_CMD_ACCEPTED        = 2'b10;
-localparam SM_DONE_WAIT           = 2'b11;
-
-////////////////////////////////////////////////////////////////////////////////
-// Wires/Reg declarations
-////////////////////////////////////////////////////////////////////////////////
-reg [1:0]       state;
-// synthesis attribute MAX_FANOUT of state is 20;
-reg [1:0]       next_state;
-
-////////////////////////////////////////////////////////////////////////////////
-// BEGIN RTL
-///////////////////////////////////////////////////////////////////////////////
-
-
-always @(posedge clk) begin
-  if (reset) begin
-    state <= SM_IDLE;
-  end else begin
-    state <= next_state;
-  end
-end
-
-// Next state transitions.
-always @( * )
-begin
-  next_state = state;
-  case (state)
-    SM_IDLE:
-      if (s_awvalid) begin
-        next_state = SM_CMD_EN;
-      end else
-        next_state = state;
-
-    SM_CMD_EN:
-      if (m_awready & next_pending)
-        next_state = SM_CMD_ACCEPTED;
-      else if (m_awready & ~next_pending & b_full)
-        next_state = SM_DONE_WAIT;
-      else if (m_awready & ~next_pending & ~b_full)
-        next_state = SM_IDLE;
-      else
-        next_state = state;
-
-    SM_CMD_ACCEPTED:
-      next_state = SM_CMD_EN;
-
-    SM_DONE_WAIT:
-      if (!b_full)
-        next_state = SM_IDLE;
-      else
-        next_state = state;
-
-      default:
-        next_state = SM_IDLE;
-  endcase
-end
-
-// Assign outputs based on current state.
-
-assign m_awvalid  = (state == SM_CMD_EN);
-
-assign next    = ((state == SM_CMD_ACCEPTED)
-                 | (((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE))) ;
-
-assign a_push  = (state == SM_IDLE);
-assign s_awready = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
-assign b_push  = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
-
-endmodule
-`default_nettype wire
-
-
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wrap_cmd.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wrap_cmd.v
deleted file mode 100755
index 7fde4a8c65dbf2300f43a59e82ec1dfd06e3a877..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wrap_cmd.v
+++ /dev/null
@@ -1,188 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-//
-// File name: axi_protocol_converter_v2_1_9_b2s_wrap_cmd.v
-//
-///////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_b2s_wrap_cmd #
-(
-///////////////////////////////////////////////////////////////////////////////
-// Parameter Definitions
-///////////////////////////////////////////////////////////////////////////////
-                    // Width of AxADDR
-                    // Range: 32.
-  parameter integer C_AXI_ADDR_WIDTH            = 32
-)
-(
-///////////////////////////////////////////////////////////////////////////////
-// Port Declarations     
-///////////////////////////////////////////////////////////////////////////////
-  input  wire                                 clk           , 
-  input  wire                                 reset         , 
-  input  wire [C_AXI_ADDR_WIDTH-1:0]          axaddr        , 
-  input  wire [7:0]                           axlen         , 
-  input  wire [2:0]                           axsize        , 
-  // axhandshake = axvalid & axready
-  input  wire                                 axhandshake   , 
-  output wire [C_AXI_ADDR_WIDTH-1:0]          cmd_byte_addr , 
-
-  // Connections to/from fsm module
-  // signal to increment to the next mc transaction 
-  input  wire                                 next          , 
-  // signal to the fsm there is another transaction required
-  output reg                                  next_pending 
-
-);
-////////////////////////////////////////////////////////////////////////////////
-// Wire and register declarations
-////////////////////////////////////////////////////////////////////////////////
-reg                         sel_first;
-wire [11:0]                 axaddr_i;
-wire [3:0]                  axlen_i;
-reg  [11:0]                 wrap_boundary_axaddr;
-reg  [3:0]                  axaddr_offset;
-reg  [3:0]                  wrap_second_len;
-reg  [11:0]                 wrap_boundary_axaddr_r;
-reg  [3:0]                  axaddr_offset_r;
-reg  [3:0]                  wrap_second_len_r;
-reg  [4:0]                  axlen_cnt;
-reg  [4:0]                  wrap_cnt_r;
-wire [4:0]                  wrap_cnt;
-reg  [11:0]                 axaddr_wrap;
-reg                         next_pending_r;
-
-localparam    L_AXI_ADDR_LOW_BIT = (C_AXI_ADDR_WIDTH >= 12) ? 12 : 11;
-
-////////////////////////////////////////////////////////////////////////////////
-// BEGIN RTL
-////////////////////////////////////////////////////////////////////////////////
-generate
-  if (C_AXI_ADDR_WIDTH > 12) begin : ADDR_GT_4K
-    assign cmd_byte_addr = (sel_first) ? axaddr : {axaddr[C_AXI_ADDR_WIDTH-1:L_AXI_ADDR_LOW_BIT],axaddr_wrap[11:0]};
-  end else begin : ADDR_4K
-    assign cmd_byte_addr = (sel_first) ? axaddr : axaddr_wrap[11:0];
-  end
-endgenerate
-
-assign axaddr_i = axaddr[11:0];
-assign axlen_i = axlen[3:0];
-
-// Mask bits based on transaction length to get wrap boundary low address
-// Offset used to calculate the length of each transaction
-always @( * ) begin
-  if(axhandshake) begin
-    wrap_boundary_axaddr = axaddr_i & ~(axlen_i << axsize[1:0]);
-    axaddr_offset = axaddr_i[axsize[1:0] +: 4] & axlen_i;
-  end else begin
-    wrap_boundary_axaddr = wrap_boundary_axaddr_r;
-    axaddr_offset = axaddr_offset_r; 
-  end
-end
-
-//    case (axsize[1:0])
-//      2'b00   : axaddr_offset = axaddr_i[4:0] & axlen_i;
-//      2'b01   : axaddr_offset = axaddr_i[5:1] & axlen_i;
-//      2'b10   : axaddr_offset = axaddr_i[6:2] & axlen_i;
-//      2'b11   : axaddr_offset = axaddr_i[7:3] & axlen_i;
-//      default : axaddr_offset = axaddr_i[7:3] & axlen_i;
-//    endcase
-
-// The first and the second command from the wrap transaction could
-// be of odd length or even length with address offset. This will be 
-// an issue with BL8, extra transactions have to be issued.
-// Rounding up the length to account for extra transactions. 
-always @( * ) begin
-  if(axhandshake) begin
-    wrap_second_len = (axaddr_offset >0) ? axaddr_offset - 1 : 0;
-  end else begin
-    wrap_second_len = wrap_second_len_r;
-  end
-end
-
-// registering to be used in the combo logic. 
-always @(posedge clk) begin
-  wrap_boundary_axaddr_r <= wrap_boundary_axaddr;
-  axaddr_offset_r <= axaddr_offset;
-  wrap_second_len_r <= wrap_second_len;
-end
-   
-// determining if extra data is required for even offsets
-
-// wrap_cnt used to switch the address for first and second transaction.
-assign wrap_cnt = {1'b0, wrap_second_len + {3'b000, (|axaddr_offset)}}; 
-
-always @(posedge clk)
-  wrap_cnt_r <= wrap_cnt;
-
-always @(posedge clk) begin
-  if (axhandshake) begin
-    axaddr_wrap <= axaddr[11:0];
-  end if(next)begin
-    if(axlen_cnt == wrap_cnt_r) begin
-      axaddr_wrap <= wrap_boundary_axaddr_r;
-    end else begin
-      axaddr_wrap <= axaddr_wrap + (1 << axsize[1:0]);
-    end
-  end
-end 
-
-
-
-// Even numbber of transactions with offset, inc len by 2 for BL8
-always @(posedge clk) begin
-  if (axhandshake)begin
-    axlen_cnt <= axlen_i;
-    next_pending_r <= axlen_i >= 1;
-  end else if (next) begin
-    if (axlen_cnt > 1) begin
-      axlen_cnt <= axlen_cnt - 1;
-      next_pending_r <= (axlen_cnt - 1) >= 1;
-    end else begin
-      axlen_cnt <= 5'd0;
-      next_pending_r <= 1'b0;
-    end
-  end  
-end  
-
-always @( * ) begin
-  if (axhandshake)begin
-    next_pending = axlen_i >= 1;
-  end else if (next) begin
-    if (axlen_cnt > 1) begin
-      next_pending = (axlen_cnt - 1) >= 1;
-    end else begin
-      next_pending = 1'b0;
-    end
-  end else begin
-    next_pending = next_pending_r;
-  end 
-end  
-
-// last and ignore signals to data channel. These signals are used for
-// BL8 to ignore and insert data for even len transactions with offset
-// and odd len transactions
-// For odd len transactions with no offset the last read is ignored and
-// last write is masked
-// For odd len transactions with offset the first read is ignored and
-// first write is masked
-// For even len transactions with offset the last & first read is ignored and
-// last& first  write is masked
-// For even len transactions no ingnores or masks. 
-
-
-// Indicates if we are on the first transaction of a mc translation with more
-// than 1 transaction.
-always @(posedge clk) begin
-  if (reset | axhandshake) begin
-    sel_first <= 1'b1;
-  end else if (next) begin
-    sel_first <= 1'b0;
-  end
-end
-
-endmodule
-`default_nettype wire
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b_downsizer.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b_downsizer.v
deleted file mode 100755
index 613fdc84d55b2660babcd361cb14c6fe8bb3d747..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b_downsizer.v
+++ /dev/null
@@ -1,305 +0,0 @@
-// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
-// --
-// -- This file contains confidential and proprietary information
-// -- of Xilinx, Inc. and is protected under U.S. and 
-// -- international copyright and other intellectual property
-// -- laws.
-// --
-// -- DISCLAIMER
-// -- This disclaimer is not a license and does not grant any
-// -- rights to the materials distributed herewith. Except as
-// -- otherwise provided in a valid license issued to you by
-// -- Xilinx, and to the maximum extent permitted by applicable
-// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// -- (2) Xilinx shall not be liable (whether in contract or tort,
-// -- including negligence, or under any other theory of
-// -- liability) for any loss or damage of any kind or nature
-// -- related to, arising under or in connection with these
-// -- materials, including for any direct, or any indirect,
-// -- special, incidental, or consequential loss or damage
-// -- (including loss of data, profits, goodwill, or any type of
-// -- loss or damage suffered as a result of any action brought
-// -- by a third party) even if such damage or loss was
-// -- reasonably foreseeable or Xilinx had been advised of the
-// -- possibility of the same.
-// --
-// -- CRITICAL APPLICATIONS
-// -- Xilinx products are not designed or intended to be fail-
-// -- safe, or for use in any application requiring fail-safe
-// -- performance, such as life-support or safety devices or
-// -- systems, Class III medical devices, nuclear facilities,
-// -- applications related to the deployment of airbags, or any
-// -- other applications that could lead to death, personal
-// -- injury, or severe property or environmental damage
-// -- (individually and collectively, "Critical
-// -- Applications"). Customer assumes the sole risk and
-// -- liability of any use of Xilinx products in Critical
-// -- Applications, subject only to applicable laws and
-// -- regulations governing limitations on product liability.
-// --
-// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// -- PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-//
-// Description: Write Data Response Down-Sizer
-// Collect MI-side responses and set the SI-side response to the most critical
-// level (in descending order):
-//    DECERR, SLVERROR and OKAY.
-// EXOKAY cannot occur for split transactions. 
-//
-//
-// Verilog-standard:  Verilog 2001
-//--------------------------------------------------------------------------
-//
-// Structure:
-//   wr_upsizer
-//
-//--------------------------------------------------------------------------
-`timescale 1ps/1ps
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_b_downsizer #
-  (
-   parameter         C_FAMILY                         = "none", 
-                       // FPGA Family. Current version: virtex6 or spartan6.
-   parameter integer C_AXI_ID_WIDTH                   = 4, 
-                       // Width of all ID signals on SI and MI side of converter.
-                       // Range: >= 1.
-   parameter integer C_AXI_SUPPORTS_USER_SIGNALS      = 0,
-                       // 1 = Propagate all USER signals, 0 = Don�t propagate.
-   parameter integer C_AXI_BUSER_WIDTH                = 1
-                       // Width of BUSER signals. 
-                       // Range: >= 1.
-   )
-  (
-   // Global Signals
-   input  wire                                                    ARESET,
-   input  wire                                                    ACLK,
-
-   // Command Interface
-   input  wire                              cmd_valid,
-   input  wire                              cmd_split,
-   input  wire [4-1:0]                      cmd_repeat,
-   output wire                              cmd_ready,
-   
-   // Slave Interface Write Response Ports
-   output wire [C_AXI_ID_WIDTH-1:0]           S_AXI_BID,
-   output wire [2-1:0]                          S_AXI_BRESP,
-   output wire [C_AXI_BUSER_WIDTH-1:0]          S_AXI_BUSER,
-   output wire                                                    S_AXI_BVALID,
-   input  wire                                                    S_AXI_BREADY,
-
-   // Master Interface Write Response Ports
-   input  wire [C_AXI_ID_WIDTH-1:0]          M_AXI_BID,
-   input  wire [2-1:0]                         M_AXI_BRESP,
-   input  wire [C_AXI_BUSER_WIDTH-1:0]         M_AXI_BUSER,
-   input  wire                                                   M_AXI_BVALID,
-   output wire                                                   M_AXI_BREADY
-   );
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Variables for generating parameter controlled instances.
-  /////////////////////////////////////////////////////////////////////////////
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Local params
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Constants for packing levels.
-  localparam [2-1:0] C_RESP_OKAY        = 2'b00;
-  localparam [2-1:0] C_RESP_EXOKAY      = 2'b01;
-  localparam [2-1:0] C_RESP_SLVERROR    = 2'b10;
-  localparam [2-1:0] C_RESP_DECERR      = 2'b11;
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Functions
-  /////////////////////////////////////////////////////////////////////////////
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Internal signals
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Throttling help signals.
-  wire                            cmd_ready_i;
-  wire                            pop_mi_data;
-  wire                            mi_stalling;
-  
-  // Repeat handling related.
-  reg  [4-1:0]                    repeat_cnt_pre;
-  reg  [4-1:0]                    repeat_cnt;
-  wire [4-1:0]                    next_repeat_cnt;
-  reg                             first_mi_word;
-  wire                            last_word;
-  
-  // Ongoing split transaction.
-  wire                            load_bresp;
-  wire                            need_to_update_bresp;
-  reg  [2-1:0]                    S_AXI_BRESP_ACC;
-  
-  // Internal signals for MI-side.
-  wire                            M_AXI_BREADY_I;
-  
-  // Internal signals for SI-side.
-  wire [C_AXI_ID_WIDTH-1:0]       S_AXI_BID_I;
-  reg  [2-1:0]                    S_AXI_BRESP_I;
-  wire [C_AXI_BUSER_WIDTH-1:0]    S_AXI_BUSER_I;
-  wire                            S_AXI_BVALID_I;
-  wire                            S_AXI_BREADY_I;
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Handle interface handshaking:
-  // 
-  // The MI-side BRESP is popped when at once for split transactions, except 
-  // for the last cycle that behaves like a "normal" transaction.
-  // A "normal" BRESP is popped once the SI-side is able to use it,
-  // 
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Pop word from MI-side.
-  assign M_AXI_BREADY_I = M_AXI_BVALID & ~mi_stalling;
-  assign M_AXI_BREADY   = M_AXI_BREADY_I;
-  
-  // Indicate when there is a BRESP available @ SI-side.
-  assign S_AXI_BVALID_I = M_AXI_BVALID & last_word;
-  
-  // Get MI-side data.
-  assign pop_mi_data    = M_AXI_BVALID & M_AXI_BREADY_I;
-  
-  // Signal that the command is done (so that it can be poped from command queue).
-  assign cmd_ready_i    = cmd_valid & pop_mi_data & last_word;
-  assign cmd_ready      = cmd_ready_i;
-  
-  // Detect when MI-side is stalling.
-  assign mi_stalling    = (~S_AXI_BREADY_I & last_word);
-                          
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Handle the accumulation of BRESP.
-  // 
-  // Forward the accumulated or MI-side BRESP value depending on state:
-  //  * MI-side BRESP is forwarded untouched when it is a non split cycle.
-  //    (MI-side BRESP value is also used when updating the accumulated for
-  //     the last access during a split access).
-  //  * The accumulated BRESP is for a split transaction.
-  // 
-  // The accumulated BRESP register is updated for each MI-side response that 
-  // is used.
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Force load accumulated BRESPs to first value
-  assign load_bresp           = (cmd_split & first_mi_word);
-  
-  // Update if more critical.
-  assign need_to_update_bresp = ( M_AXI_BRESP > S_AXI_BRESP_ACC );
-  
-  // Select accumultated or direct depending on setting.
-  always @ *
-  begin
-    if ( cmd_split ) begin
-      if ( load_bresp || need_to_update_bresp ) begin
-        S_AXI_BRESP_I = M_AXI_BRESP;
-      end else begin
-        S_AXI_BRESP_I = S_AXI_BRESP_ACC;
-      end
-    end else begin
-      S_AXI_BRESP_I = M_AXI_BRESP;
-    end
-  end
-  
-  // Accumulate MI-side BRESP.
-  always @ (posedge ACLK) begin
-    if (ARESET) begin
-      S_AXI_BRESP_ACC <= C_RESP_OKAY;
-    end else begin
-      if ( pop_mi_data ) begin
-        S_AXI_BRESP_ACC <= S_AXI_BRESP_I;
-      end
-    end
-  end
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Keep track of BRESP repeat counter.
-  //
-  // Last BRESP word is either:
-  //  * The first and only word when not merging.
-  //  * The last value when merging.
-  // 
-  // The internal counter is taken from the external command interface during
-  // the first response when merging. The counter is updated each time a
-  // BRESP is popped from the MI-side interface.
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Determine last BRESP cycle.
-  assign last_word  = ( ( repeat_cnt == 4'b0 ) & ~first_mi_word ) | 
-                      ~cmd_split;
-  
-  // Select command reapeat or counted repeat value.
-  always @ *
-  begin
-    if ( first_mi_word ) begin
-      repeat_cnt_pre  =  cmd_repeat;
-    end else begin
-      repeat_cnt_pre  =  repeat_cnt;
-    end
-  end
-  
-  // Calculate next repeat counter value.
-  assign next_repeat_cnt  = repeat_cnt_pre - 1'b1;
-  
-  // Keep track of the repeat count.
-  always @ (posedge ACLK) begin
-    if (ARESET) begin
-      repeat_cnt    <= 4'b0;
-      first_mi_word <= 1'b1;
-    end else begin
-      if ( pop_mi_data ) begin
-        repeat_cnt    <= next_repeat_cnt;
-        first_mi_word <= last_word;
-      end
-    end
-  end
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // BID Handling
-  /////////////////////////////////////////////////////////////////////////////
-  
-  assign S_AXI_BID_I  = M_AXI_BID;
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // USER Data bits
-  // 
-  // The last USER bits are simply taken from the last BRESP that is merged.
-  // Ground USER bits when unused.
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Select USER bits.
-  assign S_AXI_BUSER_I = {C_AXI_BUSER_WIDTH{1'b0}};
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // SI-side output handling
-  /////////////////////////////////////////////////////////////////////////////
-// TODO: registered?  
-  assign S_AXI_BID      = S_AXI_BID_I;
-  assign S_AXI_BRESP    = S_AXI_BRESP_I;
-  assign S_AXI_BUSER    = S_AXI_BUSER_I;
-  assign S_AXI_BVALID   = S_AXI_BVALID_I;
-  assign S_AXI_BREADY_I = S_AXI_BREADY;
-  
-  
-endmodule
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_decerr_slave.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_decerr_slave.v
deleted file mode 100755
index a37f21dea3ee1b28d20dd9f3d1abb580a7f69242..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_decerr_slave.v
+++ /dev/null
@@ -1,287 +0,0 @@
-// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
-// --
-// -- This file contains confidential and proprietary information
-// -- of Xilinx, Inc. and is protected under U.S. and 
-// -- international copyright and other intellectual property
-// -- laws.
-// --
-// -- DISCLAIMER
-// -- This disclaimer is not a license and does not grant any
-// -- rights to the materials distributed herewith. Except as
-// -- otherwise provided in a valid license issued to you by
-// -- Xilinx, and to the maximum extent permitted by applicable
-// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// -- (2) Xilinx shall not be liable (whether in contract or tort,
-// -- including negligence, or under any other theory of
-// -- liability) for any loss or damage of any kind or nature
-// -- related to, arising under or in connection with these
-// -- materials, including for any direct, or any indirect,
-// -- special, incidental, or consequential loss or damage
-// -- (including loss of data, profits, goodwill, or any type of
-// -- loss or damage suffered as a result of any action brought
-// -- by a third party) even if such damage or loss was
-// -- reasonably foreseeable or Xilinx had been advised of the
-// -- possibility of the same.
-// --
-// -- CRITICAL APPLICATIONS
-// -- Xilinx products are not designed or intended to be fail-
-// -- safe, or for use in any application requiring fail-safe
-// -- performance, such as life-support or safety devices or
-// -- systems, Class III medical devices, nuclear facilities,
-// -- applications related to the deployment of airbags, or any
-// -- other applications that could lead to death, personal
-// -- injury, or severe property or environmental damage
-// -- (individually and collectively, "Critical
-// -- Applications"). Customer assumes the sole risk and
-// -- liability of any use of Xilinx products in Critical
-// -- Applications, subject only to applicable laws and
-// -- regulations governing limitations on product liability.
-// --
-// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// -- PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-//
-// File name: decerr_slave.v
-//
-// Description: 
-//   Phantom slave interface used to complete W, R and B channel transfers when an
-//   erroneous transaction is trapped in the crossbar.
-//--------------------------------------------------------------------------
-//
-// Structure:
-//    decerr_slave
-//    
-//-----------------------------------------------------------------------------
-
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_decerr_slave #
-  (
-   parameter integer C_AXI_ID_WIDTH           = 1,
-   parameter integer C_AXI_DATA_WIDTH         = 32,
-   parameter integer C_AXI_BUSER_WIDTH        = 1,
-   parameter integer C_AXI_RUSER_WIDTH        = 1,
-   parameter integer C_AXI_PROTOCOL           = 0,
-   parameter integer C_RESP                   = 2'b11,
-   parameter integer C_IGNORE_ID              = 0
-   )
-  (
-   input   wire                                         ACLK,
-   input   wire                                         ARESETN,
-   input   wire [(C_AXI_ID_WIDTH-1):0]                  S_AXI_AWID,
-   input   wire                                         S_AXI_AWVALID,
-   output  wire                                         S_AXI_AWREADY,
-   input   wire                                         S_AXI_WLAST,
-   input   wire                                         S_AXI_WVALID,
-   output  wire                                         S_AXI_WREADY,
-   output  wire [(C_AXI_ID_WIDTH-1):0]                  S_AXI_BID,
-   output  wire [1:0]                                   S_AXI_BRESP,
-   output  wire [C_AXI_BUSER_WIDTH-1:0]                 S_AXI_BUSER,
-   output  wire                                         S_AXI_BVALID,
-   input   wire                                         S_AXI_BREADY,
-   input   wire [(C_AXI_ID_WIDTH-1):0]                  S_AXI_ARID,
-   input   wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0]   S_AXI_ARLEN,
-   input   wire                                         S_AXI_ARVALID,
-   output  wire                                         S_AXI_ARREADY,
-   output  wire [(C_AXI_ID_WIDTH-1):0]                  S_AXI_RID,
-   output  wire [(C_AXI_DATA_WIDTH-1):0]                S_AXI_RDATA,
-   output  wire [1:0]                                   S_AXI_RRESP,
-   output  wire [C_AXI_RUSER_WIDTH-1:0]                 S_AXI_RUSER,
-   output  wire                                         S_AXI_RLAST,
-   output  wire                                         S_AXI_RVALID,
-   input   wire                                         S_AXI_RREADY
-   );
-   
-  reg s_axi_awready_i;
-  reg s_axi_wready_i;
-  reg s_axi_bvalid_i;
-  reg s_axi_arready_i;
-  reg s_axi_rvalid_i;
-  
-  localparam P_WRITE_IDLE = 2'b00;
-  localparam P_WRITE_DATA = 2'b01;
-  localparam P_WRITE_RESP = 2'b10;
-  localparam P_READ_IDLE  = 2'b00;
-  localparam P_READ_START = 2'b01;
-  localparam P_READ_DATA  = 2'b10;
-  localparam integer  P_AXI4 = 0;
-  localparam integer  P_AXI3 = 1;
-  localparam integer  P_AXILITE = 2;
-   
-  assign S_AXI_BRESP = C_RESP;
-  assign S_AXI_RRESP = C_RESP;
-  assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
-  assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
-  assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
-  assign S_AXI_AWREADY = s_axi_awready_i;
-  assign S_AXI_WREADY = s_axi_wready_i;
-  assign S_AXI_BVALID = s_axi_bvalid_i;
-  assign S_AXI_ARREADY = s_axi_arready_i;
-  assign S_AXI_RVALID = s_axi_rvalid_i;
-  
-  generate
-  if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
-    
-    reg s_axi_rvalid_en;
-    assign S_AXI_RLAST = 1'b1;
-    assign S_AXI_BID = 0;
-    assign S_AXI_RID = 0;
-    
-    always @(posedge ACLK) begin
-      if (~ARESETN) begin
-        s_axi_awready_i <= 1'b0;
-        s_axi_wready_i <= 1'b0;
-        s_axi_bvalid_i <= 1'b0;
-      end else begin
-        if (s_axi_bvalid_i) begin
-          if (S_AXI_BREADY) begin
-            s_axi_bvalid_i <= 1'b0;
-            s_axi_awready_i <= 1'b1;
-          end
-        end else if (S_AXI_WVALID & s_axi_wready_i) begin
-            s_axi_wready_i <= 1'b0;
-            s_axi_bvalid_i <= 1'b1;
-        end else if (S_AXI_AWVALID & s_axi_awready_i) begin
-          s_axi_awready_i <= 1'b0;
-          s_axi_wready_i <= 1'b1;
-        end else begin
-          s_axi_awready_i <= 1'b1;
-        end
-      end
-    end
-           
-    always @(posedge ACLK) begin
-      if (~ARESETN) begin
-        s_axi_arready_i <= 1'b0;
-        s_axi_rvalid_i <= 1'b0;
-        s_axi_rvalid_en <= 1'b0;
-      end else begin
-        if (s_axi_rvalid_i) begin
-          if (S_AXI_RREADY) begin
-            s_axi_rvalid_i <= 1'b0;
-            s_axi_arready_i <= 1'b1;
-          end
-        end else if (s_axi_rvalid_en) begin
-          s_axi_rvalid_en <= 1'b0;
-          s_axi_rvalid_i <= 1'b1;
-        end else if (S_AXI_ARVALID & s_axi_arready_i) begin
-          s_axi_arready_i <= 1'b0;
-          s_axi_rvalid_en <= 1'b1;
-        end else begin
-          s_axi_arready_i <= 1'b1;
-        end
-      end
-    end
-        
-  end else begin : gen_axi
-  
-    reg s_axi_rlast_i;
-    reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
-    reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
-    reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt;
-    reg [1:0] write_cs;
-    reg [1:0] read_cs;
-  
-    assign S_AXI_RLAST = s_axi_rlast_i;
-    assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i;
-    assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i;
-  
-    always @(posedge ACLK) begin
-      if (~ARESETN) begin
-        write_cs <= P_WRITE_IDLE;
-        s_axi_awready_i <= 1'b0;
-        s_axi_wready_i <= 1'b0;
-        s_axi_bvalid_i <= 1'b0;
-        s_axi_bid_i <= 0;
-      end else begin
-        case (write_cs) 
-          P_WRITE_IDLE: 
-            begin
-              if (S_AXI_AWVALID & s_axi_awready_i) begin
-                s_axi_awready_i <= 1'b0;
-                if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID;
-                s_axi_wready_i <= 1'b1;
-                write_cs <= P_WRITE_DATA;
-              end else begin
-                s_axi_awready_i <= 1'b1;
-              end
-            end
-          P_WRITE_DATA:
-            begin
-              if (S_AXI_WVALID & S_AXI_WLAST) begin
-                s_axi_wready_i <= 1'b0;
-                s_axi_bvalid_i <= 1'b1;
-                write_cs <= P_WRITE_RESP;
-              end
-            end
-          P_WRITE_RESP:
-            begin
-              if (S_AXI_BREADY) begin
-                s_axi_bvalid_i <= 1'b0;
-                s_axi_awready_i <= 1'b1;
-                write_cs <= P_WRITE_IDLE;
-              end
-            end
-        endcase
-      end
-    end
-  
-    always @(posedge ACLK) begin
-      if (~ARESETN) begin
-        read_cs <= P_READ_IDLE;
-        s_axi_arready_i <= 1'b0;
-        s_axi_rvalid_i <= 1'b0;
-        s_axi_rlast_i <= 1'b0;
-        s_axi_rid_i <= 0;
-        read_cnt <= 0;
-      end else begin
-        case (read_cs) 
-          P_READ_IDLE: 
-            begin
-              if (S_AXI_ARVALID & s_axi_arready_i) begin
-                s_axi_arready_i <= 1'b0;
-                if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID;
-                read_cnt <= S_AXI_ARLEN;
-                s_axi_rlast_i <= (S_AXI_ARLEN == 0);
-                read_cs <= P_READ_START;
-              end else begin
-                s_axi_arready_i <= 1'b1;
-              end
-            end
-          P_READ_START:
-            begin
-              s_axi_rvalid_i <= 1'b1;
-              read_cs <= P_READ_DATA;
-            end
-          P_READ_DATA:
-            begin
-              if (S_AXI_RREADY) begin
-                if (read_cnt == 0) begin
-                  s_axi_rvalid_i <= 1'b0;
-                  s_axi_rlast_i <= 1'b0;
-                  s_axi_arready_i <= 1'b1;
-                  read_cs <= P_READ_IDLE;
-                end else begin
-                  if (read_cnt == 1) begin
-                    s_axi_rlast_i <= 1'b1;
-                  end
-                  read_cnt <= read_cnt - 1;
-                end
-              end
-            end
-        endcase
-      end
-    end
-  
-  end  
-  endgenerate
-
-endmodule
-
-`default_nettype wire
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_r_axi3_conv.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_r_axi3_conv.v
deleted file mode 100755
index 67ba7f9f6aa3e44cdf6f952f1ce8d1155297e056..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_r_axi3_conv.v
+++ /dev/null
@@ -1,213 +0,0 @@
-// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
-// --
-// -- This file contains confidential and proprietary information
-// -- of Xilinx, Inc. and is protected under U.S. and 
-// -- international copyright and other intellectual property
-// -- laws.
-// --
-// -- DISCLAIMER
-// -- This disclaimer is not a license and does not grant any
-// -- rights to the materials distributed herewith. Except as
-// -- otherwise provided in a valid license issued to you by
-// -- Xilinx, and to the maximum extent permitted by applicable
-// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// -- (2) Xilinx shall not be liable (whether in contract or tort,
-// -- including negligence, or under any other theory of
-// -- liability) for any loss or damage of any kind or nature
-// -- related to, arising under or in connection with these
-// -- materials, including for any direct, or any indirect,
-// -- special, incidental, or consequential loss or damage
-// -- (including loss of data, profits, goodwill, or any type of
-// -- loss or damage suffered as a result of any action brought
-// -- by a third party) even if such damage or loss was
-// -- reasonably foreseeable or Xilinx had been advised of the
-// -- possibility of the same.
-// --
-// -- CRITICAL APPLICATIONS
-// -- Xilinx products are not designed or intended to be fail-
-// -- safe, or for use in any application requiring fail-safe
-// -- performance, such as life-support or safety devices or
-// -- systems, Class III medical devices, nuclear facilities,
-// -- applications related to the deployment of airbags, or any
-// -- other applications that could lead to death, personal
-// -- injury, or severe property or environmental damage
-// -- (individually and collectively, "Critical
-// -- Applications"). Customer assumes the sole risk and
-// -- liability of any use of Xilinx products in Critical
-// -- Applications, subject only to applicable laws and
-// -- regulations governing limitations on product liability.
-// --
-// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// -- PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-//
-// Description: Read Data Response AXI3 Slave Converter
-// Forwards and re-assembles split transactions.
-//
-// Verilog-standard:  Verilog 2001
-//--------------------------------------------------------------------------
-//
-// Structure:
-//   r_axi3_conv
-//
-//--------------------------------------------------------------------------
-`timescale 1ps/1ps
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_r_axi3_conv #
-  (
-   parameter C_FAMILY                            = "none",
-   parameter integer C_AXI_ID_WIDTH              = 1,
-   parameter integer C_AXI_ADDR_WIDTH            = 32,
-   parameter integer C_AXI_DATA_WIDTH            = 32,
-   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
-   parameter integer C_AXI_RUSER_WIDTH           = 1,
-   parameter integer C_SUPPORT_SPLITTING              = 1,
-                       // Implement transaction splitting logic.
-                       // Disabled whan all connected masters are AXI3 and have same or narrower data width.
-   parameter integer C_SUPPORT_BURSTS                 = 1
-                       // Disabled when all connected masters are AxiLite,
-                       //   allowing logic to be simplified.
-   )
-  (
-   // System Signals
-   input wire ACLK,
-   input wire ARESET,
-
-   // Command Interface
-   input  wire                              cmd_valid,
-   input  wire                              cmd_split,
-   output wire                              cmd_ready,
-   
-   // Slave Interface Read Data Ports
-   output wire [C_AXI_ID_WIDTH-1:0]    S_AXI_RID,
-   output wire [C_AXI_DATA_WIDTH-1:0]  S_AXI_RDATA,
-   output wire [2-1:0]                 S_AXI_RRESP,
-   output wire                         S_AXI_RLAST,
-   output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
-   output wire                         S_AXI_RVALID,
-   input  wire                         S_AXI_RREADY,
-   
-   // Master Interface Read Data Ports
-   input  wire [C_AXI_ID_WIDTH-1:0]    M_AXI_RID,
-   input  wire [C_AXI_DATA_WIDTH-1:0]  M_AXI_RDATA,
-   input  wire [2-1:0]                 M_AXI_RRESP,
-   input  wire                         M_AXI_RLAST,
-   input  wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
-   input  wire                         M_AXI_RVALID,
-   output wire                         M_AXI_RREADY
-   );
-
-   
-  /////////////////////////////////////////////////////////////////////////////
-  // Variables for generating parameter controlled instances.
-  /////////////////////////////////////////////////////////////////////////////
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Local params
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Constants for packing levels.
-  localparam [2-1:0] C_RESP_OKAY        = 2'b00;
-  localparam [2-1:0] C_RESP_EXOKAY      = 2'b01;
-  localparam [2-1:0] C_RESP_SLVERROR    = 2'b10;
-  localparam [2-1:0] C_RESP_DECERR      = 2'b11;
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Functions
-  /////////////////////////////////////////////////////////////////////////////
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Internal signals
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Throttling help signals.
-  wire                            cmd_ready_i;
-  wire                            pop_si_data;
-  wire                            si_stalling;
-  
-  // Internal MI-side control signals.
-  wire                            M_AXI_RREADY_I;
-   
-  // Internal signals for SI-side.
-  wire [C_AXI_ID_WIDTH-1:0]       S_AXI_RID_I;
-  wire [C_AXI_DATA_WIDTH-1:0]     S_AXI_RDATA_I;
-  wire [2-1:0]                    S_AXI_RRESP_I;
-  wire                            S_AXI_RLAST_I;
-  wire [C_AXI_RUSER_WIDTH-1:0]    S_AXI_RUSER_I;
-  wire                            S_AXI_RVALID_I;
-  wire                            S_AXI_RREADY_I;
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Handle interface handshaking:
-  //
-  // Forward data from MI-Side to SI-Side while a command is available. When
-  // the transaction has completed the command is popped from the Command FIFO.
-  // 
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Pop word from SI-side.
-  assign M_AXI_RREADY_I = ~si_stalling & cmd_valid;
-  assign M_AXI_RREADY   = M_AXI_RREADY_I;
-  
-  // Indicate when there is data available @ SI-side.
-  assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
-  
-  // Get SI-side data.
-  assign pop_si_data    = S_AXI_RVALID_I & S_AXI_RREADY_I;
-  
-  // Signal that the command is done (so that it can be poped from command queue).
-  assign cmd_ready_i    = cmd_valid & pop_si_data & M_AXI_RLAST;
-  assign cmd_ready      = cmd_ready_i;
-  
-  // Detect when MI-side is stalling.
-  assign si_stalling    = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Simple AXI signal forwarding:
-  // 
-  // USER, ID, DATA and RRESP passes through untouched.
-  // 
-  // LAST has to be filtered to remove any intermediate LAST (due to split 
-  // trasactions). LAST is only removed for the first parts of a split 
-  // transaction. When splitting is unsupported is the LAST filtering completely
-  // completely removed.
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Calculate last, i.e. mask from split transactions.
-  assign S_AXI_RLAST_I  = M_AXI_RLAST & 
-                          ( ~cmd_split | ( C_SUPPORT_SPLITTING == 0 ) );
-  
-  // Data is passed through.
-  assign S_AXI_RID_I    = M_AXI_RID;
-  assign S_AXI_RUSER_I  = M_AXI_RUSER;
-  assign S_AXI_RDATA_I  = M_AXI_RDATA;
-  assign S_AXI_RRESP_I  = M_AXI_RRESP;
-      
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // SI-side output handling
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-// TODO: registered?  
-  assign S_AXI_RREADY_I = S_AXI_RREADY;
-  assign S_AXI_RVALID   = S_AXI_RVALID_I;
-  assign S_AXI_RID      = S_AXI_RID_I;
-  assign S_AXI_RDATA    = S_AXI_RDATA_I;
-  assign S_AXI_RRESP    = S_AXI_RRESP_I;
-  assign S_AXI_RLAST    = S_AXI_RLAST_I;
-  assign S_AXI_RUSER    = S_AXI_RUSER_I;
-  
-  
-endmodule
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_w_axi3_conv.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_w_axi3_conv.v
deleted file mode 100755
index 8b588874f4a82bd3e7bf80488d884d375ef42b61..0000000000000000000000000000000000000000
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_w_axi3_conv.v
+++ /dev/null
@@ -1,266 +0,0 @@
-// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
-// --
-// -- This file contains confidential and proprietary information
-// -- of Xilinx, Inc. and is protected under U.S. and 
-// -- international copyright and other intellectual property
-// -- laws.
-// --
-// -- DISCLAIMER
-// -- This disclaimer is not a license and does not grant any
-// -- rights to the materials distributed herewith. Except as
-// -- otherwise provided in a valid license issued to you by
-// -- Xilinx, and to the maximum extent permitted by applicable
-// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// -- (2) Xilinx shall not be liable (whether in contract or tort,
-// -- including negligence, or under any other theory of
-// -- liability) for any loss or damage of any kind or nature
-// -- related to, arising under or in connection with these
-// -- materials, including for any direct, or any indirect,
-// -- special, incidental, or consequential loss or damage
-// -- (including loss of data, profits, goodwill, or any type of
-// -- loss or damage suffered as a result of any action brought
-// -- by a third party) even if such damage or loss was
-// -- reasonably foreseeable or Xilinx had been advised of the
-// -- possibility of the same.
-// --
-// -- CRITICAL APPLICATIONS
-// -- Xilinx products are not designed or intended to be fail-
-// -- safe, or for use in any application requiring fail-safe
-// -- performance, such as life-support or safety devices or
-// -- systems, Class III medical devices, nuclear facilities,
-// -- applications related to the deployment of airbags, or any
-// -- other applications that could lead to death, personal
-// -- injury, or severe property or environmental damage
-// -- (individually and collectively, "Critical
-// -- Applications"). Customer assumes the sole risk and
-// -- liability of any use of Xilinx products in Critical
-// -- Applications, subject only to applicable laws and
-// -- regulations governing limitations on product liability.
-// --
-// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// -- PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-//
-// Description: Write Data AXI3 Slave Converter
-// Forward and split transactions as required.
-//
-// Verilog-standard:  Verilog 2001
-//--------------------------------------------------------------------------
-//
-// Structure:
-//   w_axi3_conv
-//
-//--------------------------------------------------------------------------
-`timescale 1ps/1ps
-
-(* DowngradeIPIdentifiedWarnings="yes" *) 
-module axi_protocol_converter_v2_1_9_w_axi3_conv #
-  (
-   parameter C_FAMILY                            = "none",
-   parameter integer C_AXI_ID_WIDTH              = 1,
-   parameter integer C_AXI_ADDR_WIDTH            = 32,
-   parameter integer C_AXI_DATA_WIDTH            = 32,
-   parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
-   parameter integer C_AXI_WUSER_WIDTH           = 1,
-   parameter integer C_SUPPORT_SPLITTING              = 1,
-                       // Implement transaction splitting logic.
-                       // Disabled whan all connected masters are AXI3 and have same or narrower data width.
-   parameter integer C_SUPPORT_BURSTS                 = 1
-                       // Disabled when all connected masters are AxiLite,
-                       //   allowing logic to be simplified.
-   )
-  (
-   // System Signals
-   input wire ACLK,
-   input wire ARESET,
-
-   // Command Interface
-   input  wire                              cmd_valid,
-   input  wire [C_AXI_ID_WIDTH-1:0]         cmd_id,
-   input  wire [4-1:0]                      cmd_length,
-   output wire                              cmd_ready,
-   
-   // Slave Interface Write Data Ports
-   input  wire [C_AXI_DATA_WIDTH-1:0]   S_AXI_WDATA,
-   input  wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
-   input  wire                          S_AXI_WLAST,
-   input  wire [C_AXI_WUSER_WIDTH-1:0]  S_AXI_WUSER,
-   input  wire                          S_AXI_WVALID,
-   output wire                          S_AXI_WREADY,
-   
-   // Master Interface Write Data Ports
-   output wire [C_AXI_ID_WIDTH-1:0]     M_AXI_WID,
-   output wire [C_AXI_DATA_WIDTH-1:0]   M_AXI_WDATA,
-   output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
-   output wire                          M_AXI_WLAST,
-   output wire [C_AXI_WUSER_WIDTH-1:0]  M_AXI_WUSER,
-   output wire                          M_AXI_WVALID,
-   input  wire                          M_AXI_WREADY
-   );
-
-   
-  /////////////////////////////////////////////////////////////////////////////
-  // Variables for generating parameter controlled instances.
-  /////////////////////////////////////////////////////////////////////////////
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Local params
-  /////////////////////////////////////////////////////////////////////////////
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Functions
-  /////////////////////////////////////////////////////////////////////////////
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Internal signals
-  /////////////////////////////////////////////////////////////////////////////
-
-  // Burst length handling.
-  reg                             first_mi_word;
-  reg  [8-1:0]                    length_counter_1;
-  reg  [8-1:0]                    length_counter;
-  wire [8-1:0]                    next_length_counter;
-  wire                            last_beat;
-  wire                            last_word;
-  
-  // Throttling help signals.
-  wire                            cmd_ready_i;
-  wire                            pop_mi_data;
-  wire                            mi_stalling;
-  
-  // Internal SI side control signals.
-  wire                            S_AXI_WREADY_I;
-  
-  // Internal signals for MI-side.
-  wire [C_AXI_ID_WIDTH-1:0]       M_AXI_WID_I;
-  wire [C_AXI_DATA_WIDTH-1:0]     M_AXI_WDATA_I;
-  wire [C_AXI_DATA_WIDTH/8-1:0]   M_AXI_WSTRB_I;
-  wire                            M_AXI_WLAST_I;
-  wire [C_AXI_WUSER_WIDTH-1:0]    M_AXI_WUSER_I;
-  wire                            M_AXI_WVALID_I;
-  wire                            M_AXI_WREADY_I;
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Handle interface handshaking:
-  // 
-  // Forward data from SI-Side to MI-Side while a command is available. When
-  // the transaction has completed the command is popped from the Command FIFO.
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-                          
-  // Pop word from SI-side.
-  assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling;
-  assign S_AXI_WREADY   = S_AXI_WREADY_I;
-  
-  // Indicate when there is data available @ MI-side.
-  assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid;
-  
-  // Get MI-side data.
-  assign pop_mi_data    = M_AXI_WVALID_I & M_AXI_WREADY_I;
-  
-  // Signal that the command is done (so that it can be poped from command queue).
-  assign cmd_ready_i    = cmd_valid & pop_mi_data & last_word;
-  assign cmd_ready      = cmd_ready_i;
-  
-  // Detect when MI-side is stalling.
-  assign mi_stalling    = M_AXI_WVALID_I & ~M_AXI_WREADY_I;
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Keep track of data forwarding:
-  // 
-  // On the first cycle of the transaction is the length taken from the Command
-  // FIFO. The length is decreased until 0 is reached which indicates last data 
-  // word.
-  //
-  // If bursts are unsupported will all data words be the last word, each one
-  // from a separate transaction.
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // Select command length or counted length.
-  always @ *
-  begin
-    if ( first_mi_word )
-      length_counter = cmd_length;
-    else
-      length_counter = length_counter_1;
-  end
-  
-  // Calculate next length counter value.
-  assign next_length_counter = length_counter - 1'b1;
-  
-  // Keep track of burst length.
-  always @ (posedge ACLK) begin
-    if (ARESET) begin
-      first_mi_word    <= 1'b1;
-      length_counter_1 <= 4'b0;
-    end else begin
-      if ( pop_mi_data ) begin
-        if ( M_AXI_WLAST_I ) begin
-          first_mi_word    <= 1'b1;
-        end else begin
-          first_mi_word    <= 1'b0;
-        end
-      
-        length_counter_1 <= next_length_counter;
-      end
-    end
-  end
-  
-  // Detect last beat in a burst.
-  assign last_beat = ( length_counter == 4'b0 );
-  
-  // Determine if this last word that shall be extracted from this SI-side word.
-  assign last_word = ( last_beat ) |
-                     ( C_SUPPORT_BURSTS == 0 );
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // Select the SI-side word to write.
-  // 
-  // Most information can be reused directly (DATA, STRB, ID and USER).
-  // ID is taken from the Command FIFO.
-  //
-  // Split transactions needs to insert new LAST transactions. So to simplify
-  // is the LAST signal always generated.
-  //
-  /////////////////////////////////////////////////////////////////////////////
-  
-  // ID and USER is copied from the SI word to all MI word transactions.
-  assign M_AXI_WUSER_I  = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1'b0}};
-  
-  // Data has to be multiplexed.
-  assign M_AXI_WDATA_I  = S_AXI_WDATA;
-  assign M_AXI_WSTRB_I  = S_AXI_WSTRB;
-  
-  // ID is taken directly from the command queue.
-  assign M_AXI_WID_I    = cmd_id;
-  
-  // Handle last flag, i.e. set for MI-side last word.
-  assign M_AXI_WLAST_I  = last_word;
-  
-  
-  /////////////////////////////////////////////////////////////////////////////
-  // MI-side output handling
-  // 
-  /////////////////////////////////////////////////////////////////////////////
-// TODO: registered?
-  assign M_AXI_WID      = M_AXI_WID_I;
-  assign M_AXI_WDATA    = M_AXI_WDATA_I;
-  assign M_AXI_WSTRB    = M_AXI_WSTRB_I;
-  assign M_AXI_WLAST    = M_AXI_WLAST_I;
-  assign M_AXI_WUSER    = M_AXI_WUSER_I;
-  assign M_AXI_WVALID   = M_AXI_WVALID_I;
-  assign M_AXI_WREADY_I = M_AXI_WREADY;
-  
-  
-endmodule
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
index 38ba45b2f647cd9383fb238e967406143e0d2e27..92edbd3353b6c8057a5cbfe37b40818b3314a733 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
@@ -430,18 +430,6 @@
             <spirit:direction>inout</spirit:direction>
           </spirit:wire>
         </spirit:port>
-        <spirit:port>
-          <spirit:name>clk_aux_p_i</spirit:name>
-          <spirit:wire>
-            <spirit:direction>in</spirit:direction>
-          </spirit:wire>
-        </spirit:port>
-        <spirit:port>
-          <spirit:name>clk_aux_n_i</spirit:name>
-          <spirit:wire>
-            <spirit:direction>in</spirit:direction>
-          </spirit:wire>
-        </spirit:port>
         <spirit:port>
           <spirit:name>gtp_dedicated_clk_p_i</spirit:name>
           <spirit:wire>
@@ -732,7 +720,7 @@
       </spirit:componentInstance>
       <spirit:componentInstance>
         <spirit:instanceName>fasec_hwtest_0</spirit:instanceName>
-        <spirit:componentRef spirit:library="user" spirit:name="fasec_hwtest" spirit:vendor="user.org" spirit:version="3.0.1"/>
+        <spirit:componentRef spirit:library="user" spirit:name="fasec_hwtest" spirit:vendor="user.org" spirit:version="3.1.0"/>
         <spirit:configurableElementValues>
           <spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_fasec_hwtest_0_0</spirit:configurableElementValue>
           <spirit:configurableElementValue spirit:referenceId="g_FMC1">EDA-03287</spirit:configurableElementValue>
@@ -741,7 +729,7 @@
       </spirit:componentInstance>
       <spirit:componentInstance>
         <spirit:instanceName>wrc_1p_kintex7_0</spirit:instanceName>
-        <spirit:componentRef spirit:library="wrc" spirit:name="wrc_1p_kintex7" spirit:vendor="CERN" spirit:version="2.3.1"/>
+        <spirit:componentRef spirit:library="wrc" spirit:name="wrc_1p_kintex7" spirit:vendor="CERN" spirit:version="3.1.0"/>
         <spirit:configurableElementValues>
           <spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_wrc_1p_kintex7_0_0</spirit:configurableElementValue>
         </spirit:configurableElementValues>
@@ -855,6 +843,8 @@
         <spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="m_axi_s2mm_aclk"/>
         <spirit:internalPortReference spirit:componentRef="xadc_wiz_0" spirit:portRef="s_axis_aclk"/>
         <spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="s_axi_aclk"/>
+        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aclk"/>
+        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aclk"/>
         <spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="ACLK"/>
         <spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="ACLK"/>
         <spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M06_ACLK"/>
@@ -868,8 +858,6 @@
         <spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="S00_ACLK"/>
         <spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="M00_ACLK"/>
         <spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M07_ACLK"/>
-        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aclk"/>
-        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aclk"/>
         <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="ps_clk_i"/>
         <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aclk"/>
       </spirit:adHocConnection>
@@ -887,6 +875,8 @@
         <spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="axi_resetn"/>
         <spirit:internalPortReference spirit:componentRef="xadc_axis_fifo_adapter_0" spirit:portRef="AXIS_RESET_N"/>
         <spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="s_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aresetn"/>
         <spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="S00_ARESETN"/>
         <spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M06_ARESETN"/>
         <spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M05_ARESETN"/>
@@ -899,8 +889,6 @@
         <spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="ARESETN"/>
         <spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="S00_ARESETN"/>
         <spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M07_ARESETN"/>
-        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aresetn"/>
-        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aresetn"/>
         <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aresetn"/>
       </spirit:adHocConnection>
       <spirit:adHocConnection>
@@ -1098,16 +1086,6 @@
         <spirit:externalPortReference spirit:portRef="eeprom_sda"/>
         <spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="fpga_sda_b"/>
       </spirit:adHocConnection>
-      <spirit:adHocConnection>
-        <spirit:name>clk_aux_p_i_1</spirit:name>
-        <spirit:externalPortReference spirit:portRef="clk_aux_p_i"/>
-        <spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="clk_aux_p_i"/>
-      </spirit:adHocConnection>
-      <spirit:adHocConnection>
-        <spirit:name>clk_aux_n_i_1</spirit:name>
-        <spirit:externalPortReference spirit:portRef="clk_aux_n_i"/>
-        <spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="clk_aux_n_i"/>
-      </spirit:adHocConnection>
       <spirit:adHocConnection>
         <spirit:name>gtp_dedicated_clk_p_i_1</spirit:name>
         <spirit:externalPortReference spirit:portRef="gtp_dedicated_clk_p_i"/>
@@ -1123,11 +1101,6 @@
         <spirit:internalPortReference spirit:componentRef="xlconstant_7" spirit:portRef="dout"/>
         <spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="pps_i"/>
       </spirit:adHocConnection>
-      <spirit:adHocConnection>
-        <spirit:name>processing_system7_0_FCLK_CLK1</spirit:name>
-        <spirit:internalPortReference spirit:componentRef="processing_system7_0" spirit:portRef="FCLK_CLK1"/>
-        <spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="ext_clk_i"/>
-      </spirit:adHocConnection>
       <spirit:adHocConnection>
         <spirit:name>axi_uartlite_0_tx</spirit:name>
         <spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="tx"/>
@@ -1174,6 +1147,21 @@
         <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="dig_out6_n"/>
         <spirit:externalPortReference spirit:portRef="dig_out6_n"/>
       </spirit:adHocConnection>
+      <spirit:adHocConnection>
+        <spirit:name>Net8</spirit:name>
+        <spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="clk_ref_b"/>
+        <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="FMC1_GP0_b"/>
+      </spirit:adHocConnection>
+      <spirit:adHocConnection>
+        <spirit:name>Net9</spirit:name>
+        <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="FMC1_GP1_b"/>
+        <spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="clk_rx_rbclk_b"/>
+      </spirit:adHocConnection>
+      <spirit:adHocConnection>
+        <spirit:name>Net12</spirit:name>
+        <spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="clk_dmtd_b"/>
+        <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="FMC1_GP2_b"/>
+      </spirit:adHocConnection>
     </spirit:adHocConnections>
     <spirit:hierConnections>
       <spirit:hierConnection spirit:interfaceRef="DDR/processing_system7_0_DDR">
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
index 41a2f673867643f8da4c6e18eeff635014bc5b1b..13e84860a3c545c681a0bf4cfdd6453b836798f9 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
@@ -2,9 +2,9 @@
 <Root MajorVersion="0" MinorVersion="33">
   <CompositeFile CompositeFileTopName="system_design" CanBeSetAsTop="true" CanDisplayChildGraph="true">
     <Description>Composite Fileset</Description>
-    <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1490301269"/>
-    <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1490301269"/>
-    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1490301269"/>
+    <Generation Name="SYNTHESIS" State="STALE" Timestamp="1490611375"/>
+    <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1490611375"/>
+    <Generation Name="SIMULATION" State="STALE" Timestamp="1490611375"/>
     <FileCollection Name="SOURCES" Type="SOURCES">
       <File Name="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci" Type="IP">
         <Instance HierarchyPath="processing_system7_0"/>
@@ -23,6 +23,7 @@
         <UsedIn Val="SIMULATION"/>
       </File>
       <File Name="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci" Type="IP">
+        <Instance HierarchyPath="processing_system7_0_axi_periph"/>
         <Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
         <Library Name="xil_defaultlib"/>
         <UsedIn Val="SYNTHESIS"/>
@@ -78,6 +79,7 @@
         <UsedIn Val="SIMULATION"/>
       </File>
       <File Name="ip/system_design_axi_interconnect_0_0/system_design_axi_interconnect_0_0.xci" Type="IP">
+        <Instance HierarchyPath="axi_interconnect_0"/>
         <Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
         <Library Name="xil_defaultlib"/>
         <UsedIn Val="SYNTHESIS"/>
@@ -141,6 +143,7 @@
         <UsedIn Val="SIMULATION"/>
       </File>
       <File Name="ip/system_design_axi_interconnect_1_0/system_design_axi_interconnect_1_0.xci" Type="IP">
+        <Instance HierarchyPath="axi_interconnect_1"/>
         <Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
         <Library Name="xil_defaultlib"/>
         <UsedIn Val="SYNTHESIS"/>
@@ -153,6 +156,28 @@
         <UsedIn Val="SYNTHESIS"/>
         <UsedIn Val="SIMULATION"/>
       </File>
+      <File Name="system_design_ooc.xdc" Type="XDC">
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="OUT_OF_CONTEXT"/>
+      </File>
+      <File Name="hw_handoff/system_design.hwh" Type="HwHandoff">
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="HW_HANDOFF"/>
+      </File>
+      <File Name="hw_handoff/system_design_bd.tcl">
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="HW_HANDOFF"/>
+      </File>
+      <File Name="hdl/system_design.hwdef">
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="HW_HANDOFF"/>
+      </File>
       <File Name="ip/system_design_auto_pc_0/system_design_auto_pc_0.xci" Type="IP">
         <Instance HierarchyPath="axi_interconnect_0/s00_couplers/auto_pc"/>
         <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
@@ -177,28 +202,6 @@
         <UsedIn Val="IMPLEMENTATION"/>
         <UsedIn Val="SIMULATION"/>
       </File>
-      <File Name="system_design_ooc.xdc" Type="XDC">
-        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
-        <Library Name="xil_defaultlib"/>
-        <UsedIn Val="SYNTHESIS"/>
-        <UsedIn Val="IMPLEMENTATION"/>
-        <UsedIn Val="OUT_OF_CONTEXT"/>
-      </File>
-      <File Name="hw_handoff/system_design.hwh" Type="HwHandoff">
-        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
-        <Library Name="xil_defaultlib"/>
-        <UsedIn Val="HW_HANDOFF"/>
-      </File>
-      <File Name="hw_handoff/system_design_bd.tcl">
-        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
-        <Library Name="xil_defaultlib"/>
-        <UsedIn Val="HW_HANDOFF"/>
-      </File>
-      <File Name="hdl/system_design.hwdef">
-        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
-        <Library Name="xil_defaultlib"/>
-        <UsedIn Val="HW_HANDOFF"/>
-      </File>
     </FileCollection>
   </CompositeFile>
 </Root>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ui/bd_7f01d80e.ui b/FASEC_prototype.srcs/sources_1/bd/system_design/ui/bd_7f01d80e.ui
index 2d6d5616598eb720f86d1c7da1040b49189e2a78..b6fafed959a90d26535aaf4e468b89c65523c8c2 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ui/bd_7f01d80e.ui
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ui/bd_7f01d80e.ui
@@ -1,160 +1,158 @@
 {
    guistr: "# # String gsaved with Nlview 6.5.12  2016-01-29 bk=1.3547 VDI=39 GEI=35 GUI=JA:1.6
 #  -string -flagsOSRD
-preplace port FMC1_CLK0M2C_N_i -pg 1 -y 260 -defaultsOSRD
-preplace port led_line_en_pl_o -pg 1 -y 380 -defaultsOSRD
-preplace port DDR -pg 1 -y 720 -defaultsOSRD
-preplace port clk_25m_vcxo_i -pg 1 -y 1220 -defaultsOSRD
-preplace port dig_in3_n_i -pg 1 -y 1140 -defaultsOSRD
-preplace port dig_in1_i -pg 1 -y 1100 -defaultsOSRD
-preplace port led_line_pl_o -pg 1 -y 400 -defaultsOSRD
-preplace port Vp_Vn -pg 1 -y 890 -defaultsOSRD
-preplace port eeprom_sda -pg 1 -y 1350 -defaultsOSRD
-preplace port gtp_dedicated_clk_n_i -pg 1 -y 1300 -defaultsOSRD
-preplace port osc100_clk_i -pg 1 -y 1180 -defaultsOSRD
-preplace port fmcx_sda -pg 1 -y 580 -defaultsOSRD
-preplace port Vaux0 -pg 1 -y 910 -defaultsOSRD
-preplace port FMC1_CLK0M2C_P_i -pg 1 -y 240 -defaultsOSRD
-preplace port Vaux1 -pg 1 -y 930 -defaultsOSRD
-preplace port thermo_id -pg 1 -y 1370 -defaultsOSRD
-preplace port dac_cs2_n_o -pg 1 -y 1310 -defaultsOSRD
-preplace port FMC2_CLK0M2C_N_i -pg 1 -y 200 -defaultsOSRD
-preplace port Vaux2 -pg 1 -y 950 -defaultsOSRD
-preplace port FMC1_CLK0C2M_P_o -pg 1 -y 240 -defaultsOSRD
-preplace port FMC2_CLK0M2C_P_i -pg 1 -y 180 -defaultsOSRD
-preplace port FMC2_PRSNTM2C_n_i -pg 1 -y 160 -defaultsOSRD
-preplace port Vaux10 -pg 1 -y 1010 -defaultsOSRD
-preplace port clk_aux_p_i -pg 1 -y 1240 -defaultsOSRD
-preplace port dac_din_o -pg 1 -y 1270 -defaultsOSRD
-preplace port FMC1_PRSNTM2C_n_i -pg 1 -y 220 -defaultsOSRD
-preplace port gtp_wr -pg 1 -y 1150 -defaultsOSRD
-preplace port gtp0_rate_select_b -pg 1 -y 1390 -defaultsOSRD
-preplace port fmcx_scl -pg 1 -y 560 -defaultsOSRD
-preplace port FIXED_IO -pg 1 -y 740 -defaultsOSRD
-preplace port eeprom_scl -pg 1 -y 1330 -defaultsOSRD
-preplace port dac_cs1_n_o -pg 1 -y 1290 -defaultsOSRD
-preplace port dig_in4_n_i -pg 1 -y 1160 -defaultsOSRD
-preplace port dig_in2_i -pg 1 -y 1120 -defaultsOSRD
-preplace port watchdog_pl_o -pg 1 -y 420 -defaultsOSRD
-preplace port gtp_dedicated_clk_p_i -pg 1 -y 1280 -defaultsOSRD
-preplace port FMC1_CLK0C2M_N_o -pg 1 -y 260 -defaultsOSRD
-preplace port pb_gp_i -pg 1 -y 1200 -defaultsOSRD
-preplace port dig_out5_n -pg 1 -y 460 -defaultsOSRD
-preplace port Vaux8 -pg 1 -y 970 -defaultsOSRD
-preplace port clk_aux_n_i -pg 1 -y 1260 -defaultsOSRD
-preplace port dac_sclk_o -pg 1 -y 1250 -defaultsOSRD
-preplace port FMC2_CLK0C2M_N_o -pg 1 -y 140 -defaultsOSRD
-preplace port FMC2_CLK0C2M_P_o -pg 1 -y 120 -defaultsOSRD
-preplace port Vaux9 -pg 1 -y 990 -defaultsOSRD
-preplace portBus FMC1_LA_P_b -pg 1 -y 80 -defaultsOSRD
-preplace portBus FMC2_LA_N_b -pg 1 -y 60 -defaultsOSRD
-preplace portBus dig_outs_i -pg 1 -y 440 -defaultsOSRD
-preplace portBus dig_out6_n -pg 1 -y 480 -defaultsOSRD
-preplace portBus FMC2_LA_P_b -pg 1 -y 40 -defaultsOSRD
-preplace portBus led_col_pl_o -pg 1 -y 360 -defaultsOSRD
-preplace portBus FMC1_LA_N_b -pg 1 -y 100 -defaultsOSRD
-preplace inst fasec_hwtest_0 -pg 1 -lvl 9 -y 260 -defaultsOSRD
-preplace inst axi_dma_0 -pg 1 -lvl 5 -y 800 -defaultsOSRD
-preplace inst xadc_axis_fifo_adapter_0 -pg 1 -lvl 4 -y 870 -defaultsOSRD
-preplace inst rst_processing_system7_0_100M -pg 1 -lvl 1 -y 540 -defaultsOSRD
-preplace inst wrc_1p_kintex7_0 -pg 1 -lvl 9 -y 1290 -defaultsOSRD
-preplace inst xadc_wiz_0 -pg 1 -lvl 3 -y 970 -defaultsOSRD
-preplace inst xlconcat_0 -pg 1 -lvl 6 -y 660 -defaultsOSRD
-preplace inst axi_wb_i2c_master_0 -pg 1 -lvl 3 -y 330 -defaultsOSRD
-preplace inst axi_wb_i2c_master_2 -pg 1 -lvl 9 -y 580 -defaultsOSRD
-preplace inst xlconstant_6 -pg 1 -lvl 8 -y 380 -defaultsOSRD
-preplace inst xlconstant_7 -pg 1 -lvl 8 -y 1350 -defaultsOSRD
-preplace inst axi_uartlite_0 -pg 1 -lvl 3 -y 680 -defaultsOSRD
-preplace inst axi_interconnect_0 -pg 1 -lvl 6 -y 880 -defaultsOSRD
-preplace inst axi_interconnect_1 -pg 1 -lvl 8 -y 1000 -defaultsOSRD
-preplace inst rst_wrc_1p_kintex7_0_62M -pg 1 -lvl 7 -y 1040 -defaultsOSRD
-preplace inst processing_system7_0_axi_periph -pg 1 -lvl 2 -y 630 -defaultsOSRD
-preplace inst processing_system7_0 -pg 1 -lvl 7 -y 810 -defaultsOSRD
-preplace netloc osc100_clk_i_1 1 0 9 NJ 130 NJ 130 NJ 130 NJ 130 NJ 130 NJ 130 NJ 130 NJ 130 NJ
+preplace port FMC1_CLK0M2C_N_i -pg 1 -y 990 -defaultsOSRD
+preplace port led_line_en_pl_o -pg 1 -y 1110 -defaultsOSRD
+preplace port DDR -pg 1 -y 310 -defaultsOSRD
+preplace port clk_25m_vcxo_i -pg 1 -y 1510 -defaultsOSRD
+preplace port dig_in3_n_i -pg 1 -y 1070 -defaultsOSRD
+preplace port dig_in1_i -pg 1 -y 1030 -defaultsOSRD
+preplace port led_line_pl_o -pg 1 -y 1130 -defaultsOSRD
+preplace port Vp_Vn -pg 1 -y 550 -defaultsOSRD
+preplace port eeprom_sda -pg 1 -y 1650 -defaultsOSRD
+preplace port gtp_dedicated_clk_n_i -pg 1 -y 1550 -defaultsOSRD
+preplace port osc100_clk_i -pg 1 -y 870 -defaultsOSRD
+preplace port fmcx_sda -pg 1 -y 400 -defaultsOSRD
+preplace port Vaux0 -pg 1 -y 370 -defaultsOSRD
+preplace port FMC1_CLK0M2C_P_i -pg 1 -y 970 -defaultsOSRD
+preplace port Vaux1 -pg 1 -y 390 -defaultsOSRD
+preplace port thermo_id -pg 1 -y 1670 -defaultsOSRD
+preplace port dac_cs2_n_o -pg 1 -y 1610 -defaultsOSRD
+preplace port FMC2_CLK0M2C_N_i -pg 1 -y 930 -defaultsOSRD
+preplace port Vaux2 -pg 1 -y 570 -defaultsOSRD
+preplace port FMC1_CLK0C2M_P_o -pg 1 -y 970 -defaultsOSRD
+preplace port FMC2_CLK0M2C_P_i -pg 1 -y 910 -defaultsOSRD
+preplace port FMC2_PRSNTM2C_n_i -pg 1 -y 890 -defaultsOSRD
+preplace port Vaux10 -pg 1 -y 630 -defaultsOSRD
+preplace port dac_din_o -pg 1 -y 1570 -defaultsOSRD
+preplace port FMC1_PRSNTM2C_n_i -pg 1 -y 950 -defaultsOSRD
+preplace port gtp_wr -pg 1 -y 1390 -defaultsOSRD
+preplace port gtp0_rate_select_b -pg 1 -y 1690 -defaultsOSRD
+preplace port fmcx_scl -pg 1 -y 380 -defaultsOSRD
+preplace port FIXED_IO -pg 1 -y 330 -defaultsOSRD
+preplace port eeprom_scl -pg 1 -y 1630 -defaultsOSRD
+preplace port dac_cs1_n_o -pg 1 -y 1590 -defaultsOSRD
+preplace port dig_in4_n_i -pg 1 -y 1090 -defaultsOSRD
+preplace port dig_in2_i -pg 1 -y 1050 -defaultsOSRD
+preplace port watchdog_pl_o -pg 1 -y 1150 -defaultsOSRD
+preplace port gtp_dedicated_clk_p_i -pg 1 -y 1530 -defaultsOSRD
+preplace port FMC1_CLK0C2M_N_o -pg 1 -y 990 -defaultsOSRD
+preplace port pb_gp_i -pg 1 -y 1010 -defaultsOSRD
+preplace port dig_out5_n -pg 1 -y 1190 -defaultsOSRD
+preplace port Vaux8 -pg 1 -y 590 -defaultsOSRD
+preplace port dac_sclk_o -pg 1 -y 1550 -defaultsOSRD
+preplace port FMC2_CLK0C2M_N_o -pg 1 -y 870 -defaultsOSRD
+preplace port FMC2_CLK0C2M_P_o -pg 1 -y 850 -defaultsOSRD
+preplace port Vaux9 -pg 1 -y 610 -defaultsOSRD
+preplace portBus FMC1_LA_P_b -pg 1 -y 810 -defaultsOSRD
+preplace portBus FMC2_LA_N_b -pg 1 -y 790 -defaultsOSRD
+preplace portBus dig_outs_i -pg 1 -y 1170 -defaultsOSRD
+preplace portBus dig_out6_n -pg 1 -y 1210 -defaultsOSRD
+preplace portBus FMC2_LA_P_b -pg 1 -y 770 -defaultsOSRD
+preplace portBus led_col_pl_o -pg 1 -y 1090 -defaultsOSRD
+preplace portBus FMC1_LA_N_b -pg 1 -y 830 -defaultsOSRD
+preplace inst fasec_hwtest_0 -pg 1 -lvl 9 -y 990 -defaultsOSRD
+preplace inst axi_dma_0 -pg 1 -lvl 5 -y 370 -defaultsOSRD
+preplace inst xadc_axis_fifo_adapter_0 -pg 1 -lvl 4 -y 440 -defaultsOSRD
+preplace inst rst_processing_system7_0_100M -pg 1 -lvl 1 -y 470 -defaultsOSRD
+preplace inst wrc_1p_kintex7_0 -pg 1 -lvl 9 -y 1560 -defaultsOSRD
+preplace inst xadc_wiz_0 -pg 1 -lvl 3 -y 590 -defaultsOSRD
+preplace inst xlconcat_0 -pg 1 -lvl 6 -y 450 -defaultsOSRD
+preplace inst axi_wb_i2c_master_0 -pg 1 -lvl 3 -y 160 -defaultsOSRD
+preplace inst axi_wb_i2c_master_2 -pg 1 -lvl 9 -y 400 -defaultsOSRD
+preplace inst xlconstant_6 -pg 1 -lvl 8 -y 1140 -defaultsOSRD
+preplace inst xlconstant_7 -pg 1 -lvl 8 -y 1600 -defaultsOSRD
+preplace inst axi_uartlite_0 -pg 1 -lvl 3 -y 830 -defaultsOSRD
+preplace inst axi_interconnect_0 -pg 1 -lvl 6 -y 110 -defaultsOSRD
+preplace inst axi_interconnect_1 -pg 1 -lvl 8 -y 790 -defaultsOSRD
+preplace inst rst_wrc_1p_kintex7_0_62M -pg 1 -lvl 7 -y 750 -defaultsOSRD
+preplace inst processing_system7_0_axi_periph -pg 1 -lvl 2 -y 280 -defaultsOSRD
+preplace inst processing_system7_0 -pg 1 -lvl 7 -y 400 -defaultsOSRD
+preplace netloc osc100_clk_i_1 1 0 9 NJ 750 NJ 750 NJ 750 NJ 640 NJ 640 NJ 640 NJ 640 NJ 640 NJ
 preplace netloc fasec_hwtest_0_led_col_pl_o 1 9 1 NJ
-preplace netloc dig_in4_n_i_1 1 0 9 NJ 160 NJ 160 NJ 160 NJ 160 NJ 160 NJ 160 NJ 160 NJ 160 NJ
-preplace netloc processing_system7_0_FIXED_IO 1 7 3 NJ 740 NJ 740 NJ
+preplace netloc dig_in4_n_i_1 1 0 9 NJ 1090 NJ 1090 NJ 1090 NJ 1090 NJ 1090 NJ 1090 NJ 1090 NJ 1090 NJ
+preplace netloc processing_system7_0_FIXED_IO 1 7 3 NJ 330 NJ 330 NJ
 preplace netloc fasec_hwtest_0_dig_outs_i 1 9 1 NJ
-preplace netloc gtp_dedicated_clk_n_i_1 1 0 9 NJ 1300 NJ 1300 NJ 1300 NJ 1300 NJ 1300 NJ 1300 NJ 1300 NJ 1300 NJ
+preplace netloc gtp_dedicated_clk_n_i_1 1 0 9 NJ 1550 NJ 1550 NJ 1550 NJ 1550 NJ 1550 NJ 1550 NJ 1550 NJ 1550 NJ
 preplace netloc wrc_1p_kintex7_0_dac_din_o 1 9 1 NJ
-preplace netloc gtp_dedicated_clk_p_i_1 1 0 9 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ 1280 NJ
-preplace netloc axi_uartlite_0_tx 1 3 7 N 690 NJ 690 NJ 750 NJ 660 NJ 660 NJ 660 3170
-preplace netloc dig_in3_n_i_1 1 0 9 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 NJ
-preplace netloc FMC1_PRSNTM2C_n_i_1 1 0 9 NJ 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ 200 NJ
-preplace netloc dig_in1_i_1 1 0 9 NJ 250 NJ 250 NJ 250 NJ 250 NJ 250 NJ 250 NJ 250 NJ 250 NJ
-preplace netloc xlconcat_0_dout 1 6 1 1970
+preplace netloc gtp_dedicated_clk_p_i_1 1 0 9 NJ 1530 NJ 1530 NJ 1530 NJ 1530 NJ 1530 NJ 1530 NJ 1530 NJ 1530 NJ
+preplace netloc axi_uartlite_0_tx 1 3 7 1040 630 NJ 630 NJ 630 NJ 630 NJ 630 NJ 630 3240
+preplace netloc dig_in3_n_i_1 1 0 9 NJ 1070 NJ 1070 NJ 1070 NJ 1070 NJ 1070 NJ 1070 NJ 1070 NJ 1070 NJ
+preplace netloc FMC1_PRSNTM2C_n_i_1 1 0 9 NJ 950 NJ 950 NJ 950 NJ 950 NJ 950 NJ 950 NJ 950 NJ 950 NJ
+preplace netloc dig_in1_i_1 1 0 9 NJ 1030 NJ 1030 NJ 1030 NJ 1030 NJ 1030 NJ 1030 NJ 1030 NJ 1030 NJ
+preplace netloc xlconcat_0_dout 1 6 1 2030
 preplace netloc fasec_hwtest_0_FMC1_CLK0C2M_P_o 1 9 1 NJ
-preplace netloc pb_gp_i_1 1 0 9 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 2780
+preplace netloc pb_gp_i_1 1 0 9 NJ 1010 NJ 1010 NJ 1010 NJ 1010 NJ 1010 NJ 1010 NJ 1010 NJ 1010 2820
 preplace netloc wrc_1p_kintex7_0_dac_sclk_o 1 9 1 NJ
 preplace netloc fasec_hwtest_0_led_line_pl_o 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph_M06_AXI 1 2 3 700 760 NJ 760 NJ
-preplace netloc axi_wb_i2c_master_2_axi_int_o 1 5 5 1670 550 NJ 550 NJ 550 NJ 650 3170
-preplace netloc processing_system7_0_DDR 1 7 3 NJ 720 NJ 720 NJ
-preplace netloc FMC1_CLK0M2C_N_i_1 1 0 9 NJ 260 NJ 260 NJ 260 NJ 260 NJ 260 NJ 260 NJ 260 NJ 260 NJ
+preplace netloc processing_system7_0_axi_periph_M06_AXI 1 2 3 NJ 320 NJ 320 1280
+preplace netloc axi_wb_i2c_master_2_axi_int_o 1 5 5 1700 250 NJ 240 NJ 240 NJ 240 3250
+preplace netloc processing_system7_0_DDR 1 7 3 NJ 310 NJ 310 NJ
+preplace netloc FMC1_CLK0M2C_N_i_1 1 0 9 NJ 990 NJ 990 NJ 990 NJ 990 NJ 990 NJ 990 NJ 990 NJ 990 NJ
 preplace netloc wrc_1p_kintex7_0_dac_cs2_n_o 1 9 1 NJ
-preplace netloc axi_interconnect_1_M00_AXI 1 8 1 2790
-preplace netloc FMC2_CLK0M2C_N_i_1 1 0 9 NJ 210 NJ 210 NJ 210 NJ 210 NJ 210 NJ 210 NJ 210 NJ 210 NJ
-preplace netloc processing_system7_0_axi_periph_M05_AXI 1 2 2 720 600 NJ
+preplace netloc axi_interconnect_1_M00_AXI 1 8 1 2800
+preplace netloc FMC2_CLK0M2C_N_i_1 1 0 9 NJ 930 NJ 930 NJ 930 NJ 930 NJ 930 NJ 930 NJ 930 NJ 930 NJ
+preplace netloc processing_system7_0_axi_periph_M05_AXI 1 2 2 NJ 310 1030
 preplace netloc fasec_hwtest_0_dig_out6_n 1 9 1 NJ
-preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 8 60 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 1980 1130 2380
-preplace netloc FMC2_PRSNTM2C_n_i_1 1 0 9 NJ 150 NJ 150 NJ 150 NJ 150 NJ 150 NJ 150 NJ 150 NJ 150 NJ
-preplace netloc rst_wrc_1p_kintex7_0_62M_interconnect_aresetn 1 7 1 2400
-preplace netloc xadc_wiz_0_M_AXIS 1 3 1 1050
-preplace netloc clk_aux_n_i_1 1 0 9 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ 1260 NJ
-preplace netloc processing_system7_0_axi_periph_M02_AXI 1 2 7 710 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ
+preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 8 20 10 NJ 10 NJ 10 NJ 10 NJ 10 NJ 290 2010 540 2430
+preplace netloc FMC2_PRSNTM2C_n_i_1 1 0 9 NJ 890 NJ 890 NJ 910 NJ 910 NJ 910 NJ 910 NJ 910 NJ 670 NJ
+preplace netloc rst_wrc_1p_kintex7_0_62M_interconnect_aresetn 1 7 1 N
+preplace netloc xadc_wiz_0_M_AXIS 1 3 1 1030
+preplace netloc processing_system7_0_axi_periph_M02_AXI 1 2 7 NJ 250 NJ 260 NJ 260 NJ 270 NJ 210 NJ 210 2860
 preplace netloc xadc_axis_fifo_adapter_0_M_AXIS 1 4 1 1280
-preplace netloc processing_system7_0_axi_periph_M07_AXI 1 2 1 740
+preplace netloc processing_system7_0_axi_periph_M07_AXI 1 2 1 700
 preplace netloc fasec_hwtest_0_FMC2_CLK0C2M_N_o 1 9 1 NJ
-preplace netloc rst_wrc_1p_kintex7_0_62M_peripheral_aresetn 1 7 2 2410 1130 NJ
-preplace netloc clk_25m_vcxo_i_1 1 0 9 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ
-preplace netloc axi_dma_0_M_AXI_S2MM 1 5 1 1630
+preplace netloc rst_wrc_1p_kintex7_0_62M_peripheral_aresetn 1 7 2 2470 910 NJ
+preplace netloc clk_25m_vcxo_i_1 1 0 9 NJ 1510 NJ 1510 NJ 1510 NJ 1510 NJ 1510 NJ 1510 NJ 1510 NJ 1510 NJ
+preplace netloc axi_dma_0_M_AXI_S2MM 1 5 1 1640
 preplace netloc fasec_hwtest_0_FMC2_CLK0C2M_P_o 1 9 1 NJ
-preplace netloc Vaux2_1 1 0 3 NJ 950 NJ 950 NJ
-preplace netloc Vp_Vn_1 1 0 3 NJ 890 NJ 890 NJ
+preplace netloc Vaux2_1 1 0 3 NJ 570 NJ 570 NJ
+preplace netloc Vp_Vn_1 1 0 3 NJ 560 NJ 560 NJ
 preplace netloc fasec_hwtest_0_FMC1_CLK0C2M_N_o 1 9 1 NJ
 preplace netloc fasec_hwtest_0_watchdog_pl_o 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph_M01_AXI 1 2 1 720
+preplace netloc processing_system7_0_axi_periph_M01_AXI 1 2 1 700
 preplace netloc fasec_hwtest_0_dig_out5_n 1 9 1 NJ
-preplace netloc FMC1_CLK0M2C_P_i_1 1 0 9 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ
-preplace netloc Vaux0_1 1 0 3 NJ 910 NJ 910 NJ
+preplace netloc FMC1_CLK0M2C_P_i_1 1 0 9 NJ 970 NJ 970 NJ 970 NJ 970 NJ 970 NJ 970 NJ 970 NJ 970 NJ
+preplace netloc Vaux0_1 1 0 3 NJ 370 NJ 540 NJ
 preplace netloc Net 1 9 1 NJ
 preplace netloc Net10 1 9 1 NJ
-preplace netloc wrc_1p_kintex7_0_uart_txd_o 1 3 7 N 670 NJ 670 NJ 760 NJ 670 NJ 670 NJ 670 3160
+preplace netloc wrc_1p_kintex7_0_uart_txd_o 1 3 7 1050 650 NJ 650 NJ 650 NJ 650 NJ 650 NJ 650 3230
 preplace netloc Net1 1 9 1 NJ
-preplace netloc processing_system7_0_FCLK_CLK0 1 0 9 60 450 380 360 730 820 1020 980 1290 900 1620 1000 1990 950 2390 580 2740
+preplace netloc processing_system7_0_FCLK_CLK0 1 0 9 30 350 360 600 720 290 1050 290 1290 280 1660 280 2040 250 2440 400 2850
 preplace netloc Net11 1 9 1 NJ
-preplace netloc processing_system7_0_FCLK_CLK1 1 7 2 NJ 880 2760
 preplace netloc Net2 1 9 1 NJ
+preplace netloc Net12 1 9 1 3200
 preplace netloc Net3 1 9 1 NJ
-preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 1 400
-preplace netloc processing_system7_0_axi_periph_M00_AXI 1 2 7 N 560 NJ 560 NJ 560 NJ 560 NJ 560 NJ 560 NJ
+preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 1 370
+preplace netloc processing_system7_0_axi_periph_M00_AXI 1 2 7 NJ 90 NJ 90 NJ 90 NJ 260 NJ 260 NJ 260 2850
 preplace netloc fasec_hwtest_0_led_line_en_pl_o 1 9 1 NJ
-preplace netloc wrc_1p_kintex7_0_s00_axi_aclk_o 1 6 4 2000 1140 2390 1120 NJ 1040 3150
+preplace netloc wrc_1p_kintex7_0_s00_axi_aclk_o 1 6 4 2050 660 2480 660 NJ 660 3250
 preplace netloc Net4 1 9 1 NJ
-preplace netloc Vaux8_1 1 0 3 NJ 970 NJ 970 NJ
+preplace netloc Vaux8_1 1 0 3 NJ 590 NJ 590 NJ
 preplace netloc Net5 1 9 1 NJ
-preplace netloc xadc_wiz_0_ip2intc_irpt 1 3 3 NJ 640 NJ 640 N
+preplace netloc xadc_wiz_0_ip2intc_irpt 1 3 3 NJ 250 NJ 250 1620
 preplace netloc Net6 1 9 1 NJ
 preplace netloc xlconstant_6_dout 1 8 1 NJ
 preplace netloc Net7 1 9 1 NJ
-preplace netloc dig_in2_i_1 1 0 9 NJ 220 NJ 220 NJ 220 NJ 220 NJ 220 NJ 220 NJ 220 NJ 220 NJ
-preplace netloc clk_aux_p_i_1 1 0 9 NJ 1240 NJ 1240 NJ 1240 NJ 1240 NJ 1240 NJ 1240 NJ 1240 NJ 1240 NJ
-preplace netloc axi_uartlite_0_interrupt 1 3 3 1030 700 NJ 700 NJ
-preplace netloc Vaux10_1 1 0 3 NJ 1010 NJ 1010 NJ
-preplace netloc processing_system7_0_M_AXI_GP0 1 1 7 400 180 NJ 180 NJ 180 NJ 180 NJ 180 NJ 180 2380
-preplace netloc Vaux1_1 1 0 3 NJ 930 NJ 930 NJ
-preplace netloc Vaux9_1 1 0 3 NJ 990 NJ 990 NJ
-preplace netloc axi_dma_0_s2mm_introut 1 5 1 1620
+preplace netloc Net8 1 9 1 3220
+preplace netloc dig_in2_i_1 1 0 9 NJ 1050 NJ 1050 NJ 1050 NJ 1050 NJ 1050 NJ 1050 NJ 1050 NJ 1050 NJ
+preplace netloc Net9 1 9 1 3210
+preplace netloc axi_uartlite_0_interrupt 1 3 3 1020 550 NJ 490 NJ
+preplace netloc Vaux10_1 1 0 3 NJ 630 NJ 630 NJ
+preplace netloc processing_system7_0_M_AXI_GP0 1 1 7 390 20 NJ 230 NJ 230 NJ 230 NJ 230 NJ 230 2430
+preplace netloc Vaux1_1 1 0 3 NJ 380 NJ 550 NJ
+preplace netloc Vaux9_1 1 0 3 NJ 610 NJ 610 NJ
+preplace netloc axi_dma_0_s2mm_introut 1 5 1 1610
 preplace netloc processing_system7_0_axi_periph_M04_AXI 1 2 1 710
-preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 1 8 390 370 750 800 1030 990 1300 890 1650 570 NJ 570 NJ 570 2790
-preplace netloc FMC2_CLK0M2C_P_i_1 1 0 9 NJ 170 NJ 170 NJ 170 NJ 170 NJ 170 NJ 170 NJ 170 NJ 170 NJ
+preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 1 8 390 580 730 330 1040 330 1270 240 1680 240 NJ 200 NJ 200 2840
+preplace netloc FMC2_CLK0M2C_P_i_1 1 0 9 NJ 740 NJ 740 NJ 740 NJ 610 NJ 610 NJ 610 NJ 610 NJ 610 NJ
 preplace netloc wrc_1p_kintex7_0_dac_cs1_n_o 1 9 1 NJ
 preplace netloc wrc_1p_kintex7_0_gtp_wr 1 9 1 NJ
-preplace netloc S00_AXI_1 1 7 1 2410
-preplace netloc axi_interconnect_0_M00_AXI 1 6 1 1980
+preplace netloc S00_AXI_1 1 7 1 2450
+preplace netloc axi_interconnect_0_M00_AXI 1 6 1 2030
 preplace netloc xlconstant_7_dout 1 8 1 NJ
-preplace netloc axi_wb_i2c_master_0_axi_int_o 1 3 3 N 350 NJ 350 NJ
-levelinfo -pg 1 -30 220 550 890 1170 1460 1820 2190 2560 2980 3190 -top 0 -bot 1550
+preplace netloc axi_wb_i2c_master_0_axi_int_o 1 3 3 NJ 180 NJ 180 1630
+levelinfo -pg 1 -10 190 540 880 1160 1450 1850 2240 2630 3030 3270 -top 0 -bot 1840
 ",
 }
 {
diff --git a/FASEC_prototype.xpr b/FASEC_prototype.xpr
index 247fc3725bdfb807cb6d943bc2d5748406db81b8..cf6a168173652e2d73c069445777eae1f72ce80a 100644
--- a/FASEC_prototype.xpr
+++ b/FASEC_prototype.xpr
@@ -20,10 +20,8 @@
     <Option Name="BoardPart" Val=""/>
     <Option Name="ActiveSimSet" Val="sim_1"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
-    <Option Name="IPRepoPath" Val="$PPRDIR/../cores/xilinx_ip_adapter_v1_00"/>
     <Option Name="IPRepoPath" Val="$PPRDIR/ip_cores/wrc-1p-fasec"/>
-    <Option Name="IPRepoPath" Val="$PPRDIR/../cores/FASEC_hwtest"/>
-    <Option Name="IPRepoPath" Val="$PPRDIR/../cores/axi_wb_i2c_master"/>
+    <Option Name="IPRepoPath" Val="$PPRDIR/ip_cores/cores"/>
     <Option Name="EnableCoreContainer" Val="FALSE"/>
     <Option Name="XPMLibraries" Val="XPM_CDC"/>
     <Option Name="XPMLibraries" Val="XPM_MEMORY"/>
@@ -38,13 +36,13 @@
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="69"/>
-    <Option Name="WTModelSimExportSim" Val="69"/>
-    <Option Name="WTQuestaExportSim" Val="69"/>
-    <Option Name="WTIesExportSim" Val="69"/>
-    <Option Name="WTVcsExportSim" Val="69"/>
-    <Option Name="WTRivieraExportSim" Val="69"/>
-    <Option Name="WTActivehdlExportSim" Val="69"/>
+    <Option Name="WTXSimExportSim" Val="71"/>
+    <Option Name="WTModelSimExportSim" Val="71"/>
+    <Option Name="WTQuestaExportSim" Val="71"/>
+    <Option Name="WTIesExportSim" Val="71"/>
+    <Option Name="WTVcsExportSim" Val="71"/>
+    <Option Name="WTRivieraExportSim" Val="71"/>
+    <Option Name="WTActivehdlExportSim" Val="71"/>
   </Configuration>
   <FileSets Version="1" Minor="31">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
@@ -55,6 +53,39 @@
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="system_design_fasec_hwtest_0_0.xml"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xbar_0/system_design_xbar_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_0_0/system_design_axi_interconnect_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_6_0/system_design_xlconstant_6_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_wrc_1p_kintex7_0_62M_0/system_design_rst_wrc_1p_kintex7_0_62M_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_1_0/system_design_axi_interconnect_1_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.vhd"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/main_pkg.vhd"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="synth/system_design_fasec_hwtest_0_0.vhd"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="sim/system_design_fasec_hwtest_0_0.vhd"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="FASEC_hwtest.srcs/constrs_1/new/hw_ip_constraints.xdc"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/pulseMeasure.vhd"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_1_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd"/>
       </File>
       <File Path="$PSRCDIR/sources_1/bd/system_design/hdl/system_design_wrapper.vhd">
         <FileInfo>
diff --git a/ip_cores/wrc-1p-fasec b/ip_cores/wrc-1p-fasec
index cf6497ead6a26db7fc8d8f76f14efebf2870b9d1..6219cce893ca161bf8a5ca1b200405e2c1beeaaf 160000
--- a/ip_cores/wrc-1p-fasec
+++ b/ip_cores/wrc-1p-fasec
@@ -1 +1 @@
-Subproject commit cf6497ead6a26db7fc8d8f76f14efebf2870b9d1
+Subproject commit 6219cce893ca161bf8a5ca1b200405e2c1beeaaf
diff --git a/ip_upgrade.log b/ip_upgrade.log
index e939e668cb912a913b544cc278aef5aabd3acd2d..a826c027a3cce0f93fcea446ada4179073697fd8 100644
--- a/ip_upgrade.log
+++ b/ip_upgrade.log
@@ -1,3 +1,106 @@
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
+| Date         : Mon Mar 27 12:41:27 2017
+| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
+| Command      : upgrade_ip
+| Device       : xc7z030ffg676-2
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'
+
+1. Summary
+----------
+
+CAUTION (success, with warnings) in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:3.0 (Rev. 14) to CERN:wrc:wrc_1p_kintex7:3.1.0 (Rev. 15)
+
+After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.
+
+2. Connection Warnings
+----------------------
+
+Detected external port differences while upgrading 'system_design_wrc_1p_kintex7_0_0'. These changes may impact your design.
+
+
+-Upgrade has removed port 'clk_dmtd_o'
+
+-Upgrade has removed port 'clk_ref_o'
+
+-Upgrade has removed port 'clk_rx_rbclk_o'
+
+-Upgrade has added port 'clk_dmtd_b'
+
+-Upgrade has added port 'clk_ref_b'
+
+-Upgrade has added port 'clk_rx_rbclk_b'
+
+
+
+
+
+
+
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
+| Date         : Mon Mar 27 12:04:12 2017
+| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
+| Command      : upgrade_ip
+| Device       : xc7z030ffg676-2
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_design_wrc_1p_kintex7_0_0'
+
+1. Summary
+----------
+
+CAUTION (success, with warnings) in the upgrade of system_design_wrc_1p_kintex7_0_0 from CERN:wrc:wrc_1p_kintex7:2.3.1 (Rev. 13) to CERN:wrc:wrc_1p_kintex7:3.0 (Rev. 14)
+
+After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.
+
+2. Connection Warnings
+----------------------
+
+Detected external port differences while upgrading 'system_design_wrc_1p_kintex7_0_0'. These changes may impact your design.
+
+
+-Upgrade has removed port 'clk_aux_n_i'
+
+-Upgrade has removed port 'clk_aux_p_i'
+
+-Upgrade has added port 'clk_dmtd_o'
+
+-Upgrade has added port 'clk_ref_o'
+
+-Upgrade has added port 'clk_rx_rbclk_o'
+
+
+
+
+
+
+
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
+| Date         : Mon Mar 27 12:04:12 2017
+| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
+| Command      : upgrade_ip
+| Device       : xc7z030ffg676-2
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_design_fasec_hwtest_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.0.1 (Rev. 25) to user.org:user:fasec_hwtest:3.1.0 (Rev. 26)
+
+
+
+
+
+
 Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
 ------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016