From 5a452d1aac61aad26c1f184a37f5294789eba9ae Mon Sep 17 00:00:00 2001
From: Pieter Van Trappen <pieter.van.trappen@cern.ch>
Date: Thu, 12 Oct 2017 10:08:31 +0200
Subject: [PATCH] fasec_hwtest updated cause of unwanted wrc signals to outputs
---
.../coregen/aximm_temp/aximm_temp.xci | 61 -
.../coregen/aximm_temp/aximm_temp.xml | 386 -
.../bd/system_design/hdl/system_design.vhd | 144 +-
...design_axi_wb_i2c_master_0_1_sim_netlist.v | 4084 +
...ign_axi_wb_i2c_master_0_1_sim_netlist.vhdl | 4862 +
...design_axi_wb_i2c_master_2_0_sim_netlist.v | 4084 +
...ign_axi_wb_i2c_master_2_0_sim_netlist.vhdl | 4862 +
.../sim/system_design_fasec_hwtest_0_0.vhd | 4 +-
...stem_design_fasec_hwtest_0_0_sim_netlist.v | 88051 ------------
...m_design_fasec_hwtest_0_0_sim_netlist.vhdl | 108803 ---------------
.../sources_1/new/dac7716_spi.vhd | 0
.../sources_1/new/general_fmc.vhd | 6 +-
.../sources_1/new/top_mod.vhd | 5 +-
.../hdl_lib/modules/axi4/axi4lite_slave.vhd | 0
.../hdl_lib/modules/general/clockDivider.vhd | 0
.../hdl_lib/modules/general/counterUpDown.vhd | 0
.../modules/general/doubleBufferEdge.vhd | 0
.../hdl_lib/modules/general/pulseMeasure.vhd | 0
.../modules/general/spi_transceiver.vhd | 0
.../ip_cores/hdl_lib/modules/main_pkg.vhd | 0
.../system_design/activehdl/README.txt | 2 +-
.../system_design/activehdl/compile.do | 20 +-
.../system_design/activehdl/file_info.txt | 38 +-
.../system_design/activehdl/system_design.sh | 2 +-
.../sim_scripts/system_design/ies/README.txt | 2 +-
.../system_design/ies/file_info.txt | 38 +-
.../sim_scripts/system_design/ies/run.f | 20 +-
.../system_design/ies/system_design.sh | 2 +-
.../system_design/modelsim/README.txt | 2 +-
.../system_design/modelsim/compile.do | 20 +-
.../system_design/modelsim/file_info.txt | 38 +-
.../system_design/modelsim/system_design.sh | 2 +-
.../system_design/questa/README.txt | 2 +-
.../system_design/questa/compile.do | 20 +-
.../system_design/questa/file_info.txt | 38 +-
.../system_design/questa/system_design.sh | 2 +-
.../system_design/riviera/README.txt | 2 +-
.../system_design/riviera/compile.do | 20 +-
.../system_design/riviera/file_info.txt | 38 +-
.../system_design/riviera/system_design.sh | 2 +-
.../sim_scripts/system_design/vcs/README.txt | 2 +-
.../system_design/vcs/file_info.txt | 38 +-
.../system_design/vcs/system_design.sh | 22 +-
.../sim_scripts/system_design/xsim/README.txt | 2 +-
.../system_design/xsim/file_info.txt | 38 +-
.../system_design/xsim/system_design.sh | 2 +-
.../sim_scripts/system_design/xsim/vhdl.prj | 20 +-
.../bd/system_design/hdl/system_design.hwdef | Bin 73075 -> 73082 bytes
.../bd/system_design/hdl/system_design.vhd | 106 +-
.../hdl/system_design_wrapper.vhd | 16 +-
.../hw_handoff/system_design.hwh | 24 +-
.../hw_handoff/system_design_bd.tcl | 90 +-
.../system_design_auto_pc_0.dcp | Bin 186813 -> 186831 bytes
.../system_design_auto_pc_0.xml | 12 +-
.../system_design_auto_pc_0_sim_netlist.v | 2 +-
.../system_design_auto_pc_0_sim_netlist.vhdl | 2 +-
.../system_design_auto_pc_0_stub.v | 2 +-
.../system_design_auto_pc_0_stub.vhdl | 2 +-
.../system_design_auto_pc_1.dcp | Bin 267193 -> 267137 bytes
.../system_design_auto_pc_1.xml | 12 +-
.../system_design_auto_pc_1_sim_netlist.v | 2 +-
.../system_design_auto_pc_1_sim_netlist.vhdl | 2 +-
.../system_design_auto_pc_1_stub.v | 2 +-
.../system_design_auto_pc_1_stub.vhdl | 2 +-
.../system_design_auto_pc_2.dcp | Bin 267347 -> 267429 bytes
.../system_design_auto_pc_2.xml | 12 +-
.../system_design_auto_pc_2_sim_netlist.v | 2 +-
.../system_design_auto_pc_2_sim_netlist.vhdl | 2 +-
.../system_design_auto_pc_2_stub.v | 2 +-
.../system_design_auto_pc_2_stub.vhdl | 2 +-
.../sim/system_design_fasec_hwtest_0_0.vhd | 4 +-
.../synth/system_design_fasec_hwtest_0_0.vhd | 4 +-
.../system_design_fasec_hwtest_0_0.dcp | Bin 1293003 -> 1296219 bytes
.../system_design_fasec_hwtest_0_0.xci | 4 +-
.../system_design_fasec_hwtest_0_0.xml | 65 +-
...stem_design_fasec_hwtest_0_0_sim_netlist.v | 1864 +-
...m_design_fasec_hwtest_0_0_sim_netlist.vhdl | 1712 +-
.../system_design_fasec_hwtest_0_0_stub.v | 2 +-
.../system_design_fasec_hwtest_0_0_stub.vhdl | 2 +-
.../sources_1/new/dac7716_spi.vhd | 0
.../sources_1/new/general_fmc.vhd | 6 +-
.../sources_1/new/top_mod.vhd | 5 +-
.../hdl_lib/modules/axi4/axi4lite_slave.vhd | 0
.../hdl_lib/modules/general/clockDivider.vhd | 0
.../hdl_lib/modules/general/counterUpDown.vhd | 0
.../modules/general/doubleBufferEdge.vhd | 0
.../hdl_lib/modules/general/pulseMeasure.vhd | 0
.../modules/general/spi_transceiver.vhd | 0
.../ip_cores/hdl_lib/modules/main_pkg.vhd | 0
.../bd/system_design/system_design.bd | 38 +-
.../bd/system_design/system_design.bxml | 6 +-
.../bd/system_design/ui/bd_7f01d80e.ui | 88 +-
FASEC_prototype.xpr | 100 +-
ip_cores/cores | 2 +-
ip_upgrade.log | 21 +
95 files changed, 20524 insertions(+), 199481 deletions(-)
delete mode 100644 .Xil/Vivado-5010-lapte24154/coregen/aximm_temp/aximm_temp.xci
delete mode 100644 .Xil/Vivado-5010-lapte24154/coregen/aximm_temp/aximm_temp.xml
create mode 100644 FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v
create mode 100644 FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl
create mode 100644 FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v
create mode 100644 FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl
delete mode 100644 FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.v
delete mode 100644 FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.vhdl
rename FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd (100%)
rename FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd (99%)
rename FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd (99%)
rename FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd (100%)
rename FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/ip_cores/hdl_lib/modules/general/clockDivider.vhd (100%)
rename FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/ip_cores/hdl_lib/modules/general/counterUpDown.vhd (100%)
rename FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd (100%)
rename FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd (100%)
rename FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd (100%)
rename FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/ip_cores/hdl_lib/modules/main_pkg.vhd (100%)
rename FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd (100%)
rename FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd (99%)
rename FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd (99%)
rename FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd (100%)
rename FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/ip_cores/hdl_lib/modules/general/clockDivider.vhd (100%)
rename FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/ip_cores/hdl_lib/modules/general/counterUpDown.vhd (100%)
rename FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd (100%)
rename FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd (100%)
rename FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd (100%)
rename FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/{fasec_hwtest_v3_2_6 => fasec_hwtest_v3_2_7}/ip_cores/hdl_lib/modules/main_pkg.vhd (100%)
diff --git a/.Xil/Vivado-5010-lapte24154/coregen/aximm_temp/aximm_temp.xci b/.Xil/Vivado-5010-lapte24154/coregen/aximm_temp/aximm_temp.xci
deleted file mode 100644
index 8d241b9f..00000000
--- a/.Xil/Vivado-5010-lapte24154/coregen/aximm_temp/aximm_temp.xci
+++ /dev/null
@@ -1,61 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>xci</spirit:library>
- <spirit:name>unknown</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:componentInstances>
- <spirit:componentInstance>
- <spirit:instanceName>aximm_temp</spirit:instanceName>
- <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="interface.param" spirit:name="aximm" spirit:version="1.0"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDR_WIDTH">32</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_DOMAIN">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">aximm_temp</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">32</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FREQ_HZ">100000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_BRESP">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_BURST">1</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_LOCK">1</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_QOS">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_REGION">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_RRESP">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_WSTRB">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE">0.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUPPORTS_NARROW_BURST">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z030</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg676</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator_BusInterface</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2016.2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
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diff --git a/.Xil/Vivado-5010-lapte24154/coregen/aximm_temp/aximm_temp.xml b/.Xil/Vivado-5010-lapte24154/coregen/aximm_temp/aximm_temp.xml
deleted file mode 100644
index beda0cdc..00000000
--- a/.Xil/Vivado-5010-lapte24154/coregen/aximm_temp/aximm_temp.xml
+++ /dev/null
@@ -1,386 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>customized_ip</spirit:library>
- <spirit:name>aximm_temp</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:model>
- <spirit:ports>
- <spirit:port>
- <spirit:name>const</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left spirit:format="long">0</spirit:left>
- <spirit:right spirit:format="long">0</spirit:right>
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- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>std_logic_vector</spirit:typeName>
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- </spirit:port>
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- <spirit:choices>
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- <spirit:name>choice_list_0e867c35</spirit:name>
- <spirit:enumeration>READ_WRITE</spirit:enumeration>
- <spirit:enumeration>READ_ONLY</spirit:enumeration>
- <spirit:enumeration>WRITE_ONLY</spirit:enumeration>
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- <spirit:choice>
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- <spirit:enumeration>0</spirit:enumeration>
- <spirit:enumeration>1</spirit:enumeration>
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- <spirit:description>aximm parameters</spirit:description>
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- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:displayName>Phase</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PHASE" spirit:order="1200">0.0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
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- </spirit:vendorExtensions>
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- <spirit:parameter>
- <spirit:name>MAX_BURST_LENGTH</spirit:name>
- <spirit:displayName>Max Burst Length</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MAX_BURST_LENGTH" spirit:order="1300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">256</spirit:value>
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- <spirit:name>AWUSER_WIDTH</spirit:name>
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- <spirit:name>ADDR_WIDTH</spirit:name>
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- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADDR_WIDTH" spirit:order="2300" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
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- <spirit:parameter>
- <spirit:name>ID_WIDTH</spirit:name>
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- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
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- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.FREQ_HZ" spirit:order="2500">100000000</spirit:value>
- <spirit:vendorExtensions>
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- <spirit:name>PROTOCOL</spirit:name>
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- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PROTOCOL" spirit:choiceRef="choice_list_839fa0cc" spirit:order="2600">AXI4</spirit:value>
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- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:choiceRef="choice_list_40181835" spirit:order="2700">32</spirit:value>
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- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_BURST</spirit:name>
- <spirit:displayName>Has BURST</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_BURST" spirit:choiceRef="choice_list_8af5a703" spirit:order="2800">1</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent">true</xilinx:isEnabled>
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- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_CACHE</spirit:name>
- <spirit:displayName>Has CACHE</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_CACHE" spirit:choiceRef="choice_list_8af5a703" spirit:order="2900">1</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent">true</xilinx:isEnabled>
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- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_LOCK</spirit:name>
- <spirit:displayName>Has LOCK</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_LOCK" spirit:choiceRef="choice_list_8af5a703" spirit:order="3000">1</spirit:value>
- <spirit:vendorExtensions>
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- <spirit:name>HAS_PROT</spirit:name>
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- <spirit:displayName>Has WSTRB</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.HAS_WSTRB" spirit:choiceRef="choice_list_8af5a703" spirit:order="3400">1</spirit:value>
- <spirit:vendorExtensions>
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- <spirit:name>HAS_BRESP</spirit:name>
- <spirit:displayName>Has BRESP</spirit:displayName>
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- <spirit:parameter>
- <spirit:name>Component_Name</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">aximm_temp</spirit:value>
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- <spirit:vendorExtensions>
- <xilinx:coreExtensions>
- <xilinx:displayName>aximm</xilinx:displayName>
- <xilinx:coreRevision>1</xilinx:coreRevision>
- <xilinx:tags>
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- </xilinx:coreExtensions>
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diff --git a/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd b/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd
index 56688d53..21496934 100644
--- a/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd
@@ -1,7 +1,7 @@
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
---Date : Wed Oct 11 14:50:45 2017
+--Date : Thu Oct 12 09:59:12 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.2
--Command : generate_target system_design.bd
--Design : system_design
@@ -3621,8 +3621,6 @@ entity system_design is
dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
eeprom_scl : inout STD_LOGIC;
eeprom_sda : inout STD_LOGIC;
- fmcx_scl : inout STD_LOGIC;
- fmcx_sda : inout STD_LOGIC;
gtp0_rate_select_b : inout STD_LOGIC;
gtp_dedicated_clk_n_i : in STD_LOGIC;
gtp_dedicated_clk_p_i : in STD_LOGIC;
@@ -3636,6 +3634,12 @@ entity system_design is
gtp_wr_tx_fault : in STD_LOGIC;
gtp_wr_txn : out STD_LOGIC;
gtp_wr_txp : out STD_LOGIC;
+ i2c_master_fmcx_scl_i : in STD_LOGIC;
+ i2c_master_fmcx_scl_o : out STD_LOGIC;
+ i2c_master_fmcx_scl_t : out STD_LOGIC;
+ i2c_master_fmcx_sda_i : in STD_LOGIC;
+ i2c_master_fmcx_sda_o : out STD_LOGIC;
+ i2c_master_fmcx_sda_t : out STD_LOGIC;
led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_line_en_pl_o : out STD_LOGIC;
led_line_pl_o : out STD_LOGIC;
@@ -4071,47 +4075,15 @@ architecture STRUCTURE of system_design is
s00_axi_rready : in STD_LOGIC
);
end component system_design_wrc_1p_kintex7_0_0;
- component system_design_fasec_hwtest_0_0 is
+ component system_design_axi_wb_i2c_master_0_1 is
port (
- ps_clk_i : in STD_LOGIC;
- osc100_clk_i : in STD_LOGIC;
- FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC2_PRSNTM2C_n_i : in STD_LOGIC;
- FMC2_CLK0M2C_P_i : in STD_LOGIC;
- FMC2_CLK0M2C_N_i : in STD_LOGIC;
- FMC2_CLK0C2M_P_o : out STD_LOGIC;
- FMC2_CLK0C2M_N_o : out STD_LOGIC;
- FMC2_GP0_i : in STD_LOGIC;
- FMC2_GP1_i : in STD_LOGIC;
- FMC2_GP2_i : in STD_LOGIC;
- FMC2_GP3_b : inout STD_LOGIC;
- FMC1_PRSNTM2C_n_i : in STD_LOGIC;
- FMC1_CLK0M2C_P_i : in STD_LOGIC;
- FMC1_CLK0M2C_N_i : in STD_LOGIC;
- FMC1_CLK0C2M_P_o : out STD_LOGIC;
- FMC1_CLK0C2M_N_o : out STD_LOGIC;
- FMC1_GP0_i : in STD_LOGIC;
- FMC1_GP1_i : in STD_LOGIC;
- FMC1_GP2_i : in STD_LOGIC;
- FMC1_GP3_b : inout STD_LOGIC;
- pb_gp_n_i : in STD_LOGIC;
- led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
- led_line_en_pl_o : out STD_LOGIC;
- led_line_pl_o : out STD_LOGIC;
- watchdog_pl_o : out STD_LOGIC;
- dig_in1_i : in STD_LOGIC;
- dig_in2_i : in STD_LOGIC;
- dig_in3_n_i : in STD_LOGIC;
- dig_in4_n_i : in STD_LOGIC;
- dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
- dig_out5_n : out STD_LOGIC;
- dig_out6_n : out STD_LOGIC;
- gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
- intr_o : out STD_LOGIC;
- intr_led_o : out STD_LOGIC;
+ i2c_scl_i : in STD_LOGIC;
+ i2c_scl_o : out STD_LOGIC;
+ i2c_scl_t : out STD_LOGIC;
+ i2c_sda_i : in STD_LOGIC;
+ i2c_sda_o : out STD_LOGIC;
+ i2c_sda_t : out STD_LOGIC;
+ axi_int_o : out STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -4134,8 +4106,8 @@ architecture STRUCTURE of system_design is
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
- end component system_design_fasec_hwtest_0_0;
- component system_design_axi_wb_i2c_master_0_1 is
+ end component system_design_axi_wb_i2c_master_0_1;
+ component system_design_axi_wb_i2c_master_2_0 is
port (
i2c_scl_i : in STD_LOGIC;
i2c_scl_o : out STD_LOGIC;
@@ -4166,16 +4138,48 @@ architecture STRUCTURE of system_design is
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
- end component system_design_axi_wb_i2c_master_0_1;
- component system_design_axi_wb_i2c_master_2_0 is
+ end component system_design_axi_wb_i2c_master_2_0;
+ component system_design_fasec_hwtest_0_0 is
port (
- i2c_scl_i : in STD_LOGIC;
- i2c_scl_o : out STD_LOGIC;
- i2c_scl_t : out STD_LOGIC;
- i2c_sda_i : in STD_LOGIC;
- i2c_sda_o : out STD_LOGIC;
- i2c_sda_t : out STD_LOGIC;
- axi_int_o : out STD_LOGIC;
+ ps_clk_i : in STD_LOGIC;
+ osc100_clk_i : in STD_LOGIC;
+ FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+ FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+ FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+ FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+ FMC2_PRSNTM2C_n_i : in STD_LOGIC;
+ FMC2_CLK0M2C_P_i : in STD_LOGIC;
+ FMC2_CLK0M2C_N_i : in STD_LOGIC;
+ FMC2_CLK0C2M_P_o : out STD_LOGIC;
+ FMC2_CLK0C2M_N_o : out STD_LOGIC;
+ FMC2_GP0_i : in STD_LOGIC;
+ FMC2_GP1_i : in STD_LOGIC;
+ FMC2_GP2_i : in STD_LOGIC;
+ FMC2_GP3_b : inout STD_LOGIC;
+ FMC1_PRSNTM2C_n_i : in STD_LOGIC;
+ FMC1_CLK0M2C_P_i : in STD_LOGIC;
+ FMC1_CLK0M2C_N_i : in STD_LOGIC;
+ FMC1_CLK0C2M_P_o : out STD_LOGIC;
+ FMC1_CLK0C2M_N_o : out STD_LOGIC;
+ FMC1_GP0_i : in STD_LOGIC;
+ FMC1_GP1_i : in STD_LOGIC;
+ FMC1_GP2_i : in STD_LOGIC;
+ FMC1_GP3_b : inout STD_LOGIC;
+ pb_gp_n_i : in STD_LOGIC;
+ led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ led_line_en_pl_o : out STD_LOGIC;
+ led_line_pl_o : out STD_LOGIC;
+ watchdog_pl_o : out STD_LOGIC;
+ dig_in1_i : in STD_LOGIC;
+ dig_in2_i : in STD_LOGIC;
+ dig_in3_n_i : in STD_LOGIC;
+ dig_in4_n_i : in STD_LOGIC;
+ dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ dig_out5_n : out STD_LOGIC;
+ dig_out6_n : out STD_LOGIC;
+ gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ intr_o : out STD_LOGIC;
+ intr_led_o : out STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -4198,15 +4202,13 @@ architecture STRUCTURE of system_design is
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
- end component system_design_axi_wb_i2c_master_2_0;
+ end component system_design_fasec_hwtest_0_0;
signal FMC1_CLK0M2C_N_i_1 : STD_LOGIC;
signal FMC1_CLK0M2C_P_i_1 : STD_LOGIC;
signal FMC1_PRSNTM2C_n_i_1 : STD_LOGIC;
signal FMC2_CLK0M2C_N_i_1 : STD_LOGIC;
signal FMC2_CLK0M2C_P_i_1 : STD_LOGIC;
signal FMC2_PRSNTM2C_n_i_1 : STD_LOGIC;
- signal Net : STD_LOGIC;
- signal Net1 : STD_LOGIC;
signal Net10 : STD_LOGIC;
signal Net11 : STD_LOGIC;
signal Net2 : STD_LOGIC;
@@ -4325,6 +4327,12 @@ architecture STRUCTURE of system_design is
signal axi_uartlite_0_tx : STD_LOGIC;
signal axi_wb_i2c_master_0_axi_int_o : STD_LOGIC;
signal axi_wb_i2c_master_2_axi_int_o : STD_LOGIC;
+ signal axi_wb_i2c_master_2_i2c_master_SCL_I : STD_LOGIC;
+ signal axi_wb_i2c_master_2_i2c_master_SCL_O : STD_LOGIC;
+ signal axi_wb_i2c_master_2_i2c_master_SCL_T : STD_LOGIC;
+ signal axi_wb_i2c_master_2_i2c_master_SDA_I : STD_LOGIC;
+ signal axi_wb_i2c_master_2_i2c_master_SDA_O : STD_LOGIC;
+ signal axi_wb_i2c_master_2_i2c_master_SDA_T : STD_LOGIC;
signal clk_25m_vcxo_i_1 : STD_LOGIC;
signal dig_in1_i_1 : STD_LOGIC;
signal dig_in2_i_1 : STD_LOGIC;
@@ -4575,10 +4583,6 @@ architecture STRUCTURE of system_design is
signal NLW_axi_wb_i2c_master_0_i2c_scl_t_UNCONNECTED : STD_LOGIC;
signal NLW_axi_wb_i2c_master_0_i2c_sda_o_UNCONNECTED : STD_LOGIC;
signal NLW_axi_wb_i2c_master_0_i2c_sda_t_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_wb_i2c_master_2_i2c_scl_o_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_wb_i2c_master_2_i2c_scl_t_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_wb_i2c_master_2_i2c_sda_o_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_wb_i2c_master_2_i2c_sda_t_UNCONNECTED : STD_LOGIC;
signal NLW_fasec_hwtest_0_FMC1_GP3_b_UNCONNECTED : STD_LOGIC;
signal NLW_fasec_hwtest_0_FMC2_GP3_b_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
@@ -4649,6 +4653,8 @@ begin
Vaux9_1_V_P <= Vaux9_v_p;
Vp_Vn_1_V_N <= Vp_Vn_v_n;
Vp_Vn_1_V_P <= Vp_Vn_v_p;
+ axi_wb_i2c_master_2_i2c_master_SCL_I <= i2c_master_fmcx_scl_i;
+ axi_wb_i2c_master_2_i2c_master_SDA_I <= i2c_master_fmcx_sda_i;
clk_25m_vcxo_i_1 <= clk_25m_vcxo_i;
dac_cs1_n_o <= wrc_1p_kintex7_0_dac_cs1_n_o;
dac_cs2_n_o <= wrc_1p_kintex7_0_dac_cs2_n_o;
@@ -4666,6 +4672,10 @@ begin
gtp_wr_tx_disable <= wrc_1p_kintex7_0_gtp_wr_TX_DISABLE;
gtp_wr_txn <= wrc_1p_kintex7_0_gtp_wr_TXN;
gtp_wr_txp <= wrc_1p_kintex7_0_gtp_wr_TXP;
+ i2c_master_fmcx_scl_o <= axi_wb_i2c_master_2_i2c_master_SCL_O;
+ i2c_master_fmcx_scl_t <= axi_wb_i2c_master_2_i2c_master_SCL_T;
+ i2c_master_fmcx_sda_o <= axi_wb_i2c_master_2_i2c_master_SDA_O;
+ i2c_master_fmcx_sda_t <= axi_wb_i2c_master_2_i2c_master_SDA_T;
led_col_pl_o(3 downto 0) <= fasec_hwtest_0_led_col_pl_o(3 downto 0);
led_line_en_pl_o <= fasec_hwtest_0_led_line_en_pl_o;
led_line_pl_o <= fasec_hwtest_0_led_line_pl_o;
@@ -4890,12 +4900,12 @@ axi_wb_i2c_master_0: component system_design_axi_wb_i2c_master_0_1
axi_wb_i2c_master_2: component system_design_axi_wb_i2c_master_2_0
port map (
axi_int_o => axi_wb_i2c_master_2_axi_int_o,
- i2c_scl_i => '0',
- i2c_scl_o => NLW_axi_wb_i2c_master_2_i2c_scl_o_UNCONNECTED,
- i2c_scl_t => NLW_axi_wb_i2c_master_2_i2c_scl_t_UNCONNECTED,
- i2c_sda_i => '0',
- i2c_sda_o => NLW_axi_wb_i2c_master_2_i2c_sda_o_UNCONNECTED,
- i2c_sda_t => NLW_axi_wb_i2c_master_2_i2c_sda_t_UNCONNECTED,
+ i2c_scl_i => axi_wb_i2c_master_2_i2c_master_SCL_I,
+ i2c_scl_o => axi_wb_i2c_master_2_i2c_master_SCL_O,
+ i2c_scl_t => axi_wb_i2c_master_2_i2c_master_SCL_T,
+ i2c_sda_i => axi_wb_i2c_master_2_i2c_master_SDA_I,
+ i2c_sda_o => axi_wb_i2c_master_2_i2c_master_SDA_O,
+ i2c_sda_t => axi_wb_i2c_master_2_i2c_master_SDA_T,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v
new file mode 100644
index 00000000..1a9b16dc
--- /dev/null
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v
@@ -0,0 +1,4084 @@
+// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
+// Date : Wed Oct 11 14:52:24 2017
+// Host : lapte24154 running 64-bit openSUSE Leap 42.2
+// Command : write_verilog -force -mode funcsim
+// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.v
+// Design : system_design_axi_wb_i2c_master_0_1
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7z030ffg676-2
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "system_design_axi_wb_i2c_master_0_1,axi_wb_i2c_master,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_wb_i2c_master,Vivado 2016.2" *)
+(* NotValidForBitStream *)
+module system_design_axi_wb_i2c_master_0_1
+ (i2c_scl_i,
+ i2c_scl_o,
+ i2c_scl_t,
+ i2c_sda_i,
+ i2c_sda_o,
+ i2c_sda_t,
+ axi_int_o,
+ s00_axi_aclk,
+ s00_axi_aresetn,
+ s00_axi_awaddr,
+ s00_axi_awprot,
+ s00_axi_awvalid,
+ s00_axi_awready,
+ s00_axi_wdata,
+ s00_axi_wstrb,
+ s00_axi_wvalid,
+ s00_axi_wready,
+ s00_axi_bresp,
+ s00_axi_bvalid,
+ s00_axi_bready,
+ s00_axi_araddr,
+ s00_axi_arprot,
+ s00_axi_arvalid,
+ s00_axi_arready,
+ s00_axi_rdata,
+ s00_axi_rresp,
+ s00_axi_rvalid,
+ s00_axi_rready);
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 i2c_master SCL_I" *) input i2c_scl_i;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 i2c_master SCL_O" *) output i2c_scl_o;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 i2c_master SCL_T" *) output i2c_scl_t;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 i2c_master SDA_I" *) input i2c_sda_i;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 i2c_master SDA_O" *) output i2c_sda_o;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 i2c_master SDA_T" *) output i2c_sda_t;
+ output axi_int_o;
+ (* x_interface_info = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *) input s00_axi_aclk;
+ (* x_interface_info = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *) input s00_axi_aresetn;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *) input [31:0]s00_axi_awaddr;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *) input [2:0]s00_axi_awprot;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *) input s00_axi_awvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *) output s00_axi_awready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *) input [31:0]s00_axi_wdata;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *) input [3:0]s00_axi_wstrb;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *) input s00_axi_wvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *) output s00_axi_wready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *) output [1:0]s00_axi_bresp;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *) output s00_axi_bvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *) input s00_axi_bready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *) input [31:0]s00_axi_araddr;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *) input [2:0]s00_axi_arprot;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *) input s00_axi_arvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *) output s00_axi_arready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *) output [31:0]s00_axi_rdata;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *) output [1:0]s00_axi_rresp;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *) output s00_axi_rvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *) input s00_axi_rready;
+
+ wire axi_int_o;
+ wire i2c_scl_i;
+ wire i2c_scl_o;
+ wire i2c_scl_t;
+ wire i2c_sda_i;
+ wire i2c_sda_o;
+ wire i2c_sda_t;
+ wire s00_axi_aclk;
+ wire [31:0]s00_axi_araddr;
+ wire s00_axi_aresetn;
+ wire [2:0]s00_axi_arprot;
+ wire s00_axi_arready;
+ wire s00_axi_arvalid;
+ wire [31:0]s00_axi_awaddr;
+ wire [2:0]s00_axi_awprot;
+ wire s00_axi_awready;
+ wire s00_axi_awvalid;
+ wire s00_axi_bready;
+ wire [1:0]s00_axi_bresp;
+ wire s00_axi_bvalid;
+ wire [31:0]s00_axi_rdata;
+ wire s00_axi_rready;
+ wire [1:0]s00_axi_rresp;
+ wire s00_axi_rvalid;
+ wire [31:0]s00_axi_wdata;
+ wire s00_axi_wready;
+ wire [3:0]s00_axi_wstrb;
+ wire s00_axi_wvalid;
+
+ (* C_S00_AXI_ADDR_WIDTH = "32" *)
+ (* C_S00_AXI_DATA_WIDTH = "32" *)
+ system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master U0
+ (.axi_int_o(axi_int_o),
+ .i2c_scl_i(i2c_scl_i),
+ .i2c_scl_o(i2c_scl_o),
+ .i2c_scl_t(i2c_scl_t),
+ .i2c_sda_i(i2c_sda_i),
+ .i2c_sda_o(i2c_sda_o),
+ .i2c_sda_t(i2c_sda_t),
+ .s00_axi_aclk(s00_axi_aclk),
+ .s00_axi_araddr(s00_axi_araddr),
+ .s00_axi_aresetn(s00_axi_aresetn),
+ .s00_axi_arprot(s00_axi_arprot),
+ .s00_axi_arready(s00_axi_arready),
+ .s00_axi_arvalid(s00_axi_arvalid),
+ .s00_axi_awaddr(s00_axi_awaddr),
+ .s00_axi_awprot(s00_axi_awprot),
+ .s00_axi_awready(s00_axi_awready),
+ .s00_axi_awvalid(s00_axi_awvalid),
+ .s00_axi_bready(s00_axi_bready),
+ .s00_axi_bresp(s00_axi_bresp),
+ .s00_axi_bvalid(s00_axi_bvalid),
+ .s00_axi_rdata(s00_axi_rdata),
+ .s00_axi_rready(s00_axi_rready),
+ .s00_axi_rresp(s00_axi_rresp),
+ .s00_axi_rvalid(s00_axi_rvalid),
+ .s00_axi_wdata(s00_axi_wdata),
+ .s00_axi_wready(s00_axi_wready),
+ .s00_axi_wstrb(s00_axi_wstrb),
+ .s00_axi_wvalid(s00_axi_wvalid));
+endmodule
+
+(* C_S00_AXI_ADDR_WIDTH = "32" *) (* C_S00_AXI_DATA_WIDTH = "32" *) (* ORIG_REF_NAME = "axi_wb_i2c_master" *)
+module system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master
+ (i2c_scl_i,
+ i2c_scl_o,
+ i2c_scl_t,
+ i2c_sda_i,
+ i2c_sda_o,
+ i2c_sda_t,
+ axi_int_o,
+ s00_axi_aclk,
+ s00_axi_aresetn,
+ s00_axi_awaddr,
+ s00_axi_awprot,
+ s00_axi_awvalid,
+ s00_axi_awready,
+ s00_axi_wdata,
+ s00_axi_wstrb,
+ s00_axi_wvalid,
+ s00_axi_wready,
+ s00_axi_bresp,
+ s00_axi_bvalid,
+ s00_axi_bready,
+ s00_axi_araddr,
+ s00_axi_arprot,
+ s00_axi_arvalid,
+ s00_axi_arready,
+ s00_axi_rdata,
+ s00_axi_rresp,
+ s00_axi_rvalid,
+ s00_axi_rready);
+ input i2c_scl_i;
+ output i2c_scl_o;
+ output i2c_scl_t;
+ input i2c_sda_i;
+ output i2c_sda_o;
+ output i2c_sda_t;
+ output axi_int_o;
+ input s00_axi_aclk;
+ input s00_axi_aresetn;
+ input [31:0]s00_axi_awaddr;
+ input [2:0]s00_axi_awprot;
+ input s00_axi_awvalid;
+ output s00_axi_awready;
+ input [31:0]s00_axi_wdata;
+ input [3:0]s00_axi_wstrb;
+ input s00_axi_wvalid;
+ output s00_axi_wready;
+ output [1:0]s00_axi_bresp;
+ output s00_axi_bvalid;
+ input s00_axi_bready;
+ input [31:0]s00_axi_araddr;
+ input [2:0]s00_axi_arprot;
+ input s00_axi_arvalid;
+ output s00_axi_arready;
+ output [31:0]s00_axi_rdata;
+ output [1:0]s00_axi_rresp;
+ output s00_axi_rvalid;
+ input s00_axi_rready;
+
+ wire \<const0> ;
+ wire axi_int_o;
+ wire cmp_axis_wbm_bridge_n_11;
+ wire cmp_axis_wbm_bridge_n_12;
+ wire cmp_axis_wbm_bridge_n_13;
+ wire cmp_axis_wbm_bridge_n_14;
+ wire cmp_axis_wbm_bridge_n_15;
+ wire cmp_axis_wbm_bridge_n_16;
+ wire cmp_axis_wbm_bridge_n_17;
+ wire cmp_axis_wbm_bridge_n_18;
+ wire cmp_axis_wbm_bridge_n_19;
+ wire cmp_axis_wbm_bridge_n_21;
+ wire cmp_axis_wbm_bridge_n_7;
+ wire cmp_i2c_master_top_n_6;
+ wire cmp_i2c_master_top_n_7;
+ wire ena;
+ wire i2c_scl_i;
+ wire i2c_scl_t;
+ wire i2c_sda_i;
+ wire i2c_sda_t;
+ wire s00_axi_aclk;
+ wire [31:0]s00_axi_araddr;
+ wire s00_axi_aresetn;
+ wire s00_axi_arready;
+ wire s00_axi_arvalid;
+ wire [31:0]s00_axi_awaddr;
+ wire s00_axi_awready;
+ wire s00_axi_awvalid;
+ wire s00_axi_bready;
+ wire [1:1]\^s00_axi_bresp ;
+ wire s00_axi_bvalid;
+ wire [7:0]\^s00_axi_rdata ;
+ wire s00_axi_rready;
+ wire s00_axi_rvalid;
+ wire [31:0]s00_axi_wdata;
+ wire s00_axi_wready;
+ wire s00_axi_wvalid;
+ wire wb_ack_i;
+ wire [2:0]wb_adr_o;
+ wire wb_cyc_o;
+ wire [7:0]wb_dat_o;
+ wire wb_rst_o;
+ wire wb_we_o;
+
+ assign i2c_scl_o = \<const0> ;
+ assign i2c_sda_o = \<const0> ;
+ assign s00_axi_bresp[1] = \^s00_axi_bresp [1];
+ assign s00_axi_bresp[0] = \<const0> ;
+ assign s00_axi_rdata[31] = \<const0> ;
+ assign s00_axi_rdata[30] = \<const0> ;
+ assign s00_axi_rdata[29] = \<const0> ;
+ assign s00_axi_rdata[28] = \<const0> ;
+ assign s00_axi_rdata[27] = \<const0> ;
+ assign s00_axi_rdata[26] = \<const0> ;
+ assign s00_axi_rdata[25] = \<const0> ;
+ assign s00_axi_rdata[24] = \<const0> ;
+ assign s00_axi_rdata[23] = \<const0> ;
+ assign s00_axi_rdata[22] = \<const0> ;
+ assign s00_axi_rdata[21] = \<const0> ;
+ assign s00_axi_rdata[20] = \<const0> ;
+ assign s00_axi_rdata[19] = \<const0> ;
+ assign s00_axi_rdata[18] = \<const0> ;
+ assign s00_axi_rdata[17] = \<const0> ;
+ assign s00_axi_rdata[16] = \<const0> ;
+ assign s00_axi_rdata[15] = \<const0> ;
+ assign s00_axi_rdata[14] = \<const0> ;
+ assign s00_axi_rdata[13] = \<const0> ;
+ assign s00_axi_rdata[12] = \<const0> ;
+ assign s00_axi_rdata[11] = \<const0> ;
+ assign s00_axi_rdata[10] = \<const0> ;
+ assign s00_axi_rdata[9] = \<const0> ;
+ assign s00_axi_rdata[8] = \<const0> ;
+ assign s00_axi_rdata[7:0] = \^s00_axi_rdata [7:0];
+ assign s00_axi_rresp[1] = \<const0> ;
+ assign s00_axi_rresp[0] = \<const0> ;
+ GND GND
+ (.G(\<const0> ));
+ system_design_axi_wb_i2c_master_0_1_axis_wbm_bridge cmp_axis_wbm_bridge
+ (.D({cmp_axis_wbm_bridge_n_12,cmp_axis_wbm_bridge_n_13,cmp_axis_wbm_bridge_n_14,cmp_axis_wbm_bridge_n_15}),
+ .E(cmp_axis_wbm_bridge_n_11),
+ .Q(ena),
+ .\cr_reg[2] (cmp_axis_wbm_bridge_n_7),
+ .\cr_reg[4] (cmp_axis_wbm_bridge_n_16),
+ .\ctr_reg[0] (cmp_axis_wbm_bridge_n_19),
+ .iack_o_reg(cmp_axis_wbm_bridge_n_21),
+ .iack_o_reg_0(cmp_i2c_master_top_n_6),
+ .iack_o_reg_1(cmp_i2c_master_top_n_7),
+ .\prer_reg[8] ({cmp_axis_wbm_bridge_n_17,cmp_axis_wbm_bridge_n_18}),
+ .s00_axi_aclk(s00_axi_aclk),
+ .s00_axi_araddr(s00_axi_araddr[4:2]),
+ .s00_axi_aresetn(s00_axi_aresetn),
+ .s00_axi_arready(s00_axi_arready),
+ .s00_axi_arvalid(s00_axi_arvalid),
+ .s00_axi_awaddr(s00_axi_awaddr[4:2]),
+ .s00_axi_awready(s00_axi_awready),
+ .s00_axi_awvalid(s00_axi_awvalid),
+ .s00_axi_bready(s00_axi_bready),
+ .s00_axi_bresp(\^s00_axi_bresp ),
+ .s00_axi_bvalid(s00_axi_bvalid),
+ .s00_axi_rdata(\^s00_axi_rdata ),
+ .s00_axi_rready(s00_axi_rready),
+ .s00_axi_rvalid(s00_axi_rvalid),
+ .s00_axi_wdata(s00_axi_wdata[7:4]),
+ .s00_axi_wready(s00_axi_wready),
+ .s00_axi_wvalid(s00_axi_wvalid),
+ .wb_ack_i(wb_ack_i),
+ .wb_adr_o(wb_adr_o),
+ .wb_cyc_o(wb_cyc_o),
+ .\wb_dat_o_reg[7] (wb_dat_o),
+ .wb_rst_o(wb_rst_o),
+ .wb_we_o(wb_we_o));
+ system_design_axi_wb_i2c_master_0_1_i2c_master_top cmp_i2c_master_top
+ (.D({cmp_axis_wbm_bridge_n_12,cmp_axis_wbm_bridge_n_13,cmp_axis_wbm_bridge_n_14,cmp_axis_wbm_bridge_n_15}),
+ .E({cmp_axis_wbm_bridge_n_17,cmp_axis_wbm_bridge_n_18}),
+ .Q(ena),
+ .axi_int_o(axi_int_o),
+ .i2c_scl_i(i2c_scl_i),
+ .i2c_scl_t(i2c_scl_t),
+ .i2c_sda_i(i2c_sda_i),
+ .i2c_sda_t(i2c_sda_t),
+ .iack_o_reg_0(cmp_axis_wbm_bridge_n_16),
+ .s00_axi_aclk(s00_axi_aclk),
+ .s00_axi_aresetn(s00_axi_aresetn),
+ .s00_axi_arvalid(s00_axi_arvalid),
+ .s00_axi_awvalid(s00_axi_awvalid),
+ .s00_axi_wdata(s00_axi_wdata[7:0]),
+ .\s_addr_reg[4] (cmp_axis_wbm_bridge_n_7),
+ .\s_rdata_reg[0] (cmp_i2c_master_top_n_7),
+ .\s_rdata_reg[7] (wb_dat_o),
+ .s_stb_r_reg(cmp_i2c_master_top_n_6),
+ .s_stb_r_reg_0(cmp_axis_wbm_bridge_n_21),
+ .s_we_r_reg(cmp_axis_wbm_bridge_n_19),
+ .s_we_r_reg_0(cmp_axis_wbm_bridge_n_11),
+ .wb_ack_i(wb_ack_i),
+ .wb_adr_o(wb_adr_o),
+ .wb_cyc_o(wb_cyc_o),
+ .wb_rst_o(wb_rst_o),
+ .wb_we_o(wb_we_o));
+endmodule
+
+(* ORIG_REF_NAME = "axis_wbm_bridge" *)
+module system_design_axi_wb_i2c_master_0_1_axis_wbm_bridge
+ (s00_axi_awready,
+ s00_axi_wready,
+ s00_axi_arready,
+ wb_we_o,
+ wb_cyc_o,
+ s00_axi_bresp,
+ s00_axi_bvalid,
+ \cr_reg[2] ,
+ wb_adr_o,
+ E,
+ D,
+ \cr_reg[4] ,
+ \prer_reg[8] ,
+ \ctr_reg[0] ,
+ s00_axi_rvalid,
+ iack_o_reg,
+ s00_axi_rdata,
+ wb_rst_o,
+ s00_axi_aclk,
+ iack_o_reg_0,
+ Q,
+ s00_axi_aresetn,
+ wb_ack_i,
+ s00_axi_awvalid,
+ s00_axi_arvalid,
+ s00_axi_bready,
+ s00_axi_rready,
+ s00_axi_wvalid,
+ s00_axi_wdata,
+ s00_axi_araddr,
+ s00_axi_awaddr,
+ iack_o_reg_1,
+ \wb_dat_o_reg[7] );
+ output s00_axi_awready;
+ output s00_axi_wready;
+ output s00_axi_arready;
+ output wb_we_o;
+ output wb_cyc_o;
+ output [0:0]s00_axi_bresp;
+ output s00_axi_bvalid;
+ output \cr_reg[2] ;
+ output [2:0]wb_adr_o;
+ output [0:0]E;
+ output [3:0]D;
+ output \cr_reg[4] ;
+ output [1:0]\prer_reg[8] ;
+ output [0:0]\ctr_reg[0] ;
+ output s00_axi_rvalid;
+ output iack_o_reg;
+ output [7:0]s00_axi_rdata;
+ input wb_rst_o;
+ input s00_axi_aclk;
+ input iack_o_reg_0;
+ input [0:0]Q;
+ input s00_axi_aresetn;
+ input wb_ack_i;
+ input s00_axi_awvalid;
+ input s00_axi_arvalid;
+ input s00_axi_bready;
+ input s00_axi_rready;
+ input s00_axi_wvalid;
+ input [3:0]s00_axi_wdata;
+ input [2:0]s00_axi_araddr;
+ input [2:0]s00_axi_awaddr;
+ input [0:0]iack_o_reg_1;
+ input [7:0]\wb_dat_o_reg[7] ;
+
+ wire [3:0]D;
+ wire [0:0]E;
+ wire [0:0]Q;
+ wire \cr[2]_i_3_n_0 ;
+ wire \cr_reg[2] ;
+ wire \cr_reg[4] ;
+ wire [0:0]\ctr_reg[0] ;
+ wire iack_o_reg;
+ wire iack_o_reg_0;
+ wire [0:0]iack_o_reg_1;
+ wire [1:0]\prer_reg[8] ;
+ wire s00_axi_aclk;
+ wire [2:0]s00_axi_araddr;
+ wire s00_axi_aresetn;
+ wire s00_axi_arready;
+ wire s00_axi_arvalid;
+ wire [2:0]s00_axi_awaddr;
+ wire s00_axi_awready;
+ wire s00_axi_awvalid;
+ wire s00_axi_bready;
+ wire [0:0]s00_axi_bresp;
+ wire s00_axi_bvalid;
+ wire [7:0]s00_axi_rdata;
+ wire s00_axi_rready;
+ wire s00_axi_rvalid;
+ wire [3:0]s00_axi_wdata;
+ wire s00_axi_wready;
+ wire s00_axi_wvalid;
+ wire \s_addr[2]_i_1_n_0 ;
+ wire \s_addr[3]_i_1_n_0 ;
+ wire \s_addr[4]_i_1_n_0 ;
+ wire s_arready_i_1_n_0;
+ wire s_awready_i_1_n_0;
+ wire \s_bresp[1]_i_1_n_0 ;
+ wire s_bvalid;
+ wire s_bvalid_i_1_n_0;
+ wire s_rvalid;
+ wire s_rvalid_i_1_n_0;
+ wire s_we_r_i_1_n_0;
+ wire s_wready_i_1_n_0;
+ wire wb_ack_i;
+ wire [2:0]wb_adr_o;
+ wire wb_cyc_o;
+ wire [7:0]\wb_dat_o_reg[7] ;
+ wire wb_rst_o;
+ wire wb_we_o;
+
+ LUT6 #(
+ .INIT(64'hFFFF0008FFFFFFFF))
+ \cr[2]_i_2
+ (.I0(wb_adr_o[2]),
+ .I1(Q),
+ .I2(wb_adr_o[1]),
+ .I3(wb_adr_o[0]),
+ .I4(\cr[2]_i_3_n_0 ),
+ .I5(s00_axi_aresetn),
+ .O(\cr_reg[2] ));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT2 #(
+ .INIT(4'h7))
+ \cr[2]_i_3
+ (.I0(wb_we_o),
+ .I1(wb_ack_i),
+ .O(\cr[2]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT4 #(
+ .INIT(16'h8000))
+ \cr[4]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[0]),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .O(D[0]));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT4 #(
+ .INIT(16'h8000))
+ \cr[5]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[1]),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .O(D[1]));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT4 #(
+ .INIT(16'h8000))
+ \cr[6]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[2]),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .O(D[2]));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT4 #(
+ .INIT(16'h8000))
+ \cr[7]_i_2
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[3]),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .O(D[3]));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFF7FFF))
+ \cr[7]_i_3
+ (.I0(wb_ack_i),
+ .I1(wb_we_o),
+ .I2(wb_adr_o[2]),
+ .I3(Q),
+ .I4(wb_adr_o[1]),
+ .I5(wb_adr_o[0]),
+ .O(\cr_reg[4] ));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT5 #(
+ .INIT(32'h0080FFFF))
+ \ctr[7]_i_1
+ (.I0(wb_we_o),
+ .I1(wb_ack_i),
+ .I2(wb_adr_o[1]),
+ .I3(wb_adr_o[0]),
+ .I4(s00_axi_aresetn),
+ .O(\ctr_reg[0] ));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT2 #(
+ .INIT(4'h2))
+ iack_o_i_1
+ (.I0(wb_cyc_o),
+ .I1(wb_ack_i),
+ .O(iack_o_reg));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT5 #(
+ .INIT(32'h75555555))
+ \prer[15]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(wb_adr_o[1]),
+ .I2(wb_ack_i),
+ .I3(wb_we_o),
+ .I4(wb_adr_o[0]),
+ .O(\prer_reg[8] [1]));
+ LUT6 #(
+ .INIT(64'h5555555557555555))
+ \prer[7]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(wb_adr_o[1]),
+ .I2(wb_adr_o[2]),
+ .I3(wb_ack_i),
+ .I4(wb_we_o),
+ .I5(wb_adr_o[0]),
+ .O(\prer_reg[8] [0]));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT2 #(
+ .INIT(4'h8))
+ s00_axi_bvalid_INST_0
+ (.I0(s_bvalid),
+ .I1(wb_we_o),
+ .O(s00_axi_bvalid));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT2 #(
+ .INIT(4'h2))
+ s00_axi_rvalid_INST_0
+ (.I0(s_rvalid),
+ .I1(wb_we_o),
+ .O(s00_axi_rvalid));
+ LUT5 #(
+ .INIT(32'hAACFAAC0))
+ \s_addr[2]_i_1
+ (.I0(s00_axi_araddr[0]),
+ .I1(s00_axi_awaddr[0]),
+ .I2(s00_axi_awvalid),
+ .I3(s00_axi_arvalid),
+ .I4(wb_adr_o[0]),
+ .O(\s_addr[2]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hAACFAAC0))
+ \s_addr[3]_i_1
+ (.I0(s00_axi_araddr[1]),
+ .I1(s00_axi_awaddr[1]),
+ .I2(s00_axi_awvalid),
+ .I3(s00_axi_arvalid),
+ .I4(wb_adr_o[1]),
+ .O(\s_addr[3]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hAACFAAC0))
+ \s_addr[4]_i_1
+ (.I0(s00_axi_araddr[2]),
+ .I1(s00_axi_awaddr[2]),
+ .I2(s00_axi_awvalid),
+ .I3(s00_axi_arvalid),
+ .I4(wb_adr_o[2]),
+ .O(\s_addr[4]_i_1_n_0 ));
+ FDRE #(
+ .INIT(1'b0))
+ \s_addr_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\s_addr[2]_i_1_n_0 ),
+ .Q(wb_adr_o[0]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_addr_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\s_addr[3]_i_1_n_0 ),
+ .Q(wb_adr_o[1]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_addr_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\s_addr[4]_i_1_n_0 ),
+ .Q(wb_adr_o[2]),
+ .R(wb_rst_o));
+ LUT2 #(
+ .INIT(4'h2))
+ s_arready_i_1
+ (.I0(s00_axi_arvalid),
+ .I1(s00_axi_arready),
+ .O(s_arready_i_1_n_0));
+ FDRE s_arready_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(s_arready_i_1_n_0),
+ .Q(s00_axi_arready),
+ .R(wb_rst_o));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
+ LUT3 #(
+ .INIT(8'h08))
+ s_awready_i_1
+ (.I0(s00_axi_wvalid),
+ .I1(s00_axi_awvalid),
+ .I2(s00_axi_awready),
+ .O(s_awready_i_1_n_0));
+ FDRE s_awready_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(s_awready_i_1_n_0),
+ .Q(s00_axi_awready),
+ .R(wb_rst_o));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT5 #(
+ .INIT(32'hFF7F0000))
+ \s_bresp[1]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(wb_we_o),
+ .I2(wb_ack_i),
+ .I3(s_bvalid),
+ .I4(s00_axi_bresp),
+ .O(\s_bresp[1]_i_1_n_0 ));
+ FDRE #(
+ .INIT(1'b0))
+ \s_bresp_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\s_bresp[1]_i_1_n_0 ),
+ .Q(s00_axi_bresp),
+ .R(1'b0));
+ LUT4 #(
+ .INIT(16'h0F88))
+ s_bvalid_i_1
+ (.I0(wb_we_o),
+ .I1(wb_ack_i),
+ .I2(s00_axi_bready),
+ .I3(s_bvalid),
+ .O(s_bvalid_i_1_n_0));
+ FDRE s_bvalid_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(s_bvalid_i_1_n_0),
+ .Q(s_bvalid),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [0]),
+ .Q(s00_axi_rdata[0]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [1]),
+ .Q(s00_axi_rdata[1]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [2]),
+ .Q(s00_axi_rdata[2]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [3]),
+ .Q(s00_axi_rdata[3]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [4]),
+ .Q(s00_axi_rdata[4]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [5]),
+ .Q(s00_axi_rdata[5]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [6]),
+ .Q(s00_axi_rdata[6]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [7]),
+ .Q(s00_axi_rdata[7]),
+ .R(wb_rst_o));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT4 #(
+ .INIT(16'h4F44))
+ s_rvalid_i_1
+ (.I0(s00_axi_rready),
+ .I1(s_rvalid),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .O(s_rvalid_i_1_n_0));
+ FDRE s_rvalid_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(s_rvalid_i_1_n_0),
+ .Q(s_rvalid),
+ .R(wb_rst_o));
+ FDRE s_stb_r_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(iack_o_reg_0),
+ .Q(wb_cyc_o),
+ .R(wb_rst_o));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT4 #(
+ .INIT(16'h00E0))
+ s_we_r_i_1
+ (.I0(wb_we_o),
+ .I1(s00_axi_awvalid),
+ .I2(s00_axi_aresetn),
+ .I3(s00_axi_arvalid),
+ .O(s_we_r_i_1_n_0));
+ FDRE s_we_r_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(s_we_r_i_1_n_0),
+ .Q(wb_we_o),
+ .R(1'b0));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
+ LUT3 #(
+ .INIT(8'h08))
+ s_wready_i_1
+ (.I0(s00_axi_wvalid),
+ .I1(s00_axi_awvalid),
+ .I2(s00_axi_wready),
+ .O(s_wready_i_1_n_0));
+ FDRE s_wready_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(s_wready_i_1_n_0),
+ .Q(s00_axi_wready),
+ .R(wb_rst_o));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT5 #(
+ .INIT(32'h8000FFFF))
+ \txr[7]_i_1
+ (.I0(wb_we_o),
+ .I1(wb_ack_i),
+ .I2(wb_adr_o[0]),
+ .I3(wb_adr_o[1]),
+ .I4(s00_axi_aresetn),
+ .O(E));
+endmodule
+
+(* ORIG_REF_NAME = "i2c_master_bit_ctrl" *)
+module system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
+ (iscl_oen_reg_0,
+ i2c_scl_t,
+ i2c_sda_t,
+ E,
+ irq_flag1_out,
+ al,
+ D,
+ \statemachine.core_cmd_reg[3] ,
+ \statemachine.ld_reg ,
+ \statemachine.core_txd_reg ,
+ \statemachine.shift_reg ,
+ \statemachine.host_ack_reg ,
+ \statemachine.ack_out_reg ,
+ \cr_reg[4] ,
+ \sr_reg[0] ,
+ \FSM_sequential_statemachine.c_state_reg[2] ,
+ s00_axi_aclk,
+ s00_axi_aresetn,
+ out,
+ \cr_reg[0] ,
+ cmd_ack,
+ irq_flag,
+ Q,
+ \ctr_reg[7] ,
+ i2c_sda_i,
+ i2c_scl_i,
+ \statemachine.core_cmd_reg[3]_0 ,
+ \st_irq_block.al_reg ,
+ \cr_reg[7] ,
+ wb_adr_o,
+ \sr_reg[6] ,
+ \txr_reg[6] ,
+ \FSM_sequential_statemachine.c_state_reg[1] ,
+ core_cmd,
+ \FSM_sequential_statemachine.c_state_reg[1]_0 ,
+ cnt_done,
+ ack_out,
+ iack_o_reg,
+ wb_we_o,
+ iack_o_reg_0,
+ \statemachine.ld_reg_0 ,
+ \FSM_sequential_statemachine.c_state_reg[1]_1 ,
+ \FSM_sequential_statemachine.c_state_reg[1]_2 ,
+ ack_in,
+ \sr_reg[7] ,
+ \cr_reg[7]_0 ,
+ \statemachine.core_txd_reg_0 );
+ output iscl_oen_reg_0;
+ output i2c_scl_t;
+ output i2c_sda_t;
+ output [0:0]E;
+ output irq_flag1_out;
+ output al;
+ output [0:0]D;
+ output [3:0]\statemachine.core_cmd_reg[3] ;
+ output \statemachine.ld_reg ;
+ output \statemachine.core_txd_reg ;
+ output \statemachine.shift_reg ;
+ output \statemachine.host_ack_reg ;
+ output \statemachine.ack_out_reg ;
+ output [0:0]\cr_reg[4] ;
+ output [0:0]\sr_reg[0] ;
+ output [2:0]\FSM_sequential_statemachine.c_state_reg[2] ;
+ input s00_axi_aclk;
+ input s00_axi_aresetn;
+ input [2:0]out;
+ input \cr_reg[0] ;
+ input cmd_ack;
+ input irq_flag;
+ input [15:0]Q;
+ input [0:0]\ctr_reg[7] ;
+ input i2c_sda_i;
+ input i2c_scl_i;
+ input [3:0]\statemachine.core_cmd_reg[3]_0 ;
+ input \st_irq_block.al_reg ;
+ input [3:0]\cr_reg[7] ;
+ input [2:0]wb_adr_o;
+ input \sr_reg[6] ;
+ input [1:0]\txr_reg[6] ;
+ input \FSM_sequential_statemachine.c_state_reg[1] ;
+ input [0:0]core_cmd;
+ input \FSM_sequential_statemachine.c_state_reg[1]_0 ;
+ input cnt_done;
+ input ack_out;
+ input iack_o_reg;
+ input wb_we_o;
+ input iack_o_reg_0;
+ input \statemachine.ld_reg_0 ;
+ input \FSM_sequential_statemachine.c_state_reg[1]_1 ;
+ input \FSM_sequential_statemachine.c_state_reg[1]_2 ;
+ input ack_in;
+ input [0:0]\sr_reg[7] ;
+ input \cr_reg[7]_0 ;
+ input \statemachine.core_txd_reg_0 ;
+
+ wire [0:0]D;
+ wire [0:0]E;
+ wire \FSM_sequential_c_state[0]_i_1_n_0 ;
+ wire \FSM_sequential_c_state[0]_i_2_n_0 ;
+ wire \FSM_sequential_c_state[1]_i_1_n_0 ;
+ wire \FSM_sequential_c_state[1]_i_2_n_0 ;
+ wire \FSM_sequential_c_state[1]_i_3_n_0 ;
+ wire \FSM_sequential_c_state[2]_i_1_n_0 ;
+ wire \FSM_sequential_c_state[2]_i_2_n_0 ;
+ wire \FSM_sequential_c_state[3]_i_1_n_0 ;
+ wire \FSM_sequential_c_state[3]_i_2_n_0 ;
+ wire \FSM_sequential_c_state[3]_i_3_n_0 ;
+ wire \FSM_sequential_c_state[4]_i_1_n_0 ;
+ wire \FSM_sequential_c_state[4]_i_2_n_0 ;
+ wire \FSM_sequential_c_state[4]_i_3_n_0 ;
+ wire \FSM_sequential_statemachine.c_state[2]_i_3_n_0 ;
+ wire \FSM_sequential_statemachine.c_state_reg[1] ;
+ wire \FSM_sequential_statemachine.c_state_reg[1]_0 ;
+ wire \FSM_sequential_statemachine.c_state_reg[1]_1 ;
+ wire \FSM_sequential_statemachine.c_state_reg[1]_2 ;
+ wire [2:0]\FSM_sequential_statemachine.c_state_reg[2] ;
+ wire [15:0]Q;
+ wire ack_in;
+ wire ack_out;
+ wire al;
+ wire \bus_status_ctrl.cSCL[0]_i_1_n_0 ;
+ wire \bus_status_ctrl.cSCL[1]_i_1_n_0 ;
+ wire \bus_status_ctrl.cSDA[0]_i_1_n_0 ;
+ wire \bus_status_ctrl.cSDA[1]_i_1_n_0 ;
+ wire \bus_status_ctrl.cSDA_reg_n_0_[1] ;
+ wire \bus_status_ctrl.cmd_stop_i_1_n_0 ;
+ wire \bus_status_ctrl.cmd_stop_i_2_n_0 ;
+ wire \bus_status_ctrl.cmd_stop_reg_n_0 ;
+ wire \bus_status_ctrl.dSCL_i_1_n_0 ;
+ wire \bus_status_ctrl.dSDA_i_1_n_0 ;
+ wire \bus_status_ctrl.dout_i_1_n_0 ;
+ wire \bus_status_ctrl.fSCL[0]_i_1_n_0 ;
+ wire \bus_status_ctrl.fSCL[1]_i_1_n_0 ;
+ wire \bus_status_ctrl.fSCL[2]_i_1_n_0 ;
+ wire \bus_status_ctrl.fSCL_reg_n_0_[2] ;
+ wire \bus_status_ctrl.fSDA[0]_i_1_n_0 ;
+ wire \bus_status_ctrl.fSDA[1]_i_1_n_0 ;
+ wire \bus_status_ctrl.fSDA[2]_i_1_n_0 ;
+ wire \bus_status_ctrl.fSDA[2]_i_2_n_0 ;
+ wire \bus_status_ctrl.fSDA_reg_n_0_[0] ;
+ wire \bus_status_ctrl.fSDA_reg_n_0_[1] ;
+ wire \bus_status_ctrl.fSDA_reg_n_0_[2] ;
+ wire \bus_status_ctrl.filter_cnt[0]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[10]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[11]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[12]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[13]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[13]_i_2_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[13]_i_3_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[13]_i_4_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[1]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[2]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[3]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[4]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[5]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[6]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[7]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[8]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[9]_i_1_n_0 ;
+ wire \bus_status_ctrl.ial_i_2_n_0 ;
+ wire \bus_status_ctrl.ial_i_3_n_0 ;
+ wire \bus_status_ctrl.sSCL_i_1_n_0 ;
+ wire \bus_status_ctrl.sSDA_i_1_n_0 ;
+ wire \bus_status_ctrl.sta_condition_reg_n_0 ;
+ wire \bus_status_ctrl.sto_condition_reg_n_0 ;
+ (* RTL_KEEP = "yes" *) wire [4:0]c_state;
+ wire clk_en;
+ wire clk_en_i_2_n_0;
+ wire clk_en_i_3_n_0;
+ wire clk_en_i_4_n_0;
+ wire clk_en_i_5_n_0;
+ wire clk_en_i_6_n_0;
+ wire cmd_ack;
+ wire cmd_ack3_out;
+ wire cmd_ack_i_2_n_0;
+ wire cnt1;
+ wire \cnt[0]_i_10_n_0 ;
+ wire \cnt[0]_i_1_n_0 ;
+ wire \cnt[0]_i_3_n_0 ;
+ wire \cnt[0]_i_4_n_0 ;
+ wire \cnt[0]_i_5_n_0 ;
+ wire \cnt[0]_i_6_n_0 ;
+ wire \cnt[0]_i_7_n_0 ;
+ wire \cnt[0]_i_8_n_0 ;
+ wire \cnt[0]_i_9_n_0 ;
+ wire \cnt[12]_i_2_n_0 ;
+ wire \cnt[12]_i_3_n_0 ;
+ wire \cnt[12]_i_4_n_0 ;
+ wire \cnt[12]_i_5_n_0 ;
+ wire \cnt[12]_i_6_n_0 ;
+ wire \cnt[12]_i_7_n_0 ;
+ wire \cnt[12]_i_8_n_0 ;
+ wire \cnt[4]_i_2_n_0 ;
+ wire \cnt[4]_i_3_n_0 ;
+ wire \cnt[4]_i_4_n_0 ;
+ wire \cnt[4]_i_5_n_0 ;
+ wire \cnt[4]_i_6_n_0 ;
+ wire \cnt[4]_i_7_n_0 ;
+ wire \cnt[4]_i_8_n_0 ;
+ wire \cnt[4]_i_9_n_0 ;
+ wire \cnt[8]_i_2_n_0 ;
+ wire \cnt[8]_i_3_n_0 ;
+ wire \cnt[8]_i_4_n_0 ;
+ wire \cnt[8]_i_5_n_0 ;
+ wire \cnt[8]_i_6_n_0 ;
+ wire \cnt[8]_i_7_n_0 ;
+ wire \cnt[8]_i_8_n_0 ;
+ wire \cnt[8]_i_9_n_0 ;
+ wire cnt_done;
+ wire [15:0]cnt_reg;
+ wire \cnt_reg[0]_i_2_n_0 ;
+ wire \cnt_reg[0]_i_2_n_1 ;
+ wire \cnt_reg[0]_i_2_n_2 ;
+ wire \cnt_reg[0]_i_2_n_3 ;
+ wire \cnt_reg[0]_i_2_n_4 ;
+ wire \cnt_reg[0]_i_2_n_5 ;
+ wire \cnt_reg[0]_i_2_n_6 ;
+ wire \cnt_reg[0]_i_2_n_7 ;
+ wire \cnt_reg[12]_i_1_n_1 ;
+ wire \cnt_reg[12]_i_1_n_2 ;
+ wire \cnt_reg[12]_i_1_n_3 ;
+ wire \cnt_reg[12]_i_1_n_4 ;
+ wire \cnt_reg[12]_i_1_n_5 ;
+ wire \cnt_reg[12]_i_1_n_6 ;
+ wire \cnt_reg[12]_i_1_n_7 ;
+ wire \cnt_reg[4]_i_1_n_0 ;
+ wire \cnt_reg[4]_i_1_n_1 ;
+ wire \cnt_reg[4]_i_1_n_2 ;
+ wire \cnt_reg[4]_i_1_n_3 ;
+ wire \cnt_reg[4]_i_1_n_4 ;
+ wire \cnt_reg[4]_i_1_n_5 ;
+ wire \cnt_reg[4]_i_1_n_6 ;
+ wire \cnt_reg[4]_i_1_n_7 ;
+ wire \cnt_reg[8]_i_1_n_0 ;
+ wire \cnt_reg[8]_i_1_n_1 ;
+ wire \cnt_reg[8]_i_1_n_2 ;
+ wire \cnt_reg[8]_i_1_n_3 ;
+ wire \cnt_reg[8]_i_1_n_4 ;
+ wire \cnt_reg[8]_i_1_n_5 ;
+ wire \cnt_reg[8]_i_1_n_6 ;
+ wire \cnt_reg[8]_i_1_n_7 ;
+ wire core_ack;
+ wire [0:0]core_cmd;
+ wire core_rxd;
+ wire core_txd;
+ wire \cr_reg[0] ;
+ wire [0:0]\cr_reg[4] ;
+ wire [3:0]\cr_reg[7] ;
+ wire \cr_reg[7]_0 ;
+ wire [0:0]\ctr_reg[7] ;
+ wire dSCL;
+ wire dSDA;
+ wire dscl_oen;
+ wire [13:0]filter_cnt;
+ wire i2c_al;
+ wire i2c_busy;
+ wire i2c_scl_i;
+ wire i2c_scl_t;
+ wire i2c_sda_i;
+ wire i2c_sda_t;
+ wire iack_o_reg;
+ wire iack_o_reg_0;
+ wire ial;
+ wire ibusy;
+ wire irq_flag;
+ wire irq_flag1_out;
+ wire iscl_oen;
+ wire iscl_oen9_out__0;
+ wire iscl_oen_i_1_n_0;
+ wire iscl_oen_reg_0;
+ wire isda_oen;
+ wire isda_oen7_out__0;
+ wire isda_oen_i_1_n_0;
+ wire minusOp_carry__0_i_1_n_0;
+ wire minusOp_carry__0_i_2_n_0;
+ wire minusOp_carry__0_i_3_n_0;
+ wire minusOp_carry__0_i_4_n_0;
+ wire minusOp_carry__0_n_0;
+ wire minusOp_carry__0_n_1;
+ wire minusOp_carry__0_n_2;
+ wire minusOp_carry__0_n_3;
+ wire minusOp_carry__0_n_4;
+ wire minusOp_carry__0_n_5;
+ wire minusOp_carry__0_n_6;
+ wire minusOp_carry__0_n_7;
+ wire minusOp_carry__1_i_1_n_0;
+ wire minusOp_carry__1_i_2_n_0;
+ wire minusOp_carry__1_i_3_n_0;
+ wire minusOp_carry__1_i_4_n_0;
+ wire minusOp_carry__1_n_0;
+ wire minusOp_carry__1_n_1;
+ wire minusOp_carry__1_n_2;
+ wire minusOp_carry__1_n_3;
+ wire minusOp_carry__1_n_4;
+ wire minusOp_carry__1_n_5;
+ wire minusOp_carry__1_n_6;
+ wire minusOp_carry__1_n_7;
+ wire minusOp_carry__2_i_1_n_0;
+ wire minusOp_carry__2_n_7;
+ wire minusOp_carry_i_1_n_0;
+ wire minusOp_carry_i_2_n_0;
+ wire minusOp_carry_i_3_n_0;
+ wire minusOp_carry_i_4_n_0;
+ wire minusOp_carry_n_0;
+ wire minusOp_carry_n_1;
+ wire minusOp_carry_n_2;
+ wire minusOp_carry_n_3;
+ wire minusOp_carry_n_4;
+ wire minusOp_carry_n_5;
+ wire minusOp_carry_n_6;
+ wire minusOp_carry_n_7;
+ wire [2:0]out;
+ wire [1:1]p_0_in;
+ wire [1:1]p_0_in__0;
+ wire [2:0]p_0_in__1;
+ wire s00_axi_aclk;
+ wire s00_axi_aresetn;
+ wire sSCL;
+ wire sSDA;
+ wire sda_chk_i_1_n_0;
+ wire sda_chk_reg_n_0;
+ wire slave_wait;
+ wire slave_wait0;
+ wire [0:0]\sr_reg[0] ;
+ wire \sr_reg[6] ;
+ wire [0:0]\sr_reg[7] ;
+ wire \st_irq_block.al_reg ;
+ wire sta_condition;
+ wire \statemachine.ack_out_i_2_n_0 ;
+ wire \statemachine.ack_out_reg ;
+ wire [3:0]\statemachine.core_cmd_reg[3] ;
+ wire [3:0]\statemachine.core_cmd_reg[3]_0 ;
+ wire \statemachine.core_txd_reg ;
+ wire \statemachine.core_txd_reg_0 ;
+ wire \statemachine.host_ack_reg ;
+ wire \statemachine.ld_reg ;
+ wire \statemachine.ld_reg_0 ;
+ wire \statemachine.shift_reg ;
+ wire sto_condition;
+ wire [1:0]\txr_reg[6] ;
+ wire [2:0]wb_adr_o;
+ wire \wb_dat_o[6]_i_3_n_0 ;
+ wire wb_we_o;
+ wire [3:3]\NLW_cnt_reg[12]_i_1_CO_UNCONNECTED ;
+ wire [3:0]NLW_minusOp_carry__2_CO_UNCONNECTED;
+ wire [3:1]NLW_minusOp_carry__2_O_UNCONNECTED;
+
+ LUT6 #(
+ .INIT(64'h1111111111111110))
+ \FSM_sequential_c_state[0]_i_1
+ (.I0(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .I1(c_state[0]),
+ .I2(c_state[2]),
+ .I3(c_state[3]),
+ .I4(\FSM_sequential_c_state[0]_i_2_n_0 ),
+ .I5(c_state[4]),
+ .O(\FSM_sequential_c_state[0]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hAAAAAABA))
+ \FSM_sequential_c_state[0]_i_2
+ (.I0(c_state[1]),
+ .I1(\statemachine.core_cmd_reg[3]_0 [1]),
+ .I2(\statemachine.core_cmd_reg[3]_0 [0]),
+ .I3(\statemachine.core_cmd_reg[3]_0 [3]),
+ .I4(\statemachine.core_cmd_reg[3]_0 [2]),
+ .O(\FSM_sequential_c_state[0]_i_2_n_0 ));
+ LUT4 #(
+ .INIT(16'h0400))
+ \FSM_sequential_c_state[1]_i_1
+ (.I0(i2c_al),
+ .I1(s00_axi_aresetn),
+ .I2(c_state[4]),
+ .I3(\FSM_sequential_c_state[1]_i_2_n_0 ),
+ .O(\FSM_sequential_c_state[1]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'hEEEFEFFE44444444))
+ \FSM_sequential_c_state[1]_i_2
+ (.I0(c_state[0]),
+ .I1(c_state[1]),
+ .I2(\statemachine.core_cmd_reg[3]_0 [1]),
+ .I3(\statemachine.core_cmd_reg[3]_0 [2]),
+ .I4(\statemachine.core_cmd_reg[3]_0 [3]),
+ .I5(\FSM_sequential_c_state[1]_i_3_n_0 ),
+ .O(\FSM_sequential_c_state[1]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'h00001101))
+ \FSM_sequential_c_state[1]_i_3
+ (.I0(c_state[2]),
+ .I1(c_state[1]),
+ .I2(\statemachine.core_cmd_reg[3]_0 [0]),
+ .I3(c_state[0]),
+ .I4(c_state[3]),
+ .O(\FSM_sequential_c_state[1]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'h0002A0A2AAAA0002))
+ \FSM_sequential_c_state[2]_i_1
+ (.I0(\FSM_sequential_c_state[3]_i_2_n_0 ),
+ .I1(c_state[3]),
+ .I2(c_state[1]),
+ .I3(\FSM_sequential_c_state[2]_i_2_n_0 ),
+ .I4(c_state[2]),
+ .I5(c_state[0]),
+ .O(\FSM_sequential_c_state[2]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hFFFFFEEF))
+ \FSM_sequential_c_state[2]_i_2
+ (.I0(c_state[0]),
+ .I1(\statemachine.core_cmd_reg[3]_0 [3]),
+ .I2(\statemachine.core_cmd_reg[3]_0 [1]),
+ .I3(\statemachine.core_cmd_reg[3]_0 [2]),
+ .I4(\statemachine.core_cmd_reg[3]_0 [0]),
+ .O(\FSM_sequential_c_state[2]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0AA8A0A800A800A8))
+ \FSM_sequential_c_state[3]_i_1
+ (.I0(\FSM_sequential_c_state[3]_i_2_n_0 ),
+ .I1(\FSM_sequential_c_state[3]_i_3_n_0 ),
+ .I2(c_state[3]),
+ .I3(c_state[0]),
+ .I4(c_state[2]),
+ .I5(c_state[1]),
+ .O(\FSM_sequential_c_state[3]_i_1_n_0 ));
+ LUT3 #(
+ .INIT(8'h04))
+ \FSM_sequential_c_state[3]_i_2
+ (.I0(c_state[4]),
+ .I1(s00_axi_aresetn),
+ .I2(i2c_al),
+ .O(\FSM_sequential_c_state[3]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000006))
+ \FSM_sequential_c_state[3]_i_3
+ (.I0(\statemachine.core_cmd_reg[3]_0 [3]),
+ .I1(\statemachine.core_cmd_reg[3]_0 [2]),
+ .I2(\statemachine.core_cmd_reg[3]_0 [0]),
+ .I3(\statemachine.core_cmd_reg[3]_0 [1]),
+ .I4(c_state[1]),
+ .I5(c_state[2]),
+ .O(\FSM_sequential_c_state[3]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hBBBBBBBFAAAAAAAA))
+ \FSM_sequential_c_state[4]_i_1
+ (.I0(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .I1(c_state[4]),
+ .I2(c_state[3]),
+ .I3(c_state[1]),
+ .I4(c_state[2]),
+ .I5(clk_en),
+ .O(\FSM_sequential_c_state[4]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000080FF8000))
+ \FSM_sequential_c_state[4]_i_2
+ (.I0(c_state[3]),
+ .I1(c_state[1]),
+ .I2(c_state[2]),
+ .I3(c_state[0]),
+ .I4(c_state[4]),
+ .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .O(\FSM_sequential_c_state[4]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \FSM_sequential_c_state[4]_i_3
+ (.I0(i2c_al),
+ .I1(s00_axi_aresetn),
+ .O(\FSM_sequential_c_state[4]_i_3_n_0 ));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_c_state_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\FSM_sequential_c_state[0]_i_1_n_0 ),
+ .Q(c_state[0]));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_c_state_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\FSM_sequential_c_state[1]_i_1_n_0 ),
+ .Q(c_state[1]));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_c_state_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\FSM_sequential_c_state[2]_i_1_n_0 ),
+ .Q(c_state[2]));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_c_state_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\FSM_sequential_c_state[3]_i_1_n_0 ),
+ .Q(c_state[3]));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_c_state_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\FSM_sequential_c_state[4]_i_2_n_0 ),
+ .Q(c_state[4]));
+ LUT6 #(
+ .INIT(64'h0000000022222E22))
+ \FSM_sequential_statemachine.c_state[0]_i_1
+ (.I0(\FSM_sequential_statemachine.c_state_reg[1]_1 ),
+ .I1(out[2]),
+ .I2(out[1]),
+ .I3(\cr_reg[7] [2]),
+ .I4(out[0]),
+ .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .O(\FSM_sequential_statemachine.c_state_reg[2] [0]));
+ LUT6 #(
+ .INIT(64'h0000000015100000))
+ \FSM_sequential_statemachine.c_state[1]_i_1
+ (.I0(out[2]),
+ .I1(cnt_done),
+ .I2(out[1]),
+ .I3(\cr_reg[7]_0 ),
+ .I4(s00_axi_aresetn),
+ .I5(i2c_al),
+ .O(\FSM_sequential_statemachine.c_state_reg[2] [1]));
+ LUT6 #(
+ .INIT(64'hDDFFDDDDFFFDDDFD))
+ \FSM_sequential_statemachine.c_state[2]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(i2c_al),
+ .I2(\FSM_sequential_statemachine.c_state[2]_i_3_n_0 ),
+ .I3(out[1]),
+ .I4(core_ack),
+ .I5(out[2]),
+ .O(E));
+ LUT6 #(
+ .INIT(64'h0000000022222E22))
+ \FSM_sequential_statemachine.c_state[2]_i_2
+ (.I0(\FSM_sequential_statemachine.c_state_reg[1]_2 ),
+ .I1(out[2]),
+ .I2(out[1]),
+ .I3(\cr_reg[7] [2]),
+ .I4(out[0]),
+ .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .O(\FSM_sequential_statemachine.c_state_reg[2] [2]));
+ LUT6 #(
+ .INIT(64'h8B8B8B8B8B8B8B88))
+ \FSM_sequential_statemachine.c_state[2]_i_3
+ (.I0(core_ack),
+ .I1(out[0]),
+ .I2(cmd_ack),
+ .I3(\cr_reg[7] [0]),
+ .I4(\cr_reg[7] [1]),
+ .I5(\cr_reg[7] [2]),
+ .O(\FSM_sequential_statemachine.c_state[2]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \bus_status_ctrl.cSCL[0]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(i2c_scl_i),
+ .O(\bus_status_ctrl.cSCL[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \bus_status_ctrl.cSCL[1]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(p_0_in__0),
+ .O(\bus_status_ctrl.cSCL[1]_i_1_n_0 ));
+ FDCE \bus_status_ctrl.cSCL_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.cSCL[0]_i_1_n_0 ),
+ .Q(p_0_in__0));
+ FDCE \bus_status_ctrl.cSCL_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.cSCL[1]_i_1_n_0 ),
+ .Q(p_0_in__1[0]));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \bus_status_ctrl.cSDA[0]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(i2c_sda_i),
+ .O(\bus_status_ctrl.cSDA[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \bus_status_ctrl.cSDA[1]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(p_0_in),
+ .O(\bus_status_ctrl.cSDA[1]_i_1_n_0 ));
+ FDCE \bus_status_ctrl.cSDA_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.cSDA[0]_i_1_n_0 ),
+ .Q(p_0_in));
+ FDCE \bus_status_ctrl.cSDA_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.cSDA[1]_i_1_n_0 ),
+ .Q(\bus_status_ctrl.cSDA_reg_n_0_[1] ));
+ LUT6 #(
+ .INIT(64'h04FF000004000000))
+ \bus_status_ctrl.cmd_stop_i_1
+ (.I0(\statemachine.core_cmd_reg[3]_0 [0]),
+ .I1(\statemachine.core_cmd_reg[3]_0 [1]),
+ .I2(\bus_status_ctrl.cmd_stop_i_2_n_0 ),
+ .I3(clk_en),
+ .I4(s00_axi_aresetn),
+ .I5(\bus_status_ctrl.cmd_stop_reg_n_0 ),
+ .O(\bus_status_ctrl.cmd_stop_i_1_n_0 ));
+ LUT2 #(
+ .INIT(4'hE))
+ \bus_status_ctrl.cmd_stop_i_2
+ (.I0(\statemachine.core_cmd_reg[3]_0 [2]),
+ .I1(\statemachine.core_cmd_reg[3]_0 [3]),
+ .O(\bus_status_ctrl.cmd_stop_i_2_n_0 ));
+ FDCE \bus_status_ctrl.cmd_stop_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.cmd_stop_i_1_n_0 ),
+ .Q(\bus_status_ctrl.cmd_stop_reg_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.dSCL_i_1
+ (.I0(sSCL),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.dSCL_i_1_n_0 ));
+ FDPE \bus_status_ctrl.dSCL_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\bus_status_ctrl.dSCL_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(dSCL));
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.dSDA_i_1
+ (.I0(sSDA),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.dSDA_i_1_n_0 ));
+ FDPE \bus_status_ctrl.dSDA_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\bus_status_ctrl.dSDA_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(dSDA));
+ LUT4 #(
+ .INIT(16'hFB08))
+ \bus_status_ctrl.dout_i_1
+ (.I0(sSDA),
+ .I1(sSCL),
+ .I2(dSCL),
+ .I3(core_rxd),
+ .O(\bus_status_ctrl.dout_i_1_n_0 ));
+ FDCE \bus_status_ctrl.dout_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.dout_i_1_n_0 ),
+ .Q(core_rxd));
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.fSCL[0]_i_1
+ (.I0(p_0_in__1[0]),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.fSCL[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.fSCL[1]_i_1
+ (.I0(p_0_in__1[1]),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.fSCL[1]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.fSCL[2]_i_1
+ (.I0(p_0_in__1[2]),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.fSCL[2]_i_1_n_0 ));
+ FDPE \bus_status_ctrl.fSCL_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
+ .D(\bus_status_ctrl.fSCL[0]_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(p_0_in__1[1]));
+ FDPE \bus_status_ctrl.fSCL_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
+ .D(\bus_status_ctrl.fSCL[1]_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(p_0_in__1[2]));
+ FDPE \bus_status_ctrl.fSCL_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
+ .D(\bus_status_ctrl.fSCL[2]_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(\bus_status_ctrl.fSCL_reg_n_0_[2] ));
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.fSDA[0]_i_1
+ (.I0(\bus_status_ctrl.cSDA_reg_n_0_[1] ),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.fSDA[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.fSDA[1]_i_1
+ (.I0(\bus_status_ctrl.fSDA_reg_n_0_[0] ),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.fSDA[1]_i_1_n_0 ));
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.fSDA[2]_i_1
+ (.I0(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.fSDA[2]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.fSDA[2]_i_2
+ (.I0(\bus_status_ctrl.fSDA_reg_n_0_[1] ),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.fSDA[2]_i_2_n_0 ));
+ FDPE \bus_status_ctrl.fSDA_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
+ .D(\bus_status_ctrl.fSDA[0]_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(\bus_status_ctrl.fSDA_reg_n_0_[0] ));
+ FDPE \bus_status_ctrl.fSDA_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
+ .D(\bus_status_ctrl.fSDA[1]_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(\bus_status_ctrl.fSDA_reg_n_0_[1] ));
+ FDPE \bus_status_ctrl.fSDA_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
+ .D(\bus_status_ctrl.fSDA[2]_i_2_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(\bus_status_ctrl.fSDA_reg_n_0_[2] ));
+ LUT5 #(
+ .INIT(32'hD1000000))
+ \bus_status_ctrl.filter_cnt[0]_i_1
+ (.I0(filter_cnt[0]),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[2]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[0]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[10]_i_1
+ (.I0(minusOp_carry__1_n_6),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[12]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[10]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[11]_i_1
+ (.I0(minusOp_carry__1_n_5),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[13]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[11]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[12]_i_1
+ (.I0(minusOp_carry__1_n_4),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[14]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[12]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[13]_i_1
+ (.I0(minusOp_carry__2_n_7),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[15]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[13]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000001))
+ \bus_status_ctrl.filter_cnt[13]_i_2
+ (.I0(\bus_status_ctrl.filter_cnt[13]_i_3_n_0 ),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_4_n_0 ),
+ .I2(filter_cnt[6]),
+ .I3(filter_cnt[7]),
+ .I4(filter_cnt[4]),
+ .I5(filter_cnt[5]),
+ .O(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFFFFFE))
+ \bus_status_ctrl.filter_cnt[13]_i_3
+ (.I0(filter_cnt[13]),
+ .I1(filter_cnt[12]),
+ .I2(filter_cnt[9]),
+ .I3(filter_cnt[8]),
+ .I4(filter_cnt[11]),
+ .I5(filter_cnt[10]),
+ .O(\bus_status_ctrl.filter_cnt[13]_i_3_n_0 ));
+ LUT4 #(
+ .INIT(16'hFFFE))
+ \bus_status_ctrl.filter_cnt[13]_i_4
+ (.I0(filter_cnt[2]),
+ .I1(filter_cnt[3]),
+ .I2(filter_cnt[0]),
+ .I3(filter_cnt[1]),
+ .O(\bus_status_ctrl.filter_cnt[13]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[1]_i_1
+ (.I0(minusOp_carry_n_7),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[3]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[1]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[2]_i_1
+ (.I0(minusOp_carry_n_6),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[4]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[2]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[3]_i_1
+ (.I0(minusOp_carry_n_5),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[5]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[3]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[4]_i_1
+ (.I0(minusOp_carry_n_4),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[6]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[4]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[5]_i_1
+ (.I0(minusOp_carry__0_n_7),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[7]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[5]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[6]_i_1
+ (.I0(minusOp_carry__0_n_6),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[8]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[6]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[7]_i_1
+ (.I0(minusOp_carry__0_n_5),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[9]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[7]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[8]_i_1
+ (.I0(minusOp_carry__0_n_4),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[10]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[8]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[9]_i_1
+ (.I0(minusOp_carry__1_n_7),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[11]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[9]_i_1_n_0 ));
+ FDCE \bus_status_ctrl.filter_cnt_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[0]_i_1_n_0 ),
+ .Q(filter_cnt[0]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[10]_i_1_n_0 ),
+ .Q(filter_cnt[10]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[11]_i_1_n_0 ),
+ .Q(filter_cnt[11]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[12]_i_1_n_0 ),
+ .Q(filter_cnt[12]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[13]_i_1_n_0 ),
+ .Q(filter_cnt[13]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[1]_i_1_n_0 ),
+ .Q(filter_cnt[1]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[2]_i_1_n_0 ),
+ .Q(filter_cnt[2]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[3]_i_1_n_0 ),
+ .Q(filter_cnt[3]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[4]_i_1_n_0 ),
+ .Q(filter_cnt[4]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[5]_i_1_n_0 ),
+ .Q(filter_cnt[5]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[6]_i_1_n_0 ),
+ .Q(filter_cnt[6]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[7]_i_1_n_0 ),
+ .Q(filter_cnt[7]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[8]_i_1_n_0 ),
+ .Q(filter_cnt[8]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[9]_i_1_n_0 ),
+ .Q(filter_cnt[9]));
+ LUT6 #(
+ .INIT(64'h08000800AAAA0800))
+ \bus_status_ctrl.ial_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(sda_chk_reg_n_0),
+ .I2(sSDA),
+ .I3(i2c_sda_t),
+ .I4(\bus_status_ctrl.ial_i_2_n_0 ),
+ .I5(\bus_status_ctrl.ial_i_3_n_0 ),
+ .O(ial));
+ LUT2 #(
+ .INIT(4'h1))
+ \bus_status_ctrl.ial_i_2
+ (.I0(c_state[0]),
+ .I1(c_state[4]),
+ .O(\bus_status_ctrl.ial_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hFFFFFFEF))
+ \bus_status_ctrl.ial_i_3
+ (.I0(c_state[2]),
+ .I1(c_state[3]),
+ .I2(\bus_status_ctrl.sto_condition_reg_n_0 ),
+ .I3(\bus_status_ctrl.cmd_stop_reg_n_0 ),
+ .I4(c_state[1]),
+ .O(\bus_status_ctrl.ial_i_3_n_0 ));
+ FDCE \bus_status_ctrl.ial_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(ial),
+ .Q(i2c_al));
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
+ LUT4 #(
+ .INIT(16'h5400))
+ \bus_status_ctrl.ibusy_i_1
+ (.I0(\bus_status_ctrl.sto_condition_reg_n_0 ),
+ .I1(\bus_status_ctrl.sta_condition_reg_n_0 ),
+ .I2(i2c_busy),
+ .I3(s00_axi_aresetn),
+ .O(ibusy));
+ FDCE \bus_status_ctrl.ibusy_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(ibusy),
+ .Q(i2c_busy));
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
+ LUT4 #(
+ .INIT(16'hE8FF))
+ \bus_status_ctrl.sSCL_i_1
+ (.I0(p_0_in__1[2]),
+ .I1(\bus_status_ctrl.fSCL_reg_n_0_[2] ),
+ .I2(p_0_in__1[1]),
+ .I3(s00_axi_aresetn),
+ .O(\bus_status_ctrl.sSCL_i_1_n_0 ));
+ FDPE \bus_status_ctrl.sSCL_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\bus_status_ctrl.sSCL_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(sSCL));
+ LUT4 #(
+ .INIT(16'hE8FF))
+ \bus_status_ctrl.sSDA_i_1
+ (.I0(\bus_status_ctrl.fSDA_reg_n_0_[1] ),
+ .I1(\bus_status_ctrl.fSDA_reg_n_0_[2] ),
+ .I2(\bus_status_ctrl.fSDA_reg_n_0_[0] ),
+ .I3(s00_axi_aresetn),
+ .O(\bus_status_ctrl.sSDA_i_1_n_0 ));
+ FDPE \bus_status_ctrl.sSDA_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\bus_status_ctrl.sSDA_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(sSDA));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT4 #(
+ .INIT(16'h2000))
+ \bus_status_ctrl.sta_condition_i_1
+ (.I0(dSDA),
+ .I1(sSDA),
+ .I2(s00_axi_aresetn),
+ .I3(sSCL),
+ .O(sta_condition));
+ FDCE \bus_status_ctrl.sta_condition_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(sta_condition),
+ .Q(\bus_status_ctrl.sta_condition_reg_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT4 #(
+ .INIT(16'h4000))
+ \bus_status_ctrl.sto_condition_i_1
+ (.I0(dSDA),
+ .I1(s00_axi_aresetn),
+ .I2(sSCL),
+ .I3(sSDA),
+ .O(sto_condition));
+ FDCE \bus_status_ctrl.sto_condition_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(sto_condition),
+ .Q(\bus_status_ctrl.sto_condition_reg_n_0 ));
+ LUT5 #(
+ .INIT(32'hAAAAAAAB))
+ clk_en_i_1
+ (.I0(clk_en_i_2_n_0),
+ .I1(clk_en_i_3_n_0),
+ .I2(clk_en_i_4_n_0),
+ .I3(clk_en_i_5_n_0),
+ .I4(clk_en_i_6_n_0),
+ .O(cnt1));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
+ LUT5 #(
+ .INIT(32'h7555FFFF))
+ clk_en_i_2
+ (.I0(\ctr_reg[7] ),
+ .I1(sSCL),
+ .I2(i2c_scl_t),
+ .I3(dSCL),
+ .I4(s00_axi_aresetn),
+ .O(clk_en_i_2_n_0));
+ LUT4 #(
+ .INIT(16'hFFFE))
+ clk_en_i_3
+ (.I0(cnt_reg[6]),
+ .I1(cnt_reg[7]),
+ .I2(cnt_reg[4]),
+ .I3(cnt_reg[5]),
+ .O(clk_en_i_3_n_0));
+ LUT4 #(
+ .INIT(16'hFFFE))
+ clk_en_i_4
+ (.I0(cnt_reg[2]),
+ .I1(cnt_reg[3]),
+ .I2(cnt_reg[0]),
+ .I3(cnt_reg[1]),
+ .O(clk_en_i_4_n_0));
+ LUT4 #(
+ .INIT(16'hFFFE))
+ clk_en_i_5
+ (.I0(cnt_reg[15]),
+ .I1(cnt_reg[14]),
+ .I2(cnt_reg[12]),
+ .I3(cnt_reg[13]),
+ .O(clk_en_i_5_n_0));
+ LUT4 #(
+ .INIT(16'hFFFE))
+ clk_en_i_6
+ (.I0(cnt_reg[10]),
+ .I1(cnt_reg[11]),
+ .I2(cnt_reg[8]),
+ .I3(cnt_reg[9]),
+ .O(clk_en_i_6_n_0));
+ FDPE clk_en_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(cnt1),
+ .PRE(iscl_oen_reg_0),
+ .Q(clk_en));
+ LUT6 #(
+ .INIT(64'h0008000000000000))
+ cmd_ack_i_1
+ (.I0(cmd_ack_i_2_n_0),
+ .I1(c_state[0]),
+ .I2(c_state[1]),
+ .I3(i2c_al),
+ .I4(s00_axi_aresetn),
+ .I5(clk_en),
+ .O(cmd_ack3_out));
+ LUT3 #(
+ .INIT(8'h1E))
+ cmd_ack_i_2
+ (.I0(c_state[2]),
+ .I1(c_state[3]),
+ .I2(c_state[4]),
+ .O(cmd_ack_i_2_n_0));
+ FDCE cmd_ack_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(cmd_ack3_out),
+ .Q(core_ack));
+ LUT2 #(
+ .INIT(4'hB))
+ \cnt[0]_i_1
+ (.I0(cnt1),
+ .I1(slave_wait),
+ .O(\cnt[0]_i_1_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[0]_i_10
+ (.I0(cnt_reg[0]),
+ .I1(Q[0]),
+ .I2(cnt1),
+ .O(\cnt[0]_i_10_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[0]_i_3
+ (.I0(Q[3]),
+ .I1(cnt1),
+ .I2(cnt_reg[3]),
+ .O(\cnt[0]_i_3_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[0]_i_4
+ (.I0(Q[2]),
+ .I1(cnt1),
+ .I2(cnt_reg[2]),
+ .O(\cnt[0]_i_4_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[0]_i_5
+ (.I0(Q[1]),
+ .I1(cnt1),
+ .I2(cnt_reg[1]),
+ .O(\cnt[0]_i_5_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[0]_i_6
+ (.I0(Q[0]),
+ .I1(cnt1),
+ .I2(cnt_reg[0]),
+ .O(\cnt[0]_i_6_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[0]_i_7
+ (.I0(cnt_reg[3]),
+ .I1(Q[3]),
+ .I2(cnt1),
+ .O(\cnt[0]_i_7_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[0]_i_8
+ (.I0(cnt_reg[2]),
+ .I1(Q[2]),
+ .I2(cnt1),
+ .O(\cnt[0]_i_8_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[0]_i_9
+ (.I0(cnt_reg[1]),
+ .I1(Q[1]),
+ .I2(cnt1),
+ .O(\cnt[0]_i_9_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[12]_i_2
+ (.I0(Q[14]),
+ .I1(cnt1),
+ .I2(cnt_reg[14]),
+ .O(\cnt[12]_i_2_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[12]_i_3
+ (.I0(Q[13]),
+ .I1(cnt1),
+ .I2(cnt_reg[13]),
+ .O(\cnt[12]_i_3_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[12]_i_4
+ (.I0(Q[12]),
+ .I1(cnt1),
+ .I2(cnt_reg[12]),
+ .O(\cnt[12]_i_4_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[12]_i_5
+ (.I0(cnt_reg[15]),
+ .I1(Q[15]),
+ .I2(cnt1),
+ .O(\cnt[12]_i_5_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[12]_i_6
+ (.I0(cnt_reg[14]),
+ .I1(Q[14]),
+ .I2(cnt1),
+ .O(\cnt[12]_i_6_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[12]_i_7
+ (.I0(cnt_reg[13]),
+ .I1(Q[13]),
+ .I2(cnt1),
+ .O(\cnt[12]_i_7_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[12]_i_8
+ (.I0(cnt_reg[12]),
+ .I1(Q[12]),
+ .I2(cnt1),
+ .O(\cnt[12]_i_8_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[4]_i_2
+ (.I0(Q[7]),
+ .I1(cnt1),
+ .I2(cnt_reg[7]),
+ .O(\cnt[4]_i_2_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[4]_i_3
+ (.I0(Q[6]),
+ .I1(cnt1),
+ .I2(cnt_reg[6]),
+ .O(\cnt[4]_i_3_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[4]_i_4
+ (.I0(Q[5]),
+ .I1(cnt1),
+ .I2(cnt_reg[5]),
+ .O(\cnt[4]_i_4_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[4]_i_5
+ (.I0(Q[4]),
+ .I1(cnt1),
+ .I2(cnt_reg[4]),
+ .O(\cnt[4]_i_5_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[4]_i_6
+ (.I0(cnt_reg[7]),
+ .I1(Q[7]),
+ .I2(cnt1),
+ .O(\cnt[4]_i_6_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[4]_i_7
+ (.I0(cnt_reg[6]),
+ .I1(Q[6]),
+ .I2(cnt1),
+ .O(\cnt[4]_i_7_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[4]_i_8
+ (.I0(cnt_reg[5]),
+ .I1(Q[5]),
+ .I2(cnt1),
+ .O(\cnt[4]_i_8_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[4]_i_9
+ (.I0(cnt_reg[4]),
+ .I1(Q[4]),
+ .I2(cnt1),
+ .O(\cnt[4]_i_9_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[8]_i_2
+ (.I0(Q[11]),
+ .I1(cnt1),
+ .I2(cnt_reg[11]),
+ .O(\cnt[8]_i_2_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[8]_i_3
+ (.I0(Q[10]),
+ .I1(cnt1),
+ .I2(cnt_reg[10]),
+ .O(\cnt[8]_i_3_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[8]_i_4
+ (.I0(Q[9]),
+ .I1(cnt1),
+ .I2(cnt_reg[9]),
+ .O(\cnt[8]_i_4_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[8]_i_5
+ (.I0(Q[8]),
+ .I1(cnt1),
+ .I2(cnt_reg[8]),
+ .O(\cnt[8]_i_5_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[8]_i_6
+ (.I0(cnt_reg[11]),
+ .I1(Q[11]),
+ .I2(cnt1),
+ .O(\cnt[8]_i_6_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[8]_i_7
+ (.I0(cnt_reg[10]),
+ .I1(Q[10]),
+ .I2(cnt1),
+ .O(\cnt[8]_i_7_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[8]_i_8
+ (.I0(cnt_reg[9]),
+ .I1(Q[9]),
+ .I2(cnt1),
+ .O(\cnt[8]_i_8_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[8]_i_9
+ (.I0(cnt_reg[8]),
+ .I1(Q[8]),
+ .I2(cnt1),
+ .O(\cnt[8]_i_9_n_0 ));
+ FDCE \cnt_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[0]_i_2_n_7 ),
+ .Q(cnt_reg[0]));
+ CARRY4 \cnt_reg[0]_i_2
+ (.CI(1'b0),
+ .CO({\cnt_reg[0]_i_2_n_0 ,\cnt_reg[0]_i_2_n_1 ,\cnt_reg[0]_i_2_n_2 ,\cnt_reg[0]_i_2_n_3 }),
+ .CYINIT(1'b0),
+ .DI({\cnt[0]_i_3_n_0 ,\cnt[0]_i_4_n_0 ,\cnt[0]_i_5_n_0 ,\cnt[0]_i_6_n_0 }),
+ .O({\cnt_reg[0]_i_2_n_4 ,\cnt_reg[0]_i_2_n_5 ,\cnt_reg[0]_i_2_n_6 ,\cnt_reg[0]_i_2_n_7 }),
+ .S({\cnt[0]_i_7_n_0 ,\cnt[0]_i_8_n_0 ,\cnt[0]_i_9_n_0 ,\cnt[0]_i_10_n_0 }));
+ FDCE \cnt_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[8]_i_1_n_5 ),
+ .Q(cnt_reg[10]));
+ FDCE \cnt_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[8]_i_1_n_4 ),
+ .Q(cnt_reg[11]));
+ FDCE \cnt_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[12]_i_1_n_7 ),
+ .Q(cnt_reg[12]));
+ CARRY4 \cnt_reg[12]_i_1
+ (.CI(\cnt_reg[8]_i_1_n_0 ),
+ .CO({\NLW_cnt_reg[12]_i_1_CO_UNCONNECTED [3],\cnt_reg[12]_i_1_n_1 ,\cnt_reg[12]_i_1_n_2 ,\cnt_reg[12]_i_1_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,\cnt[12]_i_2_n_0 ,\cnt[12]_i_3_n_0 ,\cnt[12]_i_4_n_0 }),
+ .O({\cnt_reg[12]_i_1_n_4 ,\cnt_reg[12]_i_1_n_5 ,\cnt_reg[12]_i_1_n_6 ,\cnt_reg[12]_i_1_n_7 }),
+ .S({\cnt[12]_i_5_n_0 ,\cnt[12]_i_6_n_0 ,\cnt[12]_i_7_n_0 ,\cnt[12]_i_8_n_0 }));
+ FDCE \cnt_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[12]_i_1_n_6 ),
+ .Q(cnt_reg[13]));
+ FDCE \cnt_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[12]_i_1_n_5 ),
+ .Q(cnt_reg[14]));
+ FDCE \cnt_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[12]_i_1_n_4 ),
+ .Q(cnt_reg[15]));
+ FDCE \cnt_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[0]_i_2_n_6 ),
+ .Q(cnt_reg[1]));
+ FDCE \cnt_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[0]_i_2_n_5 ),
+ .Q(cnt_reg[2]));
+ FDCE \cnt_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[0]_i_2_n_4 ),
+ .Q(cnt_reg[3]));
+ FDCE \cnt_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[4]_i_1_n_7 ),
+ .Q(cnt_reg[4]));
+ CARRY4 \cnt_reg[4]_i_1
+ (.CI(\cnt_reg[0]_i_2_n_0 ),
+ .CO({\cnt_reg[4]_i_1_n_0 ,\cnt_reg[4]_i_1_n_1 ,\cnt_reg[4]_i_1_n_2 ,\cnt_reg[4]_i_1_n_3 }),
+ .CYINIT(1'b0),
+ .DI({\cnt[4]_i_2_n_0 ,\cnt[4]_i_3_n_0 ,\cnt[4]_i_4_n_0 ,\cnt[4]_i_5_n_0 }),
+ .O({\cnt_reg[4]_i_1_n_4 ,\cnt_reg[4]_i_1_n_5 ,\cnt_reg[4]_i_1_n_6 ,\cnt_reg[4]_i_1_n_7 }),
+ .S({\cnt[4]_i_6_n_0 ,\cnt[4]_i_7_n_0 ,\cnt[4]_i_8_n_0 ,\cnt[4]_i_9_n_0 }));
+ FDCE \cnt_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[4]_i_1_n_6 ),
+ .Q(cnt_reg[5]));
+ FDCE \cnt_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[4]_i_1_n_5 ),
+ .Q(cnt_reg[6]));
+ FDCE \cnt_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[4]_i_1_n_4 ),
+ .Q(cnt_reg[7]));
+ FDCE \cnt_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[8]_i_1_n_7 ),
+ .Q(cnt_reg[8]));
+ CARRY4 \cnt_reg[8]_i_1
+ (.CI(\cnt_reg[4]_i_1_n_0 ),
+ .CO({\cnt_reg[8]_i_1_n_0 ,\cnt_reg[8]_i_1_n_1 ,\cnt_reg[8]_i_1_n_2 ,\cnt_reg[8]_i_1_n_3 }),
+ .CYINIT(1'b0),
+ .DI({\cnt[8]_i_2_n_0 ,\cnt[8]_i_3_n_0 ,\cnt[8]_i_4_n_0 ,\cnt[8]_i_5_n_0 }),
+ .O({\cnt_reg[8]_i_1_n_4 ,\cnt_reg[8]_i_1_n_5 ,\cnt_reg[8]_i_1_n_6 ,\cnt_reg[8]_i_1_n_7 }),
+ .S({\cnt[8]_i_6_n_0 ,\cnt[8]_i_7_n_0 ,\cnt[8]_i_8_n_0 ,\cnt[8]_i_9_n_0 }));
+ FDCE \cnt_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[8]_i_1_n_6 ),
+ .Q(cnt_reg[9]));
+ LUT6 #(
+ .INIT(64'h55FDFDFDFFFFFFFF))
+ \cr[7]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(i2c_al),
+ .I2(cmd_ack),
+ .I3(iack_o_reg),
+ .I4(wb_we_o),
+ .I5(iack_o_reg_0),
+ .O(\cr_reg[4] ));
+ FDCE dscl_oen_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(i2c_scl_t),
+ .Q(dscl_oen));
+ LUT5 #(
+ .INIT(32'hFBFFFBF3))
+ iscl_oen_i_1
+ (.I0(iscl_oen),
+ .I1(s00_axi_aresetn),
+ .I2(i2c_al),
+ .I3(iscl_oen9_out__0),
+ .I4(i2c_scl_t),
+ .O(iscl_oen_i_1_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ iscl_oen_i_2
+ (.I0(s00_axi_aresetn),
+ .O(iscl_oen_reg_0));
+ LUT5 #(
+ .INIT(32'h00F3011F))
+ iscl_oen_i_3
+ (.I0(c_state[3]),
+ .I1(c_state[2]),
+ .I2(c_state[1]),
+ .I3(c_state[4]),
+ .I4(c_state[0]),
+ .O(iscl_oen));
+ LUT5 #(
+ .INIT(32'h55560000))
+ iscl_oen_i_4
+ (.I0(c_state[4]),
+ .I1(c_state[3]),
+ .I2(c_state[2]),
+ .I3(c_state[1]),
+ .I4(clk_en),
+ .O(iscl_oen9_out__0));
+ FDPE iscl_oen_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(iscl_oen_i_1_n_0),
+ .PRE(iscl_oen_reg_0),
+ .Q(i2c_scl_t));
+ LUT5 #(
+ .INIT(32'hFBFFFBF3))
+ isda_oen_i_1
+ (.I0(isda_oen),
+ .I1(s00_axi_aresetn),
+ .I2(i2c_al),
+ .I3(isda_oen7_out__0),
+ .I4(i2c_sda_t),
+ .O(isda_oen_i_1_n_0));
+ LUT6 #(
+ .INIT(64'h0000C8CB03038F83))
+ isda_oen_i_2
+ (.I0(\statemachine.core_txd_reg_0 ),
+ .I1(c_state[3]),
+ .I2(c_state[2]),
+ .I3(c_state[0]),
+ .I4(c_state[4]),
+ .I5(c_state[1]),
+ .O(isda_oen));
+ LUT6 #(
+ .INIT(64'h0F0F1F1E00000000))
+ isda_oen_i_3
+ (.I0(c_state[1]),
+ .I1(c_state[2]),
+ .I2(c_state[4]),
+ .I3(c_state[0]),
+ .I4(c_state[3]),
+ .I5(clk_en),
+ .O(isda_oen7_out__0));
+ FDPE isda_oen_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(isda_oen_i_1_n_0),
+ .PRE(iscl_oen_reg_0),
+ .Q(i2c_sda_t));
+ CARRY4 minusOp_carry
+ (.CI(1'b0),
+ .CO({minusOp_carry_n_0,minusOp_carry_n_1,minusOp_carry_n_2,minusOp_carry_n_3}),
+ .CYINIT(filter_cnt[0]),
+ .DI(filter_cnt[4:1]),
+ .O({minusOp_carry_n_4,minusOp_carry_n_5,minusOp_carry_n_6,minusOp_carry_n_7}),
+ .S({minusOp_carry_i_1_n_0,minusOp_carry_i_2_n_0,minusOp_carry_i_3_n_0,minusOp_carry_i_4_n_0}));
+ CARRY4 minusOp_carry__0
+ (.CI(minusOp_carry_n_0),
+ .CO({minusOp_carry__0_n_0,minusOp_carry__0_n_1,minusOp_carry__0_n_2,minusOp_carry__0_n_3}),
+ .CYINIT(1'b0),
+ .DI(filter_cnt[8:5]),
+ .O({minusOp_carry__0_n_4,minusOp_carry__0_n_5,minusOp_carry__0_n_6,minusOp_carry__0_n_7}),
+ .S({minusOp_carry__0_i_1_n_0,minusOp_carry__0_i_2_n_0,minusOp_carry__0_i_3_n_0,minusOp_carry__0_i_4_n_0}));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__0_i_1
+ (.I0(filter_cnt[8]),
+ .O(minusOp_carry__0_i_1_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__0_i_2
+ (.I0(filter_cnt[7]),
+ .O(minusOp_carry__0_i_2_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__0_i_3
+ (.I0(filter_cnt[6]),
+ .O(minusOp_carry__0_i_3_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__0_i_4
+ (.I0(filter_cnt[5]),
+ .O(minusOp_carry__0_i_4_n_0));
+ CARRY4 minusOp_carry__1
+ (.CI(minusOp_carry__0_n_0),
+ .CO({minusOp_carry__1_n_0,minusOp_carry__1_n_1,minusOp_carry__1_n_2,minusOp_carry__1_n_3}),
+ .CYINIT(1'b0),
+ .DI(filter_cnt[12:9]),
+ .O({minusOp_carry__1_n_4,minusOp_carry__1_n_5,minusOp_carry__1_n_6,minusOp_carry__1_n_7}),
+ .S({minusOp_carry__1_i_1_n_0,minusOp_carry__1_i_2_n_0,minusOp_carry__1_i_3_n_0,minusOp_carry__1_i_4_n_0}));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__1_i_1
+ (.I0(filter_cnt[12]),
+ .O(minusOp_carry__1_i_1_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__1_i_2
+ (.I0(filter_cnt[11]),
+ .O(minusOp_carry__1_i_2_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__1_i_3
+ (.I0(filter_cnt[10]),
+ .O(minusOp_carry__1_i_3_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__1_i_4
+ (.I0(filter_cnt[9]),
+ .O(minusOp_carry__1_i_4_n_0));
+ CARRY4 minusOp_carry__2
+ (.CI(minusOp_carry__1_n_0),
+ .CO(NLW_minusOp_carry__2_CO_UNCONNECTED[3:0]),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O({NLW_minusOp_carry__2_O_UNCONNECTED[3:1],minusOp_carry__2_n_7}),
+ .S({1'b0,1'b0,1'b0,minusOp_carry__2_i_1_n_0}));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__2_i_1
+ (.I0(filter_cnt[13]),
+ .O(minusOp_carry__2_i_1_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry_i_1
+ (.I0(filter_cnt[4]),
+ .O(minusOp_carry_i_1_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry_i_2
+ (.I0(filter_cnt[3]),
+ .O(minusOp_carry_i_2_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry_i_3
+ (.I0(filter_cnt[2]),
+ .O(minusOp_carry_i_3_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry_i_4
+ (.I0(filter_cnt[1]),
+ .O(minusOp_carry_i_4_n_0));
+ LUT6 #(
+ .INIT(64'h0000000000100000))
+ sda_chk_i_1
+ (.I0(c_state[4]),
+ .I1(c_state[1]),
+ .I2(c_state[3]),
+ .I3(c_state[0]),
+ .I4(c_state[2]),
+ .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .O(sda_chk_i_1_n_0));
+ FDCE sda_chk_reg
+ (.C(s00_axi_aclk),
+ .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(sda_chk_i_1_n_0),
+ .Q(sda_chk_reg_n_0));
+ LUT4 #(
+ .INIT(16'h0F04))
+ slave_wait_i_1
+ (.I0(dscl_oen),
+ .I1(i2c_scl_t),
+ .I2(sSCL),
+ .I3(slave_wait),
+ .O(slave_wait0));
+ FDCE slave_wait_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(slave_wait0),
+ .Q(slave_wait));
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[0]_i_1
+ (.I0(\statemachine.ld_reg_0 ),
+ .I1(core_rxd),
+ .I2(\txr_reg[6] [0]),
+ .I3(s00_axi_aresetn),
+ .O(\sr_reg[0] ));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT4 #(
+ .INIT(16'hAA08))
+ \st_irq_block.al_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(\st_irq_block.al_reg ),
+ .I2(\cr_reg[7] [3]),
+ .I3(i2c_al),
+ .O(al));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
+ LUT5 #(
+ .INIT(32'h55540000))
+ \st_irq_block.irq_flag_i_1
+ (.I0(\cr_reg[0] ),
+ .I1(i2c_al),
+ .I2(cmd_ack),
+ .I3(irq_flag),
+ .I4(s00_axi_aresetn),
+ .O(irq_flag1_out));
+ LUT5 #(
+ .INIT(32'h08FF0800))
+ \statemachine.ack_out_i_1
+ (.I0(core_rxd),
+ .I1(s00_axi_aresetn),
+ .I2(i2c_al),
+ .I3(\statemachine.ack_out_i_2_n_0 ),
+ .I4(ack_out),
+ .O(\statemachine.ack_out_reg ));
+ LUT6 #(
+ .INIT(64'hDDDDDDDDDDFDDDDD))
+ \statemachine.ack_out_i_2
+ (.I0(s00_axi_aresetn),
+ .I1(i2c_al),
+ .I2(out[2]),
+ .I3(out[0]),
+ .I4(core_ack),
+ .I5(out[1]),
+ .O(\statemachine.ack_out_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000100000))
+ \statemachine.core_cmd[0]_i_1
+ (.I0(out[2]),
+ .I1(out[0]),
+ .I2(\cr_reg[7] [3]),
+ .I3(out[1]),
+ .I4(s00_axi_aresetn),
+ .I5(i2c_al),
+ .O(\statemachine.core_cmd_reg[3] [0]));
+ LUT6 #(
+ .INIT(64'h0000000022222E22))
+ \statemachine.core_cmd[1]_i_1
+ (.I0(\FSM_sequential_statemachine.c_state_reg[1]_0 ),
+ .I1(out[2]),
+ .I2(out[1]),
+ .I3(\cr_reg[7] [2]),
+ .I4(out[0]),
+ .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .O(\statemachine.core_cmd_reg[3] [1]));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT3 #(
+ .INIT(8'h08))
+ \statemachine.core_cmd[2]_i_1
+ (.I0(core_cmd),
+ .I1(s00_axi_aresetn),
+ .I2(i2c_al),
+ .O(\statemachine.core_cmd_reg[3] [2]));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT4 #(
+ .INIT(16'h0040))
+ \statemachine.core_cmd[3]_i_1
+ (.I0(out[2]),
+ .I1(\FSM_sequential_statemachine.c_state_reg[1] ),
+ .I2(s00_axi_aresetn),
+ .I3(i2c_al),
+ .O(\statemachine.core_cmd_reg[3] [3]));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT3 #(
+ .INIT(8'h08))
+ \statemachine.core_txd_i_1
+ (.I0(core_txd),
+ .I1(s00_axi_aresetn),
+ .I2(i2c_al),
+ .O(\statemachine.core_txd_reg ));
+ LUT6 #(
+ .INIT(64'h5455FFFD10002220))
+ \statemachine.core_txd_i_2
+ (.I0(out[2]),
+ .I1(out[0]),
+ .I2(ack_in),
+ .I3(core_ack),
+ .I4(out[1]),
+ .I5(\sr_reg[7] ),
+ .O(core_txd));
+ LUT6 #(
+ .INIT(64'h000000000000A020))
+ \statemachine.host_ack_i_1
+ (.I0(out[2]),
+ .I1(\cr_reg[7] [2]),
+ .I2(core_ack),
+ .I3(out[0]),
+ .I4(out[1]),
+ .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .O(\statemachine.host_ack_reg ));
+ LUT5 #(
+ .INIT(32'h00000400))
+ \statemachine.ld_i_1
+ (.I0(out[2]),
+ .I1(\FSM_sequential_statemachine.c_state[2]_i_3_n_0 ),
+ .I2(out[1]),
+ .I3(s00_axi_aresetn),
+ .I4(i2c_al),
+ .O(\statemachine.ld_reg ));
+ LUT6 #(
+ .INIT(64'h0000000004440000))
+ \statemachine.shift_i_1
+ (.I0(out[2]),
+ .I1(core_ack),
+ .I2(out[0]),
+ .I3(cnt_done),
+ .I4(out[1]),
+ .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .O(\statemachine.shift_reg ));
+ LUT5 #(
+ .INIT(32'h30BB3088))
+ \wb_dat_o[6]_i_3
+ (.I0(\cr_reg[7] [2]),
+ .I1(wb_adr_o[1]),
+ .I2(\txr_reg[6] [1]),
+ .I3(wb_adr_o[0]),
+ .I4(i2c_busy),
+ .O(\wb_dat_o[6]_i_3_n_0 ));
+ MUXF7 \wb_dat_o_reg[6]_i_1
+ (.I0(\sr_reg[6] ),
+ .I1(\wb_dat_o[6]_i_3_n_0 ),
+ .O(D),
+ .S(wb_adr_o[2]));
+endmodule
+
+(* ORIG_REF_NAME = "i2c_master_byte_ctrl" *)
+module system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
+ (iscl_oen_reg,
+ i2c_scl_t,
+ i2c_sda_t,
+ irq_flag1_out,
+ rxack_0,
+ al,
+ D,
+ E,
+ s00_axi_aclk,
+ s00_axi_aresetn,
+ \cr_reg[0] ,
+ irq_flag,
+ Q,
+ \ctr_reg[7] ,
+ i2c_sda_i,
+ i2c_scl_i,
+ \st_irq_block.al_reg ,
+ \cr_reg[7] ,
+ wb_adr_o,
+ \cr_reg[0]_0 ,
+ \cr_reg[1] ,
+ \cr_reg[2] ,
+ \txr_reg[7] ,
+ ack_in,
+ \cr_reg[5] ,
+ \cr_reg[7]_0 ,
+ iack_o_reg,
+ wb_we_o,
+ iack_o_reg_0);
+ output iscl_oen_reg;
+ output i2c_scl_t;
+ output i2c_sda_t;
+ output irq_flag1_out;
+ output rxack_0;
+ output al;
+ output [7:0]D;
+ output [0:0]E;
+ input s00_axi_aclk;
+ input s00_axi_aresetn;
+ input \cr_reg[0] ;
+ input irq_flag;
+ input [15:0]Q;
+ input [7:0]\ctr_reg[7] ;
+ input i2c_sda_i;
+ input i2c_scl_i;
+ input \st_irq_block.al_reg ;
+ input [3:0]\cr_reg[7] ;
+ input [2:0]wb_adr_o;
+ input \cr_reg[0]_0 ;
+ input \cr_reg[1] ;
+ input \cr_reg[2] ;
+ input [7:0]\txr_reg[7] ;
+ input ack_in;
+ input \cr_reg[5] ;
+ input \cr_reg[7]_0 ;
+ input iack_o_reg;
+ input wb_we_o;
+ input iack_o_reg_0;
+
+ wire [7:0]D;
+ wire [0:0]E;
+ wire \FSM_sequential_statemachine.c_state[0]_i_2_n_0 ;
+ wire \FSM_sequential_statemachine.c_state[1]_i_3_n_0 ;
+ wire \FSM_sequential_statemachine.c_state[2]_i_4_n_0 ;
+ wire [15:0]Q;
+ wire ack_in;
+ wire ack_out;
+ wire al;
+ wire bit_ctrl_n_10;
+ wire bit_ctrl_n_11;
+ wire bit_ctrl_n_12;
+ wire bit_ctrl_n_13;
+ wire bit_ctrl_n_14;
+ wire bit_ctrl_n_15;
+ wire bit_ctrl_n_17;
+ wire bit_ctrl_n_18;
+ wire bit_ctrl_n_19;
+ wire bit_ctrl_n_20;
+ wire bit_ctrl_n_7;
+ wire bit_ctrl_n_8;
+ wire bit_ctrl_n_9;
+ wire c_state;
+ (* RTL_KEEP = "yes" *) wire [2:0]c_state__0;
+ wire [3:0]cmd;
+ wire cmd_ack;
+ wire cnt_done;
+ wire [2:2]core_cmd;
+ wire \cr_reg[0] ;
+ wire \cr_reg[0]_0 ;
+ wire \cr_reg[1] ;
+ wire \cr_reg[2] ;
+ wire \cr_reg[5] ;
+ wire [3:0]\cr_reg[7] ;
+ wire \cr_reg[7]_0 ;
+ wire [7:0]\ctr_reg[7] ;
+ wire dcnt;
+ wire \dcnt[0]_i_1_n_0 ;
+ wire \dcnt[1]_i_1_n_0 ;
+ wire \dcnt[2]_i_1_n_0 ;
+ wire \dcnt_reg_n_0_[0] ;
+ wire \dcnt_reg_n_0_[1] ;
+ wire \dcnt_reg_n_0_[2] ;
+ wire [7:7]dout;
+ wire i2c_scl_i;
+ wire i2c_scl_t;
+ wire i2c_sda_i;
+ wire i2c_sda_t;
+ wire iack_o_reg;
+ wire iack_o_reg_0;
+ wire irq_flag;
+ wire irq_flag1_out;
+ wire iscl_oen_reg;
+ wire rxack_0;
+ wire s00_axi_aclk;
+ wire s00_axi_aresetn;
+ wire \sr[1]_i_1_n_0 ;
+ wire \sr[2]_i_1_n_0 ;
+ wire \sr[3]_i_1_n_0 ;
+ wire \sr[4]_i_1_n_0 ;
+ wire \sr[5]_i_1_n_0 ;
+ wire \sr[6]_i_1_n_0 ;
+ wire \sr[7]_i_2_n_0 ;
+ wire \sr_reg_n_0_[0] ;
+ wire \sr_reg_n_0_[1] ;
+ wire \sr_reg_n_0_[2] ;
+ wire \sr_reg_n_0_[3] ;
+ wire \sr_reg_n_0_[4] ;
+ wire \sr_reg_n_0_[5] ;
+ wire \sr_reg_n_0_[6] ;
+ wire \st_irq_block.al_reg ;
+ wire \statemachine.core_cmd[1]_i_2_n_0 ;
+ wire \statemachine.core_cmd[3]_i_2_n_0 ;
+ wire \statemachine.core_txd_reg_n_0 ;
+ wire \statemachine.ld_reg_n_0 ;
+ wire \statemachine.shift_reg_n_0 ;
+ wire [7:0]\txr_reg[7] ;
+ wire [2:0]wb_adr_o;
+ wire \wb_dat_o[0]_i_2_n_0 ;
+ wire \wb_dat_o[1]_i_2_n_0 ;
+ wire \wb_dat_o[2]_i_2_n_0 ;
+ wire \wb_dat_o[3]_i_2_n_0 ;
+ wire \wb_dat_o[4]_i_2_n_0 ;
+ wire \wb_dat_o[5]_i_2_n_0 ;
+ wire \wb_dat_o[6]_i_2_n_0 ;
+ wire \wb_dat_o[7]_i_2_n_0 ;
+ wire wb_we_o;
+
+ LUT5 #(
+ .INIT(32'h43407373))
+ \FSM_sequential_statemachine.c_state[0]_i_2
+ (.I0(cnt_done),
+ .I1(c_state__0[1]),
+ .I2(c_state__0[0]),
+ .I3(\cr_reg[7] [3]),
+ .I4(\cr_reg[7] [1]),
+ .O(\FSM_sequential_statemachine.c_state[0]_i_2_n_0 ));
+ LUT3 #(
+ .INIT(8'h01))
+ \FSM_sequential_statemachine.c_state[1]_i_2
+ (.I0(\dcnt_reg_n_0_[1] ),
+ .I1(\dcnt_reg_n_0_[0] ),
+ .I2(\dcnt_reg_n_0_[2] ),
+ .O(cnt_done));
+ LUT4 #(
+ .INIT(16'hFF54))
+ \FSM_sequential_statemachine.c_state[1]_i_3
+ (.I0(\cr_reg[7] [3]),
+ .I1(\cr_reg[7] [1]),
+ .I2(\cr_reg[7] [0]),
+ .I3(c_state__0[0]),
+ .O(\FSM_sequential_statemachine.c_state[1]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'h888888888888888B))
+ \FSM_sequential_statemachine.c_state[2]_i_4
+ (.I0(cnt_done),
+ .I1(c_state__0[1]),
+ .I2(\cr_reg[7] [3]),
+ .I3(\cr_reg[7] [0]),
+ .I4(\cr_reg[7] [1]),
+ .I5(c_state__0[0]),
+ .O(\FSM_sequential_statemachine.c_state[2]_i_4_n_0 ));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_statemachine.c_state_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(c_state),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_20),
+ .Q(c_state__0[0]));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_statemachine.c_state_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(c_state),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_19),
+ .Q(c_state__0[1]));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_statemachine.c_state_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(c_state),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_18),
+ .Q(c_state__0[2]));
+ system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl bit_ctrl
+ (.D(D[6]),
+ .E(c_state),
+ .\FSM_sequential_statemachine.c_state_reg[1] (\statemachine.core_cmd[3]_i_2_n_0 ),
+ .\FSM_sequential_statemachine.c_state_reg[1]_0 (\statemachine.core_cmd[1]_i_2_n_0 ),
+ .\FSM_sequential_statemachine.c_state_reg[1]_1 (\FSM_sequential_statemachine.c_state[0]_i_2_n_0 ),
+ .\FSM_sequential_statemachine.c_state_reg[1]_2 (\FSM_sequential_statemachine.c_state[2]_i_4_n_0 ),
+ .\FSM_sequential_statemachine.c_state_reg[2] ({bit_ctrl_n_18,bit_ctrl_n_19,bit_ctrl_n_20}),
+ .Q(Q),
+ .ack_in(ack_in),
+ .ack_out(ack_out),
+ .al(al),
+ .cmd_ack(cmd_ack),
+ .cnt_done(cnt_done),
+ .core_cmd(core_cmd),
+ .\cr_reg[0] (\cr_reg[0] ),
+ .\cr_reg[4] (E),
+ .\cr_reg[7] (\cr_reg[7] ),
+ .\cr_reg[7]_0 (\FSM_sequential_statemachine.c_state[1]_i_3_n_0 ),
+ .\ctr_reg[7] (\ctr_reg[7] [7]),
+ .i2c_scl_i(i2c_scl_i),
+ .i2c_scl_t(i2c_scl_t),
+ .i2c_sda_i(i2c_sda_i),
+ .i2c_sda_t(i2c_sda_t),
+ .iack_o_reg(iack_o_reg),
+ .iack_o_reg_0(iack_o_reg_0),
+ .irq_flag(irq_flag),
+ .irq_flag1_out(irq_flag1_out),
+ .iscl_oen_reg_0(iscl_oen_reg),
+ .out(c_state__0),
+ .s00_axi_aclk(s00_axi_aclk),
+ .s00_axi_aresetn(s00_axi_aresetn),
+ .\sr_reg[0] (bit_ctrl_n_17),
+ .\sr_reg[6] (\wb_dat_o[6]_i_2_n_0 ),
+ .\sr_reg[7] (dout),
+ .\st_irq_block.al_reg (\st_irq_block.al_reg ),
+ .\statemachine.ack_out_reg (bit_ctrl_n_15),
+ .\statemachine.core_cmd_reg[3] ({bit_ctrl_n_7,bit_ctrl_n_8,bit_ctrl_n_9,bit_ctrl_n_10}),
+ .\statemachine.core_cmd_reg[3]_0 (cmd),
+ .\statemachine.core_txd_reg (bit_ctrl_n_12),
+ .\statemachine.core_txd_reg_0 (\statemachine.core_txd_reg_n_0 ),
+ .\statemachine.host_ack_reg (bit_ctrl_n_14),
+ .\statemachine.ld_reg (bit_ctrl_n_11),
+ .\statemachine.ld_reg_0 (\statemachine.ld_reg_n_0 ),
+ .\statemachine.shift_reg (bit_ctrl_n_13),
+ .\txr_reg[6] ({\txr_reg[7] [6],\txr_reg[7] [0]}),
+ .wb_adr_o(wb_adr_o),
+ .wb_we_o(wb_we_o));
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
+ LUT3 #(
+ .INIT(8'h8A))
+ \dcnt[0]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(\statemachine.ld_reg_n_0 ),
+ .I2(\dcnt_reg_n_0_[0] ),
+ .O(\dcnt[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
+ LUT4 #(
+ .INIT(16'hA88A))
+ \dcnt[1]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(\statemachine.ld_reg_n_0 ),
+ .I2(\dcnt_reg_n_0_[0] ),
+ .I3(\dcnt_reg_n_0_[1] ),
+ .O(\dcnt[1]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
+ LUT5 #(
+ .INIT(32'hAAA8888A))
+ \dcnt[2]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(\statemachine.ld_reg_n_0 ),
+ .I2(\dcnt_reg_n_0_[1] ),
+ .I3(\dcnt_reg_n_0_[0] ),
+ .I4(\dcnt_reg_n_0_[2] ),
+ .O(\dcnt[2]_i_1_n_0 ));
+ FDCE \dcnt_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\dcnt[0]_i_1_n_0 ),
+ .Q(\dcnt_reg_n_0_[0] ));
+ FDCE \dcnt_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\dcnt[1]_i_1_n_0 ),
+ .Q(\dcnt_reg_n_0_[1] ));
+ FDCE \dcnt_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\dcnt[2]_i_1_n_0 ),
+ .Q(\dcnt_reg_n_0_[2] ));
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[1]_i_1
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(\sr_reg_n_0_[0] ),
+ .I2(\txr_reg[7] [1]),
+ .I3(s00_axi_aresetn),
+ .O(\sr[1]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[2]_i_1
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(\sr_reg_n_0_[1] ),
+ .I2(\txr_reg[7] [2]),
+ .I3(s00_axi_aresetn),
+ .O(\sr[2]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[3]_i_1
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(\sr_reg_n_0_[2] ),
+ .I2(\txr_reg[7] [3]),
+ .I3(s00_axi_aresetn),
+ .O(\sr[3]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[4]_i_1
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(\sr_reg_n_0_[3] ),
+ .I2(\txr_reg[7] [4]),
+ .I3(s00_axi_aresetn),
+ .O(\sr[4]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[5]_i_1
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(\sr_reg_n_0_[4] ),
+ .I2(\txr_reg[7] [5]),
+ .I3(s00_axi_aresetn),
+ .O(\sr[5]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[6]_i_1
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(\sr_reg_n_0_[5] ),
+ .I2(\txr_reg[7] [6]),
+ .I3(s00_axi_aresetn),
+ .O(\sr[6]_i_1_n_0 ));
+ LUT3 #(
+ .INIT(8'hFB))
+ \sr[7]_i_1
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(s00_axi_aresetn),
+ .I2(\statemachine.shift_reg_n_0 ),
+ .O(dcnt));
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[7]_i_2
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(\sr_reg_n_0_[6] ),
+ .I2(\txr_reg[7] [7]),
+ .I3(s00_axi_aresetn),
+ .O(\sr[7]_i_2_n_0 ));
+ FDCE \sr_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_17),
+ .Q(\sr_reg_n_0_[0] ));
+ FDCE \sr_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\sr[1]_i_1_n_0 ),
+ .Q(\sr_reg_n_0_[1] ));
+ FDCE \sr_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\sr[2]_i_1_n_0 ),
+ .Q(\sr_reg_n_0_[2] ));
+ FDCE \sr_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\sr[3]_i_1_n_0 ),
+ .Q(\sr_reg_n_0_[3] ));
+ FDCE \sr_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\sr[4]_i_1_n_0 ),
+ .Q(\sr_reg_n_0_[4] ));
+ FDCE \sr_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\sr[5]_i_1_n_0 ),
+ .Q(\sr_reg_n_0_[5] ));
+ FDCE \sr_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\sr[6]_i_1_n_0 ),
+ .Q(\sr_reg_n_0_[6] ));
+ FDCE \sr_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\sr[7]_i_2_n_0 ),
+ .Q(dout));
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \st_irq_block.rxack_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(ack_out),
+ .O(rxack_0));
+ FDCE \statemachine.ack_out_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_15),
+ .Q(ack_out));
+ LUT5 #(
+ .INIT(32'h00000001))
+ \statemachine.core_cmd[1]_i_2
+ (.I0(c_state__0[1]),
+ .I1(c_state__0[0]),
+ .I2(\cr_reg[7] [3]),
+ .I3(\cr_reg[7] [0]),
+ .I4(\cr_reg[7] [1]),
+ .O(\statemachine.core_cmd[1]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h00000000F0C40FC4))
+ \statemachine.core_cmd[2]_i_2
+ (.I0(\cr_reg[7] [3]),
+ .I1(\cr_reg[7] [1]),
+ .I2(c_state__0[0]),
+ .I3(c_state__0[1]),
+ .I4(cnt_done),
+ .I5(c_state__0[2]),
+ .O(core_cmd));
+ LUT6 #(
+ .INIT(64'h4848484878787B78))
+ \statemachine.core_cmd[3]_i_2
+ (.I0(cnt_done),
+ .I1(c_state__0[1]),
+ .I2(c_state__0[0]),
+ .I3(\cr_reg[7] [0]),
+ .I4(\cr_reg[7] [3]),
+ .I5(\cr_reg[7] [1]),
+ .O(\statemachine.core_cmd[3]_i_2_n_0 ));
+ FDCE \statemachine.core_cmd_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(c_state),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_10),
+ .Q(cmd[0]));
+ FDCE \statemachine.core_cmd_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(c_state),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_9),
+ .Q(cmd[1]));
+ FDCE \statemachine.core_cmd_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(c_state),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_8),
+ .Q(cmd[2]));
+ FDCE \statemachine.core_cmd_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(c_state),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_7),
+ .Q(cmd[3]));
+ FDCE \statemachine.core_txd_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_12),
+ .Q(\statemachine.core_txd_reg_n_0 ));
+ FDCE \statemachine.host_ack_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_14),
+ .Q(cmd_ack));
+ FDCE \statemachine.ld_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_11),
+ .Q(\statemachine.ld_reg_n_0 ));
+ FDCE \statemachine.shift_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_13),
+ .Q(\statemachine.shift_reg_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[0]_i_2
+ (.I0(\sr_reg_n_0_[0] ),
+ .I1(\ctr_reg[7] [0]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[8]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[0]),
+ .O(\wb_dat_o[0]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[1]_i_2
+ (.I0(\sr_reg_n_0_[1] ),
+ .I1(\ctr_reg[7] [1]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[9]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[1]),
+ .O(\wb_dat_o[1]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h3808FFFF38080000))
+ \wb_dat_o[2]_i_1
+ (.I0(\cr_reg[2] ),
+ .I1(wb_adr_o[1]),
+ .I2(wb_adr_o[0]),
+ .I3(\txr_reg[7] [2]),
+ .I4(wb_adr_o[2]),
+ .I5(\wb_dat_o[2]_i_2_n_0 ),
+ .O(D[2]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[2]_i_2
+ (.I0(\sr_reg_n_0_[2] ),
+ .I1(\ctr_reg[7] [2]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[10]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[2]),
+ .O(\wb_dat_o[2]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h3808FFFF38080000))
+ \wb_dat_o[3]_i_1
+ (.I0(ack_in),
+ .I1(wb_adr_o[1]),
+ .I2(wb_adr_o[0]),
+ .I3(\txr_reg[7] [3]),
+ .I4(wb_adr_o[2]),
+ .I5(\wb_dat_o[3]_i_2_n_0 ),
+ .O(D[3]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[3]_i_2
+ (.I0(\sr_reg_n_0_[3] ),
+ .I1(\ctr_reg[7] [3]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[11]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[3]),
+ .O(\wb_dat_o[3]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h3808FFFF38080000))
+ \wb_dat_o[4]_i_1
+ (.I0(\cr_reg[7] [0]),
+ .I1(wb_adr_o[1]),
+ .I2(wb_adr_o[0]),
+ .I3(\txr_reg[7] [4]),
+ .I4(wb_adr_o[2]),
+ .I5(\wb_dat_o[4]_i_2_n_0 ),
+ .O(D[4]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[4]_i_2
+ (.I0(\sr_reg_n_0_[4] ),
+ .I1(\ctr_reg[7] [4]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[12]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[4]),
+ .O(\wb_dat_o[4]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[5]_i_2
+ (.I0(\sr_reg_n_0_[5] ),
+ .I1(\ctr_reg[7] [5]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[13]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[5]),
+ .O(\wb_dat_o[5]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[6]_i_2
+ (.I0(\sr_reg_n_0_[6] ),
+ .I1(\ctr_reg[7] [6]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[14]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[6]),
+ .O(\wb_dat_o[6]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[7]_i_2
+ (.I0(dout),
+ .I1(\ctr_reg[7] [7]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[15]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[7]),
+ .O(\wb_dat_o[7]_i_2_n_0 ));
+ MUXF7 \wb_dat_o_reg[0]_i_1
+ (.I0(\wb_dat_o[0]_i_2_n_0 ),
+ .I1(\cr_reg[0]_0 ),
+ .O(D[0]),
+ .S(wb_adr_o[2]));
+ MUXF7 \wb_dat_o_reg[1]_i_1
+ (.I0(\wb_dat_o[1]_i_2_n_0 ),
+ .I1(\cr_reg[1] ),
+ .O(D[1]),
+ .S(wb_adr_o[2]));
+ MUXF7 \wb_dat_o_reg[5]_i_1
+ (.I0(\wb_dat_o[5]_i_2_n_0 ),
+ .I1(\cr_reg[5] ),
+ .O(D[5]),
+ .S(wb_adr_o[2]));
+ MUXF7 \wb_dat_o_reg[7]_i_1
+ (.I0(\wb_dat_o[7]_i_2_n_0 ),
+ .I1(\cr_reg[7]_0 ),
+ .O(D[7]),
+ .S(wb_adr_o[2]));
+endmodule
+
+(* ORIG_REF_NAME = "i2c_master_top" *)
+module system_design_axi_wb_i2c_master_0_1_i2c_master_top
+ (wb_ack_i,
+ wb_rst_o,
+ i2c_scl_t,
+ axi_int_o,
+ i2c_sda_t,
+ Q,
+ s_stb_r_reg,
+ \s_rdata_reg[0] ,
+ \s_rdata_reg[7] ,
+ s_stb_r_reg_0,
+ s00_axi_aclk,
+ s00_axi_aresetn,
+ i2c_sda_i,
+ i2c_scl_i,
+ s00_axi_wdata,
+ wb_adr_o,
+ s00_axi_awvalid,
+ s00_axi_arvalid,
+ wb_cyc_o,
+ wb_we_o,
+ iack_o_reg_0,
+ E,
+ s_we_r_reg,
+ s_we_r_reg_0,
+ D,
+ \s_addr_reg[4] );
+ output wb_ack_i;
+ output wb_rst_o;
+ output i2c_scl_t;
+ output axi_int_o;
+ output i2c_sda_t;
+ output [0:0]Q;
+ output s_stb_r_reg;
+ output [0:0]\s_rdata_reg[0] ;
+ output [7:0]\s_rdata_reg[7] ;
+ input s_stb_r_reg_0;
+ input s00_axi_aclk;
+ input s00_axi_aresetn;
+ input i2c_sda_i;
+ input i2c_scl_i;
+ input [7:0]s00_axi_wdata;
+ input [2:0]wb_adr_o;
+ input s00_axi_awvalid;
+ input s00_axi_arvalid;
+ input wb_cyc_o;
+ input wb_we_o;
+ input iack_o_reg_0;
+ input [1:0]E;
+ input [0:0]s_we_r_reg;
+ input [0:0]s_we_r_reg_0;
+ input [3:0]D;
+ input \s_addr_reg[4] ;
+
+ wire [3:0]D;
+ wire [1:0]E;
+ wire [0:0]Q;
+ wire ack_in;
+ wire al;
+ wire axi_int_o;
+ wire byte_ctrl_n_14;
+ wire \cr[0]_i_1_n_0 ;
+ wire \cr[1]_i_1_n_0 ;
+ wire \cr[2]_i_1_n_0 ;
+ wire \cr[3]_i_1_n_0 ;
+ wire \cr_reg_n_0_[0] ;
+ wire \cr_reg_n_0_[1] ;
+ wire \cr_reg_n_0_[2] ;
+ wire [7:0]ctr;
+ wire \ctr_reg_n_0_[0] ;
+ wire \ctr_reg_n_0_[1] ;
+ wire \ctr_reg_n_0_[2] ;
+ wire \ctr_reg_n_0_[3] ;
+ wire \ctr_reg_n_0_[4] ;
+ wire \ctr_reg_n_0_[5] ;
+ wire [13:0]data0;
+ wire i2c_scl_i;
+ wire i2c_scl_t;
+ wire i2c_sda_i;
+ wire i2c_sda_t;
+ wire iack_o_reg_0;
+ wire ien;
+ wire irq_flag;
+ wire irq_flag1_out;
+ wire \prer[10]_i_1_n_0 ;
+ wire \prer[11]_i_1_n_0 ;
+ wire \prer[12]_i_1_n_0 ;
+ wire \prer[13]_i_1_n_0 ;
+ wire \prer[14]_i_1_n_0 ;
+ wire \prer[15]_i_2_n_0 ;
+ wire \prer[8]_i_1_n_0 ;
+ wire \prer[9]_i_1_n_0 ;
+ wire \prer_reg_n_0_[0] ;
+ wire \prer_reg_n_0_[1] ;
+ wire read;
+ wire rxack;
+ wire rxack_0;
+ wire s00_axi_aclk;
+ wire s00_axi_aresetn;
+ wire s00_axi_arvalid;
+ wire s00_axi_awvalid;
+ wire [7:0]s00_axi_wdata;
+ wire \s_addr_reg[4] ;
+ wire [0:0]\s_rdata_reg[0] ;
+ wire [7:0]\s_rdata_reg[7] ;
+ wire s_stb_r_reg;
+ wire s_stb_r_reg_0;
+ wire [0:0]s_we_r_reg;
+ wire [0:0]s_we_r_reg_0;
+ wire \st_irq_block.al_reg_n_0 ;
+ wire \st_irq_block.wb_inta_o_i_1_n_0 ;
+ wire start;
+ wire stop;
+ wire tip;
+ wire tip_1;
+ wire [7:0]txr;
+ wire wb_ack_i;
+ wire [2:0]wb_adr_o;
+ wire wb_cyc_o;
+ wire [7:0]wb_dat_o;
+ wire \wb_dat_o[0]_i_3_n_0 ;
+ wire \wb_dat_o[1]_i_3_n_0 ;
+ wire \wb_dat_o[5]_i_3_n_0 ;
+ wire \wb_dat_o[7]_i_3_n_0 ;
+ wire wb_rst_o;
+ wire wb_we_o;
+ wire write;
+
+ system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl byte_ctrl
+ (.D(wb_dat_o),
+ .E(byte_ctrl_n_14),
+ .Q({data0,\prer_reg_n_0_[1] ,\prer_reg_n_0_[0] }),
+ .ack_in(ack_in),
+ .al(al),
+ .\cr_reg[0] (\cr_reg_n_0_[0] ),
+ .\cr_reg[0]_0 (\wb_dat_o[0]_i_3_n_0 ),
+ .\cr_reg[1] (\wb_dat_o[1]_i_3_n_0 ),
+ .\cr_reg[2] (\cr_reg_n_0_[2] ),
+ .\cr_reg[5] (\wb_dat_o[5]_i_3_n_0 ),
+ .\cr_reg[7] ({start,stop,read,write}),
+ .\cr_reg[7]_0 (\wb_dat_o[7]_i_3_n_0 ),
+ .\ctr_reg[7] ({Q,ien,\ctr_reg_n_0_[5] ,\ctr_reg_n_0_[4] ,\ctr_reg_n_0_[3] ,\ctr_reg_n_0_[2] ,\ctr_reg_n_0_[1] ,\ctr_reg_n_0_[0] }),
+ .i2c_scl_i(i2c_scl_i),
+ .i2c_scl_t(i2c_scl_t),
+ .i2c_sda_i(i2c_sda_i),
+ .i2c_sda_t(i2c_sda_t),
+ .iack_o_reg(wb_ack_i),
+ .iack_o_reg_0(iack_o_reg_0),
+ .irq_flag(irq_flag),
+ .irq_flag1_out(irq_flag1_out),
+ .iscl_oen_reg(wb_rst_o),
+ .rxack_0(rxack_0),
+ .s00_axi_aclk(s00_axi_aclk),
+ .s00_axi_aresetn(s00_axi_aresetn),
+ .\st_irq_block.al_reg (\st_irq_block.al_reg_n_0 ),
+ .\txr_reg[7] (txr),
+ .wb_adr_o(wb_adr_o),
+ .wb_we_o(wb_we_o));
+ LUT6 #(
+ .INIT(64'h8000FFFF80000000))
+ \cr[0]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[0]),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .I4(\s_addr_reg[4] ),
+ .I5(\cr_reg_n_0_[0] ),
+ .O(\cr[0]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h8000FFFF80000000))
+ \cr[1]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[1]),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .I4(\s_addr_reg[4] ),
+ .I5(\cr_reg_n_0_[1] ),
+ .O(\cr[1]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h8000FFFF80000000))
+ \cr[2]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[2]),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .I4(\s_addr_reg[4] ),
+ .I5(\cr_reg_n_0_[2] ),
+ .O(\cr[2]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
+ LUT4 #(
+ .INIT(16'hC808))
+ \cr[3]_i_1
+ (.I0(s00_axi_wdata[3]),
+ .I1(s00_axi_aresetn),
+ .I2(iack_o_reg_0),
+ .I3(ack_in),
+ .O(\cr[3]_i_1_n_0 ));
+ FDCE \cr_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(\cr[0]_i_1_n_0 ),
+ .Q(\cr_reg_n_0_[0] ));
+ FDCE \cr_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(\cr[1]_i_1_n_0 ),
+ .Q(\cr_reg_n_0_[1] ));
+ FDCE \cr_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(\cr[2]_i_1_n_0 ),
+ .Q(\cr_reg_n_0_[2] ));
+ FDCE \cr_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(\cr[3]_i_1_n_0 ),
+ .Q(ack_in));
+ FDCE \cr_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(byte_ctrl_n_14),
+ .CLR(wb_rst_o),
+ .D(D[0]),
+ .Q(write));
+ FDCE \cr_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(byte_ctrl_n_14),
+ .CLR(wb_rst_o),
+ .D(D[1]),
+ .Q(read));
+ FDCE \cr_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(byte_ctrl_n_14),
+ .CLR(wb_rst_o),
+ .D(D[2]),
+ .Q(stop));
+ FDCE \cr_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(byte_ctrl_n_14),
+ .CLR(wb_rst_o),
+ .D(D[3]),
+ .Q(start));
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[0]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[0]),
+ .O(ctr[0]));
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[1]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[1]),
+ .O(ctr[1]));
+ (* SOFT_HLUTNM = "soft_lutpair28" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[2]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[2]),
+ .O(ctr[2]));
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[3]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[3]),
+ .O(ctr[3]));
+ (* SOFT_HLUTNM = "soft_lutpair29" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[4]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[4]),
+ .O(ctr[4]));
+ (* SOFT_HLUTNM = "soft_lutpair30" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[5]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[5]),
+ .O(ctr[5]));
+ (* SOFT_HLUTNM = "soft_lutpair31" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[6]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[6]),
+ .O(ctr[6]));
+ (* SOFT_HLUTNM = "soft_lutpair32" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[7]_i_2
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[7]),
+ .O(ctr[7]));
+ FDCE \ctr_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[0]),
+ .Q(\ctr_reg_n_0_[0] ));
+ FDCE \ctr_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[1]),
+ .Q(\ctr_reg_n_0_[1] ));
+ FDCE \ctr_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[2]),
+ .Q(\ctr_reg_n_0_[2] ));
+ FDCE \ctr_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[3]),
+ .Q(\ctr_reg_n_0_[3] ));
+ FDCE \ctr_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[4]),
+ .Q(\ctr_reg_n_0_[4] ));
+ FDCE \ctr_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[5]),
+ .Q(\ctr_reg_n_0_[5] ));
+ FDCE \ctr_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[6]),
+ .Q(ien));
+ FDCE \ctr_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[7]),
+ .Q(Q));
+ FDRE iack_o_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(s_stb_r_reg_0),
+ .Q(wb_ack_i),
+ .R(1'b0));
+ (* SOFT_HLUTNM = "soft_lutpair28" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[10]_i_1
+ (.I0(s00_axi_wdata[2]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[10]_i_1_n_0 ));
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[11]_i_1
+ (.I0(s00_axi_wdata[3]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[11]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair29" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[12]_i_1
+ (.I0(s00_axi_wdata[4]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[12]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair30" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[13]_i_1
+ (.I0(s00_axi_wdata[5]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[13]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair31" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[14]_i_1
+ (.I0(s00_axi_wdata[6]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[14]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair32" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[15]_i_2
+ (.I0(s00_axi_wdata[7]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[15]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[8]_i_1
+ (.I0(s00_axi_wdata[0]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[8]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[9]_i_1
+ (.I0(s00_axi_wdata[1]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[9]_i_1_n_0 ));
+ FDPE \prer_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[8]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(\prer_reg_n_0_[0] ));
+ FDPE \prer_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[10]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[8]));
+ FDPE \prer_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[11]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[9]));
+ FDPE \prer_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[12]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[10]));
+ FDPE \prer_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[13]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[11]));
+ FDPE \prer_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[14]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[12]));
+ FDPE \prer_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[15]_i_2_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[13]));
+ FDPE \prer_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[9]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(\prer_reg_n_0_[1] ));
+ FDPE \prer_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[10]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[0]));
+ FDPE \prer_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[11]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[1]));
+ FDPE \prer_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[12]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[2]));
+ FDPE \prer_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[13]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[3]));
+ FDPE \prer_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[14]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[4]));
+ FDPE \prer_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[15]_i_2_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[5]));
+ FDPE \prer_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[8]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[6]));
+ FDPE \prer_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[9]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[7]));
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \s_rdata[7]_i_1
+ (.I0(wb_ack_i),
+ .I1(wb_we_o),
+ .O(\s_rdata_reg[0] ));
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
+ LUT4 #(
+ .INIT(16'hEFEE))
+ s_stb_r_i_1
+ (.I0(s00_axi_awvalid),
+ .I1(s00_axi_arvalid),
+ .I2(wb_ack_i),
+ .I3(wb_cyc_o),
+ .O(s_stb_r_reg));
+ FDCE \st_irq_block.al_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(al),
+ .Q(\st_irq_block.al_reg_n_0 ));
+ FDCE \st_irq_block.irq_flag_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(irq_flag1_out),
+ .Q(irq_flag));
+ FDCE \st_irq_block.rxack_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(rxack_0),
+ .Q(rxack));
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
+ LUT3 #(
+ .INIT(8'hA8))
+ \st_irq_block.tip_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(write),
+ .I2(read),
+ .O(tip_1));
+ FDCE \st_irq_block.tip_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(tip_1),
+ .Q(tip));
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
+ LUT3 #(
+ .INIT(8'h80))
+ \st_irq_block.wb_inta_o_i_1
+ (.I0(irq_flag),
+ .I1(s00_axi_aresetn),
+ .I2(ien),
+ .O(\st_irq_block.wb_inta_o_i_1_n_0 ));
+ FDCE \st_irq_block.wb_inta_o_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(\st_irq_block.wb_inta_o_i_1_n_0 ),
+ .Q(axi_int_o));
+ FDCE \txr_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[0]),
+ .Q(txr[0]));
+ FDCE \txr_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[1]),
+ .Q(txr[1]));
+ FDCE \txr_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[2]),
+ .Q(txr[2]));
+ FDCE \txr_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[3]),
+ .Q(txr[3]));
+ FDCE \txr_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[4]),
+ .Q(txr[4]));
+ FDCE \txr_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[5]),
+ .Q(txr[5]));
+ FDCE \txr_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[6]),
+ .Q(txr[6]));
+ FDCE \txr_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[7]),
+ .Q(txr[7]));
+ LUT5 #(
+ .INIT(32'h30BB3088))
+ \wb_dat_o[0]_i_3
+ (.I0(\cr_reg_n_0_[0] ),
+ .I1(wb_adr_o[1]),
+ .I2(txr[0]),
+ .I3(wb_adr_o[0]),
+ .I4(irq_flag),
+ .O(\wb_dat_o[0]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'h30BB3088))
+ \wb_dat_o[1]_i_3
+ (.I0(\cr_reg_n_0_[1] ),
+ .I1(wb_adr_o[1]),
+ .I2(txr[1]),
+ .I3(wb_adr_o[0]),
+ .I4(tip),
+ .O(\wb_dat_o[1]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'h30BB3088))
+ \wb_dat_o[5]_i_3
+ (.I0(read),
+ .I1(wb_adr_o[1]),
+ .I2(txr[5]),
+ .I3(wb_adr_o[0]),
+ .I4(\st_irq_block.al_reg_n_0 ),
+ .O(\wb_dat_o[5]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'h30BB3088))
+ \wb_dat_o[7]_i_3
+ (.I0(start),
+ .I1(wb_adr_o[1]),
+ .I2(txr[7]),
+ .I3(wb_adr_o[0]),
+ .I4(rxack),
+ .O(\wb_dat_o[7]_i_3_n_0 ));
+ FDRE \wb_dat_o_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[0]),
+ .Q(\s_rdata_reg[7] [0]),
+ .R(1'b0));
+ FDRE \wb_dat_o_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[1]),
+ .Q(\s_rdata_reg[7] [1]),
+ .R(1'b0));
+ FDRE \wb_dat_o_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[2]),
+ .Q(\s_rdata_reg[7] [2]),
+ .R(1'b0));
+ FDRE \wb_dat_o_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[3]),
+ .Q(\s_rdata_reg[7] [3]),
+ .R(1'b0));
+ FDRE \wb_dat_o_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[4]),
+ .Q(\s_rdata_reg[7] [4]),
+ .R(1'b0));
+ FDRE \wb_dat_o_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[5]),
+ .Q(\s_rdata_reg[7] [5]),
+ .R(1'b0));
+ FDRE \wb_dat_o_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[6]),
+ .Q(\s_rdata_reg[7] [6]),
+ .R(1'b0));
+ FDRE \wb_dat_o_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[7]),
+ .Q(\s_rdata_reg[7] [7]),
+ .R(1'b0));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl
new file mode 100644
index 00000000..203eaabe
--- /dev/null
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl
@@ -0,0 +1,4862 @@
+-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
+-- Date : Wed Oct 11 14:52:24 2017
+-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
+-- Command : write_vhdl -force -mode funcsim
+-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1_sim_netlist.vhdl
+-- Design : system_design_axi_wb_i2c_master_0_1
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7z030ffg676-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity system_design_axi_wb_i2c_master_0_1_axis_wbm_bridge is
+ port (
+ s00_axi_awready : out STD_LOGIC;
+ s00_axi_wready : out STD_LOGIC;
+ s00_axi_arready : out STD_LOGIC;
+ wb_we_o : out STD_LOGIC;
+ wb_cyc_o : out STD_LOGIC;
+ s00_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
+ s00_axi_bvalid : out STD_LOGIC;
+ \cr_reg[2]\ : out STD_LOGIC;
+ wb_adr_o : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ D : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \cr_reg[4]\ : out STD_LOGIC;
+ \prer_reg[8]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ \ctr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ s00_axi_rvalid : out STD_LOGIC;
+ iack_o_reg : out STD_LOGIC;
+ s00_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ wb_rst_o : in STD_LOGIC;
+ s00_axi_aclk : in STD_LOGIC;
+ iack_o_reg_0 : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 0 to 0 );
+ s00_axi_aresetn : in STD_LOGIC;
+ wb_ack_i : in STD_LOGIC;
+ s00_axi_awvalid : in STD_LOGIC;
+ s00_axi_arvalid : in STD_LOGIC;
+ s00_axi_bready : in STD_LOGIC;
+ s00_axi_rready : in STD_LOGIC;
+ s00_axi_wvalid : in STD_LOGIC;
+ s00_axi_wdata : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s00_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ iack_o_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \wb_dat_o_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_0_1_axis_wbm_bridge : entity is "axis_wbm_bridge";
+end system_design_axi_wb_i2c_master_0_1_axis_wbm_bridge;
+
+architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_axis_wbm_bridge is
+ signal \cr[2]_i_3_n_0\ : STD_LOGIC;
+ signal \^s00_axi_arready\ : STD_LOGIC;
+ signal \^s00_axi_awready\ : STD_LOGIC;
+ signal \^s00_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^s00_axi_wready\ : STD_LOGIC;
+ signal \s_addr[2]_i_1_n_0\ : STD_LOGIC;
+ signal \s_addr[3]_i_1_n_0\ : STD_LOGIC;
+ signal \s_addr[4]_i_1_n_0\ : STD_LOGIC;
+ signal s_arready_i_1_n_0 : STD_LOGIC;
+ signal s_awready_i_1_n_0 : STD_LOGIC;
+ signal \s_bresp[1]_i_1_n_0\ : STD_LOGIC;
+ signal s_bvalid : STD_LOGIC;
+ signal s_bvalid_i_1_n_0 : STD_LOGIC;
+ signal s_rvalid : STD_LOGIC;
+ signal s_rvalid_i_1_n_0 : STD_LOGIC;
+ signal s_we_r_i_1_n_0 : STD_LOGIC;
+ signal s_wready_i_1_n_0 : STD_LOGIC;
+ signal \^wb_adr_o\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \^wb_cyc_o\ : STD_LOGIC;
+ signal \^wb_we_o\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \cr[2]_i_3\ : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of \cr[4]_i_1\ : label is "soft_lutpair4";
+ attribute SOFT_HLUTNM of \cr[5]_i_1\ : label is "soft_lutpair4";
+ attribute SOFT_HLUTNM of \cr[6]_i_1\ : label is "soft_lutpair6";
+ attribute SOFT_HLUTNM of \cr[7]_i_2\ : label is "soft_lutpair6";
+ attribute SOFT_HLUTNM of \ctr[7]_i_1\ : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of iack_o_i_1 : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \prer[15]_i_1\ : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of s00_axi_bvalid_INST_0 : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of s00_axi_rvalid_INST_0 : label is "soft_lutpair3";
+ attribute SOFT_HLUTNM of s_awready_i_1 : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \s_bresp[1]_i_1\ : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of s_rvalid_i_1 : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of s_we_r_i_1 : label is "soft_lutpair3";
+ attribute SOFT_HLUTNM of s_wready_i_1 : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \txr[7]_i_1\ : label is "soft_lutpair0";
+begin
+ s00_axi_arready <= \^s00_axi_arready\;
+ s00_axi_awready <= \^s00_axi_awready\;
+ s00_axi_bresp(0) <= \^s00_axi_bresp\(0);
+ s00_axi_wready <= \^s00_axi_wready\;
+ wb_adr_o(2 downto 0) <= \^wb_adr_o\(2 downto 0);
+ wb_cyc_o <= \^wb_cyc_o\;
+ wb_we_o <= \^wb_we_o\;
+\cr[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF0008FFFFFFFF"
+ )
+ port map (
+ I0 => \^wb_adr_o\(2),
+ I1 => Q(0),
+ I2 => \^wb_adr_o\(1),
+ I3 => \^wb_adr_o\(0),
+ I4 => \cr[2]_i_3_n_0\,
+ I5 => s00_axi_aresetn,
+ O => \cr_reg[2]\
+ );
+\cr[2]_i_3\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"7"
+ )
+ port map (
+ I0 => \^wb_we_o\,
+ I1 => wb_ack_i,
+ O => \cr[2]_i_3_n_0\
+ );
+\cr[4]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(0),
+ I2 => \^wb_we_o\,
+ I3 => wb_ack_i,
+ O => D(0)
+ );
+\cr[5]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(1),
+ I2 => \^wb_we_o\,
+ I3 => wb_ack_i,
+ O => D(1)
+ );
+\cr[6]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(2),
+ I2 => \^wb_we_o\,
+ I3 => wb_ack_i,
+ O => D(2)
+ );
+\cr[7]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(3),
+ I2 => \^wb_we_o\,
+ I3 => wb_ack_i,
+ O => D(3)
+ );
+\cr[7]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFF7FFF"
+ )
+ port map (
+ I0 => wb_ack_i,
+ I1 => \^wb_we_o\,
+ I2 => \^wb_adr_o\(2),
+ I3 => Q(0),
+ I4 => \^wb_adr_o\(1),
+ I5 => \^wb_adr_o\(0),
+ O => \cr_reg[4]\
+ );
+\ctr[7]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0080FFFF"
+ )
+ port map (
+ I0 => \^wb_we_o\,
+ I1 => wb_ack_i,
+ I2 => \^wb_adr_o\(1),
+ I3 => \^wb_adr_o\(0),
+ I4 => s00_axi_aresetn,
+ O => \ctr_reg[0]\(0)
+ );
+iack_o_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^wb_cyc_o\,
+ I1 => wb_ack_i,
+ O => iack_o_reg
+ );
+\prer[15]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"75555555"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \^wb_adr_o\(1),
+ I2 => wb_ack_i,
+ I3 => \^wb_we_o\,
+ I4 => \^wb_adr_o\(0),
+ O => \prer_reg[8]\(1)
+ );
+\prer[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"5555555557555555"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \^wb_adr_o\(1),
+ I2 => \^wb_adr_o\(2),
+ I3 => wb_ack_i,
+ I4 => \^wb_we_o\,
+ I5 => \^wb_adr_o\(0),
+ O => \prer_reg[8]\(0)
+ );
+s00_axi_bvalid_INST_0: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s_bvalid,
+ I1 => \^wb_we_o\,
+ O => s00_axi_bvalid
+ );
+s00_axi_rvalid_INST_0: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => s_rvalid,
+ I1 => \^wb_we_o\,
+ O => s00_axi_rvalid
+ );
+\s_addr[2]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AACFAAC0"
+ )
+ port map (
+ I0 => s00_axi_araddr(0),
+ I1 => s00_axi_awaddr(0),
+ I2 => s00_axi_awvalid,
+ I3 => s00_axi_arvalid,
+ I4 => \^wb_adr_o\(0),
+ O => \s_addr[2]_i_1_n_0\
+ );
+\s_addr[3]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AACFAAC0"
+ )
+ port map (
+ I0 => s00_axi_araddr(1),
+ I1 => s00_axi_awaddr(1),
+ I2 => s00_axi_awvalid,
+ I3 => s00_axi_arvalid,
+ I4 => \^wb_adr_o\(1),
+ O => \s_addr[3]_i_1_n_0\
+ );
+\s_addr[4]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AACFAAC0"
+ )
+ port map (
+ I0 => s00_axi_araddr(2),
+ I1 => s00_axi_awaddr(2),
+ I2 => s00_axi_awvalid,
+ I3 => s00_axi_arvalid,
+ I4 => \^wb_adr_o\(2),
+ O => \s_addr[4]_i_1_n_0\
+ );
+\s_addr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \s_addr[2]_i_1_n_0\,
+ Q => \^wb_adr_o\(0),
+ R => wb_rst_o
+ );
+\s_addr_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \s_addr[3]_i_1_n_0\,
+ Q => \^wb_adr_o\(1),
+ R => wb_rst_o
+ );
+\s_addr_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \s_addr[4]_i_1_n_0\,
+ Q => \^wb_adr_o\(2),
+ R => wb_rst_o
+ );
+s_arready_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => s00_axi_arvalid,
+ I1 => \^s00_axi_arready\,
+ O => s_arready_i_1_n_0
+ );
+s_arready_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => s_arready_i_1_n_0,
+ Q => \^s00_axi_arready\,
+ R => wb_rst_o
+ );
+s_awready_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => s00_axi_wvalid,
+ I1 => s00_axi_awvalid,
+ I2 => \^s00_axi_awready\,
+ O => s_awready_i_1_n_0
+ );
+s_awready_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => s_awready_i_1_n_0,
+ Q => \^s00_axi_awready\,
+ R => wb_rst_o
+ );
+\s_bresp[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FF7F0000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \^wb_we_o\,
+ I2 => wb_ack_i,
+ I3 => s_bvalid,
+ I4 => \^s00_axi_bresp\(0),
+ O => \s_bresp[1]_i_1_n_0\
+ );
+\s_bresp_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \s_bresp[1]_i_1_n_0\,
+ Q => \^s00_axi_bresp\(0),
+ R => '0'
+ );
+s_bvalid_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0F88"
+ )
+ port map (
+ I0 => \^wb_we_o\,
+ I1 => wb_ack_i,
+ I2 => s00_axi_bready,
+ I3 => s_bvalid,
+ O => s_bvalid_i_1_n_0
+ );
+s_bvalid_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => s_bvalid_i_1_n_0,
+ Q => s_bvalid,
+ R => wb_rst_o
+ );
+\s_rdata_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(0),
+ Q => s00_axi_rdata(0),
+ R => wb_rst_o
+ );
+\s_rdata_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(1),
+ Q => s00_axi_rdata(1),
+ R => wb_rst_o
+ );
+\s_rdata_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(2),
+ Q => s00_axi_rdata(2),
+ R => wb_rst_o
+ );
+\s_rdata_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(3),
+ Q => s00_axi_rdata(3),
+ R => wb_rst_o
+ );
+\s_rdata_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(4),
+ Q => s00_axi_rdata(4),
+ R => wb_rst_o
+ );
+\s_rdata_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(5),
+ Q => s00_axi_rdata(5),
+ R => wb_rst_o
+ );
+\s_rdata_reg[6]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(6),
+ Q => s00_axi_rdata(6),
+ R => wb_rst_o
+ );
+\s_rdata_reg[7]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(7),
+ Q => s00_axi_rdata(7),
+ R => wb_rst_o
+ );
+s_rvalid_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"4F44"
+ )
+ port map (
+ I0 => s00_axi_rready,
+ I1 => s_rvalid,
+ I2 => \^wb_we_o\,
+ I3 => wb_ack_i,
+ O => s_rvalid_i_1_n_0
+ );
+s_rvalid_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => s_rvalid_i_1_n_0,
+ Q => s_rvalid,
+ R => wb_rst_o
+ );
+s_stb_r_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => iack_o_reg_0,
+ Q => \^wb_cyc_o\,
+ R => wb_rst_o
+ );
+s_we_r_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00E0"
+ )
+ port map (
+ I0 => \^wb_we_o\,
+ I1 => s00_axi_awvalid,
+ I2 => s00_axi_aresetn,
+ I3 => s00_axi_arvalid,
+ O => s_we_r_i_1_n_0
+ );
+s_we_r_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => s_we_r_i_1_n_0,
+ Q => \^wb_we_o\,
+ R => '0'
+ );
+s_wready_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => s00_axi_wvalid,
+ I1 => s00_axi_awvalid,
+ I2 => \^s00_axi_wready\,
+ O => s_wready_i_1_n_0
+ );
+s_wready_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => s_wready_i_1_n_0,
+ Q => \^s00_axi_wready\,
+ R => wb_rst_o
+ );
+\txr[7]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"8000FFFF"
+ )
+ port map (
+ I0 => \^wb_we_o\,
+ I1 => wb_ack_i,
+ I2 => \^wb_adr_o\(0),
+ I3 => \^wb_adr_o\(1),
+ I4 => s00_axi_aresetn,
+ O => E(0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl is
+ port (
+ iscl_oen_reg_0 : out STD_LOGIC;
+ i2c_scl_t : out STD_LOGIC;
+ i2c_sda_t : out STD_LOGIC;
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ irq_flag1_out : out STD_LOGIC;
+ al : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \statemachine.core_cmd_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \statemachine.ld_reg\ : out STD_LOGIC;
+ \statemachine.core_txd_reg\ : out STD_LOGIC;
+ \statemachine.shift_reg\ : out STD_LOGIC;
+ \statemachine.host_ack_reg\ : out STD_LOGIC;
+ \statemachine.ack_out_reg\ : out STD_LOGIC;
+ \cr_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \sr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \FSM_sequential_statemachine.c_state_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_aclk : in STD_LOGIC;
+ s00_axi_aresetn : in STD_LOGIC;
+ \out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \cr_reg[0]\ : in STD_LOGIC;
+ cmd_ack : in STD_LOGIC;
+ irq_flag : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ \ctr_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ i2c_sda_i : in STD_LOGIC;
+ i2c_scl_i : in STD_LOGIC;
+ \statemachine.core_cmd_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \st_irq_block.al_reg\ : in STD_LOGIC;
+ \cr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \sr_reg[6]\ : in STD_LOGIC;
+ \txr_reg[6]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \FSM_sequential_statemachine.c_state_reg[1]\ : in STD_LOGIC;
+ core_cmd : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \FSM_sequential_statemachine.c_state_reg[1]_0\ : in STD_LOGIC;
+ cnt_done : in STD_LOGIC;
+ ack_out : in STD_LOGIC;
+ iack_o_reg : in STD_LOGIC;
+ wb_we_o : in STD_LOGIC;
+ iack_o_reg_0 : in STD_LOGIC;
+ \statemachine.ld_reg_0\ : in STD_LOGIC;
+ \FSM_sequential_statemachine.c_state_reg[1]_1\ : in STD_LOGIC;
+ \FSM_sequential_statemachine.c_state_reg[1]_2\ : in STD_LOGIC;
+ ack_in : in STD_LOGIC;
+ \sr_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \cr_reg[7]_0\ : in STD_LOGIC;
+ \statemachine.core_txd_reg_0\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl : entity is "i2c_master_bit_ctrl";
+end system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl;
+
+architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl is
+ signal \FSM_sequential_c_state[0]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[0]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[1]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[1]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[1]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[2]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[2]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[3]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[3]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[3]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[4]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[4]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[4]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_statemachine.c_state[2]_i_3_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.cSCL[0]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.cSCL[1]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.cSDA[0]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.cSDA[1]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.cSDA_reg_n_0_[1]\ : STD_LOGIC;
+ signal \bus_status_ctrl.cmd_stop_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.cmd_stop_i_2_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.cmd_stop_reg_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.dSCL_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.dSDA_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.dout_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSCL[0]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSCL[1]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSCL[2]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSCL_reg_n_0_[2]\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSDA[0]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSDA[1]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSDA[2]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSDA[2]_i_2_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSDA_reg_n_0_[0]\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSDA_reg_n_0_[1]\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSDA_reg_n_0_[2]\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[0]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[10]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[11]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[12]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[13]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[13]_i_2_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[13]_i_3_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[13]_i_4_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[1]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[2]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[3]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[4]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[5]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[6]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[7]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[8]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[9]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.ial_i_2_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.ial_i_3_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.sSCL_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.sSDA_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.sta_condition_reg_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.sto_condition_reg_n_0\ : STD_LOGIC;
+ signal c_state : STD_LOGIC_VECTOR ( 4 downto 0 );
+ attribute RTL_KEEP : string;
+ attribute RTL_KEEP of c_state : signal is "yes";
+ signal clk_en : STD_LOGIC;
+ signal clk_en_i_2_n_0 : STD_LOGIC;
+ signal clk_en_i_3_n_0 : STD_LOGIC;
+ signal clk_en_i_4_n_0 : STD_LOGIC;
+ signal clk_en_i_5_n_0 : STD_LOGIC;
+ signal clk_en_i_6_n_0 : STD_LOGIC;
+ signal cmd_ack3_out : STD_LOGIC;
+ signal cmd_ack_i_2_n_0 : STD_LOGIC;
+ signal cnt1 : STD_LOGIC;
+ signal \cnt[0]_i_10_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_1_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_3_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_4_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_5_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_6_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_7_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_8_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_9_n_0\ : STD_LOGIC;
+ signal \cnt[12]_i_2_n_0\ : STD_LOGIC;
+ signal \cnt[12]_i_3_n_0\ : STD_LOGIC;
+ signal \cnt[12]_i_4_n_0\ : STD_LOGIC;
+ signal \cnt[12]_i_5_n_0\ : STD_LOGIC;
+ signal \cnt[12]_i_6_n_0\ : STD_LOGIC;
+ signal \cnt[12]_i_7_n_0\ : STD_LOGIC;
+ signal \cnt[12]_i_8_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_2_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_3_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_4_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_5_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_6_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_7_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_8_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_9_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_2_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_3_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_4_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_5_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_6_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_7_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_8_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_9_n_0\ : STD_LOGIC;
+ signal cnt_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
+ signal \cnt_reg[0]_i_2_n_0\ : STD_LOGIC;
+ signal \cnt_reg[0]_i_2_n_1\ : STD_LOGIC;
+ signal \cnt_reg[0]_i_2_n_2\ : STD_LOGIC;
+ signal \cnt_reg[0]_i_2_n_3\ : STD_LOGIC;
+ signal \cnt_reg[0]_i_2_n_4\ : STD_LOGIC;
+ signal \cnt_reg[0]_i_2_n_5\ : STD_LOGIC;
+ signal \cnt_reg[0]_i_2_n_6\ : STD_LOGIC;
+ signal \cnt_reg[0]_i_2_n_7\ : STD_LOGIC;
+ signal \cnt_reg[12]_i_1_n_1\ : STD_LOGIC;
+ signal \cnt_reg[12]_i_1_n_2\ : STD_LOGIC;
+ signal \cnt_reg[12]_i_1_n_3\ : STD_LOGIC;
+ signal \cnt_reg[12]_i_1_n_4\ : STD_LOGIC;
+ signal \cnt_reg[12]_i_1_n_5\ : STD_LOGIC;
+ signal \cnt_reg[12]_i_1_n_6\ : STD_LOGIC;
+ signal \cnt_reg[12]_i_1_n_7\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_0\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_1\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_2\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_3\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_4\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_5\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_6\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_7\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_0\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_1\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_2\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_3\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_4\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_5\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_6\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_7\ : STD_LOGIC;
+ signal core_ack : STD_LOGIC;
+ signal core_rxd : STD_LOGIC;
+ signal core_txd : STD_LOGIC;
+ signal dSCL : STD_LOGIC;
+ signal dSDA : STD_LOGIC;
+ signal dscl_oen : STD_LOGIC;
+ signal filter_cnt : STD_LOGIC_VECTOR ( 13 downto 0 );
+ signal i2c_al : STD_LOGIC;
+ signal i2c_busy : STD_LOGIC;
+ signal \^i2c_scl_t\ : STD_LOGIC;
+ signal \^i2c_sda_t\ : STD_LOGIC;
+ signal ial : STD_LOGIC;
+ signal ibusy : STD_LOGIC;
+ signal iscl_oen : STD_LOGIC;
+ signal \iscl_oen9_out__0\ : STD_LOGIC;
+ signal iscl_oen_i_1_n_0 : STD_LOGIC;
+ signal \^iscl_oen_reg_0\ : STD_LOGIC;
+ signal isda_oen : STD_LOGIC;
+ signal \isda_oen7_out__0\ : STD_LOGIC;
+ signal isda_oen_i_1_n_0 : STD_LOGIC;
+ signal \minusOp_carry__0_i_1_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__0_i_2_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__0_i_3_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__0_i_4_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_1\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_2\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_3\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_4\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_5\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_6\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_7\ : STD_LOGIC;
+ signal \minusOp_carry__1_i_1_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__1_i_2_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__1_i_3_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__1_i_4_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_1\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_2\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_3\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_4\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_5\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_6\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_7\ : STD_LOGIC;
+ signal \minusOp_carry__2_i_1_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__2_n_7\ : STD_LOGIC;
+ signal minusOp_carry_i_1_n_0 : STD_LOGIC;
+ signal minusOp_carry_i_2_n_0 : STD_LOGIC;
+ signal minusOp_carry_i_3_n_0 : STD_LOGIC;
+ signal minusOp_carry_i_4_n_0 : STD_LOGIC;
+ signal minusOp_carry_n_0 : STD_LOGIC;
+ signal minusOp_carry_n_1 : STD_LOGIC;
+ signal minusOp_carry_n_2 : STD_LOGIC;
+ signal minusOp_carry_n_3 : STD_LOGIC;
+ signal minusOp_carry_n_4 : STD_LOGIC;
+ signal minusOp_carry_n_5 : STD_LOGIC;
+ signal minusOp_carry_n_6 : STD_LOGIC;
+ signal minusOp_carry_n_7 : STD_LOGIC;
+ signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal sSCL : STD_LOGIC;
+ signal sSDA : STD_LOGIC;
+ signal sda_chk_i_1_n_0 : STD_LOGIC;
+ signal sda_chk_reg_n_0 : STD_LOGIC;
+ signal slave_wait : STD_LOGIC;
+ signal slave_wait0 : STD_LOGIC;
+ signal sta_condition : STD_LOGIC;
+ signal \statemachine.ack_out_i_2_n_0\ : STD_LOGIC;
+ signal sto_condition : STD_LOGIC;
+ signal \wb_dat_o[6]_i_3_n_0\ : STD_LOGIC;
+ signal \NLW_cnt_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal \NLW_minusOp_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_minusOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_c_state[4]_i_3\ : label is "soft_lutpair9";
+ attribute KEEP : string;
+ attribute KEEP of \FSM_sequential_c_state_reg[0]\ : label is "yes";
+ attribute KEEP of \FSM_sequential_c_state_reg[1]\ : label is "yes";
+ attribute KEEP of \FSM_sequential_c_state_reg[2]\ : label is "yes";
+ attribute KEEP of \FSM_sequential_c_state_reg[3]\ : label is "yes";
+ attribute KEEP of \FSM_sequential_c_state_reg[4]\ : label is "yes";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSCL[0]_i_1\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSCL[1]_i_1\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSDA[0]_i_1\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSDA[1]_i_1\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.dSCL_i_1\ : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.dSDA_i_1\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[0]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[1]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[2]_i_1\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[0]_i_1\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[1]_i_1\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[2]_i_2\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.ibusy_i_1\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.sSCL_i_1\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.sta_condition_i_1\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.sto_condition_i_1\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of clk_en_i_2 : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of \sr[0]_i_1\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \st_irq_block.al_i_1\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \st_irq_block.irq_flag_i_1\ : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \statemachine.core_cmd[2]_i_1\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \statemachine.core_cmd[3]_i_1\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \statemachine.core_txd_i_1\ : label is "soft_lutpair14";
+begin
+ i2c_scl_t <= \^i2c_scl_t\;
+ i2c_sda_t <= \^i2c_sda_t\;
+ iscl_oen_reg_0 <= \^iscl_oen_reg_0\;
+\FSM_sequential_c_state[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"1111111111111110"
+ )
+ port map (
+ I0 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ I1 => c_state(0),
+ I2 => c_state(2),
+ I3 => c_state(3),
+ I4 => \FSM_sequential_c_state[0]_i_2_n_0\,
+ I5 => c_state(4),
+ O => \FSM_sequential_c_state[0]_i_1_n_0\
+ );
+\FSM_sequential_c_state[0]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AAAAAABA"
+ )
+ port map (
+ I0 => c_state(1),
+ I1 => \statemachine.core_cmd_reg[3]_0\(1),
+ I2 => \statemachine.core_cmd_reg[3]_0\(0),
+ I3 => \statemachine.core_cmd_reg[3]_0\(3),
+ I4 => \statemachine.core_cmd_reg[3]_0\(2),
+ O => \FSM_sequential_c_state[0]_i_2_n_0\
+ );
+\FSM_sequential_c_state[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0400"
+ )
+ port map (
+ I0 => i2c_al,
+ I1 => s00_axi_aresetn,
+ I2 => c_state(4),
+ I3 => \FSM_sequential_c_state[1]_i_2_n_0\,
+ O => \FSM_sequential_c_state[1]_i_1_n_0\
+ );
+\FSM_sequential_c_state[1]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"EEEFEFFE44444444"
+ )
+ port map (
+ I0 => c_state(0),
+ I1 => c_state(1),
+ I2 => \statemachine.core_cmd_reg[3]_0\(1),
+ I3 => \statemachine.core_cmd_reg[3]_0\(2),
+ I4 => \statemachine.core_cmd_reg[3]_0\(3),
+ I5 => \FSM_sequential_c_state[1]_i_3_n_0\,
+ O => \FSM_sequential_c_state[1]_i_2_n_0\
+ );
+\FSM_sequential_c_state[1]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00001101"
+ )
+ port map (
+ I0 => c_state(2),
+ I1 => c_state(1),
+ I2 => \statemachine.core_cmd_reg[3]_0\(0),
+ I3 => c_state(0),
+ I4 => c_state(3),
+ O => \FSM_sequential_c_state[1]_i_3_n_0\
+ );
+\FSM_sequential_c_state[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0002A0A2AAAA0002"
+ )
+ port map (
+ I0 => \FSM_sequential_c_state[3]_i_2_n_0\,
+ I1 => c_state(3),
+ I2 => c_state(1),
+ I3 => \FSM_sequential_c_state[2]_i_2_n_0\,
+ I4 => c_state(2),
+ I5 => c_state(0),
+ O => \FSM_sequential_c_state[2]_i_1_n_0\
+ );
+\FSM_sequential_c_state[2]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFFFEEF"
+ )
+ port map (
+ I0 => c_state(0),
+ I1 => \statemachine.core_cmd_reg[3]_0\(3),
+ I2 => \statemachine.core_cmd_reg[3]_0\(1),
+ I3 => \statemachine.core_cmd_reg[3]_0\(2),
+ I4 => \statemachine.core_cmd_reg[3]_0\(0),
+ O => \FSM_sequential_c_state[2]_i_2_n_0\
+ );
+\FSM_sequential_c_state[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0AA8A0A800A800A8"
+ )
+ port map (
+ I0 => \FSM_sequential_c_state[3]_i_2_n_0\,
+ I1 => \FSM_sequential_c_state[3]_i_3_n_0\,
+ I2 => c_state(3),
+ I3 => c_state(0),
+ I4 => c_state(2),
+ I5 => c_state(1),
+ O => \FSM_sequential_c_state[3]_i_1_n_0\
+ );
+\FSM_sequential_c_state[3]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"04"
+ )
+ port map (
+ I0 => c_state(4),
+ I1 => s00_axi_aresetn,
+ I2 => i2c_al,
+ O => \FSM_sequential_c_state[3]_i_2_n_0\
+ );
+\FSM_sequential_c_state[3]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000006"
+ )
+ port map (
+ I0 => \statemachine.core_cmd_reg[3]_0\(3),
+ I1 => \statemachine.core_cmd_reg[3]_0\(2),
+ I2 => \statemachine.core_cmd_reg[3]_0\(0),
+ I3 => \statemachine.core_cmd_reg[3]_0\(1),
+ I4 => c_state(1),
+ I5 => c_state(2),
+ O => \FSM_sequential_c_state[3]_i_3_n_0\
+ );
+\FSM_sequential_c_state[4]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"BBBBBBBFAAAAAAAA"
+ )
+ port map (
+ I0 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ I1 => c_state(4),
+ I2 => c_state(3),
+ I3 => c_state(1),
+ I4 => c_state(2),
+ I5 => clk_en,
+ O => \FSM_sequential_c_state[4]_i_1_n_0\
+ );
+\FSM_sequential_c_state[4]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000080FF8000"
+ )
+ port map (
+ I0 => c_state(3),
+ I1 => c_state(1),
+ I2 => c_state(2),
+ I3 => c_state(0),
+ I4 => c_state(4),
+ I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ O => \FSM_sequential_c_state[4]_i_2_n_0\
+ );
+\FSM_sequential_c_state[4]_i_3\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => i2c_al,
+ I1 => s00_axi_aresetn,
+ O => \FSM_sequential_c_state[4]_i_3_n_0\
+ );
+\FSM_sequential_c_state_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \FSM_sequential_c_state[4]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \FSM_sequential_c_state[0]_i_1_n_0\,
+ Q => c_state(0)
+ );
+\FSM_sequential_c_state_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \FSM_sequential_c_state[4]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \FSM_sequential_c_state[1]_i_1_n_0\,
+ Q => c_state(1)
+ );
+\FSM_sequential_c_state_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \FSM_sequential_c_state[4]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \FSM_sequential_c_state[2]_i_1_n_0\,
+ Q => c_state(2)
+ );
+\FSM_sequential_c_state_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \FSM_sequential_c_state[4]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \FSM_sequential_c_state[3]_i_1_n_0\,
+ Q => c_state(3)
+ );
+\FSM_sequential_c_state_reg[4]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \FSM_sequential_c_state[4]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \FSM_sequential_c_state[4]_i_2_n_0\,
+ Q => c_state(4)
+ );
+\FSM_sequential_statemachine.c_state[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000022222E22"
+ )
+ port map (
+ I0 => \FSM_sequential_statemachine.c_state_reg[1]_1\,
+ I1 => \out\(2),
+ I2 => \out\(1),
+ I3 => \cr_reg[7]\(2),
+ I4 => \out\(0),
+ I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ O => \FSM_sequential_statemachine.c_state_reg[2]\(0)
+ );
+\FSM_sequential_statemachine.c_state[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000015100000"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => cnt_done,
+ I2 => \out\(1),
+ I3 => \cr_reg[7]_0\,
+ I4 => s00_axi_aresetn,
+ I5 => i2c_al,
+ O => \FSM_sequential_statemachine.c_state_reg[2]\(1)
+ );
+\FSM_sequential_statemachine.c_state[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"DDFFDDDDFFFDDDFD"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => i2c_al,
+ I2 => \FSM_sequential_statemachine.c_state[2]_i_3_n_0\,
+ I3 => \out\(1),
+ I4 => core_ack,
+ I5 => \out\(2),
+ O => E(0)
+ );
+\FSM_sequential_statemachine.c_state[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000022222E22"
+ )
+ port map (
+ I0 => \FSM_sequential_statemachine.c_state_reg[1]_2\,
+ I1 => \out\(2),
+ I2 => \out\(1),
+ I3 => \cr_reg[7]\(2),
+ I4 => \out\(0),
+ I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ O => \FSM_sequential_statemachine.c_state_reg[2]\(2)
+ );
+\FSM_sequential_statemachine.c_state[2]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8B8B8B8B8B8B8B88"
+ )
+ port map (
+ I0 => core_ack,
+ I1 => \out\(0),
+ I2 => cmd_ack,
+ I3 => \cr_reg[7]\(0),
+ I4 => \cr_reg[7]\(1),
+ I5 => \cr_reg[7]\(2),
+ O => \FSM_sequential_statemachine.c_state[2]_i_3_n_0\
+ );
+\bus_status_ctrl.cSCL[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => i2c_scl_i,
+ O => \bus_status_ctrl.cSCL[0]_i_1_n_0\
+ );
+\bus_status_ctrl.cSCL[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \p_0_in__0\(1),
+ O => \bus_status_ctrl.cSCL[1]_i_1_n_0\
+ );
+\bus_status_ctrl.cSCL_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.cSCL[0]_i_1_n_0\,
+ Q => \p_0_in__0\(1)
+ );
+\bus_status_ctrl.cSCL_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.cSCL[1]_i_1_n_0\,
+ Q => \p_0_in__1\(0)
+ );
+\bus_status_ctrl.cSDA[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => i2c_sda_i,
+ O => \bus_status_ctrl.cSDA[0]_i_1_n_0\
+ );
+\bus_status_ctrl.cSDA[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => p_0_in(1),
+ O => \bus_status_ctrl.cSDA[1]_i_1_n_0\
+ );
+\bus_status_ctrl.cSDA_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.cSDA[0]_i_1_n_0\,
+ Q => p_0_in(1)
+ );
+\bus_status_ctrl.cSDA_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.cSDA[1]_i_1_n_0\,
+ Q => \bus_status_ctrl.cSDA_reg_n_0_[1]\
+ );
+\bus_status_ctrl.cmd_stop_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"04FF000004000000"
+ )
+ port map (
+ I0 => \statemachine.core_cmd_reg[3]_0\(0),
+ I1 => \statemachine.core_cmd_reg[3]_0\(1),
+ I2 => \bus_status_ctrl.cmd_stop_i_2_n_0\,
+ I3 => clk_en,
+ I4 => s00_axi_aresetn,
+ I5 => \bus_status_ctrl.cmd_stop_reg_n_0\,
+ O => \bus_status_ctrl.cmd_stop_i_1_n_0\
+ );
+\bus_status_ctrl.cmd_stop_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => \statemachine.core_cmd_reg[3]_0\(2),
+ I1 => \statemachine.core_cmd_reg[3]_0\(3),
+ O => \bus_status_ctrl.cmd_stop_i_2_n_0\
+ );
+\bus_status_ctrl.cmd_stop_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.cmd_stop_i_1_n_0\,
+ Q => \bus_status_ctrl.cmd_stop_reg_n_0\
+ );
+\bus_status_ctrl.dSCL_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => sSCL,
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.dSCL_i_1_n_0\
+ );
+\bus_status_ctrl.dSCL_reg\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \bus_status_ctrl.dSCL_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => dSCL
+ );
+\bus_status_ctrl.dSDA_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => sSDA,
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.dSDA_i_1_n_0\
+ );
+\bus_status_ctrl.dSDA_reg\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \bus_status_ctrl.dSDA_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => dSDA
+ );
+\bus_status_ctrl.dout_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FB08"
+ )
+ port map (
+ I0 => sSDA,
+ I1 => sSCL,
+ I2 => dSCL,
+ I3 => core_rxd,
+ O => \bus_status_ctrl.dout_i_1_n_0\
+ );
+\bus_status_ctrl.dout_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.dout_i_1_n_0\,
+ Q => core_rxd
+ );
+\bus_status_ctrl.fSCL[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \p_0_in__1\(0),
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.fSCL[0]_i_1_n_0\
+ );
+\bus_status_ctrl.fSCL[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \p_0_in__1\(1),
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.fSCL[1]_i_1_n_0\
+ );
+\bus_status_ctrl.fSCL[2]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \p_0_in__1\(2),
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.fSCL[2]_i_1_n_0\
+ );
+\bus_status_ctrl.fSCL_reg[0]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
+ D => \bus_status_ctrl.fSCL[0]_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \p_0_in__1\(1)
+ );
+\bus_status_ctrl.fSCL_reg[1]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
+ D => \bus_status_ctrl.fSCL[1]_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \p_0_in__1\(2)
+ );
+\bus_status_ctrl.fSCL_reg[2]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
+ D => \bus_status_ctrl.fSCL[2]_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \bus_status_ctrl.fSCL_reg_n_0_[2]\
+ );
+\bus_status_ctrl.fSDA[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \bus_status_ctrl.cSDA_reg_n_0_[1]\,
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.fSDA[0]_i_1_n_0\
+ );
+\bus_status_ctrl.fSDA[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \bus_status_ctrl.fSDA_reg_n_0_[0]\,
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.fSDA[1]_i_1_n_0\
+ );
+\bus_status_ctrl.fSDA[2]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.fSDA[2]_i_1_n_0\
+ );
+\bus_status_ctrl.fSDA[2]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \bus_status_ctrl.fSDA_reg_n_0_[1]\,
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.fSDA[2]_i_2_n_0\
+ );
+\bus_status_ctrl.fSDA_reg[0]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
+ D => \bus_status_ctrl.fSDA[0]_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \bus_status_ctrl.fSDA_reg_n_0_[0]\
+ );
+\bus_status_ctrl.fSDA_reg[1]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
+ D => \bus_status_ctrl.fSDA[1]_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \bus_status_ctrl.fSDA_reg_n_0_[1]\
+ );
+\bus_status_ctrl.fSDA_reg[2]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
+ D => \bus_status_ctrl.fSDA[2]_i_2_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \bus_status_ctrl.fSDA_reg_n_0_[2]\
+ );
+\bus_status_ctrl.filter_cnt[0]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"D1000000"
+ )
+ port map (
+ I0 => filter_cnt(0),
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(2),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[0]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[10]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__1_n_6\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(12),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[10]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[11]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__1_n_5\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(13),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[11]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[12]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__1_n_4\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(14),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[12]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[13]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__2_n_7\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(15),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[13]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[13]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000001"
+ )
+ port map (
+ I0 => \bus_status_ctrl.filter_cnt[13]_i_3_n_0\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_4_n_0\,
+ I2 => filter_cnt(6),
+ I3 => filter_cnt(7),
+ I4 => filter_cnt(4),
+ I5 => filter_cnt(5),
+ O => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\
+ );
+\bus_status_ctrl.filter_cnt[13]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFFFFE"
+ )
+ port map (
+ I0 => filter_cnt(13),
+ I1 => filter_cnt(12),
+ I2 => filter_cnt(9),
+ I3 => filter_cnt(8),
+ I4 => filter_cnt(11),
+ I5 => filter_cnt(10),
+ O => \bus_status_ctrl.filter_cnt[13]_i_3_n_0\
+ );
+\bus_status_ctrl.filter_cnt[13]_i_4\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => filter_cnt(2),
+ I1 => filter_cnt(3),
+ I2 => filter_cnt(0),
+ I3 => filter_cnt(1),
+ O => \bus_status_ctrl.filter_cnt[13]_i_4_n_0\
+ );
+\bus_status_ctrl.filter_cnt[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => minusOp_carry_n_7,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(3),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[1]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[2]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => minusOp_carry_n_6,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(4),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[2]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[3]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => minusOp_carry_n_5,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(5),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[3]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[4]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => minusOp_carry_n_4,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(6),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[4]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[5]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__0_n_7\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(7),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[5]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[6]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__0_n_6\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(8),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[6]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[7]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__0_n_5\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(9),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[7]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[8]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__0_n_4\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(10),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[8]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[9]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__1_n_7\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(11),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[9]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[0]_i_1_n_0\,
+ Q => filter_cnt(0)
+ );
+\bus_status_ctrl.filter_cnt_reg[10]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[10]_i_1_n_0\,
+ Q => filter_cnt(10)
+ );
+\bus_status_ctrl.filter_cnt_reg[11]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[11]_i_1_n_0\,
+ Q => filter_cnt(11)
+ );
+\bus_status_ctrl.filter_cnt_reg[12]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[12]_i_1_n_0\,
+ Q => filter_cnt(12)
+ );
+\bus_status_ctrl.filter_cnt_reg[13]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[13]_i_1_n_0\,
+ Q => filter_cnt(13)
+ );
+\bus_status_ctrl.filter_cnt_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[1]_i_1_n_0\,
+ Q => filter_cnt(1)
+ );
+\bus_status_ctrl.filter_cnt_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[2]_i_1_n_0\,
+ Q => filter_cnt(2)
+ );
+\bus_status_ctrl.filter_cnt_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[3]_i_1_n_0\,
+ Q => filter_cnt(3)
+ );
+\bus_status_ctrl.filter_cnt_reg[4]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[4]_i_1_n_0\,
+ Q => filter_cnt(4)
+ );
+\bus_status_ctrl.filter_cnt_reg[5]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[5]_i_1_n_0\,
+ Q => filter_cnt(5)
+ );
+\bus_status_ctrl.filter_cnt_reg[6]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[6]_i_1_n_0\,
+ Q => filter_cnt(6)
+ );
+\bus_status_ctrl.filter_cnt_reg[7]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[7]_i_1_n_0\,
+ Q => filter_cnt(7)
+ );
+\bus_status_ctrl.filter_cnt_reg[8]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[8]_i_1_n_0\,
+ Q => filter_cnt(8)
+ );
+\bus_status_ctrl.filter_cnt_reg[9]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[9]_i_1_n_0\,
+ Q => filter_cnt(9)
+ );
+\bus_status_ctrl.ial_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"08000800AAAA0800"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => sda_chk_reg_n_0,
+ I2 => sSDA,
+ I3 => \^i2c_sda_t\,
+ I4 => \bus_status_ctrl.ial_i_2_n_0\,
+ I5 => \bus_status_ctrl.ial_i_3_n_0\,
+ O => ial
+ );
+\bus_status_ctrl.ial_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => c_state(0),
+ I1 => c_state(4),
+ O => \bus_status_ctrl.ial_i_2_n_0\
+ );
+\bus_status_ctrl.ial_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFFFFEF"
+ )
+ port map (
+ I0 => c_state(2),
+ I1 => c_state(3),
+ I2 => \bus_status_ctrl.sto_condition_reg_n_0\,
+ I3 => \bus_status_ctrl.cmd_stop_reg_n_0\,
+ I4 => c_state(1),
+ O => \bus_status_ctrl.ial_i_3_n_0\
+ );
+\bus_status_ctrl.ial_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => ial,
+ Q => i2c_al
+ );
+\bus_status_ctrl.ibusy_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"5400"
+ )
+ port map (
+ I0 => \bus_status_ctrl.sto_condition_reg_n_0\,
+ I1 => \bus_status_ctrl.sta_condition_reg_n_0\,
+ I2 => i2c_busy,
+ I3 => s00_axi_aresetn,
+ O => ibusy
+ );
+\bus_status_ctrl.ibusy_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => ibusy,
+ Q => i2c_busy
+ );
+\bus_status_ctrl.sSCL_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E8FF"
+ )
+ port map (
+ I0 => \p_0_in__1\(2),
+ I1 => \bus_status_ctrl.fSCL_reg_n_0_[2]\,
+ I2 => \p_0_in__1\(1),
+ I3 => s00_axi_aresetn,
+ O => \bus_status_ctrl.sSCL_i_1_n_0\
+ );
+\bus_status_ctrl.sSCL_reg\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \bus_status_ctrl.sSCL_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => sSCL
+ );
+\bus_status_ctrl.sSDA_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E8FF"
+ )
+ port map (
+ I0 => \bus_status_ctrl.fSDA_reg_n_0_[1]\,
+ I1 => \bus_status_ctrl.fSDA_reg_n_0_[2]\,
+ I2 => \bus_status_ctrl.fSDA_reg_n_0_[0]\,
+ I3 => s00_axi_aresetn,
+ O => \bus_status_ctrl.sSDA_i_1_n_0\
+ );
+\bus_status_ctrl.sSDA_reg\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \bus_status_ctrl.sSDA_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => sSDA
+ );
+\bus_status_ctrl.sta_condition_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"2000"
+ )
+ port map (
+ I0 => dSDA,
+ I1 => sSDA,
+ I2 => s00_axi_aresetn,
+ I3 => sSCL,
+ O => sta_condition
+ );
+\bus_status_ctrl.sta_condition_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => sta_condition,
+ Q => \bus_status_ctrl.sta_condition_reg_n_0\
+ );
+\bus_status_ctrl.sto_condition_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"4000"
+ )
+ port map (
+ I0 => dSDA,
+ I1 => s00_axi_aresetn,
+ I2 => sSCL,
+ I3 => sSDA,
+ O => sto_condition
+ );
+\bus_status_ctrl.sto_condition_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => sto_condition,
+ Q => \bus_status_ctrl.sto_condition_reg_n_0\
+ );
+clk_en_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AAAAAAAB"
+ )
+ port map (
+ I0 => clk_en_i_2_n_0,
+ I1 => clk_en_i_3_n_0,
+ I2 => clk_en_i_4_n_0,
+ I3 => clk_en_i_5_n_0,
+ I4 => clk_en_i_6_n_0,
+ O => cnt1
+ );
+clk_en_i_2: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"7555FFFF"
+ )
+ port map (
+ I0 => \ctr_reg[7]\(0),
+ I1 => sSCL,
+ I2 => \^i2c_scl_t\,
+ I3 => dSCL,
+ I4 => s00_axi_aresetn,
+ O => clk_en_i_2_n_0
+ );
+clk_en_i_3: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => cnt_reg(6),
+ I1 => cnt_reg(7),
+ I2 => cnt_reg(4),
+ I3 => cnt_reg(5),
+ O => clk_en_i_3_n_0
+ );
+clk_en_i_4: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => cnt_reg(2),
+ I1 => cnt_reg(3),
+ I2 => cnt_reg(0),
+ I3 => cnt_reg(1),
+ O => clk_en_i_4_n_0
+ );
+clk_en_i_5: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => cnt_reg(15),
+ I1 => cnt_reg(14),
+ I2 => cnt_reg(12),
+ I3 => cnt_reg(13),
+ O => clk_en_i_5_n_0
+ );
+clk_en_i_6: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => cnt_reg(10),
+ I1 => cnt_reg(11),
+ I2 => cnt_reg(8),
+ I3 => cnt_reg(9),
+ O => clk_en_i_6_n_0
+ );
+clk_en_reg: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => cnt1,
+ PRE => \^iscl_oen_reg_0\,
+ Q => clk_en
+ );
+cmd_ack_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0008000000000000"
+ )
+ port map (
+ I0 => cmd_ack_i_2_n_0,
+ I1 => c_state(0),
+ I2 => c_state(1),
+ I3 => i2c_al,
+ I4 => s00_axi_aresetn,
+ I5 => clk_en,
+ O => cmd_ack3_out
+ );
+cmd_ack_i_2: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"1E"
+ )
+ port map (
+ I0 => c_state(2),
+ I1 => c_state(3),
+ I2 => c_state(4),
+ O => cmd_ack_i_2_n_0
+ );
+cmd_ack_reg: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => cmd_ack3_out,
+ Q => core_ack
+ );
+\cnt[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => cnt1,
+ I1 => slave_wait,
+ O => \cnt[0]_i_1_n_0\
+ );
+\cnt[0]_i_10\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(0),
+ I1 => Q(0),
+ I2 => cnt1,
+ O => \cnt[0]_i_10_n_0\
+ );
+\cnt[0]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(3),
+ I1 => cnt1,
+ I2 => cnt_reg(3),
+ O => \cnt[0]_i_3_n_0\
+ );
+\cnt[0]_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => cnt1,
+ I2 => cnt_reg(2),
+ O => \cnt[0]_i_4_n_0\
+ );
+\cnt[0]_i_5\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => cnt1,
+ I2 => cnt_reg(1),
+ O => \cnt[0]_i_5_n_0\
+ );
+\cnt[0]_i_6\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => cnt1,
+ I2 => cnt_reg(0),
+ O => \cnt[0]_i_6_n_0\
+ );
+\cnt[0]_i_7\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(3),
+ I1 => Q(3),
+ I2 => cnt1,
+ O => \cnt[0]_i_7_n_0\
+ );
+\cnt[0]_i_8\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(2),
+ I1 => Q(2),
+ I2 => cnt1,
+ O => \cnt[0]_i_8_n_0\
+ );
+\cnt[0]_i_9\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(1),
+ I1 => Q(1),
+ I2 => cnt1,
+ O => \cnt[0]_i_9_n_0\
+ );
+\cnt[12]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(14),
+ I1 => cnt1,
+ I2 => cnt_reg(14),
+ O => \cnt[12]_i_2_n_0\
+ );
+\cnt[12]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(13),
+ I1 => cnt1,
+ I2 => cnt_reg(13),
+ O => \cnt[12]_i_3_n_0\
+ );
+\cnt[12]_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(12),
+ I1 => cnt1,
+ I2 => cnt_reg(12),
+ O => \cnt[12]_i_4_n_0\
+ );
+\cnt[12]_i_5\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(15),
+ I1 => Q(15),
+ I2 => cnt1,
+ O => \cnt[12]_i_5_n_0\
+ );
+\cnt[12]_i_6\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(14),
+ I1 => Q(14),
+ I2 => cnt1,
+ O => \cnt[12]_i_6_n_0\
+ );
+\cnt[12]_i_7\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(13),
+ I1 => Q(13),
+ I2 => cnt1,
+ O => \cnt[12]_i_7_n_0\
+ );
+\cnt[12]_i_8\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(12),
+ I1 => Q(12),
+ I2 => cnt1,
+ O => \cnt[12]_i_8_n_0\
+ );
+\cnt[4]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(7),
+ I1 => cnt1,
+ I2 => cnt_reg(7),
+ O => \cnt[4]_i_2_n_0\
+ );
+\cnt[4]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(6),
+ I1 => cnt1,
+ I2 => cnt_reg(6),
+ O => \cnt[4]_i_3_n_0\
+ );
+\cnt[4]_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(5),
+ I1 => cnt1,
+ I2 => cnt_reg(5),
+ O => \cnt[4]_i_4_n_0\
+ );
+\cnt[4]_i_5\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(4),
+ I1 => cnt1,
+ I2 => cnt_reg(4),
+ O => \cnt[4]_i_5_n_0\
+ );
+\cnt[4]_i_6\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(7),
+ I1 => Q(7),
+ I2 => cnt1,
+ O => \cnt[4]_i_6_n_0\
+ );
+\cnt[4]_i_7\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(6),
+ I1 => Q(6),
+ I2 => cnt1,
+ O => \cnt[4]_i_7_n_0\
+ );
+\cnt[4]_i_8\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(5),
+ I1 => Q(5),
+ I2 => cnt1,
+ O => \cnt[4]_i_8_n_0\
+ );
+\cnt[4]_i_9\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(4),
+ I1 => Q(4),
+ I2 => cnt1,
+ O => \cnt[4]_i_9_n_0\
+ );
+\cnt[8]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(11),
+ I1 => cnt1,
+ I2 => cnt_reg(11),
+ O => \cnt[8]_i_2_n_0\
+ );
+\cnt[8]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(10),
+ I1 => cnt1,
+ I2 => cnt_reg(10),
+ O => \cnt[8]_i_3_n_0\
+ );
+\cnt[8]_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(9),
+ I1 => cnt1,
+ I2 => cnt_reg(9),
+ O => \cnt[8]_i_4_n_0\
+ );
+\cnt[8]_i_5\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(8),
+ I1 => cnt1,
+ I2 => cnt_reg(8),
+ O => \cnt[8]_i_5_n_0\
+ );
+\cnt[8]_i_6\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(11),
+ I1 => Q(11),
+ I2 => cnt1,
+ O => \cnt[8]_i_6_n_0\
+ );
+\cnt[8]_i_7\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(10),
+ I1 => Q(10),
+ I2 => cnt1,
+ O => \cnt[8]_i_7_n_0\
+ );
+\cnt[8]_i_8\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(9),
+ I1 => Q(9),
+ I2 => cnt1,
+ O => \cnt[8]_i_8_n_0\
+ );
+\cnt[8]_i_9\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(8),
+ I1 => Q(8),
+ I2 => cnt1,
+ O => \cnt[8]_i_9_n_0\
+ );
+\cnt_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[0]_i_2_n_7\,
+ Q => cnt_reg(0)
+ );
+\cnt_reg[0]_i_2\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \cnt_reg[0]_i_2_n_0\,
+ CO(2) => \cnt_reg[0]_i_2_n_1\,
+ CO(1) => \cnt_reg[0]_i_2_n_2\,
+ CO(0) => \cnt_reg[0]_i_2_n_3\,
+ CYINIT => '0',
+ DI(3) => \cnt[0]_i_3_n_0\,
+ DI(2) => \cnt[0]_i_4_n_0\,
+ DI(1) => \cnt[0]_i_5_n_0\,
+ DI(0) => \cnt[0]_i_6_n_0\,
+ O(3) => \cnt_reg[0]_i_2_n_4\,
+ O(2) => \cnt_reg[0]_i_2_n_5\,
+ O(1) => \cnt_reg[0]_i_2_n_6\,
+ O(0) => \cnt_reg[0]_i_2_n_7\,
+ S(3) => \cnt[0]_i_7_n_0\,
+ S(2) => \cnt[0]_i_8_n_0\,
+ S(1) => \cnt[0]_i_9_n_0\,
+ S(0) => \cnt[0]_i_10_n_0\
+ );
+\cnt_reg[10]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[8]_i_1_n_5\,
+ Q => cnt_reg(10)
+ );
+\cnt_reg[11]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[8]_i_1_n_4\,
+ Q => cnt_reg(11)
+ );
+\cnt_reg[12]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[12]_i_1_n_7\,
+ Q => cnt_reg(12)
+ );
+\cnt_reg[12]_i_1\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \cnt_reg[8]_i_1_n_0\,
+ CO(3) => \NLW_cnt_reg[12]_i_1_CO_UNCONNECTED\(3),
+ CO(2) => \cnt_reg[12]_i_1_n_1\,
+ CO(1) => \cnt_reg[12]_i_1_n_2\,
+ CO(0) => \cnt_reg[12]_i_1_n_3\,
+ CYINIT => '0',
+ DI(3) => '0',
+ DI(2) => \cnt[12]_i_2_n_0\,
+ DI(1) => \cnt[12]_i_3_n_0\,
+ DI(0) => \cnt[12]_i_4_n_0\,
+ O(3) => \cnt_reg[12]_i_1_n_4\,
+ O(2) => \cnt_reg[12]_i_1_n_5\,
+ O(1) => \cnt_reg[12]_i_1_n_6\,
+ O(0) => \cnt_reg[12]_i_1_n_7\,
+ S(3) => \cnt[12]_i_5_n_0\,
+ S(2) => \cnt[12]_i_6_n_0\,
+ S(1) => \cnt[12]_i_7_n_0\,
+ S(0) => \cnt[12]_i_8_n_0\
+ );
+\cnt_reg[13]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[12]_i_1_n_6\,
+ Q => cnt_reg(13)
+ );
+\cnt_reg[14]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[12]_i_1_n_5\,
+ Q => cnt_reg(14)
+ );
+\cnt_reg[15]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[12]_i_1_n_4\,
+ Q => cnt_reg(15)
+ );
+\cnt_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[0]_i_2_n_6\,
+ Q => cnt_reg(1)
+ );
+\cnt_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[0]_i_2_n_5\,
+ Q => cnt_reg(2)
+ );
+\cnt_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[0]_i_2_n_4\,
+ Q => cnt_reg(3)
+ );
+\cnt_reg[4]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[4]_i_1_n_7\,
+ Q => cnt_reg(4)
+ );
+\cnt_reg[4]_i_1\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \cnt_reg[0]_i_2_n_0\,
+ CO(3) => \cnt_reg[4]_i_1_n_0\,
+ CO(2) => \cnt_reg[4]_i_1_n_1\,
+ CO(1) => \cnt_reg[4]_i_1_n_2\,
+ CO(0) => \cnt_reg[4]_i_1_n_3\,
+ CYINIT => '0',
+ DI(3) => \cnt[4]_i_2_n_0\,
+ DI(2) => \cnt[4]_i_3_n_0\,
+ DI(1) => \cnt[4]_i_4_n_0\,
+ DI(0) => \cnt[4]_i_5_n_0\,
+ O(3) => \cnt_reg[4]_i_1_n_4\,
+ O(2) => \cnt_reg[4]_i_1_n_5\,
+ O(1) => \cnt_reg[4]_i_1_n_6\,
+ O(0) => \cnt_reg[4]_i_1_n_7\,
+ S(3) => \cnt[4]_i_6_n_0\,
+ S(2) => \cnt[4]_i_7_n_0\,
+ S(1) => \cnt[4]_i_8_n_0\,
+ S(0) => \cnt[4]_i_9_n_0\
+ );
+\cnt_reg[5]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[4]_i_1_n_6\,
+ Q => cnt_reg(5)
+ );
+\cnt_reg[6]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[4]_i_1_n_5\,
+ Q => cnt_reg(6)
+ );
+\cnt_reg[7]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[4]_i_1_n_4\,
+ Q => cnt_reg(7)
+ );
+\cnt_reg[8]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[8]_i_1_n_7\,
+ Q => cnt_reg(8)
+ );
+\cnt_reg[8]_i_1\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \cnt_reg[4]_i_1_n_0\,
+ CO(3) => \cnt_reg[8]_i_1_n_0\,
+ CO(2) => \cnt_reg[8]_i_1_n_1\,
+ CO(1) => \cnt_reg[8]_i_1_n_2\,
+ CO(0) => \cnt_reg[8]_i_1_n_3\,
+ CYINIT => '0',
+ DI(3) => \cnt[8]_i_2_n_0\,
+ DI(2) => \cnt[8]_i_3_n_0\,
+ DI(1) => \cnt[8]_i_4_n_0\,
+ DI(0) => \cnt[8]_i_5_n_0\,
+ O(3) => \cnt_reg[8]_i_1_n_4\,
+ O(2) => \cnt_reg[8]_i_1_n_5\,
+ O(1) => \cnt_reg[8]_i_1_n_6\,
+ O(0) => \cnt_reg[8]_i_1_n_7\,
+ S(3) => \cnt[8]_i_6_n_0\,
+ S(2) => \cnt[8]_i_7_n_0\,
+ S(1) => \cnt[8]_i_8_n_0\,
+ S(0) => \cnt[8]_i_9_n_0\
+ );
+\cnt_reg[9]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[8]_i_1_n_6\,
+ Q => cnt_reg(9)
+ );
+\cr[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"55FDFDFDFFFFFFFF"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => i2c_al,
+ I2 => cmd_ack,
+ I3 => iack_o_reg,
+ I4 => wb_we_o,
+ I5 => iack_o_reg_0,
+ O => \cr_reg[4]\(0)
+ );
+dscl_oen_reg: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \^i2c_scl_t\,
+ Q => dscl_oen
+ );
+iscl_oen_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FBFFFBF3"
+ )
+ port map (
+ I0 => iscl_oen,
+ I1 => s00_axi_aresetn,
+ I2 => i2c_al,
+ I3 => \iscl_oen9_out__0\,
+ I4 => \^i2c_scl_t\,
+ O => iscl_oen_i_1_n_0
+ );
+iscl_oen_i_2: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ O => \^iscl_oen_reg_0\
+ );
+iscl_oen_i_3: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00F3011F"
+ )
+ port map (
+ I0 => c_state(3),
+ I1 => c_state(2),
+ I2 => c_state(1),
+ I3 => c_state(4),
+ I4 => c_state(0),
+ O => iscl_oen
+ );
+iscl_oen_i_4: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"55560000"
+ )
+ port map (
+ I0 => c_state(4),
+ I1 => c_state(3),
+ I2 => c_state(2),
+ I3 => c_state(1),
+ I4 => clk_en,
+ O => \iscl_oen9_out__0\
+ );
+iscl_oen_reg: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => iscl_oen_i_1_n_0,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \^i2c_scl_t\
+ );
+isda_oen_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FBFFFBF3"
+ )
+ port map (
+ I0 => isda_oen,
+ I1 => s00_axi_aresetn,
+ I2 => i2c_al,
+ I3 => \isda_oen7_out__0\,
+ I4 => \^i2c_sda_t\,
+ O => isda_oen_i_1_n_0
+ );
+isda_oen_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000C8CB03038F83"
+ )
+ port map (
+ I0 => \statemachine.core_txd_reg_0\,
+ I1 => c_state(3),
+ I2 => c_state(2),
+ I3 => c_state(0),
+ I4 => c_state(4),
+ I5 => c_state(1),
+ O => isda_oen
+ );
+isda_oen_i_3: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0F0F1F1E00000000"
+ )
+ port map (
+ I0 => c_state(1),
+ I1 => c_state(2),
+ I2 => c_state(4),
+ I3 => c_state(0),
+ I4 => c_state(3),
+ I5 => clk_en,
+ O => \isda_oen7_out__0\
+ );
+isda_oen_reg: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => isda_oen_i_1_n_0,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \^i2c_sda_t\
+ );
+minusOp_carry: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => minusOp_carry_n_0,
+ CO(2) => minusOp_carry_n_1,
+ CO(1) => minusOp_carry_n_2,
+ CO(0) => minusOp_carry_n_3,
+ CYINIT => filter_cnt(0),
+ DI(3 downto 0) => filter_cnt(4 downto 1),
+ O(3) => minusOp_carry_n_4,
+ O(2) => minusOp_carry_n_5,
+ O(1) => minusOp_carry_n_6,
+ O(0) => minusOp_carry_n_7,
+ S(3) => minusOp_carry_i_1_n_0,
+ S(2) => minusOp_carry_i_2_n_0,
+ S(1) => minusOp_carry_i_3_n_0,
+ S(0) => minusOp_carry_i_4_n_0
+ );
+\minusOp_carry__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => minusOp_carry_n_0,
+ CO(3) => \minusOp_carry__0_n_0\,
+ CO(2) => \minusOp_carry__0_n_1\,
+ CO(1) => \minusOp_carry__0_n_2\,
+ CO(0) => \minusOp_carry__0_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => filter_cnt(8 downto 5),
+ O(3) => \minusOp_carry__0_n_4\,
+ O(2) => \minusOp_carry__0_n_5\,
+ O(1) => \minusOp_carry__0_n_6\,
+ O(0) => \minusOp_carry__0_n_7\,
+ S(3) => \minusOp_carry__0_i_1_n_0\,
+ S(2) => \minusOp_carry__0_i_2_n_0\,
+ S(1) => \minusOp_carry__0_i_3_n_0\,
+ S(0) => \minusOp_carry__0_i_4_n_0\
+ );
+\minusOp_carry__0_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(8),
+ O => \minusOp_carry__0_i_1_n_0\
+ );
+\minusOp_carry__0_i_2\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(7),
+ O => \minusOp_carry__0_i_2_n_0\
+ );
+\minusOp_carry__0_i_3\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(6),
+ O => \minusOp_carry__0_i_3_n_0\
+ );
+\minusOp_carry__0_i_4\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(5),
+ O => \minusOp_carry__0_i_4_n_0\
+ );
+\minusOp_carry__1\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \minusOp_carry__0_n_0\,
+ CO(3) => \minusOp_carry__1_n_0\,
+ CO(2) => \minusOp_carry__1_n_1\,
+ CO(1) => \minusOp_carry__1_n_2\,
+ CO(0) => \minusOp_carry__1_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => filter_cnt(12 downto 9),
+ O(3) => \minusOp_carry__1_n_4\,
+ O(2) => \minusOp_carry__1_n_5\,
+ O(1) => \minusOp_carry__1_n_6\,
+ O(0) => \minusOp_carry__1_n_7\,
+ S(3) => \minusOp_carry__1_i_1_n_0\,
+ S(2) => \minusOp_carry__1_i_2_n_0\,
+ S(1) => \minusOp_carry__1_i_3_n_0\,
+ S(0) => \minusOp_carry__1_i_4_n_0\
+ );
+\minusOp_carry__1_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(12),
+ O => \minusOp_carry__1_i_1_n_0\
+ );
+\minusOp_carry__1_i_2\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(11),
+ O => \minusOp_carry__1_i_2_n_0\
+ );
+\minusOp_carry__1_i_3\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(10),
+ O => \minusOp_carry__1_i_3_n_0\
+ );
+\minusOp_carry__1_i_4\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(9),
+ O => \minusOp_carry__1_i_4_n_0\
+ );
+\minusOp_carry__2\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \minusOp_carry__1_n_0\,
+ CO(3 downto 0) => \NLW_minusOp_carry__2_CO_UNCONNECTED\(3 downto 0),
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 1) => \NLW_minusOp_carry__2_O_UNCONNECTED\(3 downto 1),
+ O(0) => \minusOp_carry__2_n_7\,
+ S(3 downto 1) => B"000",
+ S(0) => \minusOp_carry__2_i_1_n_0\
+ );
+\minusOp_carry__2_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(13),
+ O => \minusOp_carry__2_i_1_n_0\
+ );
+minusOp_carry_i_1: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(4),
+ O => minusOp_carry_i_1_n_0
+ );
+minusOp_carry_i_2: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(3),
+ O => minusOp_carry_i_2_n_0
+ );
+minusOp_carry_i_3: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(2),
+ O => minusOp_carry_i_3_n_0
+ );
+minusOp_carry_i_4: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(1),
+ O => minusOp_carry_i_4_n_0
+ );
+sda_chk_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000100000"
+ )
+ port map (
+ I0 => c_state(4),
+ I1 => c_state(1),
+ I2 => c_state(3),
+ I3 => c_state(0),
+ I4 => c_state(2),
+ I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ O => sda_chk_i_1_n_0
+ );
+sda_chk_reg: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \FSM_sequential_c_state[4]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => sda_chk_i_1_n_0,
+ Q => sda_chk_reg_n_0
+ );
+slave_wait_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0F04"
+ )
+ port map (
+ I0 => dscl_oen,
+ I1 => \^i2c_scl_t\,
+ I2 => sSCL,
+ I3 => slave_wait,
+ O => slave_wait0
+ );
+slave_wait_reg: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => slave_wait0,
+ Q => slave_wait
+ );
+\sr[0]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_0\,
+ I1 => core_rxd,
+ I2 => \txr_reg[6]\(0),
+ I3 => s00_axi_aresetn,
+ O => \sr_reg[0]\(0)
+ );
+\st_irq_block.al_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"AA08"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \st_irq_block.al_reg\,
+ I2 => \cr_reg[7]\(3),
+ I3 => i2c_al,
+ O => al
+ );
+\st_irq_block.irq_flag_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"55540000"
+ )
+ port map (
+ I0 => \cr_reg[0]\,
+ I1 => i2c_al,
+ I2 => cmd_ack,
+ I3 => irq_flag,
+ I4 => s00_axi_aresetn,
+ O => irq_flag1_out
+ );
+\statemachine.ack_out_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"08FF0800"
+ )
+ port map (
+ I0 => core_rxd,
+ I1 => s00_axi_aresetn,
+ I2 => i2c_al,
+ I3 => \statemachine.ack_out_i_2_n_0\,
+ I4 => ack_out,
+ O => \statemachine.ack_out_reg\
+ );
+\statemachine.ack_out_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"DDDDDDDDDDFDDDDD"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => i2c_al,
+ I2 => \out\(2),
+ I3 => \out\(0),
+ I4 => core_ack,
+ I5 => \out\(1),
+ O => \statemachine.ack_out_i_2_n_0\
+ );
+\statemachine.core_cmd[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000100000"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => \out\(0),
+ I2 => \cr_reg[7]\(3),
+ I3 => \out\(1),
+ I4 => s00_axi_aresetn,
+ I5 => i2c_al,
+ O => \statemachine.core_cmd_reg[3]\(0)
+ );
+\statemachine.core_cmd[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000022222E22"
+ )
+ port map (
+ I0 => \FSM_sequential_statemachine.c_state_reg[1]_0\,
+ I1 => \out\(2),
+ I2 => \out\(1),
+ I3 => \cr_reg[7]\(2),
+ I4 => \out\(0),
+ I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ O => \statemachine.core_cmd_reg[3]\(1)
+ );
+\statemachine.core_cmd[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => core_cmd(0),
+ I1 => s00_axi_aresetn,
+ I2 => i2c_al,
+ O => \statemachine.core_cmd_reg[3]\(2)
+ );
+\statemachine.core_cmd[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0040"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => \FSM_sequential_statemachine.c_state_reg[1]\,
+ I2 => s00_axi_aresetn,
+ I3 => i2c_al,
+ O => \statemachine.core_cmd_reg[3]\(3)
+ );
+\statemachine.core_txd_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => core_txd,
+ I1 => s00_axi_aresetn,
+ I2 => i2c_al,
+ O => \statemachine.core_txd_reg\
+ );
+\statemachine.core_txd_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"5455FFFD10002220"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => \out\(0),
+ I2 => ack_in,
+ I3 => core_ack,
+ I4 => \out\(1),
+ I5 => \sr_reg[7]\(0),
+ O => core_txd
+ );
+\statemachine.host_ack_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"000000000000A020"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => \cr_reg[7]\(2),
+ I2 => core_ack,
+ I3 => \out\(0),
+ I4 => \out\(1),
+ I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ O => \statemachine.host_ack_reg\
+ );
+\statemachine.ld_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00000400"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => \FSM_sequential_statemachine.c_state[2]_i_3_n_0\,
+ I2 => \out\(1),
+ I3 => s00_axi_aresetn,
+ I4 => i2c_al,
+ O => \statemachine.ld_reg\
+ );
+\statemachine.shift_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000004440000"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => core_ack,
+ I2 => \out\(0),
+ I3 => cnt_done,
+ I4 => \out\(1),
+ I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ O => \statemachine.shift_reg\
+ );
+\wb_dat_o[6]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"30BB3088"
+ )
+ port map (
+ I0 => \cr_reg[7]\(2),
+ I1 => wb_adr_o(1),
+ I2 => \txr_reg[6]\(1),
+ I3 => wb_adr_o(0),
+ I4 => i2c_busy,
+ O => \wb_dat_o[6]_i_3_n_0\
+ );
+\wb_dat_o_reg[6]_i_1\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \sr_reg[6]\,
+ I1 => \wb_dat_o[6]_i_3_n_0\,
+ O => D(0),
+ S => wb_adr_o(2)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl is
+ port (
+ iscl_oen_reg : out STD_LOGIC;
+ i2c_scl_t : out STD_LOGIC;
+ i2c_sda_t : out STD_LOGIC;
+ irq_flag1_out : out STD_LOGIC;
+ rxack_0 : out STD_LOGIC;
+ al : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ s00_axi_aclk : in STD_LOGIC;
+ s00_axi_aresetn : in STD_LOGIC;
+ \cr_reg[0]\ : in STD_LOGIC;
+ irq_flag : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ \ctr_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ i2c_sda_i : in STD_LOGIC;
+ i2c_scl_i : in STD_LOGIC;
+ \st_irq_block.al_reg\ : in STD_LOGIC;
+ \cr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \cr_reg[0]_0\ : in STD_LOGIC;
+ \cr_reg[1]\ : in STD_LOGIC;
+ \cr_reg[2]\ : in STD_LOGIC;
+ \txr_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ ack_in : in STD_LOGIC;
+ \cr_reg[5]\ : in STD_LOGIC;
+ \cr_reg[7]_0\ : in STD_LOGIC;
+ iack_o_reg : in STD_LOGIC;
+ wb_we_o : in STD_LOGIC;
+ iack_o_reg_0 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl : entity is "i2c_master_byte_ctrl";
+end system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl;
+
+architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl is
+ signal \FSM_sequential_statemachine.c_state[0]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_statemachine.c_state[1]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_statemachine.c_state[2]_i_4_n_0\ : STD_LOGIC;
+ signal ack_out : STD_LOGIC;
+ signal bit_ctrl_n_10 : STD_LOGIC;
+ signal bit_ctrl_n_11 : STD_LOGIC;
+ signal bit_ctrl_n_12 : STD_LOGIC;
+ signal bit_ctrl_n_13 : STD_LOGIC;
+ signal bit_ctrl_n_14 : STD_LOGIC;
+ signal bit_ctrl_n_15 : STD_LOGIC;
+ signal bit_ctrl_n_17 : STD_LOGIC;
+ signal bit_ctrl_n_18 : STD_LOGIC;
+ signal bit_ctrl_n_19 : STD_LOGIC;
+ signal bit_ctrl_n_20 : STD_LOGIC;
+ signal bit_ctrl_n_7 : STD_LOGIC;
+ signal bit_ctrl_n_8 : STD_LOGIC;
+ signal bit_ctrl_n_9 : STD_LOGIC;
+ signal c_state : STD_LOGIC;
+ signal \c_state__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ attribute RTL_KEEP : string;
+ attribute RTL_KEEP of \c_state__0\ : signal is "yes";
+ signal cmd : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal cmd_ack : STD_LOGIC;
+ signal cnt_done : STD_LOGIC;
+ signal core_cmd : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal dcnt : STD_LOGIC;
+ signal \dcnt[0]_i_1_n_0\ : STD_LOGIC;
+ signal \dcnt[1]_i_1_n_0\ : STD_LOGIC;
+ signal \dcnt[2]_i_1_n_0\ : STD_LOGIC;
+ signal \dcnt_reg_n_0_[0]\ : STD_LOGIC;
+ signal \dcnt_reg_n_0_[1]\ : STD_LOGIC;
+ signal \dcnt_reg_n_0_[2]\ : STD_LOGIC;
+ signal dout : STD_LOGIC_VECTOR ( 7 to 7 );
+ signal \^iscl_oen_reg\ : STD_LOGIC;
+ signal \sr[1]_i_1_n_0\ : STD_LOGIC;
+ signal \sr[2]_i_1_n_0\ : STD_LOGIC;
+ signal \sr[3]_i_1_n_0\ : STD_LOGIC;
+ signal \sr[4]_i_1_n_0\ : STD_LOGIC;
+ signal \sr[5]_i_1_n_0\ : STD_LOGIC;
+ signal \sr[6]_i_1_n_0\ : STD_LOGIC;
+ signal \sr[7]_i_2_n_0\ : STD_LOGIC;
+ signal \sr_reg_n_0_[0]\ : STD_LOGIC;
+ signal \sr_reg_n_0_[1]\ : STD_LOGIC;
+ signal \sr_reg_n_0_[2]\ : STD_LOGIC;
+ signal \sr_reg_n_0_[3]\ : STD_LOGIC;
+ signal \sr_reg_n_0_[4]\ : STD_LOGIC;
+ signal \sr_reg_n_0_[5]\ : STD_LOGIC;
+ signal \sr_reg_n_0_[6]\ : STD_LOGIC;
+ signal \statemachine.core_cmd[1]_i_2_n_0\ : STD_LOGIC;
+ signal \statemachine.core_cmd[3]_i_2_n_0\ : STD_LOGIC;
+ signal \statemachine.core_txd_reg_n_0\ : STD_LOGIC;
+ signal \statemachine.ld_reg_n_0\ : STD_LOGIC;
+ signal \statemachine.shift_reg_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[0]_i_2_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[1]_i_2_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[2]_i_2_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[3]_i_2_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[4]_i_2_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[5]_i_2_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[6]_i_2_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[7]_i_2_n_0\ : STD_LOGIC;
+ attribute KEEP : string;
+ attribute KEEP of \FSM_sequential_statemachine.c_state_reg[0]\ : label is "yes";
+ attribute KEEP of \FSM_sequential_statemachine.c_state_reg[1]\ : label is "yes";
+ attribute KEEP of \FSM_sequential_statemachine.c_state_reg[2]\ : label is "yes";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \dcnt[0]_i_1\ : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of \dcnt[1]_i_1\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \dcnt[2]_i_1\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \sr[1]_i_1\ : label is "soft_lutpair22";
+ attribute SOFT_HLUTNM of \sr[2]_i_1\ : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of \st_irq_block.rxack_i_1\ : label is "soft_lutpair22";
+begin
+ iscl_oen_reg <= \^iscl_oen_reg\;
+\FSM_sequential_statemachine.c_state[0]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"43407373"
+ )
+ port map (
+ I0 => cnt_done,
+ I1 => \c_state__0\(1),
+ I2 => \c_state__0\(0),
+ I3 => \cr_reg[7]\(3),
+ I4 => \cr_reg[7]\(1),
+ O => \FSM_sequential_statemachine.c_state[0]_i_2_n_0\
+ );
+\FSM_sequential_statemachine.c_state[1]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"01"
+ )
+ port map (
+ I0 => \dcnt_reg_n_0_[1]\,
+ I1 => \dcnt_reg_n_0_[0]\,
+ I2 => \dcnt_reg_n_0_[2]\,
+ O => cnt_done
+ );
+\FSM_sequential_statemachine.c_state[1]_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FF54"
+ )
+ port map (
+ I0 => \cr_reg[7]\(3),
+ I1 => \cr_reg[7]\(1),
+ I2 => \cr_reg[7]\(0),
+ I3 => \c_state__0\(0),
+ O => \FSM_sequential_statemachine.c_state[1]_i_3_n_0\
+ );
+\FSM_sequential_statemachine.c_state[2]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"888888888888888B"
+ )
+ port map (
+ I0 => cnt_done,
+ I1 => \c_state__0\(1),
+ I2 => \cr_reg[7]\(3),
+ I3 => \cr_reg[7]\(0),
+ I4 => \cr_reg[7]\(1),
+ I5 => \c_state__0\(0),
+ O => \FSM_sequential_statemachine.c_state[2]_i_4_n_0\
+ );
+\FSM_sequential_statemachine.c_state_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => c_state,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_20,
+ Q => \c_state__0\(0)
+ );
+\FSM_sequential_statemachine.c_state_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => c_state,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_19,
+ Q => \c_state__0\(1)
+ );
+\FSM_sequential_statemachine.c_state_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => c_state,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_18,
+ Q => \c_state__0\(2)
+ );
+bit_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_bit_ctrl
+ port map (
+ D(0) => D(6),
+ E(0) => c_state,
+ \FSM_sequential_statemachine.c_state_reg[1]\ => \statemachine.core_cmd[3]_i_2_n_0\,
+ \FSM_sequential_statemachine.c_state_reg[1]_0\ => \statemachine.core_cmd[1]_i_2_n_0\,
+ \FSM_sequential_statemachine.c_state_reg[1]_1\ => \FSM_sequential_statemachine.c_state[0]_i_2_n_0\,
+ \FSM_sequential_statemachine.c_state_reg[1]_2\ => \FSM_sequential_statemachine.c_state[2]_i_4_n_0\,
+ \FSM_sequential_statemachine.c_state_reg[2]\(2) => bit_ctrl_n_18,
+ \FSM_sequential_statemachine.c_state_reg[2]\(1) => bit_ctrl_n_19,
+ \FSM_sequential_statemachine.c_state_reg[2]\(0) => bit_ctrl_n_20,
+ Q(15 downto 0) => Q(15 downto 0),
+ ack_in => ack_in,
+ ack_out => ack_out,
+ al => al,
+ cmd_ack => cmd_ack,
+ cnt_done => cnt_done,
+ core_cmd(0) => core_cmd(2),
+ \cr_reg[0]\ => \cr_reg[0]\,
+ \cr_reg[4]\(0) => E(0),
+ \cr_reg[7]\(3 downto 0) => \cr_reg[7]\(3 downto 0),
+ \cr_reg[7]_0\ => \FSM_sequential_statemachine.c_state[1]_i_3_n_0\,
+ \ctr_reg[7]\(0) => \ctr_reg[7]\(7),
+ i2c_scl_i => i2c_scl_i,
+ i2c_scl_t => i2c_scl_t,
+ i2c_sda_i => i2c_sda_i,
+ i2c_sda_t => i2c_sda_t,
+ iack_o_reg => iack_o_reg,
+ iack_o_reg_0 => iack_o_reg_0,
+ irq_flag => irq_flag,
+ irq_flag1_out => irq_flag1_out,
+ iscl_oen_reg_0 => \^iscl_oen_reg\,
+ \out\(2 downto 0) => \c_state__0\(2 downto 0),
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_aresetn => s00_axi_aresetn,
+ \sr_reg[0]\(0) => bit_ctrl_n_17,
+ \sr_reg[6]\ => \wb_dat_o[6]_i_2_n_0\,
+ \sr_reg[7]\(0) => dout(7),
+ \st_irq_block.al_reg\ => \st_irq_block.al_reg\,
+ \statemachine.ack_out_reg\ => bit_ctrl_n_15,
+ \statemachine.core_cmd_reg[3]\(3) => bit_ctrl_n_7,
+ \statemachine.core_cmd_reg[3]\(2) => bit_ctrl_n_8,
+ \statemachine.core_cmd_reg[3]\(1) => bit_ctrl_n_9,
+ \statemachine.core_cmd_reg[3]\(0) => bit_ctrl_n_10,
+ \statemachine.core_cmd_reg[3]_0\(3 downto 0) => cmd(3 downto 0),
+ \statemachine.core_txd_reg\ => bit_ctrl_n_12,
+ \statemachine.core_txd_reg_0\ => \statemachine.core_txd_reg_n_0\,
+ \statemachine.host_ack_reg\ => bit_ctrl_n_14,
+ \statemachine.ld_reg\ => bit_ctrl_n_11,
+ \statemachine.ld_reg_0\ => \statemachine.ld_reg_n_0\,
+ \statemachine.shift_reg\ => bit_ctrl_n_13,
+ \txr_reg[6]\(1) => \txr_reg[7]\(6),
+ \txr_reg[6]\(0) => \txr_reg[7]\(0),
+ wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
+ wb_we_o => wb_we_o
+ );
+\dcnt[0]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"8A"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \statemachine.ld_reg_n_0\,
+ I2 => \dcnt_reg_n_0_[0]\,
+ O => \dcnt[0]_i_1_n_0\
+ );
+\dcnt[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"A88A"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \statemachine.ld_reg_n_0\,
+ I2 => \dcnt_reg_n_0_[0]\,
+ I3 => \dcnt_reg_n_0_[1]\,
+ O => \dcnt[1]_i_1_n_0\
+ );
+\dcnt[2]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AAA8888A"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \statemachine.ld_reg_n_0\,
+ I2 => \dcnt_reg_n_0_[1]\,
+ I3 => \dcnt_reg_n_0_[0]\,
+ I4 => \dcnt_reg_n_0_[2]\,
+ O => \dcnt[2]_i_1_n_0\
+ );
+\dcnt_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \dcnt[0]_i_1_n_0\,
+ Q => \dcnt_reg_n_0_[0]\
+ );
+\dcnt_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \dcnt[1]_i_1_n_0\,
+ Q => \dcnt_reg_n_0_[1]\
+ );
+\dcnt_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \dcnt[2]_i_1_n_0\,
+ Q => \dcnt_reg_n_0_[2]\
+ );
+\sr[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => \sr_reg_n_0_[0]\,
+ I2 => \txr_reg[7]\(1),
+ I3 => s00_axi_aresetn,
+ O => \sr[1]_i_1_n_0\
+ );
+\sr[2]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => \sr_reg_n_0_[1]\,
+ I2 => \txr_reg[7]\(2),
+ I3 => s00_axi_aresetn,
+ O => \sr[2]_i_1_n_0\
+ );
+\sr[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => \sr_reg_n_0_[2]\,
+ I2 => \txr_reg[7]\(3),
+ I3 => s00_axi_aresetn,
+ O => \sr[3]_i_1_n_0\
+ );
+\sr[4]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => \sr_reg_n_0_[3]\,
+ I2 => \txr_reg[7]\(4),
+ I3 => s00_axi_aresetn,
+ O => \sr[4]_i_1_n_0\
+ );
+\sr[5]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => \sr_reg_n_0_[4]\,
+ I2 => \txr_reg[7]\(5),
+ I3 => s00_axi_aresetn,
+ O => \sr[5]_i_1_n_0\
+ );
+\sr[6]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => \sr_reg_n_0_[5]\,
+ I2 => \txr_reg[7]\(6),
+ I3 => s00_axi_aresetn,
+ O => \sr[6]_i_1_n_0\
+ );
+\sr[7]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"FB"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => s00_axi_aresetn,
+ I2 => \statemachine.shift_reg_n_0\,
+ O => dcnt
+ );
+\sr[7]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => \sr_reg_n_0_[6]\,
+ I2 => \txr_reg[7]\(7),
+ I3 => s00_axi_aresetn,
+ O => \sr[7]_i_2_n_0\
+ );
+\sr_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_17,
+ Q => \sr_reg_n_0_[0]\
+ );
+\sr_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \sr[1]_i_1_n_0\,
+ Q => \sr_reg_n_0_[1]\
+ );
+\sr_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \sr[2]_i_1_n_0\,
+ Q => \sr_reg_n_0_[2]\
+ );
+\sr_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \sr[3]_i_1_n_0\,
+ Q => \sr_reg_n_0_[3]\
+ );
+\sr_reg[4]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \sr[4]_i_1_n_0\,
+ Q => \sr_reg_n_0_[4]\
+ );
+\sr_reg[5]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \sr[5]_i_1_n_0\,
+ Q => \sr_reg_n_0_[5]\
+ );
+\sr_reg[6]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \sr[6]_i_1_n_0\,
+ Q => \sr_reg_n_0_[6]\
+ );
+\sr_reg[7]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \sr[7]_i_2_n_0\,
+ Q => dout(7)
+ );
+\st_irq_block.rxack_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => ack_out,
+ O => rxack_0
+ );
+\statemachine.ack_out_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_15,
+ Q => ack_out
+ );
+\statemachine.core_cmd[1]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00000001"
+ )
+ port map (
+ I0 => \c_state__0\(1),
+ I1 => \c_state__0\(0),
+ I2 => \cr_reg[7]\(3),
+ I3 => \cr_reg[7]\(0),
+ I4 => \cr_reg[7]\(1),
+ O => \statemachine.core_cmd[1]_i_2_n_0\
+ );
+\statemachine.core_cmd[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000F0C40FC4"
+ )
+ port map (
+ I0 => \cr_reg[7]\(3),
+ I1 => \cr_reg[7]\(1),
+ I2 => \c_state__0\(0),
+ I3 => \c_state__0\(1),
+ I4 => cnt_done,
+ I5 => \c_state__0\(2),
+ O => core_cmd(2)
+ );
+\statemachine.core_cmd[3]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4848484878787B78"
+ )
+ port map (
+ I0 => cnt_done,
+ I1 => \c_state__0\(1),
+ I2 => \c_state__0\(0),
+ I3 => \cr_reg[7]\(0),
+ I4 => \cr_reg[7]\(3),
+ I5 => \cr_reg[7]\(1),
+ O => \statemachine.core_cmd[3]_i_2_n_0\
+ );
+\statemachine.core_cmd_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => c_state,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_10,
+ Q => cmd(0)
+ );
+\statemachine.core_cmd_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => c_state,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_9,
+ Q => cmd(1)
+ );
+\statemachine.core_cmd_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => c_state,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_8,
+ Q => cmd(2)
+ );
+\statemachine.core_cmd_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => c_state,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_7,
+ Q => cmd(3)
+ );
+\statemachine.core_txd_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_12,
+ Q => \statemachine.core_txd_reg_n_0\
+ );
+\statemachine.host_ack_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_14,
+ Q => cmd_ack
+ );
+\statemachine.ld_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_11,
+ Q => \statemachine.ld_reg_n_0\
+ );
+\statemachine.shift_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_13,
+ Q => \statemachine.shift_reg_n_0\
+ );
+\wb_dat_o[0]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \sr_reg_n_0_[0]\,
+ I1 => \ctr_reg[7]\(0),
+ I2 => wb_adr_o(1),
+ I3 => Q(8),
+ I4 => wb_adr_o(0),
+ I5 => Q(0),
+ O => \wb_dat_o[0]_i_2_n_0\
+ );
+\wb_dat_o[1]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \sr_reg_n_0_[1]\,
+ I1 => \ctr_reg[7]\(1),
+ I2 => wb_adr_o(1),
+ I3 => Q(9),
+ I4 => wb_adr_o(0),
+ I5 => Q(1),
+ O => \wb_dat_o[1]_i_2_n_0\
+ );
+\wb_dat_o[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"3808FFFF38080000"
+ )
+ port map (
+ I0 => \cr_reg[2]\,
+ I1 => wb_adr_o(1),
+ I2 => wb_adr_o(0),
+ I3 => \txr_reg[7]\(2),
+ I4 => wb_adr_o(2),
+ I5 => \wb_dat_o[2]_i_2_n_0\,
+ O => D(2)
+ );
+\wb_dat_o[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \sr_reg_n_0_[2]\,
+ I1 => \ctr_reg[7]\(2),
+ I2 => wb_adr_o(1),
+ I3 => Q(10),
+ I4 => wb_adr_o(0),
+ I5 => Q(2),
+ O => \wb_dat_o[2]_i_2_n_0\
+ );
+\wb_dat_o[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"3808FFFF38080000"
+ )
+ port map (
+ I0 => ack_in,
+ I1 => wb_adr_o(1),
+ I2 => wb_adr_o(0),
+ I3 => \txr_reg[7]\(3),
+ I4 => wb_adr_o(2),
+ I5 => \wb_dat_o[3]_i_2_n_0\,
+ O => D(3)
+ );
+\wb_dat_o[3]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \sr_reg_n_0_[3]\,
+ I1 => \ctr_reg[7]\(3),
+ I2 => wb_adr_o(1),
+ I3 => Q(11),
+ I4 => wb_adr_o(0),
+ I5 => Q(3),
+ O => \wb_dat_o[3]_i_2_n_0\
+ );
+\wb_dat_o[4]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"3808FFFF38080000"
+ )
+ port map (
+ I0 => \cr_reg[7]\(0),
+ I1 => wb_adr_o(1),
+ I2 => wb_adr_o(0),
+ I3 => \txr_reg[7]\(4),
+ I4 => wb_adr_o(2),
+ I5 => \wb_dat_o[4]_i_2_n_0\,
+ O => D(4)
+ );
+\wb_dat_o[4]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \sr_reg_n_0_[4]\,
+ I1 => \ctr_reg[7]\(4),
+ I2 => wb_adr_o(1),
+ I3 => Q(12),
+ I4 => wb_adr_o(0),
+ I5 => Q(4),
+ O => \wb_dat_o[4]_i_2_n_0\
+ );
+\wb_dat_o[5]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \sr_reg_n_0_[5]\,
+ I1 => \ctr_reg[7]\(5),
+ I2 => wb_adr_o(1),
+ I3 => Q(13),
+ I4 => wb_adr_o(0),
+ I5 => Q(5),
+ O => \wb_dat_o[5]_i_2_n_0\
+ );
+\wb_dat_o[6]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \sr_reg_n_0_[6]\,
+ I1 => \ctr_reg[7]\(6),
+ I2 => wb_adr_o(1),
+ I3 => Q(14),
+ I4 => wb_adr_o(0),
+ I5 => Q(6),
+ O => \wb_dat_o[6]_i_2_n_0\
+ );
+\wb_dat_o[7]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => dout(7),
+ I1 => \ctr_reg[7]\(7),
+ I2 => wb_adr_o(1),
+ I3 => Q(15),
+ I4 => wb_adr_o(0),
+ I5 => Q(7),
+ O => \wb_dat_o[7]_i_2_n_0\
+ );
+\wb_dat_o_reg[0]_i_1\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \wb_dat_o[0]_i_2_n_0\,
+ I1 => \cr_reg[0]_0\,
+ O => D(0),
+ S => wb_adr_o(2)
+ );
+\wb_dat_o_reg[1]_i_1\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \wb_dat_o[1]_i_2_n_0\,
+ I1 => \cr_reg[1]\,
+ O => D(1),
+ S => wb_adr_o(2)
+ );
+\wb_dat_o_reg[5]_i_1\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \wb_dat_o[5]_i_2_n_0\,
+ I1 => \cr_reg[5]\,
+ O => D(5),
+ S => wb_adr_o(2)
+ );
+\wb_dat_o_reg[7]_i_1\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \wb_dat_o[7]_i_2_n_0\,
+ I1 => \cr_reg[7]_0\,
+ O => D(7),
+ S => wb_adr_o(2)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity system_design_axi_wb_i2c_master_0_1_i2c_master_top is
+ port (
+ wb_ack_i : out STD_LOGIC;
+ wb_rst_o : out STD_LOGIC;
+ i2c_scl_t : out STD_LOGIC;
+ axi_int_o : out STD_LOGIC;
+ i2c_sda_t : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 0 to 0 );
+ s_stb_r_reg : out STD_LOGIC;
+ \s_rdata_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \s_rdata_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ s_stb_r_reg_0 : in STD_LOGIC;
+ s00_axi_aclk : in STD_LOGIC;
+ s00_axi_aresetn : in STD_LOGIC;
+ i2c_sda_i : in STD_LOGIC;
+ i2c_scl_i : in STD_LOGIC;
+ s00_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_awvalid : in STD_LOGIC;
+ s00_axi_arvalid : in STD_LOGIC;
+ wb_cyc_o : in STD_LOGIC;
+ wb_we_o : in STD_LOGIC;
+ iack_o_reg_0 : in STD_LOGIC;
+ E : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_we_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
+ s_we_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ D : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \s_addr_reg[4]\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_0_1_i2c_master_top : entity is "i2c_master_top";
+end system_design_axi_wb_i2c_master_0_1_i2c_master_top;
+
+architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_i2c_master_top is
+ signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal ack_in : STD_LOGIC;
+ signal al : STD_LOGIC;
+ signal byte_ctrl_n_14 : STD_LOGIC;
+ signal \cr[0]_i_1_n_0\ : STD_LOGIC;
+ signal \cr[1]_i_1_n_0\ : STD_LOGIC;
+ signal \cr[2]_i_1_n_0\ : STD_LOGIC;
+ signal \cr[3]_i_1_n_0\ : STD_LOGIC;
+ signal \cr_reg_n_0_[0]\ : STD_LOGIC;
+ signal \cr_reg_n_0_[1]\ : STD_LOGIC;
+ signal \cr_reg_n_0_[2]\ : STD_LOGIC;
+ signal ctr : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal \ctr_reg_n_0_[0]\ : STD_LOGIC;
+ signal \ctr_reg_n_0_[1]\ : STD_LOGIC;
+ signal \ctr_reg_n_0_[2]\ : STD_LOGIC;
+ signal \ctr_reg_n_0_[3]\ : STD_LOGIC;
+ signal \ctr_reg_n_0_[4]\ : STD_LOGIC;
+ signal \ctr_reg_n_0_[5]\ : STD_LOGIC;
+ signal data0 : STD_LOGIC_VECTOR ( 13 downto 0 );
+ signal ien : STD_LOGIC;
+ signal irq_flag : STD_LOGIC;
+ signal irq_flag1_out : STD_LOGIC;
+ signal \prer[10]_i_1_n_0\ : STD_LOGIC;
+ signal \prer[11]_i_1_n_0\ : STD_LOGIC;
+ signal \prer[12]_i_1_n_0\ : STD_LOGIC;
+ signal \prer[13]_i_1_n_0\ : STD_LOGIC;
+ signal \prer[14]_i_1_n_0\ : STD_LOGIC;
+ signal \prer[15]_i_2_n_0\ : STD_LOGIC;
+ signal \prer[8]_i_1_n_0\ : STD_LOGIC;
+ signal \prer[9]_i_1_n_0\ : STD_LOGIC;
+ signal \prer_reg_n_0_[0]\ : STD_LOGIC;
+ signal \prer_reg_n_0_[1]\ : STD_LOGIC;
+ signal read : STD_LOGIC;
+ signal rxack : STD_LOGIC;
+ signal rxack_0 : STD_LOGIC;
+ signal \st_irq_block.al_reg_n_0\ : STD_LOGIC;
+ signal \st_irq_block.wb_inta_o_i_1_n_0\ : STD_LOGIC;
+ signal start : STD_LOGIC;
+ signal stop : STD_LOGIC;
+ signal tip : STD_LOGIC;
+ signal tip_1 : STD_LOGIC;
+ signal txr : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal \^wb_ack_i\ : STD_LOGIC;
+ signal wb_dat_o : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal \wb_dat_o[0]_i_3_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[1]_i_3_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[5]_i_3_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[7]_i_3_n_0\ : STD_LOGIC;
+ signal \^wb_rst_o\ : STD_LOGIC;
+ signal write : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair24";
+ attribute SOFT_HLUTNM of \ctr[0]_i_1\ : label is "soft_lutpair26";
+ attribute SOFT_HLUTNM of \ctr[1]_i_1\ : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of \ctr[2]_i_1\ : label is "soft_lutpair28";
+ attribute SOFT_HLUTNM of \ctr[3]_i_1\ : label is "soft_lutpair24";
+ attribute SOFT_HLUTNM of \ctr[4]_i_1\ : label is "soft_lutpair29";
+ attribute SOFT_HLUTNM of \ctr[5]_i_1\ : label is "soft_lutpair30";
+ attribute SOFT_HLUTNM of \ctr[6]_i_1\ : label is "soft_lutpair31";
+ attribute SOFT_HLUTNM of \ctr[7]_i_2\ : label is "soft_lutpair32";
+ attribute SOFT_HLUTNM of \prer[10]_i_1\ : label is "soft_lutpair28";
+ attribute SOFT_HLUTNM of \prer[12]_i_1\ : label is "soft_lutpair29";
+ attribute SOFT_HLUTNM of \prer[13]_i_1\ : label is "soft_lutpair30";
+ attribute SOFT_HLUTNM of \prer[14]_i_1\ : label is "soft_lutpair31";
+ attribute SOFT_HLUTNM of \prer[15]_i_2\ : label is "soft_lutpair32";
+ attribute SOFT_HLUTNM of \prer[8]_i_1\ : label is "soft_lutpair26";
+ attribute SOFT_HLUTNM of \prer[9]_i_1\ : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of \s_rdata[7]_i_1\ : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of s_stb_r_i_1 : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of \st_irq_block.tip_i_1\ : label is "soft_lutpair25";
+ attribute SOFT_HLUTNM of \st_irq_block.wb_inta_o_i_1\ : label is "soft_lutpair25";
+begin
+ Q(0) <= \^q\(0);
+ wb_ack_i <= \^wb_ack_i\;
+ wb_rst_o <= \^wb_rst_o\;
+byte_ctrl: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_byte_ctrl
+ port map (
+ D(7 downto 0) => wb_dat_o(7 downto 0),
+ E(0) => byte_ctrl_n_14,
+ Q(15 downto 2) => data0(13 downto 0),
+ Q(1) => \prer_reg_n_0_[1]\,
+ Q(0) => \prer_reg_n_0_[0]\,
+ ack_in => ack_in,
+ al => al,
+ \cr_reg[0]\ => \cr_reg_n_0_[0]\,
+ \cr_reg[0]_0\ => \wb_dat_o[0]_i_3_n_0\,
+ \cr_reg[1]\ => \wb_dat_o[1]_i_3_n_0\,
+ \cr_reg[2]\ => \cr_reg_n_0_[2]\,
+ \cr_reg[5]\ => \wb_dat_o[5]_i_3_n_0\,
+ \cr_reg[7]\(3) => start,
+ \cr_reg[7]\(2) => stop,
+ \cr_reg[7]\(1) => read,
+ \cr_reg[7]\(0) => write,
+ \cr_reg[7]_0\ => \wb_dat_o[7]_i_3_n_0\,
+ \ctr_reg[7]\(7) => \^q\(0),
+ \ctr_reg[7]\(6) => ien,
+ \ctr_reg[7]\(5) => \ctr_reg_n_0_[5]\,
+ \ctr_reg[7]\(4) => \ctr_reg_n_0_[4]\,
+ \ctr_reg[7]\(3) => \ctr_reg_n_0_[3]\,
+ \ctr_reg[7]\(2) => \ctr_reg_n_0_[2]\,
+ \ctr_reg[7]\(1) => \ctr_reg_n_0_[1]\,
+ \ctr_reg[7]\(0) => \ctr_reg_n_0_[0]\,
+ i2c_scl_i => i2c_scl_i,
+ i2c_scl_t => i2c_scl_t,
+ i2c_sda_i => i2c_sda_i,
+ i2c_sda_t => i2c_sda_t,
+ iack_o_reg => \^wb_ack_i\,
+ iack_o_reg_0 => iack_o_reg_0,
+ irq_flag => irq_flag,
+ irq_flag1_out => irq_flag1_out,
+ iscl_oen_reg => \^wb_rst_o\,
+ rxack_0 => rxack_0,
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_aresetn => s00_axi_aresetn,
+ \st_irq_block.al_reg\ => \st_irq_block.al_reg_n_0\,
+ \txr_reg[7]\(7 downto 0) => txr(7 downto 0),
+ wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
+ wb_we_o => wb_we_o
+ );
+\cr[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8000FFFF80000000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(0),
+ I2 => wb_we_o,
+ I3 => \^wb_ack_i\,
+ I4 => \s_addr_reg[4]\,
+ I5 => \cr_reg_n_0_[0]\,
+ O => \cr[0]_i_1_n_0\
+ );
+\cr[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8000FFFF80000000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(1),
+ I2 => wb_we_o,
+ I3 => \^wb_ack_i\,
+ I4 => \s_addr_reg[4]\,
+ I5 => \cr_reg_n_0_[1]\,
+ O => \cr[1]_i_1_n_0\
+ );
+\cr[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8000FFFF80000000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(2),
+ I2 => wb_we_o,
+ I3 => \^wb_ack_i\,
+ I4 => \s_addr_reg[4]\,
+ I5 => \cr_reg_n_0_[2]\,
+ O => \cr[2]_i_1_n_0\
+ );
+\cr[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"C808"
+ )
+ port map (
+ I0 => s00_axi_wdata(3),
+ I1 => s00_axi_aresetn,
+ I2 => iack_o_reg_0,
+ I3 => ack_in,
+ O => \cr[3]_i_1_n_0\
+ );
+\cr_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => \cr[0]_i_1_n_0\,
+ Q => \cr_reg_n_0_[0]\
+ );
+\cr_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => \cr[1]_i_1_n_0\,
+ Q => \cr_reg_n_0_[1]\
+ );
+\cr_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => \cr[2]_i_1_n_0\,
+ Q => \cr_reg_n_0_[2]\
+ );
+\cr_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => \cr[3]_i_1_n_0\,
+ Q => ack_in
+ );
+\cr_reg[4]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => byte_ctrl_n_14,
+ CLR => \^wb_rst_o\,
+ D => D(0),
+ Q => write
+ );
+\cr_reg[5]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => byte_ctrl_n_14,
+ CLR => \^wb_rst_o\,
+ D => D(1),
+ Q => read
+ );
+\cr_reg[6]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => byte_ctrl_n_14,
+ CLR => \^wb_rst_o\,
+ D => D(2),
+ Q => stop
+ );
+\cr_reg[7]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => byte_ctrl_n_14,
+ CLR => \^wb_rst_o\,
+ D => D(3),
+ Q => start
+ );
+\ctr[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(0),
+ O => ctr(0)
+ );
+\ctr[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(1),
+ O => ctr(1)
+ );
+\ctr[2]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(2),
+ O => ctr(2)
+ );
+\ctr[3]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(3),
+ O => ctr(3)
+ );
+\ctr[4]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(4),
+ O => ctr(4)
+ );
+\ctr[5]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(5),
+ O => ctr(5)
+ );
+\ctr[6]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(6),
+ O => ctr(6)
+ );
+\ctr[7]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(7),
+ O => ctr(7)
+ );
+\ctr_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(0),
+ Q => \ctr_reg_n_0_[0]\
+ );
+\ctr_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(1),
+ Q => \ctr_reg_n_0_[1]\
+ );
+\ctr_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(2),
+ Q => \ctr_reg_n_0_[2]\
+ );
+\ctr_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(3),
+ Q => \ctr_reg_n_0_[3]\
+ );
+\ctr_reg[4]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(4),
+ Q => \ctr_reg_n_0_[4]\
+ );
+\ctr_reg[5]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(5),
+ Q => \ctr_reg_n_0_[5]\
+ );
+\ctr_reg[6]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(6),
+ Q => ien
+ );
+\ctr_reg[7]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(7),
+ Q => \^q\(0)
+ );
+iack_o_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => s_stb_r_reg_0,
+ Q => \^wb_ack_i\,
+ R => '0'
+ );
+\prer[10]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(2),
+ I1 => s00_axi_aresetn,
+ O => \prer[10]_i_1_n_0\
+ );
+\prer[11]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(3),
+ I1 => s00_axi_aresetn,
+ O => \prer[11]_i_1_n_0\
+ );
+\prer[12]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(4),
+ I1 => s00_axi_aresetn,
+ O => \prer[12]_i_1_n_0\
+ );
+\prer[13]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(5),
+ I1 => s00_axi_aresetn,
+ O => \prer[13]_i_1_n_0\
+ );
+\prer[14]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(6),
+ I1 => s00_axi_aresetn,
+ O => \prer[14]_i_1_n_0\
+ );
+\prer[15]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(7),
+ I1 => s00_axi_aresetn,
+ O => \prer[15]_i_2_n_0\
+ );
+\prer[8]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(0),
+ I1 => s00_axi_aresetn,
+ O => \prer[8]_i_1_n_0\
+ );
+\prer[9]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(1),
+ I1 => s00_axi_aresetn,
+ O => \prer[9]_i_1_n_0\
+ );
+\prer_reg[0]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[8]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => \prer_reg_n_0_[0]\
+ );
+\prer_reg[10]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[10]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(8)
+ );
+\prer_reg[11]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[11]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(9)
+ );
+\prer_reg[12]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[12]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(10)
+ );
+\prer_reg[13]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[13]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(11)
+ );
+\prer_reg[14]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[14]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(12)
+ );
+\prer_reg[15]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[15]_i_2_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(13)
+ );
+\prer_reg[1]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[9]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => \prer_reg_n_0_[1]\
+ );
+\prer_reg[2]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[10]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(0)
+ );
+\prer_reg[3]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[11]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(1)
+ );
+\prer_reg[4]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[12]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(2)
+ );
+\prer_reg[5]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[13]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(3)
+ );
+\prer_reg[6]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[14]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(4)
+ );
+\prer_reg[7]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[15]_i_2_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(5)
+ );
+\prer_reg[8]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[8]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(6)
+ );
+\prer_reg[9]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[9]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(7)
+ );
+\s_rdata[7]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^wb_ack_i\,
+ I1 => wb_we_o,
+ O => \s_rdata_reg[0]\(0)
+ );
+s_stb_r_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EFEE"
+ )
+ port map (
+ I0 => s00_axi_awvalid,
+ I1 => s00_axi_arvalid,
+ I2 => \^wb_ack_i\,
+ I3 => wb_cyc_o,
+ O => s_stb_r_reg
+ );
+\st_irq_block.al_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => al,
+ Q => \st_irq_block.al_reg_n_0\
+ );
+\st_irq_block.irq_flag_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => irq_flag1_out,
+ Q => irq_flag
+ );
+\st_irq_block.rxack_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => rxack_0,
+ Q => rxack
+ );
+\st_irq_block.tip_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"A8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => write,
+ I2 => read,
+ O => tip_1
+ );
+\st_irq_block.tip_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => tip_1,
+ Q => tip
+ );
+\st_irq_block.wb_inta_o_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"80"
+ )
+ port map (
+ I0 => irq_flag,
+ I1 => s00_axi_aresetn,
+ I2 => ien,
+ O => \st_irq_block.wb_inta_o_i_1_n_0\
+ );
+\st_irq_block.wb_inta_o_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => \st_irq_block.wb_inta_o_i_1_n_0\,
+ Q => axi_int_o
+ );
+\txr_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(0),
+ Q => txr(0)
+ );
+\txr_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(1),
+ Q => txr(1)
+ );
+\txr_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(2),
+ Q => txr(2)
+ );
+\txr_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(3),
+ Q => txr(3)
+ );
+\txr_reg[4]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(4),
+ Q => txr(4)
+ );
+\txr_reg[5]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(5),
+ Q => txr(5)
+ );
+\txr_reg[6]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(6),
+ Q => txr(6)
+ );
+\txr_reg[7]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(7),
+ Q => txr(7)
+ );
+\wb_dat_o[0]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"30BB3088"
+ )
+ port map (
+ I0 => \cr_reg_n_0_[0]\,
+ I1 => wb_adr_o(1),
+ I2 => txr(0),
+ I3 => wb_adr_o(0),
+ I4 => irq_flag,
+ O => \wb_dat_o[0]_i_3_n_0\
+ );
+\wb_dat_o[1]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"30BB3088"
+ )
+ port map (
+ I0 => \cr_reg_n_0_[1]\,
+ I1 => wb_adr_o(1),
+ I2 => txr(1),
+ I3 => wb_adr_o(0),
+ I4 => tip,
+ O => \wb_dat_o[1]_i_3_n_0\
+ );
+\wb_dat_o[5]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"30BB3088"
+ )
+ port map (
+ I0 => read,
+ I1 => wb_adr_o(1),
+ I2 => txr(5),
+ I3 => wb_adr_o(0),
+ I4 => \st_irq_block.al_reg_n_0\,
+ O => \wb_dat_o[5]_i_3_n_0\
+ );
+\wb_dat_o[7]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"30BB3088"
+ )
+ port map (
+ I0 => start,
+ I1 => wb_adr_o(1),
+ I2 => txr(7),
+ I3 => wb_adr_o(0),
+ I4 => rxack,
+ O => \wb_dat_o[7]_i_3_n_0\
+ );
+\wb_dat_o_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(0),
+ Q => \s_rdata_reg[7]\(0),
+ R => '0'
+ );
+\wb_dat_o_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(1),
+ Q => \s_rdata_reg[7]\(1),
+ R => '0'
+ );
+\wb_dat_o_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(2),
+ Q => \s_rdata_reg[7]\(2),
+ R => '0'
+ );
+\wb_dat_o_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(3),
+ Q => \s_rdata_reg[7]\(3),
+ R => '0'
+ );
+\wb_dat_o_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(4),
+ Q => \s_rdata_reg[7]\(4),
+ R => '0'
+ );
+\wb_dat_o_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(5),
+ Q => \s_rdata_reg[7]\(5),
+ R => '0'
+ );
+\wb_dat_o_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(6),
+ Q => \s_rdata_reg[7]\(6),
+ R => '0'
+ );
+\wb_dat_o_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(7),
+ Q => \s_rdata_reg[7]\(7),
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master is
+ port (
+ i2c_scl_i : in STD_LOGIC;
+ i2c_scl_o : out STD_LOGIC;
+ i2c_scl_t : out STD_LOGIC;
+ i2c_sda_i : in STD_LOGIC;
+ i2c_sda_o : out STD_LOGIC;
+ i2c_sda_t : out STD_LOGIC;
+ axi_int_o : out STD_LOGIC;
+ s00_axi_aclk : in STD_LOGIC;
+ s00_axi_aresetn : in STD_LOGIC;
+ s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_awvalid : in STD_LOGIC;
+ s00_axi_awready : out STD_LOGIC;
+ s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s00_axi_wvalid : in STD_LOGIC;
+ s00_axi_wready : out STD_LOGIC;
+ s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s00_axi_bvalid : out STD_LOGIC;
+ s00_axi_bready : in STD_LOGIC;
+ s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_arvalid : in STD_LOGIC;
+ s00_axi_arready : out STD_LOGIC;
+ s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s00_axi_rvalid : out STD_LOGIC;
+ s00_axi_rready : in STD_LOGIC
+ );
+ attribute C_S00_AXI_ADDR_WIDTH : integer;
+ attribute C_S00_AXI_ADDR_WIDTH of system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master : entity is 32;
+ attribute C_S00_AXI_DATA_WIDTH : integer;
+ attribute C_S00_AXI_DATA_WIDTH of system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master : entity is 32;
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master : entity is "axi_wb_i2c_master";
+end system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master;
+
+architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master is
+ signal \<const0>\ : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_11 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_12 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_13 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_14 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_15 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_16 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_17 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_18 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_19 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_21 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_7 : STD_LOGIC;
+ signal cmp_i2c_master_top_n_6 : STD_LOGIC;
+ signal cmp_i2c_master_top_n_7 : STD_LOGIC;
+ signal ena : STD_LOGIC;
+ signal \^s00_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal \^s00_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal wb_ack_i : STD_LOGIC;
+ signal wb_adr_o : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal wb_cyc_o : STD_LOGIC;
+ signal wb_dat_o : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal wb_rst_o : STD_LOGIC;
+ signal wb_we_o : STD_LOGIC;
+begin
+ i2c_scl_o <= \<const0>\;
+ i2c_sda_o <= \<const0>\;
+ s00_axi_bresp(1) <= \^s00_axi_bresp\(1);
+ s00_axi_bresp(0) <= \<const0>\;
+ s00_axi_rdata(31) <= \<const0>\;
+ s00_axi_rdata(30) <= \<const0>\;
+ s00_axi_rdata(29) <= \<const0>\;
+ s00_axi_rdata(28) <= \<const0>\;
+ s00_axi_rdata(27) <= \<const0>\;
+ s00_axi_rdata(26) <= \<const0>\;
+ s00_axi_rdata(25) <= \<const0>\;
+ s00_axi_rdata(24) <= \<const0>\;
+ s00_axi_rdata(23) <= \<const0>\;
+ s00_axi_rdata(22) <= \<const0>\;
+ s00_axi_rdata(21) <= \<const0>\;
+ s00_axi_rdata(20) <= \<const0>\;
+ s00_axi_rdata(19) <= \<const0>\;
+ s00_axi_rdata(18) <= \<const0>\;
+ s00_axi_rdata(17) <= \<const0>\;
+ s00_axi_rdata(16) <= \<const0>\;
+ s00_axi_rdata(15) <= \<const0>\;
+ s00_axi_rdata(14) <= \<const0>\;
+ s00_axi_rdata(13) <= \<const0>\;
+ s00_axi_rdata(12) <= \<const0>\;
+ s00_axi_rdata(11) <= \<const0>\;
+ s00_axi_rdata(10) <= \<const0>\;
+ s00_axi_rdata(9) <= \<const0>\;
+ s00_axi_rdata(8) <= \<const0>\;
+ s00_axi_rdata(7 downto 0) <= \^s00_axi_rdata\(7 downto 0);
+ s00_axi_rresp(1) <= \<const0>\;
+ s00_axi_rresp(0) <= \<const0>\;
+GND: unisim.vcomponents.GND
+ port map (
+ G => \<const0>\
+ );
+cmp_axis_wbm_bridge: entity work.system_design_axi_wb_i2c_master_0_1_axis_wbm_bridge
+ port map (
+ D(3) => cmp_axis_wbm_bridge_n_12,
+ D(2) => cmp_axis_wbm_bridge_n_13,
+ D(1) => cmp_axis_wbm_bridge_n_14,
+ D(0) => cmp_axis_wbm_bridge_n_15,
+ E(0) => cmp_axis_wbm_bridge_n_11,
+ Q(0) => ena,
+ \cr_reg[2]\ => cmp_axis_wbm_bridge_n_7,
+ \cr_reg[4]\ => cmp_axis_wbm_bridge_n_16,
+ \ctr_reg[0]\(0) => cmp_axis_wbm_bridge_n_19,
+ iack_o_reg => cmp_axis_wbm_bridge_n_21,
+ iack_o_reg_0 => cmp_i2c_master_top_n_6,
+ iack_o_reg_1(0) => cmp_i2c_master_top_n_7,
+ \prer_reg[8]\(1) => cmp_axis_wbm_bridge_n_17,
+ \prer_reg[8]\(0) => cmp_axis_wbm_bridge_n_18,
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_araddr(2 downto 0) => s00_axi_araddr(4 downto 2),
+ s00_axi_aresetn => s00_axi_aresetn,
+ s00_axi_arready => s00_axi_arready,
+ s00_axi_arvalid => s00_axi_arvalid,
+ s00_axi_awaddr(2 downto 0) => s00_axi_awaddr(4 downto 2),
+ s00_axi_awready => s00_axi_awready,
+ s00_axi_awvalid => s00_axi_awvalid,
+ s00_axi_bready => s00_axi_bready,
+ s00_axi_bresp(0) => \^s00_axi_bresp\(1),
+ s00_axi_bvalid => s00_axi_bvalid,
+ s00_axi_rdata(7 downto 0) => \^s00_axi_rdata\(7 downto 0),
+ s00_axi_rready => s00_axi_rready,
+ s00_axi_rvalid => s00_axi_rvalid,
+ s00_axi_wdata(3 downto 0) => s00_axi_wdata(7 downto 4),
+ s00_axi_wready => s00_axi_wready,
+ s00_axi_wvalid => s00_axi_wvalid,
+ wb_ack_i => wb_ack_i,
+ wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
+ wb_cyc_o => wb_cyc_o,
+ \wb_dat_o_reg[7]\(7 downto 0) => wb_dat_o(7 downto 0),
+ wb_rst_o => wb_rst_o,
+ wb_we_o => wb_we_o
+ );
+cmp_i2c_master_top: entity work.system_design_axi_wb_i2c_master_0_1_i2c_master_top
+ port map (
+ D(3) => cmp_axis_wbm_bridge_n_12,
+ D(2) => cmp_axis_wbm_bridge_n_13,
+ D(1) => cmp_axis_wbm_bridge_n_14,
+ D(0) => cmp_axis_wbm_bridge_n_15,
+ E(1) => cmp_axis_wbm_bridge_n_17,
+ E(0) => cmp_axis_wbm_bridge_n_18,
+ Q(0) => ena,
+ axi_int_o => axi_int_o,
+ i2c_scl_i => i2c_scl_i,
+ i2c_scl_t => i2c_scl_t,
+ i2c_sda_i => i2c_sda_i,
+ i2c_sda_t => i2c_sda_t,
+ iack_o_reg_0 => cmp_axis_wbm_bridge_n_16,
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_aresetn => s00_axi_aresetn,
+ s00_axi_arvalid => s00_axi_arvalid,
+ s00_axi_awvalid => s00_axi_awvalid,
+ s00_axi_wdata(7 downto 0) => s00_axi_wdata(7 downto 0),
+ \s_addr_reg[4]\ => cmp_axis_wbm_bridge_n_7,
+ \s_rdata_reg[0]\(0) => cmp_i2c_master_top_n_7,
+ \s_rdata_reg[7]\(7 downto 0) => wb_dat_o(7 downto 0),
+ s_stb_r_reg => cmp_i2c_master_top_n_6,
+ s_stb_r_reg_0 => cmp_axis_wbm_bridge_n_21,
+ s_we_r_reg(0) => cmp_axis_wbm_bridge_n_19,
+ s_we_r_reg_0(0) => cmp_axis_wbm_bridge_n_11,
+ wb_ack_i => wb_ack_i,
+ wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
+ wb_cyc_o => wb_cyc_o,
+ wb_rst_o => wb_rst_o,
+ wb_we_o => wb_we_o
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity system_design_axi_wb_i2c_master_0_1 is
+ port (
+ i2c_scl_i : in STD_LOGIC;
+ i2c_scl_o : out STD_LOGIC;
+ i2c_scl_t : out STD_LOGIC;
+ i2c_sda_i : in STD_LOGIC;
+ i2c_sda_o : out STD_LOGIC;
+ i2c_sda_t : out STD_LOGIC;
+ axi_int_o : out STD_LOGIC;
+ s00_axi_aclk : in STD_LOGIC;
+ s00_axi_aresetn : in STD_LOGIC;
+ s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_awvalid : in STD_LOGIC;
+ s00_axi_awready : out STD_LOGIC;
+ s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s00_axi_wvalid : in STD_LOGIC;
+ s00_axi_wready : out STD_LOGIC;
+ s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s00_axi_bvalid : out STD_LOGIC;
+ s00_axi_bready : in STD_LOGIC;
+ s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_arvalid : in STD_LOGIC;
+ s00_axi_arready : out STD_LOGIC;
+ s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s00_axi_rvalid : out STD_LOGIC;
+ s00_axi_rready : in STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of system_design_axi_wb_i2c_master_0_1 : entity is true;
+ attribute CHECK_LICENSE_TYPE : string;
+ attribute CHECK_LICENSE_TYPE of system_design_axi_wb_i2c_master_0_1 : entity is "system_design_axi_wb_i2c_master_0_1,axi_wb_i2c_master,{}";
+ attribute downgradeipidentifiedwarnings : string;
+ attribute downgradeipidentifiedwarnings of system_design_axi_wb_i2c_master_0_1 : entity is "yes";
+ attribute x_core_info : string;
+ attribute x_core_info of system_design_axi_wb_i2c_master_0_1 : entity is "axi_wb_i2c_master,Vivado 2016.2";
+end system_design_axi_wb_i2c_master_0_1;
+
+architecture STRUCTURE of system_design_axi_wb_i2c_master_0_1 is
+ attribute C_S00_AXI_ADDR_WIDTH : integer;
+ attribute C_S00_AXI_ADDR_WIDTH of U0 : label is 32;
+ attribute C_S00_AXI_DATA_WIDTH : integer;
+ attribute C_S00_AXI_DATA_WIDTH of U0 : label is 32;
+begin
+U0: entity work.system_design_axi_wb_i2c_master_0_1_axi_wb_i2c_master
+ port map (
+ axi_int_o => axi_int_o,
+ i2c_scl_i => i2c_scl_i,
+ i2c_scl_o => i2c_scl_o,
+ i2c_scl_t => i2c_scl_t,
+ i2c_sda_i => i2c_sda_i,
+ i2c_sda_o => i2c_sda_o,
+ i2c_sda_t => i2c_sda_t,
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_araddr(31 downto 0) => s00_axi_araddr(31 downto 0),
+ s00_axi_aresetn => s00_axi_aresetn,
+ s00_axi_arprot(2 downto 0) => s00_axi_arprot(2 downto 0),
+ s00_axi_arready => s00_axi_arready,
+ s00_axi_arvalid => s00_axi_arvalid,
+ s00_axi_awaddr(31 downto 0) => s00_axi_awaddr(31 downto 0),
+ s00_axi_awprot(2 downto 0) => s00_axi_awprot(2 downto 0),
+ s00_axi_awready => s00_axi_awready,
+ s00_axi_awvalid => s00_axi_awvalid,
+ s00_axi_bready => s00_axi_bready,
+ s00_axi_bresp(1 downto 0) => s00_axi_bresp(1 downto 0),
+ s00_axi_bvalid => s00_axi_bvalid,
+ s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
+ s00_axi_rready => s00_axi_rready,
+ s00_axi_rresp(1 downto 0) => s00_axi_rresp(1 downto 0),
+ s00_axi_rvalid => s00_axi_rvalid,
+ s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
+ s00_axi_wready => s00_axi_wready,
+ s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
+ s00_axi_wvalid => s00_axi_wvalid
+ );
+end STRUCTURE;
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v
new file mode 100644
index 00000000..5fdb044f
--- /dev/null
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v
@@ -0,0 +1,4084 @@
+// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
+// Date : Wed Oct 11 14:52:21 2017
+// Host : lapte24154 running 64-bit openSUSE Leap 42.2
+// Command : write_verilog -force -mode funcsim
+// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.v
+// Design : system_design_axi_wb_i2c_master_2_0
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7z030ffg676-2
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "system_design_axi_wb_i2c_master_2_0,axi_wb_i2c_master,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_wb_i2c_master,Vivado 2016.2" *)
+(* NotValidForBitStream *)
+module system_design_axi_wb_i2c_master_2_0
+ (i2c_scl_i,
+ i2c_scl_o,
+ i2c_scl_t,
+ i2c_sda_i,
+ i2c_sda_o,
+ i2c_sda_t,
+ axi_int_o,
+ s00_axi_aclk,
+ s00_axi_aresetn,
+ s00_axi_awaddr,
+ s00_axi_awprot,
+ s00_axi_awvalid,
+ s00_axi_awready,
+ s00_axi_wdata,
+ s00_axi_wstrb,
+ s00_axi_wvalid,
+ s00_axi_wready,
+ s00_axi_bresp,
+ s00_axi_bvalid,
+ s00_axi_bready,
+ s00_axi_araddr,
+ s00_axi_arprot,
+ s00_axi_arvalid,
+ s00_axi_arready,
+ s00_axi_rdata,
+ s00_axi_rresp,
+ s00_axi_rvalid,
+ s00_axi_rready);
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 i2c_master SCL_I" *) input i2c_scl_i;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 i2c_master SCL_O" *) output i2c_scl_o;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 i2c_master SCL_T" *) output i2c_scl_t;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 i2c_master SDA_I" *) input i2c_sda_i;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 i2c_master SDA_O" *) output i2c_sda_o;
+ (* x_interface_info = "xilinx.com:interface:iic:1.0 i2c_master SDA_T" *) output i2c_sda_t;
+ output axi_int_o;
+ (* x_interface_info = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *) input s00_axi_aclk;
+ (* x_interface_info = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *) input s00_axi_aresetn;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *) input [31:0]s00_axi_awaddr;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *) input [2:0]s00_axi_awprot;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *) input s00_axi_awvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *) output s00_axi_awready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *) input [31:0]s00_axi_wdata;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *) input [3:0]s00_axi_wstrb;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *) input s00_axi_wvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *) output s00_axi_wready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *) output [1:0]s00_axi_bresp;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *) output s00_axi_bvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *) input s00_axi_bready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *) input [31:0]s00_axi_araddr;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *) input [2:0]s00_axi_arprot;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *) input s00_axi_arvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *) output s00_axi_arready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *) output [31:0]s00_axi_rdata;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *) output [1:0]s00_axi_rresp;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *) output s00_axi_rvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *) input s00_axi_rready;
+
+ wire axi_int_o;
+ wire i2c_scl_i;
+ wire i2c_scl_o;
+ wire i2c_scl_t;
+ wire i2c_sda_i;
+ wire i2c_sda_o;
+ wire i2c_sda_t;
+ wire s00_axi_aclk;
+ wire [31:0]s00_axi_araddr;
+ wire s00_axi_aresetn;
+ wire [2:0]s00_axi_arprot;
+ wire s00_axi_arready;
+ wire s00_axi_arvalid;
+ wire [31:0]s00_axi_awaddr;
+ wire [2:0]s00_axi_awprot;
+ wire s00_axi_awready;
+ wire s00_axi_awvalid;
+ wire s00_axi_bready;
+ wire [1:0]s00_axi_bresp;
+ wire s00_axi_bvalid;
+ wire [31:0]s00_axi_rdata;
+ wire s00_axi_rready;
+ wire [1:0]s00_axi_rresp;
+ wire s00_axi_rvalid;
+ wire [31:0]s00_axi_wdata;
+ wire s00_axi_wready;
+ wire [3:0]s00_axi_wstrb;
+ wire s00_axi_wvalid;
+
+ (* C_S00_AXI_ADDR_WIDTH = "32" *)
+ (* C_S00_AXI_DATA_WIDTH = "32" *)
+ system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master U0
+ (.axi_int_o(axi_int_o),
+ .i2c_scl_i(i2c_scl_i),
+ .i2c_scl_o(i2c_scl_o),
+ .i2c_scl_t(i2c_scl_t),
+ .i2c_sda_i(i2c_sda_i),
+ .i2c_sda_o(i2c_sda_o),
+ .i2c_sda_t(i2c_sda_t),
+ .s00_axi_aclk(s00_axi_aclk),
+ .s00_axi_araddr(s00_axi_araddr),
+ .s00_axi_aresetn(s00_axi_aresetn),
+ .s00_axi_arprot(s00_axi_arprot),
+ .s00_axi_arready(s00_axi_arready),
+ .s00_axi_arvalid(s00_axi_arvalid),
+ .s00_axi_awaddr(s00_axi_awaddr),
+ .s00_axi_awprot(s00_axi_awprot),
+ .s00_axi_awready(s00_axi_awready),
+ .s00_axi_awvalid(s00_axi_awvalid),
+ .s00_axi_bready(s00_axi_bready),
+ .s00_axi_bresp(s00_axi_bresp),
+ .s00_axi_bvalid(s00_axi_bvalid),
+ .s00_axi_rdata(s00_axi_rdata),
+ .s00_axi_rready(s00_axi_rready),
+ .s00_axi_rresp(s00_axi_rresp),
+ .s00_axi_rvalid(s00_axi_rvalid),
+ .s00_axi_wdata(s00_axi_wdata),
+ .s00_axi_wready(s00_axi_wready),
+ .s00_axi_wstrb(s00_axi_wstrb),
+ .s00_axi_wvalid(s00_axi_wvalid));
+endmodule
+
+(* C_S00_AXI_ADDR_WIDTH = "32" *) (* C_S00_AXI_DATA_WIDTH = "32" *) (* ORIG_REF_NAME = "axi_wb_i2c_master" *)
+module system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master
+ (i2c_scl_i,
+ i2c_scl_o,
+ i2c_scl_t,
+ i2c_sda_i,
+ i2c_sda_o,
+ i2c_sda_t,
+ axi_int_o,
+ s00_axi_aclk,
+ s00_axi_aresetn,
+ s00_axi_awaddr,
+ s00_axi_awprot,
+ s00_axi_awvalid,
+ s00_axi_awready,
+ s00_axi_wdata,
+ s00_axi_wstrb,
+ s00_axi_wvalid,
+ s00_axi_wready,
+ s00_axi_bresp,
+ s00_axi_bvalid,
+ s00_axi_bready,
+ s00_axi_araddr,
+ s00_axi_arprot,
+ s00_axi_arvalid,
+ s00_axi_arready,
+ s00_axi_rdata,
+ s00_axi_rresp,
+ s00_axi_rvalid,
+ s00_axi_rready);
+ input i2c_scl_i;
+ output i2c_scl_o;
+ output i2c_scl_t;
+ input i2c_sda_i;
+ output i2c_sda_o;
+ output i2c_sda_t;
+ output axi_int_o;
+ input s00_axi_aclk;
+ input s00_axi_aresetn;
+ input [31:0]s00_axi_awaddr;
+ input [2:0]s00_axi_awprot;
+ input s00_axi_awvalid;
+ output s00_axi_awready;
+ input [31:0]s00_axi_wdata;
+ input [3:0]s00_axi_wstrb;
+ input s00_axi_wvalid;
+ output s00_axi_wready;
+ output [1:0]s00_axi_bresp;
+ output s00_axi_bvalid;
+ input s00_axi_bready;
+ input [31:0]s00_axi_araddr;
+ input [2:0]s00_axi_arprot;
+ input s00_axi_arvalid;
+ output s00_axi_arready;
+ output [31:0]s00_axi_rdata;
+ output [1:0]s00_axi_rresp;
+ output s00_axi_rvalid;
+ input s00_axi_rready;
+
+ wire \<const0> ;
+ wire axi_int_o;
+ wire cmp_axis_wbm_bridge_n_11;
+ wire cmp_axis_wbm_bridge_n_12;
+ wire cmp_axis_wbm_bridge_n_13;
+ wire cmp_axis_wbm_bridge_n_14;
+ wire cmp_axis_wbm_bridge_n_15;
+ wire cmp_axis_wbm_bridge_n_16;
+ wire cmp_axis_wbm_bridge_n_17;
+ wire cmp_axis_wbm_bridge_n_18;
+ wire cmp_axis_wbm_bridge_n_19;
+ wire cmp_axis_wbm_bridge_n_21;
+ wire cmp_axis_wbm_bridge_n_7;
+ wire cmp_i2c_master_top_n_6;
+ wire cmp_i2c_master_top_n_7;
+ wire ena;
+ wire i2c_scl_i;
+ wire i2c_scl_t;
+ wire i2c_sda_i;
+ wire i2c_sda_t;
+ wire s00_axi_aclk;
+ wire [31:0]s00_axi_araddr;
+ wire s00_axi_aresetn;
+ wire s00_axi_arready;
+ wire s00_axi_arvalid;
+ wire [31:0]s00_axi_awaddr;
+ wire s00_axi_awready;
+ wire s00_axi_awvalid;
+ wire s00_axi_bready;
+ wire [1:1]\^s00_axi_bresp ;
+ wire s00_axi_bvalid;
+ wire [7:0]\^s00_axi_rdata ;
+ wire s00_axi_rready;
+ wire s00_axi_rvalid;
+ wire [31:0]s00_axi_wdata;
+ wire s00_axi_wready;
+ wire s00_axi_wvalid;
+ wire wb_ack_i;
+ wire [2:0]wb_adr_o;
+ wire wb_cyc_o;
+ wire [7:0]wb_dat_o;
+ wire wb_rst_o;
+ wire wb_we_o;
+
+ assign i2c_scl_o = \<const0> ;
+ assign i2c_sda_o = \<const0> ;
+ assign s00_axi_bresp[1] = \^s00_axi_bresp [1];
+ assign s00_axi_bresp[0] = \<const0> ;
+ assign s00_axi_rdata[31] = \<const0> ;
+ assign s00_axi_rdata[30] = \<const0> ;
+ assign s00_axi_rdata[29] = \<const0> ;
+ assign s00_axi_rdata[28] = \<const0> ;
+ assign s00_axi_rdata[27] = \<const0> ;
+ assign s00_axi_rdata[26] = \<const0> ;
+ assign s00_axi_rdata[25] = \<const0> ;
+ assign s00_axi_rdata[24] = \<const0> ;
+ assign s00_axi_rdata[23] = \<const0> ;
+ assign s00_axi_rdata[22] = \<const0> ;
+ assign s00_axi_rdata[21] = \<const0> ;
+ assign s00_axi_rdata[20] = \<const0> ;
+ assign s00_axi_rdata[19] = \<const0> ;
+ assign s00_axi_rdata[18] = \<const0> ;
+ assign s00_axi_rdata[17] = \<const0> ;
+ assign s00_axi_rdata[16] = \<const0> ;
+ assign s00_axi_rdata[15] = \<const0> ;
+ assign s00_axi_rdata[14] = \<const0> ;
+ assign s00_axi_rdata[13] = \<const0> ;
+ assign s00_axi_rdata[12] = \<const0> ;
+ assign s00_axi_rdata[11] = \<const0> ;
+ assign s00_axi_rdata[10] = \<const0> ;
+ assign s00_axi_rdata[9] = \<const0> ;
+ assign s00_axi_rdata[8] = \<const0> ;
+ assign s00_axi_rdata[7:0] = \^s00_axi_rdata [7:0];
+ assign s00_axi_rresp[1] = \<const0> ;
+ assign s00_axi_rresp[0] = \<const0> ;
+ GND GND
+ (.G(\<const0> ));
+ system_design_axi_wb_i2c_master_2_0_axis_wbm_bridge cmp_axis_wbm_bridge
+ (.D({cmp_axis_wbm_bridge_n_12,cmp_axis_wbm_bridge_n_13,cmp_axis_wbm_bridge_n_14,cmp_axis_wbm_bridge_n_15}),
+ .E(cmp_axis_wbm_bridge_n_11),
+ .Q(ena),
+ .\cr_reg[2] (cmp_axis_wbm_bridge_n_7),
+ .\cr_reg[4] (cmp_axis_wbm_bridge_n_16),
+ .\ctr_reg[0] (cmp_axis_wbm_bridge_n_19),
+ .iack_o_reg(cmp_axis_wbm_bridge_n_21),
+ .iack_o_reg_0(cmp_i2c_master_top_n_6),
+ .iack_o_reg_1(cmp_i2c_master_top_n_7),
+ .\prer_reg[8] ({cmp_axis_wbm_bridge_n_17,cmp_axis_wbm_bridge_n_18}),
+ .s00_axi_aclk(s00_axi_aclk),
+ .s00_axi_araddr(s00_axi_araddr[4:2]),
+ .s00_axi_aresetn(s00_axi_aresetn),
+ .s00_axi_arready(s00_axi_arready),
+ .s00_axi_arvalid(s00_axi_arvalid),
+ .s00_axi_awaddr(s00_axi_awaddr[4:2]),
+ .s00_axi_awready(s00_axi_awready),
+ .s00_axi_awvalid(s00_axi_awvalid),
+ .s00_axi_bready(s00_axi_bready),
+ .s00_axi_bresp(\^s00_axi_bresp ),
+ .s00_axi_bvalid(s00_axi_bvalid),
+ .s00_axi_rdata(\^s00_axi_rdata ),
+ .s00_axi_rready(s00_axi_rready),
+ .s00_axi_rvalid(s00_axi_rvalid),
+ .s00_axi_wdata(s00_axi_wdata[7:4]),
+ .s00_axi_wready(s00_axi_wready),
+ .s00_axi_wvalid(s00_axi_wvalid),
+ .wb_ack_i(wb_ack_i),
+ .wb_adr_o(wb_adr_o),
+ .wb_cyc_o(wb_cyc_o),
+ .\wb_dat_o_reg[7] (wb_dat_o),
+ .wb_rst_o(wb_rst_o),
+ .wb_we_o(wb_we_o));
+ system_design_axi_wb_i2c_master_2_0_i2c_master_top cmp_i2c_master_top
+ (.D({cmp_axis_wbm_bridge_n_12,cmp_axis_wbm_bridge_n_13,cmp_axis_wbm_bridge_n_14,cmp_axis_wbm_bridge_n_15}),
+ .E({cmp_axis_wbm_bridge_n_17,cmp_axis_wbm_bridge_n_18}),
+ .Q(ena),
+ .axi_int_o(axi_int_o),
+ .i2c_scl_i(i2c_scl_i),
+ .i2c_scl_t(i2c_scl_t),
+ .i2c_sda_i(i2c_sda_i),
+ .i2c_sda_t(i2c_sda_t),
+ .iack_o_reg_0(cmp_axis_wbm_bridge_n_16),
+ .s00_axi_aclk(s00_axi_aclk),
+ .s00_axi_aresetn(s00_axi_aresetn),
+ .s00_axi_arvalid(s00_axi_arvalid),
+ .s00_axi_awvalid(s00_axi_awvalid),
+ .s00_axi_wdata(s00_axi_wdata[7:0]),
+ .\s_addr_reg[4] (cmp_axis_wbm_bridge_n_7),
+ .\s_rdata_reg[0] (cmp_i2c_master_top_n_7),
+ .\s_rdata_reg[7] (wb_dat_o),
+ .s_stb_r_reg(cmp_i2c_master_top_n_6),
+ .s_stb_r_reg_0(cmp_axis_wbm_bridge_n_21),
+ .s_we_r_reg(cmp_axis_wbm_bridge_n_19),
+ .s_we_r_reg_0(cmp_axis_wbm_bridge_n_11),
+ .wb_ack_i(wb_ack_i),
+ .wb_adr_o(wb_adr_o),
+ .wb_cyc_o(wb_cyc_o),
+ .wb_rst_o(wb_rst_o),
+ .wb_we_o(wb_we_o));
+endmodule
+
+(* ORIG_REF_NAME = "axis_wbm_bridge" *)
+module system_design_axi_wb_i2c_master_2_0_axis_wbm_bridge
+ (s00_axi_awready,
+ s00_axi_wready,
+ s00_axi_arready,
+ wb_we_o,
+ wb_cyc_o,
+ s00_axi_bresp,
+ s00_axi_bvalid,
+ \cr_reg[2] ,
+ wb_adr_o,
+ E,
+ D,
+ \cr_reg[4] ,
+ \prer_reg[8] ,
+ \ctr_reg[0] ,
+ s00_axi_rvalid,
+ iack_o_reg,
+ s00_axi_rdata,
+ wb_rst_o,
+ s00_axi_aclk,
+ iack_o_reg_0,
+ Q,
+ s00_axi_aresetn,
+ wb_ack_i,
+ s00_axi_awvalid,
+ s00_axi_arvalid,
+ s00_axi_bready,
+ s00_axi_rready,
+ s00_axi_wvalid,
+ s00_axi_wdata,
+ s00_axi_araddr,
+ s00_axi_awaddr,
+ iack_o_reg_1,
+ \wb_dat_o_reg[7] );
+ output s00_axi_awready;
+ output s00_axi_wready;
+ output s00_axi_arready;
+ output wb_we_o;
+ output wb_cyc_o;
+ output [0:0]s00_axi_bresp;
+ output s00_axi_bvalid;
+ output \cr_reg[2] ;
+ output [2:0]wb_adr_o;
+ output [0:0]E;
+ output [3:0]D;
+ output \cr_reg[4] ;
+ output [1:0]\prer_reg[8] ;
+ output [0:0]\ctr_reg[0] ;
+ output s00_axi_rvalid;
+ output iack_o_reg;
+ output [7:0]s00_axi_rdata;
+ input wb_rst_o;
+ input s00_axi_aclk;
+ input iack_o_reg_0;
+ input [0:0]Q;
+ input s00_axi_aresetn;
+ input wb_ack_i;
+ input s00_axi_awvalid;
+ input s00_axi_arvalid;
+ input s00_axi_bready;
+ input s00_axi_rready;
+ input s00_axi_wvalid;
+ input [3:0]s00_axi_wdata;
+ input [2:0]s00_axi_araddr;
+ input [2:0]s00_axi_awaddr;
+ input [0:0]iack_o_reg_1;
+ input [7:0]\wb_dat_o_reg[7] ;
+
+ wire [3:0]D;
+ wire [0:0]E;
+ wire [0:0]Q;
+ wire \cr[2]_i_3_n_0 ;
+ wire \cr_reg[2] ;
+ wire \cr_reg[4] ;
+ wire [0:0]\ctr_reg[0] ;
+ wire iack_o_reg;
+ wire iack_o_reg_0;
+ wire [0:0]iack_o_reg_1;
+ wire [1:0]\prer_reg[8] ;
+ wire s00_axi_aclk;
+ wire [2:0]s00_axi_araddr;
+ wire s00_axi_aresetn;
+ wire s00_axi_arready;
+ wire s00_axi_arvalid;
+ wire [2:0]s00_axi_awaddr;
+ wire s00_axi_awready;
+ wire s00_axi_awvalid;
+ wire s00_axi_bready;
+ wire [0:0]s00_axi_bresp;
+ wire s00_axi_bvalid;
+ wire [7:0]s00_axi_rdata;
+ wire s00_axi_rready;
+ wire s00_axi_rvalid;
+ wire [3:0]s00_axi_wdata;
+ wire s00_axi_wready;
+ wire s00_axi_wvalid;
+ wire \s_addr[2]_i_1_n_0 ;
+ wire \s_addr[3]_i_1_n_0 ;
+ wire \s_addr[4]_i_1_n_0 ;
+ wire s_arready_i_1_n_0;
+ wire s_awready_i_1_n_0;
+ wire \s_bresp[1]_i_1_n_0 ;
+ wire s_bvalid;
+ wire s_bvalid_i_1_n_0;
+ wire s_rvalid;
+ wire s_rvalid_i_1_n_0;
+ wire s_we_r_i_1_n_0;
+ wire s_wready_i_1_n_0;
+ wire wb_ack_i;
+ wire [2:0]wb_adr_o;
+ wire wb_cyc_o;
+ wire [7:0]\wb_dat_o_reg[7] ;
+ wire wb_rst_o;
+ wire wb_we_o;
+
+ LUT6 #(
+ .INIT(64'hFFFF0008FFFFFFFF))
+ \cr[2]_i_2
+ (.I0(wb_adr_o[2]),
+ .I1(Q),
+ .I2(wb_adr_o[1]),
+ .I3(wb_adr_o[0]),
+ .I4(\cr[2]_i_3_n_0 ),
+ .I5(s00_axi_aresetn),
+ .O(\cr_reg[2] ));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT2 #(
+ .INIT(4'h7))
+ \cr[2]_i_3
+ (.I0(wb_we_o),
+ .I1(wb_ack_i),
+ .O(\cr[2]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT4 #(
+ .INIT(16'h8000))
+ \cr[4]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[0]),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .O(D[0]));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT4 #(
+ .INIT(16'h8000))
+ \cr[5]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[1]),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .O(D[1]));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT4 #(
+ .INIT(16'h8000))
+ \cr[6]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[2]),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .O(D[2]));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT4 #(
+ .INIT(16'h8000))
+ \cr[7]_i_2
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[3]),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .O(D[3]));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFF7FFF))
+ \cr[7]_i_3
+ (.I0(wb_ack_i),
+ .I1(wb_we_o),
+ .I2(wb_adr_o[2]),
+ .I3(Q),
+ .I4(wb_adr_o[1]),
+ .I5(wb_adr_o[0]),
+ .O(\cr_reg[4] ));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT5 #(
+ .INIT(32'h0080FFFF))
+ \ctr[7]_i_1
+ (.I0(wb_we_o),
+ .I1(wb_ack_i),
+ .I2(wb_adr_o[1]),
+ .I3(wb_adr_o[0]),
+ .I4(s00_axi_aresetn),
+ .O(\ctr_reg[0] ));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT2 #(
+ .INIT(4'h2))
+ iack_o_i_1
+ (.I0(wb_cyc_o),
+ .I1(wb_ack_i),
+ .O(iack_o_reg));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT5 #(
+ .INIT(32'h75555555))
+ \prer[15]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(wb_adr_o[1]),
+ .I2(wb_ack_i),
+ .I3(wb_we_o),
+ .I4(wb_adr_o[0]),
+ .O(\prer_reg[8] [1]));
+ LUT6 #(
+ .INIT(64'h5555555557555555))
+ \prer[7]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(wb_adr_o[1]),
+ .I2(wb_adr_o[2]),
+ .I3(wb_ack_i),
+ .I4(wb_we_o),
+ .I5(wb_adr_o[0]),
+ .O(\prer_reg[8] [0]));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT2 #(
+ .INIT(4'h8))
+ s00_axi_bvalid_INST_0
+ (.I0(s_bvalid),
+ .I1(wb_we_o),
+ .O(s00_axi_bvalid));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT2 #(
+ .INIT(4'h2))
+ s00_axi_rvalid_INST_0
+ (.I0(s_rvalid),
+ .I1(wb_we_o),
+ .O(s00_axi_rvalid));
+ LUT5 #(
+ .INIT(32'hAACFAAC0))
+ \s_addr[2]_i_1
+ (.I0(s00_axi_araddr[0]),
+ .I1(s00_axi_awaddr[0]),
+ .I2(s00_axi_awvalid),
+ .I3(s00_axi_arvalid),
+ .I4(wb_adr_o[0]),
+ .O(\s_addr[2]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hAACFAAC0))
+ \s_addr[3]_i_1
+ (.I0(s00_axi_araddr[1]),
+ .I1(s00_axi_awaddr[1]),
+ .I2(s00_axi_awvalid),
+ .I3(s00_axi_arvalid),
+ .I4(wb_adr_o[1]),
+ .O(\s_addr[3]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hAACFAAC0))
+ \s_addr[4]_i_1
+ (.I0(s00_axi_araddr[2]),
+ .I1(s00_axi_awaddr[2]),
+ .I2(s00_axi_awvalid),
+ .I3(s00_axi_arvalid),
+ .I4(wb_adr_o[2]),
+ .O(\s_addr[4]_i_1_n_0 ));
+ FDRE #(
+ .INIT(1'b0))
+ \s_addr_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\s_addr[2]_i_1_n_0 ),
+ .Q(wb_adr_o[0]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_addr_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\s_addr[3]_i_1_n_0 ),
+ .Q(wb_adr_o[1]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_addr_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\s_addr[4]_i_1_n_0 ),
+ .Q(wb_adr_o[2]),
+ .R(wb_rst_o));
+ LUT2 #(
+ .INIT(4'h2))
+ s_arready_i_1
+ (.I0(s00_axi_arvalid),
+ .I1(s00_axi_arready),
+ .O(s_arready_i_1_n_0));
+ FDRE s_arready_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(s_arready_i_1_n_0),
+ .Q(s00_axi_arready),
+ .R(wb_rst_o));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
+ LUT3 #(
+ .INIT(8'h08))
+ s_awready_i_1
+ (.I0(s00_axi_wvalid),
+ .I1(s00_axi_awvalid),
+ .I2(s00_axi_awready),
+ .O(s_awready_i_1_n_0));
+ FDRE s_awready_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(s_awready_i_1_n_0),
+ .Q(s00_axi_awready),
+ .R(wb_rst_o));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT5 #(
+ .INIT(32'hFF7F0000))
+ \s_bresp[1]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(wb_we_o),
+ .I2(wb_ack_i),
+ .I3(s_bvalid),
+ .I4(s00_axi_bresp),
+ .O(\s_bresp[1]_i_1_n_0 ));
+ FDRE #(
+ .INIT(1'b0))
+ \s_bresp_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\s_bresp[1]_i_1_n_0 ),
+ .Q(s00_axi_bresp),
+ .R(1'b0));
+ LUT4 #(
+ .INIT(16'h0F88))
+ s_bvalid_i_1
+ (.I0(wb_we_o),
+ .I1(wb_ack_i),
+ .I2(s00_axi_bready),
+ .I3(s_bvalid),
+ .O(s_bvalid_i_1_n_0));
+ FDRE s_bvalid_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(s_bvalid_i_1_n_0),
+ .Q(s_bvalid),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [0]),
+ .Q(s00_axi_rdata[0]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [1]),
+ .Q(s00_axi_rdata[1]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [2]),
+ .Q(s00_axi_rdata[2]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [3]),
+ .Q(s00_axi_rdata[3]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [4]),
+ .Q(s00_axi_rdata[4]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [5]),
+ .Q(s00_axi_rdata[5]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [6]),
+ .Q(s00_axi_rdata[6]),
+ .R(wb_rst_o));
+ FDRE #(
+ .INIT(1'b0))
+ \s_rdata_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(iack_o_reg_1),
+ .D(\wb_dat_o_reg[7] [7]),
+ .Q(s00_axi_rdata[7]),
+ .R(wb_rst_o));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT4 #(
+ .INIT(16'h4F44))
+ s_rvalid_i_1
+ (.I0(s00_axi_rready),
+ .I1(s_rvalid),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .O(s_rvalid_i_1_n_0));
+ FDRE s_rvalid_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(s_rvalid_i_1_n_0),
+ .Q(s_rvalid),
+ .R(wb_rst_o));
+ FDRE s_stb_r_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(iack_o_reg_0),
+ .Q(wb_cyc_o),
+ .R(wb_rst_o));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT4 #(
+ .INIT(16'h00E0))
+ s_we_r_i_1
+ (.I0(wb_we_o),
+ .I1(s00_axi_awvalid),
+ .I2(s00_axi_aresetn),
+ .I3(s00_axi_arvalid),
+ .O(s_we_r_i_1_n_0));
+ FDRE s_we_r_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(s_we_r_i_1_n_0),
+ .Q(wb_we_o),
+ .R(1'b0));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
+ LUT3 #(
+ .INIT(8'h08))
+ s_wready_i_1
+ (.I0(s00_axi_wvalid),
+ .I1(s00_axi_awvalid),
+ .I2(s00_axi_wready),
+ .O(s_wready_i_1_n_0));
+ FDRE s_wready_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(s_wready_i_1_n_0),
+ .Q(s00_axi_wready),
+ .R(wb_rst_o));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT5 #(
+ .INIT(32'h8000FFFF))
+ \txr[7]_i_1
+ (.I0(wb_we_o),
+ .I1(wb_ack_i),
+ .I2(wb_adr_o[0]),
+ .I3(wb_adr_o[1]),
+ .I4(s00_axi_aresetn),
+ .O(E));
+endmodule
+
+(* ORIG_REF_NAME = "i2c_master_bit_ctrl" *)
+module system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
+ (iscl_oen_reg_0,
+ i2c_scl_t,
+ i2c_sda_t,
+ E,
+ irq_flag1_out,
+ al,
+ D,
+ \statemachine.core_cmd_reg[3] ,
+ \statemachine.ld_reg ,
+ \statemachine.core_txd_reg ,
+ \statemachine.shift_reg ,
+ \statemachine.host_ack_reg ,
+ \statemachine.ack_out_reg ,
+ \cr_reg[4] ,
+ \sr_reg[0] ,
+ \FSM_sequential_statemachine.c_state_reg[2] ,
+ s00_axi_aclk,
+ s00_axi_aresetn,
+ out,
+ \cr_reg[0] ,
+ cmd_ack,
+ irq_flag,
+ Q,
+ \ctr_reg[7] ,
+ i2c_sda_i,
+ i2c_scl_i,
+ \statemachine.core_cmd_reg[3]_0 ,
+ \st_irq_block.al_reg ,
+ \cr_reg[7] ,
+ wb_adr_o,
+ \sr_reg[6] ,
+ \txr_reg[6] ,
+ \FSM_sequential_statemachine.c_state_reg[1] ,
+ core_cmd,
+ \FSM_sequential_statemachine.c_state_reg[1]_0 ,
+ cnt_done,
+ ack_out,
+ iack_o_reg,
+ wb_we_o,
+ iack_o_reg_0,
+ \statemachine.ld_reg_0 ,
+ \FSM_sequential_statemachine.c_state_reg[1]_1 ,
+ \FSM_sequential_statemachine.c_state_reg[1]_2 ,
+ ack_in,
+ \sr_reg[7] ,
+ \cr_reg[7]_0 ,
+ \statemachine.core_txd_reg_0 );
+ output iscl_oen_reg_0;
+ output i2c_scl_t;
+ output i2c_sda_t;
+ output [0:0]E;
+ output irq_flag1_out;
+ output al;
+ output [0:0]D;
+ output [3:0]\statemachine.core_cmd_reg[3] ;
+ output \statemachine.ld_reg ;
+ output \statemachine.core_txd_reg ;
+ output \statemachine.shift_reg ;
+ output \statemachine.host_ack_reg ;
+ output \statemachine.ack_out_reg ;
+ output [0:0]\cr_reg[4] ;
+ output [0:0]\sr_reg[0] ;
+ output [2:0]\FSM_sequential_statemachine.c_state_reg[2] ;
+ input s00_axi_aclk;
+ input s00_axi_aresetn;
+ input [2:0]out;
+ input \cr_reg[0] ;
+ input cmd_ack;
+ input irq_flag;
+ input [15:0]Q;
+ input [0:0]\ctr_reg[7] ;
+ input i2c_sda_i;
+ input i2c_scl_i;
+ input [3:0]\statemachine.core_cmd_reg[3]_0 ;
+ input \st_irq_block.al_reg ;
+ input [3:0]\cr_reg[7] ;
+ input [2:0]wb_adr_o;
+ input \sr_reg[6] ;
+ input [1:0]\txr_reg[6] ;
+ input \FSM_sequential_statemachine.c_state_reg[1] ;
+ input [0:0]core_cmd;
+ input \FSM_sequential_statemachine.c_state_reg[1]_0 ;
+ input cnt_done;
+ input ack_out;
+ input iack_o_reg;
+ input wb_we_o;
+ input iack_o_reg_0;
+ input \statemachine.ld_reg_0 ;
+ input \FSM_sequential_statemachine.c_state_reg[1]_1 ;
+ input \FSM_sequential_statemachine.c_state_reg[1]_2 ;
+ input ack_in;
+ input [0:0]\sr_reg[7] ;
+ input \cr_reg[7]_0 ;
+ input \statemachine.core_txd_reg_0 ;
+
+ wire [0:0]D;
+ wire [0:0]E;
+ wire \FSM_sequential_c_state[0]_i_1_n_0 ;
+ wire \FSM_sequential_c_state[0]_i_2_n_0 ;
+ wire \FSM_sequential_c_state[1]_i_1_n_0 ;
+ wire \FSM_sequential_c_state[1]_i_2_n_0 ;
+ wire \FSM_sequential_c_state[1]_i_3_n_0 ;
+ wire \FSM_sequential_c_state[2]_i_1_n_0 ;
+ wire \FSM_sequential_c_state[2]_i_2_n_0 ;
+ wire \FSM_sequential_c_state[3]_i_1_n_0 ;
+ wire \FSM_sequential_c_state[3]_i_2_n_0 ;
+ wire \FSM_sequential_c_state[3]_i_3_n_0 ;
+ wire \FSM_sequential_c_state[4]_i_1_n_0 ;
+ wire \FSM_sequential_c_state[4]_i_2_n_0 ;
+ wire \FSM_sequential_c_state[4]_i_3_n_0 ;
+ wire \FSM_sequential_statemachine.c_state[2]_i_3_n_0 ;
+ wire \FSM_sequential_statemachine.c_state_reg[1] ;
+ wire \FSM_sequential_statemachine.c_state_reg[1]_0 ;
+ wire \FSM_sequential_statemachine.c_state_reg[1]_1 ;
+ wire \FSM_sequential_statemachine.c_state_reg[1]_2 ;
+ wire [2:0]\FSM_sequential_statemachine.c_state_reg[2] ;
+ wire [15:0]Q;
+ wire ack_in;
+ wire ack_out;
+ wire al;
+ wire \bus_status_ctrl.cSCL[0]_i_1_n_0 ;
+ wire \bus_status_ctrl.cSCL[1]_i_1_n_0 ;
+ wire \bus_status_ctrl.cSDA[0]_i_1_n_0 ;
+ wire \bus_status_ctrl.cSDA[1]_i_1_n_0 ;
+ wire \bus_status_ctrl.cSDA_reg_n_0_[1] ;
+ wire \bus_status_ctrl.cmd_stop_i_1_n_0 ;
+ wire \bus_status_ctrl.cmd_stop_i_2_n_0 ;
+ wire \bus_status_ctrl.cmd_stop_reg_n_0 ;
+ wire \bus_status_ctrl.dSCL_i_1_n_0 ;
+ wire \bus_status_ctrl.dSDA_i_1_n_0 ;
+ wire \bus_status_ctrl.dout_i_1_n_0 ;
+ wire \bus_status_ctrl.fSCL[0]_i_1_n_0 ;
+ wire \bus_status_ctrl.fSCL[1]_i_1_n_0 ;
+ wire \bus_status_ctrl.fSCL[2]_i_1_n_0 ;
+ wire \bus_status_ctrl.fSCL_reg_n_0_[2] ;
+ wire \bus_status_ctrl.fSDA[0]_i_1_n_0 ;
+ wire \bus_status_ctrl.fSDA[1]_i_1_n_0 ;
+ wire \bus_status_ctrl.fSDA[2]_i_1_n_0 ;
+ wire \bus_status_ctrl.fSDA[2]_i_2_n_0 ;
+ wire \bus_status_ctrl.fSDA_reg_n_0_[0] ;
+ wire \bus_status_ctrl.fSDA_reg_n_0_[1] ;
+ wire \bus_status_ctrl.fSDA_reg_n_0_[2] ;
+ wire \bus_status_ctrl.filter_cnt[0]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[10]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[11]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[12]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[13]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[13]_i_2_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[13]_i_3_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[13]_i_4_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[1]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[2]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[3]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[4]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[5]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[6]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[7]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[8]_i_1_n_0 ;
+ wire \bus_status_ctrl.filter_cnt[9]_i_1_n_0 ;
+ wire \bus_status_ctrl.ial_i_2_n_0 ;
+ wire \bus_status_ctrl.ial_i_3_n_0 ;
+ wire \bus_status_ctrl.sSCL_i_1_n_0 ;
+ wire \bus_status_ctrl.sSDA_i_1_n_0 ;
+ wire \bus_status_ctrl.sta_condition_reg_n_0 ;
+ wire \bus_status_ctrl.sto_condition_reg_n_0 ;
+ (* RTL_KEEP = "yes" *) wire [4:0]c_state;
+ wire clk_en;
+ wire clk_en_i_2_n_0;
+ wire clk_en_i_3_n_0;
+ wire clk_en_i_4_n_0;
+ wire clk_en_i_5_n_0;
+ wire clk_en_i_6_n_0;
+ wire cmd_ack;
+ wire cmd_ack3_out;
+ wire cmd_ack_i_2_n_0;
+ wire cnt1;
+ wire \cnt[0]_i_10_n_0 ;
+ wire \cnt[0]_i_1_n_0 ;
+ wire \cnt[0]_i_3_n_0 ;
+ wire \cnt[0]_i_4_n_0 ;
+ wire \cnt[0]_i_5_n_0 ;
+ wire \cnt[0]_i_6_n_0 ;
+ wire \cnt[0]_i_7_n_0 ;
+ wire \cnt[0]_i_8_n_0 ;
+ wire \cnt[0]_i_9_n_0 ;
+ wire \cnt[12]_i_2_n_0 ;
+ wire \cnt[12]_i_3_n_0 ;
+ wire \cnt[12]_i_4_n_0 ;
+ wire \cnt[12]_i_5_n_0 ;
+ wire \cnt[12]_i_6_n_0 ;
+ wire \cnt[12]_i_7_n_0 ;
+ wire \cnt[12]_i_8_n_0 ;
+ wire \cnt[4]_i_2_n_0 ;
+ wire \cnt[4]_i_3_n_0 ;
+ wire \cnt[4]_i_4_n_0 ;
+ wire \cnt[4]_i_5_n_0 ;
+ wire \cnt[4]_i_6_n_0 ;
+ wire \cnt[4]_i_7_n_0 ;
+ wire \cnt[4]_i_8_n_0 ;
+ wire \cnt[4]_i_9_n_0 ;
+ wire \cnt[8]_i_2_n_0 ;
+ wire \cnt[8]_i_3_n_0 ;
+ wire \cnt[8]_i_4_n_0 ;
+ wire \cnt[8]_i_5_n_0 ;
+ wire \cnt[8]_i_6_n_0 ;
+ wire \cnt[8]_i_7_n_0 ;
+ wire \cnt[8]_i_8_n_0 ;
+ wire \cnt[8]_i_9_n_0 ;
+ wire cnt_done;
+ wire [15:0]cnt_reg;
+ wire \cnt_reg[0]_i_2_n_0 ;
+ wire \cnt_reg[0]_i_2_n_1 ;
+ wire \cnt_reg[0]_i_2_n_2 ;
+ wire \cnt_reg[0]_i_2_n_3 ;
+ wire \cnt_reg[0]_i_2_n_4 ;
+ wire \cnt_reg[0]_i_2_n_5 ;
+ wire \cnt_reg[0]_i_2_n_6 ;
+ wire \cnt_reg[0]_i_2_n_7 ;
+ wire \cnt_reg[12]_i_1_n_1 ;
+ wire \cnt_reg[12]_i_1_n_2 ;
+ wire \cnt_reg[12]_i_1_n_3 ;
+ wire \cnt_reg[12]_i_1_n_4 ;
+ wire \cnt_reg[12]_i_1_n_5 ;
+ wire \cnt_reg[12]_i_1_n_6 ;
+ wire \cnt_reg[12]_i_1_n_7 ;
+ wire \cnt_reg[4]_i_1_n_0 ;
+ wire \cnt_reg[4]_i_1_n_1 ;
+ wire \cnt_reg[4]_i_1_n_2 ;
+ wire \cnt_reg[4]_i_1_n_3 ;
+ wire \cnt_reg[4]_i_1_n_4 ;
+ wire \cnt_reg[4]_i_1_n_5 ;
+ wire \cnt_reg[4]_i_1_n_6 ;
+ wire \cnt_reg[4]_i_1_n_7 ;
+ wire \cnt_reg[8]_i_1_n_0 ;
+ wire \cnt_reg[8]_i_1_n_1 ;
+ wire \cnt_reg[8]_i_1_n_2 ;
+ wire \cnt_reg[8]_i_1_n_3 ;
+ wire \cnt_reg[8]_i_1_n_4 ;
+ wire \cnt_reg[8]_i_1_n_5 ;
+ wire \cnt_reg[8]_i_1_n_6 ;
+ wire \cnt_reg[8]_i_1_n_7 ;
+ wire core_ack;
+ wire [0:0]core_cmd;
+ wire core_rxd;
+ wire core_txd;
+ wire \cr_reg[0] ;
+ wire [0:0]\cr_reg[4] ;
+ wire [3:0]\cr_reg[7] ;
+ wire \cr_reg[7]_0 ;
+ wire [0:0]\ctr_reg[7] ;
+ wire dSCL;
+ wire dSDA;
+ wire dscl_oen;
+ wire [13:0]filter_cnt;
+ wire i2c_al;
+ wire i2c_busy;
+ wire i2c_scl_i;
+ wire i2c_scl_t;
+ wire i2c_sda_i;
+ wire i2c_sda_t;
+ wire iack_o_reg;
+ wire iack_o_reg_0;
+ wire ial;
+ wire ibusy;
+ wire irq_flag;
+ wire irq_flag1_out;
+ wire iscl_oen;
+ wire iscl_oen9_out__0;
+ wire iscl_oen_i_1_n_0;
+ wire iscl_oen_reg_0;
+ wire isda_oen;
+ wire isda_oen7_out__0;
+ wire isda_oen_i_1_n_0;
+ wire minusOp_carry__0_i_1_n_0;
+ wire minusOp_carry__0_i_2_n_0;
+ wire minusOp_carry__0_i_3_n_0;
+ wire minusOp_carry__0_i_4_n_0;
+ wire minusOp_carry__0_n_0;
+ wire minusOp_carry__0_n_1;
+ wire minusOp_carry__0_n_2;
+ wire minusOp_carry__0_n_3;
+ wire minusOp_carry__0_n_4;
+ wire minusOp_carry__0_n_5;
+ wire minusOp_carry__0_n_6;
+ wire minusOp_carry__0_n_7;
+ wire minusOp_carry__1_i_1_n_0;
+ wire minusOp_carry__1_i_2_n_0;
+ wire minusOp_carry__1_i_3_n_0;
+ wire minusOp_carry__1_i_4_n_0;
+ wire minusOp_carry__1_n_0;
+ wire minusOp_carry__1_n_1;
+ wire minusOp_carry__1_n_2;
+ wire minusOp_carry__1_n_3;
+ wire minusOp_carry__1_n_4;
+ wire minusOp_carry__1_n_5;
+ wire minusOp_carry__1_n_6;
+ wire minusOp_carry__1_n_7;
+ wire minusOp_carry__2_i_1_n_0;
+ wire minusOp_carry__2_n_7;
+ wire minusOp_carry_i_1_n_0;
+ wire minusOp_carry_i_2_n_0;
+ wire minusOp_carry_i_3_n_0;
+ wire minusOp_carry_i_4_n_0;
+ wire minusOp_carry_n_0;
+ wire minusOp_carry_n_1;
+ wire minusOp_carry_n_2;
+ wire minusOp_carry_n_3;
+ wire minusOp_carry_n_4;
+ wire minusOp_carry_n_5;
+ wire minusOp_carry_n_6;
+ wire minusOp_carry_n_7;
+ wire [2:0]out;
+ wire [1:1]p_0_in;
+ wire [1:1]p_0_in__0;
+ wire [2:0]p_0_in__1;
+ wire s00_axi_aclk;
+ wire s00_axi_aresetn;
+ wire sSCL;
+ wire sSDA;
+ wire sda_chk_i_1_n_0;
+ wire sda_chk_reg_n_0;
+ wire slave_wait;
+ wire slave_wait0;
+ wire [0:0]\sr_reg[0] ;
+ wire \sr_reg[6] ;
+ wire [0:0]\sr_reg[7] ;
+ wire \st_irq_block.al_reg ;
+ wire sta_condition;
+ wire \statemachine.ack_out_i_2_n_0 ;
+ wire \statemachine.ack_out_reg ;
+ wire [3:0]\statemachine.core_cmd_reg[3] ;
+ wire [3:0]\statemachine.core_cmd_reg[3]_0 ;
+ wire \statemachine.core_txd_reg ;
+ wire \statemachine.core_txd_reg_0 ;
+ wire \statemachine.host_ack_reg ;
+ wire \statemachine.ld_reg ;
+ wire \statemachine.ld_reg_0 ;
+ wire \statemachine.shift_reg ;
+ wire sto_condition;
+ wire [1:0]\txr_reg[6] ;
+ wire [2:0]wb_adr_o;
+ wire \wb_dat_o[6]_i_3_n_0 ;
+ wire wb_we_o;
+ wire [3:3]\NLW_cnt_reg[12]_i_1_CO_UNCONNECTED ;
+ wire [3:0]NLW_minusOp_carry__2_CO_UNCONNECTED;
+ wire [3:1]NLW_minusOp_carry__2_O_UNCONNECTED;
+
+ LUT6 #(
+ .INIT(64'h1111111111111110))
+ \FSM_sequential_c_state[0]_i_1
+ (.I0(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .I1(c_state[0]),
+ .I2(c_state[2]),
+ .I3(c_state[3]),
+ .I4(\FSM_sequential_c_state[0]_i_2_n_0 ),
+ .I5(c_state[4]),
+ .O(\FSM_sequential_c_state[0]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hAAAAAABA))
+ \FSM_sequential_c_state[0]_i_2
+ (.I0(c_state[1]),
+ .I1(\statemachine.core_cmd_reg[3]_0 [1]),
+ .I2(\statemachine.core_cmd_reg[3]_0 [0]),
+ .I3(\statemachine.core_cmd_reg[3]_0 [3]),
+ .I4(\statemachine.core_cmd_reg[3]_0 [2]),
+ .O(\FSM_sequential_c_state[0]_i_2_n_0 ));
+ LUT4 #(
+ .INIT(16'h0400))
+ \FSM_sequential_c_state[1]_i_1
+ (.I0(i2c_al),
+ .I1(s00_axi_aresetn),
+ .I2(c_state[4]),
+ .I3(\FSM_sequential_c_state[1]_i_2_n_0 ),
+ .O(\FSM_sequential_c_state[1]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'hEEEFEFFE44444444))
+ \FSM_sequential_c_state[1]_i_2
+ (.I0(c_state[0]),
+ .I1(c_state[1]),
+ .I2(\statemachine.core_cmd_reg[3]_0 [1]),
+ .I3(\statemachine.core_cmd_reg[3]_0 [2]),
+ .I4(\statemachine.core_cmd_reg[3]_0 [3]),
+ .I5(\FSM_sequential_c_state[1]_i_3_n_0 ),
+ .O(\FSM_sequential_c_state[1]_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'h00001101))
+ \FSM_sequential_c_state[1]_i_3
+ (.I0(c_state[2]),
+ .I1(c_state[1]),
+ .I2(\statemachine.core_cmd_reg[3]_0 [0]),
+ .I3(c_state[0]),
+ .I4(c_state[3]),
+ .O(\FSM_sequential_c_state[1]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'h0002A0A2AAAA0002))
+ \FSM_sequential_c_state[2]_i_1
+ (.I0(\FSM_sequential_c_state[3]_i_2_n_0 ),
+ .I1(c_state[3]),
+ .I2(c_state[1]),
+ .I3(\FSM_sequential_c_state[2]_i_2_n_0 ),
+ .I4(c_state[2]),
+ .I5(c_state[0]),
+ .O(\FSM_sequential_c_state[2]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hFFFFFEEF))
+ \FSM_sequential_c_state[2]_i_2
+ (.I0(c_state[0]),
+ .I1(\statemachine.core_cmd_reg[3]_0 [3]),
+ .I2(\statemachine.core_cmd_reg[3]_0 [1]),
+ .I3(\statemachine.core_cmd_reg[3]_0 [2]),
+ .I4(\statemachine.core_cmd_reg[3]_0 [0]),
+ .O(\FSM_sequential_c_state[2]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0AA8A0A800A800A8))
+ \FSM_sequential_c_state[3]_i_1
+ (.I0(\FSM_sequential_c_state[3]_i_2_n_0 ),
+ .I1(\FSM_sequential_c_state[3]_i_3_n_0 ),
+ .I2(c_state[3]),
+ .I3(c_state[0]),
+ .I4(c_state[2]),
+ .I5(c_state[1]),
+ .O(\FSM_sequential_c_state[3]_i_1_n_0 ));
+ LUT3 #(
+ .INIT(8'h04))
+ \FSM_sequential_c_state[3]_i_2
+ (.I0(c_state[4]),
+ .I1(s00_axi_aresetn),
+ .I2(i2c_al),
+ .O(\FSM_sequential_c_state[3]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000006))
+ \FSM_sequential_c_state[3]_i_3
+ (.I0(\statemachine.core_cmd_reg[3]_0 [3]),
+ .I1(\statemachine.core_cmd_reg[3]_0 [2]),
+ .I2(\statemachine.core_cmd_reg[3]_0 [0]),
+ .I3(\statemachine.core_cmd_reg[3]_0 [1]),
+ .I4(c_state[1]),
+ .I5(c_state[2]),
+ .O(\FSM_sequential_c_state[3]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hBBBBBBBFAAAAAAAA))
+ \FSM_sequential_c_state[4]_i_1
+ (.I0(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .I1(c_state[4]),
+ .I2(c_state[3]),
+ .I3(c_state[1]),
+ .I4(c_state[2]),
+ .I5(clk_en),
+ .O(\FSM_sequential_c_state[4]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000080FF8000))
+ \FSM_sequential_c_state[4]_i_2
+ (.I0(c_state[3]),
+ .I1(c_state[1]),
+ .I2(c_state[2]),
+ .I3(c_state[0]),
+ .I4(c_state[4]),
+ .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .O(\FSM_sequential_c_state[4]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \FSM_sequential_c_state[4]_i_3
+ (.I0(i2c_al),
+ .I1(s00_axi_aresetn),
+ .O(\FSM_sequential_c_state[4]_i_3_n_0 ));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_c_state_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\FSM_sequential_c_state[0]_i_1_n_0 ),
+ .Q(c_state[0]));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_c_state_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\FSM_sequential_c_state[1]_i_1_n_0 ),
+ .Q(c_state[1]));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_c_state_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\FSM_sequential_c_state[2]_i_1_n_0 ),
+ .Q(c_state[2]));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_c_state_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\FSM_sequential_c_state[3]_i_1_n_0 ),
+ .Q(c_state[3]));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_c_state_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\FSM_sequential_c_state[4]_i_2_n_0 ),
+ .Q(c_state[4]));
+ LUT6 #(
+ .INIT(64'h0000000022222E22))
+ \FSM_sequential_statemachine.c_state[0]_i_1
+ (.I0(\FSM_sequential_statemachine.c_state_reg[1]_1 ),
+ .I1(out[2]),
+ .I2(out[1]),
+ .I3(\cr_reg[7] [2]),
+ .I4(out[0]),
+ .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .O(\FSM_sequential_statemachine.c_state_reg[2] [0]));
+ LUT6 #(
+ .INIT(64'h0000000015100000))
+ \FSM_sequential_statemachine.c_state[1]_i_1
+ (.I0(out[2]),
+ .I1(cnt_done),
+ .I2(out[1]),
+ .I3(\cr_reg[7]_0 ),
+ .I4(s00_axi_aresetn),
+ .I5(i2c_al),
+ .O(\FSM_sequential_statemachine.c_state_reg[2] [1]));
+ LUT6 #(
+ .INIT(64'hDDFFDDDDFFFDDDFD))
+ \FSM_sequential_statemachine.c_state[2]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(i2c_al),
+ .I2(\FSM_sequential_statemachine.c_state[2]_i_3_n_0 ),
+ .I3(out[1]),
+ .I4(core_ack),
+ .I5(out[2]),
+ .O(E));
+ LUT6 #(
+ .INIT(64'h0000000022222E22))
+ \FSM_sequential_statemachine.c_state[2]_i_2
+ (.I0(\FSM_sequential_statemachine.c_state_reg[1]_2 ),
+ .I1(out[2]),
+ .I2(out[1]),
+ .I3(\cr_reg[7] [2]),
+ .I4(out[0]),
+ .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .O(\FSM_sequential_statemachine.c_state_reg[2] [2]));
+ LUT6 #(
+ .INIT(64'h8B8B8B8B8B8B8B88))
+ \FSM_sequential_statemachine.c_state[2]_i_3
+ (.I0(core_ack),
+ .I1(out[0]),
+ .I2(cmd_ack),
+ .I3(\cr_reg[7] [0]),
+ .I4(\cr_reg[7] [1]),
+ .I5(\cr_reg[7] [2]),
+ .O(\FSM_sequential_statemachine.c_state[2]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \bus_status_ctrl.cSCL[0]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(i2c_scl_i),
+ .O(\bus_status_ctrl.cSCL[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \bus_status_ctrl.cSCL[1]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(p_0_in__0),
+ .O(\bus_status_ctrl.cSCL[1]_i_1_n_0 ));
+ FDCE \bus_status_ctrl.cSCL_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.cSCL[0]_i_1_n_0 ),
+ .Q(p_0_in__0));
+ FDCE \bus_status_ctrl.cSCL_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.cSCL[1]_i_1_n_0 ),
+ .Q(p_0_in__1[0]));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \bus_status_ctrl.cSDA[0]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(i2c_sda_i),
+ .O(\bus_status_ctrl.cSDA[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \bus_status_ctrl.cSDA[1]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(p_0_in),
+ .O(\bus_status_ctrl.cSDA[1]_i_1_n_0 ));
+ FDCE \bus_status_ctrl.cSDA_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.cSDA[0]_i_1_n_0 ),
+ .Q(p_0_in));
+ FDCE \bus_status_ctrl.cSDA_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.cSDA[1]_i_1_n_0 ),
+ .Q(\bus_status_ctrl.cSDA_reg_n_0_[1] ));
+ LUT6 #(
+ .INIT(64'h04FF000004000000))
+ \bus_status_ctrl.cmd_stop_i_1
+ (.I0(\statemachine.core_cmd_reg[3]_0 [0]),
+ .I1(\statemachine.core_cmd_reg[3]_0 [1]),
+ .I2(\bus_status_ctrl.cmd_stop_i_2_n_0 ),
+ .I3(clk_en),
+ .I4(s00_axi_aresetn),
+ .I5(\bus_status_ctrl.cmd_stop_reg_n_0 ),
+ .O(\bus_status_ctrl.cmd_stop_i_1_n_0 ));
+ LUT2 #(
+ .INIT(4'hE))
+ \bus_status_ctrl.cmd_stop_i_2
+ (.I0(\statemachine.core_cmd_reg[3]_0 [2]),
+ .I1(\statemachine.core_cmd_reg[3]_0 [3]),
+ .O(\bus_status_ctrl.cmd_stop_i_2_n_0 ));
+ FDCE \bus_status_ctrl.cmd_stop_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.cmd_stop_i_1_n_0 ),
+ .Q(\bus_status_ctrl.cmd_stop_reg_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.dSCL_i_1
+ (.I0(sSCL),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.dSCL_i_1_n_0 ));
+ FDPE \bus_status_ctrl.dSCL_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\bus_status_ctrl.dSCL_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(dSCL));
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.dSDA_i_1
+ (.I0(sSDA),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.dSDA_i_1_n_0 ));
+ FDPE \bus_status_ctrl.dSDA_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\bus_status_ctrl.dSDA_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(dSDA));
+ LUT4 #(
+ .INIT(16'hFB08))
+ \bus_status_ctrl.dout_i_1
+ (.I0(sSDA),
+ .I1(sSCL),
+ .I2(dSCL),
+ .I3(core_rxd),
+ .O(\bus_status_ctrl.dout_i_1_n_0 ));
+ FDCE \bus_status_ctrl.dout_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.dout_i_1_n_0 ),
+ .Q(core_rxd));
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.fSCL[0]_i_1
+ (.I0(p_0_in__1[0]),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.fSCL[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.fSCL[1]_i_1
+ (.I0(p_0_in__1[1]),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.fSCL[1]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.fSCL[2]_i_1
+ (.I0(p_0_in__1[2]),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.fSCL[2]_i_1_n_0 ));
+ FDPE \bus_status_ctrl.fSCL_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
+ .D(\bus_status_ctrl.fSCL[0]_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(p_0_in__1[1]));
+ FDPE \bus_status_ctrl.fSCL_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
+ .D(\bus_status_ctrl.fSCL[1]_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(p_0_in__1[2]));
+ FDPE \bus_status_ctrl.fSCL_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
+ .D(\bus_status_ctrl.fSCL[2]_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(\bus_status_ctrl.fSCL_reg_n_0_[2] ));
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.fSDA[0]_i_1
+ (.I0(\bus_status_ctrl.cSDA_reg_n_0_[1] ),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.fSDA[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.fSDA[1]_i_1
+ (.I0(\bus_status_ctrl.fSDA_reg_n_0_[0] ),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.fSDA[1]_i_1_n_0 ));
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.fSDA[2]_i_1
+ (.I0(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.fSDA[2]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \bus_status_ctrl.fSDA[2]_i_2
+ (.I0(\bus_status_ctrl.fSDA_reg_n_0_[1] ),
+ .I1(s00_axi_aresetn),
+ .O(\bus_status_ctrl.fSDA[2]_i_2_n_0 ));
+ FDPE \bus_status_ctrl.fSDA_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
+ .D(\bus_status_ctrl.fSDA[0]_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(\bus_status_ctrl.fSDA_reg_n_0_[0] ));
+ FDPE \bus_status_ctrl.fSDA_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
+ .D(\bus_status_ctrl.fSDA[1]_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(\bus_status_ctrl.fSDA_reg_n_0_[1] ));
+ FDPE \bus_status_ctrl.fSDA_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\bus_status_ctrl.fSDA[2]_i_1_n_0 ),
+ .D(\bus_status_ctrl.fSDA[2]_i_2_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(\bus_status_ctrl.fSDA_reg_n_0_[2] ));
+ LUT5 #(
+ .INIT(32'hD1000000))
+ \bus_status_ctrl.filter_cnt[0]_i_1
+ (.I0(filter_cnt[0]),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[2]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[0]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[10]_i_1
+ (.I0(minusOp_carry__1_n_6),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[12]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[10]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[11]_i_1
+ (.I0(minusOp_carry__1_n_5),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[13]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[11]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[12]_i_1
+ (.I0(minusOp_carry__1_n_4),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[14]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[12]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[13]_i_1
+ (.I0(minusOp_carry__2_n_7),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[15]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[13]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000001))
+ \bus_status_ctrl.filter_cnt[13]_i_2
+ (.I0(\bus_status_ctrl.filter_cnt[13]_i_3_n_0 ),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_4_n_0 ),
+ .I2(filter_cnt[6]),
+ .I3(filter_cnt[7]),
+ .I4(filter_cnt[4]),
+ .I5(filter_cnt[5]),
+ .O(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFFFFFFE))
+ \bus_status_ctrl.filter_cnt[13]_i_3
+ (.I0(filter_cnt[13]),
+ .I1(filter_cnt[12]),
+ .I2(filter_cnt[9]),
+ .I3(filter_cnt[8]),
+ .I4(filter_cnt[11]),
+ .I5(filter_cnt[10]),
+ .O(\bus_status_ctrl.filter_cnt[13]_i_3_n_0 ));
+ LUT4 #(
+ .INIT(16'hFFFE))
+ \bus_status_ctrl.filter_cnt[13]_i_4
+ (.I0(filter_cnt[2]),
+ .I1(filter_cnt[3]),
+ .I2(filter_cnt[0]),
+ .I3(filter_cnt[1]),
+ .O(\bus_status_ctrl.filter_cnt[13]_i_4_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[1]_i_1
+ (.I0(minusOp_carry_n_7),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[3]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[1]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[2]_i_1
+ (.I0(minusOp_carry_n_6),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[4]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[2]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[3]_i_1
+ (.I0(minusOp_carry_n_5),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[5]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[3]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[4]_i_1
+ (.I0(minusOp_carry_n_4),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[6]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[4]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[5]_i_1
+ (.I0(minusOp_carry__0_n_7),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[7]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[5]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[6]_i_1
+ (.I0(minusOp_carry__0_n_6),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[8]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[6]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[7]_i_1
+ (.I0(minusOp_carry__0_n_5),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[9]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[7]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[8]_i_1
+ (.I0(minusOp_carry__0_n_4),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[10]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[8]_i_1_n_0 ));
+ LUT5 #(
+ .INIT(32'hE2000000))
+ \bus_status_ctrl.filter_cnt[9]_i_1
+ (.I0(minusOp_carry__1_n_7),
+ .I1(\bus_status_ctrl.filter_cnt[13]_i_2_n_0 ),
+ .I2(Q[11]),
+ .I3(\ctr_reg[7] ),
+ .I4(s00_axi_aresetn),
+ .O(\bus_status_ctrl.filter_cnt[9]_i_1_n_0 ));
+ FDCE \bus_status_ctrl.filter_cnt_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[0]_i_1_n_0 ),
+ .Q(filter_cnt[0]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[10]_i_1_n_0 ),
+ .Q(filter_cnt[10]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[11]_i_1_n_0 ),
+ .Q(filter_cnt[11]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[12]_i_1_n_0 ),
+ .Q(filter_cnt[12]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[13]_i_1_n_0 ),
+ .Q(filter_cnt[13]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[1]_i_1_n_0 ),
+ .Q(filter_cnt[1]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[2]_i_1_n_0 ),
+ .Q(filter_cnt[2]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[3]_i_1_n_0 ),
+ .Q(filter_cnt[3]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[4]_i_1_n_0 ),
+ .Q(filter_cnt[4]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[5]_i_1_n_0 ),
+ .Q(filter_cnt[5]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[6]_i_1_n_0 ),
+ .Q(filter_cnt[6]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[7]_i_1_n_0 ),
+ .Q(filter_cnt[7]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[8]_i_1_n_0 ),
+ .Q(filter_cnt[8]));
+ FDCE \bus_status_ctrl.filter_cnt_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(\bus_status_ctrl.filter_cnt[9]_i_1_n_0 ),
+ .Q(filter_cnt[9]));
+ LUT6 #(
+ .INIT(64'h08000800AAAA0800))
+ \bus_status_ctrl.ial_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(sda_chk_reg_n_0),
+ .I2(sSDA),
+ .I3(i2c_sda_t),
+ .I4(\bus_status_ctrl.ial_i_2_n_0 ),
+ .I5(\bus_status_ctrl.ial_i_3_n_0 ),
+ .O(ial));
+ LUT2 #(
+ .INIT(4'h1))
+ \bus_status_ctrl.ial_i_2
+ (.I0(c_state[0]),
+ .I1(c_state[4]),
+ .O(\bus_status_ctrl.ial_i_2_n_0 ));
+ LUT5 #(
+ .INIT(32'hFFFFFFEF))
+ \bus_status_ctrl.ial_i_3
+ (.I0(c_state[2]),
+ .I1(c_state[3]),
+ .I2(\bus_status_ctrl.sto_condition_reg_n_0 ),
+ .I3(\bus_status_ctrl.cmd_stop_reg_n_0 ),
+ .I4(c_state[1]),
+ .O(\bus_status_ctrl.ial_i_3_n_0 ));
+ FDCE \bus_status_ctrl.ial_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(ial),
+ .Q(i2c_al));
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
+ LUT4 #(
+ .INIT(16'h5400))
+ \bus_status_ctrl.ibusy_i_1
+ (.I0(\bus_status_ctrl.sto_condition_reg_n_0 ),
+ .I1(\bus_status_ctrl.sta_condition_reg_n_0 ),
+ .I2(i2c_busy),
+ .I3(s00_axi_aresetn),
+ .O(ibusy));
+ FDCE \bus_status_ctrl.ibusy_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(ibusy),
+ .Q(i2c_busy));
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
+ LUT4 #(
+ .INIT(16'hE8FF))
+ \bus_status_ctrl.sSCL_i_1
+ (.I0(p_0_in__1[2]),
+ .I1(\bus_status_ctrl.fSCL_reg_n_0_[2] ),
+ .I2(p_0_in__1[1]),
+ .I3(s00_axi_aresetn),
+ .O(\bus_status_ctrl.sSCL_i_1_n_0 ));
+ FDPE \bus_status_ctrl.sSCL_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\bus_status_ctrl.sSCL_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(sSCL));
+ LUT4 #(
+ .INIT(16'hE8FF))
+ \bus_status_ctrl.sSDA_i_1
+ (.I0(\bus_status_ctrl.fSDA_reg_n_0_[1] ),
+ .I1(\bus_status_ctrl.fSDA_reg_n_0_[2] ),
+ .I2(\bus_status_ctrl.fSDA_reg_n_0_[0] ),
+ .I3(s00_axi_aresetn),
+ .O(\bus_status_ctrl.sSDA_i_1_n_0 ));
+ FDPE \bus_status_ctrl.sSDA_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(\bus_status_ctrl.sSDA_i_1_n_0 ),
+ .PRE(iscl_oen_reg_0),
+ .Q(sSDA));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT4 #(
+ .INIT(16'h2000))
+ \bus_status_ctrl.sta_condition_i_1
+ (.I0(dSDA),
+ .I1(sSDA),
+ .I2(s00_axi_aresetn),
+ .I3(sSCL),
+ .O(sta_condition));
+ FDCE \bus_status_ctrl.sta_condition_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(sta_condition),
+ .Q(\bus_status_ctrl.sta_condition_reg_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT4 #(
+ .INIT(16'h4000))
+ \bus_status_ctrl.sto_condition_i_1
+ (.I0(dSDA),
+ .I1(s00_axi_aresetn),
+ .I2(sSCL),
+ .I3(sSDA),
+ .O(sto_condition));
+ FDCE \bus_status_ctrl.sto_condition_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(sto_condition),
+ .Q(\bus_status_ctrl.sto_condition_reg_n_0 ));
+ LUT5 #(
+ .INIT(32'hAAAAAAAB))
+ clk_en_i_1
+ (.I0(clk_en_i_2_n_0),
+ .I1(clk_en_i_3_n_0),
+ .I2(clk_en_i_4_n_0),
+ .I3(clk_en_i_5_n_0),
+ .I4(clk_en_i_6_n_0),
+ .O(cnt1));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
+ LUT5 #(
+ .INIT(32'h7555FFFF))
+ clk_en_i_2
+ (.I0(\ctr_reg[7] ),
+ .I1(sSCL),
+ .I2(i2c_scl_t),
+ .I3(dSCL),
+ .I4(s00_axi_aresetn),
+ .O(clk_en_i_2_n_0));
+ LUT4 #(
+ .INIT(16'hFFFE))
+ clk_en_i_3
+ (.I0(cnt_reg[6]),
+ .I1(cnt_reg[7]),
+ .I2(cnt_reg[4]),
+ .I3(cnt_reg[5]),
+ .O(clk_en_i_3_n_0));
+ LUT4 #(
+ .INIT(16'hFFFE))
+ clk_en_i_4
+ (.I0(cnt_reg[2]),
+ .I1(cnt_reg[3]),
+ .I2(cnt_reg[0]),
+ .I3(cnt_reg[1]),
+ .O(clk_en_i_4_n_0));
+ LUT4 #(
+ .INIT(16'hFFFE))
+ clk_en_i_5
+ (.I0(cnt_reg[15]),
+ .I1(cnt_reg[14]),
+ .I2(cnt_reg[12]),
+ .I3(cnt_reg[13]),
+ .O(clk_en_i_5_n_0));
+ LUT4 #(
+ .INIT(16'hFFFE))
+ clk_en_i_6
+ (.I0(cnt_reg[10]),
+ .I1(cnt_reg[11]),
+ .I2(cnt_reg[8]),
+ .I3(cnt_reg[9]),
+ .O(clk_en_i_6_n_0));
+ FDPE clk_en_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(cnt1),
+ .PRE(iscl_oen_reg_0),
+ .Q(clk_en));
+ LUT6 #(
+ .INIT(64'h0008000000000000))
+ cmd_ack_i_1
+ (.I0(cmd_ack_i_2_n_0),
+ .I1(c_state[0]),
+ .I2(c_state[1]),
+ .I3(i2c_al),
+ .I4(s00_axi_aresetn),
+ .I5(clk_en),
+ .O(cmd_ack3_out));
+ LUT3 #(
+ .INIT(8'h1E))
+ cmd_ack_i_2
+ (.I0(c_state[2]),
+ .I1(c_state[3]),
+ .I2(c_state[4]),
+ .O(cmd_ack_i_2_n_0));
+ FDCE cmd_ack_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(cmd_ack3_out),
+ .Q(core_ack));
+ LUT2 #(
+ .INIT(4'hB))
+ \cnt[0]_i_1
+ (.I0(cnt1),
+ .I1(slave_wait),
+ .O(\cnt[0]_i_1_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[0]_i_10
+ (.I0(cnt_reg[0]),
+ .I1(Q[0]),
+ .I2(cnt1),
+ .O(\cnt[0]_i_10_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[0]_i_3
+ (.I0(Q[3]),
+ .I1(cnt1),
+ .I2(cnt_reg[3]),
+ .O(\cnt[0]_i_3_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[0]_i_4
+ (.I0(Q[2]),
+ .I1(cnt1),
+ .I2(cnt_reg[2]),
+ .O(\cnt[0]_i_4_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[0]_i_5
+ (.I0(Q[1]),
+ .I1(cnt1),
+ .I2(cnt_reg[1]),
+ .O(\cnt[0]_i_5_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[0]_i_6
+ (.I0(Q[0]),
+ .I1(cnt1),
+ .I2(cnt_reg[0]),
+ .O(\cnt[0]_i_6_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[0]_i_7
+ (.I0(cnt_reg[3]),
+ .I1(Q[3]),
+ .I2(cnt1),
+ .O(\cnt[0]_i_7_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[0]_i_8
+ (.I0(cnt_reg[2]),
+ .I1(Q[2]),
+ .I2(cnt1),
+ .O(\cnt[0]_i_8_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[0]_i_9
+ (.I0(cnt_reg[1]),
+ .I1(Q[1]),
+ .I2(cnt1),
+ .O(\cnt[0]_i_9_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[12]_i_2
+ (.I0(Q[14]),
+ .I1(cnt1),
+ .I2(cnt_reg[14]),
+ .O(\cnt[12]_i_2_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[12]_i_3
+ (.I0(Q[13]),
+ .I1(cnt1),
+ .I2(cnt_reg[13]),
+ .O(\cnt[12]_i_3_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[12]_i_4
+ (.I0(Q[12]),
+ .I1(cnt1),
+ .I2(cnt_reg[12]),
+ .O(\cnt[12]_i_4_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[12]_i_5
+ (.I0(cnt_reg[15]),
+ .I1(Q[15]),
+ .I2(cnt1),
+ .O(\cnt[12]_i_5_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[12]_i_6
+ (.I0(cnt_reg[14]),
+ .I1(Q[14]),
+ .I2(cnt1),
+ .O(\cnt[12]_i_6_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[12]_i_7
+ (.I0(cnt_reg[13]),
+ .I1(Q[13]),
+ .I2(cnt1),
+ .O(\cnt[12]_i_7_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[12]_i_8
+ (.I0(cnt_reg[12]),
+ .I1(Q[12]),
+ .I2(cnt1),
+ .O(\cnt[12]_i_8_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[4]_i_2
+ (.I0(Q[7]),
+ .I1(cnt1),
+ .I2(cnt_reg[7]),
+ .O(\cnt[4]_i_2_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[4]_i_3
+ (.I0(Q[6]),
+ .I1(cnt1),
+ .I2(cnt_reg[6]),
+ .O(\cnt[4]_i_3_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[4]_i_4
+ (.I0(Q[5]),
+ .I1(cnt1),
+ .I2(cnt_reg[5]),
+ .O(\cnt[4]_i_4_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[4]_i_5
+ (.I0(Q[4]),
+ .I1(cnt1),
+ .I2(cnt_reg[4]),
+ .O(\cnt[4]_i_5_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[4]_i_6
+ (.I0(cnt_reg[7]),
+ .I1(Q[7]),
+ .I2(cnt1),
+ .O(\cnt[4]_i_6_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[4]_i_7
+ (.I0(cnt_reg[6]),
+ .I1(Q[6]),
+ .I2(cnt1),
+ .O(\cnt[4]_i_7_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[4]_i_8
+ (.I0(cnt_reg[5]),
+ .I1(Q[5]),
+ .I2(cnt1),
+ .O(\cnt[4]_i_8_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[4]_i_9
+ (.I0(cnt_reg[4]),
+ .I1(Q[4]),
+ .I2(cnt1),
+ .O(\cnt[4]_i_9_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[8]_i_2
+ (.I0(Q[11]),
+ .I1(cnt1),
+ .I2(cnt_reg[11]),
+ .O(\cnt[8]_i_2_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[8]_i_3
+ (.I0(Q[10]),
+ .I1(cnt1),
+ .I2(cnt_reg[10]),
+ .O(\cnt[8]_i_3_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[8]_i_4
+ (.I0(Q[9]),
+ .I1(cnt1),
+ .I2(cnt_reg[9]),
+ .O(\cnt[8]_i_4_n_0 ));
+ LUT3 #(
+ .INIT(8'hB8))
+ \cnt[8]_i_5
+ (.I0(Q[8]),
+ .I1(cnt1),
+ .I2(cnt_reg[8]),
+ .O(\cnt[8]_i_5_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[8]_i_6
+ (.I0(cnt_reg[11]),
+ .I1(Q[11]),
+ .I2(cnt1),
+ .O(\cnt[8]_i_6_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[8]_i_7
+ (.I0(cnt_reg[10]),
+ .I1(Q[10]),
+ .I2(cnt1),
+ .O(\cnt[8]_i_7_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[8]_i_8
+ (.I0(cnt_reg[9]),
+ .I1(Q[9]),
+ .I2(cnt1),
+ .O(\cnt[8]_i_8_n_0 ));
+ LUT3 #(
+ .INIT(8'hC5))
+ \cnt[8]_i_9
+ (.I0(cnt_reg[8]),
+ .I1(Q[8]),
+ .I2(cnt1),
+ .O(\cnt[8]_i_9_n_0 ));
+ FDCE \cnt_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[0]_i_2_n_7 ),
+ .Q(cnt_reg[0]));
+ CARRY4 \cnt_reg[0]_i_2
+ (.CI(1'b0),
+ .CO({\cnt_reg[0]_i_2_n_0 ,\cnt_reg[0]_i_2_n_1 ,\cnt_reg[0]_i_2_n_2 ,\cnt_reg[0]_i_2_n_3 }),
+ .CYINIT(1'b0),
+ .DI({\cnt[0]_i_3_n_0 ,\cnt[0]_i_4_n_0 ,\cnt[0]_i_5_n_0 ,\cnt[0]_i_6_n_0 }),
+ .O({\cnt_reg[0]_i_2_n_4 ,\cnt_reg[0]_i_2_n_5 ,\cnt_reg[0]_i_2_n_6 ,\cnt_reg[0]_i_2_n_7 }),
+ .S({\cnt[0]_i_7_n_0 ,\cnt[0]_i_8_n_0 ,\cnt[0]_i_9_n_0 ,\cnt[0]_i_10_n_0 }));
+ FDCE \cnt_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[8]_i_1_n_5 ),
+ .Q(cnt_reg[10]));
+ FDCE \cnt_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[8]_i_1_n_4 ),
+ .Q(cnt_reg[11]));
+ FDCE \cnt_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[12]_i_1_n_7 ),
+ .Q(cnt_reg[12]));
+ CARRY4 \cnt_reg[12]_i_1
+ (.CI(\cnt_reg[8]_i_1_n_0 ),
+ .CO({\NLW_cnt_reg[12]_i_1_CO_UNCONNECTED [3],\cnt_reg[12]_i_1_n_1 ,\cnt_reg[12]_i_1_n_2 ,\cnt_reg[12]_i_1_n_3 }),
+ .CYINIT(1'b0),
+ .DI({1'b0,\cnt[12]_i_2_n_0 ,\cnt[12]_i_3_n_0 ,\cnt[12]_i_4_n_0 }),
+ .O({\cnt_reg[12]_i_1_n_4 ,\cnt_reg[12]_i_1_n_5 ,\cnt_reg[12]_i_1_n_6 ,\cnt_reg[12]_i_1_n_7 }),
+ .S({\cnt[12]_i_5_n_0 ,\cnt[12]_i_6_n_0 ,\cnt[12]_i_7_n_0 ,\cnt[12]_i_8_n_0 }));
+ FDCE \cnt_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[12]_i_1_n_6 ),
+ .Q(cnt_reg[13]));
+ FDCE \cnt_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[12]_i_1_n_5 ),
+ .Q(cnt_reg[14]));
+ FDCE \cnt_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[12]_i_1_n_4 ),
+ .Q(cnt_reg[15]));
+ FDCE \cnt_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[0]_i_2_n_6 ),
+ .Q(cnt_reg[1]));
+ FDCE \cnt_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[0]_i_2_n_5 ),
+ .Q(cnt_reg[2]));
+ FDCE \cnt_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[0]_i_2_n_4 ),
+ .Q(cnt_reg[3]));
+ FDCE \cnt_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[4]_i_1_n_7 ),
+ .Q(cnt_reg[4]));
+ CARRY4 \cnt_reg[4]_i_1
+ (.CI(\cnt_reg[0]_i_2_n_0 ),
+ .CO({\cnt_reg[4]_i_1_n_0 ,\cnt_reg[4]_i_1_n_1 ,\cnt_reg[4]_i_1_n_2 ,\cnt_reg[4]_i_1_n_3 }),
+ .CYINIT(1'b0),
+ .DI({\cnt[4]_i_2_n_0 ,\cnt[4]_i_3_n_0 ,\cnt[4]_i_4_n_0 ,\cnt[4]_i_5_n_0 }),
+ .O({\cnt_reg[4]_i_1_n_4 ,\cnt_reg[4]_i_1_n_5 ,\cnt_reg[4]_i_1_n_6 ,\cnt_reg[4]_i_1_n_7 }),
+ .S({\cnt[4]_i_6_n_0 ,\cnt[4]_i_7_n_0 ,\cnt[4]_i_8_n_0 ,\cnt[4]_i_9_n_0 }));
+ FDCE \cnt_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[4]_i_1_n_6 ),
+ .Q(cnt_reg[5]));
+ FDCE \cnt_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[4]_i_1_n_5 ),
+ .Q(cnt_reg[6]));
+ FDCE \cnt_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[4]_i_1_n_4 ),
+ .Q(cnt_reg[7]));
+ FDCE \cnt_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[8]_i_1_n_7 ),
+ .Q(cnt_reg[8]));
+ CARRY4 \cnt_reg[8]_i_1
+ (.CI(\cnt_reg[4]_i_1_n_0 ),
+ .CO({\cnt_reg[8]_i_1_n_0 ,\cnt_reg[8]_i_1_n_1 ,\cnt_reg[8]_i_1_n_2 ,\cnt_reg[8]_i_1_n_3 }),
+ .CYINIT(1'b0),
+ .DI({\cnt[8]_i_2_n_0 ,\cnt[8]_i_3_n_0 ,\cnt[8]_i_4_n_0 ,\cnt[8]_i_5_n_0 }),
+ .O({\cnt_reg[8]_i_1_n_4 ,\cnt_reg[8]_i_1_n_5 ,\cnt_reg[8]_i_1_n_6 ,\cnt_reg[8]_i_1_n_7 }),
+ .S({\cnt[8]_i_6_n_0 ,\cnt[8]_i_7_n_0 ,\cnt[8]_i_8_n_0 ,\cnt[8]_i_9_n_0 }));
+ FDCE \cnt_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(\cnt[0]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(\cnt_reg[8]_i_1_n_6 ),
+ .Q(cnt_reg[9]));
+ LUT6 #(
+ .INIT(64'h55FDFDFDFFFFFFFF))
+ \cr[7]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(i2c_al),
+ .I2(cmd_ack),
+ .I3(iack_o_reg),
+ .I4(wb_we_o),
+ .I5(iack_o_reg_0),
+ .O(\cr_reg[4] ));
+ FDCE dscl_oen_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(i2c_scl_t),
+ .Q(dscl_oen));
+ LUT5 #(
+ .INIT(32'hFBFFFBF3))
+ iscl_oen_i_1
+ (.I0(iscl_oen),
+ .I1(s00_axi_aresetn),
+ .I2(i2c_al),
+ .I3(iscl_oen9_out__0),
+ .I4(i2c_scl_t),
+ .O(iscl_oen_i_1_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ iscl_oen_i_2
+ (.I0(s00_axi_aresetn),
+ .O(iscl_oen_reg_0));
+ LUT5 #(
+ .INIT(32'h00F3011F))
+ iscl_oen_i_3
+ (.I0(c_state[3]),
+ .I1(c_state[2]),
+ .I2(c_state[1]),
+ .I3(c_state[4]),
+ .I4(c_state[0]),
+ .O(iscl_oen));
+ LUT5 #(
+ .INIT(32'h55560000))
+ iscl_oen_i_4
+ (.I0(c_state[4]),
+ .I1(c_state[3]),
+ .I2(c_state[2]),
+ .I3(c_state[1]),
+ .I4(clk_en),
+ .O(iscl_oen9_out__0));
+ FDPE iscl_oen_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(iscl_oen_i_1_n_0),
+ .PRE(iscl_oen_reg_0),
+ .Q(i2c_scl_t));
+ LUT5 #(
+ .INIT(32'hFBFFFBF3))
+ isda_oen_i_1
+ (.I0(isda_oen),
+ .I1(s00_axi_aresetn),
+ .I2(i2c_al),
+ .I3(isda_oen7_out__0),
+ .I4(i2c_sda_t),
+ .O(isda_oen_i_1_n_0));
+ LUT6 #(
+ .INIT(64'h0000C8CB03038F83))
+ isda_oen_i_2
+ (.I0(\statemachine.core_txd_reg_0 ),
+ .I1(c_state[3]),
+ .I2(c_state[2]),
+ .I3(c_state[0]),
+ .I4(c_state[4]),
+ .I5(c_state[1]),
+ .O(isda_oen));
+ LUT6 #(
+ .INIT(64'h0F0F1F1E00000000))
+ isda_oen_i_3
+ (.I0(c_state[1]),
+ .I1(c_state[2]),
+ .I2(c_state[4]),
+ .I3(c_state[0]),
+ .I4(c_state[3]),
+ .I5(clk_en),
+ .O(isda_oen7_out__0));
+ FDPE isda_oen_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(isda_oen_i_1_n_0),
+ .PRE(iscl_oen_reg_0),
+ .Q(i2c_sda_t));
+ CARRY4 minusOp_carry
+ (.CI(1'b0),
+ .CO({minusOp_carry_n_0,minusOp_carry_n_1,minusOp_carry_n_2,minusOp_carry_n_3}),
+ .CYINIT(filter_cnt[0]),
+ .DI(filter_cnt[4:1]),
+ .O({minusOp_carry_n_4,minusOp_carry_n_5,minusOp_carry_n_6,minusOp_carry_n_7}),
+ .S({minusOp_carry_i_1_n_0,minusOp_carry_i_2_n_0,minusOp_carry_i_3_n_0,minusOp_carry_i_4_n_0}));
+ CARRY4 minusOp_carry__0
+ (.CI(minusOp_carry_n_0),
+ .CO({minusOp_carry__0_n_0,minusOp_carry__0_n_1,minusOp_carry__0_n_2,minusOp_carry__0_n_3}),
+ .CYINIT(1'b0),
+ .DI(filter_cnt[8:5]),
+ .O({minusOp_carry__0_n_4,minusOp_carry__0_n_5,minusOp_carry__0_n_6,minusOp_carry__0_n_7}),
+ .S({minusOp_carry__0_i_1_n_0,minusOp_carry__0_i_2_n_0,minusOp_carry__0_i_3_n_0,minusOp_carry__0_i_4_n_0}));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__0_i_1
+ (.I0(filter_cnt[8]),
+ .O(minusOp_carry__0_i_1_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__0_i_2
+ (.I0(filter_cnt[7]),
+ .O(minusOp_carry__0_i_2_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__0_i_3
+ (.I0(filter_cnt[6]),
+ .O(minusOp_carry__0_i_3_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__0_i_4
+ (.I0(filter_cnt[5]),
+ .O(minusOp_carry__0_i_4_n_0));
+ CARRY4 minusOp_carry__1
+ (.CI(minusOp_carry__0_n_0),
+ .CO({minusOp_carry__1_n_0,minusOp_carry__1_n_1,minusOp_carry__1_n_2,minusOp_carry__1_n_3}),
+ .CYINIT(1'b0),
+ .DI(filter_cnt[12:9]),
+ .O({minusOp_carry__1_n_4,minusOp_carry__1_n_5,minusOp_carry__1_n_6,minusOp_carry__1_n_7}),
+ .S({minusOp_carry__1_i_1_n_0,minusOp_carry__1_i_2_n_0,minusOp_carry__1_i_3_n_0,minusOp_carry__1_i_4_n_0}));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__1_i_1
+ (.I0(filter_cnt[12]),
+ .O(minusOp_carry__1_i_1_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__1_i_2
+ (.I0(filter_cnt[11]),
+ .O(minusOp_carry__1_i_2_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__1_i_3
+ (.I0(filter_cnt[10]),
+ .O(minusOp_carry__1_i_3_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__1_i_4
+ (.I0(filter_cnt[9]),
+ .O(minusOp_carry__1_i_4_n_0));
+ CARRY4 minusOp_carry__2
+ (.CI(minusOp_carry__1_n_0),
+ .CO(NLW_minusOp_carry__2_CO_UNCONNECTED[3:0]),
+ .CYINIT(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0}),
+ .O({NLW_minusOp_carry__2_O_UNCONNECTED[3:1],minusOp_carry__2_n_7}),
+ .S({1'b0,1'b0,1'b0,minusOp_carry__2_i_1_n_0}));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry__2_i_1
+ (.I0(filter_cnt[13]),
+ .O(minusOp_carry__2_i_1_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry_i_1
+ (.I0(filter_cnt[4]),
+ .O(minusOp_carry_i_1_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry_i_2
+ (.I0(filter_cnt[3]),
+ .O(minusOp_carry_i_2_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry_i_3
+ (.I0(filter_cnt[2]),
+ .O(minusOp_carry_i_3_n_0));
+ LUT1 #(
+ .INIT(2'h1))
+ minusOp_carry_i_4
+ (.I0(filter_cnt[1]),
+ .O(minusOp_carry_i_4_n_0));
+ LUT6 #(
+ .INIT(64'h0000000000100000))
+ sda_chk_i_1
+ (.I0(c_state[4]),
+ .I1(c_state[1]),
+ .I2(c_state[3]),
+ .I3(c_state[0]),
+ .I4(c_state[2]),
+ .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .O(sda_chk_i_1_n_0));
+ FDCE sda_chk_reg
+ (.C(s00_axi_aclk),
+ .CE(\FSM_sequential_c_state[4]_i_1_n_0 ),
+ .CLR(iscl_oen_reg_0),
+ .D(sda_chk_i_1_n_0),
+ .Q(sda_chk_reg_n_0));
+ LUT4 #(
+ .INIT(16'h0F04))
+ slave_wait_i_1
+ (.I0(dscl_oen),
+ .I1(i2c_scl_t),
+ .I2(sSCL),
+ .I3(slave_wait),
+ .O(slave_wait0));
+ FDCE slave_wait_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg_0),
+ .D(slave_wait0),
+ .Q(slave_wait));
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[0]_i_1
+ (.I0(\statemachine.ld_reg_0 ),
+ .I1(core_rxd),
+ .I2(\txr_reg[6] [0]),
+ .I3(s00_axi_aresetn),
+ .O(\sr_reg[0] ));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT4 #(
+ .INIT(16'hAA08))
+ \st_irq_block.al_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(\st_irq_block.al_reg ),
+ .I2(\cr_reg[7] [3]),
+ .I3(i2c_al),
+ .O(al));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
+ LUT5 #(
+ .INIT(32'h55540000))
+ \st_irq_block.irq_flag_i_1
+ (.I0(\cr_reg[0] ),
+ .I1(i2c_al),
+ .I2(cmd_ack),
+ .I3(irq_flag),
+ .I4(s00_axi_aresetn),
+ .O(irq_flag1_out));
+ LUT5 #(
+ .INIT(32'h08FF0800))
+ \statemachine.ack_out_i_1
+ (.I0(core_rxd),
+ .I1(s00_axi_aresetn),
+ .I2(i2c_al),
+ .I3(\statemachine.ack_out_i_2_n_0 ),
+ .I4(ack_out),
+ .O(\statemachine.ack_out_reg ));
+ LUT6 #(
+ .INIT(64'hDDDDDDDDDDFDDDDD))
+ \statemachine.ack_out_i_2
+ (.I0(s00_axi_aresetn),
+ .I1(i2c_al),
+ .I2(out[2]),
+ .I3(out[0]),
+ .I4(core_ack),
+ .I5(out[1]),
+ .O(\statemachine.ack_out_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000100000))
+ \statemachine.core_cmd[0]_i_1
+ (.I0(out[2]),
+ .I1(out[0]),
+ .I2(\cr_reg[7] [3]),
+ .I3(out[1]),
+ .I4(s00_axi_aresetn),
+ .I5(i2c_al),
+ .O(\statemachine.core_cmd_reg[3] [0]));
+ LUT6 #(
+ .INIT(64'h0000000022222E22))
+ \statemachine.core_cmd[1]_i_1
+ (.I0(\FSM_sequential_statemachine.c_state_reg[1]_0 ),
+ .I1(out[2]),
+ .I2(out[1]),
+ .I3(\cr_reg[7] [2]),
+ .I4(out[0]),
+ .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .O(\statemachine.core_cmd_reg[3] [1]));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT3 #(
+ .INIT(8'h08))
+ \statemachine.core_cmd[2]_i_1
+ (.I0(core_cmd),
+ .I1(s00_axi_aresetn),
+ .I2(i2c_al),
+ .O(\statemachine.core_cmd_reg[3] [2]));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT4 #(
+ .INIT(16'h0040))
+ \statemachine.core_cmd[3]_i_1
+ (.I0(out[2]),
+ .I1(\FSM_sequential_statemachine.c_state_reg[1] ),
+ .I2(s00_axi_aresetn),
+ .I3(i2c_al),
+ .O(\statemachine.core_cmd_reg[3] [3]));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT3 #(
+ .INIT(8'h08))
+ \statemachine.core_txd_i_1
+ (.I0(core_txd),
+ .I1(s00_axi_aresetn),
+ .I2(i2c_al),
+ .O(\statemachine.core_txd_reg ));
+ LUT6 #(
+ .INIT(64'h5455FFFD10002220))
+ \statemachine.core_txd_i_2
+ (.I0(out[2]),
+ .I1(out[0]),
+ .I2(ack_in),
+ .I3(core_ack),
+ .I4(out[1]),
+ .I5(\sr_reg[7] ),
+ .O(core_txd));
+ LUT6 #(
+ .INIT(64'h000000000000A020))
+ \statemachine.host_ack_i_1
+ (.I0(out[2]),
+ .I1(\cr_reg[7] [2]),
+ .I2(core_ack),
+ .I3(out[0]),
+ .I4(out[1]),
+ .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .O(\statemachine.host_ack_reg ));
+ LUT5 #(
+ .INIT(32'h00000400))
+ \statemachine.ld_i_1
+ (.I0(out[2]),
+ .I1(\FSM_sequential_statemachine.c_state[2]_i_3_n_0 ),
+ .I2(out[1]),
+ .I3(s00_axi_aresetn),
+ .I4(i2c_al),
+ .O(\statemachine.ld_reg ));
+ LUT6 #(
+ .INIT(64'h0000000004440000))
+ \statemachine.shift_i_1
+ (.I0(out[2]),
+ .I1(core_ack),
+ .I2(out[0]),
+ .I3(cnt_done),
+ .I4(out[1]),
+ .I5(\FSM_sequential_c_state[4]_i_3_n_0 ),
+ .O(\statemachine.shift_reg ));
+ LUT5 #(
+ .INIT(32'h30BB3088))
+ \wb_dat_o[6]_i_3
+ (.I0(\cr_reg[7] [2]),
+ .I1(wb_adr_o[1]),
+ .I2(\txr_reg[6] [1]),
+ .I3(wb_adr_o[0]),
+ .I4(i2c_busy),
+ .O(\wb_dat_o[6]_i_3_n_0 ));
+ MUXF7 \wb_dat_o_reg[6]_i_1
+ (.I0(\sr_reg[6] ),
+ .I1(\wb_dat_o[6]_i_3_n_0 ),
+ .O(D),
+ .S(wb_adr_o[2]));
+endmodule
+
+(* ORIG_REF_NAME = "i2c_master_byte_ctrl" *)
+module system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
+ (iscl_oen_reg,
+ i2c_scl_t,
+ i2c_sda_t,
+ irq_flag1_out,
+ rxack_0,
+ al,
+ D,
+ E,
+ s00_axi_aclk,
+ s00_axi_aresetn,
+ \cr_reg[0] ,
+ irq_flag,
+ Q,
+ \ctr_reg[7] ,
+ i2c_sda_i,
+ i2c_scl_i,
+ \st_irq_block.al_reg ,
+ \cr_reg[7] ,
+ wb_adr_o,
+ \cr_reg[0]_0 ,
+ \cr_reg[1] ,
+ \cr_reg[2] ,
+ \txr_reg[7] ,
+ ack_in,
+ \cr_reg[5] ,
+ \cr_reg[7]_0 ,
+ iack_o_reg,
+ wb_we_o,
+ iack_o_reg_0);
+ output iscl_oen_reg;
+ output i2c_scl_t;
+ output i2c_sda_t;
+ output irq_flag1_out;
+ output rxack_0;
+ output al;
+ output [7:0]D;
+ output [0:0]E;
+ input s00_axi_aclk;
+ input s00_axi_aresetn;
+ input \cr_reg[0] ;
+ input irq_flag;
+ input [15:0]Q;
+ input [7:0]\ctr_reg[7] ;
+ input i2c_sda_i;
+ input i2c_scl_i;
+ input \st_irq_block.al_reg ;
+ input [3:0]\cr_reg[7] ;
+ input [2:0]wb_adr_o;
+ input \cr_reg[0]_0 ;
+ input \cr_reg[1] ;
+ input \cr_reg[2] ;
+ input [7:0]\txr_reg[7] ;
+ input ack_in;
+ input \cr_reg[5] ;
+ input \cr_reg[7]_0 ;
+ input iack_o_reg;
+ input wb_we_o;
+ input iack_o_reg_0;
+
+ wire [7:0]D;
+ wire [0:0]E;
+ wire \FSM_sequential_statemachine.c_state[0]_i_2_n_0 ;
+ wire \FSM_sequential_statemachine.c_state[1]_i_3_n_0 ;
+ wire \FSM_sequential_statemachine.c_state[2]_i_4_n_0 ;
+ wire [15:0]Q;
+ wire ack_in;
+ wire ack_out;
+ wire al;
+ wire bit_ctrl_n_10;
+ wire bit_ctrl_n_11;
+ wire bit_ctrl_n_12;
+ wire bit_ctrl_n_13;
+ wire bit_ctrl_n_14;
+ wire bit_ctrl_n_15;
+ wire bit_ctrl_n_17;
+ wire bit_ctrl_n_18;
+ wire bit_ctrl_n_19;
+ wire bit_ctrl_n_20;
+ wire bit_ctrl_n_7;
+ wire bit_ctrl_n_8;
+ wire bit_ctrl_n_9;
+ wire c_state;
+ (* RTL_KEEP = "yes" *) wire [2:0]c_state__0;
+ wire [3:0]cmd;
+ wire cmd_ack;
+ wire cnt_done;
+ wire [2:2]core_cmd;
+ wire \cr_reg[0] ;
+ wire \cr_reg[0]_0 ;
+ wire \cr_reg[1] ;
+ wire \cr_reg[2] ;
+ wire \cr_reg[5] ;
+ wire [3:0]\cr_reg[7] ;
+ wire \cr_reg[7]_0 ;
+ wire [7:0]\ctr_reg[7] ;
+ wire dcnt;
+ wire \dcnt[0]_i_1_n_0 ;
+ wire \dcnt[1]_i_1_n_0 ;
+ wire \dcnt[2]_i_1_n_0 ;
+ wire \dcnt_reg_n_0_[0] ;
+ wire \dcnt_reg_n_0_[1] ;
+ wire \dcnt_reg_n_0_[2] ;
+ wire [7:7]dout;
+ wire i2c_scl_i;
+ wire i2c_scl_t;
+ wire i2c_sda_i;
+ wire i2c_sda_t;
+ wire iack_o_reg;
+ wire iack_o_reg_0;
+ wire irq_flag;
+ wire irq_flag1_out;
+ wire iscl_oen_reg;
+ wire rxack_0;
+ wire s00_axi_aclk;
+ wire s00_axi_aresetn;
+ wire \sr[1]_i_1_n_0 ;
+ wire \sr[2]_i_1_n_0 ;
+ wire \sr[3]_i_1_n_0 ;
+ wire \sr[4]_i_1_n_0 ;
+ wire \sr[5]_i_1_n_0 ;
+ wire \sr[6]_i_1_n_0 ;
+ wire \sr[7]_i_2_n_0 ;
+ wire \sr_reg_n_0_[0] ;
+ wire \sr_reg_n_0_[1] ;
+ wire \sr_reg_n_0_[2] ;
+ wire \sr_reg_n_0_[3] ;
+ wire \sr_reg_n_0_[4] ;
+ wire \sr_reg_n_0_[5] ;
+ wire \sr_reg_n_0_[6] ;
+ wire \st_irq_block.al_reg ;
+ wire \statemachine.core_cmd[1]_i_2_n_0 ;
+ wire \statemachine.core_cmd[3]_i_2_n_0 ;
+ wire \statemachine.core_txd_reg_n_0 ;
+ wire \statemachine.ld_reg_n_0 ;
+ wire \statemachine.shift_reg_n_0 ;
+ wire [7:0]\txr_reg[7] ;
+ wire [2:0]wb_adr_o;
+ wire \wb_dat_o[0]_i_2_n_0 ;
+ wire \wb_dat_o[1]_i_2_n_0 ;
+ wire \wb_dat_o[2]_i_2_n_0 ;
+ wire \wb_dat_o[3]_i_2_n_0 ;
+ wire \wb_dat_o[4]_i_2_n_0 ;
+ wire \wb_dat_o[5]_i_2_n_0 ;
+ wire \wb_dat_o[6]_i_2_n_0 ;
+ wire \wb_dat_o[7]_i_2_n_0 ;
+ wire wb_we_o;
+
+ LUT5 #(
+ .INIT(32'h43407373))
+ \FSM_sequential_statemachine.c_state[0]_i_2
+ (.I0(cnt_done),
+ .I1(c_state__0[1]),
+ .I2(c_state__0[0]),
+ .I3(\cr_reg[7] [3]),
+ .I4(\cr_reg[7] [1]),
+ .O(\FSM_sequential_statemachine.c_state[0]_i_2_n_0 ));
+ LUT3 #(
+ .INIT(8'h01))
+ \FSM_sequential_statemachine.c_state[1]_i_2
+ (.I0(\dcnt_reg_n_0_[1] ),
+ .I1(\dcnt_reg_n_0_[0] ),
+ .I2(\dcnt_reg_n_0_[2] ),
+ .O(cnt_done));
+ LUT4 #(
+ .INIT(16'hFF54))
+ \FSM_sequential_statemachine.c_state[1]_i_3
+ (.I0(\cr_reg[7] [3]),
+ .I1(\cr_reg[7] [1]),
+ .I2(\cr_reg[7] [0]),
+ .I3(c_state__0[0]),
+ .O(\FSM_sequential_statemachine.c_state[1]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'h888888888888888B))
+ \FSM_sequential_statemachine.c_state[2]_i_4
+ (.I0(cnt_done),
+ .I1(c_state__0[1]),
+ .I2(\cr_reg[7] [3]),
+ .I3(\cr_reg[7] [0]),
+ .I4(\cr_reg[7] [1]),
+ .I5(c_state__0[0]),
+ .O(\FSM_sequential_statemachine.c_state[2]_i_4_n_0 ));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_statemachine.c_state_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(c_state),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_20),
+ .Q(c_state__0[0]));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_statemachine.c_state_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(c_state),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_19),
+ .Q(c_state__0[1]));
+ (* KEEP = "yes" *)
+ FDCE \FSM_sequential_statemachine.c_state_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(c_state),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_18),
+ .Q(c_state__0[2]));
+ system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl bit_ctrl
+ (.D(D[6]),
+ .E(c_state),
+ .\FSM_sequential_statemachine.c_state_reg[1] (\statemachine.core_cmd[3]_i_2_n_0 ),
+ .\FSM_sequential_statemachine.c_state_reg[1]_0 (\statemachine.core_cmd[1]_i_2_n_0 ),
+ .\FSM_sequential_statemachine.c_state_reg[1]_1 (\FSM_sequential_statemachine.c_state[0]_i_2_n_0 ),
+ .\FSM_sequential_statemachine.c_state_reg[1]_2 (\FSM_sequential_statemachine.c_state[2]_i_4_n_0 ),
+ .\FSM_sequential_statemachine.c_state_reg[2] ({bit_ctrl_n_18,bit_ctrl_n_19,bit_ctrl_n_20}),
+ .Q(Q),
+ .ack_in(ack_in),
+ .ack_out(ack_out),
+ .al(al),
+ .cmd_ack(cmd_ack),
+ .cnt_done(cnt_done),
+ .core_cmd(core_cmd),
+ .\cr_reg[0] (\cr_reg[0] ),
+ .\cr_reg[4] (E),
+ .\cr_reg[7] (\cr_reg[7] ),
+ .\cr_reg[7]_0 (\FSM_sequential_statemachine.c_state[1]_i_3_n_0 ),
+ .\ctr_reg[7] (\ctr_reg[7] [7]),
+ .i2c_scl_i(i2c_scl_i),
+ .i2c_scl_t(i2c_scl_t),
+ .i2c_sda_i(i2c_sda_i),
+ .i2c_sda_t(i2c_sda_t),
+ .iack_o_reg(iack_o_reg),
+ .iack_o_reg_0(iack_o_reg_0),
+ .irq_flag(irq_flag),
+ .irq_flag1_out(irq_flag1_out),
+ .iscl_oen_reg_0(iscl_oen_reg),
+ .out(c_state__0),
+ .s00_axi_aclk(s00_axi_aclk),
+ .s00_axi_aresetn(s00_axi_aresetn),
+ .\sr_reg[0] (bit_ctrl_n_17),
+ .\sr_reg[6] (\wb_dat_o[6]_i_2_n_0 ),
+ .\sr_reg[7] (dout),
+ .\st_irq_block.al_reg (\st_irq_block.al_reg ),
+ .\statemachine.ack_out_reg (bit_ctrl_n_15),
+ .\statemachine.core_cmd_reg[3] ({bit_ctrl_n_7,bit_ctrl_n_8,bit_ctrl_n_9,bit_ctrl_n_10}),
+ .\statemachine.core_cmd_reg[3]_0 (cmd),
+ .\statemachine.core_txd_reg (bit_ctrl_n_12),
+ .\statemachine.core_txd_reg_0 (\statemachine.core_txd_reg_n_0 ),
+ .\statemachine.host_ack_reg (bit_ctrl_n_14),
+ .\statemachine.ld_reg (bit_ctrl_n_11),
+ .\statemachine.ld_reg_0 (\statemachine.ld_reg_n_0 ),
+ .\statemachine.shift_reg (bit_ctrl_n_13),
+ .\txr_reg[6] ({\txr_reg[7] [6],\txr_reg[7] [0]}),
+ .wb_adr_o(wb_adr_o),
+ .wb_we_o(wb_we_o));
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
+ LUT3 #(
+ .INIT(8'h8A))
+ \dcnt[0]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(\statemachine.ld_reg_n_0 ),
+ .I2(\dcnt_reg_n_0_[0] ),
+ .O(\dcnt[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
+ LUT4 #(
+ .INIT(16'hA88A))
+ \dcnt[1]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(\statemachine.ld_reg_n_0 ),
+ .I2(\dcnt_reg_n_0_[0] ),
+ .I3(\dcnt_reg_n_0_[1] ),
+ .O(\dcnt[1]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
+ LUT5 #(
+ .INIT(32'hAAA8888A))
+ \dcnt[2]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(\statemachine.ld_reg_n_0 ),
+ .I2(\dcnt_reg_n_0_[1] ),
+ .I3(\dcnt_reg_n_0_[0] ),
+ .I4(\dcnt_reg_n_0_[2] ),
+ .O(\dcnt[2]_i_1_n_0 ));
+ FDCE \dcnt_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\dcnt[0]_i_1_n_0 ),
+ .Q(\dcnt_reg_n_0_[0] ));
+ FDCE \dcnt_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\dcnt[1]_i_1_n_0 ),
+ .Q(\dcnt_reg_n_0_[1] ));
+ FDCE \dcnt_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\dcnt[2]_i_1_n_0 ),
+ .Q(\dcnt_reg_n_0_[2] ));
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[1]_i_1
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(\sr_reg_n_0_[0] ),
+ .I2(\txr_reg[7] [1]),
+ .I3(s00_axi_aresetn),
+ .O(\sr[1]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[2]_i_1
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(\sr_reg_n_0_[1] ),
+ .I2(\txr_reg[7] [2]),
+ .I3(s00_axi_aresetn),
+ .O(\sr[2]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[3]_i_1
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(\sr_reg_n_0_[2] ),
+ .I2(\txr_reg[7] [3]),
+ .I3(s00_axi_aresetn),
+ .O(\sr[3]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[4]_i_1
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(\sr_reg_n_0_[3] ),
+ .I2(\txr_reg[7] [4]),
+ .I3(s00_axi_aresetn),
+ .O(\sr[4]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[5]_i_1
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(\sr_reg_n_0_[4] ),
+ .I2(\txr_reg[7] [5]),
+ .I3(s00_axi_aresetn),
+ .O(\sr[5]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[6]_i_1
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(\sr_reg_n_0_[5] ),
+ .I2(\txr_reg[7] [6]),
+ .I3(s00_axi_aresetn),
+ .O(\sr[6]_i_1_n_0 ));
+ LUT3 #(
+ .INIT(8'hFB))
+ \sr[7]_i_1
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(s00_axi_aresetn),
+ .I2(\statemachine.shift_reg_n_0 ),
+ .O(dcnt));
+ LUT4 #(
+ .INIT(16'hE400))
+ \sr[7]_i_2
+ (.I0(\statemachine.ld_reg_n_0 ),
+ .I1(\sr_reg_n_0_[6] ),
+ .I2(\txr_reg[7] [7]),
+ .I3(s00_axi_aresetn),
+ .O(\sr[7]_i_2_n_0 ));
+ FDCE \sr_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_17),
+ .Q(\sr_reg_n_0_[0] ));
+ FDCE \sr_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\sr[1]_i_1_n_0 ),
+ .Q(\sr_reg_n_0_[1] ));
+ FDCE \sr_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\sr[2]_i_1_n_0 ),
+ .Q(\sr_reg_n_0_[2] ));
+ FDCE \sr_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\sr[3]_i_1_n_0 ),
+ .Q(\sr_reg_n_0_[3] ));
+ FDCE \sr_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\sr[4]_i_1_n_0 ),
+ .Q(\sr_reg_n_0_[4] ));
+ FDCE \sr_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\sr[5]_i_1_n_0 ),
+ .Q(\sr_reg_n_0_[5] ));
+ FDCE \sr_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\sr[6]_i_1_n_0 ),
+ .Q(\sr_reg_n_0_[6] ));
+ FDCE \sr_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(dcnt),
+ .CLR(iscl_oen_reg),
+ .D(\sr[7]_i_2_n_0 ),
+ .Q(dout));
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \st_irq_block.rxack_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(ack_out),
+ .O(rxack_0));
+ FDCE \statemachine.ack_out_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_15),
+ .Q(ack_out));
+ LUT5 #(
+ .INIT(32'h00000001))
+ \statemachine.core_cmd[1]_i_2
+ (.I0(c_state__0[1]),
+ .I1(c_state__0[0]),
+ .I2(\cr_reg[7] [3]),
+ .I3(\cr_reg[7] [0]),
+ .I4(\cr_reg[7] [1]),
+ .O(\statemachine.core_cmd[1]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h00000000F0C40FC4))
+ \statemachine.core_cmd[2]_i_2
+ (.I0(\cr_reg[7] [3]),
+ .I1(\cr_reg[7] [1]),
+ .I2(c_state__0[0]),
+ .I3(c_state__0[1]),
+ .I4(cnt_done),
+ .I5(c_state__0[2]),
+ .O(core_cmd));
+ LUT6 #(
+ .INIT(64'h4848484878787B78))
+ \statemachine.core_cmd[3]_i_2
+ (.I0(cnt_done),
+ .I1(c_state__0[1]),
+ .I2(c_state__0[0]),
+ .I3(\cr_reg[7] [0]),
+ .I4(\cr_reg[7] [3]),
+ .I5(\cr_reg[7] [1]),
+ .O(\statemachine.core_cmd[3]_i_2_n_0 ));
+ FDCE \statemachine.core_cmd_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(c_state),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_10),
+ .Q(cmd[0]));
+ FDCE \statemachine.core_cmd_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(c_state),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_9),
+ .Q(cmd[1]));
+ FDCE \statemachine.core_cmd_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(c_state),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_8),
+ .Q(cmd[2]));
+ FDCE \statemachine.core_cmd_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(c_state),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_7),
+ .Q(cmd[3]));
+ FDCE \statemachine.core_txd_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_12),
+ .Q(\statemachine.core_txd_reg_n_0 ));
+ FDCE \statemachine.host_ack_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_14),
+ .Q(cmd_ack));
+ FDCE \statemachine.ld_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_11),
+ .Q(\statemachine.ld_reg_n_0 ));
+ FDCE \statemachine.shift_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(iscl_oen_reg),
+ .D(bit_ctrl_n_13),
+ .Q(\statemachine.shift_reg_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[0]_i_2
+ (.I0(\sr_reg_n_0_[0] ),
+ .I1(\ctr_reg[7] [0]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[8]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[0]),
+ .O(\wb_dat_o[0]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[1]_i_2
+ (.I0(\sr_reg_n_0_[1] ),
+ .I1(\ctr_reg[7] [1]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[9]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[1]),
+ .O(\wb_dat_o[1]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h3808FFFF38080000))
+ \wb_dat_o[2]_i_1
+ (.I0(\cr_reg[2] ),
+ .I1(wb_adr_o[1]),
+ .I2(wb_adr_o[0]),
+ .I3(\txr_reg[7] [2]),
+ .I4(wb_adr_o[2]),
+ .I5(\wb_dat_o[2]_i_2_n_0 ),
+ .O(D[2]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[2]_i_2
+ (.I0(\sr_reg_n_0_[2] ),
+ .I1(\ctr_reg[7] [2]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[10]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[2]),
+ .O(\wb_dat_o[2]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h3808FFFF38080000))
+ \wb_dat_o[3]_i_1
+ (.I0(ack_in),
+ .I1(wb_adr_o[1]),
+ .I2(wb_adr_o[0]),
+ .I3(\txr_reg[7] [3]),
+ .I4(wb_adr_o[2]),
+ .I5(\wb_dat_o[3]_i_2_n_0 ),
+ .O(D[3]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[3]_i_2
+ (.I0(\sr_reg_n_0_[3] ),
+ .I1(\ctr_reg[7] [3]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[11]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[3]),
+ .O(\wb_dat_o[3]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h3808FFFF38080000))
+ \wb_dat_o[4]_i_1
+ (.I0(\cr_reg[7] [0]),
+ .I1(wb_adr_o[1]),
+ .I2(wb_adr_o[0]),
+ .I3(\txr_reg[7] [4]),
+ .I4(wb_adr_o[2]),
+ .I5(\wb_dat_o[4]_i_2_n_0 ),
+ .O(D[4]));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[4]_i_2
+ (.I0(\sr_reg_n_0_[4] ),
+ .I1(\ctr_reg[7] [4]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[12]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[4]),
+ .O(\wb_dat_o[4]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[5]_i_2
+ (.I0(\sr_reg_n_0_[5] ),
+ .I1(\ctr_reg[7] [5]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[13]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[5]),
+ .O(\wb_dat_o[5]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[6]_i_2
+ (.I0(\sr_reg_n_0_[6] ),
+ .I1(\ctr_reg[7] [6]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[14]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[6]),
+ .O(\wb_dat_o[6]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'hAFA0CFCFAFA0C0C0))
+ \wb_dat_o[7]_i_2
+ (.I0(dout),
+ .I1(\ctr_reg[7] [7]),
+ .I2(wb_adr_o[1]),
+ .I3(Q[15]),
+ .I4(wb_adr_o[0]),
+ .I5(Q[7]),
+ .O(\wb_dat_o[7]_i_2_n_0 ));
+ MUXF7 \wb_dat_o_reg[0]_i_1
+ (.I0(\wb_dat_o[0]_i_2_n_0 ),
+ .I1(\cr_reg[0]_0 ),
+ .O(D[0]),
+ .S(wb_adr_o[2]));
+ MUXF7 \wb_dat_o_reg[1]_i_1
+ (.I0(\wb_dat_o[1]_i_2_n_0 ),
+ .I1(\cr_reg[1] ),
+ .O(D[1]),
+ .S(wb_adr_o[2]));
+ MUXF7 \wb_dat_o_reg[5]_i_1
+ (.I0(\wb_dat_o[5]_i_2_n_0 ),
+ .I1(\cr_reg[5] ),
+ .O(D[5]),
+ .S(wb_adr_o[2]));
+ MUXF7 \wb_dat_o_reg[7]_i_1
+ (.I0(\wb_dat_o[7]_i_2_n_0 ),
+ .I1(\cr_reg[7]_0 ),
+ .O(D[7]),
+ .S(wb_adr_o[2]));
+endmodule
+
+(* ORIG_REF_NAME = "i2c_master_top" *)
+module system_design_axi_wb_i2c_master_2_0_i2c_master_top
+ (wb_ack_i,
+ wb_rst_o,
+ i2c_scl_t,
+ axi_int_o,
+ i2c_sda_t,
+ Q,
+ s_stb_r_reg,
+ \s_rdata_reg[0] ,
+ \s_rdata_reg[7] ,
+ s_stb_r_reg_0,
+ s00_axi_aclk,
+ s00_axi_aresetn,
+ i2c_sda_i,
+ i2c_scl_i,
+ s00_axi_wdata,
+ wb_adr_o,
+ s00_axi_awvalid,
+ s00_axi_arvalid,
+ wb_cyc_o,
+ wb_we_o,
+ iack_o_reg_0,
+ E,
+ s_we_r_reg,
+ s_we_r_reg_0,
+ D,
+ \s_addr_reg[4] );
+ output wb_ack_i;
+ output wb_rst_o;
+ output i2c_scl_t;
+ output axi_int_o;
+ output i2c_sda_t;
+ output [0:0]Q;
+ output s_stb_r_reg;
+ output [0:0]\s_rdata_reg[0] ;
+ output [7:0]\s_rdata_reg[7] ;
+ input s_stb_r_reg_0;
+ input s00_axi_aclk;
+ input s00_axi_aresetn;
+ input i2c_sda_i;
+ input i2c_scl_i;
+ input [7:0]s00_axi_wdata;
+ input [2:0]wb_adr_o;
+ input s00_axi_awvalid;
+ input s00_axi_arvalid;
+ input wb_cyc_o;
+ input wb_we_o;
+ input iack_o_reg_0;
+ input [1:0]E;
+ input [0:0]s_we_r_reg;
+ input [0:0]s_we_r_reg_0;
+ input [3:0]D;
+ input \s_addr_reg[4] ;
+
+ wire [3:0]D;
+ wire [1:0]E;
+ wire [0:0]Q;
+ wire ack_in;
+ wire al;
+ wire axi_int_o;
+ wire byte_ctrl_n_14;
+ wire \cr[0]_i_1_n_0 ;
+ wire \cr[1]_i_1_n_0 ;
+ wire \cr[2]_i_1_n_0 ;
+ wire \cr[3]_i_1_n_0 ;
+ wire \cr_reg_n_0_[0] ;
+ wire \cr_reg_n_0_[1] ;
+ wire \cr_reg_n_0_[2] ;
+ wire [7:0]ctr;
+ wire \ctr_reg_n_0_[0] ;
+ wire \ctr_reg_n_0_[1] ;
+ wire \ctr_reg_n_0_[2] ;
+ wire \ctr_reg_n_0_[3] ;
+ wire \ctr_reg_n_0_[4] ;
+ wire \ctr_reg_n_0_[5] ;
+ wire [13:0]data0;
+ wire i2c_scl_i;
+ wire i2c_scl_t;
+ wire i2c_sda_i;
+ wire i2c_sda_t;
+ wire iack_o_reg_0;
+ wire ien;
+ wire irq_flag;
+ wire irq_flag1_out;
+ wire \prer[10]_i_1_n_0 ;
+ wire \prer[11]_i_1_n_0 ;
+ wire \prer[12]_i_1_n_0 ;
+ wire \prer[13]_i_1_n_0 ;
+ wire \prer[14]_i_1_n_0 ;
+ wire \prer[15]_i_2_n_0 ;
+ wire \prer[8]_i_1_n_0 ;
+ wire \prer[9]_i_1_n_0 ;
+ wire \prer_reg_n_0_[0] ;
+ wire \prer_reg_n_0_[1] ;
+ wire read;
+ wire rxack;
+ wire rxack_0;
+ wire s00_axi_aclk;
+ wire s00_axi_aresetn;
+ wire s00_axi_arvalid;
+ wire s00_axi_awvalid;
+ wire [7:0]s00_axi_wdata;
+ wire \s_addr_reg[4] ;
+ wire [0:0]\s_rdata_reg[0] ;
+ wire [7:0]\s_rdata_reg[7] ;
+ wire s_stb_r_reg;
+ wire s_stb_r_reg_0;
+ wire [0:0]s_we_r_reg;
+ wire [0:0]s_we_r_reg_0;
+ wire \st_irq_block.al_reg_n_0 ;
+ wire \st_irq_block.wb_inta_o_i_1_n_0 ;
+ wire start;
+ wire stop;
+ wire tip;
+ wire tip_1;
+ wire [7:0]txr;
+ wire wb_ack_i;
+ wire [2:0]wb_adr_o;
+ wire wb_cyc_o;
+ wire [7:0]wb_dat_o;
+ wire \wb_dat_o[0]_i_3_n_0 ;
+ wire \wb_dat_o[1]_i_3_n_0 ;
+ wire \wb_dat_o[5]_i_3_n_0 ;
+ wire \wb_dat_o[7]_i_3_n_0 ;
+ wire wb_rst_o;
+ wire wb_we_o;
+ wire write;
+
+ system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl byte_ctrl
+ (.D(wb_dat_o),
+ .E(byte_ctrl_n_14),
+ .Q({data0,\prer_reg_n_0_[1] ,\prer_reg_n_0_[0] }),
+ .ack_in(ack_in),
+ .al(al),
+ .\cr_reg[0] (\cr_reg_n_0_[0] ),
+ .\cr_reg[0]_0 (\wb_dat_o[0]_i_3_n_0 ),
+ .\cr_reg[1] (\wb_dat_o[1]_i_3_n_0 ),
+ .\cr_reg[2] (\cr_reg_n_0_[2] ),
+ .\cr_reg[5] (\wb_dat_o[5]_i_3_n_0 ),
+ .\cr_reg[7] ({start,stop,read,write}),
+ .\cr_reg[7]_0 (\wb_dat_o[7]_i_3_n_0 ),
+ .\ctr_reg[7] ({Q,ien,\ctr_reg_n_0_[5] ,\ctr_reg_n_0_[4] ,\ctr_reg_n_0_[3] ,\ctr_reg_n_0_[2] ,\ctr_reg_n_0_[1] ,\ctr_reg_n_0_[0] }),
+ .i2c_scl_i(i2c_scl_i),
+ .i2c_scl_t(i2c_scl_t),
+ .i2c_sda_i(i2c_sda_i),
+ .i2c_sda_t(i2c_sda_t),
+ .iack_o_reg(wb_ack_i),
+ .iack_o_reg_0(iack_o_reg_0),
+ .irq_flag(irq_flag),
+ .irq_flag1_out(irq_flag1_out),
+ .iscl_oen_reg(wb_rst_o),
+ .rxack_0(rxack_0),
+ .s00_axi_aclk(s00_axi_aclk),
+ .s00_axi_aresetn(s00_axi_aresetn),
+ .\st_irq_block.al_reg (\st_irq_block.al_reg_n_0 ),
+ .\txr_reg[7] (txr),
+ .wb_adr_o(wb_adr_o),
+ .wb_we_o(wb_we_o));
+ LUT6 #(
+ .INIT(64'h8000FFFF80000000))
+ \cr[0]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[0]),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .I4(\s_addr_reg[4] ),
+ .I5(\cr_reg_n_0_[0] ),
+ .O(\cr[0]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h8000FFFF80000000))
+ \cr[1]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[1]),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .I4(\s_addr_reg[4] ),
+ .I5(\cr_reg_n_0_[1] ),
+ .O(\cr[1]_i_1_n_0 ));
+ LUT6 #(
+ .INIT(64'h8000FFFF80000000))
+ \cr[2]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[2]),
+ .I2(wb_we_o),
+ .I3(wb_ack_i),
+ .I4(\s_addr_reg[4] ),
+ .I5(\cr_reg_n_0_[2] ),
+ .O(\cr[2]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
+ LUT4 #(
+ .INIT(16'hC808))
+ \cr[3]_i_1
+ (.I0(s00_axi_wdata[3]),
+ .I1(s00_axi_aresetn),
+ .I2(iack_o_reg_0),
+ .I3(ack_in),
+ .O(\cr[3]_i_1_n_0 ));
+ FDCE \cr_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(\cr[0]_i_1_n_0 ),
+ .Q(\cr_reg_n_0_[0] ));
+ FDCE \cr_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(\cr[1]_i_1_n_0 ),
+ .Q(\cr_reg_n_0_[1] ));
+ FDCE \cr_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(\cr[2]_i_1_n_0 ),
+ .Q(\cr_reg_n_0_[2] ));
+ FDCE \cr_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(\cr[3]_i_1_n_0 ),
+ .Q(ack_in));
+ FDCE \cr_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(byte_ctrl_n_14),
+ .CLR(wb_rst_o),
+ .D(D[0]),
+ .Q(write));
+ FDCE \cr_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(byte_ctrl_n_14),
+ .CLR(wb_rst_o),
+ .D(D[1]),
+ .Q(read));
+ FDCE \cr_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(byte_ctrl_n_14),
+ .CLR(wb_rst_o),
+ .D(D[2]),
+ .Q(stop));
+ FDCE \cr_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(byte_ctrl_n_14),
+ .CLR(wb_rst_o),
+ .D(D[3]),
+ .Q(start));
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[0]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[0]),
+ .O(ctr[0]));
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[1]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[1]),
+ .O(ctr[1]));
+ (* SOFT_HLUTNM = "soft_lutpair28" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[2]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[2]),
+ .O(ctr[2]));
+ (* SOFT_HLUTNM = "soft_lutpair24" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[3]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[3]),
+ .O(ctr[3]));
+ (* SOFT_HLUTNM = "soft_lutpair29" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[4]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[4]),
+ .O(ctr[4]));
+ (* SOFT_HLUTNM = "soft_lutpair30" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[5]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[5]),
+ .O(ctr[5]));
+ (* SOFT_HLUTNM = "soft_lutpair31" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[6]_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[6]),
+ .O(ctr[6]));
+ (* SOFT_HLUTNM = "soft_lutpair32" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \ctr[7]_i_2
+ (.I0(s00_axi_aresetn),
+ .I1(s00_axi_wdata[7]),
+ .O(ctr[7]));
+ FDCE \ctr_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[0]),
+ .Q(\ctr_reg_n_0_[0] ));
+ FDCE \ctr_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[1]),
+ .Q(\ctr_reg_n_0_[1] ));
+ FDCE \ctr_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[2]),
+ .Q(\ctr_reg_n_0_[2] ));
+ FDCE \ctr_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[3]),
+ .Q(\ctr_reg_n_0_[3] ));
+ FDCE \ctr_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[4]),
+ .Q(\ctr_reg_n_0_[4] ));
+ FDCE \ctr_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[5]),
+ .Q(\ctr_reg_n_0_[5] ));
+ FDCE \ctr_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[6]),
+ .Q(ien));
+ FDCE \ctr_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg),
+ .CLR(wb_rst_o),
+ .D(ctr[7]),
+ .Q(Q));
+ FDRE iack_o_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(s_stb_r_reg_0),
+ .Q(wb_ack_i),
+ .R(1'b0));
+ (* SOFT_HLUTNM = "soft_lutpair28" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[10]_i_1
+ (.I0(s00_axi_wdata[2]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[10]_i_1_n_0 ));
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[11]_i_1
+ (.I0(s00_axi_wdata[3]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[11]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair29" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[12]_i_1
+ (.I0(s00_axi_wdata[4]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[12]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair30" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[13]_i_1
+ (.I0(s00_axi_wdata[5]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[13]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair31" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[14]_i_1
+ (.I0(s00_axi_wdata[6]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[14]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair32" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[15]_i_2
+ (.I0(s00_axi_wdata[7]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[15]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair26" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[8]_i_1
+ (.I0(s00_axi_wdata[0]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[8]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair27" *)
+ LUT2 #(
+ .INIT(4'hB))
+ \prer[9]_i_1
+ (.I0(s00_axi_wdata[1]),
+ .I1(s00_axi_aresetn),
+ .O(\prer[9]_i_1_n_0 ));
+ FDPE \prer_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[8]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(\prer_reg_n_0_[0] ));
+ FDPE \prer_reg[10]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[10]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[8]));
+ FDPE \prer_reg[11]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[11]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[9]));
+ FDPE \prer_reg[12]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[12]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[10]));
+ FDPE \prer_reg[13]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[13]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[11]));
+ FDPE \prer_reg[14]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[14]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[12]));
+ FDPE \prer_reg[15]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[15]_i_2_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[13]));
+ FDPE \prer_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[9]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(\prer_reg_n_0_[1] ));
+ FDPE \prer_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[10]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[0]));
+ FDPE \prer_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[11]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[1]));
+ FDPE \prer_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[12]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[2]));
+ FDPE \prer_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[13]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[3]));
+ FDPE \prer_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[14]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[4]));
+ FDPE \prer_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(E[0]),
+ .D(\prer[15]_i_2_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[5]));
+ FDPE \prer_reg[8]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[8]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[6]));
+ FDPE \prer_reg[9]
+ (.C(s00_axi_aclk),
+ .CE(E[1]),
+ .D(\prer[9]_i_1_n_0 ),
+ .PRE(wb_rst_o),
+ .Q(data0[7]));
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \s_rdata[7]_i_1
+ (.I0(wb_ack_i),
+ .I1(wb_we_o),
+ .O(\s_rdata_reg[0] ));
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
+ LUT4 #(
+ .INIT(16'hEFEE))
+ s_stb_r_i_1
+ (.I0(s00_axi_awvalid),
+ .I1(s00_axi_arvalid),
+ .I2(wb_ack_i),
+ .I3(wb_cyc_o),
+ .O(s_stb_r_reg));
+ FDCE \st_irq_block.al_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(al),
+ .Q(\st_irq_block.al_reg_n_0 ));
+ FDCE \st_irq_block.irq_flag_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(irq_flag1_out),
+ .Q(irq_flag));
+ FDCE \st_irq_block.rxack_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(rxack_0),
+ .Q(rxack));
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
+ LUT3 #(
+ .INIT(8'hA8))
+ \st_irq_block.tip_i_1
+ (.I0(s00_axi_aresetn),
+ .I1(write),
+ .I2(read),
+ .O(tip_1));
+ FDCE \st_irq_block.tip_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(tip_1),
+ .Q(tip));
+ (* SOFT_HLUTNM = "soft_lutpair25" *)
+ LUT3 #(
+ .INIT(8'h80))
+ \st_irq_block.wb_inta_o_i_1
+ (.I0(irq_flag),
+ .I1(s00_axi_aresetn),
+ .I2(ien),
+ .O(\st_irq_block.wb_inta_o_i_1_n_0 ));
+ FDCE \st_irq_block.wb_inta_o_reg
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .CLR(wb_rst_o),
+ .D(\st_irq_block.wb_inta_o_i_1_n_0 ),
+ .Q(axi_int_o));
+ FDCE \txr_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[0]),
+ .Q(txr[0]));
+ FDCE \txr_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[1]),
+ .Q(txr[1]));
+ FDCE \txr_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[2]),
+ .Q(txr[2]));
+ FDCE \txr_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[3]),
+ .Q(txr[3]));
+ FDCE \txr_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[4]),
+ .Q(txr[4]));
+ FDCE \txr_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[5]),
+ .Q(txr[5]));
+ FDCE \txr_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[6]),
+ .Q(txr[6]));
+ FDCE \txr_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(s_we_r_reg_0),
+ .CLR(wb_rst_o),
+ .D(ctr[7]),
+ .Q(txr[7]));
+ LUT5 #(
+ .INIT(32'h30BB3088))
+ \wb_dat_o[0]_i_3
+ (.I0(\cr_reg_n_0_[0] ),
+ .I1(wb_adr_o[1]),
+ .I2(txr[0]),
+ .I3(wb_adr_o[0]),
+ .I4(irq_flag),
+ .O(\wb_dat_o[0]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'h30BB3088))
+ \wb_dat_o[1]_i_3
+ (.I0(\cr_reg_n_0_[1] ),
+ .I1(wb_adr_o[1]),
+ .I2(txr[1]),
+ .I3(wb_adr_o[0]),
+ .I4(tip),
+ .O(\wb_dat_o[1]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'h30BB3088))
+ \wb_dat_o[5]_i_3
+ (.I0(read),
+ .I1(wb_adr_o[1]),
+ .I2(txr[5]),
+ .I3(wb_adr_o[0]),
+ .I4(\st_irq_block.al_reg_n_0 ),
+ .O(\wb_dat_o[5]_i_3_n_0 ));
+ LUT5 #(
+ .INIT(32'h30BB3088))
+ \wb_dat_o[7]_i_3
+ (.I0(start),
+ .I1(wb_adr_o[1]),
+ .I2(txr[7]),
+ .I3(wb_adr_o[0]),
+ .I4(rxack),
+ .O(\wb_dat_o[7]_i_3_n_0 ));
+ FDRE \wb_dat_o_reg[0]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[0]),
+ .Q(\s_rdata_reg[7] [0]),
+ .R(1'b0));
+ FDRE \wb_dat_o_reg[1]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[1]),
+ .Q(\s_rdata_reg[7] [1]),
+ .R(1'b0));
+ FDRE \wb_dat_o_reg[2]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[2]),
+ .Q(\s_rdata_reg[7] [2]),
+ .R(1'b0));
+ FDRE \wb_dat_o_reg[3]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[3]),
+ .Q(\s_rdata_reg[7] [3]),
+ .R(1'b0));
+ FDRE \wb_dat_o_reg[4]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[4]),
+ .Q(\s_rdata_reg[7] [4]),
+ .R(1'b0));
+ FDRE \wb_dat_o_reg[5]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[5]),
+ .Q(\s_rdata_reg[7] [5]),
+ .R(1'b0));
+ FDRE \wb_dat_o_reg[6]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[6]),
+ .Q(\s_rdata_reg[7] [6]),
+ .R(1'b0));
+ FDRE \wb_dat_o_reg[7]
+ (.C(s00_axi_aclk),
+ .CE(1'b1),
+ .D(wb_dat_o[7]),
+ .Q(\s_rdata_reg[7] [7]),
+ .R(1'b0));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl
new file mode 100644
index 00000000..0e7bf9db
--- /dev/null
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl
@@ -0,0 +1,4862 @@
+-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
+-- Date : Wed Oct 11 14:52:21 2017
+-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
+-- Command : write_vhdl -force -mode funcsim
+-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0_sim_netlist.vhdl
+-- Design : system_design_axi_wb_i2c_master_2_0
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7z030ffg676-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity system_design_axi_wb_i2c_master_2_0_axis_wbm_bridge is
+ port (
+ s00_axi_awready : out STD_LOGIC;
+ s00_axi_wready : out STD_LOGIC;
+ s00_axi_arready : out STD_LOGIC;
+ wb_we_o : out STD_LOGIC;
+ wb_cyc_o : out STD_LOGIC;
+ s00_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
+ s00_axi_bvalid : out STD_LOGIC;
+ \cr_reg[2]\ : out STD_LOGIC;
+ wb_adr_o : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ D : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \cr_reg[4]\ : out STD_LOGIC;
+ \prer_reg[8]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ \ctr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ s00_axi_rvalid : out STD_LOGIC;
+ iack_o_reg : out STD_LOGIC;
+ s00_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ wb_rst_o : in STD_LOGIC;
+ s00_axi_aclk : in STD_LOGIC;
+ iack_o_reg_0 : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 0 to 0 );
+ s00_axi_aresetn : in STD_LOGIC;
+ wb_ack_i : in STD_LOGIC;
+ s00_axi_awvalid : in STD_LOGIC;
+ s00_axi_arvalid : in STD_LOGIC;
+ s00_axi_bready : in STD_LOGIC;
+ s00_axi_rready : in STD_LOGIC;
+ s00_axi_wvalid : in STD_LOGIC;
+ s00_axi_wdata : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s00_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ iack_o_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \wb_dat_o_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_2_0_axis_wbm_bridge : entity is "axis_wbm_bridge";
+end system_design_axi_wb_i2c_master_2_0_axis_wbm_bridge;
+
+architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_axis_wbm_bridge is
+ signal \cr[2]_i_3_n_0\ : STD_LOGIC;
+ signal \^s00_axi_arready\ : STD_LOGIC;
+ signal \^s00_axi_awready\ : STD_LOGIC;
+ signal \^s00_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \^s00_axi_wready\ : STD_LOGIC;
+ signal \s_addr[2]_i_1_n_0\ : STD_LOGIC;
+ signal \s_addr[3]_i_1_n_0\ : STD_LOGIC;
+ signal \s_addr[4]_i_1_n_0\ : STD_LOGIC;
+ signal s_arready_i_1_n_0 : STD_LOGIC;
+ signal s_awready_i_1_n_0 : STD_LOGIC;
+ signal \s_bresp[1]_i_1_n_0\ : STD_LOGIC;
+ signal s_bvalid : STD_LOGIC;
+ signal s_bvalid_i_1_n_0 : STD_LOGIC;
+ signal s_rvalid : STD_LOGIC;
+ signal s_rvalid_i_1_n_0 : STD_LOGIC;
+ signal s_we_r_i_1_n_0 : STD_LOGIC;
+ signal s_wready_i_1_n_0 : STD_LOGIC;
+ signal \^wb_adr_o\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \^wb_cyc_o\ : STD_LOGIC;
+ signal \^wb_we_o\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \cr[2]_i_3\ : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of \cr[4]_i_1\ : label is "soft_lutpair4";
+ attribute SOFT_HLUTNM of \cr[5]_i_1\ : label is "soft_lutpair4";
+ attribute SOFT_HLUTNM of \cr[6]_i_1\ : label is "soft_lutpair6";
+ attribute SOFT_HLUTNM of \cr[7]_i_2\ : label is "soft_lutpair6";
+ attribute SOFT_HLUTNM of \ctr[7]_i_1\ : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of iack_o_i_1 : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \prer[15]_i_1\ : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of s00_axi_bvalid_INST_0 : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of s00_axi_rvalid_INST_0 : label is "soft_lutpair3";
+ attribute SOFT_HLUTNM of s_awready_i_1 : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \s_bresp[1]_i_1\ : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of s_rvalid_i_1 : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of s_we_r_i_1 : label is "soft_lutpair3";
+ attribute SOFT_HLUTNM of s_wready_i_1 : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \txr[7]_i_1\ : label is "soft_lutpair0";
+begin
+ s00_axi_arready <= \^s00_axi_arready\;
+ s00_axi_awready <= \^s00_axi_awready\;
+ s00_axi_bresp(0) <= \^s00_axi_bresp\(0);
+ s00_axi_wready <= \^s00_axi_wready\;
+ wb_adr_o(2 downto 0) <= \^wb_adr_o\(2 downto 0);
+ wb_cyc_o <= \^wb_cyc_o\;
+ wb_we_o <= \^wb_we_o\;
+\cr[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFF0008FFFFFFFF"
+ )
+ port map (
+ I0 => \^wb_adr_o\(2),
+ I1 => Q(0),
+ I2 => \^wb_adr_o\(1),
+ I3 => \^wb_adr_o\(0),
+ I4 => \cr[2]_i_3_n_0\,
+ I5 => s00_axi_aresetn,
+ O => \cr_reg[2]\
+ );
+\cr[2]_i_3\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"7"
+ )
+ port map (
+ I0 => \^wb_we_o\,
+ I1 => wb_ack_i,
+ O => \cr[2]_i_3_n_0\
+ );
+\cr[4]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(0),
+ I2 => \^wb_we_o\,
+ I3 => wb_ack_i,
+ O => D(0)
+ );
+\cr[5]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(1),
+ I2 => \^wb_we_o\,
+ I3 => wb_ack_i,
+ O => D(1)
+ );
+\cr[6]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(2),
+ I2 => \^wb_we_o\,
+ I3 => wb_ack_i,
+ O => D(2)
+ );
+\cr[7]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(3),
+ I2 => \^wb_we_o\,
+ I3 => wb_ack_i,
+ O => D(3)
+ );
+\cr[7]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFF7FFF"
+ )
+ port map (
+ I0 => wb_ack_i,
+ I1 => \^wb_we_o\,
+ I2 => \^wb_adr_o\(2),
+ I3 => Q(0),
+ I4 => \^wb_adr_o\(1),
+ I5 => \^wb_adr_o\(0),
+ O => \cr_reg[4]\
+ );
+\ctr[7]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0080FFFF"
+ )
+ port map (
+ I0 => \^wb_we_o\,
+ I1 => wb_ack_i,
+ I2 => \^wb_adr_o\(1),
+ I3 => \^wb_adr_o\(0),
+ I4 => s00_axi_aresetn,
+ O => \ctr_reg[0]\(0)
+ );
+iack_o_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^wb_cyc_o\,
+ I1 => wb_ack_i,
+ O => iack_o_reg
+ );
+\prer[15]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"75555555"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \^wb_adr_o\(1),
+ I2 => wb_ack_i,
+ I3 => \^wb_we_o\,
+ I4 => \^wb_adr_o\(0),
+ O => \prer_reg[8]\(1)
+ );
+\prer[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"5555555557555555"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \^wb_adr_o\(1),
+ I2 => \^wb_adr_o\(2),
+ I3 => wb_ack_i,
+ I4 => \^wb_we_o\,
+ I5 => \^wb_adr_o\(0),
+ O => \prer_reg[8]\(0)
+ );
+s00_axi_bvalid_INST_0: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s_bvalid,
+ I1 => \^wb_we_o\,
+ O => s00_axi_bvalid
+ );
+s00_axi_rvalid_INST_0: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => s_rvalid,
+ I1 => \^wb_we_o\,
+ O => s00_axi_rvalid
+ );
+\s_addr[2]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AACFAAC0"
+ )
+ port map (
+ I0 => s00_axi_araddr(0),
+ I1 => s00_axi_awaddr(0),
+ I2 => s00_axi_awvalid,
+ I3 => s00_axi_arvalid,
+ I4 => \^wb_adr_o\(0),
+ O => \s_addr[2]_i_1_n_0\
+ );
+\s_addr[3]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AACFAAC0"
+ )
+ port map (
+ I0 => s00_axi_araddr(1),
+ I1 => s00_axi_awaddr(1),
+ I2 => s00_axi_awvalid,
+ I3 => s00_axi_arvalid,
+ I4 => \^wb_adr_o\(1),
+ O => \s_addr[3]_i_1_n_0\
+ );
+\s_addr[4]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AACFAAC0"
+ )
+ port map (
+ I0 => s00_axi_araddr(2),
+ I1 => s00_axi_awaddr(2),
+ I2 => s00_axi_awvalid,
+ I3 => s00_axi_arvalid,
+ I4 => \^wb_adr_o\(2),
+ O => \s_addr[4]_i_1_n_0\
+ );
+\s_addr_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \s_addr[2]_i_1_n_0\,
+ Q => \^wb_adr_o\(0),
+ R => wb_rst_o
+ );
+\s_addr_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \s_addr[3]_i_1_n_0\,
+ Q => \^wb_adr_o\(1),
+ R => wb_rst_o
+ );
+\s_addr_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \s_addr[4]_i_1_n_0\,
+ Q => \^wb_adr_o\(2),
+ R => wb_rst_o
+ );
+s_arready_i_1: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => s00_axi_arvalid,
+ I1 => \^s00_axi_arready\,
+ O => s_arready_i_1_n_0
+ );
+s_arready_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => s_arready_i_1_n_0,
+ Q => \^s00_axi_arready\,
+ R => wb_rst_o
+ );
+s_awready_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => s00_axi_wvalid,
+ I1 => s00_axi_awvalid,
+ I2 => \^s00_axi_awready\,
+ O => s_awready_i_1_n_0
+ );
+s_awready_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => s_awready_i_1_n_0,
+ Q => \^s00_axi_awready\,
+ R => wb_rst_o
+ );
+\s_bresp[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FF7F0000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \^wb_we_o\,
+ I2 => wb_ack_i,
+ I3 => s_bvalid,
+ I4 => \^s00_axi_bresp\(0),
+ O => \s_bresp[1]_i_1_n_0\
+ );
+\s_bresp_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \s_bresp[1]_i_1_n_0\,
+ Q => \^s00_axi_bresp\(0),
+ R => '0'
+ );
+s_bvalid_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0F88"
+ )
+ port map (
+ I0 => \^wb_we_o\,
+ I1 => wb_ack_i,
+ I2 => s00_axi_bready,
+ I3 => s_bvalid,
+ O => s_bvalid_i_1_n_0
+ );
+s_bvalid_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => s_bvalid_i_1_n_0,
+ Q => s_bvalid,
+ R => wb_rst_o
+ );
+\s_rdata_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(0),
+ Q => s00_axi_rdata(0),
+ R => wb_rst_o
+ );
+\s_rdata_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(1),
+ Q => s00_axi_rdata(1),
+ R => wb_rst_o
+ );
+\s_rdata_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(2),
+ Q => s00_axi_rdata(2),
+ R => wb_rst_o
+ );
+\s_rdata_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(3),
+ Q => s00_axi_rdata(3),
+ R => wb_rst_o
+ );
+\s_rdata_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(4),
+ Q => s00_axi_rdata(4),
+ R => wb_rst_o
+ );
+\s_rdata_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(5),
+ Q => s00_axi_rdata(5),
+ R => wb_rst_o
+ );
+\s_rdata_reg[6]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(6),
+ Q => s00_axi_rdata(6),
+ R => wb_rst_o
+ );
+\s_rdata_reg[7]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s00_axi_aclk,
+ CE => iack_o_reg_1(0),
+ D => \wb_dat_o_reg[7]\(7),
+ Q => s00_axi_rdata(7),
+ R => wb_rst_o
+ );
+s_rvalid_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"4F44"
+ )
+ port map (
+ I0 => s00_axi_rready,
+ I1 => s_rvalid,
+ I2 => \^wb_we_o\,
+ I3 => wb_ack_i,
+ O => s_rvalid_i_1_n_0
+ );
+s_rvalid_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => s_rvalid_i_1_n_0,
+ Q => s_rvalid,
+ R => wb_rst_o
+ );
+s_stb_r_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => iack_o_reg_0,
+ Q => \^wb_cyc_o\,
+ R => wb_rst_o
+ );
+s_we_r_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"00E0"
+ )
+ port map (
+ I0 => \^wb_we_o\,
+ I1 => s00_axi_awvalid,
+ I2 => s00_axi_aresetn,
+ I3 => s00_axi_arvalid,
+ O => s_we_r_i_1_n_0
+ );
+s_we_r_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => s_we_r_i_1_n_0,
+ Q => \^wb_we_o\,
+ R => '0'
+ );
+s_wready_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => s00_axi_wvalid,
+ I1 => s00_axi_awvalid,
+ I2 => \^s00_axi_wready\,
+ O => s_wready_i_1_n_0
+ );
+s_wready_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => s_wready_i_1_n_0,
+ Q => \^s00_axi_wready\,
+ R => wb_rst_o
+ );
+\txr[7]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"8000FFFF"
+ )
+ port map (
+ I0 => \^wb_we_o\,
+ I1 => wb_ack_i,
+ I2 => \^wb_adr_o\(0),
+ I3 => \^wb_adr_o\(1),
+ I4 => s00_axi_aresetn,
+ O => E(0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl is
+ port (
+ iscl_oen_reg_0 : out STD_LOGIC;
+ i2c_scl_t : out STD_LOGIC;
+ i2c_sda_t : out STD_LOGIC;
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ irq_flag1_out : out STD_LOGIC;
+ al : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \statemachine.core_cmd_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ \statemachine.ld_reg\ : out STD_LOGIC;
+ \statemachine.core_txd_reg\ : out STD_LOGIC;
+ \statemachine.shift_reg\ : out STD_LOGIC;
+ \statemachine.host_ack_reg\ : out STD_LOGIC;
+ \statemachine.ack_out_reg\ : out STD_LOGIC;
+ \cr_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \sr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \FSM_sequential_statemachine.c_state_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_aclk : in STD_LOGIC;
+ s00_axi_aresetn : in STD_LOGIC;
+ \out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \cr_reg[0]\ : in STD_LOGIC;
+ cmd_ack : in STD_LOGIC;
+ irq_flag : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ \ctr_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ i2c_sda_i : in STD_LOGIC;
+ i2c_scl_i : in STD_LOGIC;
+ \statemachine.core_cmd_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \st_irq_block.al_reg\ : in STD_LOGIC;
+ \cr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \sr_reg[6]\ : in STD_LOGIC;
+ \txr_reg[6]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \FSM_sequential_statemachine.c_state_reg[1]\ : in STD_LOGIC;
+ core_cmd : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \FSM_sequential_statemachine.c_state_reg[1]_0\ : in STD_LOGIC;
+ cnt_done : in STD_LOGIC;
+ ack_out : in STD_LOGIC;
+ iack_o_reg : in STD_LOGIC;
+ wb_we_o : in STD_LOGIC;
+ iack_o_reg_0 : in STD_LOGIC;
+ \statemachine.ld_reg_0\ : in STD_LOGIC;
+ \FSM_sequential_statemachine.c_state_reg[1]_1\ : in STD_LOGIC;
+ \FSM_sequential_statemachine.c_state_reg[1]_2\ : in STD_LOGIC;
+ ack_in : in STD_LOGIC;
+ \sr_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \cr_reg[7]_0\ : in STD_LOGIC;
+ \statemachine.core_txd_reg_0\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl : entity is "i2c_master_bit_ctrl";
+end system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl;
+
+architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl is
+ signal \FSM_sequential_c_state[0]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[0]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[1]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[1]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[1]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[2]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[2]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[3]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[3]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[3]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[4]_i_1_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[4]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_c_state[4]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_statemachine.c_state[2]_i_3_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.cSCL[0]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.cSCL[1]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.cSDA[0]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.cSDA[1]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.cSDA_reg_n_0_[1]\ : STD_LOGIC;
+ signal \bus_status_ctrl.cmd_stop_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.cmd_stop_i_2_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.cmd_stop_reg_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.dSCL_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.dSDA_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.dout_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSCL[0]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSCL[1]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSCL[2]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSCL_reg_n_0_[2]\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSDA[0]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSDA[1]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSDA[2]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSDA[2]_i_2_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSDA_reg_n_0_[0]\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSDA_reg_n_0_[1]\ : STD_LOGIC;
+ signal \bus_status_ctrl.fSDA_reg_n_0_[2]\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[0]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[10]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[11]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[12]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[13]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[13]_i_2_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[13]_i_3_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[13]_i_4_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[1]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[2]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[3]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[4]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[5]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[6]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[7]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[8]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.filter_cnt[9]_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.ial_i_2_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.ial_i_3_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.sSCL_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.sSDA_i_1_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.sta_condition_reg_n_0\ : STD_LOGIC;
+ signal \bus_status_ctrl.sto_condition_reg_n_0\ : STD_LOGIC;
+ signal c_state : STD_LOGIC_VECTOR ( 4 downto 0 );
+ attribute RTL_KEEP : string;
+ attribute RTL_KEEP of c_state : signal is "yes";
+ signal clk_en : STD_LOGIC;
+ signal clk_en_i_2_n_0 : STD_LOGIC;
+ signal clk_en_i_3_n_0 : STD_LOGIC;
+ signal clk_en_i_4_n_0 : STD_LOGIC;
+ signal clk_en_i_5_n_0 : STD_LOGIC;
+ signal clk_en_i_6_n_0 : STD_LOGIC;
+ signal cmd_ack3_out : STD_LOGIC;
+ signal cmd_ack_i_2_n_0 : STD_LOGIC;
+ signal cnt1 : STD_LOGIC;
+ signal \cnt[0]_i_10_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_1_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_3_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_4_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_5_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_6_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_7_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_8_n_0\ : STD_LOGIC;
+ signal \cnt[0]_i_9_n_0\ : STD_LOGIC;
+ signal \cnt[12]_i_2_n_0\ : STD_LOGIC;
+ signal \cnt[12]_i_3_n_0\ : STD_LOGIC;
+ signal \cnt[12]_i_4_n_0\ : STD_LOGIC;
+ signal \cnt[12]_i_5_n_0\ : STD_LOGIC;
+ signal \cnt[12]_i_6_n_0\ : STD_LOGIC;
+ signal \cnt[12]_i_7_n_0\ : STD_LOGIC;
+ signal \cnt[12]_i_8_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_2_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_3_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_4_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_5_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_6_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_7_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_8_n_0\ : STD_LOGIC;
+ signal \cnt[4]_i_9_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_2_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_3_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_4_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_5_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_6_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_7_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_8_n_0\ : STD_LOGIC;
+ signal \cnt[8]_i_9_n_0\ : STD_LOGIC;
+ signal cnt_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
+ signal \cnt_reg[0]_i_2_n_0\ : STD_LOGIC;
+ signal \cnt_reg[0]_i_2_n_1\ : STD_LOGIC;
+ signal \cnt_reg[0]_i_2_n_2\ : STD_LOGIC;
+ signal \cnt_reg[0]_i_2_n_3\ : STD_LOGIC;
+ signal \cnt_reg[0]_i_2_n_4\ : STD_LOGIC;
+ signal \cnt_reg[0]_i_2_n_5\ : STD_LOGIC;
+ signal \cnt_reg[0]_i_2_n_6\ : STD_LOGIC;
+ signal \cnt_reg[0]_i_2_n_7\ : STD_LOGIC;
+ signal \cnt_reg[12]_i_1_n_1\ : STD_LOGIC;
+ signal \cnt_reg[12]_i_1_n_2\ : STD_LOGIC;
+ signal \cnt_reg[12]_i_1_n_3\ : STD_LOGIC;
+ signal \cnt_reg[12]_i_1_n_4\ : STD_LOGIC;
+ signal \cnt_reg[12]_i_1_n_5\ : STD_LOGIC;
+ signal \cnt_reg[12]_i_1_n_6\ : STD_LOGIC;
+ signal \cnt_reg[12]_i_1_n_7\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_0\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_1\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_2\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_3\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_4\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_5\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_6\ : STD_LOGIC;
+ signal \cnt_reg[4]_i_1_n_7\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_0\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_1\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_2\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_3\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_4\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_5\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_6\ : STD_LOGIC;
+ signal \cnt_reg[8]_i_1_n_7\ : STD_LOGIC;
+ signal core_ack : STD_LOGIC;
+ signal core_rxd : STD_LOGIC;
+ signal core_txd : STD_LOGIC;
+ signal dSCL : STD_LOGIC;
+ signal dSDA : STD_LOGIC;
+ signal dscl_oen : STD_LOGIC;
+ signal filter_cnt : STD_LOGIC_VECTOR ( 13 downto 0 );
+ signal i2c_al : STD_LOGIC;
+ signal i2c_busy : STD_LOGIC;
+ signal \^i2c_scl_t\ : STD_LOGIC;
+ signal \^i2c_sda_t\ : STD_LOGIC;
+ signal ial : STD_LOGIC;
+ signal ibusy : STD_LOGIC;
+ signal iscl_oen : STD_LOGIC;
+ signal \iscl_oen9_out__0\ : STD_LOGIC;
+ signal iscl_oen_i_1_n_0 : STD_LOGIC;
+ signal \^iscl_oen_reg_0\ : STD_LOGIC;
+ signal isda_oen : STD_LOGIC;
+ signal \isda_oen7_out__0\ : STD_LOGIC;
+ signal isda_oen_i_1_n_0 : STD_LOGIC;
+ signal \minusOp_carry__0_i_1_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__0_i_2_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__0_i_3_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__0_i_4_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_1\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_2\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_3\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_4\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_5\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_6\ : STD_LOGIC;
+ signal \minusOp_carry__0_n_7\ : STD_LOGIC;
+ signal \minusOp_carry__1_i_1_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__1_i_2_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__1_i_3_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__1_i_4_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_1\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_2\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_3\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_4\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_5\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_6\ : STD_LOGIC;
+ signal \minusOp_carry__1_n_7\ : STD_LOGIC;
+ signal \minusOp_carry__2_i_1_n_0\ : STD_LOGIC;
+ signal \minusOp_carry__2_n_7\ : STD_LOGIC;
+ signal minusOp_carry_i_1_n_0 : STD_LOGIC;
+ signal minusOp_carry_i_2_n_0 : STD_LOGIC;
+ signal minusOp_carry_i_3_n_0 : STD_LOGIC;
+ signal minusOp_carry_i_4_n_0 : STD_LOGIC;
+ signal minusOp_carry_n_0 : STD_LOGIC;
+ signal minusOp_carry_n_1 : STD_LOGIC;
+ signal minusOp_carry_n_2 : STD_LOGIC;
+ signal minusOp_carry_n_3 : STD_LOGIC;
+ signal minusOp_carry_n_4 : STD_LOGIC;
+ signal minusOp_carry_n_5 : STD_LOGIC;
+ signal minusOp_carry_n_6 : STD_LOGIC;
+ signal minusOp_carry_n_7 : STD_LOGIC;
+ signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal sSCL : STD_LOGIC;
+ signal sSDA : STD_LOGIC;
+ signal sda_chk_i_1_n_0 : STD_LOGIC;
+ signal sda_chk_reg_n_0 : STD_LOGIC;
+ signal slave_wait : STD_LOGIC;
+ signal slave_wait0 : STD_LOGIC;
+ signal sta_condition : STD_LOGIC;
+ signal \statemachine.ack_out_i_2_n_0\ : STD_LOGIC;
+ signal sto_condition : STD_LOGIC;
+ signal \wb_dat_o[6]_i_3_n_0\ : STD_LOGIC;
+ signal \NLW_cnt_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal \NLW_minusOp_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal \NLW_minusOp_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \FSM_sequential_c_state[4]_i_3\ : label is "soft_lutpair9";
+ attribute KEEP : string;
+ attribute KEEP of \FSM_sequential_c_state_reg[0]\ : label is "yes";
+ attribute KEEP of \FSM_sequential_c_state_reg[1]\ : label is "yes";
+ attribute KEEP of \FSM_sequential_c_state_reg[2]\ : label is "yes";
+ attribute KEEP of \FSM_sequential_c_state_reg[3]\ : label is "yes";
+ attribute KEEP of \FSM_sequential_c_state_reg[4]\ : label is "yes";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSCL[0]_i_1\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSCL[1]_i_1\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSDA[0]_i_1\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.cSDA[1]_i_1\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.dSCL_i_1\ : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.dSDA_i_1\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[0]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[1]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSCL[2]_i_1\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[0]_i_1\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[1]_i_1\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.fSDA[2]_i_2\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.ibusy_i_1\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.sSCL_i_1\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.sta_condition_i_1\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \bus_status_ctrl.sto_condition_i_1\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of clk_en_i_2 : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of \sr[0]_i_1\ : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of \st_irq_block.al_i_1\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \st_irq_block.irq_flag_i_1\ : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \statemachine.core_cmd[2]_i_1\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \statemachine.core_cmd[3]_i_1\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \statemachine.core_txd_i_1\ : label is "soft_lutpair14";
+begin
+ i2c_scl_t <= \^i2c_scl_t\;
+ i2c_sda_t <= \^i2c_sda_t\;
+ iscl_oen_reg_0 <= \^iscl_oen_reg_0\;
+\FSM_sequential_c_state[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"1111111111111110"
+ )
+ port map (
+ I0 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ I1 => c_state(0),
+ I2 => c_state(2),
+ I3 => c_state(3),
+ I4 => \FSM_sequential_c_state[0]_i_2_n_0\,
+ I5 => c_state(4),
+ O => \FSM_sequential_c_state[0]_i_1_n_0\
+ );
+\FSM_sequential_c_state[0]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AAAAAABA"
+ )
+ port map (
+ I0 => c_state(1),
+ I1 => \statemachine.core_cmd_reg[3]_0\(1),
+ I2 => \statemachine.core_cmd_reg[3]_0\(0),
+ I3 => \statemachine.core_cmd_reg[3]_0\(3),
+ I4 => \statemachine.core_cmd_reg[3]_0\(2),
+ O => \FSM_sequential_c_state[0]_i_2_n_0\
+ );
+\FSM_sequential_c_state[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0400"
+ )
+ port map (
+ I0 => i2c_al,
+ I1 => s00_axi_aresetn,
+ I2 => c_state(4),
+ I3 => \FSM_sequential_c_state[1]_i_2_n_0\,
+ O => \FSM_sequential_c_state[1]_i_1_n_0\
+ );
+\FSM_sequential_c_state[1]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"EEEFEFFE44444444"
+ )
+ port map (
+ I0 => c_state(0),
+ I1 => c_state(1),
+ I2 => \statemachine.core_cmd_reg[3]_0\(1),
+ I3 => \statemachine.core_cmd_reg[3]_0\(2),
+ I4 => \statemachine.core_cmd_reg[3]_0\(3),
+ I5 => \FSM_sequential_c_state[1]_i_3_n_0\,
+ O => \FSM_sequential_c_state[1]_i_2_n_0\
+ );
+\FSM_sequential_c_state[1]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00001101"
+ )
+ port map (
+ I0 => c_state(2),
+ I1 => c_state(1),
+ I2 => \statemachine.core_cmd_reg[3]_0\(0),
+ I3 => c_state(0),
+ I4 => c_state(3),
+ O => \FSM_sequential_c_state[1]_i_3_n_0\
+ );
+\FSM_sequential_c_state[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0002A0A2AAAA0002"
+ )
+ port map (
+ I0 => \FSM_sequential_c_state[3]_i_2_n_0\,
+ I1 => c_state(3),
+ I2 => c_state(1),
+ I3 => \FSM_sequential_c_state[2]_i_2_n_0\,
+ I4 => c_state(2),
+ I5 => c_state(0),
+ O => \FSM_sequential_c_state[2]_i_1_n_0\
+ );
+\FSM_sequential_c_state[2]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFFFEEF"
+ )
+ port map (
+ I0 => c_state(0),
+ I1 => \statemachine.core_cmd_reg[3]_0\(3),
+ I2 => \statemachine.core_cmd_reg[3]_0\(1),
+ I3 => \statemachine.core_cmd_reg[3]_0\(2),
+ I4 => \statemachine.core_cmd_reg[3]_0\(0),
+ O => \FSM_sequential_c_state[2]_i_2_n_0\
+ );
+\FSM_sequential_c_state[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0AA8A0A800A800A8"
+ )
+ port map (
+ I0 => \FSM_sequential_c_state[3]_i_2_n_0\,
+ I1 => \FSM_sequential_c_state[3]_i_3_n_0\,
+ I2 => c_state(3),
+ I3 => c_state(0),
+ I4 => c_state(2),
+ I5 => c_state(1),
+ O => \FSM_sequential_c_state[3]_i_1_n_0\
+ );
+\FSM_sequential_c_state[3]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"04"
+ )
+ port map (
+ I0 => c_state(4),
+ I1 => s00_axi_aresetn,
+ I2 => i2c_al,
+ O => \FSM_sequential_c_state[3]_i_2_n_0\
+ );
+\FSM_sequential_c_state[3]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000006"
+ )
+ port map (
+ I0 => \statemachine.core_cmd_reg[3]_0\(3),
+ I1 => \statemachine.core_cmd_reg[3]_0\(2),
+ I2 => \statemachine.core_cmd_reg[3]_0\(0),
+ I3 => \statemachine.core_cmd_reg[3]_0\(1),
+ I4 => c_state(1),
+ I5 => c_state(2),
+ O => \FSM_sequential_c_state[3]_i_3_n_0\
+ );
+\FSM_sequential_c_state[4]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"BBBBBBBFAAAAAAAA"
+ )
+ port map (
+ I0 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ I1 => c_state(4),
+ I2 => c_state(3),
+ I3 => c_state(1),
+ I4 => c_state(2),
+ I5 => clk_en,
+ O => \FSM_sequential_c_state[4]_i_1_n_0\
+ );
+\FSM_sequential_c_state[4]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000080FF8000"
+ )
+ port map (
+ I0 => c_state(3),
+ I1 => c_state(1),
+ I2 => c_state(2),
+ I3 => c_state(0),
+ I4 => c_state(4),
+ I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ O => \FSM_sequential_c_state[4]_i_2_n_0\
+ );
+\FSM_sequential_c_state[4]_i_3\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => i2c_al,
+ I1 => s00_axi_aresetn,
+ O => \FSM_sequential_c_state[4]_i_3_n_0\
+ );
+\FSM_sequential_c_state_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \FSM_sequential_c_state[4]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \FSM_sequential_c_state[0]_i_1_n_0\,
+ Q => c_state(0)
+ );
+\FSM_sequential_c_state_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \FSM_sequential_c_state[4]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \FSM_sequential_c_state[1]_i_1_n_0\,
+ Q => c_state(1)
+ );
+\FSM_sequential_c_state_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \FSM_sequential_c_state[4]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \FSM_sequential_c_state[2]_i_1_n_0\,
+ Q => c_state(2)
+ );
+\FSM_sequential_c_state_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \FSM_sequential_c_state[4]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \FSM_sequential_c_state[3]_i_1_n_0\,
+ Q => c_state(3)
+ );
+\FSM_sequential_c_state_reg[4]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \FSM_sequential_c_state[4]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \FSM_sequential_c_state[4]_i_2_n_0\,
+ Q => c_state(4)
+ );
+\FSM_sequential_statemachine.c_state[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000022222E22"
+ )
+ port map (
+ I0 => \FSM_sequential_statemachine.c_state_reg[1]_1\,
+ I1 => \out\(2),
+ I2 => \out\(1),
+ I3 => \cr_reg[7]\(2),
+ I4 => \out\(0),
+ I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ O => \FSM_sequential_statemachine.c_state_reg[2]\(0)
+ );
+\FSM_sequential_statemachine.c_state[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000015100000"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => cnt_done,
+ I2 => \out\(1),
+ I3 => \cr_reg[7]_0\,
+ I4 => s00_axi_aresetn,
+ I5 => i2c_al,
+ O => \FSM_sequential_statemachine.c_state_reg[2]\(1)
+ );
+\FSM_sequential_statemachine.c_state[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"DDFFDDDDFFFDDDFD"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => i2c_al,
+ I2 => \FSM_sequential_statemachine.c_state[2]_i_3_n_0\,
+ I3 => \out\(1),
+ I4 => core_ack,
+ I5 => \out\(2),
+ O => E(0)
+ );
+\FSM_sequential_statemachine.c_state[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000022222E22"
+ )
+ port map (
+ I0 => \FSM_sequential_statemachine.c_state_reg[1]_2\,
+ I1 => \out\(2),
+ I2 => \out\(1),
+ I3 => \cr_reg[7]\(2),
+ I4 => \out\(0),
+ I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ O => \FSM_sequential_statemachine.c_state_reg[2]\(2)
+ );
+\FSM_sequential_statemachine.c_state[2]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8B8B8B8B8B8B8B88"
+ )
+ port map (
+ I0 => core_ack,
+ I1 => \out\(0),
+ I2 => cmd_ack,
+ I3 => \cr_reg[7]\(0),
+ I4 => \cr_reg[7]\(1),
+ I5 => \cr_reg[7]\(2),
+ O => \FSM_sequential_statemachine.c_state[2]_i_3_n_0\
+ );
+\bus_status_ctrl.cSCL[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => i2c_scl_i,
+ O => \bus_status_ctrl.cSCL[0]_i_1_n_0\
+ );
+\bus_status_ctrl.cSCL[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \p_0_in__0\(1),
+ O => \bus_status_ctrl.cSCL[1]_i_1_n_0\
+ );
+\bus_status_ctrl.cSCL_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.cSCL[0]_i_1_n_0\,
+ Q => \p_0_in__0\(1)
+ );
+\bus_status_ctrl.cSCL_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.cSCL[1]_i_1_n_0\,
+ Q => \p_0_in__1\(0)
+ );
+\bus_status_ctrl.cSDA[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => i2c_sda_i,
+ O => \bus_status_ctrl.cSDA[0]_i_1_n_0\
+ );
+\bus_status_ctrl.cSDA[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => p_0_in(1),
+ O => \bus_status_ctrl.cSDA[1]_i_1_n_0\
+ );
+\bus_status_ctrl.cSDA_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.cSDA[0]_i_1_n_0\,
+ Q => p_0_in(1)
+ );
+\bus_status_ctrl.cSDA_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.cSDA[1]_i_1_n_0\,
+ Q => \bus_status_ctrl.cSDA_reg_n_0_[1]\
+ );
+\bus_status_ctrl.cmd_stop_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"04FF000004000000"
+ )
+ port map (
+ I0 => \statemachine.core_cmd_reg[3]_0\(0),
+ I1 => \statemachine.core_cmd_reg[3]_0\(1),
+ I2 => \bus_status_ctrl.cmd_stop_i_2_n_0\,
+ I3 => clk_en,
+ I4 => s00_axi_aresetn,
+ I5 => \bus_status_ctrl.cmd_stop_reg_n_0\,
+ O => \bus_status_ctrl.cmd_stop_i_1_n_0\
+ );
+\bus_status_ctrl.cmd_stop_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"E"
+ )
+ port map (
+ I0 => \statemachine.core_cmd_reg[3]_0\(2),
+ I1 => \statemachine.core_cmd_reg[3]_0\(3),
+ O => \bus_status_ctrl.cmd_stop_i_2_n_0\
+ );
+\bus_status_ctrl.cmd_stop_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.cmd_stop_i_1_n_0\,
+ Q => \bus_status_ctrl.cmd_stop_reg_n_0\
+ );
+\bus_status_ctrl.dSCL_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => sSCL,
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.dSCL_i_1_n_0\
+ );
+\bus_status_ctrl.dSCL_reg\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \bus_status_ctrl.dSCL_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => dSCL
+ );
+\bus_status_ctrl.dSDA_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => sSDA,
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.dSDA_i_1_n_0\
+ );
+\bus_status_ctrl.dSDA_reg\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \bus_status_ctrl.dSDA_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => dSDA
+ );
+\bus_status_ctrl.dout_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FB08"
+ )
+ port map (
+ I0 => sSDA,
+ I1 => sSCL,
+ I2 => dSCL,
+ I3 => core_rxd,
+ O => \bus_status_ctrl.dout_i_1_n_0\
+ );
+\bus_status_ctrl.dout_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.dout_i_1_n_0\,
+ Q => core_rxd
+ );
+\bus_status_ctrl.fSCL[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \p_0_in__1\(0),
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.fSCL[0]_i_1_n_0\
+ );
+\bus_status_ctrl.fSCL[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \p_0_in__1\(1),
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.fSCL[1]_i_1_n_0\
+ );
+\bus_status_ctrl.fSCL[2]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \p_0_in__1\(2),
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.fSCL[2]_i_1_n_0\
+ );
+\bus_status_ctrl.fSCL_reg[0]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
+ D => \bus_status_ctrl.fSCL[0]_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \p_0_in__1\(1)
+ );
+\bus_status_ctrl.fSCL_reg[1]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
+ D => \bus_status_ctrl.fSCL[1]_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \p_0_in__1\(2)
+ );
+\bus_status_ctrl.fSCL_reg[2]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
+ D => \bus_status_ctrl.fSCL[2]_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \bus_status_ctrl.fSCL_reg_n_0_[2]\
+ );
+\bus_status_ctrl.fSDA[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \bus_status_ctrl.cSDA_reg_n_0_[1]\,
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.fSDA[0]_i_1_n_0\
+ );
+\bus_status_ctrl.fSDA[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \bus_status_ctrl.fSDA_reg_n_0_[0]\,
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.fSDA[1]_i_1_n_0\
+ );
+\bus_status_ctrl.fSDA[2]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.fSDA[2]_i_1_n_0\
+ );
+\bus_status_ctrl.fSDA[2]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => \bus_status_ctrl.fSDA_reg_n_0_[1]\,
+ I1 => s00_axi_aresetn,
+ O => \bus_status_ctrl.fSDA[2]_i_2_n_0\
+ );
+\bus_status_ctrl.fSDA_reg[0]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
+ D => \bus_status_ctrl.fSDA[0]_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \bus_status_ctrl.fSDA_reg_n_0_[0]\
+ );
+\bus_status_ctrl.fSDA_reg[1]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
+ D => \bus_status_ctrl.fSDA[1]_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \bus_status_ctrl.fSDA_reg_n_0_[1]\
+ );
+\bus_status_ctrl.fSDA_reg[2]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => \bus_status_ctrl.fSDA[2]_i_1_n_0\,
+ D => \bus_status_ctrl.fSDA[2]_i_2_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \bus_status_ctrl.fSDA_reg_n_0_[2]\
+ );
+\bus_status_ctrl.filter_cnt[0]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"D1000000"
+ )
+ port map (
+ I0 => filter_cnt(0),
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(2),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[0]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[10]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__1_n_6\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(12),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[10]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[11]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__1_n_5\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(13),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[11]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[12]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__1_n_4\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(14),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[12]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[13]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__2_n_7\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(15),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[13]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[13]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000001"
+ )
+ port map (
+ I0 => \bus_status_ctrl.filter_cnt[13]_i_3_n_0\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_4_n_0\,
+ I2 => filter_cnt(6),
+ I3 => filter_cnt(7),
+ I4 => filter_cnt(4),
+ I5 => filter_cnt(5),
+ O => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\
+ );
+\bus_status_ctrl.filter_cnt[13]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFFFFFFE"
+ )
+ port map (
+ I0 => filter_cnt(13),
+ I1 => filter_cnt(12),
+ I2 => filter_cnt(9),
+ I3 => filter_cnt(8),
+ I4 => filter_cnt(11),
+ I5 => filter_cnt(10),
+ O => \bus_status_ctrl.filter_cnt[13]_i_3_n_0\
+ );
+\bus_status_ctrl.filter_cnt[13]_i_4\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => filter_cnt(2),
+ I1 => filter_cnt(3),
+ I2 => filter_cnt(0),
+ I3 => filter_cnt(1),
+ O => \bus_status_ctrl.filter_cnt[13]_i_4_n_0\
+ );
+\bus_status_ctrl.filter_cnt[1]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => minusOp_carry_n_7,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(3),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[1]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[2]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => minusOp_carry_n_6,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(4),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[2]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[3]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => minusOp_carry_n_5,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(5),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[3]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[4]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => minusOp_carry_n_4,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(6),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[4]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[5]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__0_n_7\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(7),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[5]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[6]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__0_n_6\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(8),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[6]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[7]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__0_n_5\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(9),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[7]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[8]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__0_n_4\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(10),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[8]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt[9]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"E2000000"
+ )
+ port map (
+ I0 => \minusOp_carry__1_n_7\,
+ I1 => \bus_status_ctrl.filter_cnt[13]_i_2_n_0\,
+ I2 => Q(11),
+ I3 => \ctr_reg[7]\(0),
+ I4 => s00_axi_aresetn,
+ O => \bus_status_ctrl.filter_cnt[9]_i_1_n_0\
+ );
+\bus_status_ctrl.filter_cnt_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[0]_i_1_n_0\,
+ Q => filter_cnt(0)
+ );
+\bus_status_ctrl.filter_cnt_reg[10]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[10]_i_1_n_0\,
+ Q => filter_cnt(10)
+ );
+\bus_status_ctrl.filter_cnt_reg[11]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[11]_i_1_n_0\,
+ Q => filter_cnt(11)
+ );
+\bus_status_ctrl.filter_cnt_reg[12]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[12]_i_1_n_0\,
+ Q => filter_cnt(12)
+ );
+\bus_status_ctrl.filter_cnt_reg[13]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[13]_i_1_n_0\,
+ Q => filter_cnt(13)
+ );
+\bus_status_ctrl.filter_cnt_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[1]_i_1_n_0\,
+ Q => filter_cnt(1)
+ );
+\bus_status_ctrl.filter_cnt_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[2]_i_1_n_0\,
+ Q => filter_cnt(2)
+ );
+\bus_status_ctrl.filter_cnt_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[3]_i_1_n_0\,
+ Q => filter_cnt(3)
+ );
+\bus_status_ctrl.filter_cnt_reg[4]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[4]_i_1_n_0\,
+ Q => filter_cnt(4)
+ );
+\bus_status_ctrl.filter_cnt_reg[5]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[5]_i_1_n_0\,
+ Q => filter_cnt(5)
+ );
+\bus_status_ctrl.filter_cnt_reg[6]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[6]_i_1_n_0\,
+ Q => filter_cnt(6)
+ );
+\bus_status_ctrl.filter_cnt_reg[7]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[7]_i_1_n_0\,
+ Q => filter_cnt(7)
+ );
+\bus_status_ctrl.filter_cnt_reg[8]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[8]_i_1_n_0\,
+ Q => filter_cnt(8)
+ );
+\bus_status_ctrl.filter_cnt_reg[9]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \bus_status_ctrl.filter_cnt[9]_i_1_n_0\,
+ Q => filter_cnt(9)
+ );
+\bus_status_ctrl.ial_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"08000800AAAA0800"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => sda_chk_reg_n_0,
+ I2 => sSDA,
+ I3 => \^i2c_sda_t\,
+ I4 => \bus_status_ctrl.ial_i_2_n_0\,
+ I5 => \bus_status_ctrl.ial_i_3_n_0\,
+ O => ial
+ );
+\bus_status_ctrl.ial_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => c_state(0),
+ I1 => c_state(4),
+ O => \bus_status_ctrl.ial_i_2_n_0\
+ );
+\bus_status_ctrl.ial_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FFFFFFEF"
+ )
+ port map (
+ I0 => c_state(2),
+ I1 => c_state(3),
+ I2 => \bus_status_ctrl.sto_condition_reg_n_0\,
+ I3 => \bus_status_ctrl.cmd_stop_reg_n_0\,
+ I4 => c_state(1),
+ O => \bus_status_ctrl.ial_i_3_n_0\
+ );
+\bus_status_ctrl.ial_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => ial,
+ Q => i2c_al
+ );
+\bus_status_ctrl.ibusy_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"5400"
+ )
+ port map (
+ I0 => \bus_status_ctrl.sto_condition_reg_n_0\,
+ I1 => \bus_status_ctrl.sta_condition_reg_n_0\,
+ I2 => i2c_busy,
+ I3 => s00_axi_aresetn,
+ O => ibusy
+ );
+\bus_status_ctrl.ibusy_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => ibusy,
+ Q => i2c_busy
+ );
+\bus_status_ctrl.sSCL_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E8FF"
+ )
+ port map (
+ I0 => \p_0_in__1\(2),
+ I1 => \bus_status_ctrl.fSCL_reg_n_0_[2]\,
+ I2 => \p_0_in__1\(1),
+ I3 => s00_axi_aresetn,
+ O => \bus_status_ctrl.sSCL_i_1_n_0\
+ );
+\bus_status_ctrl.sSCL_reg\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \bus_status_ctrl.sSCL_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => sSCL
+ );
+\bus_status_ctrl.sSDA_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E8FF"
+ )
+ port map (
+ I0 => \bus_status_ctrl.fSDA_reg_n_0_[1]\,
+ I1 => \bus_status_ctrl.fSDA_reg_n_0_[2]\,
+ I2 => \bus_status_ctrl.fSDA_reg_n_0_[0]\,
+ I3 => s00_axi_aresetn,
+ O => \bus_status_ctrl.sSDA_i_1_n_0\
+ );
+\bus_status_ctrl.sSDA_reg\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => \bus_status_ctrl.sSDA_i_1_n_0\,
+ PRE => \^iscl_oen_reg_0\,
+ Q => sSDA
+ );
+\bus_status_ctrl.sta_condition_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"2000"
+ )
+ port map (
+ I0 => dSDA,
+ I1 => sSDA,
+ I2 => s00_axi_aresetn,
+ I3 => sSCL,
+ O => sta_condition
+ );
+\bus_status_ctrl.sta_condition_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => sta_condition,
+ Q => \bus_status_ctrl.sta_condition_reg_n_0\
+ );
+\bus_status_ctrl.sto_condition_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"4000"
+ )
+ port map (
+ I0 => dSDA,
+ I1 => s00_axi_aresetn,
+ I2 => sSCL,
+ I3 => sSDA,
+ O => sto_condition
+ );
+\bus_status_ctrl.sto_condition_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => sto_condition,
+ Q => \bus_status_ctrl.sto_condition_reg_n_0\
+ );
+clk_en_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AAAAAAAB"
+ )
+ port map (
+ I0 => clk_en_i_2_n_0,
+ I1 => clk_en_i_3_n_0,
+ I2 => clk_en_i_4_n_0,
+ I3 => clk_en_i_5_n_0,
+ I4 => clk_en_i_6_n_0,
+ O => cnt1
+ );
+clk_en_i_2: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"7555FFFF"
+ )
+ port map (
+ I0 => \ctr_reg[7]\(0),
+ I1 => sSCL,
+ I2 => \^i2c_scl_t\,
+ I3 => dSCL,
+ I4 => s00_axi_aresetn,
+ O => clk_en_i_2_n_0
+ );
+clk_en_i_3: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => cnt_reg(6),
+ I1 => cnt_reg(7),
+ I2 => cnt_reg(4),
+ I3 => cnt_reg(5),
+ O => clk_en_i_3_n_0
+ );
+clk_en_i_4: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => cnt_reg(2),
+ I1 => cnt_reg(3),
+ I2 => cnt_reg(0),
+ I3 => cnt_reg(1),
+ O => clk_en_i_4_n_0
+ );
+clk_en_i_5: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => cnt_reg(15),
+ I1 => cnt_reg(14),
+ I2 => cnt_reg(12),
+ I3 => cnt_reg(13),
+ O => clk_en_i_5_n_0
+ );
+clk_en_i_6: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => cnt_reg(10),
+ I1 => cnt_reg(11),
+ I2 => cnt_reg(8),
+ I3 => cnt_reg(9),
+ O => clk_en_i_6_n_0
+ );
+clk_en_reg: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => cnt1,
+ PRE => \^iscl_oen_reg_0\,
+ Q => clk_en
+ );
+cmd_ack_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0008000000000000"
+ )
+ port map (
+ I0 => cmd_ack_i_2_n_0,
+ I1 => c_state(0),
+ I2 => c_state(1),
+ I3 => i2c_al,
+ I4 => s00_axi_aresetn,
+ I5 => clk_en,
+ O => cmd_ack3_out
+ );
+cmd_ack_i_2: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"1E"
+ )
+ port map (
+ I0 => c_state(2),
+ I1 => c_state(3),
+ I2 => c_state(4),
+ O => cmd_ack_i_2_n_0
+ );
+cmd_ack_reg: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => cmd_ack3_out,
+ Q => core_ack
+ );
+\cnt[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => cnt1,
+ I1 => slave_wait,
+ O => \cnt[0]_i_1_n_0\
+ );
+\cnt[0]_i_10\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(0),
+ I1 => Q(0),
+ I2 => cnt1,
+ O => \cnt[0]_i_10_n_0\
+ );
+\cnt[0]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(3),
+ I1 => cnt1,
+ I2 => cnt_reg(3),
+ O => \cnt[0]_i_3_n_0\
+ );
+\cnt[0]_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => cnt1,
+ I2 => cnt_reg(2),
+ O => \cnt[0]_i_4_n_0\
+ );
+\cnt[0]_i_5\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => cnt1,
+ I2 => cnt_reg(1),
+ O => \cnt[0]_i_5_n_0\
+ );
+\cnt[0]_i_6\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => cnt1,
+ I2 => cnt_reg(0),
+ O => \cnt[0]_i_6_n_0\
+ );
+\cnt[0]_i_7\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(3),
+ I1 => Q(3),
+ I2 => cnt1,
+ O => \cnt[0]_i_7_n_0\
+ );
+\cnt[0]_i_8\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(2),
+ I1 => Q(2),
+ I2 => cnt1,
+ O => \cnt[0]_i_8_n_0\
+ );
+\cnt[0]_i_9\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(1),
+ I1 => Q(1),
+ I2 => cnt1,
+ O => \cnt[0]_i_9_n_0\
+ );
+\cnt[12]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(14),
+ I1 => cnt1,
+ I2 => cnt_reg(14),
+ O => \cnt[12]_i_2_n_0\
+ );
+\cnt[12]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(13),
+ I1 => cnt1,
+ I2 => cnt_reg(13),
+ O => \cnt[12]_i_3_n_0\
+ );
+\cnt[12]_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(12),
+ I1 => cnt1,
+ I2 => cnt_reg(12),
+ O => \cnt[12]_i_4_n_0\
+ );
+\cnt[12]_i_5\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(15),
+ I1 => Q(15),
+ I2 => cnt1,
+ O => \cnt[12]_i_5_n_0\
+ );
+\cnt[12]_i_6\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(14),
+ I1 => Q(14),
+ I2 => cnt1,
+ O => \cnt[12]_i_6_n_0\
+ );
+\cnt[12]_i_7\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(13),
+ I1 => Q(13),
+ I2 => cnt1,
+ O => \cnt[12]_i_7_n_0\
+ );
+\cnt[12]_i_8\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(12),
+ I1 => Q(12),
+ I2 => cnt1,
+ O => \cnt[12]_i_8_n_0\
+ );
+\cnt[4]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(7),
+ I1 => cnt1,
+ I2 => cnt_reg(7),
+ O => \cnt[4]_i_2_n_0\
+ );
+\cnt[4]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(6),
+ I1 => cnt1,
+ I2 => cnt_reg(6),
+ O => \cnt[4]_i_3_n_0\
+ );
+\cnt[4]_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(5),
+ I1 => cnt1,
+ I2 => cnt_reg(5),
+ O => \cnt[4]_i_4_n_0\
+ );
+\cnt[4]_i_5\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(4),
+ I1 => cnt1,
+ I2 => cnt_reg(4),
+ O => \cnt[4]_i_5_n_0\
+ );
+\cnt[4]_i_6\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(7),
+ I1 => Q(7),
+ I2 => cnt1,
+ O => \cnt[4]_i_6_n_0\
+ );
+\cnt[4]_i_7\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(6),
+ I1 => Q(6),
+ I2 => cnt1,
+ O => \cnt[4]_i_7_n_0\
+ );
+\cnt[4]_i_8\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(5),
+ I1 => Q(5),
+ I2 => cnt1,
+ O => \cnt[4]_i_8_n_0\
+ );
+\cnt[4]_i_9\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(4),
+ I1 => Q(4),
+ I2 => cnt1,
+ O => \cnt[4]_i_9_n_0\
+ );
+\cnt[8]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(11),
+ I1 => cnt1,
+ I2 => cnt_reg(11),
+ O => \cnt[8]_i_2_n_0\
+ );
+\cnt[8]_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(10),
+ I1 => cnt1,
+ I2 => cnt_reg(10),
+ O => \cnt[8]_i_3_n_0\
+ );
+\cnt[8]_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(9),
+ I1 => cnt1,
+ I2 => cnt_reg(9),
+ O => \cnt[8]_i_4_n_0\
+ );
+\cnt[8]_i_5\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"B8"
+ )
+ port map (
+ I0 => Q(8),
+ I1 => cnt1,
+ I2 => cnt_reg(8),
+ O => \cnt[8]_i_5_n_0\
+ );
+\cnt[8]_i_6\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(11),
+ I1 => Q(11),
+ I2 => cnt1,
+ O => \cnt[8]_i_6_n_0\
+ );
+\cnt[8]_i_7\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(10),
+ I1 => Q(10),
+ I2 => cnt1,
+ O => \cnt[8]_i_7_n_0\
+ );
+\cnt[8]_i_8\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(9),
+ I1 => Q(9),
+ I2 => cnt1,
+ O => \cnt[8]_i_8_n_0\
+ );
+\cnt[8]_i_9\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C5"
+ )
+ port map (
+ I0 => cnt_reg(8),
+ I1 => Q(8),
+ I2 => cnt1,
+ O => \cnt[8]_i_9_n_0\
+ );
+\cnt_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[0]_i_2_n_7\,
+ Q => cnt_reg(0)
+ );
+\cnt_reg[0]_i_2\: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => \cnt_reg[0]_i_2_n_0\,
+ CO(2) => \cnt_reg[0]_i_2_n_1\,
+ CO(1) => \cnt_reg[0]_i_2_n_2\,
+ CO(0) => \cnt_reg[0]_i_2_n_3\,
+ CYINIT => '0',
+ DI(3) => \cnt[0]_i_3_n_0\,
+ DI(2) => \cnt[0]_i_4_n_0\,
+ DI(1) => \cnt[0]_i_5_n_0\,
+ DI(0) => \cnt[0]_i_6_n_0\,
+ O(3) => \cnt_reg[0]_i_2_n_4\,
+ O(2) => \cnt_reg[0]_i_2_n_5\,
+ O(1) => \cnt_reg[0]_i_2_n_6\,
+ O(0) => \cnt_reg[0]_i_2_n_7\,
+ S(3) => \cnt[0]_i_7_n_0\,
+ S(2) => \cnt[0]_i_8_n_0\,
+ S(1) => \cnt[0]_i_9_n_0\,
+ S(0) => \cnt[0]_i_10_n_0\
+ );
+\cnt_reg[10]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[8]_i_1_n_5\,
+ Q => cnt_reg(10)
+ );
+\cnt_reg[11]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[8]_i_1_n_4\,
+ Q => cnt_reg(11)
+ );
+\cnt_reg[12]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[12]_i_1_n_7\,
+ Q => cnt_reg(12)
+ );
+\cnt_reg[12]_i_1\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \cnt_reg[8]_i_1_n_0\,
+ CO(3) => \NLW_cnt_reg[12]_i_1_CO_UNCONNECTED\(3),
+ CO(2) => \cnt_reg[12]_i_1_n_1\,
+ CO(1) => \cnt_reg[12]_i_1_n_2\,
+ CO(0) => \cnt_reg[12]_i_1_n_3\,
+ CYINIT => '0',
+ DI(3) => '0',
+ DI(2) => \cnt[12]_i_2_n_0\,
+ DI(1) => \cnt[12]_i_3_n_0\,
+ DI(0) => \cnt[12]_i_4_n_0\,
+ O(3) => \cnt_reg[12]_i_1_n_4\,
+ O(2) => \cnt_reg[12]_i_1_n_5\,
+ O(1) => \cnt_reg[12]_i_1_n_6\,
+ O(0) => \cnt_reg[12]_i_1_n_7\,
+ S(3) => \cnt[12]_i_5_n_0\,
+ S(2) => \cnt[12]_i_6_n_0\,
+ S(1) => \cnt[12]_i_7_n_0\,
+ S(0) => \cnt[12]_i_8_n_0\
+ );
+\cnt_reg[13]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[12]_i_1_n_6\,
+ Q => cnt_reg(13)
+ );
+\cnt_reg[14]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[12]_i_1_n_5\,
+ Q => cnt_reg(14)
+ );
+\cnt_reg[15]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[12]_i_1_n_4\,
+ Q => cnt_reg(15)
+ );
+\cnt_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[0]_i_2_n_6\,
+ Q => cnt_reg(1)
+ );
+\cnt_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[0]_i_2_n_5\,
+ Q => cnt_reg(2)
+ );
+\cnt_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[0]_i_2_n_4\,
+ Q => cnt_reg(3)
+ );
+\cnt_reg[4]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[4]_i_1_n_7\,
+ Q => cnt_reg(4)
+ );
+\cnt_reg[4]_i_1\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \cnt_reg[0]_i_2_n_0\,
+ CO(3) => \cnt_reg[4]_i_1_n_0\,
+ CO(2) => \cnt_reg[4]_i_1_n_1\,
+ CO(1) => \cnt_reg[4]_i_1_n_2\,
+ CO(0) => \cnt_reg[4]_i_1_n_3\,
+ CYINIT => '0',
+ DI(3) => \cnt[4]_i_2_n_0\,
+ DI(2) => \cnt[4]_i_3_n_0\,
+ DI(1) => \cnt[4]_i_4_n_0\,
+ DI(0) => \cnt[4]_i_5_n_0\,
+ O(3) => \cnt_reg[4]_i_1_n_4\,
+ O(2) => \cnt_reg[4]_i_1_n_5\,
+ O(1) => \cnt_reg[4]_i_1_n_6\,
+ O(0) => \cnt_reg[4]_i_1_n_7\,
+ S(3) => \cnt[4]_i_6_n_0\,
+ S(2) => \cnt[4]_i_7_n_0\,
+ S(1) => \cnt[4]_i_8_n_0\,
+ S(0) => \cnt[4]_i_9_n_0\
+ );
+\cnt_reg[5]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[4]_i_1_n_6\,
+ Q => cnt_reg(5)
+ );
+\cnt_reg[6]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[4]_i_1_n_5\,
+ Q => cnt_reg(6)
+ );
+\cnt_reg[7]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[4]_i_1_n_4\,
+ Q => cnt_reg(7)
+ );
+\cnt_reg[8]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[8]_i_1_n_7\,
+ Q => cnt_reg(8)
+ );
+\cnt_reg[8]_i_1\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \cnt_reg[4]_i_1_n_0\,
+ CO(3) => \cnt_reg[8]_i_1_n_0\,
+ CO(2) => \cnt_reg[8]_i_1_n_1\,
+ CO(1) => \cnt_reg[8]_i_1_n_2\,
+ CO(0) => \cnt_reg[8]_i_1_n_3\,
+ CYINIT => '0',
+ DI(3) => \cnt[8]_i_2_n_0\,
+ DI(2) => \cnt[8]_i_3_n_0\,
+ DI(1) => \cnt[8]_i_4_n_0\,
+ DI(0) => \cnt[8]_i_5_n_0\,
+ O(3) => \cnt_reg[8]_i_1_n_4\,
+ O(2) => \cnt_reg[8]_i_1_n_5\,
+ O(1) => \cnt_reg[8]_i_1_n_6\,
+ O(0) => \cnt_reg[8]_i_1_n_7\,
+ S(3) => \cnt[8]_i_6_n_0\,
+ S(2) => \cnt[8]_i_7_n_0\,
+ S(1) => \cnt[8]_i_8_n_0\,
+ S(0) => \cnt[8]_i_9_n_0\
+ );
+\cnt_reg[9]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \cnt[0]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => \cnt_reg[8]_i_1_n_6\,
+ Q => cnt_reg(9)
+ );
+\cr[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"55FDFDFDFFFFFFFF"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => i2c_al,
+ I2 => cmd_ack,
+ I3 => iack_o_reg,
+ I4 => wb_we_o,
+ I5 => iack_o_reg_0,
+ O => \cr_reg[4]\(0)
+ );
+dscl_oen_reg: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => \^i2c_scl_t\,
+ Q => dscl_oen
+ );
+iscl_oen_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FBFFFBF3"
+ )
+ port map (
+ I0 => iscl_oen,
+ I1 => s00_axi_aresetn,
+ I2 => i2c_al,
+ I3 => \iscl_oen9_out__0\,
+ I4 => \^i2c_scl_t\,
+ O => iscl_oen_i_1_n_0
+ );
+iscl_oen_i_2: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ O => \^iscl_oen_reg_0\
+ );
+iscl_oen_i_3: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00F3011F"
+ )
+ port map (
+ I0 => c_state(3),
+ I1 => c_state(2),
+ I2 => c_state(1),
+ I3 => c_state(4),
+ I4 => c_state(0),
+ O => iscl_oen
+ );
+iscl_oen_i_4: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"55560000"
+ )
+ port map (
+ I0 => c_state(4),
+ I1 => c_state(3),
+ I2 => c_state(2),
+ I3 => c_state(1),
+ I4 => clk_en,
+ O => \iscl_oen9_out__0\
+ );
+iscl_oen_reg: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => iscl_oen_i_1_n_0,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \^i2c_scl_t\
+ );
+isda_oen_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"FBFFFBF3"
+ )
+ port map (
+ I0 => isda_oen,
+ I1 => s00_axi_aresetn,
+ I2 => i2c_al,
+ I3 => \isda_oen7_out__0\,
+ I4 => \^i2c_sda_t\,
+ O => isda_oen_i_1_n_0
+ );
+isda_oen_i_2: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000C8CB03038F83"
+ )
+ port map (
+ I0 => \statemachine.core_txd_reg_0\,
+ I1 => c_state(3),
+ I2 => c_state(2),
+ I3 => c_state(0),
+ I4 => c_state(4),
+ I5 => c_state(1),
+ O => isda_oen
+ );
+isda_oen_i_3: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0F0F1F1E00000000"
+ )
+ port map (
+ I0 => c_state(1),
+ I1 => c_state(2),
+ I2 => c_state(4),
+ I3 => c_state(0),
+ I4 => c_state(3),
+ I5 => clk_en,
+ O => \isda_oen7_out__0\
+ );
+isda_oen_reg: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => isda_oen_i_1_n_0,
+ PRE => \^iscl_oen_reg_0\,
+ Q => \^i2c_sda_t\
+ );
+minusOp_carry: unisim.vcomponents.CARRY4
+ port map (
+ CI => '0',
+ CO(3) => minusOp_carry_n_0,
+ CO(2) => minusOp_carry_n_1,
+ CO(1) => minusOp_carry_n_2,
+ CO(0) => minusOp_carry_n_3,
+ CYINIT => filter_cnt(0),
+ DI(3 downto 0) => filter_cnt(4 downto 1),
+ O(3) => minusOp_carry_n_4,
+ O(2) => minusOp_carry_n_5,
+ O(1) => minusOp_carry_n_6,
+ O(0) => minusOp_carry_n_7,
+ S(3) => minusOp_carry_i_1_n_0,
+ S(2) => minusOp_carry_i_2_n_0,
+ S(1) => minusOp_carry_i_3_n_0,
+ S(0) => minusOp_carry_i_4_n_0
+ );
+\minusOp_carry__0\: unisim.vcomponents.CARRY4
+ port map (
+ CI => minusOp_carry_n_0,
+ CO(3) => \minusOp_carry__0_n_0\,
+ CO(2) => \minusOp_carry__0_n_1\,
+ CO(1) => \minusOp_carry__0_n_2\,
+ CO(0) => \minusOp_carry__0_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => filter_cnt(8 downto 5),
+ O(3) => \minusOp_carry__0_n_4\,
+ O(2) => \minusOp_carry__0_n_5\,
+ O(1) => \minusOp_carry__0_n_6\,
+ O(0) => \minusOp_carry__0_n_7\,
+ S(3) => \minusOp_carry__0_i_1_n_0\,
+ S(2) => \minusOp_carry__0_i_2_n_0\,
+ S(1) => \minusOp_carry__0_i_3_n_0\,
+ S(0) => \minusOp_carry__0_i_4_n_0\
+ );
+\minusOp_carry__0_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(8),
+ O => \minusOp_carry__0_i_1_n_0\
+ );
+\minusOp_carry__0_i_2\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(7),
+ O => \minusOp_carry__0_i_2_n_0\
+ );
+\minusOp_carry__0_i_3\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(6),
+ O => \minusOp_carry__0_i_3_n_0\
+ );
+\minusOp_carry__0_i_4\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(5),
+ O => \minusOp_carry__0_i_4_n_0\
+ );
+\minusOp_carry__1\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \minusOp_carry__0_n_0\,
+ CO(3) => \minusOp_carry__1_n_0\,
+ CO(2) => \minusOp_carry__1_n_1\,
+ CO(1) => \minusOp_carry__1_n_2\,
+ CO(0) => \minusOp_carry__1_n_3\,
+ CYINIT => '0',
+ DI(3 downto 0) => filter_cnt(12 downto 9),
+ O(3) => \minusOp_carry__1_n_4\,
+ O(2) => \minusOp_carry__1_n_5\,
+ O(1) => \minusOp_carry__1_n_6\,
+ O(0) => \minusOp_carry__1_n_7\,
+ S(3) => \minusOp_carry__1_i_1_n_0\,
+ S(2) => \minusOp_carry__1_i_2_n_0\,
+ S(1) => \minusOp_carry__1_i_3_n_0\,
+ S(0) => \minusOp_carry__1_i_4_n_0\
+ );
+\minusOp_carry__1_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(12),
+ O => \minusOp_carry__1_i_1_n_0\
+ );
+\minusOp_carry__1_i_2\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(11),
+ O => \minusOp_carry__1_i_2_n_0\
+ );
+\minusOp_carry__1_i_3\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(10),
+ O => \minusOp_carry__1_i_3_n_0\
+ );
+\minusOp_carry__1_i_4\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(9),
+ O => \minusOp_carry__1_i_4_n_0\
+ );
+\minusOp_carry__2\: unisim.vcomponents.CARRY4
+ port map (
+ CI => \minusOp_carry__1_n_0\,
+ CO(3 downto 0) => \NLW_minusOp_carry__2_CO_UNCONNECTED\(3 downto 0),
+ CYINIT => '0',
+ DI(3 downto 0) => B"0000",
+ O(3 downto 1) => \NLW_minusOp_carry__2_O_UNCONNECTED\(3 downto 1),
+ O(0) => \minusOp_carry__2_n_7\,
+ S(3 downto 1) => B"000",
+ S(0) => \minusOp_carry__2_i_1_n_0\
+ );
+\minusOp_carry__2_i_1\: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(13),
+ O => \minusOp_carry__2_i_1_n_0\
+ );
+minusOp_carry_i_1: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(4),
+ O => minusOp_carry_i_1_n_0
+ );
+minusOp_carry_i_2: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(3),
+ O => minusOp_carry_i_2_n_0
+ );
+minusOp_carry_i_3: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(2),
+ O => minusOp_carry_i_3_n_0
+ );
+minusOp_carry_i_4: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => filter_cnt(1),
+ O => minusOp_carry_i_4_n_0
+ );
+sda_chk_i_1: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000100000"
+ )
+ port map (
+ I0 => c_state(4),
+ I1 => c_state(1),
+ I2 => c_state(3),
+ I3 => c_state(0),
+ I4 => c_state(2),
+ I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ O => sda_chk_i_1_n_0
+ );
+sda_chk_reg: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => \FSM_sequential_c_state[4]_i_1_n_0\,
+ CLR => \^iscl_oen_reg_0\,
+ D => sda_chk_i_1_n_0,
+ Q => sda_chk_reg_n_0
+ );
+slave_wait_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0F04"
+ )
+ port map (
+ I0 => dscl_oen,
+ I1 => \^i2c_scl_t\,
+ I2 => sSCL,
+ I3 => slave_wait,
+ O => slave_wait0
+ );
+slave_wait_reg: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg_0\,
+ D => slave_wait0,
+ Q => slave_wait
+ );
+\sr[0]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_0\,
+ I1 => core_rxd,
+ I2 => \txr_reg[6]\(0),
+ I3 => s00_axi_aresetn,
+ O => \sr_reg[0]\(0)
+ );
+\st_irq_block.al_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"AA08"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \st_irq_block.al_reg\,
+ I2 => \cr_reg[7]\(3),
+ I3 => i2c_al,
+ O => al
+ );
+\st_irq_block.irq_flag_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"55540000"
+ )
+ port map (
+ I0 => \cr_reg[0]\,
+ I1 => i2c_al,
+ I2 => cmd_ack,
+ I3 => irq_flag,
+ I4 => s00_axi_aresetn,
+ O => irq_flag1_out
+ );
+\statemachine.ack_out_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"08FF0800"
+ )
+ port map (
+ I0 => core_rxd,
+ I1 => s00_axi_aresetn,
+ I2 => i2c_al,
+ I3 => \statemachine.ack_out_i_2_n_0\,
+ I4 => ack_out,
+ O => \statemachine.ack_out_reg\
+ );
+\statemachine.ack_out_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"DDDDDDDDDDFDDDDD"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => i2c_al,
+ I2 => \out\(2),
+ I3 => \out\(0),
+ I4 => core_ack,
+ I5 => \out\(1),
+ O => \statemachine.ack_out_i_2_n_0\
+ );
+\statemachine.core_cmd[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000100000"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => \out\(0),
+ I2 => \cr_reg[7]\(3),
+ I3 => \out\(1),
+ I4 => s00_axi_aresetn,
+ I5 => i2c_al,
+ O => \statemachine.core_cmd_reg[3]\(0)
+ );
+\statemachine.core_cmd[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000022222E22"
+ )
+ port map (
+ I0 => \FSM_sequential_statemachine.c_state_reg[1]_0\,
+ I1 => \out\(2),
+ I2 => \out\(1),
+ I3 => \cr_reg[7]\(2),
+ I4 => \out\(0),
+ I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ O => \statemachine.core_cmd_reg[3]\(1)
+ );
+\statemachine.core_cmd[2]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => core_cmd(0),
+ I1 => s00_axi_aresetn,
+ I2 => i2c_al,
+ O => \statemachine.core_cmd_reg[3]\(2)
+ );
+\statemachine.core_cmd[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0040"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => \FSM_sequential_statemachine.c_state_reg[1]\,
+ I2 => s00_axi_aresetn,
+ I3 => i2c_al,
+ O => \statemachine.core_cmd_reg[3]\(3)
+ );
+\statemachine.core_txd_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => core_txd,
+ I1 => s00_axi_aresetn,
+ I2 => i2c_al,
+ O => \statemachine.core_txd_reg\
+ );
+\statemachine.core_txd_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"5455FFFD10002220"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => \out\(0),
+ I2 => ack_in,
+ I3 => core_ack,
+ I4 => \out\(1),
+ I5 => \sr_reg[7]\(0),
+ O => core_txd
+ );
+\statemachine.host_ack_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"000000000000A020"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => \cr_reg[7]\(2),
+ I2 => core_ack,
+ I3 => \out\(0),
+ I4 => \out\(1),
+ I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ O => \statemachine.host_ack_reg\
+ );
+\statemachine.ld_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00000400"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => \FSM_sequential_statemachine.c_state[2]_i_3_n_0\,
+ I2 => \out\(1),
+ I3 => s00_axi_aresetn,
+ I4 => i2c_al,
+ O => \statemachine.ld_reg\
+ );
+\statemachine.shift_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000004440000"
+ )
+ port map (
+ I0 => \out\(2),
+ I1 => core_ack,
+ I2 => \out\(0),
+ I3 => cnt_done,
+ I4 => \out\(1),
+ I5 => \FSM_sequential_c_state[4]_i_3_n_0\,
+ O => \statemachine.shift_reg\
+ );
+\wb_dat_o[6]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"30BB3088"
+ )
+ port map (
+ I0 => \cr_reg[7]\(2),
+ I1 => wb_adr_o(1),
+ I2 => \txr_reg[6]\(1),
+ I3 => wb_adr_o(0),
+ I4 => i2c_busy,
+ O => \wb_dat_o[6]_i_3_n_0\
+ );
+\wb_dat_o_reg[6]_i_1\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \sr_reg[6]\,
+ I1 => \wb_dat_o[6]_i_3_n_0\,
+ O => D(0),
+ S => wb_adr_o(2)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl is
+ port (
+ iscl_oen_reg : out STD_LOGIC;
+ i2c_scl_t : out STD_LOGIC;
+ i2c_sda_t : out STD_LOGIC;
+ irq_flag1_out : out STD_LOGIC;
+ rxack_0 : out STD_LOGIC;
+ al : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ s00_axi_aclk : in STD_LOGIC;
+ s00_axi_aresetn : in STD_LOGIC;
+ \cr_reg[0]\ : in STD_LOGIC;
+ irq_flag : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ \ctr_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ i2c_sda_i : in STD_LOGIC;
+ i2c_scl_i : in STD_LOGIC;
+ \st_irq_block.al_reg\ : in STD_LOGIC;
+ \cr_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \cr_reg[0]_0\ : in STD_LOGIC;
+ \cr_reg[1]\ : in STD_LOGIC;
+ \cr_reg[2]\ : in STD_LOGIC;
+ \txr_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ ack_in : in STD_LOGIC;
+ \cr_reg[5]\ : in STD_LOGIC;
+ \cr_reg[7]_0\ : in STD_LOGIC;
+ iack_o_reg : in STD_LOGIC;
+ wb_we_o : in STD_LOGIC;
+ iack_o_reg_0 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl : entity is "i2c_master_byte_ctrl";
+end system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl;
+
+architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl is
+ signal \FSM_sequential_statemachine.c_state[0]_i_2_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_statemachine.c_state[1]_i_3_n_0\ : STD_LOGIC;
+ signal \FSM_sequential_statemachine.c_state[2]_i_4_n_0\ : STD_LOGIC;
+ signal ack_out : STD_LOGIC;
+ signal bit_ctrl_n_10 : STD_LOGIC;
+ signal bit_ctrl_n_11 : STD_LOGIC;
+ signal bit_ctrl_n_12 : STD_LOGIC;
+ signal bit_ctrl_n_13 : STD_LOGIC;
+ signal bit_ctrl_n_14 : STD_LOGIC;
+ signal bit_ctrl_n_15 : STD_LOGIC;
+ signal bit_ctrl_n_17 : STD_LOGIC;
+ signal bit_ctrl_n_18 : STD_LOGIC;
+ signal bit_ctrl_n_19 : STD_LOGIC;
+ signal bit_ctrl_n_20 : STD_LOGIC;
+ signal bit_ctrl_n_7 : STD_LOGIC;
+ signal bit_ctrl_n_8 : STD_LOGIC;
+ signal bit_ctrl_n_9 : STD_LOGIC;
+ signal c_state : STD_LOGIC;
+ signal \c_state__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ attribute RTL_KEEP : string;
+ attribute RTL_KEEP of \c_state__0\ : signal is "yes";
+ signal cmd : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal cmd_ack : STD_LOGIC;
+ signal cnt_done : STD_LOGIC;
+ signal core_cmd : STD_LOGIC_VECTOR ( 2 to 2 );
+ signal dcnt : STD_LOGIC;
+ signal \dcnt[0]_i_1_n_0\ : STD_LOGIC;
+ signal \dcnt[1]_i_1_n_0\ : STD_LOGIC;
+ signal \dcnt[2]_i_1_n_0\ : STD_LOGIC;
+ signal \dcnt_reg_n_0_[0]\ : STD_LOGIC;
+ signal \dcnt_reg_n_0_[1]\ : STD_LOGIC;
+ signal \dcnt_reg_n_0_[2]\ : STD_LOGIC;
+ signal dout : STD_LOGIC_VECTOR ( 7 to 7 );
+ signal \^iscl_oen_reg\ : STD_LOGIC;
+ signal \sr[1]_i_1_n_0\ : STD_LOGIC;
+ signal \sr[2]_i_1_n_0\ : STD_LOGIC;
+ signal \sr[3]_i_1_n_0\ : STD_LOGIC;
+ signal \sr[4]_i_1_n_0\ : STD_LOGIC;
+ signal \sr[5]_i_1_n_0\ : STD_LOGIC;
+ signal \sr[6]_i_1_n_0\ : STD_LOGIC;
+ signal \sr[7]_i_2_n_0\ : STD_LOGIC;
+ signal \sr_reg_n_0_[0]\ : STD_LOGIC;
+ signal \sr_reg_n_0_[1]\ : STD_LOGIC;
+ signal \sr_reg_n_0_[2]\ : STD_LOGIC;
+ signal \sr_reg_n_0_[3]\ : STD_LOGIC;
+ signal \sr_reg_n_0_[4]\ : STD_LOGIC;
+ signal \sr_reg_n_0_[5]\ : STD_LOGIC;
+ signal \sr_reg_n_0_[6]\ : STD_LOGIC;
+ signal \statemachine.core_cmd[1]_i_2_n_0\ : STD_LOGIC;
+ signal \statemachine.core_cmd[3]_i_2_n_0\ : STD_LOGIC;
+ signal \statemachine.core_txd_reg_n_0\ : STD_LOGIC;
+ signal \statemachine.ld_reg_n_0\ : STD_LOGIC;
+ signal \statemachine.shift_reg_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[0]_i_2_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[1]_i_2_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[2]_i_2_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[3]_i_2_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[4]_i_2_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[5]_i_2_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[6]_i_2_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[7]_i_2_n_0\ : STD_LOGIC;
+ attribute KEEP : string;
+ attribute KEEP of \FSM_sequential_statemachine.c_state_reg[0]\ : label is "yes";
+ attribute KEEP of \FSM_sequential_statemachine.c_state_reg[1]\ : label is "yes";
+ attribute KEEP of \FSM_sequential_statemachine.c_state_reg[2]\ : label is "yes";
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \dcnt[0]_i_1\ : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of \dcnt[1]_i_1\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \dcnt[2]_i_1\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \sr[1]_i_1\ : label is "soft_lutpair22";
+ attribute SOFT_HLUTNM of \sr[2]_i_1\ : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of \st_irq_block.rxack_i_1\ : label is "soft_lutpair22";
+begin
+ iscl_oen_reg <= \^iscl_oen_reg\;
+\FSM_sequential_statemachine.c_state[0]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"43407373"
+ )
+ port map (
+ I0 => cnt_done,
+ I1 => \c_state__0\(1),
+ I2 => \c_state__0\(0),
+ I3 => \cr_reg[7]\(3),
+ I4 => \cr_reg[7]\(1),
+ O => \FSM_sequential_statemachine.c_state[0]_i_2_n_0\
+ );
+\FSM_sequential_statemachine.c_state[1]_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"01"
+ )
+ port map (
+ I0 => \dcnt_reg_n_0_[1]\,
+ I1 => \dcnt_reg_n_0_[0]\,
+ I2 => \dcnt_reg_n_0_[2]\,
+ O => cnt_done
+ );
+\FSM_sequential_statemachine.c_state[1]_i_3\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FF54"
+ )
+ port map (
+ I0 => \cr_reg[7]\(3),
+ I1 => \cr_reg[7]\(1),
+ I2 => \cr_reg[7]\(0),
+ I3 => \c_state__0\(0),
+ O => \FSM_sequential_statemachine.c_state[1]_i_3_n_0\
+ );
+\FSM_sequential_statemachine.c_state[2]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"888888888888888B"
+ )
+ port map (
+ I0 => cnt_done,
+ I1 => \c_state__0\(1),
+ I2 => \cr_reg[7]\(3),
+ I3 => \cr_reg[7]\(0),
+ I4 => \cr_reg[7]\(1),
+ I5 => \c_state__0\(0),
+ O => \FSM_sequential_statemachine.c_state[2]_i_4_n_0\
+ );
+\FSM_sequential_statemachine.c_state_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => c_state,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_20,
+ Q => \c_state__0\(0)
+ );
+\FSM_sequential_statemachine.c_state_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => c_state,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_19,
+ Q => \c_state__0\(1)
+ );
+\FSM_sequential_statemachine.c_state_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => c_state,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_18,
+ Q => \c_state__0\(2)
+ );
+bit_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_bit_ctrl
+ port map (
+ D(0) => D(6),
+ E(0) => c_state,
+ \FSM_sequential_statemachine.c_state_reg[1]\ => \statemachine.core_cmd[3]_i_2_n_0\,
+ \FSM_sequential_statemachine.c_state_reg[1]_0\ => \statemachine.core_cmd[1]_i_2_n_0\,
+ \FSM_sequential_statemachine.c_state_reg[1]_1\ => \FSM_sequential_statemachine.c_state[0]_i_2_n_0\,
+ \FSM_sequential_statemachine.c_state_reg[1]_2\ => \FSM_sequential_statemachine.c_state[2]_i_4_n_0\,
+ \FSM_sequential_statemachine.c_state_reg[2]\(2) => bit_ctrl_n_18,
+ \FSM_sequential_statemachine.c_state_reg[2]\(1) => bit_ctrl_n_19,
+ \FSM_sequential_statemachine.c_state_reg[2]\(0) => bit_ctrl_n_20,
+ Q(15 downto 0) => Q(15 downto 0),
+ ack_in => ack_in,
+ ack_out => ack_out,
+ al => al,
+ cmd_ack => cmd_ack,
+ cnt_done => cnt_done,
+ core_cmd(0) => core_cmd(2),
+ \cr_reg[0]\ => \cr_reg[0]\,
+ \cr_reg[4]\(0) => E(0),
+ \cr_reg[7]\(3 downto 0) => \cr_reg[7]\(3 downto 0),
+ \cr_reg[7]_0\ => \FSM_sequential_statemachine.c_state[1]_i_3_n_0\,
+ \ctr_reg[7]\(0) => \ctr_reg[7]\(7),
+ i2c_scl_i => i2c_scl_i,
+ i2c_scl_t => i2c_scl_t,
+ i2c_sda_i => i2c_sda_i,
+ i2c_sda_t => i2c_sda_t,
+ iack_o_reg => iack_o_reg,
+ iack_o_reg_0 => iack_o_reg_0,
+ irq_flag => irq_flag,
+ irq_flag1_out => irq_flag1_out,
+ iscl_oen_reg_0 => \^iscl_oen_reg\,
+ \out\(2 downto 0) => \c_state__0\(2 downto 0),
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_aresetn => s00_axi_aresetn,
+ \sr_reg[0]\(0) => bit_ctrl_n_17,
+ \sr_reg[6]\ => \wb_dat_o[6]_i_2_n_0\,
+ \sr_reg[7]\(0) => dout(7),
+ \st_irq_block.al_reg\ => \st_irq_block.al_reg\,
+ \statemachine.ack_out_reg\ => bit_ctrl_n_15,
+ \statemachine.core_cmd_reg[3]\(3) => bit_ctrl_n_7,
+ \statemachine.core_cmd_reg[3]\(2) => bit_ctrl_n_8,
+ \statemachine.core_cmd_reg[3]\(1) => bit_ctrl_n_9,
+ \statemachine.core_cmd_reg[3]\(0) => bit_ctrl_n_10,
+ \statemachine.core_cmd_reg[3]_0\(3 downto 0) => cmd(3 downto 0),
+ \statemachine.core_txd_reg\ => bit_ctrl_n_12,
+ \statemachine.core_txd_reg_0\ => \statemachine.core_txd_reg_n_0\,
+ \statemachine.host_ack_reg\ => bit_ctrl_n_14,
+ \statemachine.ld_reg\ => bit_ctrl_n_11,
+ \statemachine.ld_reg_0\ => \statemachine.ld_reg_n_0\,
+ \statemachine.shift_reg\ => bit_ctrl_n_13,
+ \txr_reg[6]\(1) => \txr_reg[7]\(6),
+ \txr_reg[6]\(0) => \txr_reg[7]\(0),
+ wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
+ wb_we_o => wb_we_o
+ );
+\dcnt[0]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"8A"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \statemachine.ld_reg_n_0\,
+ I2 => \dcnt_reg_n_0_[0]\,
+ O => \dcnt[0]_i_1_n_0\
+ );
+\dcnt[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"A88A"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \statemachine.ld_reg_n_0\,
+ I2 => \dcnt_reg_n_0_[0]\,
+ I3 => \dcnt_reg_n_0_[1]\,
+ O => \dcnt[1]_i_1_n_0\
+ );
+\dcnt[2]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AAA8888A"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => \statemachine.ld_reg_n_0\,
+ I2 => \dcnt_reg_n_0_[1]\,
+ I3 => \dcnt_reg_n_0_[0]\,
+ I4 => \dcnt_reg_n_0_[2]\,
+ O => \dcnt[2]_i_1_n_0\
+ );
+\dcnt_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \dcnt[0]_i_1_n_0\,
+ Q => \dcnt_reg_n_0_[0]\
+ );
+\dcnt_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \dcnt[1]_i_1_n_0\,
+ Q => \dcnt_reg_n_0_[1]\
+ );
+\dcnt_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \dcnt[2]_i_1_n_0\,
+ Q => \dcnt_reg_n_0_[2]\
+ );
+\sr[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => \sr_reg_n_0_[0]\,
+ I2 => \txr_reg[7]\(1),
+ I3 => s00_axi_aresetn,
+ O => \sr[1]_i_1_n_0\
+ );
+\sr[2]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => \sr_reg_n_0_[1]\,
+ I2 => \txr_reg[7]\(2),
+ I3 => s00_axi_aresetn,
+ O => \sr[2]_i_1_n_0\
+ );
+\sr[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => \sr_reg_n_0_[2]\,
+ I2 => \txr_reg[7]\(3),
+ I3 => s00_axi_aresetn,
+ O => \sr[3]_i_1_n_0\
+ );
+\sr[4]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => \sr_reg_n_0_[3]\,
+ I2 => \txr_reg[7]\(4),
+ I3 => s00_axi_aresetn,
+ O => \sr[4]_i_1_n_0\
+ );
+\sr[5]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => \sr_reg_n_0_[4]\,
+ I2 => \txr_reg[7]\(5),
+ I3 => s00_axi_aresetn,
+ O => \sr[5]_i_1_n_0\
+ );
+\sr[6]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => \sr_reg_n_0_[5]\,
+ I2 => \txr_reg[7]\(6),
+ I3 => s00_axi_aresetn,
+ O => \sr[6]_i_1_n_0\
+ );
+\sr[7]_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"FB"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => s00_axi_aresetn,
+ I2 => \statemachine.shift_reg_n_0\,
+ O => dcnt
+ );
+\sr[7]_i_2\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"E400"
+ )
+ port map (
+ I0 => \statemachine.ld_reg_n_0\,
+ I1 => \sr_reg_n_0_[6]\,
+ I2 => \txr_reg[7]\(7),
+ I3 => s00_axi_aresetn,
+ O => \sr[7]_i_2_n_0\
+ );
+\sr_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_17,
+ Q => \sr_reg_n_0_[0]\
+ );
+\sr_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \sr[1]_i_1_n_0\,
+ Q => \sr_reg_n_0_[1]\
+ );
+\sr_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \sr[2]_i_1_n_0\,
+ Q => \sr_reg_n_0_[2]\
+ );
+\sr_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \sr[3]_i_1_n_0\,
+ Q => \sr_reg_n_0_[3]\
+ );
+\sr_reg[4]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \sr[4]_i_1_n_0\,
+ Q => \sr_reg_n_0_[4]\
+ );
+\sr_reg[5]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \sr[5]_i_1_n_0\,
+ Q => \sr_reg_n_0_[5]\
+ );
+\sr_reg[6]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \sr[6]_i_1_n_0\,
+ Q => \sr_reg_n_0_[6]\
+ );
+\sr_reg[7]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => dcnt,
+ CLR => \^iscl_oen_reg\,
+ D => \sr[7]_i_2_n_0\,
+ Q => dout(7)
+ );
+\st_irq_block.rxack_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => ack_out,
+ O => rxack_0
+ );
+\statemachine.ack_out_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_15,
+ Q => ack_out
+ );
+\statemachine.core_cmd[1]_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00000001"
+ )
+ port map (
+ I0 => \c_state__0\(1),
+ I1 => \c_state__0\(0),
+ I2 => \cr_reg[7]\(3),
+ I3 => \cr_reg[7]\(0),
+ I4 => \cr_reg[7]\(1),
+ O => \statemachine.core_cmd[1]_i_2_n_0\
+ );
+\statemachine.core_cmd[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000000F0C40FC4"
+ )
+ port map (
+ I0 => \cr_reg[7]\(3),
+ I1 => \cr_reg[7]\(1),
+ I2 => \c_state__0\(0),
+ I3 => \c_state__0\(1),
+ I4 => cnt_done,
+ I5 => \c_state__0\(2),
+ O => core_cmd(2)
+ );
+\statemachine.core_cmd[3]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"4848484878787B78"
+ )
+ port map (
+ I0 => cnt_done,
+ I1 => \c_state__0\(1),
+ I2 => \c_state__0\(0),
+ I3 => \cr_reg[7]\(0),
+ I4 => \cr_reg[7]\(3),
+ I5 => \cr_reg[7]\(1),
+ O => \statemachine.core_cmd[3]_i_2_n_0\
+ );
+\statemachine.core_cmd_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => c_state,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_10,
+ Q => cmd(0)
+ );
+\statemachine.core_cmd_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => c_state,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_9,
+ Q => cmd(1)
+ );
+\statemachine.core_cmd_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => c_state,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_8,
+ Q => cmd(2)
+ );
+\statemachine.core_cmd_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => c_state,
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_7,
+ Q => cmd(3)
+ );
+\statemachine.core_txd_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_12,
+ Q => \statemachine.core_txd_reg_n_0\
+ );
+\statemachine.host_ack_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_14,
+ Q => cmd_ack
+ );
+\statemachine.ld_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_11,
+ Q => \statemachine.ld_reg_n_0\
+ );
+\statemachine.shift_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^iscl_oen_reg\,
+ D => bit_ctrl_n_13,
+ Q => \statemachine.shift_reg_n_0\
+ );
+\wb_dat_o[0]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \sr_reg_n_0_[0]\,
+ I1 => \ctr_reg[7]\(0),
+ I2 => wb_adr_o(1),
+ I3 => Q(8),
+ I4 => wb_adr_o(0),
+ I5 => Q(0),
+ O => \wb_dat_o[0]_i_2_n_0\
+ );
+\wb_dat_o[1]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \sr_reg_n_0_[1]\,
+ I1 => \ctr_reg[7]\(1),
+ I2 => wb_adr_o(1),
+ I3 => Q(9),
+ I4 => wb_adr_o(0),
+ I5 => Q(1),
+ O => \wb_dat_o[1]_i_2_n_0\
+ );
+\wb_dat_o[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"3808FFFF38080000"
+ )
+ port map (
+ I0 => \cr_reg[2]\,
+ I1 => wb_adr_o(1),
+ I2 => wb_adr_o(0),
+ I3 => \txr_reg[7]\(2),
+ I4 => wb_adr_o(2),
+ I5 => \wb_dat_o[2]_i_2_n_0\,
+ O => D(2)
+ );
+\wb_dat_o[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \sr_reg_n_0_[2]\,
+ I1 => \ctr_reg[7]\(2),
+ I2 => wb_adr_o(1),
+ I3 => Q(10),
+ I4 => wb_adr_o(0),
+ I5 => Q(2),
+ O => \wb_dat_o[2]_i_2_n_0\
+ );
+\wb_dat_o[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"3808FFFF38080000"
+ )
+ port map (
+ I0 => ack_in,
+ I1 => wb_adr_o(1),
+ I2 => wb_adr_o(0),
+ I3 => \txr_reg[7]\(3),
+ I4 => wb_adr_o(2),
+ I5 => \wb_dat_o[3]_i_2_n_0\,
+ O => D(3)
+ );
+\wb_dat_o[3]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \sr_reg_n_0_[3]\,
+ I1 => \ctr_reg[7]\(3),
+ I2 => wb_adr_o(1),
+ I3 => Q(11),
+ I4 => wb_adr_o(0),
+ I5 => Q(3),
+ O => \wb_dat_o[3]_i_2_n_0\
+ );
+\wb_dat_o[4]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"3808FFFF38080000"
+ )
+ port map (
+ I0 => \cr_reg[7]\(0),
+ I1 => wb_adr_o(1),
+ I2 => wb_adr_o(0),
+ I3 => \txr_reg[7]\(4),
+ I4 => wb_adr_o(2),
+ I5 => \wb_dat_o[4]_i_2_n_0\,
+ O => D(4)
+ );
+\wb_dat_o[4]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \sr_reg_n_0_[4]\,
+ I1 => \ctr_reg[7]\(4),
+ I2 => wb_adr_o(1),
+ I3 => Q(12),
+ I4 => wb_adr_o(0),
+ I5 => Q(4),
+ O => \wb_dat_o[4]_i_2_n_0\
+ );
+\wb_dat_o[5]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \sr_reg_n_0_[5]\,
+ I1 => \ctr_reg[7]\(5),
+ I2 => wb_adr_o(1),
+ I3 => Q(13),
+ I4 => wb_adr_o(0),
+ I5 => Q(5),
+ O => \wb_dat_o[5]_i_2_n_0\
+ );
+\wb_dat_o[6]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => \sr_reg_n_0_[6]\,
+ I1 => \ctr_reg[7]\(6),
+ I2 => wb_adr_o(1),
+ I3 => Q(14),
+ I4 => wb_adr_o(0),
+ I5 => Q(6),
+ O => \wb_dat_o[6]_i_2_n_0\
+ );
+\wb_dat_o[7]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AFA0CFCFAFA0C0C0"
+ )
+ port map (
+ I0 => dout(7),
+ I1 => \ctr_reg[7]\(7),
+ I2 => wb_adr_o(1),
+ I3 => Q(15),
+ I4 => wb_adr_o(0),
+ I5 => Q(7),
+ O => \wb_dat_o[7]_i_2_n_0\
+ );
+\wb_dat_o_reg[0]_i_1\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \wb_dat_o[0]_i_2_n_0\,
+ I1 => \cr_reg[0]_0\,
+ O => D(0),
+ S => wb_adr_o(2)
+ );
+\wb_dat_o_reg[1]_i_1\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \wb_dat_o[1]_i_2_n_0\,
+ I1 => \cr_reg[1]\,
+ O => D(1),
+ S => wb_adr_o(2)
+ );
+\wb_dat_o_reg[5]_i_1\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \wb_dat_o[5]_i_2_n_0\,
+ I1 => \cr_reg[5]\,
+ O => D(5),
+ S => wb_adr_o(2)
+ );
+\wb_dat_o_reg[7]_i_1\: unisim.vcomponents.MUXF7
+ port map (
+ I0 => \wb_dat_o[7]_i_2_n_0\,
+ I1 => \cr_reg[7]_0\,
+ O => D(7),
+ S => wb_adr_o(2)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity system_design_axi_wb_i2c_master_2_0_i2c_master_top is
+ port (
+ wb_ack_i : out STD_LOGIC;
+ wb_rst_o : out STD_LOGIC;
+ i2c_scl_t : out STD_LOGIC;
+ axi_int_o : out STD_LOGIC;
+ i2c_sda_t : out STD_LOGIC;
+ Q : out STD_LOGIC_VECTOR ( 0 to 0 );
+ s_stb_r_reg : out STD_LOGIC;
+ \s_rdata_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ \s_rdata_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
+ s_stb_r_reg_0 : in STD_LOGIC;
+ s00_axi_aclk : in STD_LOGIC;
+ s00_axi_aresetn : in STD_LOGIC;
+ i2c_sda_i : in STD_LOGIC;
+ i2c_scl_i : in STD_LOGIC;
+ s00_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
+ wb_adr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_awvalid : in STD_LOGIC;
+ s00_axi_arvalid : in STD_LOGIC;
+ wb_cyc_o : in STD_LOGIC;
+ wb_we_o : in STD_LOGIC;
+ iack_o_reg_0 : in STD_LOGIC;
+ E : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_we_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
+ s_we_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+ D : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \s_addr_reg[4]\ : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_2_0_i2c_master_top : entity is "i2c_master_top";
+end system_design_axi_wb_i2c_master_2_0_i2c_master_top;
+
+architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_i2c_master_top is
+ signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal ack_in : STD_LOGIC;
+ signal al : STD_LOGIC;
+ signal byte_ctrl_n_14 : STD_LOGIC;
+ signal \cr[0]_i_1_n_0\ : STD_LOGIC;
+ signal \cr[1]_i_1_n_0\ : STD_LOGIC;
+ signal \cr[2]_i_1_n_0\ : STD_LOGIC;
+ signal \cr[3]_i_1_n_0\ : STD_LOGIC;
+ signal \cr_reg_n_0_[0]\ : STD_LOGIC;
+ signal \cr_reg_n_0_[1]\ : STD_LOGIC;
+ signal \cr_reg_n_0_[2]\ : STD_LOGIC;
+ signal ctr : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal \ctr_reg_n_0_[0]\ : STD_LOGIC;
+ signal \ctr_reg_n_0_[1]\ : STD_LOGIC;
+ signal \ctr_reg_n_0_[2]\ : STD_LOGIC;
+ signal \ctr_reg_n_0_[3]\ : STD_LOGIC;
+ signal \ctr_reg_n_0_[4]\ : STD_LOGIC;
+ signal \ctr_reg_n_0_[5]\ : STD_LOGIC;
+ signal data0 : STD_LOGIC_VECTOR ( 13 downto 0 );
+ signal ien : STD_LOGIC;
+ signal irq_flag : STD_LOGIC;
+ signal irq_flag1_out : STD_LOGIC;
+ signal \prer[10]_i_1_n_0\ : STD_LOGIC;
+ signal \prer[11]_i_1_n_0\ : STD_LOGIC;
+ signal \prer[12]_i_1_n_0\ : STD_LOGIC;
+ signal \prer[13]_i_1_n_0\ : STD_LOGIC;
+ signal \prer[14]_i_1_n_0\ : STD_LOGIC;
+ signal \prer[15]_i_2_n_0\ : STD_LOGIC;
+ signal \prer[8]_i_1_n_0\ : STD_LOGIC;
+ signal \prer[9]_i_1_n_0\ : STD_LOGIC;
+ signal \prer_reg_n_0_[0]\ : STD_LOGIC;
+ signal \prer_reg_n_0_[1]\ : STD_LOGIC;
+ signal read : STD_LOGIC;
+ signal rxack : STD_LOGIC;
+ signal rxack_0 : STD_LOGIC;
+ signal \st_irq_block.al_reg_n_0\ : STD_LOGIC;
+ signal \st_irq_block.wb_inta_o_i_1_n_0\ : STD_LOGIC;
+ signal start : STD_LOGIC;
+ signal stop : STD_LOGIC;
+ signal tip : STD_LOGIC;
+ signal tip_1 : STD_LOGIC;
+ signal txr : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal \^wb_ack_i\ : STD_LOGIC;
+ signal wb_dat_o : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal \wb_dat_o[0]_i_3_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[1]_i_3_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[5]_i_3_n_0\ : STD_LOGIC;
+ signal \wb_dat_o[7]_i_3_n_0\ : STD_LOGIC;
+ signal \^wb_rst_o\ : STD_LOGIC;
+ signal write : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair24";
+ attribute SOFT_HLUTNM of \ctr[0]_i_1\ : label is "soft_lutpair26";
+ attribute SOFT_HLUTNM of \ctr[1]_i_1\ : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of \ctr[2]_i_1\ : label is "soft_lutpair28";
+ attribute SOFT_HLUTNM of \ctr[3]_i_1\ : label is "soft_lutpair24";
+ attribute SOFT_HLUTNM of \ctr[4]_i_1\ : label is "soft_lutpair29";
+ attribute SOFT_HLUTNM of \ctr[5]_i_1\ : label is "soft_lutpair30";
+ attribute SOFT_HLUTNM of \ctr[6]_i_1\ : label is "soft_lutpair31";
+ attribute SOFT_HLUTNM of \ctr[7]_i_2\ : label is "soft_lutpair32";
+ attribute SOFT_HLUTNM of \prer[10]_i_1\ : label is "soft_lutpair28";
+ attribute SOFT_HLUTNM of \prer[12]_i_1\ : label is "soft_lutpair29";
+ attribute SOFT_HLUTNM of \prer[13]_i_1\ : label is "soft_lutpair30";
+ attribute SOFT_HLUTNM of \prer[14]_i_1\ : label is "soft_lutpair31";
+ attribute SOFT_HLUTNM of \prer[15]_i_2\ : label is "soft_lutpair32";
+ attribute SOFT_HLUTNM of \prer[8]_i_1\ : label is "soft_lutpair26";
+ attribute SOFT_HLUTNM of \prer[9]_i_1\ : label is "soft_lutpair27";
+ attribute SOFT_HLUTNM of \s_rdata[7]_i_1\ : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of s_stb_r_i_1 : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of \st_irq_block.tip_i_1\ : label is "soft_lutpair25";
+ attribute SOFT_HLUTNM of \st_irq_block.wb_inta_o_i_1\ : label is "soft_lutpair25";
+begin
+ Q(0) <= \^q\(0);
+ wb_ack_i <= \^wb_ack_i\;
+ wb_rst_o <= \^wb_rst_o\;
+byte_ctrl: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_byte_ctrl
+ port map (
+ D(7 downto 0) => wb_dat_o(7 downto 0),
+ E(0) => byte_ctrl_n_14,
+ Q(15 downto 2) => data0(13 downto 0),
+ Q(1) => \prer_reg_n_0_[1]\,
+ Q(0) => \prer_reg_n_0_[0]\,
+ ack_in => ack_in,
+ al => al,
+ \cr_reg[0]\ => \cr_reg_n_0_[0]\,
+ \cr_reg[0]_0\ => \wb_dat_o[0]_i_3_n_0\,
+ \cr_reg[1]\ => \wb_dat_o[1]_i_3_n_0\,
+ \cr_reg[2]\ => \cr_reg_n_0_[2]\,
+ \cr_reg[5]\ => \wb_dat_o[5]_i_3_n_0\,
+ \cr_reg[7]\(3) => start,
+ \cr_reg[7]\(2) => stop,
+ \cr_reg[7]\(1) => read,
+ \cr_reg[7]\(0) => write,
+ \cr_reg[7]_0\ => \wb_dat_o[7]_i_3_n_0\,
+ \ctr_reg[7]\(7) => \^q\(0),
+ \ctr_reg[7]\(6) => ien,
+ \ctr_reg[7]\(5) => \ctr_reg_n_0_[5]\,
+ \ctr_reg[7]\(4) => \ctr_reg_n_0_[4]\,
+ \ctr_reg[7]\(3) => \ctr_reg_n_0_[3]\,
+ \ctr_reg[7]\(2) => \ctr_reg_n_0_[2]\,
+ \ctr_reg[7]\(1) => \ctr_reg_n_0_[1]\,
+ \ctr_reg[7]\(0) => \ctr_reg_n_0_[0]\,
+ i2c_scl_i => i2c_scl_i,
+ i2c_scl_t => i2c_scl_t,
+ i2c_sda_i => i2c_sda_i,
+ i2c_sda_t => i2c_sda_t,
+ iack_o_reg => \^wb_ack_i\,
+ iack_o_reg_0 => iack_o_reg_0,
+ irq_flag => irq_flag,
+ irq_flag1_out => irq_flag1_out,
+ iscl_oen_reg => \^wb_rst_o\,
+ rxack_0 => rxack_0,
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_aresetn => s00_axi_aresetn,
+ \st_irq_block.al_reg\ => \st_irq_block.al_reg_n_0\,
+ \txr_reg[7]\(7 downto 0) => txr(7 downto 0),
+ wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
+ wb_we_o => wb_we_o
+ );
+\cr[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8000FFFF80000000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(0),
+ I2 => wb_we_o,
+ I3 => \^wb_ack_i\,
+ I4 => \s_addr_reg[4]\,
+ I5 => \cr_reg_n_0_[0]\,
+ O => \cr[0]_i_1_n_0\
+ );
+\cr[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8000FFFF80000000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(1),
+ I2 => wb_we_o,
+ I3 => \^wb_ack_i\,
+ I4 => \s_addr_reg[4]\,
+ I5 => \cr_reg_n_0_[1]\,
+ O => \cr[1]_i_1_n_0\
+ );
+\cr[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8000FFFF80000000"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(2),
+ I2 => wb_we_o,
+ I3 => \^wb_ack_i\,
+ I4 => \s_addr_reg[4]\,
+ I5 => \cr_reg_n_0_[2]\,
+ O => \cr[2]_i_1_n_0\
+ );
+\cr[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"C808"
+ )
+ port map (
+ I0 => s00_axi_wdata(3),
+ I1 => s00_axi_aresetn,
+ I2 => iack_o_reg_0,
+ I3 => ack_in,
+ O => \cr[3]_i_1_n_0\
+ );
+\cr_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => \cr[0]_i_1_n_0\,
+ Q => \cr_reg_n_0_[0]\
+ );
+\cr_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => \cr[1]_i_1_n_0\,
+ Q => \cr_reg_n_0_[1]\
+ );
+\cr_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => \cr[2]_i_1_n_0\,
+ Q => \cr_reg_n_0_[2]\
+ );
+\cr_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => \cr[3]_i_1_n_0\,
+ Q => ack_in
+ );
+\cr_reg[4]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => byte_ctrl_n_14,
+ CLR => \^wb_rst_o\,
+ D => D(0),
+ Q => write
+ );
+\cr_reg[5]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => byte_ctrl_n_14,
+ CLR => \^wb_rst_o\,
+ D => D(1),
+ Q => read
+ );
+\cr_reg[6]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => byte_ctrl_n_14,
+ CLR => \^wb_rst_o\,
+ D => D(2),
+ Q => stop
+ );
+\cr_reg[7]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => byte_ctrl_n_14,
+ CLR => \^wb_rst_o\,
+ D => D(3),
+ Q => start
+ );
+\ctr[0]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(0),
+ O => ctr(0)
+ );
+\ctr[1]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(1),
+ O => ctr(1)
+ );
+\ctr[2]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(2),
+ O => ctr(2)
+ );
+\ctr[3]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(3),
+ O => ctr(3)
+ );
+\ctr[4]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(4),
+ O => ctr(4)
+ );
+\ctr[5]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(5),
+ O => ctr(5)
+ );
+\ctr[6]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(6),
+ O => ctr(6)
+ );
+\ctr[7]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => s00_axi_wdata(7),
+ O => ctr(7)
+ );
+\ctr_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(0),
+ Q => \ctr_reg_n_0_[0]\
+ );
+\ctr_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(1),
+ Q => \ctr_reg_n_0_[1]\
+ );
+\ctr_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(2),
+ Q => \ctr_reg_n_0_[2]\
+ );
+\ctr_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(3),
+ Q => \ctr_reg_n_0_[3]\
+ );
+\ctr_reg[4]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(4),
+ Q => \ctr_reg_n_0_[4]\
+ );
+\ctr_reg[5]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(5),
+ Q => \ctr_reg_n_0_[5]\
+ );
+\ctr_reg[6]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(6),
+ Q => ien
+ );
+\ctr_reg[7]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(7),
+ Q => \^q\(0)
+ );
+iack_o_reg: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => s_stb_r_reg_0,
+ Q => \^wb_ack_i\,
+ R => '0'
+ );
+\prer[10]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(2),
+ I1 => s00_axi_aresetn,
+ O => \prer[10]_i_1_n_0\
+ );
+\prer[11]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(3),
+ I1 => s00_axi_aresetn,
+ O => \prer[11]_i_1_n_0\
+ );
+\prer[12]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(4),
+ I1 => s00_axi_aresetn,
+ O => \prer[12]_i_1_n_0\
+ );
+\prer[13]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(5),
+ I1 => s00_axi_aresetn,
+ O => \prer[13]_i_1_n_0\
+ );
+\prer[14]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(6),
+ I1 => s00_axi_aresetn,
+ O => \prer[14]_i_1_n_0\
+ );
+\prer[15]_i_2\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(7),
+ I1 => s00_axi_aresetn,
+ O => \prer[15]_i_2_n_0\
+ );
+\prer[8]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(0),
+ I1 => s00_axi_aresetn,
+ O => \prer[8]_i_1_n_0\
+ );
+\prer[9]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"B"
+ )
+ port map (
+ I0 => s00_axi_wdata(1),
+ I1 => s00_axi_aresetn,
+ O => \prer[9]_i_1_n_0\
+ );
+\prer_reg[0]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[8]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => \prer_reg_n_0_[0]\
+ );
+\prer_reg[10]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[10]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(8)
+ );
+\prer_reg[11]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[11]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(9)
+ );
+\prer_reg[12]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[12]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(10)
+ );
+\prer_reg[13]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[13]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(11)
+ );
+\prer_reg[14]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[14]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(12)
+ );
+\prer_reg[15]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[15]_i_2_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(13)
+ );
+\prer_reg[1]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[9]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => \prer_reg_n_0_[1]\
+ );
+\prer_reg[2]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[10]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(0)
+ );
+\prer_reg[3]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[11]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(1)
+ );
+\prer_reg[4]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[12]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(2)
+ );
+\prer_reg[5]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[13]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(3)
+ );
+\prer_reg[6]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[14]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(4)
+ );
+\prer_reg[7]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(0),
+ D => \prer[15]_i_2_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(5)
+ );
+\prer_reg[8]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[8]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(6)
+ );
+\prer_reg[9]\: unisim.vcomponents.FDPE
+ port map (
+ C => s00_axi_aclk,
+ CE => E(1),
+ D => \prer[9]_i_1_n_0\,
+ PRE => \^wb_rst_o\,
+ Q => data0(7)
+ );
+\s_rdata[7]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^wb_ack_i\,
+ I1 => wb_we_o,
+ O => \s_rdata_reg[0]\(0)
+ );
+s_stb_r_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EFEE"
+ )
+ port map (
+ I0 => s00_axi_awvalid,
+ I1 => s00_axi_arvalid,
+ I2 => \^wb_ack_i\,
+ I3 => wb_cyc_o,
+ O => s_stb_r_reg
+ );
+\st_irq_block.al_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => al,
+ Q => \st_irq_block.al_reg_n_0\
+ );
+\st_irq_block.irq_flag_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => irq_flag1_out,
+ Q => irq_flag
+ );
+\st_irq_block.rxack_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => rxack_0,
+ Q => rxack
+ );
+\st_irq_block.tip_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"A8"
+ )
+ port map (
+ I0 => s00_axi_aresetn,
+ I1 => write,
+ I2 => read,
+ O => tip_1
+ );
+\st_irq_block.tip_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => tip_1,
+ Q => tip
+ );
+\st_irq_block.wb_inta_o_i_1\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"80"
+ )
+ port map (
+ I0 => irq_flag,
+ I1 => s00_axi_aresetn,
+ I2 => ien,
+ O => \st_irq_block.wb_inta_o_i_1_n_0\
+ );
+\st_irq_block.wb_inta_o_reg\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ CLR => \^wb_rst_o\,
+ D => \st_irq_block.wb_inta_o_i_1_n_0\,
+ Q => axi_int_o
+ );
+\txr_reg[0]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(0),
+ Q => txr(0)
+ );
+\txr_reg[1]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(1),
+ Q => txr(1)
+ );
+\txr_reg[2]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(2),
+ Q => txr(2)
+ );
+\txr_reg[3]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(3),
+ Q => txr(3)
+ );
+\txr_reg[4]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(4),
+ Q => txr(4)
+ );
+\txr_reg[5]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(5),
+ Q => txr(5)
+ );
+\txr_reg[6]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(6),
+ Q => txr(6)
+ );
+\txr_reg[7]\: unisim.vcomponents.FDCE
+ port map (
+ C => s00_axi_aclk,
+ CE => s_we_r_reg_0(0),
+ CLR => \^wb_rst_o\,
+ D => ctr(7),
+ Q => txr(7)
+ );
+\wb_dat_o[0]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"30BB3088"
+ )
+ port map (
+ I0 => \cr_reg_n_0_[0]\,
+ I1 => wb_adr_o(1),
+ I2 => txr(0),
+ I3 => wb_adr_o(0),
+ I4 => irq_flag,
+ O => \wb_dat_o[0]_i_3_n_0\
+ );
+\wb_dat_o[1]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"30BB3088"
+ )
+ port map (
+ I0 => \cr_reg_n_0_[1]\,
+ I1 => wb_adr_o(1),
+ I2 => txr(1),
+ I3 => wb_adr_o(0),
+ I4 => tip,
+ O => \wb_dat_o[1]_i_3_n_0\
+ );
+\wb_dat_o[5]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"30BB3088"
+ )
+ port map (
+ I0 => read,
+ I1 => wb_adr_o(1),
+ I2 => txr(5),
+ I3 => wb_adr_o(0),
+ I4 => \st_irq_block.al_reg_n_0\,
+ O => \wb_dat_o[5]_i_3_n_0\
+ );
+\wb_dat_o[7]_i_3\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"30BB3088"
+ )
+ port map (
+ I0 => start,
+ I1 => wb_adr_o(1),
+ I2 => txr(7),
+ I3 => wb_adr_o(0),
+ I4 => rxack,
+ O => \wb_dat_o[7]_i_3_n_0\
+ );
+\wb_dat_o_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(0),
+ Q => \s_rdata_reg[7]\(0),
+ R => '0'
+ );
+\wb_dat_o_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(1),
+ Q => \s_rdata_reg[7]\(1),
+ R => '0'
+ );
+\wb_dat_o_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(2),
+ Q => \s_rdata_reg[7]\(2),
+ R => '0'
+ );
+\wb_dat_o_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(3),
+ Q => \s_rdata_reg[7]\(3),
+ R => '0'
+ );
+\wb_dat_o_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(4),
+ Q => \s_rdata_reg[7]\(4),
+ R => '0'
+ );
+\wb_dat_o_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(5),
+ Q => \s_rdata_reg[7]\(5),
+ R => '0'
+ );
+\wb_dat_o_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(6),
+ Q => \s_rdata_reg[7]\(6),
+ R => '0'
+ );
+\wb_dat_o_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s00_axi_aclk,
+ CE => '1',
+ D => wb_dat_o(7),
+ Q => \s_rdata_reg[7]\(7),
+ R => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master is
+ port (
+ i2c_scl_i : in STD_LOGIC;
+ i2c_scl_o : out STD_LOGIC;
+ i2c_scl_t : out STD_LOGIC;
+ i2c_sda_i : in STD_LOGIC;
+ i2c_sda_o : out STD_LOGIC;
+ i2c_sda_t : out STD_LOGIC;
+ axi_int_o : out STD_LOGIC;
+ s00_axi_aclk : in STD_LOGIC;
+ s00_axi_aresetn : in STD_LOGIC;
+ s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_awvalid : in STD_LOGIC;
+ s00_axi_awready : out STD_LOGIC;
+ s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s00_axi_wvalid : in STD_LOGIC;
+ s00_axi_wready : out STD_LOGIC;
+ s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s00_axi_bvalid : out STD_LOGIC;
+ s00_axi_bready : in STD_LOGIC;
+ s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_arvalid : in STD_LOGIC;
+ s00_axi_arready : out STD_LOGIC;
+ s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s00_axi_rvalid : out STD_LOGIC;
+ s00_axi_rready : in STD_LOGIC
+ );
+ attribute C_S00_AXI_ADDR_WIDTH : integer;
+ attribute C_S00_AXI_ADDR_WIDTH of system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master : entity is 32;
+ attribute C_S00_AXI_DATA_WIDTH : integer;
+ attribute C_S00_AXI_DATA_WIDTH of system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master : entity is 32;
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master : entity is "axi_wb_i2c_master";
+end system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master;
+
+architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master is
+ signal \<const0>\ : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_11 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_12 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_13 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_14 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_15 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_16 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_17 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_18 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_19 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_21 : STD_LOGIC;
+ signal cmp_axis_wbm_bridge_n_7 : STD_LOGIC;
+ signal cmp_i2c_master_top_n_6 : STD_LOGIC;
+ signal cmp_i2c_master_top_n_7 : STD_LOGIC;
+ signal ena : STD_LOGIC;
+ signal \^s00_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
+ signal \^s00_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal wb_ack_i : STD_LOGIC;
+ signal wb_adr_o : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal wb_cyc_o : STD_LOGIC;
+ signal wb_dat_o : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal wb_rst_o : STD_LOGIC;
+ signal wb_we_o : STD_LOGIC;
+begin
+ i2c_scl_o <= \<const0>\;
+ i2c_sda_o <= \<const0>\;
+ s00_axi_bresp(1) <= \^s00_axi_bresp\(1);
+ s00_axi_bresp(0) <= \<const0>\;
+ s00_axi_rdata(31) <= \<const0>\;
+ s00_axi_rdata(30) <= \<const0>\;
+ s00_axi_rdata(29) <= \<const0>\;
+ s00_axi_rdata(28) <= \<const0>\;
+ s00_axi_rdata(27) <= \<const0>\;
+ s00_axi_rdata(26) <= \<const0>\;
+ s00_axi_rdata(25) <= \<const0>\;
+ s00_axi_rdata(24) <= \<const0>\;
+ s00_axi_rdata(23) <= \<const0>\;
+ s00_axi_rdata(22) <= \<const0>\;
+ s00_axi_rdata(21) <= \<const0>\;
+ s00_axi_rdata(20) <= \<const0>\;
+ s00_axi_rdata(19) <= \<const0>\;
+ s00_axi_rdata(18) <= \<const0>\;
+ s00_axi_rdata(17) <= \<const0>\;
+ s00_axi_rdata(16) <= \<const0>\;
+ s00_axi_rdata(15) <= \<const0>\;
+ s00_axi_rdata(14) <= \<const0>\;
+ s00_axi_rdata(13) <= \<const0>\;
+ s00_axi_rdata(12) <= \<const0>\;
+ s00_axi_rdata(11) <= \<const0>\;
+ s00_axi_rdata(10) <= \<const0>\;
+ s00_axi_rdata(9) <= \<const0>\;
+ s00_axi_rdata(8) <= \<const0>\;
+ s00_axi_rdata(7 downto 0) <= \^s00_axi_rdata\(7 downto 0);
+ s00_axi_rresp(1) <= \<const0>\;
+ s00_axi_rresp(0) <= \<const0>\;
+GND: unisim.vcomponents.GND
+ port map (
+ G => \<const0>\
+ );
+cmp_axis_wbm_bridge: entity work.system_design_axi_wb_i2c_master_2_0_axis_wbm_bridge
+ port map (
+ D(3) => cmp_axis_wbm_bridge_n_12,
+ D(2) => cmp_axis_wbm_bridge_n_13,
+ D(1) => cmp_axis_wbm_bridge_n_14,
+ D(0) => cmp_axis_wbm_bridge_n_15,
+ E(0) => cmp_axis_wbm_bridge_n_11,
+ Q(0) => ena,
+ \cr_reg[2]\ => cmp_axis_wbm_bridge_n_7,
+ \cr_reg[4]\ => cmp_axis_wbm_bridge_n_16,
+ \ctr_reg[0]\(0) => cmp_axis_wbm_bridge_n_19,
+ iack_o_reg => cmp_axis_wbm_bridge_n_21,
+ iack_o_reg_0 => cmp_i2c_master_top_n_6,
+ iack_o_reg_1(0) => cmp_i2c_master_top_n_7,
+ \prer_reg[8]\(1) => cmp_axis_wbm_bridge_n_17,
+ \prer_reg[8]\(0) => cmp_axis_wbm_bridge_n_18,
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_araddr(2 downto 0) => s00_axi_araddr(4 downto 2),
+ s00_axi_aresetn => s00_axi_aresetn,
+ s00_axi_arready => s00_axi_arready,
+ s00_axi_arvalid => s00_axi_arvalid,
+ s00_axi_awaddr(2 downto 0) => s00_axi_awaddr(4 downto 2),
+ s00_axi_awready => s00_axi_awready,
+ s00_axi_awvalid => s00_axi_awvalid,
+ s00_axi_bready => s00_axi_bready,
+ s00_axi_bresp(0) => \^s00_axi_bresp\(1),
+ s00_axi_bvalid => s00_axi_bvalid,
+ s00_axi_rdata(7 downto 0) => \^s00_axi_rdata\(7 downto 0),
+ s00_axi_rready => s00_axi_rready,
+ s00_axi_rvalid => s00_axi_rvalid,
+ s00_axi_wdata(3 downto 0) => s00_axi_wdata(7 downto 4),
+ s00_axi_wready => s00_axi_wready,
+ s00_axi_wvalid => s00_axi_wvalid,
+ wb_ack_i => wb_ack_i,
+ wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
+ wb_cyc_o => wb_cyc_o,
+ \wb_dat_o_reg[7]\(7 downto 0) => wb_dat_o(7 downto 0),
+ wb_rst_o => wb_rst_o,
+ wb_we_o => wb_we_o
+ );
+cmp_i2c_master_top: entity work.system_design_axi_wb_i2c_master_2_0_i2c_master_top
+ port map (
+ D(3) => cmp_axis_wbm_bridge_n_12,
+ D(2) => cmp_axis_wbm_bridge_n_13,
+ D(1) => cmp_axis_wbm_bridge_n_14,
+ D(0) => cmp_axis_wbm_bridge_n_15,
+ E(1) => cmp_axis_wbm_bridge_n_17,
+ E(0) => cmp_axis_wbm_bridge_n_18,
+ Q(0) => ena,
+ axi_int_o => axi_int_o,
+ i2c_scl_i => i2c_scl_i,
+ i2c_scl_t => i2c_scl_t,
+ i2c_sda_i => i2c_sda_i,
+ i2c_sda_t => i2c_sda_t,
+ iack_o_reg_0 => cmp_axis_wbm_bridge_n_16,
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_aresetn => s00_axi_aresetn,
+ s00_axi_arvalid => s00_axi_arvalid,
+ s00_axi_awvalid => s00_axi_awvalid,
+ s00_axi_wdata(7 downto 0) => s00_axi_wdata(7 downto 0),
+ \s_addr_reg[4]\ => cmp_axis_wbm_bridge_n_7,
+ \s_rdata_reg[0]\(0) => cmp_i2c_master_top_n_7,
+ \s_rdata_reg[7]\(7 downto 0) => wb_dat_o(7 downto 0),
+ s_stb_r_reg => cmp_i2c_master_top_n_6,
+ s_stb_r_reg_0 => cmp_axis_wbm_bridge_n_21,
+ s_we_r_reg(0) => cmp_axis_wbm_bridge_n_19,
+ s_we_r_reg_0(0) => cmp_axis_wbm_bridge_n_11,
+ wb_ack_i => wb_ack_i,
+ wb_adr_o(2 downto 0) => wb_adr_o(2 downto 0),
+ wb_cyc_o => wb_cyc_o,
+ wb_rst_o => wb_rst_o,
+ wb_we_o => wb_we_o
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity system_design_axi_wb_i2c_master_2_0 is
+ port (
+ i2c_scl_i : in STD_LOGIC;
+ i2c_scl_o : out STD_LOGIC;
+ i2c_scl_t : out STD_LOGIC;
+ i2c_sda_i : in STD_LOGIC;
+ i2c_sda_o : out STD_LOGIC;
+ i2c_sda_t : out STD_LOGIC;
+ axi_int_o : out STD_LOGIC;
+ s00_axi_aclk : in STD_LOGIC;
+ s00_axi_aresetn : in STD_LOGIC;
+ s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_awvalid : in STD_LOGIC;
+ s00_axi_awready : out STD_LOGIC;
+ s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s00_axi_wvalid : in STD_LOGIC;
+ s00_axi_wready : out STD_LOGIC;
+ s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s00_axi_bvalid : out STD_LOGIC;
+ s00_axi_bready : in STD_LOGIC;
+ s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s00_axi_arvalid : in STD_LOGIC;
+ s00_axi_arready : out STD_LOGIC;
+ s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s00_axi_rvalid : out STD_LOGIC;
+ s00_axi_rready : in STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of system_design_axi_wb_i2c_master_2_0 : entity is true;
+ attribute CHECK_LICENSE_TYPE : string;
+ attribute CHECK_LICENSE_TYPE of system_design_axi_wb_i2c_master_2_0 : entity is "system_design_axi_wb_i2c_master_2_0,axi_wb_i2c_master,{}";
+ attribute downgradeipidentifiedwarnings : string;
+ attribute downgradeipidentifiedwarnings of system_design_axi_wb_i2c_master_2_0 : entity is "yes";
+ attribute x_core_info : string;
+ attribute x_core_info of system_design_axi_wb_i2c_master_2_0 : entity is "axi_wb_i2c_master,Vivado 2016.2";
+end system_design_axi_wb_i2c_master_2_0;
+
+architecture STRUCTURE of system_design_axi_wb_i2c_master_2_0 is
+ attribute C_S00_AXI_ADDR_WIDTH : integer;
+ attribute C_S00_AXI_ADDR_WIDTH of U0 : label is 32;
+ attribute C_S00_AXI_DATA_WIDTH : integer;
+ attribute C_S00_AXI_DATA_WIDTH of U0 : label is 32;
+begin
+U0: entity work.system_design_axi_wb_i2c_master_2_0_axi_wb_i2c_master
+ port map (
+ axi_int_o => axi_int_o,
+ i2c_scl_i => i2c_scl_i,
+ i2c_scl_o => i2c_scl_o,
+ i2c_scl_t => i2c_scl_t,
+ i2c_sda_i => i2c_sda_i,
+ i2c_sda_o => i2c_sda_o,
+ i2c_sda_t => i2c_sda_t,
+ s00_axi_aclk => s00_axi_aclk,
+ s00_axi_araddr(31 downto 0) => s00_axi_araddr(31 downto 0),
+ s00_axi_aresetn => s00_axi_aresetn,
+ s00_axi_arprot(2 downto 0) => s00_axi_arprot(2 downto 0),
+ s00_axi_arready => s00_axi_arready,
+ s00_axi_arvalid => s00_axi_arvalid,
+ s00_axi_awaddr(31 downto 0) => s00_axi_awaddr(31 downto 0),
+ s00_axi_awprot(2 downto 0) => s00_axi_awprot(2 downto 0),
+ s00_axi_awready => s00_axi_awready,
+ s00_axi_awvalid => s00_axi_awvalid,
+ s00_axi_bready => s00_axi_bready,
+ s00_axi_bresp(1 downto 0) => s00_axi_bresp(1 downto 0),
+ s00_axi_bvalid => s00_axi_bvalid,
+ s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
+ s00_axi_rready => s00_axi_rready,
+ s00_axi_rresp(1 downto 0) => s00_axi_rresp(1 downto 0),
+ s00_axi_rvalid => s00_axi_rvalid,
+ s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
+ s00_axi_wready => s00_axi_wready,
+ s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
+ s00_axi_wvalid => s00_axi_wvalid
+ );
+end STRUCTURE;
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
index e8dbc970..cb35c120 100644
--- a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
--- IP VLNV: user.org:user:fasec_hwtest:3.2.6
--- IP Revision: 34
+-- IP VLNV: user.org:user:fasec_hwtest:3.2.7
+-- IP Revision: 35
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.v b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.v
deleted file mode 100644
index 9e7f05a2..00000000
--- a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.v
+++ /dev/null
@@ -1,88051 +0,0 @@
-// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Oct 11 12:21:16 2017
-// Host : lapte24154 running 64-bit openSUSE Leap 42.2
-// Command : write_verilog -force -mode funcsim
-// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.v
-// Design : system_design_fasec_hwtest_0_0
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z030ffg676-2
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* CHECK_LICENSE_TYPE = "system_design_fasec_hwtest_0_0,fasec_hwtest,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fasec_hwtest,Vivado 2016.2" *)
-(* NotValidForBitStream *)
-module system_design_fasec_hwtest_0_0
- (ps_clk_i,
- osc100_clk_i,
- FMC2_LA_P_b,
- FMC2_LA_N_b,
- FMC1_LA_P_b,
- FMC1_LA_N_b,
- FMC2_PRSNTM2C_n_i,
- FMC2_CLK0M2C_P_i,
- FMC2_CLK0M2C_N_i,
- FMC2_CLK0C2M_P_o,
- FMC2_CLK0C2M_N_o,
- FMC2_GP0_i,
- FMC2_GP1_i,
- FMC2_GP2_i,
- FMC2_GP3_b,
- FMC1_PRSNTM2C_n_i,
- FMC1_CLK0M2C_P_i,
- FMC1_CLK0M2C_N_i,
- FMC1_CLK0C2M_P_o,
- FMC1_CLK0C2M_N_o,
- FMC1_GP0_i,
- FMC1_GP1_i,
- FMC1_GP2_i,
- FMC1_GP3_b,
- pb_gp_n_i,
- led_col_pl_o,
- led_line_en_pl_o,
- led_line_pl_o,
- watchdog_pl_o,
- dig_in1_i,
- dig_in2_i,
- dig_in3_n_i,
- dig_in4_n_i,
- dig_outs_i,
- dig_out5_n,
- dig_out6_n,
- gem_status_vector_i,
- intr_o,
- intr_led_o,
- s00_axi_aclk,
- s00_axi_aresetn,
- s00_axi_awaddr,
- s00_axi_awprot,
- s00_axi_awvalid,
- s00_axi_awready,
- s00_axi_wdata,
- s00_axi_wstrb,
- s00_axi_wvalid,
- s00_axi_wready,
- s00_axi_bresp,
- s00_axi_bvalid,
- s00_axi_bready,
- s00_axi_araddr,
- s00_axi_arprot,
- s00_axi_arvalid,
- s00_axi_arready,
- s00_axi_rdata,
- s00_axi_rresp,
- s00_axi_rvalid,
- s00_axi_rready);
- input ps_clk_i;
- input osc100_clk_i;
- inout [33:0]FMC2_LA_P_b;
- inout [33:0]FMC2_LA_N_b;
- inout [33:0]FMC1_LA_P_b;
- inout [33:0]FMC1_LA_N_b;
- input FMC2_PRSNTM2C_n_i;
- input FMC2_CLK0M2C_P_i;
- input FMC2_CLK0M2C_N_i;
- output FMC2_CLK0C2M_P_o;
- output FMC2_CLK0C2M_N_o;
- input FMC2_GP0_i;
- input FMC2_GP1_i;
- input FMC2_GP2_i;
- inout FMC2_GP3_b;
- input FMC1_PRSNTM2C_n_i;
- input FMC1_CLK0M2C_P_i;
- input FMC1_CLK0M2C_N_i;
- output FMC1_CLK0C2M_P_o;
- output FMC1_CLK0C2M_N_o;
- input FMC1_GP0_i;
- input FMC1_GP1_i;
- input FMC1_GP2_i;
- inout FMC1_GP3_b;
- input pb_gp_n_i;
- output [3:0]led_col_pl_o;
- output led_line_en_pl_o;
- output led_line_pl_o;
- output watchdog_pl_o;
- input dig_in1_i;
- input dig_in2_i;
- input dig_in3_n_i;
- input dig_in4_n_i;
- output [3:0]dig_outs_i;
- output dig_out5_n;
- output dig_out6_n;
- input [15:0]gem_status_vector_i;
- output intr_o;
- output intr_led_o;
- (* x_interface_info = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *) input s00_axi_aclk;
- (* x_interface_info = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *) input s00_axi_aresetn;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s00_axi_awaddr;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s00_axi_awprot;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input s00_axi_awvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output s00_axi_awready;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s00_axi_wdata;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s00_axi_wstrb;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input s00_axi_wvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output s00_axi_wready;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s00_axi_bresp;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output s00_axi_bvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input s00_axi_bready;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s00_axi_araddr;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s00_axi_arprot;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input s00_axi_arvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output s00_axi_arready;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s00_axi_rdata;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s00_axi_rresp;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output s00_axi_rvalid;
- (* x_interface_info = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input s00_axi_rready;
-
- wire FMC1_CLK0C2M_N_o;
- wire FMC1_CLK0C2M_P_o;
- wire FMC1_CLK0M2C_N_i;
- wire FMC1_CLK0M2C_P_i;
- (* SLEW = "FAST" *) wire FMC1_GP0_i;
- (* SLEW = "FAST" *) wire FMC1_GP1_i;
- (* SLEW = "FAST" *) wire FMC1_GP2_i;
- (* SLEW = "FAST" *) wire FMC1_GP3_b;
- wire [33:0]FMC1_LA_N_b;
- wire [33:0]FMC1_LA_P_b;
- wire FMC1_PRSNTM2C_n_i;
- wire FMC2_CLK0C2M_N_o;
- wire FMC2_CLK0C2M_P_o;
- wire FMC2_CLK0M2C_N_i;
- wire FMC2_CLK0M2C_P_i;
- (* SLEW = "FAST" *) wire FMC2_GP0_i;
- (* SLEW = "FAST" *) wire FMC2_GP1_i;
- (* SLEW = "FAST" *) wire FMC2_GP2_i;
- (* SLEW = "FAST" *) wire FMC2_GP3_b;
- wire [33:0]FMC2_LA_N_b;
- wire [33:0]FMC2_LA_P_b;
- wire FMC2_PRSNTM2C_n_i;
- wire dig_in1_i;
- wire dig_in2_i;
- wire dig_in3_n_i;
- wire dig_in4_n_i;
- wire dig_out5_n;
- wire dig_out6_n;
- wire [3:0]dig_outs_i;
- wire [15:0]gem_status_vector_i;
- wire intr_led_o;
- wire intr_o;
- wire [3:0]led_col_pl_o;
- wire led_line_en_pl_o;
- wire led_line_pl_o;
- wire osc100_clk_i;
- wire pb_gp_n_i;
- wire ps_clk_i;
- wire s00_axi_aclk;
- wire [31:0]s00_axi_araddr;
- wire s00_axi_aresetn;
- wire [2:0]s00_axi_arprot;
- wire s00_axi_arready;
- wire s00_axi_arvalid;
- wire [31:0]s00_axi_awaddr;
- wire [2:0]s00_axi_awprot;
- wire s00_axi_awready;
- wire s00_axi_awvalid;
- wire s00_axi_bready;
- wire [1:0]s00_axi_bresp;
- wire s00_axi_bvalid;
- wire [31:0]s00_axi_rdata;
- wire s00_axi_rready;
- wire [1:0]s00_axi_rresp;
- wire s00_axi_rvalid;
- wire [31:0]s00_axi_wdata;
- wire s00_axi_wready;
- wire [3:0]s00_axi_wstrb;
- wire s00_axi_wvalid;
- wire watchdog_pl_o;
-
- (* g_FMC1 = "EDA-03287" *)
- (* g_FMC2 = "EDA-03287" *)
- (* g_S00_AXI_ADDR_WIDTH = "32" *)
- (* g_S00_AXI_DATA_WIDTH = "32" *)
- (* g_USE_GEM_LEDS = "FALSE" *)
- system_design_fasec_hwtest_0_0_fasec_hwtest U0
- (.FMC1_CLK0C2M_N_o(FMC1_CLK0C2M_N_o),
- .FMC1_CLK0C2M_P_o(FMC1_CLK0C2M_P_o),
- .FMC1_CLK0M2C_N_i(FMC1_CLK0M2C_N_i),
- .FMC1_CLK0M2C_P_i(FMC1_CLK0M2C_P_i),
- .FMC1_GP0_i(FMC1_GP0_i),
- .FMC1_GP1_i(FMC1_GP1_i),
- .FMC1_GP2_i(FMC1_GP2_i),
- .FMC1_GP3_b(FMC1_GP3_b),
- .FMC1_LA_N_b(FMC1_LA_N_b),
- .FMC1_LA_P_b(FMC1_LA_P_b),
- .FMC1_PRSNTM2C_n_i(FMC1_PRSNTM2C_n_i),
- .FMC2_CLK0C2M_N_o(FMC2_CLK0C2M_N_o),
- .FMC2_CLK0C2M_P_o(FMC2_CLK0C2M_P_o),
- .FMC2_CLK0M2C_N_i(FMC2_CLK0M2C_N_i),
- .FMC2_CLK0M2C_P_i(FMC2_CLK0M2C_P_i),
- .FMC2_GP0_i(FMC2_GP0_i),
- .FMC2_GP1_i(FMC2_GP1_i),
- .FMC2_GP2_i(FMC2_GP2_i),
- .FMC2_GP3_b(FMC2_GP3_b),
- .FMC2_LA_N_b(FMC2_LA_N_b),
- .FMC2_LA_P_b(FMC2_LA_P_b),
- .FMC2_PRSNTM2C_n_i(FMC2_PRSNTM2C_n_i),
- .dig_in1_i(dig_in1_i),
- .dig_in2_i(dig_in2_i),
- .dig_in3_n_i(dig_in3_n_i),
- .dig_in4_n_i(dig_in4_n_i),
- .dig_out5_n(dig_out5_n),
- .dig_out6_n(dig_out6_n),
- .dig_outs_i(dig_outs_i),
- .gem_status_vector_i(gem_status_vector_i),
- .intr_led_o(intr_led_o),
- .intr_o(intr_o),
- .led_col_pl_o(led_col_pl_o),
- .led_line_en_pl_o(led_line_en_pl_o),
- .led_line_pl_o(led_line_pl_o),
- .osc100_clk_i(osc100_clk_i),
- .pb_gp_n_i(pb_gp_n_i),
- .ps_clk_i(ps_clk_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_araddr(s00_axi_araddr),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s00_axi_arprot(s00_axi_arprot),
- .s00_axi_arready(s00_axi_arready),
- .s00_axi_arvalid(s00_axi_arvalid),
- .s00_axi_awaddr(s00_axi_awaddr),
- .s00_axi_awprot(s00_axi_awprot),
- .s00_axi_awready(s00_axi_awready),
- .s00_axi_awvalid(s00_axi_awvalid),
- .s00_axi_bready(s00_axi_bready),
- .s00_axi_bresp(s00_axi_bresp),
- .s00_axi_bvalid(s00_axi_bvalid),
- .s00_axi_rdata(s00_axi_rdata),
- .s00_axi_rready(s00_axi_rready),
- .s00_axi_rresp(s00_axi_rresp),
- .s00_axi_rvalid(s00_axi_rvalid),
- .s00_axi_wdata(s00_axi_wdata),
- .s00_axi_wready(s00_axi_wready),
- .s00_axi_wstrb(s00_axi_wstrb),
- .s00_axi_wvalid(s00_axi_wvalid),
- .watchdog_pl_o(watchdog_pl_o));
-endmodule
-
-(* ORIG_REF_NAME = "axi4lite_slave" *)
-module system_design_fasec_hwtest_0_0_axi4lite_slave
- (s00_axi_awready,
- s00_axi_wready,
- s00_axi_arready,
- s00_axi_bvalid,
- s00_axi_rvalid,
- Q,
- \[0].[2].s_reqs_reg[2][value][11] ,
- \[0].[1].s_reqs_reg[1][value][11] ,
- \[0].[0].s_reqs_reg[0][value][11] ,
- \[1].[0].s_reqs_reg[4][value][11] ,
- \[1].[1].s_reqs_reg[5][value][11] ,
- \[1].[2].s_reqs_reg[6][value][11] ,
- \[1].[3].s_reqs_reg[7][value][11] ,
- CO,
- \[0].[2].s_reqs_reg[2][changed] ,
- \[0].[1].s_reqs_reg[1][changed] ,
- \[0].[0].s_reqs_reg[0][changed] ,
- \[1].[0].s_reqs_reg[4][changed] ,
- \[1].[1].s_reqs_reg[5][changed] ,
- \[1].[2].s_reqs_reg[6][changed] ,
- \[1].[3].s_reqs_reg[7][changed] ,
- \[0].[3].s_reqs_reg[3][value][11] ,
- \[0].[2].s_reqs_reg[2][value][11]_0 ,
- \[0].[1].s_reqs_reg[1][value][11]_0 ,
- \[0].[0].s_reqs_reg[0][value][11]_0 ,
- \[1].[0].s_reqs_reg[4][value][11]_0 ,
- \[1].[1].s_reqs_reg[5][value][11]_0 ,
- \[1].[2].s_reqs_reg[6][value][11]_0 ,
- \[1].[3].s_reqs_reg[7][value][11]_0 ,
- \[0].[3].s_reqs_reg[3][changed] ,
- \[0].[2].s_reqs_reg[2][changed]_0 ,
- \[0].[1].s_reqs_reg[1][changed]_0 ,
- \[0].[0].s_reqs_reg[0][changed]_0 ,
- \[1].[0].s_reqs_reg[4][changed]_0 ,
- \[1].[1].s_reqs_reg[5][changed]_0 ,
- \[1].[2].s_reqs_reg[6][changed]_0 ,
- \[1].[3].s_reqs_reg[7][changed]_0 ,
- \axi_rdata_reg[23]_0 ,
- \axi_rdata_reg[10]_0 ,
- \axi_rdata_reg[0]_0 ,
- \axi_rdata_reg[2]_0 ,
- \axi_rdata_reg[2]_1 ,
- \[2].[3].s_reqs_reg[11][value][11] ,
- \[2].[2].s_reqs_reg[10][value][11] ,
- \[2].[1].s_reqs_reg[9][value][11] ,
- \[2].[0].s_reqs_reg[8][value][11] ,
- \[3].[3].s_reqs_reg[15][value][11] ,
- \[3].[2].s_reqs_reg[14][value][11] ,
- \[3].[1].s_reqs_reg[13][value][11] ,
- \[3].[0].s_reqs_reg[12][value][11] ,
- \[4].[3].s_reqs_reg[19][value][11] ,
- \[4].[2].s_reqs_reg[18][value][11] ,
- \[4].[1].s_reqs_reg[17][value][11] ,
- \[4].[0].s_reqs_reg[16][value][11] ,
- \[2].[3].s_reqs_reg[11][value][11]_0 ,
- \[2].[2].s_reqs_reg[10][value][11]_0 ,
- \[2].[1].s_reqs_reg[9][value][11]_0 ,
- \[2].[0].s_reqs_reg[8][value][11]_0 ,
- \[3].[3].s_reqs_reg[15][value][11]_0 ,
- \[3].[2].s_reqs_reg[14][value][11]_0 ,
- \[3].[1].s_reqs_reg[13][value][11]_0 ,
- \[3].[0].s_reqs_reg[12][value][11]_0 ,
- \[4].[3].s_reqs_reg[19][value][11]_0 ,
- \[4].[2].s_reqs_reg[18][value][11]_0 ,
- \[4].[1].s_reqs_reg[17][value][11]_0 ,
- \[4].[0].s_reqs_reg[16][value][11]_0 ,
- \axi_rdata_reg[9]_0 ,
- \v_dout_reg[7] ,
- \v_dout_reg[7]_0 ,
- \axi_rdata_reg[7]_0 ,
- \axi_rdata_reg[7]_1 ,
- \axi_rdata_reg[12]_0 ,
- \axi_rdata_reg[12]_1 ,
- \axi_rdata_reg[18]_0 ,
- \axi_rdata_reg[17]_0 ,
- \axi_rdata_reg[17]_1 ,
- \axi_rdata_reg[22]_0 ,
- \axi_rdata_reg[22]_1 ,
- dig_outs_i,
- dig_out6_n,
- \v_dout_reg[7]_1 ,
- \v_dout_reg[6] ,
- \v_dout_reg[5] ,
- \v_dout_reg[4] ,
- \v_dout_reg[7]_2 ,
- \v_dout_reg[6]_0 ,
- \v_dout_reg[5]_0 ,
- \v_dout_reg[4]_0 ,
- s00_axi_bresp,
- s00_axi_rdata,
- s00_axi_rresp,
- rst_i,
- s00_axi_aclk,
- \[0].[3].s_reqs_reg[3][value][11]_0 ,
- \[0].[2].s_reqs_reg[2][value][11]_1 ,
- \[0].[1].s_reqs_reg[1][value][11]_1 ,
- \[0].[0].s_reqs_reg[0][value][11]_1 ,
- \[1].[0].s_reqs_reg[4][value][11]_1 ,
- \[1].[1].s_reqs_reg[5][value][11]_1 ,
- \[1].[2].s_reqs_reg[6][value][11]_1 ,
- \[1].[3].s_reqs_reg[7][value][11]_1 ,
- \[0].[3].s_reqs_reg[3][value][11]_1 ,
- \[0].[2].s_reqs_reg[2][value][11]_2 ,
- \[0].[1].s_reqs_reg[1][value][11]_2 ,
- \[0].[0].s_reqs_reg[0][value][11]_2 ,
- \[1].[0].s_reqs_reg[4][value][11]_2 ,
- \[1].[1].s_reqs_reg[5][value][11]_2 ,
- \[1].[2].s_reqs_reg[6][value][11]_2 ,
- \[1].[3].s_reqs_reg[7][value][11]_2 ,
- s00_axi_wvalid,
- s00_axi_awvalid,
- s00_axi_rready,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][0] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][0] ,
- gem_status_vector_i,
- \s_ins_reg[3] ,
- \data_o_reg[6][0] ,
- \data_o_reg[1][3] ,
- \s_datao_fmc1[0] ,
- \axi_araddr_reg[4]_rep__1_0 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][0]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][0] ,
- \data_o_reg[1][3]_0 ,
- \s_datao_fmc2[0] ,
- \data_o_reg[6][0]_0 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][1] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][1] ,
- \data_o_reg[6][1] ,
- \axi_araddr_reg[4]_rep__0_0 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][1]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][1] ,
- \data_o_reg[6][1]_0 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][2] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][2] ,
- \data_o_reg[6][2] ,
- \axi_araddr_reg[4]_rep__0_1 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][2]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][2] ,
- \data_o_reg[6][2]_0 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][3] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][3] ,
- \data_o_reg[6][3] ,
- \axi_araddr_reg[4]_rep__0_2 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][3]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][3] ,
- \data_o_reg[6][3]_0 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][4] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][4] ,
- \data_o_reg[6][4] ,
- \axi_araddr_reg[4]_rep__0_3 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][4]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][4] ,
- \data_o_reg[6][4]_0 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][5] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][5] ,
- \data_o_reg[6][5] ,
- \axi_araddr_reg[4]_rep__0_4 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][5]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][5] ,
- \data_o_reg[6][5]_0 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][6] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][6] ,
- \data_o_reg[6][6] ,
- \axi_araddr_reg[4]_rep__0_5 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][6]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][6] ,
- \data_o_reg[6][6]_0 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][7] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][7] ,
- \data_o_reg[6][7] ,
- \axi_araddr_reg[4]_rep__0_6 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][7]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][7] ,
- \data_o_reg[6][7]_0 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][8] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][8] ,
- \s_datao_fmc1[4] ,
- \axi_araddr_reg[4]_rep__0_7 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][8]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][8] ,
- \s_datao_fmc2[4] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][9] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][9] ,
- \axi_araddr_reg[4]_rep__0_8 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][9]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][9] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][10] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][10] ,
- \axi_araddr_reg[4]_rep_0 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][10]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][10] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][11] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][11] ,
- \axi_araddr_reg[4]_rep_1 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][11]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][11] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][12] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][12] ,
- \axi_araddr_reg[4]_rep_2 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][12]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][12] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][13] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][13] ,
- \axi_araddr_reg[4]_rep_3 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][13]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][13] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][14] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][14] ,
- \axi_araddr_reg[4]_rep_4 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][14]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][14] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][15] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][15] ,
- \axi_araddr_reg[4]_rep_5 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][15]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][15] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][16] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][16] ,
- \axi_araddr_reg[4]_rep_6 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][16]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][16] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][17] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][17] ,
- \axi_araddr_reg[4]_rep_7 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][17]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][17] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][18] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][18] ,
- \axi_araddr_reg[4]_rep_8 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][18]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][18] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][19] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][19] ,
- \axi_araddr_reg[4]_0 ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][19]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][19] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][20] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][20] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][20]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][20] ,
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][20] ,
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][20] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][21] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][21] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][21]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][21] ,
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][21] ,
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][21] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][22] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][22] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][22]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][22] ,
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][22] ,
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][22] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][23] ,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][23] ,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]_0 ,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][23] ,
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][23] ,
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][23] ,
- \dac_ch_o_reg[0][31] ,
- s00_axi_bready,
- s00_axi_arvalid,
- s_tick,
- \axi_araddr_reg[4]_1 ,
- \axi_araddr_reg[4]_2 ,
- \axi_araddr_reg[4]_3 ,
- \axi_araddr_reg[4]_4 ,
- \axi_araddr_reg[4]_5 ,
- \axi_araddr_reg[4]_6 ,
- \axi_araddr_reg[4]_7 ,
- \axi_araddr_reg[4]_8 ,
- \axi_araddr_reg[5]_0 ,
- \axi_araddr_reg[5]_1 ,
- \axi_araddr_reg[5]_2 ,
- \axi_araddr_reg[5]_3 ,
- \axi_araddr_reg[5]_4 ,
- \axi_araddr_reg[5]_5 ,
- \axi_araddr_reg[5]_6 ,
- \axi_araddr_reg[5]_7 ,
- \axi_araddr_reg[5]_8 ,
- \axi_araddr_reg[5]_rep_0 ,
- \axi_araddr_reg[5]_rep_1 ,
- \axi_araddr_reg[5]_rep_2 ,
- \axi_araddr_reg[5]_rep_3 ,
- \axi_araddr_reg[5]_rep_4 ,
- \axi_araddr_reg[5]_rep_5 ,
- \axi_araddr_reg[5]_rep_6 ,
- \axi_araddr_reg[5]_rep_7 ,
- \axi_araddr_reg[5]_rep_8 ,
- \axi_araddr_reg[5]_rep_9 ,
- \axi_araddr_reg[5]_rep_10 ,
- \dac_ch_o_reg[0][31]_0 ,
- s00_axi_wstrb,
- s00_axi_awaddr,
- s00_axi_wdata,
- s00_axi_aresetn,
- s00_axi_araddr);
- output s00_axi_awready;
- output s00_axi_wready;
- output s00_axi_arready;
- output s00_axi_bvalid;
- output s00_axi_rvalid;
- output [11:0]Q;
- output [11:0]\[0].[2].s_reqs_reg[2][value][11] ;
- output [11:0]\[0].[1].s_reqs_reg[1][value][11] ;
- output [11:0]\[0].[0].s_reqs_reg[0][value][11] ;
- output [11:0]\[1].[0].s_reqs_reg[4][value][11] ;
- output [11:0]\[1].[1].s_reqs_reg[5][value][11] ;
- output [11:0]\[1].[2].s_reqs_reg[6][value][11] ;
- output [11:0]\[1].[3].s_reqs_reg[7][value][11] ;
- output [0:0]CO;
- output [0:0]\[0].[2].s_reqs_reg[2][changed] ;
- output [0:0]\[0].[1].s_reqs_reg[1][changed] ;
- output [0:0]\[0].[0].s_reqs_reg[0][changed] ;
- output [0:0]\[1].[0].s_reqs_reg[4][changed] ;
- output [0:0]\[1].[1].s_reqs_reg[5][changed] ;
- output [0:0]\[1].[2].s_reqs_reg[6][changed] ;
- output [0:0]\[1].[3].s_reqs_reg[7][changed] ;
- output [11:0]\[0].[3].s_reqs_reg[3][value][11] ;
- output [11:0]\[0].[2].s_reqs_reg[2][value][11]_0 ;
- output [11:0]\[0].[1].s_reqs_reg[1][value][11]_0 ;
- output [11:0]\[0].[0].s_reqs_reg[0][value][11]_0 ;
- output [11:0]\[1].[0].s_reqs_reg[4][value][11]_0 ;
- output [11:0]\[1].[1].s_reqs_reg[5][value][11]_0 ;
- output [11:0]\[1].[2].s_reqs_reg[6][value][11]_0 ;
- output [11:0]\[1].[3].s_reqs_reg[7][value][11]_0 ;
- output [0:0]\[0].[3].s_reqs_reg[3][changed] ;
- output [0:0]\[0].[2].s_reqs_reg[2][changed]_0 ;
- output [0:0]\[0].[1].s_reqs_reg[1][changed]_0 ;
- output [0:0]\[0].[0].s_reqs_reg[0][changed]_0 ;
- output [0:0]\[1].[0].s_reqs_reg[4][changed]_0 ;
- output [0:0]\[1].[1].s_reqs_reg[5][changed]_0 ;
- output [0:0]\[1].[2].s_reqs_reg[6][changed]_0 ;
- output [0:0]\[1].[3].s_reqs_reg[7][changed]_0 ;
- output [3:0]\axi_rdata_reg[23]_0 ;
- output \axi_rdata_reg[10]_0 ;
- output \axi_rdata_reg[0]_0 ;
- output \axi_rdata_reg[2]_0 ;
- output \axi_rdata_reg[2]_1 ;
- output [11:0]\[2].[3].s_reqs_reg[11][value][11] ;
- output [11:0]\[2].[2].s_reqs_reg[10][value][11] ;
- output [11:0]\[2].[1].s_reqs_reg[9][value][11] ;
- output [11:0]\[2].[0].s_reqs_reg[8][value][11] ;
- output [11:0]\[3].[3].s_reqs_reg[15][value][11] ;
- output [11:0]\[3].[2].s_reqs_reg[14][value][11] ;
- output [11:0]\[3].[1].s_reqs_reg[13][value][11] ;
- output [11:0]\[3].[0].s_reqs_reg[12][value][11] ;
- output [11:0]\[4].[3].s_reqs_reg[19][value][11] ;
- output [11:0]\[4].[2].s_reqs_reg[18][value][11] ;
- output [11:0]\[4].[1].s_reqs_reg[17][value][11] ;
- output [11:0]\[4].[0].s_reqs_reg[16][value][11] ;
- output [11:0]\[2].[3].s_reqs_reg[11][value][11]_0 ;
- output [11:0]\[2].[2].s_reqs_reg[10][value][11]_0 ;
- output [11:0]\[2].[1].s_reqs_reg[9][value][11]_0 ;
- output [11:0]\[2].[0].s_reqs_reg[8][value][11]_0 ;
- output [11:0]\[3].[3].s_reqs_reg[15][value][11]_0 ;
- output [11:0]\[3].[2].s_reqs_reg[14][value][11]_0 ;
- output [11:0]\[3].[1].s_reqs_reg[13][value][11]_0 ;
- output [11:0]\[3].[0].s_reqs_reg[12][value][11]_0 ;
- output [11:0]\[4].[3].s_reqs_reg[19][value][11]_0 ;
- output [11:0]\[4].[2].s_reqs_reg[18][value][11]_0 ;
- output [11:0]\[4].[1].s_reqs_reg[17][value][11]_0 ;
- output [11:0]\[4].[0].s_reqs_reg[16][value][11]_0 ;
- output \axi_rdata_reg[9]_0 ;
- output [2:0]\v_dout_reg[7] ;
- output [2:0]\v_dout_reg[7]_0 ;
- output \axi_rdata_reg[7]_0 ;
- output \axi_rdata_reg[7]_1 ;
- output \axi_rdata_reg[12]_0 ;
- output \axi_rdata_reg[12]_1 ;
- output \axi_rdata_reg[18]_0 ;
- output \axi_rdata_reg[17]_0 ;
- output \axi_rdata_reg[17]_1 ;
- output \axi_rdata_reg[22]_0 ;
- output \axi_rdata_reg[22]_1 ;
- output [0:0]dig_outs_i;
- output dig_out6_n;
- output \v_dout_reg[7]_1 ;
- output \v_dout_reg[6] ;
- output \v_dout_reg[5] ;
- output \v_dout_reg[4] ;
- output \v_dout_reg[7]_2 ;
- output \v_dout_reg[6]_0 ;
- output \v_dout_reg[5]_0 ;
- output \v_dout_reg[4]_0 ;
- output [0:0]s00_axi_bresp;
- output [31:0]s00_axi_rdata;
- output [0:0]s00_axi_rresp;
- input rst_i;
- input s00_axi_aclk;
- input [11:0]\[0].[3].s_reqs_reg[3][value][11]_0 ;
- input [11:0]\[0].[2].s_reqs_reg[2][value][11]_1 ;
- input [11:0]\[0].[1].s_reqs_reg[1][value][11]_1 ;
- input [11:0]\[0].[0].s_reqs_reg[0][value][11]_1 ;
- input [11:0]\[1].[0].s_reqs_reg[4][value][11]_1 ;
- input [11:0]\[1].[1].s_reqs_reg[5][value][11]_1 ;
- input [11:0]\[1].[2].s_reqs_reg[6][value][11]_1 ;
- input [11:0]\[1].[3].s_reqs_reg[7][value][11]_1 ;
- input [11:0]\[0].[3].s_reqs_reg[3][value][11]_1 ;
- input [11:0]\[0].[2].s_reqs_reg[2][value][11]_2 ;
- input [11:0]\[0].[1].s_reqs_reg[1][value][11]_2 ;
- input [11:0]\[0].[0].s_reqs_reg[0][value][11]_2 ;
- input [11:0]\[1].[0].s_reqs_reg[4][value][11]_2 ;
- input [11:0]\[1].[1].s_reqs_reg[5][value][11]_2 ;
- input [11:0]\[1].[2].s_reqs_reg[6][value][11]_2 ;
- input [11:0]\[1].[3].s_reqs_reg[7][value][11]_2 ;
- input s00_axi_wvalid;
- input s00_axi_awvalid;
- input s00_axi_rready;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][0] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][0] ;
- input [15:0]gem_status_vector_i;
- input [3:0]\s_ins_reg[3] ;
- input \data_o_reg[6][0] ;
- input [3:0]\data_o_reg[1][3] ;
- input [19:0]\s_datao_fmc1[0] ;
- input \axi_araddr_reg[4]_rep__1_0 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][0]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][0] ;
- input [3:0]\data_o_reg[1][3]_0 ;
- input [19:0]\s_datao_fmc2[0] ;
- input \data_o_reg[6][0]_0 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][1] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][1] ;
- input \data_o_reg[6][1] ;
- input \axi_araddr_reg[4]_rep__0_0 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][1]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][1] ;
- input \data_o_reg[6][1]_0 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][2] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][2] ;
- input \data_o_reg[6][2] ;
- input \axi_araddr_reg[4]_rep__0_1 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][2]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][2] ;
- input \data_o_reg[6][2]_0 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][3] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][3] ;
- input \data_o_reg[6][3] ;
- input \axi_araddr_reg[4]_rep__0_2 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][3]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][3] ;
- input \data_o_reg[6][3]_0 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][4] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][4] ;
- input \data_o_reg[6][4] ;
- input \axi_araddr_reg[4]_rep__0_3 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][4]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][4] ;
- input \data_o_reg[6][4]_0 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][5] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][5] ;
- input \data_o_reg[6][5] ;
- input \axi_araddr_reg[4]_rep__0_4 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][5]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][5] ;
- input \data_o_reg[6][5]_0 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][6] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][6] ;
- input \data_o_reg[6][6] ;
- input \axi_araddr_reg[4]_rep__0_5 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][6]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][6] ;
- input \data_o_reg[6][6]_0 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][7] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][7] ;
- input \data_o_reg[6][7] ;
- input \axi_araddr_reg[4]_rep__0_6 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][7]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][7] ;
- input \data_o_reg[6][7]_0 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][8] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][8] ;
- input [11:0]\s_datao_fmc1[4] ;
- input \axi_araddr_reg[4]_rep__0_7 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][8]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][8] ;
- input [11:0]\s_datao_fmc2[4] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][9] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][9] ;
- input \axi_araddr_reg[4]_rep__0_8 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][9]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][9] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][10] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][10] ;
- input \axi_araddr_reg[4]_rep_0 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][10]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][10] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][11] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][11] ;
- input \axi_araddr_reg[4]_rep_1 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][11]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][11] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][12] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][12] ;
- input \axi_araddr_reg[4]_rep_2 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][12]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][12] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][13] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][13] ;
- input \axi_araddr_reg[4]_rep_3 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][13]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][13] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][14] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][14] ;
- input \axi_araddr_reg[4]_rep_4 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][14]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][14] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][15] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][15] ;
- input \axi_araddr_reg[4]_rep_5 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][15]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][15] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][16] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][16] ;
- input \axi_araddr_reg[4]_rep_6 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][16]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][16] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][17] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][17] ;
- input \axi_araddr_reg[4]_rep_7 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][17]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][17] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][18] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][18] ;
- input \axi_araddr_reg[4]_rep_8 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][18]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][18] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][19] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][19] ;
- input \axi_araddr_reg[4]_0 ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][19]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][19] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][20] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][20] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][20]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][20] ;
- input \fmc_03287_channels[15].gen_chs.data_o_reg[63][20] ;
- input \fmc_03287_channels[11].gen_chs.data_o_reg[59][20] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][21] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][21] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][21]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][21] ;
- input \fmc_03287_channels[15].gen_chs.data_o_reg[63][21] ;
- input \fmc_03287_channels[11].gen_chs.data_o_reg[59][21] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][22] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][22] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][22]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][22] ;
- input \fmc_03287_channels[15].gen_chs.data_o_reg[63][22] ;
- input \fmc_03287_channels[11].gen_chs.data_o_reg[59][22] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][23] ;
- input \fmc_03287_channels[7].gen_chs.data_o_reg[55][23] ;
- input \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]_0 ;
- input \fmc_03287_channels[19].gen_chs.data_o_reg[67][23] ;
- input \fmc_03287_channels[15].gen_chs.data_o_reg[63][23] ;
- input \fmc_03287_channels[11].gen_chs.data_o_reg[59][23] ;
- input [31:0]\dac_ch_o_reg[0][31] ;
- input s00_axi_bready;
- input s00_axi_arvalid;
- input s_tick;
- input \axi_araddr_reg[4]_1 ;
- input \axi_araddr_reg[4]_2 ;
- input \axi_araddr_reg[4]_3 ;
- input \axi_araddr_reg[4]_4 ;
- input \axi_araddr_reg[4]_5 ;
- input \axi_araddr_reg[4]_6 ;
- input \axi_araddr_reg[4]_7 ;
- input \axi_araddr_reg[4]_8 ;
- input \axi_araddr_reg[5]_0 ;
- input \axi_araddr_reg[5]_1 ;
- input \axi_araddr_reg[5]_2 ;
- input \axi_araddr_reg[5]_3 ;
- input \axi_araddr_reg[5]_4 ;
- input \axi_araddr_reg[5]_5 ;
- input \axi_araddr_reg[5]_6 ;
- input \axi_araddr_reg[5]_7 ;
- input \axi_araddr_reg[5]_8 ;
- input \axi_araddr_reg[5]_rep_0 ;
- input \axi_araddr_reg[5]_rep_1 ;
- input \axi_araddr_reg[5]_rep_2 ;
- input \axi_araddr_reg[5]_rep_3 ;
- input \axi_araddr_reg[5]_rep_4 ;
- input \axi_araddr_reg[5]_rep_5 ;
- input \axi_araddr_reg[5]_rep_6 ;
- input \axi_araddr_reg[5]_rep_7 ;
- input \axi_araddr_reg[5]_rep_8 ;
- input \axi_araddr_reg[5]_rep_9 ;
- input \axi_araddr_reg[5]_rep_10 ;
- input [31:0]\dac_ch_o_reg[0][31]_0 ;
- input [3:0]s00_axi_wstrb;
- input [7:0]s00_axi_awaddr;
- input [31:0]s00_axi_wdata;
- input s00_axi_aresetn;
- input [8:0]s00_axi_araddr;
-
- wire [0:0]CO;
- wire [11:0]Q;
- wire \[0].[0].s_reqs[0][changed]_i_3__0_n_0 ;
- wire \[0].[0].s_reqs[0][changed]_i_3_n_0 ;
- wire \[0].[0].s_reqs[0][changed]_i_4__0_n_0 ;
- wire \[0].[0].s_reqs[0][changed]_i_4_n_0 ;
- wire \[0].[0].s_reqs[0][changed]_i_5__0_n_0 ;
- wire \[0].[0].s_reqs[0][changed]_i_5_n_0 ;
- wire \[0].[0].s_reqs[0][changed]_i_6__0_n_0 ;
- wire \[0].[0].s_reqs[0][changed]_i_6_n_0 ;
- wire [0:0]\[0].[0].s_reqs_reg[0][changed] ;
- wire [0:0]\[0].[0].s_reqs_reg[0][changed]_0 ;
- wire \[0].[0].s_reqs_reg[0][changed]_i_2__0_n_1 ;
- wire \[0].[0].s_reqs_reg[0][changed]_i_2__0_n_2 ;
- wire \[0].[0].s_reqs_reg[0][changed]_i_2__0_n_3 ;
- wire \[0].[0].s_reqs_reg[0][changed]_i_2_n_1 ;
- wire \[0].[0].s_reqs_reg[0][changed]_i_2_n_2 ;
- wire \[0].[0].s_reqs_reg[0][changed]_i_2_n_3 ;
- wire [11:0]\[0].[0].s_reqs_reg[0][value][11] ;
- wire [11:0]\[0].[0].s_reqs_reg[0][value][11]_0 ;
- wire [11:0]\[0].[0].s_reqs_reg[0][value][11]_1 ;
- wire [11:0]\[0].[0].s_reqs_reg[0][value][11]_2 ;
- wire \[0].[1].s_reqs[1][changed]_i_3__0_n_0 ;
- wire \[0].[1].s_reqs[1][changed]_i_3_n_0 ;
- wire \[0].[1].s_reqs[1][changed]_i_4__0_n_0 ;
- wire \[0].[1].s_reqs[1][changed]_i_4_n_0 ;
- wire \[0].[1].s_reqs[1][changed]_i_5__0_n_0 ;
- wire \[0].[1].s_reqs[1][changed]_i_5_n_0 ;
- wire \[0].[1].s_reqs[1][changed]_i_6__0_n_0 ;
- wire \[0].[1].s_reqs[1][changed]_i_6_n_0 ;
- wire [0:0]\[0].[1].s_reqs_reg[1][changed] ;
- wire [0:0]\[0].[1].s_reqs_reg[1][changed]_0 ;
- wire \[0].[1].s_reqs_reg[1][changed]_i_2__0_n_1 ;
- wire \[0].[1].s_reqs_reg[1][changed]_i_2__0_n_2 ;
- wire \[0].[1].s_reqs_reg[1][changed]_i_2__0_n_3 ;
- wire \[0].[1].s_reqs_reg[1][changed]_i_2_n_1 ;
- wire \[0].[1].s_reqs_reg[1][changed]_i_2_n_2 ;
- wire \[0].[1].s_reqs_reg[1][changed]_i_2_n_3 ;
- wire [11:0]\[0].[1].s_reqs_reg[1][value][11] ;
- wire [11:0]\[0].[1].s_reqs_reg[1][value][11]_0 ;
- wire [11:0]\[0].[1].s_reqs_reg[1][value][11]_1 ;
- wire [11:0]\[0].[1].s_reqs_reg[1][value][11]_2 ;
- wire \[0].[2].s_reqs[2][changed]_i_3__0_n_0 ;
- wire \[0].[2].s_reqs[2][changed]_i_3_n_0 ;
- wire \[0].[2].s_reqs[2][changed]_i_4__0_n_0 ;
- wire \[0].[2].s_reqs[2][changed]_i_4_n_0 ;
- wire \[0].[2].s_reqs[2][changed]_i_5__0_n_0 ;
- wire \[0].[2].s_reqs[2][changed]_i_5_n_0 ;
- wire \[0].[2].s_reqs[2][changed]_i_6__0_n_0 ;
- wire \[0].[2].s_reqs[2][changed]_i_6_n_0 ;
- wire [0:0]\[0].[2].s_reqs_reg[2][changed] ;
- wire [0:0]\[0].[2].s_reqs_reg[2][changed]_0 ;
- wire \[0].[2].s_reqs_reg[2][changed]_i_2__0_n_1 ;
- wire \[0].[2].s_reqs_reg[2][changed]_i_2__0_n_2 ;
- wire \[0].[2].s_reqs_reg[2][changed]_i_2__0_n_3 ;
- wire \[0].[2].s_reqs_reg[2][changed]_i_2_n_1 ;
- wire \[0].[2].s_reqs_reg[2][changed]_i_2_n_2 ;
- wire \[0].[2].s_reqs_reg[2][changed]_i_2_n_3 ;
- wire [11:0]\[0].[2].s_reqs_reg[2][value][11] ;
- wire [11:0]\[0].[2].s_reqs_reg[2][value][11]_0 ;
- wire [11:0]\[0].[2].s_reqs_reg[2][value][11]_1 ;
- wire [11:0]\[0].[2].s_reqs_reg[2][value][11]_2 ;
- wire \[0].[3].s_reqs[3][changed]_i_3__0_n_0 ;
- wire \[0].[3].s_reqs[3][changed]_i_3_n_0 ;
- wire \[0].[3].s_reqs[3][changed]_i_4__0_n_0 ;
- wire \[0].[3].s_reqs[3][changed]_i_4_n_0 ;
- wire \[0].[3].s_reqs[3][changed]_i_5__0_n_0 ;
- wire \[0].[3].s_reqs[3][changed]_i_5_n_0 ;
- wire \[0].[3].s_reqs[3][changed]_i_6__0_n_0 ;
- wire \[0].[3].s_reqs[3][changed]_i_6_n_0 ;
- wire [0:0]\[0].[3].s_reqs_reg[3][changed] ;
- wire \[0].[3].s_reqs_reg[3][changed]_i_2__0_n_1 ;
- wire \[0].[3].s_reqs_reg[3][changed]_i_2__0_n_2 ;
- wire \[0].[3].s_reqs_reg[3][changed]_i_2__0_n_3 ;
- wire \[0].[3].s_reqs_reg[3][changed]_i_2_n_1 ;
- wire \[0].[3].s_reqs_reg[3][changed]_i_2_n_2 ;
- wire \[0].[3].s_reqs_reg[3][changed]_i_2_n_3 ;
- wire [11:0]\[0].[3].s_reqs_reg[3][value][11] ;
- wire [11:0]\[0].[3].s_reqs_reg[3][value][11]_0 ;
- wire [11:0]\[0].[3].s_reqs_reg[3][value][11]_1 ;
- wire \[1].[0].s_reqs[4][changed]_i_3__0_n_0 ;
- wire \[1].[0].s_reqs[4][changed]_i_3_n_0 ;
- wire \[1].[0].s_reqs[4][changed]_i_4__0_n_0 ;
- wire \[1].[0].s_reqs[4][changed]_i_4_n_0 ;
- wire \[1].[0].s_reqs[4][changed]_i_5__0_n_0 ;
- wire \[1].[0].s_reqs[4][changed]_i_5_n_0 ;
- wire \[1].[0].s_reqs[4][changed]_i_6__0_n_0 ;
- wire \[1].[0].s_reqs[4][changed]_i_6_n_0 ;
- wire [0:0]\[1].[0].s_reqs_reg[4][changed] ;
- wire [0:0]\[1].[0].s_reqs_reg[4][changed]_0 ;
- wire \[1].[0].s_reqs_reg[4][changed]_i_2__0_n_1 ;
- wire \[1].[0].s_reqs_reg[4][changed]_i_2__0_n_2 ;
- wire \[1].[0].s_reqs_reg[4][changed]_i_2__0_n_3 ;
- wire \[1].[0].s_reqs_reg[4][changed]_i_2_n_1 ;
- wire \[1].[0].s_reqs_reg[4][changed]_i_2_n_2 ;
- wire \[1].[0].s_reqs_reg[4][changed]_i_2_n_3 ;
- wire [11:0]\[1].[0].s_reqs_reg[4][value][11] ;
- wire [11:0]\[1].[0].s_reqs_reg[4][value][11]_0 ;
- wire [11:0]\[1].[0].s_reqs_reg[4][value][11]_1 ;
- wire [11:0]\[1].[0].s_reqs_reg[4][value][11]_2 ;
- wire \[1].[1].s_reqs[5][changed]_i_3__0_n_0 ;
- wire \[1].[1].s_reqs[5][changed]_i_3_n_0 ;
- wire \[1].[1].s_reqs[5][changed]_i_4__0_n_0 ;
- wire \[1].[1].s_reqs[5][changed]_i_4_n_0 ;
- wire \[1].[1].s_reqs[5][changed]_i_5__0_n_0 ;
- wire \[1].[1].s_reqs[5][changed]_i_5_n_0 ;
- wire \[1].[1].s_reqs[5][changed]_i_6__0_n_0 ;
- wire \[1].[1].s_reqs[5][changed]_i_6_n_0 ;
- wire [0:0]\[1].[1].s_reqs_reg[5][changed] ;
- wire [0:0]\[1].[1].s_reqs_reg[5][changed]_0 ;
- wire \[1].[1].s_reqs_reg[5][changed]_i_2__0_n_1 ;
- wire \[1].[1].s_reqs_reg[5][changed]_i_2__0_n_2 ;
- wire \[1].[1].s_reqs_reg[5][changed]_i_2__0_n_3 ;
- wire \[1].[1].s_reqs_reg[5][changed]_i_2_n_1 ;
- wire \[1].[1].s_reqs_reg[5][changed]_i_2_n_2 ;
- wire \[1].[1].s_reqs_reg[5][changed]_i_2_n_3 ;
- wire [11:0]\[1].[1].s_reqs_reg[5][value][11] ;
- wire [11:0]\[1].[1].s_reqs_reg[5][value][11]_0 ;
- wire [11:0]\[1].[1].s_reqs_reg[5][value][11]_1 ;
- wire [11:0]\[1].[1].s_reqs_reg[5][value][11]_2 ;
- wire \[1].[2].s_reqs[6][changed]_i_3__0_n_0 ;
- wire \[1].[2].s_reqs[6][changed]_i_3_n_0 ;
- wire \[1].[2].s_reqs[6][changed]_i_4__0_n_0 ;
- wire \[1].[2].s_reqs[6][changed]_i_4_n_0 ;
- wire \[1].[2].s_reqs[6][changed]_i_5__0_n_0 ;
- wire \[1].[2].s_reqs[6][changed]_i_5_n_0 ;
- wire \[1].[2].s_reqs[6][changed]_i_6__0_n_0 ;
- wire \[1].[2].s_reqs[6][changed]_i_6_n_0 ;
- wire [0:0]\[1].[2].s_reqs_reg[6][changed] ;
- wire [0:0]\[1].[2].s_reqs_reg[6][changed]_0 ;
- wire \[1].[2].s_reqs_reg[6][changed]_i_2__0_n_1 ;
- wire \[1].[2].s_reqs_reg[6][changed]_i_2__0_n_2 ;
- wire \[1].[2].s_reqs_reg[6][changed]_i_2__0_n_3 ;
- wire \[1].[2].s_reqs_reg[6][changed]_i_2_n_1 ;
- wire \[1].[2].s_reqs_reg[6][changed]_i_2_n_2 ;
- wire \[1].[2].s_reqs_reg[6][changed]_i_2_n_3 ;
- wire [11:0]\[1].[2].s_reqs_reg[6][value][11] ;
- wire [11:0]\[1].[2].s_reqs_reg[6][value][11]_0 ;
- wire [11:0]\[1].[2].s_reqs_reg[6][value][11]_1 ;
- wire [11:0]\[1].[2].s_reqs_reg[6][value][11]_2 ;
- wire \[1].[3].s_reqs[7][changed]_i_3__0_n_0 ;
- wire \[1].[3].s_reqs[7][changed]_i_3_n_0 ;
- wire \[1].[3].s_reqs[7][changed]_i_4__0_n_0 ;
- wire \[1].[3].s_reqs[7][changed]_i_4_n_0 ;
- wire \[1].[3].s_reqs[7][changed]_i_5__0_n_0 ;
- wire \[1].[3].s_reqs[7][changed]_i_5_n_0 ;
- wire \[1].[3].s_reqs[7][changed]_i_6__0_n_0 ;
- wire \[1].[3].s_reqs[7][changed]_i_6_n_0 ;
- wire [0:0]\[1].[3].s_reqs_reg[7][changed] ;
- wire [0:0]\[1].[3].s_reqs_reg[7][changed]_0 ;
- wire \[1].[3].s_reqs_reg[7][changed]_i_2__0_n_1 ;
- wire \[1].[3].s_reqs_reg[7][changed]_i_2__0_n_2 ;
- wire \[1].[3].s_reqs_reg[7][changed]_i_2__0_n_3 ;
- wire \[1].[3].s_reqs_reg[7][changed]_i_2_n_1 ;
- wire \[1].[3].s_reqs_reg[7][changed]_i_2_n_2 ;
- wire \[1].[3].s_reqs_reg[7][changed]_i_2_n_3 ;
- wire [11:0]\[1].[3].s_reqs_reg[7][value][11] ;
- wire [11:0]\[1].[3].s_reqs_reg[7][value][11]_0 ;
- wire [11:0]\[1].[3].s_reqs_reg[7][value][11]_1 ;
- wire [11:0]\[1].[3].s_reqs_reg[7][value][11]_2 ;
- wire [11:0]\[2].[0].s_reqs_reg[8][value][11] ;
- wire [11:0]\[2].[0].s_reqs_reg[8][value][11]_0 ;
- wire [11:0]\[2].[1].s_reqs_reg[9][value][11] ;
- wire [11:0]\[2].[1].s_reqs_reg[9][value][11]_0 ;
- wire [11:0]\[2].[2].s_reqs_reg[10][value][11] ;
- wire [11:0]\[2].[2].s_reqs_reg[10][value][11]_0 ;
- wire [11:0]\[2].[3].s_reqs_reg[11][value][11] ;
- wire [11:0]\[2].[3].s_reqs_reg[11][value][11]_0 ;
- wire [11:0]\[3].[0].s_reqs_reg[12][value][11] ;
- wire [11:0]\[3].[0].s_reqs_reg[12][value][11]_0 ;
- wire [11:0]\[3].[1].s_reqs_reg[13][value][11] ;
- wire [11:0]\[3].[1].s_reqs_reg[13][value][11]_0 ;
- wire [11:0]\[3].[2].s_reqs_reg[14][value][11] ;
- wire [11:0]\[3].[2].s_reqs_reg[14][value][11]_0 ;
- wire [11:0]\[3].[3].s_reqs_reg[15][value][11] ;
- wire [11:0]\[3].[3].s_reqs_reg[15][value][11]_0 ;
- wire [11:0]\[4].[0].s_reqs_reg[16][value][11] ;
- wire [11:0]\[4].[0].s_reqs_reg[16][value][11]_0 ;
- wire [11:0]\[4].[1].s_reqs_reg[17][value][11] ;
- wire [11:0]\[4].[1].s_reqs_reg[17][value][11]_0 ;
- wire [11:0]\[4].[2].s_reqs_reg[18][value][11] ;
- wire [11:0]\[4].[2].s_reqs_reg[18][value][11]_0 ;
- wire [11:0]\[4].[3].s_reqs_reg[19][value][11] ;
- wire [11:0]\[4].[3].s_reqs_reg[19][value][11]_0 ;
- wire [10:6]axi_araddr;
- wire \axi_araddr_reg[4]_0 ;
- wire \axi_araddr_reg[4]_1 ;
- wire \axi_araddr_reg[4]_2 ;
- wire \axi_araddr_reg[4]_3 ;
- wire \axi_araddr_reg[4]_4 ;
- wire \axi_araddr_reg[4]_5 ;
- wire \axi_araddr_reg[4]_6 ;
- wire \axi_araddr_reg[4]_7 ;
- wire \axi_araddr_reg[4]_8 ;
- wire \axi_araddr_reg[4]_rep_0 ;
- wire \axi_araddr_reg[4]_rep_1 ;
- wire \axi_araddr_reg[4]_rep_2 ;
- wire \axi_araddr_reg[4]_rep_3 ;
- wire \axi_araddr_reg[4]_rep_4 ;
- wire \axi_araddr_reg[4]_rep_5 ;
- wire \axi_araddr_reg[4]_rep_6 ;
- wire \axi_araddr_reg[4]_rep_7 ;
- wire \axi_araddr_reg[4]_rep_8 ;
- wire \axi_araddr_reg[4]_rep__0_0 ;
- wire \axi_araddr_reg[4]_rep__0_1 ;
- wire \axi_araddr_reg[4]_rep__0_2 ;
- wire \axi_araddr_reg[4]_rep__0_3 ;
- wire \axi_araddr_reg[4]_rep__0_4 ;
- wire \axi_araddr_reg[4]_rep__0_5 ;
- wire \axi_araddr_reg[4]_rep__0_6 ;
- wire \axi_araddr_reg[4]_rep__0_7 ;
- wire \axi_araddr_reg[4]_rep__0_8 ;
- wire \axi_araddr_reg[4]_rep__1_0 ;
- wire \axi_araddr_reg[5]_0 ;
- wire \axi_araddr_reg[5]_1 ;
- wire \axi_araddr_reg[5]_2 ;
- wire \axi_araddr_reg[5]_3 ;
- wire \axi_araddr_reg[5]_4 ;
- wire \axi_araddr_reg[5]_5 ;
- wire \axi_araddr_reg[5]_6 ;
- wire \axi_araddr_reg[5]_7 ;
- wire \axi_araddr_reg[5]_8 ;
- wire \axi_araddr_reg[5]_rep_0 ;
- wire \axi_araddr_reg[5]_rep_1 ;
- wire \axi_araddr_reg[5]_rep_10 ;
- wire \axi_araddr_reg[5]_rep_2 ;
- wire \axi_araddr_reg[5]_rep_3 ;
- wire \axi_araddr_reg[5]_rep_4 ;
- wire \axi_araddr_reg[5]_rep_5 ;
- wire \axi_araddr_reg[5]_rep_6 ;
- wire \axi_araddr_reg[5]_rep_7 ;
- wire \axi_araddr_reg[5]_rep_8 ;
- wire \axi_araddr_reg[5]_rep_9 ;
- wire axi_arready_i_1_n_0;
- wire axi_awready_i_2_n_0;
- wire \axi_bresp[1]_i_1_n_0 ;
- wire \axi_bresp[1]_i_3_n_0 ;
- wire axi_bvalid04_out;
- wire axi_bvalid_i_1_n_0;
- wire \axi_rdata[0]_i_14_n_0 ;
- wire \axi_rdata[0]_i_17_n_0 ;
- wire \axi_rdata[0]_i_1_n_0 ;
- wire \axi_rdata[0]_i_23_n_0 ;
- wire \axi_rdata[0]_i_29_n_0 ;
- wire \axi_rdata[0]_i_30_n_0 ;
- wire \axi_rdata[0]_i_31_n_0 ;
- wire \axi_rdata[0]_i_32_n_0 ;
- wire \axi_rdata[0]_i_33_n_0 ;
- wire \axi_rdata[0]_i_35_n_0 ;
- wire \axi_rdata[0]_i_36_n_0 ;
- wire \axi_rdata[0]_i_37_n_0 ;
- wire \axi_rdata[0]_i_39_n_0 ;
- wire \axi_rdata[0]_i_41_n_0 ;
- wire \axi_rdata[0]_i_44_n_0 ;
- wire \axi_rdata[0]_i_45_n_0 ;
- wire \axi_rdata[0]_i_5_n_0 ;
- wire \axi_rdata[0]_i_6_n_0 ;
- wire \axi_rdata[0]_i_7_n_0 ;
- wire \axi_rdata[0]_i_8_n_0 ;
- wire \axi_rdata[10]_i_13_n_0 ;
- wire \axi_rdata[10]_i_14_n_0 ;
- wire \axi_rdata[10]_i_17_n_0 ;
- wire \axi_rdata[10]_i_19_n_0 ;
- wire \axi_rdata[10]_i_1_n_0 ;
- wire \axi_rdata[10]_i_23_n_0 ;
- wire \axi_rdata[10]_i_29_n_0 ;
- wire \axi_rdata[10]_i_30_n_0 ;
- wire \axi_rdata[10]_i_31_n_0 ;
- wire \axi_rdata[10]_i_32_n_0 ;
- wire \axi_rdata[10]_i_33_n_0 ;
- wire \axi_rdata[10]_i_34_n_0 ;
- wire \axi_rdata[10]_i_35_n_0 ;
- wire \axi_rdata[10]_i_36_n_0 ;
- wire \axi_rdata[10]_i_37_n_0 ;
- wire \axi_rdata[10]_i_39_n_0 ;
- wire \axi_rdata[10]_i_42_n_0 ;
- wire \axi_rdata[10]_i_43_n_0 ;
- wire \axi_rdata[10]_i_5_n_0 ;
- wire \axi_rdata[10]_i_6_n_0 ;
- wire \axi_rdata[10]_i_7_n_0 ;
- wire \axi_rdata[10]_i_8_n_0 ;
- wire \axi_rdata[11]_i_13_n_0 ;
- wire \axi_rdata[11]_i_14_n_0 ;
- wire \axi_rdata[11]_i_17_n_0 ;
- wire \axi_rdata[11]_i_19_n_0 ;
- wire \axi_rdata[11]_i_1_n_0 ;
- wire \axi_rdata[11]_i_23_n_0 ;
- wire \axi_rdata[11]_i_29_n_0 ;
- wire \axi_rdata[11]_i_30_n_0 ;
- wire \axi_rdata[11]_i_31_n_0 ;
- wire \axi_rdata[11]_i_32_n_0 ;
- wire \axi_rdata[11]_i_33_n_0 ;
- wire \axi_rdata[11]_i_34_n_0 ;
- wire \axi_rdata[11]_i_35_n_0 ;
- wire \axi_rdata[11]_i_36_n_0 ;
- wire \axi_rdata[11]_i_37_n_0 ;
- wire \axi_rdata[11]_i_39_n_0 ;
- wire \axi_rdata[11]_i_42_n_0 ;
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- wire \axi_rdata[6]_i_7_n_0 ;
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- wire \axi_rdata_reg[12]_1 ;
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- wire \axi_rdata_reg[16]_i_3_n_0 ;
- wire \axi_rdata_reg[17]_0 ;
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- wire \axi_rdata_reg[18]_0 ;
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- wire \axi_rdata_reg[19]_i_3_n_0 ;
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- wire \axi_rdata_reg[1]_i_20_n_0 ;
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- wire \axi_rdata_reg[20]_i_22_n_0 ;
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- wire \axi_rdata_reg[21]_i_6_n_0 ;
- wire \axi_rdata_reg[22]_0 ;
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- wire \axi_rdata_reg[22]_i_22_n_0 ;
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- wire [3:0]\axi_rdata_reg[23]_0 ;
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- wire \axi_rdata_reg[25]_i_8_n_0 ;
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- wire \axi_rdata_reg[26]_i_8_n_0 ;
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- wire \axi_rdata_reg[27]_i_15_n_0 ;
- wire \axi_rdata_reg[27]_i_16_n_0 ;
- wire \axi_rdata_reg[27]_i_8_n_0 ;
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- wire \axi_rdata_reg[28]_i_15_n_0 ;
- wire \axi_rdata_reg[28]_i_16_n_0 ;
- wire \axi_rdata_reg[28]_i_8_n_0 ;
- wire \axi_rdata_reg[29]_i_10_n_0 ;
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- wire \axi_rdata_reg[29]_i_16_n_0 ;
- wire \axi_rdata_reg[29]_i_8_n_0 ;
- wire \axi_rdata_reg[2]_0 ;
- wire \axi_rdata_reg[2]_1 ;
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- wire \axi_rdata_reg[2]_i_12_n_0 ;
- wire \axi_rdata_reg[2]_i_13_n_0 ;
- wire \axi_rdata_reg[2]_i_18_n_0 ;
- wire \axi_rdata_reg[2]_i_19_n_0 ;
- wire \axi_rdata_reg[2]_i_20_n_0 ;
- wire \axi_rdata_reg[2]_i_24_n_0 ;
- wire \axi_rdata_reg[2]_i_2_n_0 ;
- wire \axi_rdata_reg[2]_i_3_n_0 ;
- wire \axi_rdata_reg[30]_i_10_n_0 ;
- wire \axi_rdata_reg[30]_i_15_n_0 ;
- wire \axi_rdata_reg[30]_i_16_n_0 ;
- wire \axi_rdata_reg[30]_i_8_n_0 ;
- wire \axi_rdata_reg[31]_i_11_n_0 ;
- wire \axi_rdata_reg[31]_i_16_n_0 ;
- wire \axi_rdata_reg[31]_i_17_n_0 ;
- wire \axi_rdata_reg[31]_i_9_n_0 ;
- wire \axi_rdata_reg[3]_i_11_n_0 ;
- wire \axi_rdata_reg[3]_i_12_n_0 ;
- wire \axi_rdata_reg[3]_i_13_n_0 ;
- wire \axi_rdata_reg[3]_i_18_n_0 ;
- wire \axi_rdata_reg[3]_i_19_n_0 ;
- wire \axi_rdata_reg[3]_i_20_n_0 ;
- wire \axi_rdata_reg[3]_i_24_n_0 ;
- wire \axi_rdata_reg[3]_i_2_n_0 ;
- wire \axi_rdata_reg[3]_i_3_n_0 ;
- wire \axi_rdata_reg[4]_i_11_n_0 ;
- wire \axi_rdata_reg[4]_i_12_n_0 ;
- wire \axi_rdata_reg[4]_i_13_n_0 ;
- wire \axi_rdata_reg[4]_i_18_n_0 ;
- wire \axi_rdata_reg[4]_i_19_n_0 ;
- wire \axi_rdata_reg[4]_i_20_n_0 ;
- wire \axi_rdata_reg[4]_i_24_n_0 ;
- wire \axi_rdata_reg[4]_i_2_n_0 ;
- wire \axi_rdata_reg[4]_i_3_n_0 ;
- wire \axi_rdata_reg[5]_i_11_n_0 ;
- wire \axi_rdata_reg[5]_i_12_n_0 ;
- wire \axi_rdata_reg[5]_i_13_n_0 ;
- wire \axi_rdata_reg[5]_i_18_n_0 ;
- wire \axi_rdata_reg[5]_i_19_n_0 ;
- wire \axi_rdata_reg[5]_i_20_n_0 ;
- wire \axi_rdata_reg[5]_i_24_n_0 ;
- wire \axi_rdata_reg[5]_i_2_n_0 ;
- wire \axi_rdata_reg[5]_i_3_n_0 ;
- wire \axi_rdata_reg[6]_i_11_n_0 ;
- wire \axi_rdata_reg[6]_i_12_n_0 ;
- wire \axi_rdata_reg[6]_i_13_n_0 ;
- wire \axi_rdata_reg[6]_i_18_n_0 ;
- wire \axi_rdata_reg[6]_i_19_n_0 ;
- wire \axi_rdata_reg[6]_i_20_n_0 ;
- wire \axi_rdata_reg[6]_i_24_n_0 ;
- wire \axi_rdata_reg[6]_i_2_n_0 ;
- wire \axi_rdata_reg[6]_i_3_n_0 ;
- wire \axi_rdata_reg[7]_0 ;
- wire \axi_rdata_reg[7]_1 ;
- wire \axi_rdata_reg[7]_i_11_n_0 ;
- wire \axi_rdata_reg[7]_i_12_n_0 ;
- wire \axi_rdata_reg[7]_i_13_n_0 ;
- wire \axi_rdata_reg[7]_i_18_n_0 ;
- wire \axi_rdata_reg[7]_i_19_n_0 ;
- wire \axi_rdata_reg[7]_i_20_n_0 ;
- wire \axi_rdata_reg[7]_i_24_n_0 ;
- wire \axi_rdata_reg[7]_i_2_n_0 ;
- wire \axi_rdata_reg[7]_i_3_n_0 ;
- wire \axi_rdata_reg[8]_i_11_n_0 ;
- wire \axi_rdata_reg[8]_i_12_n_0 ;
- wire \axi_rdata_reg[8]_i_18_n_0 ;
- wire \axi_rdata_reg[8]_i_20_n_0 ;
- wire \axi_rdata_reg[8]_i_24_n_0 ;
- wire \axi_rdata_reg[8]_i_2_n_0 ;
- wire \axi_rdata_reg[8]_i_3_n_0 ;
- wire \axi_rdata_reg[9]_0 ;
- wire \axi_rdata_reg[9]_i_11_n_0 ;
- wire \axi_rdata_reg[9]_i_12_n_0 ;
- wire \axi_rdata_reg[9]_i_18_n_0 ;
- wire \axi_rdata_reg[9]_i_20_n_0 ;
- wire \axi_rdata_reg[9]_i_24_n_0 ;
- wire \axi_rdata_reg[9]_i_2_n_0 ;
- wire \axi_rdata_reg[9]_i_3_n_0 ;
- wire \axi_rresp[1]_i_1_n_0 ;
- wire axi_rvalid0;
- wire axi_rvalid_i_1_n_0;
- wire axi_wready_i_1_n_0;
- wire [31:0]\dac_ch_o_reg[0][31] ;
- wire [31:0]\dac_ch_o_reg[0][31]_0 ;
- wire [3:0]\data_o_reg[1][3] ;
- wire [3:0]\data_o_reg[1][3]_0 ;
- wire \data_o_reg[6][0] ;
- wire \data_o_reg[6][0]_0 ;
- wire \data_o_reg[6][1] ;
- wire \data_o_reg[6][1]_0 ;
- wire \data_o_reg[6][2] ;
- wire \data_o_reg[6][2]_0 ;
- wire \data_o_reg[6][3] ;
- wire \data_o_reg[6][3]_0 ;
- wire \data_o_reg[6][4] ;
- wire \data_o_reg[6][4]_0 ;
- wire \data_o_reg[6][5] ;
- wire \data_o_reg[6][5]_0 ;
- wire \data_o_reg[6][6] ;
- wire \data_o_reg[6][6]_0 ;
- wire \data_o_reg[6][7] ;
- wire \data_o_reg[6][7]_0 ;
- wire \data_rw_o[0]1 ;
- wire \data_rw_o[100][15]_i_1_n_0 ;
- wire \data_rw_o[100][23]_i_1_n_0 ;
- wire \data_rw_o[100][31]_i_1_n_0 ;
- wire \data_rw_o[100][31]_i_2_n_0 ;
- wire \data_rw_o[100][7]_i_1_n_0 ;
- wire \data_rw_o[101][15]_i_1_n_0 ;
- wire \data_rw_o[101][23]_i_1_n_0 ;
- wire \data_rw_o[101][31]_i_1_n_0 ;
- wire \data_rw_o[101][31]_i_2_n_0 ;
- wire \data_rw_o[101][7]_i_1_n_0 ;
- wire \data_rw_o[102][15]_i_1_n_0 ;
- wire \data_rw_o[102][23]_i_1_n_0 ;
- wire \data_rw_o[102][31]_i_1_n_0 ;
- wire \data_rw_o[102][31]_i_2_n_0 ;
- wire \data_rw_o[102][7]_i_1_n_0 ;
- wire \data_rw_o[103][15]_i_1_n_0 ;
- wire \data_rw_o[103][23]_i_1_n_0 ;
- wire \data_rw_o[103][31]_i_1_n_0 ;
- wire \data_rw_o[103][31]_i_2_n_0 ;
- wire \data_rw_o[103][31]_i_3_n_0 ;
- wire \data_rw_o[103][7]_i_1_n_0 ;
- wire [7:4]\data_rw_o[10] ;
- wire \data_rw_o[10][15]_i_1_n_0 ;
- wire \data_rw_o[10][23]_i_1_n_0 ;
- wire \data_rw_o[10][31]_i_1_n_0 ;
- wire \data_rw_o[10][31]_i_2_n_0 ;
- wire \data_rw_o[10][7]_i_1_n_0 ;
- wire \data_rw_o[11][15]_i_1_n_0 ;
- wire \data_rw_o[11][23]_i_1_n_0 ;
- wire \data_rw_o[11][31]_i_1_n_0 ;
- wire \data_rw_o[11][31]_i_2_n_0 ;
- wire \data_rw_o[11][7]_i_1_n_0 ;
- wire \data_rw_o[16][15]_i_1_n_0 ;
- wire \data_rw_o[16][23]_i_1_n_0 ;
- wire \data_rw_o[16][31]_i_1_n_0 ;
- wire \data_rw_o[16][31]_i_2_n_0 ;
- wire \data_rw_o[16][31]_i_3_n_0 ;
- wire \data_rw_o[16][7]_i_1_n_0 ;
- wire \data_rw_o[17][15]_i_1_n_0 ;
- wire \data_rw_o[17][23]_i_1_n_0 ;
- wire \data_rw_o[17][31]_i_1_n_0 ;
- wire \data_rw_o[17][31]_i_2_n_0 ;
- wire \data_rw_o[17][31]_i_3_n_0 ;
- wire \data_rw_o[17][7]_i_1_n_0 ;
- wire \data_rw_o[18][15]_i_1_n_0 ;
- wire \data_rw_o[18][23]_i_1_n_0 ;
- wire \data_rw_o[18][31]_i_1_n_0 ;
- wire \data_rw_o[18][31]_i_2_n_0 ;
- wire \data_rw_o[18][7]_i_1_n_0 ;
- wire \data_rw_o[19][15]_i_1_n_0 ;
- wire \data_rw_o[19][23]_i_1_n_0 ;
- wire \data_rw_o[19][31]_i_1_n_0 ;
- wire \data_rw_o[19][31]_i_2_n_0 ;
- wire \data_rw_o[19][31]_i_3_n_0 ;
- wire \data_rw_o[19][7]_i_1_n_0 ;
- wire \data_rw_o[20][15]_i_1_n_0 ;
- wire \data_rw_o[20][23]_i_1_n_0 ;
- wire \data_rw_o[20][31]_i_1_n_0 ;
- wire \data_rw_o[20][31]_i_2_n_0 ;
- wire \data_rw_o[20][7]_i_1_n_0 ;
- wire \data_rw_o[21][15]_i_1_n_0 ;
- wire \data_rw_o[21][23]_i_1_n_0 ;
- wire \data_rw_o[21][31]_i_1_n_0 ;
- wire \data_rw_o[21][31]_i_2_n_0 ;
- wire \data_rw_o[21][7]_i_1_n_0 ;
- wire \data_rw_o[22][15]_i_1_n_0 ;
- wire \data_rw_o[22][23]_i_1_n_0 ;
- wire \data_rw_o[22][31]_i_1_n_0 ;
- wire \data_rw_o[22][31]_i_2_n_0 ;
- wire \data_rw_o[22][7]_i_1_n_0 ;
- wire \data_rw_o[23][15]_i_1_n_0 ;
- wire \data_rw_o[23][23]_i_1_n_0 ;
- wire \data_rw_o[23][31]_i_1_n_0 ;
- wire \data_rw_o[23][31]_i_2_n_0 ;
- wire \data_rw_o[23][31]_i_3_n_0 ;
- wire \data_rw_o[23][31]_i_4_n_0 ;
- wire \data_rw_o[23][31]_i_5_n_0 ;
- wire \data_rw_o[23][7]_i_1_n_0 ;
- wire \data_rw_o[24][15]_i_1_n_0 ;
- wire \data_rw_o[24][23]_i_1_n_0 ;
- wire \data_rw_o[24][31]_i_1_n_0 ;
- wire \data_rw_o[24][31]_i_2_n_0 ;
- wire \data_rw_o[24][7]_i_1_n_0 ;
- wire \data_rw_o[25][15]_i_1_n_0 ;
- wire \data_rw_o[25][23]_i_1_n_0 ;
- wire \data_rw_o[25][31]_i_1_n_0 ;
- wire \data_rw_o[25][31]_i_2_n_0 ;
- wire \data_rw_o[25][7]_i_1_n_0 ;
- wire \data_rw_o[26][15]_i_1_n_0 ;
- wire \data_rw_o[26][23]_i_1_n_0 ;
- wire \data_rw_o[26][31]_i_1_n_0 ;
- wire \data_rw_o[26][31]_i_2_n_0 ;
- wire \data_rw_o[26][7]_i_1_n_0 ;
- wire \data_rw_o[27][15]_i_1_n_0 ;
- wire \data_rw_o[27][23]_i_1_n_0 ;
- wire \data_rw_o[27][31]_i_1_n_0 ;
- wire \data_rw_o[27][31]_i_2_n_0 ;
- wire \data_rw_o[27][7]_i_1_n_0 ;
- wire \data_rw_o[28][15]_i_1_n_0 ;
- wire \data_rw_o[28][23]_i_1_n_0 ;
- wire \data_rw_o[28][31]_i_1_n_0 ;
- wire \data_rw_o[28][31]_i_2_n_0 ;
- wire \data_rw_o[28][7]_i_1_n_0 ;
- wire \data_rw_o[29][15]_i_1_n_0 ;
- wire \data_rw_o[29][23]_i_1_n_0 ;
- wire \data_rw_o[29][31]_i_1_n_0 ;
- wire \data_rw_o[29][31]_i_2_n_0 ;
- wire \data_rw_o[29][7]_i_1_n_0 ;
- wire \data_rw_o[30][15]_i_1_n_0 ;
- wire \data_rw_o[30][23]_i_1_n_0 ;
- wire \data_rw_o[30][31]_i_1_n_0 ;
- wire \data_rw_o[30][31]_i_2_n_0 ;
- wire \data_rw_o[30][7]_i_1_n_0 ;
- wire \data_rw_o[31][15]_i_1_n_0 ;
- wire \data_rw_o[31][23]_i_1_n_0 ;
- wire \data_rw_o[31][31]_i_1_n_0 ;
- wire \data_rw_o[31][31]_i_2_n_0 ;
- wire \data_rw_o[31][31]_i_3_n_0 ;
- wire \data_rw_o[31][7]_i_1_n_0 ;
- wire \data_rw_o[32][15]_i_1_n_0 ;
- wire \data_rw_o[32][23]_i_1_n_0 ;
- wire \data_rw_o[32][31]_i_1_n_0 ;
- wire \data_rw_o[32][31]_i_2_n_0 ;
- wire \data_rw_o[32][31]_i_3_n_0 ;
- wire \data_rw_o[32][31]_i_4_n_0 ;
- wire \data_rw_o[32][7]_i_1_n_0 ;
- wire \data_rw_o[33][15]_i_1_n_0 ;
- wire \data_rw_o[33][23]_i_1_n_0 ;
- wire \data_rw_o[33][31]_i_1_n_0 ;
- wire \data_rw_o[33][31]_i_2_n_0 ;
- wire \data_rw_o[33][31]_i_3_n_0 ;
- wire \data_rw_o[33][7]_i_1_n_0 ;
- wire \data_rw_o[34][15]_i_1_n_0 ;
- wire \data_rw_o[34][23]_i_1_n_0 ;
- wire \data_rw_o[34][31]_i_1_n_0 ;
- wire \data_rw_o[34][31]_i_2_n_0 ;
- wire \data_rw_o[34][7]_i_1_n_0 ;
- wire \data_rw_o[35][15]_i_1_n_0 ;
- wire \data_rw_o[35][23]_i_1_n_0 ;
- wire \data_rw_o[35][31]_i_1_n_0 ;
- wire \data_rw_o[35][31]_i_2_n_0 ;
- wire \data_rw_o[35][31]_i_3_n_0 ;
- wire \data_rw_o[35][7]_i_1_n_0 ;
- wire [1:0]\data_rw_o[3] ;
- wire \data_rw_o[3][15]_i_1_n_0 ;
- wire \data_rw_o[3][23]_i_1_n_0 ;
- wire \data_rw_o[3][31]_i_1_n_0 ;
- wire \data_rw_o[3][31]_i_2_n_0 ;
- wire \data_rw_o[3][31]_i_3_n_0 ;
- wire \data_rw_o[3][31]_i_4_n_0 ;
- wire \data_rw_o[3][31]_i_5_n_0 ;
- wire \data_rw_o[3][31]_i_7_n_0 ;
- wire \data_rw_o[3][7]_i_1_n_0 ;
- wire [7:4]\data_rw_o[78] ;
- wire \data_rw_o[78][15]_i_1_n_0 ;
- wire \data_rw_o[78][23]_i_1_n_0 ;
- wire \data_rw_o[78][31]_i_1_n_0 ;
- wire \data_rw_o[78][31]_i_2_n_0 ;
- wire \data_rw_o[78][31]_i_3_n_0 ;
- wire \data_rw_o[78][31]_i_4_n_0 ;
- wire \data_rw_o[78][31]_i_5_n_0 ;
- wire \data_rw_o[78][7]_i_1_n_0 ;
- wire \data_rw_o[79][15]_i_1_n_0 ;
- wire \data_rw_o[79][23]_i_1_n_0 ;
- wire \data_rw_o[79][31]_i_1_n_0 ;
- wire \data_rw_o[79][31]_i_2_n_0 ;
- wire \data_rw_o[79][7]_i_1_n_0 ;
- wire \data_rw_o[84][15]_i_1_n_0 ;
- wire \data_rw_o[84][23]_i_1_n_0 ;
- wire \data_rw_o[84][31]_i_1_n_0 ;
- wire \data_rw_o[84][31]_i_2_n_0 ;
- wire \data_rw_o[84][31]_i_3_n_0 ;
- wire \data_rw_o[84][7]_i_1_n_0 ;
- wire \data_rw_o[85][15]_i_1_n_0 ;
- wire \data_rw_o[85][23]_i_1_n_0 ;
- wire \data_rw_o[85][31]_i_1_n_0 ;
- wire \data_rw_o[85][31]_i_2_n_0 ;
- wire \data_rw_o[85][31]_i_3_n_0 ;
- wire \data_rw_o[85][31]_i_4_n_0 ;
- wire \data_rw_o[85][7]_i_1_n_0 ;
- wire \data_rw_o[86][15]_i_1_n_0 ;
- wire \data_rw_o[86][23]_i_1_n_0 ;
- wire \data_rw_o[86][31]_i_1_n_0 ;
- wire \data_rw_o[86][31]_i_2_n_0 ;
- wire \data_rw_o[86][31]_i_3_n_0 ;
- wire \data_rw_o[86][7]_i_1_n_0 ;
- wire \data_rw_o[87][15]_i_1_n_0 ;
- wire \data_rw_o[87][23]_i_1_n_0 ;
- wire \data_rw_o[87][31]_i_1_n_0 ;
- wire \data_rw_o[87][31]_i_2_n_0 ;
- wire \data_rw_o[87][31]_i_3_n_0 ;
- wire \data_rw_o[87][7]_i_1_n_0 ;
- wire \data_rw_o[88][15]_i_1_n_0 ;
- wire \data_rw_o[88][23]_i_1_n_0 ;
- wire \data_rw_o[88][31]_i_1_n_0 ;
- wire \data_rw_o[88][31]_i_2_n_0 ;
- wire \data_rw_o[88][31]_i_3_n_0 ;
- wire \data_rw_o[88][7]_i_1_n_0 ;
- wire \data_rw_o[89][15]_i_1_n_0 ;
- wire \data_rw_o[89][23]_i_1_n_0 ;
- wire \data_rw_o[89][31]_i_1_n_0 ;
- wire \data_rw_o[89][31]_i_2_n_0 ;
- wire \data_rw_o[89][31]_i_3_n_0 ;
- wire \data_rw_o[89][31]_i_4_n_0 ;
- wire \data_rw_o[89][7]_i_1_n_0 ;
- wire \data_rw_o[90][15]_i_1_n_0 ;
- wire \data_rw_o[90][23]_i_1_n_0 ;
- wire \data_rw_o[90][31]_i_1_n_0 ;
- wire \data_rw_o[90][31]_i_2_n_0 ;
- wire \data_rw_o[90][7]_i_1_n_0 ;
- wire \data_rw_o[91][15]_i_1_n_0 ;
- wire \data_rw_o[91][23]_i_1_n_0 ;
- wire \data_rw_o[91][31]_i_1_n_0 ;
- wire \data_rw_o[91][31]_i_2_n_0 ;
- wire \data_rw_o[91][7]_i_1_n_0 ;
- wire \data_rw_o[92][15]_i_1_n_0 ;
- wire \data_rw_o[92][23]_i_1_n_0 ;
- wire \data_rw_o[92][31]_i_1_n_0 ;
- wire \data_rw_o[92][31]_i_2_n_0 ;
- wire \data_rw_o[92][7]_i_1_n_0 ;
- wire \data_rw_o[93][15]_i_1_n_0 ;
- wire \data_rw_o[93][23]_i_1_n_0 ;
- wire \data_rw_o[93][31]_i_1_n_0 ;
- wire \data_rw_o[93][31]_i_2_n_0 ;
- wire \data_rw_o[93][31]_i_3_n_0 ;
- wire \data_rw_o[93][7]_i_1_n_0 ;
- wire \data_rw_o[94][15]_i_1_n_0 ;
- wire \data_rw_o[94][23]_i_1_n_0 ;
- wire \data_rw_o[94][31]_i_1_n_0 ;
- wire \data_rw_o[94][31]_i_2_n_0 ;
- wire \data_rw_o[94][31]_i_3_n_0 ;
- wire \data_rw_o[94][7]_i_1_n_0 ;
- wire \data_rw_o[95][15]_i_1_n_0 ;
- wire \data_rw_o[95][23]_i_1_n_0 ;
- wire \data_rw_o[95][31]_i_1_n_0 ;
- wire \data_rw_o[95][31]_i_2_n_0 ;
- wire \data_rw_o[95][7]_i_1_n_0 ;
- wire \data_rw_o[96][15]_i_1_n_0 ;
- wire \data_rw_o[96][23]_i_1_n_0 ;
- wire \data_rw_o[96][31]_i_1_n_0 ;
- wire \data_rw_o[96][31]_i_2_n_0 ;
- wire \data_rw_o[96][31]_i_3_n_0 ;
- wire \data_rw_o[96][7]_i_1_n_0 ;
- wire \data_rw_o[97][15]_i_1_n_0 ;
- wire \data_rw_o[97][23]_i_1_n_0 ;
- wire \data_rw_o[97][31]_i_1_n_0 ;
- wire \data_rw_o[97][31]_i_2_n_0 ;
- wire \data_rw_o[97][31]_i_3_n_0 ;
- wire \data_rw_o[97][7]_i_1_n_0 ;
- wire \data_rw_o[98][15]_i_1_n_0 ;
- wire \data_rw_o[98][23]_i_1_n_0 ;
- wire \data_rw_o[98][31]_i_1_n_0 ;
- wire \data_rw_o[98][31]_i_2_n_0 ;
- wire \data_rw_o[98][7]_i_1_n_0 ;
- wire \data_rw_o[99][15]_i_1_n_0 ;
- wire \data_rw_o[99][23]_i_1_n_0 ;
- wire \data_rw_o[99][31]_i_1_n_0 ;
- wire \data_rw_o[99][31]_i_2_n_0 ;
- wire \data_rw_o[99][31]_i_3_n_0 ;
- wire \data_rw_o[99][7]_i_1_n_0 ;
- wire \data_rw_o_reg_n_0_[100][12] ;
- wire \data_rw_o_reg_n_0_[100][13] ;
- wire \data_rw_o_reg_n_0_[100][14] ;
- wire \data_rw_o_reg_n_0_[100][15] ;
- wire \data_rw_o_reg_n_0_[100][16] ;
- wire \data_rw_o_reg_n_0_[100][17] ;
- wire \data_rw_o_reg_n_0_[100][18] ;
- wire \data_rw_o_reg_n_0_[100][19] ;
- wire \data_rw_o_reg_n_0_[100][20] ;
- wire \data_rw_o_reg_n_0_[100][21] ;
- wire \data_rw_o_reg_n_0_[100][22] ;
- wire \data_rw_o_reg_n_0_[100][23] ;
- wire \data_rw_o_reg_n_0_[100][24] ;
- wire \data_rw_o_reg_n_0_[100][25] ;
- wire \data_rw_o_reg_n_0_[100][26] ;
- wire \data_rw_o_reg_n_0_[100][27] ;
- wire \data_rw_o_reg_n_0_[100][28] ;
- wire \data_rw_o_reg_n_0_[100][29] ;
- wire \data_rw_o_reg_n_0_[100][30] ;
- wire \data_rw_o_reg_n_0_[100][31] ;
- wire \data_rw_o_reg_n_0_[101][12] ;
- wire \data_rw_o_reg_n_0_[101][13] ;
- wire \data_rw_o_reg_n_0_[101][14] ;
- wire \data_rw_o_reg_n_0_[101][15] ;
- wire \data_rw_o_reg_n_0_[101][16] ;
- wire \data_rw_o_reg_n_0_[101][17] ;
- wire \data_rw_o_reg_n_0_[101][18] ;
- wire \data_rw_o_reg_n_0_[101][19] ;
- wire \data_rw_o_reg_n_0_[101][20] ;
- wire \data_rw_o_reg_n_0_[101][21] ;
- wire \data_rw_o_reg_n_0_[101][22] ;
- wire \data_rw_o_reg_n_0_[101][23] ;
- wire \data_rw_o_reg_n_0_[101][24] ;
- wire \data_rw_o_reg_n_0_[101][25] ;
- wire \data_rw_o_reg_n_0_[101][26] ;
- wire \data_rw_o_reg_n_0_[101][27] ;
- wire \data_rw_o_reg_n_0_[101][28] ;
- wire \data_rw_o_reg_n_0_[101][29] ;
- wire \data_rw_o_reg_n_0_[101][30] ;
- wire \data_rw_o_reg_n_0_[101][31] ;
- wire \data_rw_o_reg_n_0_[102][12] ;
- wire \data_rw_o_reg_n_0_[102][13] ;
- wire \data_rw_o_reg_n_0_[102][14] ;
- wire \data_rw_o_reg_n_0_[102][15] ;
- wire \data_rw_o_reg_n_0_[102][16] ;
- wire \data_rw_o_reg_n_0_[102][17] ;
- wire \data_rw_o_reg_n_0_[102][18] ;
- wire \data_rw_o_reg_n_0_[102][19] ;
- wire \data_rw_o_reg_n_0_[102][20] ;
- wire \data_rw_o_reg_n_0_[102][21] ;
- wire \data_rw_o_reg_n_0_[102][22] ;
- wire \data_rw_o_reg_n_0_[102][23] ;
- wire \data_rw_o_reg_n_0_[102][24] ;
- wire \data_rw_o_reg_n_0_[102][25] ;
- wire \data_rw_o_reg_n_0_[102][26] ;
- wire \data_rw_o_reg_n_0_[102][27] ;
- wire \data_rw_o_reg_n_0_[102][28] ;
- wire \data_rw_o_reg_n_0_[102][29] ;
- wire \data_rw_o_reg_n_0_[102][30] ;
- wire \data_rw_o_reg_n_0_[102][31] ;
- wire \data_rw_o_reg_n_0_[103][12] ;
- wire \data_rw_o_reg_n_0_[103][13] ;
- wire \data_rw_o_reg_n_0_[103][14] ;
- wire \data_rw_o_reg_n_0_[103][15] ;
- wire \data_rw_o_reg_n_0_[103][16] ;
- wire \data_rw_o_reg_n_0_[103][17] ;
- wire \data_rw_o_reg_n_0_[103][18] ;
- wire \data_rw_o_reg_n_0_[103][19] ;
- wire \data_rw_o_reg_n_0_[103][20] ;
- wire \data_rw_o_reg_n_0_[103][21] ;
- wire \data_rw_o_reg_n_0_[103][22] ;
- wire \data_rw_o_reg_n_0_[103][23] ;
- wire \data_rw_o_reg_n_0_[103][24] ;
- wire \data_rw_o_reg_n_0_[103][25] ;
- wire \data_rw_o_reg_n_0_[103][26] ;
- wire \data_rw_o_reg_n_0_[103][27] ;
- wire \data_rw_o_reg_n_0_[103][28] ;
- wire \data_rw_o_reg_n_0_[103][29] ;
- wire \data_rw_o_reg_n_0_[103][30] ;
- wire \data_rw_o_reg_n_0_[103][31] ;
- wire \data_rw_o_reg_n_0_[10][0] ;
- wire \data_rw_o_reg_n_0_[10][10] ;
- wire \data_rw_o_reg_n_0_[10][11] ;
- wire \data_rw_o_reg_n_0_[10][12] ;
- wire \data_rw_o_reg_n_0_[10][13] ;
- wire \data_rw_o_reg_n_0_[10][14] ;
- wire \data_rw_o_reg_n_0_[10][15] ;
- wire \data_rw_o_reg_n_0_[10][16] ;
- wire \data_rw_o_reg_n_0_[10][17] ;
- wire \data_rw_o_reg_n_0_[10][18] ;
- wire \data_rw_o_reg_n_0_[10][19] ;
- wire \data_rw_o_reg_n_0_[10][1] ;
- wire \data_rw_o_reg_n_0_[10][20] ;
- wire \data_rw_o_reg_n_0_[10][21] ;
- wire \data_rw_o_reg_n_0_[10][22] ;
- wire \data_rw_o_reg_n_0_[10][23] ;
- wire \data_rw_o_reg_n_0_[10][24] ;
- wire \data_rw_o_reg_n_0_[10][25] ;
- wire \data_rw_o_reg_n_0_[10][26] ;
- wire \data_rw_o_reg_n_0_[10][27] ;
- wire \data_rw_o_reg_n_0_[10][28] ;
- wire \data_rw_o_reg_n_0_[10][29] ;
- wire \data_rw_o_reg_n_0_[10][2] ;
- wire \data_rw_o_reg_n_0_[10][30] ;
- wire \data_rw_o_reg_n_0_[10][31] ;
- wire \data_rw_o_reg_n_0_[10][3] ;
- wire \data_rw_o_reg_n_0_[10][8] ;
- wire \data_rw_o_reg_n_0_[10][9] ;
- wire \data_rw_o_reg_n_0_[11][0] ;
- wire \data_rw_o_reg_n_0_[11][10] ;
- wire \data_rw_o_reg_n_0_[11][11] ;
- wire \data_rw_o_reg_n_0_[11][12] ;
- wire \data_rw_o_reg_n_0_[11][13] ;
- wire \data_rw_o_reg_n_0_[11][14] ;
- wire \data_rw_o_reg_n_0_[11][15] ;
- wire \data_rw_o_reg_n_0_[11][16] ;
- wire \data_rw_o_reg_n_0_[11][17] ;
- wire \data_rw_o_reg_n_0_[11][18] ;
- wire \data_rw_o_reg_n_0_[11][19] ;
- wire \data_rw_o_reg_n_0_[11][20] ;
- wire \data_rw_o_reg_n_0_[11][21] ;
- wire \data_rw_o_reg_n_0_[11][22] ;
- wire \data_rw_o_reg_n_0_[11][23] ;
- wire \data_rw_o_reg_n_0_[11][24] ;
- wire \data_rw_o_reg_n_0_[11][25] ;
- wire \data_rw_o_reg_n_0_[11][26] ;
- wire \data_rw_o_reg_n_0_[11][27] ;
- wire \data_rw_o_reg_n_0_[11][28] ;
- wire \data_rw_o_reg_n_0_[11][29] ;
- wire \data_rw_o_reg_n_0_[11][30] ;
- wire \data_rw_o_reg_n_0_[11][31] ;
- wire \data_rw_o_reg_n_0_[11][3] ;
- wire \data_rw_o_reg_n_0_[11][4] ;
- wire \data_rw_o_reg_n_0_[11][5] ;
- wire \data_rw_o_reg_n_0_[11][6] ;
- wire \data_rw_o_reg_n_0_[11][8] ;
- wire \data_rw_o_reg_n_0_[11][9] ;
- wire \data_rw_o_reg_n_0_[16][12] ;
- wire \data_rw_o_reg_n_0_[16][13] ;
- wire \data_rw_o_reg_n_0_[16][14] ;
- wire \data_rw_o_reg_n_0_[16][15] ;
- wire \data_rw_o_reg_n_0_[16][16] ;
- wire \data_rw_o_reg_n_0_[16][17] ;
- wire \data_rw_o_reg_n_0_[16][18] ;
- wire \data_rw_o_reg_n_0_[16][19] ;
- wire \data_rw_o_reg_n_0_[16][20] ;
- wire \data_rw_o_reg_n_0_[16][21] ;
- wire \data_rw_o_reg_n_0_[16][22] ;
- wire \data_rw_o_reg_n_0_[16][23] ;
- wire \data_rw_o_reg_n_0_[16][24] ;
- wire \data_rw_o_reg_n_0_[16][25] ;
- wire \data_rw_o_reg_n_0_[16][26] ;
- wire \data_rw_o_reg_n_0_[16][27] ;
- wire \data_rw_o_reg_n_0_[16][28] ;
- wire \data_rw_o_reg_n_0_[16][29] ;
- wire \data_rw_o_reg_n_0_[16][30] ;
- wire \data_rw_o_reg_n_0_[16][31] ;
- wire \data_rw_o_reg_n_0_[17][12] ;
- wire \data_rw_o_reg_n_0_[17][13] ;
- wire \data_rw_o_reg_n_0_[17][14] ;
- wire \data_rw_o_reg_n_0_[17][15] ;
- wire \data_rw_o_reg_n_0_[17][16] ;
- wire \data_rw_o_reg_n_0_[17][17] ;
- wire \data_rw_o_reg_n_0_[17][18] ;
- wire \data_rw_o_reg_n_0_[17][19] ;
- wire \data_rw_o_reg_n_0_[17][20] ;
- wire \data_rw_o_reg_n_0_[17][21] ;
- wire \data_rw_o_reg_n_0_[17][22] ;
- wire \data_rw_o_reg_n_0_[17][23] ;
- wire \data_rw_o_reg_n_0_[17][24] ;
- wire \data_rw_o_reg_n_0_[17][25] ;
- wire \data_rw_o_reg_n_0_[17][26] ;
- wire \data_rw_o_reg_n_0_[17][27] ;
- wire \data_rw_o_reg_n_0_[17][28] ;
- wire \data_rw_o_reg_n_0_[17][29] ;
- wire \data_rw_o_reg_n_0_[17][30] ;
- wire \data_rw_o_reg_n_0_[17][31] ;
- wire \data_rw_o_reg_n_0_[18][12] ;
- wire \data_rw_o_reg_n_0_[18][13] ;
- wire \data_rw_o_reg_n_0_[18][14] ;
- wire \data_rw_o_reg_n_0_[18][15] ;
- wire \data_rw_o_reg_n_0_[18][16] ;
- wire \data_rw_o_reg_n_0_[18][17] ;
- wire \data_rw_o_reg_n_0_[18][18] ;
- wire \data_rw_o_reg_n_0_[18][19] ;
- wire \data_rw_o_reg_n_0_[18][20] ;
- wire \data_rw_o_reg_n_0_[18][21] ;
- wire \data_rw_o_reg_n_0_[18][22] ;
- wire \data_rw_o_reg_n_0_[18][23] ;
- wire \data_rw_o_reg_n_0_[18][24] ;
- wire \data_rw_o_reg_n_0_[18][25] ;
- wire \data_rw_o_reg_n_0_[18][26] ;
- wire \data_rw_o_reg_n_0_[18][27] ;
- wire \data_rw_o_reg_n_0_[18][28] ;
- wire \data_rw_o_reg_n_0_[18][29] ;
- wire \data_rw_o_reg_n_0_[18][30] ;
- wire \data_rw_o_reg_n_0_[18][31] ;
- wire \data_rw_o_reg_n_0_[19][12] ;
- wire \data_rw_o_reg_n_0_[19][13] ;
- wire \data_rw_o_reg_n_0_[19][14] ;
- wire \data_rw_o_reg_n_0_[19][15] ;
- wire \data_rw_o_reg_n_0_[19][16] ;
- wire \data_rw_o_reg_n_0_[19][17] ;
- wire \data_rw_o_reg_n_0_[19][18] ;
- wire \data_rw_o_reg_n_0_[19][19] ;
- wire \data_rw_o_reg_n_0_[19][20] ;
- wire \data_rw_o_reg_n_0_[19][21] ;
- wire \data_rw_o_reg_n_0_[19][22] ;
- wire \data_rw_o_reg_n_0_[19][23] ;
- wire \data_rw_o_reg_n_0_[19][24] ;
- wire \data_rw_o_reg_n_0_[19][25] ;
- wire \data_rw_o_reg_n_0_[19][26] ;
- wire \data_rw_o_reg_n_0_[19][27] ;
- wire \data_rw_o_reg_n_0_[19][28] ;
- wire \data_rw_o_reg_n_0_[19][29] ;
- wire \data_rw_o_reg_n_0_[19][30] ;
- wire \data_rw_o_reg_n_0_[19][31] ;
- wire \data_rw_o_reg_n_0_[20][12] ;
- wire \data_rw_o_reg_n_0_[20][13] ;
- wire \data_rw_o_reg_n_0_[20][14] ;
- wire \data_rw_o_reg_n_0_[20][15] ;
- wire \data_rw_o_reg_n_0_[20][16] ;
- wire \data_rw_o_reg_n_0_[20][17] ;
- wire \data_rw_o_reg_n_0_[20][18] ;
- wire \data_rw_o_reg_n_0_[20][19] ;
- wire \data_rw_o_reg_n_0_[20][20] ;
- wire \data_rw_o_reg_n_0_[20][21] ;
- wire \data_rw_o_reg_n_0_[20][22] ;
- wire \data_rw_o_reg_n_0_[20][23] ;
- wire \data_rw_o_reg_n_0_[20][24] ;
- wire \data_rw_o_reg_n_0_[20][25] ;
- wire \data_rw_o_reg_n_0_[20][26] ;
- wire \data_rw_o_reg_n_0_[20][27] ;
- wire \data_rw_o_reg_n_0_[20][28] ;
- wire \data_rw_o_reg_n_0_[20][29] ;
- wire \data_rw_o_reg_n_0_[20][30] ;
- wire \data_rw_o_reg_n_0_[20][31] ;
- wire \data_rw_o_reg_n_0_[21][12] ;
- wire \data_rw_o_reg_n_0_[21][13] ;
- wire \data_rw_o_reg_n_0_[21][14] ;
- wire \data_rw_o_reg_n_0_[21][15] ;
- wire \data_rw_o_reg_n_0_[21][16] ;
- wire \data_rw_o_reg_n_0_[21][17] ;
- wire \data_rw_o_reg_n_0_[21][18] ;
- wire \data_rw_o_reg_n_0_[21][19] ;
- wire \data_rw_o_reg_n_0_[21][20] ;
- wire \data_rw_o_reg_n_0_[21][21] ;
- wire \data_rw_o_reg_n_0_[21][22] ;
- wire \data_rw_o_reg_n_0_[21][23] ;
- wire \data_rw_o_reg_n_0_[21][24] ;
- wire \data_rw_o_reg_n_0_[21][25] ;
- wire \data_rw_o_reg_n_0_[21][26] ;
- wire \data_rw_o_reg_n_0_[21][27] ;
- wire \data_rw_o_reg_n_0_[21][28] ;
- wire \data_rw_o_reg_n_0_[21][29] ;
- wire \data_rw_o_reg_n_0_[21][30] ;
- wire \data_rw_o_reg_n_0_[21][31] ;
- wire \data_rw_o_reg_n_0_[22][12] ;
- wire \data_rw_o_reg_n_0_[22][13] ;
- wire \data_rw_o_reg_n_0_[22][14] ;
- wire \data_rw_o_reg_n_0_[22][15] ;
- wire \data_rw_o_reg_n_0_[22][16] ;
- wire \data_rw_o_reg_n_0_[22][17] ;
- wire \data_rw_o_reg_n_0_[22][18] ;
- wire \data_rw_o_reg_n_0_[22][19] ;
- wire \data_rw_o_reg_n_0_[22][20] ;
- wire \data_rw_o_reg_n_0_[22][21] ;
- wire \data_rw_o_reg_n_0_[22][22] ;
- wire \data_rw_o_reg_n_0_[22][23] ;
- wire \data_rw_o_reg_n_0_[22][24] ;
- wire \data_rw_o_reg_n_0_[22][25] ;
- wire \data_rw_o_reg_n_0_[22][26] ;
- wire \data_rw_o_reg_n_0_[22][27] ;
- wire \data_rw_o_reg_n_0_[22][28] ;
- wire \data_rw_o_reg_n_0_[22][29] ;
- wire \data_rw_o_reg_n_0_[22][30] ;
- wire \data_rw_o_reg_n_0_[22][31] ;
- wire \data_rw_o_reg_n_0_[23][12] ;
- wire \data_rw_o_reg_n_0_[23][13] ;
- wire \data_rw_o_reg_n_0_[23][14] ;
- wire \data_rw_o_reg_n_0_[23][15] ;
- wire \data_rw_o_reg_n_0_[23][16] ;
- wire \data_rw_o_reg_n_0_[23][17] ;
- wire \data_rw_o_reg_n_0_[23][18] ;
- wire \data_rw_o_reg_n_0_[23][19] ;
- wire \data_rw_o_reg_n_0_[23][20] ;
- wire \data_rw_o_reg_n_0_[23][21] ;
- wire \data_rw_o_reg_n_0_[23][22] ;
- wire \data_rw_o_reg_n_0_[23][23] ;
- wire \data_rw_o_reg_n_0_[23][24] ;
- wire \data_rw_o_reg_n_0_[23][25] ;
- wire \data_rw_o_reg_n_0_[23][26] ;
- wire \data_rw_o_reg_n_0_[23][27] ;
- wire \data_rw_o_reg_n_0_[23][28] ;
- wire \data_rw_o_reg_n_0_[23][29] ;
- wire \data_rw_o_reg_n_0_[23][30] ;
- wire \data_rw_o_reg_n_0_[23][31] ;
- wire \data_rw_o_reg_n_0_[24][12] ;
- wire \data_rw_o_reg_n_0_[24][13] ;
- wire \data_rw_o_reg_n_0_[24][14] ;
- wire \data_rw_o_reg_n_0_[24][15] ;
- wire \data_rw_o_reg_n_0_[24][16] ;
- wire \data_rw_o_reg_n_0_[24][17] ;
- wire \data_rw_o_reg_n_0_[24][18] ;
- wire \data_rw_o_reg_n_0_[24][19] ;
- wire \data_rw_o_reg_n_0_[24][20] ;
- wire \data_rw_o_reg_n_0_[24][21] ;
- wire \data_rw_o_reg_n_0_[24][22] ;
- wire \data_rw_o_reg_n_0_[24][23] ;
- wire \data_rw_o_reg_n_0_[24][24] ;
- wire \data_rw_o_reg_n_0_[24][25] ;
- wire \data_rw_o_reg_n_0_[24][26] ;
- wire \data_rw_o_reg_n_0_[24][27] ;
- wire \data_rw_o_reg_n_0_[24][28] ;
- wire \data_rw_o_reg_n_0_[24][29] ;
- wire \data_rw_o_reg_n_0_[24][30] ;
- wire \data_rw_o_reg_n_0_[24][31] ;
- wire \data_rw_o_reg_n_0_[25][12] ;
- wire \data_rw_o_reg_n_0_[25][13] ;
- wire \data_rw_o_reg_n_0_[25][14] ;
- wire \data_rw_o_reg_n_0_[25][15] ;
- wire \data_rw_o_reg_n_0_[25][16] ;
- wire \data_rw_o_reg_n_0_[25][17] ;
- wire \data_rw_o_reg_n_0_[25][18] ;
- wire \data_rw_o_reg_n_0_[25][19] ;
- wire \data_rw_o_reg_n_0_[25][20] ;
- wire \data_rw_o_reg_n_0_[25][21] ;
- wire \data_rw_o_reg_n_0_[25][22] ;
- wire \data_rw_o_reg_n_0_[25][23] ;
- wire \data_rw_o_reg_n_0_[25][24] ;
- wire \data_rw_o_reg_n_0_[25][25] ;
- wire \data_rw_o_reg_n_0_[25][26] ;
- wire \data_rw_o_reg_n_0_[25][27] ;
- wire \data_rw_o_reg_n_0_[25][28] ;
- wire \data_rw_o_reg_n_0_[25][29] ;
- wire \data_rw_o_reg_n_0_[25][30] ;
- wire \data_rw_o_reg_n_0_[25][31] ;
- wire \data_rw_o_reg_n_0_[26][12] ;
- wire \data_rw_o_reg_n_0_[26][13] ;
- wire \data_rw_o_reg_n_0_[26][14] ;
- wire \data_rw_o_reg_n_0_[26][15] ;
- wire \data_rw_o_reg_n_0_[26][16] ;
- wire \data_rw_o_reg_n_0_[26][17] ;
- wire \data_rw_o_reg_n_0_[26][18] ;
- wire \data_rw_o_reg_n_0_[26][19] ;
- wire \data_rw_o_reg_n_0_[26][20] ;
- wire \data_rw_o_reg_n_0_[26][21] ;
- wire \data_rw_o_reg_n_0_[26][22] ;
- wire \data_rw_o_reg_n_0_[26][23] ;
- wire \data_rw_o_reg_n_0_[26][24] ;
- wire \data_rw_o_reg_n_0_[26][25] ;
- wire \data_rw_o_reg_n_0_[26][26] ;
- wire \data_rw_o_reg_n_0_[26][27] ;
- wire \data_rw_o_reg_n_0_[26][28] ;
- wire \data_rw_o_reg_n_0_[26][29] ;
- wire \data_rw_o_reg_n_0_[26][30] ;
- wire \data_rw_o_reg_n_0_[26][31] ;
- wire \data_rw_o_reg_n_0_[27][12] ;
- wire \data_rw_o_reg_n_0_[27][13] ;
- wire \data_rw_o_reg_n_0_[27][14] ;
- wire \data_rw_o_reg_n_0_[27][15] ;
- wire \data_rw_o_reg_n_0_[27][16] ;
- wire \data_rw_o_reg_n_0_[27][17] ;
- wire \data_rw_o_reg_n_0_[27][18] ;
- wire \data_rw_o_reg_n_0_[27][19] ;
- wire \data_rw_o_reg_n_0_[27][20] ;
- wire \data_rw_o_reg_n_0_[27][21] ;
- wire \data_rw_o_reg_n_0_[27][22] ;
- wire \data_rw_o_reg_n_0_[27][23] ;
- wire \data_rw_o_reg_n_0_[27][24] ;
- wire \data_rw_o_reg_n_0_[27][25] ;
- wire \data_rw_o_reg_n_0_[27][26] ;
- wire \data_rw_o_reg_n_0_[27][27] ;
- wire \data_rw_o_reg_n_0_[27][28] ;
- wire \data_rw_o_reg_n_0_[27][29] ;
- wire \data_rw_o_reg_n_0_[27][30] ;
- wire \data_rw_o_reg_n_0_[27][31] ;
- wire \data_rw_o_reg_n_0_[28][12] ;
- wire \data_rw_o_reg_n_0_[28][13] ;
- wire \data_rw_o_reg_n_0_[28][14] ;
- wire \data_rw_o_reg_n_0_[28][15] ;
- wire \data_rw_o_reg_n_0_[28][16] ;
- wire \data_rw_o_reg_n_0_[28][17] ;
- wire \data_rw_o_reg_n_0_[28][18] ;
- wire \data_rw_o_reg_n_0_[28][19] ;
- wire \data_rw_o_reg_n_0_[28][20] ;
- wire \data_rw_o_reg_n_0_[28][21] ;
- wire \data_rw_o_reg_n_0_[28][22] ;
- wire \data_rw_o_reg_n_0_[28][23] ;
- wire \data_rw_o_reg_n_0_[28][24] ;
- wire \data_rw_o_reg_n_0_[28][25] ;
- wire \data_rw_o_reg_n_0_[28][26] ;
- wire \data_rw_o_reg_n_0_[28][27] ;
- wire \data_rw_o_reg_n_0_[28][28] ;
- wire \data_rw_o_reg_n_0_[28][29] ;
- wire \data_rw_o_reg_n_0_[28][30] ;
- wire \data_rw_o_reg_n_0_[28][31] ;
- wire \data_rw_o_reg_n_0_[29][12] ;
- wire \data_rw_o_reg_n_0_[29][13] ;
- wire \data_rw_o_reg_n_0_[29][14] ;
- wire \data_rw_o_reg_n_0_[29][15] ;
- wire \data_rw_o_reg_n_0_[29][16] ;
- wire \data_rw_o_reg_n_0_[29][17] ;
- wire \data_rw_o_reg_n_0_[29][18] ;
- wire \data_rw_o_reg_n_0_[29][19] ;
- wire \data_rw_o_reg_n_0_[29][20] ;
- wire \data_rw_o_reg_n_0_[29][21] ;
- wire \data_rw_o_reg_n_0_[29][22] ;
- wire \data_rw_o_reg_n_0_[29][23] ;
- wire \data_rw_o_reg_n_0_[29][24] ;
- wire \data_rw_o_reg_n_0_[29][25] ;
- wire \data_rw_o_reg_n_0_[29][26] ;
- wire \data_rw_o_reg_n_0_[29][27] ;
- wire \data_rw_o_reg_n_0_[29][28] ;
- wire \data_rw_o_reg_n_0_[29][29] ;
- wire \data_rw_o_reg_n_0_[29][30] ;
- wire \data_rw_o_reg_n_0_[29][31] ;
- wire \data_rw_o_reg_n_0_[30][12] ;
- wire \data_rw_o_reg_n_0_[30][13] ;
- wire \data_rw_o_reg_n_0_[30][14] ;
- wire \data_rw_o_reg_n_0_[30][15] ;
- wire \data_rw_o_reg_n_0_[30][16] ;
- wire \data_rw_o_reg_n_0_[30][17] ;
- wire \data_rw_o_reg_n_0_[30][18] ;
- wire \data_rw_o_reg_n_0_[30][19] ;
- wire \data_rw_o_reg_n_0_[30][20] ;
- wire \data_rw_o_reg_n_0_[30][21] ;
- wire \data_rw_o_reg_n_0_[30][22] ;
- wire \data_rw_o_reg_n_0_[30][23] ;
- wire \data_rw_o_reg_n_0_[30][24] ;
- wire \data_rw_o_reg_n_0_[30][25] ;
- wire \data_rw_o_reg_n_0_[30][26] ;
- wire \data_rw_o_reg_n_0_[30][27] ;
- wire \data_rw_o_reg_n_0_[30][28] ;
- wire \data_rw_o_reg_n_0_[30][29] ;
- wire \data_rw_o_reg_n_0_[30][30] ;
- wire \data_rw_o_reg_n_0_[30][31] ;
- wire \data_rw_o_reg_n_0_[31][12] ;
- wire \data_rw_o_reg_n_0_[31][13] ;
- wire \data_rw_o_reg_n_0_[31][14] ;
- wire \data_rw_o_reg_n_0_[31][15] ;
- wire \data_rw_o_reg_n_0_[31][16] ;
- wire \data_rw_o_reg_n_0_[31][17] ;
- wire \data_rw_o_reg_n_0_[31][18] ;
- wire \data_rw_o_reg_n_0_[31][19] ;
- wire \data_rw_o_reg_n_0_[31][20] ;
- wire \data_rw_o_reg_n_0_[31][21] ;
- wire \data_rw_o_reg_n_0_[31][22] ;
- wire \data_rw_o_reg_n_0_[31][23] ;
- wire \data_rw_o_reg_n_0_[31][24] ;
- wire \data_rw_o_reg_n_0_[31][25] ;
- wire \data_rw_o_reg_n_0_[31][26] ;
- wire \data_rw_o_reg_n_0_[31][27] ;
- wire \data_rw_o_reg_n_0_[31][28] ;
- wire \data_rw_o_reg_n_0_[31][29] ;
- wire \data_rw_o_reg_n_0_[31][30] ;
- wire \data_rw_o_reg_n_0_[31][31] ;
- wire \data_rw_o_reg_n_0_[32][12] ;
- wire \data_rw_o_reg_n_0_[32][13] ;
- wire \data_rw_o_reg_n_0_[32][14] ;
- wire \data_rw_o_reg_n_0_[32][15] ;
- wire \data_rw_o_reg_n_0_[32][16] ;
- wire \data_rw_o_reg_n_0_[32][17] ;
- wire \data_rw_o_reg_n_0_[32][18] ;
- wire \data_rw_o_reg_n_0_[32][19] ;
- wire \data_rw_o_reg_n_0_[32][20] ;
- wire \data_rw_o_reg_n_0_[32][21] ;
- wire \data_rw_o_reg_n_0_[32][22] ;
- wire \data_rw_o_reg_n_0_[32][23] ;
- wire \data_rw_o_reg_n_0_[32][24] ;
- wire \data_rw_o_reg_n_0_[32][25] ;
- wire \data_rw_o_reg_n_0_[32][26] ;
- wire \data_rw_o_reg_n_0_[32][27] ;
- wire \data_rw_o_reg_n_0_[32][28] ;
- wire \data_rw_o_reg_n_0_[32][29] ;
- wire \data_rw_o_reg_n_0_[32][30] ;
- wire \data_rw_o_reg_n_0_[32][31] ;
- wire \data_rw_o_reg_n_0_[33][12] ;
- wire \data_rw_o_reg_n_0_[33][13] ;
- wire \data_rw_o_reg_n_0_[33][14] ;
- wire \data_rw_o_reg_n_0_[33][15] ;
- wire \data_rw_o_reg_n_0_[33][16] ;
- wire \data_rw_o_reg_n_0_[33][17] ;
- wire \data_rw_o_reg_n_0_[33][18] ;
- wire \data_rw_o_reg_n_0_[33][19] ;
- wire \data_rw_o_reg_n_0_[33][20] ;
- wire \data_rw_o_reg_n_0_[33][21] ;
- wire \data_rw_o_reg_n_0_[33][22] ;
- wire \data_rw_o_reg_n_0_[33][23] ;
- wire \data_rw_o_reg_n_0_[33][24] ;
- wire \data_rw_o_reg_n_0_[33][25] ;
- wire \data_rw_o_reg_n_0_[33][26] ;
- wire \data_rw_o_reg_n_0_[33][27] ;
- wire \data_rw_o_reg_n_0_[33][28] ;
- wire \data_rw_o_reg_n_0_[33][29] ;
- wire \data_rw_o_reg_n_0_[33][30] ;
- wire \data_rw_o_reg_n_0_[33][31] ;
- wire \data_rw_o_reg_n_0_[34][12] ;
- wire \data_rw_o_reg_n_0_[34][13] ;
- wire \data_rw_o_reg_n_0_[34][14] ;
- wire \data_rw_o_reg_n_0_[34][15] ;
- wire \data_rw_o_reg_n_0_[34][16] ;
- wire \data_rw_o_reg_n_0_[34][17] ;
- wire \data_rw_o_reg_n_0_[34][18] ;
- wire \data_rw_o_reg_n_0_[34][19] ;
- wire \data_rw_o_reg_n_0_[34][20] ;
- wire \data_rw_o_reg_n_0_[34][21] ;
- wire \data_rw_o_reg_n_0_[34][22] ;
- wire \data_rw_o_reg_n_0_[34][23] ;
- wire \data_rw_o_reg_n_0_[34][24] ;
- wire \data_rw_o_reg_n_0_[34][25] ;
- wire \data_rw_o_reg_n_0_[34][26] ;
- wire \data_rw_o_reg_n_0_[34][27] ;
- wire \data_rw_o_reg_n_0_[34][28] ;
- wire \data_rw_o_reg_n_0_[34][29] ;
- wire \data_rw_o_reg_n_0_[34][30] ;
- wire \data_rw_o_reg_n_0_[34][31] ;
- wire \data_rw_o_reg_n_0_[35][12] ;
- wire \data_rw_o_reg_n_0_[35][13] ;
- wire \data_rw_o_reg_n_0_[35][14] ;
- wire \data_rw_o_reg_n_0_[35][15] ;
- wire \data_rw_o_reg_n_0_[35][16] ;
- wire \data_rw_o_reg_n_0_[35][17] ;
- wire \data_rw_o_reg_n_0_[35][18] ;
- wire \data_rw_o_reg_n_0_[35][19] ;
- wire \data_rw_o_reg_n_0_[35][20] ;
- wire \data_rw_o_reg_n_0_[35][21] ;
- wire \data_rw_o_reg_n_0_[35][22] ;
- wire \data_rw_o_reg_n_0_[35][23] ;
- wire \data_rw_o_reg_n_0_[35][24] ;
- wire \data_rw_o_reg_n_0_[35][25] ;
- wire \data_rw_o_reg_n_0_[35][26] ;
- wire \data_rw_o_reg_n_0_[35][27] ;
- wire \data_rw_o_reg_n_0_[35][28] ;
- wire \data_rw_o_reg_n_0_[35][29] ;
- wire \data_rw_o_reg_n_0_[35][30] ;
- wire \data_rw_o_reg_n_0_[35][31] ;
- wire \data_rw_o_reg_n_0_[3][10] ;
- wire \data_rw_o_reg_n_0_[3][11] ;
- wire \data_rw_o_reg_n_0_[3][12] ;
- wire \data_rw_o_reg_n_0_[3][13] ;
- wire \data_rw_o_reg_n_0_[3][14] ;
- wire \data_rw_o_reg_n_0_[3][15] ;
- wire \data_rw_o_reg_n_0_[3][16] ;
- wire \data_rw_o_reg_n_0_[3][17] ;
- wire \data_rw_o_reg_n_0_[3][18] ;
- wire \data_rw_o_reg_n_0_[3][19] ;
- wire \data_rw_o_reg_n_0_[3][20] ;
- wire \data_rw_o_reg_n_0_[3][21] ;
- wire \data_rw_o_reg_n_0_[3][22] ;
- wire \data_rw_o_reg_n_0_[3][23] ;
- wire \data_rw_o_reg_n_0_[3][24] ;
- wire \data_rw_o_reg_n_0_[3][25] ;
- wire \data_rw_o_reg_n_0_[3][26] ;
- wire \data_rw_o_reg_n_0_[3][27] ;
- wire \data_rw_o_reg_n_0_[3][28] ;
- wire \data_rw_o_reg_n_0_[3][29] ;
- wire \data_rw_o_reg_n_0_[3][2] ;
- wire \data_rw_o_reg_n_0_[3][30] ;
- wire \data_rw_o_reg_n_0_[3][31] ;
- wire \data_rw_o_reg_n_0_[3][3] ;
- wire \data_rw_o_reg_n_0_[3][4] ;
- wire \data_rw_o_reg_n_0_[3][5] ;
- wire \data_rw_o_reg_n_0_[3][6] ;
- wire \data_rw_o_reg_n_0_[3][7] ;
- wire \data_rw_o_reg_n_0_[3][8] ;
- wire \data_rw_o_reg_n_0_[3][9] ;
- wire \data_rw_o_reg_n_0_[78][0] ;
- wire \data_rw_o_reg_n_0_[78][10] ;
- wire \data_rw_o_reg_n_0_[78][11] ;
- wire \data_rw_o_reg_n_0_[78][12] ;
- wire \data_rw_o_reg_n_0_[78][13] ;
- wire \data_rw_o_reg_n_0_[78][14] ;
- wire \data_rw_o_reg_n_0_[78][15] ;
- wire \data_rw_o_reg_n_0_[78][16] ;
- wire \data_rw_o_reg_n_0_[78][17] ;
- wire \data_rw_o_reg_n_0_[78][18] ;
- wire \data_rw_o_reg_n_0_[78][19] ;
- wire \data_rw_o_reg_n_0_[78][1] ;
- wire \data_rw_o_reg_n_0_[78][20] ;
- wire \data_rw_o_reg_n_0_[78][21] ;
- wire \data_rw_o_reg_n_0_[78][22] ;
- wire \data_rw_o_reg_n_0_[78][23] ;
- wire \data_rw_o_reg_n_0_[78][24] ;
- wire \data_rw_o_reg_n_0_[78][25] ;
- wire \data_rw_o_reg_n_0_[78][26] ;
- wire \data_rw_o_reg_n_0_[78][27] ;
- wire \data_rw_o_reg_n_0_[78][28] ;
- wire \data_rw_o_reg_n_0_[78][29] ;
- wire \data_rw_o_reg_n_0_[78][2] ;
- wire \data_rw_o_reg_n_0_[78][30] ;
- wire \data_rw_o_reg_n_0_[78][31] ;
- wire \data_rw_o_reg_n_0_[78][3] ;
- wire \data_rw_o_reg_n_0_[78][8] ;
- wire \data_rw_o_reg_n_0_[78][9] ;
- wire \data_rw_o_reg_n_0_[79][0] ;
- wire \data_rw_o_reg_n_0_[79][10] ;
- wire \data_rw_o_reg_n_0_[79][11] ;
- wire \data_rw_o_reg_n_0_[79][12] ;
- wire \data_rw_o_reg_n_0_[79][13] ;
- wire \data_rw_o_reg_n_0_[79][14] ;
- wire \data_rw_o_reg_n_0_[79][15] ;
- wire \data_rw_o_reg_n_0_[79][16] ;
- wire \data_rw_o_reg_n_0_[79][17] ;
- wire \data_rw_o_reg_n_0_[79][18] ;
- wire \data_rw_o_reg_n_0_[79][19] ;
- wire \data_rw_o_reg_n_0_[79][20] ;
- wire \data_rw_o_reg_n_0_[79][21] ;
- wire \data_rw_o_reg_n_0_[79][22] ;
- wire \data_rw_o_reg_n_0_[79][23] ;
- wire \data_rw_o_reg_n_0_[79][24] ;
- wire \data_rw_o_reg_n_0_[79][25] ;
- wire \data_rw_o_reg_n_0_[79][26] ;
- wire \data_rw_o_reg_n_0_[79][27] ;
- wire \data_rw_o_reg_n_0_[79][28] ;
- wire \data_rw_o_reg_n_0_[79][29] ;
- wire \data_rw_o_reg_n_0_[79][30] ;
- wire \data_rw_o_reg_n_0_[79][31] ;
- wire \data_rw_o_reg_n_0_[79][3] ;
- wire \data_rw_o_reg_n_0_[79][4] ;
- wire \data_rw_o_reg_n_0_[79][5] ;
- wire \data_rw_o_reg_n_0_[79][6] ;
- wire \data_rw_o_reg_n_0_[79][8] ;
- wire \data_rw_o_reg_n_0_[79][9] ;
- wire \data_rw_o_reg_n_0_[84][12] ;
- wire \data_rw_o_reg_n_0_[84][13] ;
- wire \data_rw_o_reg_n_0_[84][14] ;
- wire \data_rw_o_reg_n_0_[84][15] ;
- wire \data_rw_o_reg_n_0_[84][16] ;
- wire \data_rw_o_reg_n_0_[84][17] ;
- wire \data_rw_o_reg_n_0_[84][18] ;
- wire \data_rw_o_reg_n_0_[84][19] ;
- wire \data_rw_o_reg_n_0_[84][20] ;
- wire \data_rw_o_reg_n_0_[84][21] ;
- wire \data_rw_o_reg_n_0_[84][22] ;
- wire \data_rw_o_reg_n_0_[84][23] ;
- wire \data_rw_o_reg_n_0_[84][24] ;
- wire \data_rw_o_reg_n_0_[84][25] ;
- wire \data_rw_o_reg_n_0_[84][26] ;
- wire \data_rw_o_reg_n_0_[84][27] ;
- wire \data_rw_o_reg_n_0_[84][28] ;
- wire \data_rw_o_reg_n_0_[84][29] ;
- wire \data_rw_o_reg_n_0_[84][30] ;
- wire \data_rw_o_reg_n_0_[84][31] ;
- wire \data_rw_o_reg_n_0_[85][12] ;
- wire \data_rw_o_reg_n_0_[85][13] ;
- wire \data_rw_o_reg_n_0_[85][14] ;
- wire \data_rw_o_reg_n_0_[85][15] ;
- wire \data_rw_o_reg_n_0_[85][16] ;
- wire \data_rw_o_reg_n_0_[85][17] ;
- wire \data_rw_o_reg_n_0_[85][18] ;
- wire \data_rw_o_reg_n_0_[85][19] ;
- wire \data_rw_o_reg_n_0_[85][20] ;
- wire \data_rw_o_reg_n_0_[85][21] ;
- wire \data_rw_o_reg_n_0_[85][22] ;
- wire \data_rw_o_reg_n_0_[85][23] ;
- wire \data_rw_o_reg_n_0_[85][24] ;
- wire \data_rw_o_reg_n_0_[85][25] ;
- wire \data_rw_o_reg_n_0_[85][26] ;
- wire \data_rw_o_reg_n_0_[85][27] ;
- wire \data_rw_o_reg_n_0_[85][28] ;
- wire \data_rw_o_reg_n_0_[85][29] ;
- wire \data_rw_o_reg_n_0_[85][30] ;
- wire \data_rw_o_reg_n_0_[85][31] ;
- wire \data_rw_o_reg_n_0_[86][12] ;
- wire \data_rw_o_reg_n_0_[86][13] ;
- wire \data_rw_o_reg_n_0_[86][14] ;
- wire \data_rw_o_reg_n_0_[86][15] ;
- wire \data_rw_o_reg_n_0_[86][16] ;
- wire \data_rw_o_reg_n_0_[86][17] ;
- wire \data_rw_o_reg_n_0_[86][18] ;
- wire \data_rw_o_reg_n_0_[86][19] ;
- wire \data_rw_o_reg_n_0_[86][20] ;
- wire \data_rw_o_reg_n_0_[86][21] ;
- wire \data_rw_o_reg_n_0_[86][22] ;
- wire \data_rw_o_reg_n_0_[86][23] ;
- wire \data_rw_o_reg_n_0_[86][24] ;
- wire \data_rw_o_reg_n_0_[86][25] ;
- wire \data_rw_o_reg_n_0_[86][26] ;
- wire \data_rw_o_reg_n_0_[86][27] ;
- wire \data_rw_o_reg_n_0_[86][28] ;
- wire \data_rw_o_reg_n_0_[86][29] ;
- wire \data_rw_o_reg_n_0_[86][30] ;
- wire \data_rw_o_reg_n_0_[86][31] ;
- wire \data_rw_o_reg_n_0_[87][12] ;
- wire \data_rw_o_reg_n_0_[87][13] ;
- wire \data_rw_o_reg_n_0_[87][14] ;
- wire \data_rw_o_reg_n_0_[87][15] ;
- wire \data_rw_o_reg_n_0_[87][16] ;
- wire \data_rw_o_reg_n_0_[87][17] ;
- wire \data_rw_o_reg_n_0_[87][18] ;
- wire \data_rw_o_reg_n_0_[87][19] ;
- wire \data_rw_o_reg_n_0_[87][20] ;
- wire \data_rw_o_reg_n_0_[87][21] ;
- wire \data_rw_o_reg_n_0_[87][22] ;
- wire \data_rw_o_reg_n_0_[87][23] ;
- wire \data_rw_o_reg_n_0_[87][24] ;
- wire \data_rw_o_reg_n_0_[87][25] ;
- wire \data_rw_o_reg_n_0_[87][26] ;
- wire \data_rw_o_reg_n_0_[87][27] ;
- wire \data_rw_o_reg_n_0_[87][28] ;
- wire \data_rw_o_reg_n_0_[87][29] ;
- wire \data_rw_o_reg_n_0_[87][30] ;
- wire \data_rw_o_reg_n_0_[87][31] ;
- wire \data_rw_o_reg_n_0_[88][12] ;
- wire \data_rw_o_reg_n_0_[88][13] ;
- wire \data_rw_o_reg_n_0_[88][14] ;
- wire \data_rw_o_reg_n_0_[88][15] ;
- wire \data_rw_o_reg_n_0_[88][16] ;
- wire \data_rw_o_reg_n_0_[88][17] ;
- wire \data_rw_o_reg_n_0_[88][18] ;
- wire \data_rw_o_reg_n_0_[88][19] ;
- wire \data_rw_o_reg_n_0_[88][20] ;
- wire \data_rw_o_reg_n_0_[88][21] ;
- wire \data_rw_o_reg_n_0_[88][22] ;
- wire \data_rw_o_reg_n_0_[88][23] ;
- wire \data_rw_o_reg_n_0_[88][24] ;
- wire \data_rw_o_reg_n_0_[88][25] ;
- wire \data_rw_o_reg_n_0_[88][26] ;
- wire \data_rw_o_reg_n_0_[88][27] ;
- wire \data_rw_o_reg_n_0_[88][28] ;
- wire \data_rw_o_reg_n_0_[88][29] ;
- wire \data_rw_o_reg_n_0_[88][30] ;
- wire \data_rw_o_reg_n_0_[88][31] ;
- wire \data_rw_o_reg_n_0_[89][12] ;
- wire \data_rw_o_reg_n_0_[89][13] ;
- wire \data_rw_o_reg_n_0_[89][14] ;
- wire \data_rw_o_reg_n_0_[89][15] ;
- wire \data_rw_o_reg_n_0_[89][16] ;
- wire \data_rw_o_reg_n_0_[89][17] ;
- wire \data_rw_o_reg_n_0_[89][18] ;
- wire \data_rw_o_reg_n_0_[89][19] ;
- wire \data_rw_o_reg_n_0_[89][20] ;
- wire \data_rw_o_reg_n_0_[89][21] ;
- wire \data_rw_o_reg_n_0_[89][22] ;
- wire \data_rw_o_reg_n_0_[89][23] ;
- wire \data_rw_o_reg_n_0_[89][24] ;
- wire \data_rw_o_reg_n_0_[89][25] ;
- wire \data_rw_o_reg_n_0_[89][26] ;
- wire \data_rw_o_reg_n_0_[89][27] ;
- wire \data_rw_o_reg_n_0_[89][28] ;
- wire \data_rw_o_reg_n_0_[89][29] ;
- wire \data_rw_o_reg_n_0_[89][30] ;
- wire \data_rw_o_reg_n_0_[89][31] ;
- wire \data_rw_o_reg_n_0_[90][12] ;
- wire \data_rw_o_reg_n_0_[90][13] ;
- wire \data_rw_o_reg_n_0_[90][14] ;
- wire \data_rw_o_reg_n_0_[90][15] ;
- wire \data_rw_o_reg_n_0_[90][16] ;
- wire \data_rw_o_reg_n_0_[90][17] ;
- wire \data_rw_o_reg_n_0_[90][18] ;
- wire \data_rw_o_reg_n_0_[90][19] ;
- wire \data_rw_o_reg_n_0_[90][20] ;
- wire \data_rw_o_reg_n_0_[90][21] ;
- wire \data_rw_o_reg_n_0_[90][22] ;
- wire \data_rw_o_reg_n_0_[90][23] ;
- wire \data_rw_o_reg_n_0_[90][24] ;
- wire \data_rw_o_reg_n_0_[90][25] ;
- wire \data_rw_o_reg_n_0_[90][26] ;
- wire \data_rw_o_reg_n_0_[90][27] ;
- wire \data_rw_o_reg_n_0_[90][28] ;
- wire \data_rw_o_reg_n_0_[90][29] ;
- wire \data_rw_o_reg_n_0_[90][30] ;
- wire \data_rw_o_reg_n_0_[90][31] ;
- wire \data_rw_o_reg_n_0_[91][12] ;
- wire \data_rw_o_reg_n_0_[91][13] ;
- wire \data_rw_o_reg_n_0_[91][14] ;
- wire \data_rw_o_reg_n_0_[91][15] ;
- wire \data_rw_o_reg_n_0_[91][16] ;
- wire \data_rw_o_reg_n_0_[91][17] ;
- wire \data_rw_o_reg_n_0_[91][18] ;
- wire \data_rw_o_reg_n_0_[91][19] ;
- wire \data_rw_o_reg_n_0_[91][20] ;
- wire \data_rw_o_reg_n_0_[91][21] ;
- wire \data_rw_o_reg_n_0_[91][22] ;
- wire \data_rw_o_reg_n_0_[91][23] ;
- wire \data_rw_o_reg_n_0_[91][24] ;
- wire \data_rw_o_reg_n_0_[91][25] ;
- wire \data_rw_o_reg_n_0_[91][26] ;
- wire \data_rw_o_reg_n_0_[91][27] ;
- wire \data_rw_o_reg_n_0_[91][28] ;
- wire \data_rw_o_reg_n_0_[91][29] ;
- wire \data_rw_o_reg_n_0_[91][30] ;
- wire \data_rw_o_reg_n_0_[91][31] ;
- wire \data_rw_o_reg_n_0_[92][12] ;
- wire \data_rw_o_reg_n_0_[92][13] ;
- wire \data_rw_o_reg_n_0_[92][14] ;
- wire \data_rw_o_reg_n_0_[92][15] ;
- wire \data_rw_o_reg_n_0_[92][16] ;
- wire \data_rw_o_reg_n_0_[92][17] ;
- wire \data_rw_o_reg_n_0_[92][18] ;
- wire \data_rw_o_reg_n_0_[92][19] ;
- wire \data_rw_o_reg_n_0_[92][20] ;
- wire \data_rw_o_reg_n_0_[92][21] ;
- wire \data_rw_o_reg_n_0_[92][22] ;
- wire \data_rw_o_reg_n_0_[92][23] ;
- wire \data_rw_o_reg_n_0_[92][24] ;
- wire \data_rw_o_reg_n_0_[92][25] ;
- wire \data_rw_o_reg_n_0_[92][26] ;
- wire \data_rw_o_reg_n_0_[92][27] ;
- wire \data_rw_o_reg_n_0_[92][28] ;
- wire \data_rw_o_reg_n_0_[92][29] ;
- wire \data_rw_o_reg_n_0_[92][30] ;
- wire \data_rw_o_reg_n_0_[92][31] ;
- wire \data_rw_o_reg_n_0_[93][12] ;
- wire \data_rw_o_reg_n_0_[93][13] ;
- wire \data_rw_o_reg_n_0_[93][14] ;
- wire \data_rw_o_reg_n_0_[93][15] ;
- wire \data_rw_o_reg_n_0_[93][16] ;
- wire \data_rw_o_reg_n_0_[93][17] ;
- wire \data_rw_o_reg_n_0_[93][18] ;
- wire \data_rw_o_reg_n_0_[93][19] ;
- wire \data_rw_o_reg_n_0_[93][20] ;
- wire \data_rw_o_reg_n_0_[93][21] ;
- wire \data_rw_o_reg_n_0_[93][22] ;
- wire \data_rw_o_reg_n_0_[93][23] ;
- wire \data_rw_o_reg_n_0_[93][24] ;
- wire \data_rw_o_reg_n_0_[93][25] ;
- wire \data_rw_o_reg_n_0_[93][26] ;
- wire \data_rw_o_reg_n_0_[93][27] ;
- wire \data_rw_o_reg_n_0_[93][28] ;
- wire \data_rw_o_reg_n_0_[93][29] ;
- wire \data_rw_o_reg_n_0_[93][30] ;
- wire \data_rw_o_reg_n_0_[93][31] ;
- wire \data_rw_o_reg_n_0_[94][12] ;
- wire \data_rw_o_reg_n_0_[94][13] ;
- wire \data_rw_o_reg_n_0_[94][14] ;
- wire \data_rw_o_reg_n_0_[94][15] ;
- wire \data_rw_o_reg_n_0_[94][16] ;
- wire \data_rw_o_reg_n_0_[94][17] ;
- wire \data_rw_o_reg_n_0_[94][18] ;
- wire \data_rw_o_reg_n_0_[94][19] ;
- wire \data_rw_o_reg_n_0_[94][20] ;
- wire \data_rw_o_reg_n_0_[94][21] ;
- wire \data_rw_o_reg_n_0_[94][22] ;
- wire \data_rw_o_reg_n_0_[94][23] ;
- wire \data_rw_o_reg_n_0_[94][24] ;
- wire \data_rw_o_reg_n_0_[94][25] ;
- wire \data_rw_o_reg_n_0_[94][26] ;
- wire \data_rw_o_reg_n_0_[94][27] ;
- wire \data_rw_o_reg_n_0_[94][28] ;
- wire \data_rw_o_reg_n_0_[94][29] ;
- wire \data_rw_o_reg_n_0_[94][30] ;
- wire \data_rw_o_reg_n_0_[94][31] ;
- wire \data_rw_o_reg_n_0_[95][12] ;
- wire \data_rw_o_reg_n_0_[95][13] ;
- wire \data_rw_o_reg_n_0_[95][14] ;
- wire \data_rw_o_reg_n_0_[95][15] ;
- wire \data_rw_o_reg_n_0_[95][16] ;
- wire \data_rw_o_reg_n_0_[95][17] ;
- wire \data_rw_o_reg_n_0_[95][18] ;
- wire \data_rw_o_reg_n_0_[95][19] ;
- wire \data_rw_o_reg_n_0_[95][20] ;
- wire \data_rw_o_reg_n_0_[95][21] ;
- wire \data_rw_o_reg_n_0_[95][22] ;
- wire \data_rw_o_reg_n_0_[95][23] ;
- wire \data_rw_o_reg_n_0_[95][24] ;
- wire \data_rw_o_reg_n_0_[95][25] ;
- wire \data_rw_o_reg_n_0_[95][26] ;
- wire \data_rw_o_reg_n_0_[95][27] ;
- wire \data_rw_o_reg_n_0_[95][28] ;
- wire \data_rw_o_reg_n_0_[95][29] ;
- wire \data_rw_o_reg_n_0_[95][30] ;
- wire \data_rw_o_reg_n_0_[95][31] ;
- wire \data_rw_o_reg_n_0_[96][12] ;
- wire \data_rw_o_reg_n_0_[96][13] ;
- wire \data_rw_o_reg_n_0_[96][14] ;
- wire \data_rw_o_reg_n_0_[96][15] ;
- wire \data_rw_o_reg_n_0_[96][16] ;
- wire \data_rw_o_reg_n_0_[96][17] ;
- wire \data_rw_o_reg_n_0_[96][18] ;
- wire \data_rw_o_reg_n_0_[96][19] ;
- wire \data_rw_o_reg_n_0_[96][20] ;
- wire \data_rw_o_reg_n_0_[96][21] ;
- wire \data_rw_o_reg_n_0_[96][22] ;
- wire \data_rw_o_reg_n_0_[96][23] ;
- wire \data_rw_o_reg_n_0_[96][24] ;
- wire \data_rw_o_reg_n_0_[96][25] ;
- wire \data_rw_o_reg_n_0_[96][26] ;
- wire \data_rw_o_reg_n_0_[96][27] ;
- wire \data_rw_o_reg_n_0_[96][28] ;
- wire \data_rw_o_reg_n_0_[96][29] ;
- wire \data_rw_o_reg_n_0_[96][30] ;
- wire \data_rw_o_reg_n_0_[96][31] ;
- wire \data_rw_o_reg_n_0_[97][12] ;
- wire \data_rw_o_reg_n_0_[97][13] ;
- wire \data_rw_o_reg_n_0_[97][14] ;
- wire \data_rw_o_reg_n_0_[97][15] ;
- wire \data_rw_o_reg_n_0_[97][16] ;
- wire \data_rw_o_reg_n_0_[97][17] ;
- wire \data_rw_o_reg_n_0_[97][18] ;
- wire \data_rw_o_reg_n_0_[97][19] ;
- wire \data_rw_o_reg_n_0_[97][20] ;
- wire \data_rw_o_reg_n_0_[97][21] ;
- wire \data_rw_o_reg_n_0_[97][22] ;
- wire \data_rw_o_reg_n_0_[97][23] ;
- wire \data_rw_o_reg_n_0_[97][24] ;
- wire \data_rw_o_reg_n_0_[97][25] ;
- wire \data_rw_o_reg_n_0_[97][26] ;
- wire \data_rw_o_reg_n_0_[97][27] ;
- wire \data_rw_o_reg_n_0_[97][28] ;
- wire \data_rw_o_reg_n_0_[97][29] ;
- wire \data_rw_o_reg_n_0_[97][30] ;
- wire \data_rw_o_reg_n_0_[97][31] ;
- wire \data_rw_o_reg_n_0_[98][12] ;
- wire \data_rw_o_reg_n_0_[98][13] ;
- wire \data_rw_o_reg_n_0_[98][14] ;
- wire \data_rw_o_reg_n_0_[98][15] ;
- wire \data_rw_o_reg_n_0_[98][16] ;
- wire \data_rw_o_reg_n_0_[98][17] ;
- wire \data_rw_o_reg_n_0_[98][18] ;
- wire \data_rw_o_reg_n_0_[98][19] ;
- wire \data_rw_o_reg_n_0_[98][20] ;
- wire \data_rw_o_reg_n_0_[98][21] ;
- wire \data_rw_o_reg_n_0_[98][22] ;
- wire \data_rw_o_reg_n_0_[98][23] ;
- wire \data_rw_o_reg_n_0_[98][24] ;
- wire \data_rw_o_reg_n_0_[98][25] ;
- wire \data_rw_o_reg_n_0_[98][26] ;
- wire \data_rw_o_reg_n_0_[98][27] ;
- wire \data_rw_o_reg_n_0_[98][28] ;
- wire \data_rw_o_reg_n_0_[98][29] ;
- wire \data_rw_o_reg_n_0_[98][30] ;
- wire \data_rw_o_reg_n_0_[98][31] ;
- wire \data_rw_o_reg_n_0_[99][12] ;
- wire \data_rw_o_reg_n_0_[99][13] ;
- wire \data_rw_o_reg_n_0_[99][14] ;
- wire \data_rw_o_reg_n_0_[99][15] ;
- wire \data_rw_o_reg_n_0_[99][16] ;
- wire \data_rw_o_reg_n_0_[99][17] ;
- wire \data_rw_o_reg_n_0_[99][18] ;
- wire \data_rw_o_reg_n_0_[99][19] ;
- wire \data_rw_o_reg_n_0_[99][20] ;
- wire \data_rw_o_reg_n_0_[99][21] ;
- wire \data_rw_o_reg_n_0_[99][22] ;
- wire \data_rw_o_reg_n_0_[99][23] ;
- wire \data_rw_o_reg_n_0_[99][24] ;
- wire \data_rw_o_reg_n_0_[99][25] ;
- wire \data_rw_o_reg_n_0_[99][26] ;
- wire \data_rw_o_reg_n_0_[99][27] ;
- wire \data_rw_o_reg_n_0_[99][28] ;
- wire \data_rw_o_reg_n_0_[99][29] ;
- wire \data_rw_o_reg_n_0_[99][30] ;
- wire \data_rw_o_reg_n_0_[99][31] ;
- wire dig_out6_n;
- wire [0:0]dig_outs_i;
- wire \fmc_03287_channels[11].gen_chs.data_o_reg[59][20] ;
- wire \fmc_03287_channels[11].gen_chs.data_o_reg[59][21] ;
- wire \fmc_03287_channels[11].gen_chs.data_o_reg[59][22] ;
- wire \fmc_03287_channels[11].gen_chs.data_o_reg[59][23] ;
- wire \fmc_03287_channels[15].gen_chs.data_o_reg[63][20] ;
- wire \fmc_03287_channels[15].gen_chs.data_o_reg[63][21] ;
- wire \fmc_03287_channels[15].gen_chs.data_o_reg[63][22] ;
- wire \fmc_03287_channels[15].gen_chs.data_o_reg[63][23] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][0] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][10] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][11] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][12] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][13] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][14] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][15] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][16] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][17] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][18] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][19] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][1] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][20] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][21] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][22] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][23] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][2] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][3] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][4] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][5] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][6] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][7] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][8] ;
- wire \fmc_03287_channels[19].gen_chs.data_o_reg[67][9] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][0] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][0]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][10] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][10]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][11] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][11]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][12] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][12]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][13] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][13]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][14] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][14]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][15] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][15]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][16] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][16]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][17] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][17]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][18] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][18]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][19] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][19]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][1] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][1]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][20] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][20]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][21] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][21]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][22] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][22]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][23] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][2] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][2]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][3] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][3]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][4] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][4]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][5] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][5]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][6] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][6]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][7] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][7]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][8] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][8]_0 ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][9] ;
- wire \fmc_03287_channels[3].gen_chs.data_o_reg[51][9]_0 ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][0] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][10] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][11] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][12] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][13] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][14] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][15] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][16] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][17] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][18] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][19] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][1] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][20] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][21] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][22] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][23] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][2] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][3] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][4] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][5] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][6] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][7] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][8] ;
- wire \fmc_03287_channels[7].gen_chs.data_o_reg[55][9] ;
- wire [15:0]gem_status_vector_i;
- wire rst_i;
- wire s00_axi_aclk;
- wire [8:0]s00_axi_araddr;
- wire s00_axi_aresetn;
- wire s00_axi_arready;
- wire s00_axi_arvalid;
- wire [7:0]s00_axi_awaddr;
- wire s00_axi_awready;
- wire s00_axi_awvalid;
- wire s00_axi_bready;
- wire [0:0]s00_axi_bresp;
- wire s00_axi_bvalid;
- wire [31:0]s00_axi_rdata;
- wire s00_axi_rready;
- wire [0:0]s00_axi_rresp;
- wire s00_axi_rvalid;
- wire [31:0]s00_axi_wdata;
- wire s00_axi_wready;
- wire [3:0]s00_axi_wstrb;
- wire s00_axi_wvalid;
- wire [19:0]\s_datao_fmc1[0] ;
- wire [11:0]\s_datao_fmc1[4] ;
- wire [19:0]\s_datao_fmc2[0] ;
- wire [11:0]\s_datao_fmc2[4] ;
- wire [3:0]\s_ins_reg[3] ;
- wire s_tick;
- wire [7:0]sel0;
- wire \v_dout_reg[4] ;
- wire \v_dout_reg[4]_0 ;
- wire \v_dout_reg[5] ;
- wire \v_dout_reg[5]_0 ;
- wire \v_dout_reg[6] ;
- wire \v_dout_reg[6]_0 ;
- wire [2:0]\v_dout_reg[7] ;
- wire [2:0]\v_dout_reg[7]_0 ;
- wire \v_dout_reg[7]_1 ;
- wire \v_dout_reg[7]_2 ;
- wire [3:0]\NLW_[0].[0].s_reqs_reg[0][changed]_i_2_O_UNCONNECTED ;
- wire [3:0]\NLW_[0].[0].s_reqs_reg[0][changed]_i_2__0_O_UNCONNECTED ;
- wire [3:0]\NLW_[0].[1].s_reqs_reg[1][changed]_i_2_O_UNCONNECTED ;
- wire [3:0]\NLW_[0].[1].s_reqs_reg[1][changed]_i_2__0_O_UNCONNECTED ;
- wire [3:0]\NLW_[0].[2].s_reqs_reg[2][changed]_i_2_O_UNCONNECTED ;
- wire [3:0]\NLW_[0].[2].s_reqs_reg[2][changed]_i_2__0_O_UNCONNECTED ;
- wire [3:0]\NLW_[0].[3].s_reqs_reg[3][changed]_i_2_O_UNCONNECTED ;
- wire [3:0]\NLW_[0].[3].s_reqs_reg[3][changed]_i_2__0_O_UNCONNECTED ;
- wire [3:0]\NLW_[1].[0].s_reqs_reg[4][changed]_i_2_O_UNCONNECTED ;
- wire [3:0]\NLW_[1].[0].s_reqs_reg[4][changed]_i_2__0_O_UNCONNECTED ;
- wire [3:0]\NLW_[1].[1].s_reqs_reg[5][changed]_i_2_O_UNCONNECTED ;
- wire [3:0]\NLW_[1].[1].s_reqs_reg[5][changed]_i_2__0_O_UNCONNECTED ;
- wire [3:0]\NLW_[1].[2].s_reqs_reg[6][changed]_i_2_O_UNCONNECTED ;
- wire [3:0]\NLW_[1].[2].s_reqs_reg[6][changed]_i_2__0_O_UNCONNECTED ;
- wire [3:0]\NLW_[1].[3].s_reqs_reg[7][changed]_i_2_O_UNCONNECTED ;
- wire [3:0]\NLW_[1].[3].s_reqs_reg[7][changed]_i_2__0_O_UNCONNECTED ;
-
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[0].s_reqs[0][changed]_i_3
- (.I0(\[0].[0].s_reqs_reg[0][value][11] [11]),
- .I1(\[0].[0].s_reqs_reg[0][value][11]_1 [11]),
- .I2(\[0].[0].s_reqs_reg[0][value][11] [10]),
- .I3(\[0].[0].s_reqs_reg[0][value][11]_1 [10]),
- .I4(\[0].[0].s_reqs_reg[0][value][11]_1 [9]),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [9]),
- .O(\[0].[0].s_reqs[0][changed]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[0].s_reqs[0][changed]_i_3__0
- (.I0(\[0].[0].s_reqs_reg[0][value][11]_0 [11]),
- .I1(\[0].[0].s_reqs_reg[0][value][11]_2 [11]),
- .I2(\[0].[0].s_reqs_reg[0][value][11]_0 [10]),
- .I3(\[0].[0].s_reqs_reg[0][value][11]_2 [10]),
- .I4(\[0].[0].s_reqs_reg[0][value][11]_2 [9]),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [9]),
- .O(\[0].[0].s_reqs[0][changed]_i_3__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[0].s_reqs[0][changed]_i_4
- (.I0(\[0].[0].s_reqs_reg[0][value][11] [8]),
- .I1(\[0].[0].s_reqs_reg[0][value][11]_1 [8]),
- .I2(\[0].[0].s_reqs_reg[0][value][11] [7]),
- .I3(\[0].[0].s_reqs_reg[0][value][11]_1 [7]),
- .I4(\[0].[0].s_reqs_reg[0][value][11]_1 [6]),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [6]),
- .O(\[0].[0].s_reqs[0][changed]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[0].s_reqs[0][changed]_i_4__0
- (.I0(\[0].[0].s_reqs_reg[0][value][11]_0 [8]),
- .I1(\[0].[0].s_reqs_reg[0][value][11]_2 [8]),
- .I2(\[0].[0].s_reqs_reg[0][value][11]_0 [7]),
- .I3(\[0].[0].s_reqs_reg[0][value][11]_2 [7]),
- .I4(\[0].[0].s_reqs_reg[0][value][11]_2 [6]),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [6]),
- .O(\[0].[0].s_reqs[0][changed]_i_4__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[0].s_reqs[0][changed]_i_5
- (.I0(\[0].[0].s_reqs_reg[0][value][11] [5]),
- .I1(\[0].[0].s_reqs_reg[0][value][11]_1 [5]),
- .I2(\[0].[0].s_reqs_reg[0][value][11] [4]),
- .I3(\[0].[0].s_reqs_reg[0][value][11]_1 [4]),
- .I4(\[0].[0].s_reqs_reg[0][value][11]_1 [3]),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [3]),
- .O(\[0].[0].s_reqs[0][changed]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[0].s_reqs[0][changed]_i_5__0
- (.I0(\[0].[0].s_reqs_reg[0][value][11]_0 [5]),
- .I1(\[0].[0].s_reqs_reg[0][value][11]_2 [5]),
- .I2(\[0].[0].s_reqs_reg[0][value][11]_0 [4]),
- .I3(\[0].[0].s_reqs_reg[0][value][11]_2 [4]),
- .I4(\[0].[0].s_reqs_reg[0][value][11]_2 [3]),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [3]),
- .O(\[0].[0].s_reqs[0][changed]_i_5__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[0].s_reqs[0][changed]_i_6
- (.I0(\[0].[0].s_reqs_reg[0][value][11] [2]),
- .I1(\[0].[0].s_reqs_reg[0][value][11]_1 [2]),
- .I2(\[0].[0].s_reqs_reg[0][value][11] [1]),
- .I3(\[0].[0].s_reqs_reg[0][value][11]_1 [1]),
- .I4(\[0].[0].s_reqs_reg[0][value][11]_1 [0]),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [0]),
- .O(\[0].[0].s_reqs[0][changed]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[0].s_reqs[0][changed]_i_6__0
- (.I0(\[0].[0].s_reqs_reg[0][value][11]_0 [2]),
- .I1(\[0].[0].s_reqs_reg[0][value][11]_2 [2]),
- .I2(\[0].[0].s_reqs_reg[0][value][11]_0 [1]),
- .I3(\[0].[0].s_reqs_reg[0][value][11]_2 [1]),
- .I4(\[0].[0].s_reqs_reg[0][value][11]_2 [0]),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [0]),
- .O(\[0].[0].s_reqs[0][changed]_i_6__0_n_0 ));
- CARRY4 \[0].[0].s_reqs_reg[0][changed]_i_2
- (.CI(1'b0),
- .CO({\[0].[0].s_reqs_reg[0][changed] ,\[0].[0].s_reqs_reg[0][changed]_i_2_n_1 ,\[0].[0].s_reqs_reg[0][changed]_i_2_n_2 ,\[0].[0].s_reqs_reg[0][changed]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[0].[0].s_reqs_reg[0][changed]_i_2_O_UNCONNECTED [3:0]),
- .S({\[0].[0].s_reqs[0][changed]_i_3_n_0 ,\[0].[0].s_reqs[0][changed]_i_4_n_0 ,\[0].[0].s_reqs[0][changed]_i_5_n_0 ,\[0].[0].s_reqs[0][changed]_i_6_n_0 }));
- CARRY4 \[0].[0].s_reqs_reg[0][changed]_i_2__0
- (.CI(1'b0),
- .CO({\[0].[0].s_reqs_reg[0][changed]_0 ,\[0].[0].s_reqs_reg[0][changed]_i_2__0_n_1 ,\[0].[0].s_reqs_reg[0][changed]_i_2__0_n_2 ,\[0].[0].s_reqs_reg[0][changed]_i_2__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[0].[0].s_reqs_reg[0][changed]_i_2__0_O_UNCONNECTED [3:0]),
- .S({\[0].[0].s_reqs[0][changed]_i_3__0_n_0 ,\[0].[0].s_reqs[0][changed]_i_4__0_n_0 ,\[0].[0].s_reqs[0][changed]_i_5__0_n_0 ,\[0].[0].s_reqs[0][changed]_i_6__0_n_0 }));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[1].s_reqs[1][changed]_i_3
- (.I0(\[0].[1].s_reqs_reg[1][value][11] [11]),
- .I1(\[0].[1].s_reqs_reg[1][value][11]_1 [11]),
- .I2(\[0].[1].s_reqs_reg[1][value][11] [10]),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_1 [10]),
- .I4(\[0].[1].s_reqs_reg[1][value][11]_1 [9]),
- .I5(\[0].[1].s_reqs_reg[1][value][11] [9]),
- .O(\[0].[1].s_reqs[1][changed]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[1].s_reqs[1][changed]_i_3__0
- (.I0(\[0].[1].s_reqs_reg[1][value][11]_0 [11]),
- .I1(\[0].[1].s_reqs_reg[1][value][11]_2 [11]),
- .I2(\[0].[1].s_reqs_reg[1][value][11]_0 [10]),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_2 [10]),
- .I4(\[0].[1].s_reqs_reg[1][value][11]_2 [9]),
- .I5(\[0].[1].s_reqs_reg[1][value][11]_0 [9]),
- .O(\[0].[1].s_reqs[1][changed]_i_3__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[1].s_reqs[1][changed]_i_4
- (.I0(\[0].[1].s_reqs_reg[1][value][11] [8]),
- .I1(\[0].[1].s_reqs_reg[1][value][11]_1 [8]),
- .I2(\[0].[1].s_reqs_reg[1][value][11] [7]),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_1 [7]),
- .I4(\[0].[1].s_reqs_reg[1][value][11]_1 [6]),
- .I5(\[0].[1].s_reqs_reg[1][value][11] [6]),
- .O(\[0].[1].s_reqs[1][changed]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[1].s_reqs[1][changed]_i_4__0
- (.I0(\[0].[1].s_reqs_reg[1][value][11]_0 [8]),
- .I1(\[0].[1].s_reqs_reg[1][value][11]_2 [8]),
- .I2(\[0].[1].s_reqs_reg[1][value][11]_0 [7]),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_2 [7]),
- .I4(\[0].[1].s_reqs_reg[1][value][11]_2 [6]),
- .I5(\[0].[1].s_reqs_reg[1][value][11]_0 [6]),
- .O(\[0].[1].s_reqs[1][changed]_i_4__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[1].s_reqs[1][changed]_i_5
- (.I0(\[0].[1].s_reqs_reg[1][value][11] [5]),
- .I1(\[0].[1].s_reqs_reg[1][value][11]_1 [5]),
- .I2(\[0].[1].s_reqs_reg[1][value][11] [4]),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_1 [4]),
- .I4(\[0].[1].s_reqs_reg[1][value][11]_1 [3]),
- .I5(\[0].[1].s_reqs_reg[1][value][11] [3]),
- .O(\[0].[1].s_reqs[1][changed]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[1].s_reqs[1][changed]_i_5__0
- (.I0(\[0].[1].s_reqs_reg[1][value][11]_0 [5]),
- .I1(\[0].[1].s_reqs_reg[1][value][11]_2 [5]),
- .I2(\[0].[1].s_reqs_reg[1][value][11]_0 [4]),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_2 [4]),
- .I4(\[0].[1].s_reqs_reg[1][value][11]_2 [3]),
- .I5(\[0].[1].s_reqs_reg[1][value][11]_0 [3]),
- .O(\[0].[1].s_reqs[1][changed]_i_5__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[1].s_reqs[1][changed]_i_6
- (.I0(\[0].[1].s_reqs_reg[1][value][11] [2]),
- .I1(\[0].[1].s_reqs_reg[1][value][11]_1 [2]),
- .I2(\[0].[1].s_reqs_reg[1][value][11] [1]),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_1 [1]),
- .I4(\[0].[1].s_reqs_reg[1][value][11]_1 [0]),
- .I5(\[0].[1].s_reqs_reg[1][value][11] [0]),
- .O(\[0].[1].s_reqs[1][changed]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[1].s_reqs[1][changed]_i_6__0
- (.I0(\[0].[1].s_reqs_reg[1][value][11]_0 [2]),
- .I1(\[0].[1].s_reqs_reg[1][value][11]_2 [2]),
- .I2(\[0].[1].s_reqs_reg[1][value][11]_0 [1]),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_2 [1]),
- .I4(\[0].[1].s_reqs_reg[1][value][11]_2 [0]),
- .I5(\[0].[1].s_reqs_reg[1][value][11]_0 [0]),
- .O(\[0].[1].s_reqs[1][changed]_i_6__0_n_0 ));
- CARRY4 \[0].[1].s_reqs_reg[1][changed]_i_2
- (.CI(1'b0),
- .CO({\[0].[1].s_reqs_reg[1][changed] ,\[0].[1].s_reqs_reg[1][changed]_i_2_n_1 ,\[0].[1].s_reqs_reg[1][changed]_i_2_n_2 ,\[0].[1].s_reqs_reg[1][changed]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[0].[1].s_reqs_reg[1][changed]_i_2_O_UNCONNECTED [3:0]),
- .S({\[0].[1].s_reqs[1][changed]_i_3_n_0 ,\[0].[1].s_reqs[1][changed]_i_4_n_0 ,\[0].[1].s_reqs[1][changed]_i_5_n_0 ,\[0].[1].s_reqs[1][changed]_i_6_n_0 }));
- CARRY4 \[0].[1].s_reqs_reg[1][changed]_i_2__0
- (.CI(1'b0),
- .CO({\[0].[1].s_reqs_reg[1][changed]_0 ,\[0].[1].s_reqs_reg[1][changed]_i_2__0_n_1 ,\[0].[1].s_reqs_reg[1][changed]_i_2__0_n_2 ,\[0].[1].s_reqs_reg[1][changed]_i_2__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[0].[1].s_reqs_reg[1][changed]_i_2__0_O_UNCONNECTED [3:0]),
- .S({\[0].[1].s_reqs[1][changed]_i_3__0_n_0 ,\[0].[1].s_reqs[1][changed]_i_4__0_n_0 ,\[0].[1].s_reqs[1][changed]_i_5__0_n_0 ,\[0].[1].s_reqs[1][changed]_i_6__0_n_0 }));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[2].s_reqs[2][changed]_i_3
- (.I0(\[0].[2].s_reqs_reg[2][value][11] [11]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_1 [11]),
- .I2(\[0].[2].s_reqs_reg[2][value][11] [10]),
- .I3(\[0].[2].s_reqs_reg[2][value][11]_1 [10]),
- .I4(\[0].[2].s_reqs_reg[2][value][11]_1 [9]),
- .I5(\[0].[2].s_reqs_reg[2][value][11] [9]),
- .O(\[0].[2].s_reqs[2][changed]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[2].s_reqs[2][changed]_i_3__0
- (.I0(\[0].[2].s_reqs_reg[2][value][11]_0 [11]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_2 [11]),
- .I2(\[0].[2].s_reqs_reg[2][value][11]_0 [10]),
- .I3(\[0].[2].s_reqs_reg[2][value][11]_2 [10]),
- .I4(\[0].[2].s_reqs_reg[2][value][11]_2 [9]),
- .I5(\[0].[2].s_reqs_reg[2][value][11]_0 [9]),
- .O(\[0].[2].s_reqs[2][changed]_i_3__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[2].s_reqs[2][changed]_i_4
- (.I0(\[0].[2].s_reqs_reg[2][value][11] [8]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_1 [8]),
- .I2(\[0].[2].s_reqs_reg[2][value][11] [7]),
- .I3(\[0].[2].s_reqs_reg[2][value][11]_1 [7]),
- .I4(\[0].[2].s_reqs_reg[2][value][11]_1 [6]),
- .I5(\[0].[2].s_reqs_reg[2][value][11] [6]),
- .O(\[0].[2].s_reqs[2][changed]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[2].s_reqs[2][changed]_i_4__0
- (.I0(\[0].[2].s_reqs_reg[2][value][11]_0 [8]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_2 [8]),
- .I2(\[0].[2].s_reqs_reg[2][value][11]_0 [7]),
- .I3(\[0].[2].s_reqs_reg[2][value][11]_2 [7]),
- .I4(\[0].[2].s_reqs_reg[2][value][11]_2 [6]),
- .I5(\[0].[2].s_reqs_reg[2][value][11]_0 [6]),
- .O(\[0].[2].s_reqs[2][changed]_i_4__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[2].s_reqs[2][changed]_i_5
- (.I0(\[0].[2].s_reqs_reg[2][value][11] [5]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_1 [5]),
- .I2(\[0].[2].s_reqs_reg[2][value][11] [4]),
- .I3(\[0].[2].s_reqs_reg[2][value][11]_1 [4]),
- .I4(\[0].[2].s_reqs_reg[2][value][11]_1 [3]),
- .I5(\[0].[2].s_reqs_reg[2][value][11] [3]),
- .O(\[0].[2].s_reqs[2][changed]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[2].s_reqs[2][changed]_i_5__0
- (.I0(\[0].[2].s_reqs_reg[2][value][11]_0 [5]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_2 [5]),
- .I2(\[0].[2].s_reqs_reg[2][value][11]_0 [4]),
- .I3(\[0].[2].s_reqs_reg[2][value][11]_2 [4]),
- .I4(\[0].[2].s_reqs_reg[2][value][11]_2 [3]),
- .I5(\[0].[2].s_reqs_reg[2][value][11]_0 [3]),
- .O(\[0].[2].s_reqs[2][changed]_i_5__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[2].s_reqs[2][changed]_i_6
- (.I0(\[0].[2].s_reqs_reg[2][value][11] [2]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_1 [2]),
- .I2(\[0].[2].s_reqs_reg[2][value][11] [1]),
- .I3(\[0].[2].s_reqs_reg[2][value][11]_1 [1]),
- .I4(\[0].[2].s_reqs_reg[2][value][11]_1 [0]),
- .I5(\[0].[2].s_reqs_reg[2][value][11] [0]),
- .O(\[0].[2].s_reqs[2][changed]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[2].s_reqs[2][changed]_i_6__0
- (.I0(\[0].[2].s_reqs_reg[2][value][11]_0 [2]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_2 [2]),
- .I2(\[0].[2].s_reqs_reg[2][value][11]_0 [1]),
- .I3(\[0].[2].s_reqs_reg[2][value][11]_2 [1]),
- .I4(\[0].[2].s_reqs_reg[2][value][11]_2 [0]),
- .I5(\[0].[2].s_reqs_reg[2][value][11]_0 [0]),
- .O(\[0].[2].s_reqs[2][changed]_i_6__0_n_0 ));
- CARRY4 \[0].[2].s_reqs_reg[2][changed]_i_2
- (.CI(1'b0),
- .CO({\[0].[2].s_reqs_reg[2][changed] ,\[0].[2].s_reqs_reg[2][changed]_i_2_n_1 ,\[0].[2].s_reqs_reg[2][changed]_i_2_n_2 ,\[0].[2].s_reqs_reg[2][changed]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[0].[2].s_reqs_reg[2][changed]_i_2_O_UNCONNECTED [3:0]),
- .S({\[0].[2].s_reqs[2][changed]_i_3_n_0 ,\[0].[2].s_reqs[2][changed]_i_4_n_0 ,\[0].[2].s_reqs[2][changed]_i_5_n_0 ,\[0].[2].s_reqs[2][changed]_i_6_n_0 }));
- CARRY4 \[0].[2].s_reqs_reg[2][changed]_i_2__0
- (.CI(1'b0),
- .CO({\[0].[2].s_reqs_reg[2][changed]_0 ,\[0].[2].s_reqs_reg[2][changed]_i_2__0_n_1 ,\[0].[2].s_reqs_reg[2][changed]_i_2__0_n_2 ,\[0].[2].s_reqs_reg[2][changed]_i_2__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[0].[2].s_reqs_reg[2][changed]_i_2__0_O_UNCONNECTED [3:0]),
- .S({\[0].[2].s_reqs[2][changed]_i_3__0_n_0 ,\[0].[2].s_reqs[2][changed]_i_4__0_n_0 ,\[0].[2].s_reqs[2][changed]_i_5__0_n_0 ,\[0].[2].s_reqs[2][changed]_i_6__0_n_0 }));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[3].s_reqs[3][changed]_i_3
- (.I0(Q[11]),
- .I1(\[0].[3].s_reqs_reg[3][value][11]_0 [11]),
- .I2(Q[10]),
- .I3(\[0].[3].s_reqs_reg[3][value][11]_0 [10]),
- .I4(\[0].[3].s_reqs_reg[3][value][11]_0 [9]),
- .I5(Q[9]),
- .O(\[0].[3].s_reqs[3][changed]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[3].s_reqs[3][changed]_i_3__0
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [11]),
- .I1(\[0].[3].s_reqs_reg[3][value][11]_1 [11]),
- .I2(\[0].[3].s_reqs_reg[3][value][11] [10]),
- .I3(\[0].[3].s_reqs_reg[3][value][11]_1 [10]),
- .I4(\[0].[3].s_reqs_reg[3][value][11]_1 [9]),
- .I5(\[0].[3].s_reqs_reg[3][value][11] [9]),
- .O(\[0].[3].s_reqs[3][changed]_i_3__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[3].s_reqs[3][changed]_i_4
- (.I0(Q[8]),
- .I1(\[0].[3].s_reqs_reg[3][value][11]_0 [8]),
- .I2(Q[7]),
- .I3(\[0].[3].s_reqs_reg[3][value][11]_0 [7]),
- .I4(\[0].[3].s_reqs_reg[3][value][11]_0 [6]),
- .I5(Q[6]),
- .O(\[0].[3].s_reqs[3][changed]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[3].s_reqs[3][changed]_i_4__0
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [8]),
- .I1(\[0].[3].s_reqs_reg[3][value][11]_1 [8]),
- .I2(\[0].[3].s_reqs_reg[3][value][11] [7]),
- .I3(\[0].[3].s_reqs_reg[3][value][11]_1 [7]),
- .I4(\[0].[3].s_reqs_reg[3][value][11]_1 [6]),
- .I5(\[0].[3].s_reqs_reg[3][value][11] [6]),
- .O(\[0].[3].s_reqs[3][changed]_i_4__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[3].s_reqs[3][changed]_i_5
- (.I0(Q[5]),
- .I1(\[0].[3].s_reqs_reg[3][value][11]_0 [5]),
- .I2(Q[4]),
- .I3(\[0].[3].s_reqs_reg[3][value][11]_0 [4]),
- .I4(\[0].[3].s_reqs_reg[3][value][11]_0 [3]),
- .I5(Q[3]),
- .O(\[0].[3].s_reqs[3][changed]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[3].s_reqs[3][changed]_i_5__0
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [5]),
- .I1(\[0].[3].s_reqs_reg[3][value][11]_1 [5]),
- .I2(\[0].[3].s_reqs_reg[3][value][11] [4]),
- .I3(\[0].[3].s_reqs_reg[3][value][11]_1 [4]),
- .I4(\[0].[3].s_reqs_reg[3][value][11]_1 [3]),
- .I5(\[0].[3].s_reqs_reg[3][value][11] [3]),
- .O(\[0].[3].s_reqs[3][changed]_i_5__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[3].s_reqs[3][changed]_i_6
- (.I0(Q[2]),
- .I1(\[0].[3].s_reqs_reg[3][value][11]_0 [2]),
- .I2(Q[1]),
- .I3(\[0].[3].s_reqs_reg[3][value][11]_0 [1]),
- .I4(\[0].[3].s_reqs_reg[3][value][11]_0 [0]),
- .I5(Q[0]),
- .O(\[0].[3].s_reqs[3][changed]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[0].[3].s_reqs[3][changed]_i_6__0
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [2]),
- .I1(\[0].[3].s_reqs_reg[3][value][11]_1 [2]),
- .I2(\[0].[3].s_reqs_reg[3][value][11] [1]),
- .I3(\[0].[3].s_reqs_reg[3][value][11]_1 [1]),
- .I4(\[0].[3].s_reqs_reg[3][value][11]_1 [0]),
- .I5(\[0].[3].s_reqs_reg[3][value][11] [0]),
- .O(\[0].[3].s_reqs[3][changed]_i_6__0_n_0 ));
- CARRY4 \[0].[3].s_reqs_reg[3][changed]_i_2
- (.CI(1'b0),
- .CO({CO,\[0].[3].s_reqs_reg[3][changed]_i_2_n_1 ,\[0].[3].s_reqs_reg[3][changed]_i_2_n_2 ,\[0].[3].s_reqs_reg[3][changed]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[0].[3].s_reqs_reg[3][changed]_i_2_O_UNCONNECTED [3:0]),
- .S({\[0].[3].s_reqs[3][changed]_i_3_n_0 ,\[0].[3].s_reqs[3][changed]_i_4_n_0 ,\[0].[3].s_reqs[3][changed]_i_5_n_0 ,\[0].[3].s_reqs[3][changed]_i_6_n_0 }));
- CARRY4 \[0].[3].s_reqs_reg[3][changed]_i_2__0
- (.CI(1'b0),
- .CO({\[0].[3].s_reqs_reg[3][changed] ,\[0].[3].s_reqs_reg[3][changed]_i_2__0_n_1 ,\[0].[3].s_reqs_reg[3][changed]_i_2__0_n_2 ,\[0].[3].s_reqs_reg[3][changed]_i_2__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[0].[3].s_reqs_reg[3][changed]_i_2__0_O_UNCONNECTED [3:0]),
- .S({\[0].[3].s_reqs[3][changed]_i_3__0_n_0 ,\[0].[3].s_reqs[3][changed]_i_4__0_n_0 ,\[0].[3].s_reqs[3][changed]_i_5__0_n_0 ,\[0].[3].s_reqs[3][changed]_i_6__0_n_0 }));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[0].s_reqs[4][changed]_i_3
- (.I0(\[1].[0].s_reqs_reg[4][value][11] [11]),
- .I1(\[1].[0].s_reqs_reg[4][value][11]_1 [11]),
- .I2(\[1].[0].s_reqs_reg[4][value][11] [10]),
- .I3(\[1].[0].s_reqs_reg[4][value][11]_1 [10]),
- .I4(\[1].[0].s_reqs_reg[4][value][11]_1 [9]),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [9]),
- .O(\[1].[0].s_reqs[4][changed]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[0].s_reqs[4][changed]_i_3__0
- (.I0(\[1].[0].s_reqs_reg[4][value][11]_0 [11]),
- .I1(\[1].[0].s_reqs_reg[4][value][11]_2 [11]),
- .I2(\[1].[0].s_reqs_reg[4][value][11]_0 [10]),
- .I3(\[1].[0].s_reqs_reg[4][value][11]_2 [10]),
- .I4(\[1].[0].s_reqs_reg[4][value][11]_2 [9]),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [9]),
- .O(\[1].[0].s_reqs[4][changed]_i_3__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[0].s_reqs[4][changed]_i_4
- (.I0(\[1].[0].s_reqs_reg[4][value][11] [8]),
- .I1(\[1].[0].s_reqs_reg[4][value][11]_1 [8]),
- .I2(\[1].[0].s_reqs_reg[4][value][11] [7]),
- .I3(\[1].[0].s_reqs_reg[4][value][11]_1 [7]),
- .I4(\[1].[0].s_reqs_reg[4][value][11]_1 [6]),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [6]),
- .O(\[1].[0].s_reqs[4][changed]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[0].s_reqs[4][changed]_i_4__0
- (.I0(\[1].[0].s_reqs_reg[4][value][11]_0 [8]),
- .I1(\[1].[0].s_reqs_reg[4][value][11]_2 [8]),
- .I2(\[1].[0].s_reqs_reg[4][value][11]_0 [7]),
- .I3(\[1].[0].s_reqs_reg[4][value][11]_2 [7]),
- .I4(\[1].[0].s_reqs_reg[4][value][11]_2 [6]),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [6]),
- .O(\[1].[0].s_reqs[4][changed]_i_4__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[0].s_reqs[4][changed]_i_5
- (.I0(\[1].[0].s_reqs_reg[4][value][11] [5]),
- .I1(\[1].[0].s_reqs_reg[4][value][11]_1 [5]),
- .I2(\[1].[0].s_reqs_reg[4][value][11] [4]),
- .I3(\[1].[0].s_reqs_reg[4][value][11]_1 [4]),
- .I4(\[1].[0].s_reqs_reg[4][value][11]_1 [3]),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [3]),
- .O(\[1].[0].s_reqs[4][changed]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[0].s_reqs[4][changed]_i_5__0
- (.I0(\[1].[0].s_reqs_reg[4][value][11]_0 [5]),
- .I1(\[1].[0].s_reqs_reg[4][value][11]_2 [5]),
- .I2(\[1].[0].s_reqs_reg[4][value][11]_0 [4]),
- .I3(\[1].[0].s_reqs_reg[4][value][11]_2 [4]),
- .I4(\[1].[0].s_reqs_reg[4][value][11]_2 [3]),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [3]),
- .O(\[1].[0].s_reqs[4][changed]_i_5__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[0].s_reqs[4][changed]_i_6
- (.I0(\[1].[0].s_reqs_reg[4][value][11] [2]),
- .I1(\[1].[0].s_reqs_reg[4][value][11]_1 [2]),
- .I2(\[1].[0].s_reqs_reg[4][value][11] [1]),
- .I3(\[1].[0].s_reqs_reg[4][value][11]_1 [1]),
- .I4(\[1].[0].s_reqs_reg[4][value][11]_1 [0]),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [0]),
- .O(\[1].[0].s_reqs[4][changed]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[0].s_reqs[4][changed]_i_6__0
- (.I0(\[1].[0].s_reqs_reg[4][value][11]_0 [2]),
- .I1(\[1].[0].s_reqs_reg[4][value][11]_2 [2]),
- .I2(\[1].[0].s_reqs_reg[4][value][11]_0 [1]),
- .I3(\[1].[0].s_reqs_reg[4][value][11]_2 [1]),
- .I4(\[1].[0].s_reqs_reg[4][value][11]_2 [0]),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [0]),
- .O(\[1].[0].s_reqs[4][changed]_i_6__0_n_0 ));
- CARRY4 \[1].[0].s_reqs_reg[4][changed]_i_2
- (.CI(1'b0),
- .CO({\[1].[0].s_reqs_reg[4][changed] ,\[1].[0].s_reqs_reg[4][changed]_i_2_n_1 ,\[1].[0].s_reqs_reg[4][changed]_i_2_n_2 ,\[1].[0].s_reqs_reg[4][changed]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[1].[0].s_reqs_reg[4][changed]_i_2_O_UNCONNECTED [3:0]),
- .S({\[1].[0].s_reqs[4][changed]_i_3_n_0 ,\[1].[0].s_reqs[4][changed]_i_4_n_0 ,\[1].[0].s_reqs[4][changed]_i_5_n_0 ,\[1].[0].s_reqs[4][changed]_i_6_n_0 }));
- CARRY4 \[1].[0].s_reqs_reg[4][changed]_i_2__0
- (.CI(1'b0),
- .CO({\[1].[0].s_reqs_reg[4][changed]_0 ,\[1].[0].s_reqs_reg[4][changed]_i_2__0_n_1 ,\[1].[0].s_reqs_reg[4][changed]_i_2__0_n_2 ,\[1].[0].s_reqs_reg[4][changed]_i_2__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[1].[0].s_reqs_reg[4][changed]_i_2__0_O_UNCONNECTED [3:0]),
- .S({\[1].[0].s_reqs[4][changed]_i_3__0_n_0 ,\[1].[0].s_reqs[4][changed]_i_4__0_n_0 ,\[1].[0].s_reqs[4][changed]_i_5__0_n_0 ,\[1].[0].s_reqs[4][changed]_i_6__0_n_0 }));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[1].s_reqs[5][changed]_i_3
- (.I0(\[1].[1].s_reqs_reg[5][value][11] [11]),
- .I1(\[1].[1].s_reqs_reg[5][value][11]_1 [11]),
- .I2(\[1].[1].s_reqs_reg[5][value][11] [10]),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_1 [10]),
- .I4(\[1].[1].s_reqs_reg[5][value][11]_1 [9]),
- .I5(\[1].[1].s_reqs_reg[5][value][11] [9]),
- .O(\[1].[1].s_reqs[5][changed]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[1].s_reqs[5][changed]_i_3__0
- (.I0(\[1].[1].s_reqs_reg[5][value][11]_0 [11]),
- .I1(\[1].[1].s_reqs_reg[5][value][11]_2 [11]),
- .I2(\[1].[1].s_reqs_reg[5][value][11]_0 [10]),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_2 [10]),
- .I4(\[1].[1].s_reqs_reg[5][value][11]_2 [9]),
- .I5(\[1].[1].s_reqs_reg[5][value][11]_0 [9]),
- .O(\[1].[1].s_reqs[5][changed]_i_3__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[1].s_reqs[5][changed]_i_4
- (.I0(\[1].[1].s_reqs_reg[5][value][11] [8]),
- .I1(\[1].[1].s_reqs_reg[5][value][11]_1 [8]),
- .I2(\[1].[1].s_reqs_reg[5][value][11] [7]),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_1 [7]),
- .I4(\[1].[1].s_reqs_reg[5][value][11]_1 [6]),
- .I5(\[1].[1].s_reqs_reg[5][value][11] [6]),
- .O(\[1].[1].s_reqs[5][changed]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[1].s_reqs[5][changed]_i_4__0
- (.I0(\[1].[1].s_reqs_reg[5][value][11]_0 [8]),
- .I1(\[1].[1].s_reqs_reg[5][value][11]_2 [8]),
- .I2(\[1].[1].s_reqs_reg[5][value][11]_0 [7]),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_2 [7]),
- .I4(\[1].[1].s_reqs_reg[5][value][11]_2 [6]),
- .I5(\[1].[1].s_reqs_reg[5][value][11]_0 [6]),
- .O(\[1].[1].s_reqs[5][changed]_i_4__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[1].s_reqs[5][changed]_i_5
- (.I0(\[1].[1].s_reqs_reg[5][value][11] [5]),
- .I1(\[1].[1].s_reqs_reg[5][value][11]_1 [5]),
- .I2(\[1].[1].s_reqs_reg[5][value][11] [4]),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_1 [4]),
- .I4(\[1].[1].s_reqs_reg[5][value][11]_1 [3]),
- .I5(\[1].[1].s_reqs_reg[5][value][11] [3]),
- .O(\[1].[1].s_reqs[5][changed]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[1].s_reqs[5][changed]_i_5__0
- (.I0(\[1].[1].s_reqs_reg[5][value][11]_0 [5]),
- .I1(\[1].[1].s_reqs_reg[5][value][11]_2 [5]),
- .I2(\[1].[1].s_reqs_reg[5][value][11]_0 [4]),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_2 [4]),
- .I4(\[1].[1].s_reqs_reg[5][value][11]_2 [3]),
- .I5(\[1].[1].s_reqs_reg[5][value][11]_0 [3]),
- .O(\[1].[1].s_reqs[5][changed]_i_5__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[1].s_reqs[5][changed]_i_6
- (.I0(\[1].[1].s_reqs_reg[5][value][11] [2]),
- .I1(\[1].[1].s_reqs_reg[5][value][11]_1 [2]),
- .I2(\[1].[1].s_reqs_reg[5][value][11] [1]),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_1 [1]),
- .I4(\[1].[1].s_reqs_reg[5][value][11]_1 [0]),
- .I5(\[1].[1].s_reqs_reg[5][value][11] [0]),
- .O(\[1].[1].s_reqs[5][changed]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[1].s_reqs[5][changed]_i_6__0
- (.I0(\[1].[1].s_reqs_reg[5][value][11]_0 [2]),
- .I1(\[1].[1].s_reqs_reg[5][value][11]_2 [2]),
- .I2(\[1].[1].s_reqs_reg[5][value][11]_0 [1]),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_2 [1]),
- .I4(\[1].[1].s_reqs_reg[5][value][11]_2 [0]),
- .I5(\[1].[1].s_reqs_reg[5][value][11]_0 [0]),
- .O(\[1].[1].s_reqs[5][changed]_i_6__0_n_0 ));
- CARRY4 \[1].[1].s_reqs_reg[5][changed]_i_2
- (.CI(1'b0),
- .CO({\[1].[1].s_reqs_reg[5][changed] ,\[1].[1].s_reqs_reg[5][changed]_i_2_n_1 ,\[1].[1].s_reqs_reg[5][changed]_i_2_n_2 ,\[1].[1].s_reqs_reg[5][changed]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[1].[1].s_reqs_reg[5][changed]_i_2_O_UNCONNECTED [3:0]),
- .S({\[1].[1].s_reqs[5][changed]_i_3_n_0 ,\[1].[1].s_reqs[5][changed]_i_4_n_0 ,\[1].[1].s_reqs[5][changed]_i_5_n_0 ,\[1].[1].s_reqs[5][changed]_i_6_n_0 }));
- CARRY4 \[1].[1].s_reqs_reg[5][changed]_i_2__0
- (.CI(1'b0),
- .CO({\[1].[1].s_reqs_reg[5][changed]_0 ,\[1].[1].s_reqs_reg[5][changed]_i_2__0_n_1 ,\[1].[1].s_reqs_reg[5][changed]_i_2__0_n_2 ,\[1].[1].s_reqs_reg[5][changed]_i_2__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[1].[1].s_reqs_reg[5][changed]_i_2__0_O_UNCONNECTED [3:0]),
- .S({\[1].[1].s_reqs[5][changed]_i_3__0_n_0 ,\[1].[1].s_reqs[5][changed]_i_4__0_n_0 ,\[1].[1].s_reqs[5][changed]_i_5__0_n_0 ,\[1].[1].s_reqs[5][changed]_i_6__0_n_0 }));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[2].s_reqs[6][changed]_i_3
- (.I0(\[1].[2].s_reqs_reg[6][value][11] [11]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_1 [11]),
- .I2(\[1].[2].s_reqs_reg[6][value][11] [10]),
- .I3(\[1].[2].s_reqs_reg[6][value][11]_1 [10]),
- .I4(\[1].[2].s_reqs_reg[6][value][11]_1 [9]),
- .I5(\[1].[2].s_reqs_reg[6][value][11] [9]),
- .O(\[1].[2].s_reqs[6][changed]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[2].s_reqs[6][changed]_i_3__0
- (.I0(\[1].[2].s_reqs_reg[6][value][11]_0 [11]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_2 [11]),
- .I2(\[1].[2].s_reqs_reg[6][value][11]_0 [10]),
- .I3(\[1].[2].s_reqs_reg[6][value][11]_2 [10]),
- .I4(\[1].[2].s_reqs_reg[6][value][11]_2 [9]),
- .I5(\[1].[2].s_reqs_reg[6][value][11]_0 [9]),
- .O(\[1].[2].s_reqs[6][changed]_i_3__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[2].s_reqs[6][changed]_i_4
- (.I0(\[1].[2].s_reqs_reg[6][value][11] [8]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_1 [8]),
- .I2(\[1].[2].s_reqs_reg[6][value][11] [7]),
- .I3(\[1].[2].s_reqs_reg[6][value][11]_1 [7]),
- .I4(\[1].[2].s_reqs_reg[6][value][11]_1 [6]),
- .I5(\[1].[2].s_reqs_reg[6][value][11] [6]),
- .O(\[1].[2].s_reqs[6][changed]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[2].s_reqs[6][changed]_i_4__0
- (.I0(\[1].[2].s_reqs_reg[6][value][11]_0 [8]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_2 [8]),
- .I2(\[1].[2].s_reqs_reg[6][value][11]_0 [7]),
- .I3(\[1].[2].s_reqs_reg[6][value][11]_2 [7]),
- .I4(\[1].[2].s_reqs_reg[6][value][11]_2 [6]),
- .I5(\[1].[2].s_reqs_reg[6][value][11]_0 [6]),
- .O(\[1].[2].s_reqs[6][changed]_i_4__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[2].s_reqs[6][changed]_i_5
- (.I0(\[1].[2].s_reqs_reg[6][value][11] [5]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_1 [5]),
- .I2(\[1].[2].s_reqs_reg[6][value][11] [4]),
- .I3(\[1].[2].s_reqs_reg[6][value][11]_1 [4]),
- .I4(\[1].[2].s_reqs_reg[6][value][11]_1 [3]),
- .I5(\[1].[2].s_reqs_reg[6][value][11] [3]),
- .O(\[1].[2].s_reqs[6][changed]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[2].s_reqs[6][changed]_i_5__0
- (.I0(\[1].[2].s_reqs_reg[6][value][11]_0 [5]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_2 [5]),
- .I2(\[1].[2].s_reqs_reg[6][value][11]_0 [4]),
- .I3(\[1].[2].s_reqs_reg[6][value][11]_2 [4]),
- .I4(\[1].[2].s_reqs_reg[6][value][11]_2 [3]),
- .I5(\[1].[2].s_reqs_reg[6][value][11]_0 [3]),
- .O(\[1].[2].s_reqs[6][changed]_i_5__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[2].s_reqs[6][changed]_i_6
- (.I0(\[1].[2].s_reqs_reg[6][value][11] [2]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_1 [2]),
- .I2(\[1].[2].s_reqs_reg[6][value][11] [1]),
- .I3(\[1].[2].s_reqs_reg[6][value][11]_1 [1]),
- .I4(\[1].[2].s_reqs_reg[6][value][11]_1 [0]),
- .I5(\[1].[2].s_reqs_reg[6][value][11] [0]),
- .O(\[1].[2].s_reqs[6][changed]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[2].s_reqs[6][changed]_i_6__0
- (.I0(\[1].[2].s_reqs_reg[6][value][11]_0 [2]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_2 [2]),
- .I2(\[1].[2].s_reqs_reg[6][value][11]_0 [1]),
- .I3(\[1].[2].s_reqs_reg[6][value][11]_2 [1]),
- .I4(\[1].[2].s_reqs_reg[6][value][11]_2 [0]),
- .I5(\[1].[2].s_reqs_reg[6][value][11]_0 [0]),
- .O(\[1].[2].s_reqs[6][changed]_i_6__0_n_0 ));
- CARRY4 \[1].[2].s_reqs_reg[6][changed]_i_2
- (.CI(1'b0),
- .CO({\[1].[2].s_reqs_reg[6][changed] ,\[1].[2].s_reqs_reg[6][changed]_i_2_n_1 ,\[1].[2].s_reqs_reg[6][changed]_i_2_n_2 ,\[1].[2].s_reqs_reg[6][changed]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[1].[2].s_reqs_reg[6][changed]_i_2_O_UNCONNECTED [3:0]),
- .S({\[1].[2].s_reqs[6][changed]_i_3_n_0 ,\[1].[2].s_reqs[6][changed]_i_4_n_0 ,\[1].[2].s_reqs[6][changed]_i_5_n_0 ,\[1].[2].s_reqs[6][changed]_i_6_n_0 }));
- CARRY4 \[1].[2].s_reqs_reg[6][changed]_i_2__0
- (.CI(1'b0),
- .CO({\[1].[2].s_reqs_reg[6][changed]_0 ,\[1].[2].s_reqs_reg[6][changed]_i_2__0_n_1 ,\[1].[2].s_reqs_reg[6][changed]_i_2__0_n_2 ,\[1].[2].s_reqs_reg[6][changed]_i_2__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[1].[2].s_reqs_reg[6][changed]_i_2__0_O_UNCONNECTED [3:0]),
- .S({\[1].[2].s_reqs[6][changed]_i_3__0_n_0 ,\[1].[2].s_reqs[6][changed]_i_4__0_n_0 ,\[1].[2].s_reqs[6][changed]_i_5__0_n_0 ,\[1].[2].s_reqs[6][changed]_i_6__0_n_0 }));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[3].s_reqs[7][changed]_i_3
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [11]),
- .I1(\[1].[3].s_reqs_reg[7][value][11]_1 [11]),
- .I2(\[1].[3].s_reqs_reg[7][value][11] [10]),
- .I3(\[1].[3].s_reqs_reg[7][value][11]_1 [10]),
- .I4(\[1].[3].s_reqs_reg[7][value][11]_1 [9]),
- .I5(\[1].[3].s_reqs_reg[7][value][11] [9]),
- .O(\[1].[3].s_reqs[7][changed]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[3].s_reqs[7][changed]_i_3__0
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [11]),
- .I1(\[1].[3].s_reqs_reg[7][value][11]_2 [11]),
- .I2(\[1].[3].s_reqs_reg[7][value][11]_0 [10]),
- .I3(\[1].[3].s_reqs_reg[7][value][11]_2 [10]),
- .I4(\[1].[3].s_reqs_reg[7][value][11]_2 [9]),
- .I5(\[1].[3].s_reqs_reg[7][value][11]_0 [9]),
- .O(\[1].[3].s_reqs[7][changed]_i_3__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[3].s_reqs[7][changed]_i_4
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [8]),
- .I1(\[1].[3].s_reqs_reg[7][value][11]_1 [8]),
- .I2(\[1].[3].s_reqs_reg[7][value][11] [7]),
- .I3(\[1].[3].s_reqs_reg[7][value][11]_1 [7]),
- .I4(\[1].[3].s_reqs_reg[7][value][11]_1 [6]),
- .I5(\[1].[3].s_reqs_reg[7][value][11] [6]),
- .O(\[1].[3].s_reqs[7][changed]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[3].s_reqs[7][changed]_i_4__0
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [8]),
- .I1(\[1].[3].s_reqs_reg[7][value][11]_2 [8]),
- .I2(\[1].[3].s_reqs_reg[7][value][11]_0 [7]),
- .I3(\[1].[3].s_reqs_reg[7][value][11]_2 [7]),
- .I4(\[1].[3].s_reqs_reg[7][value][11]_2 [6]),
- .I5(\[1].[3].s_reqs_reg[7][value][11]_0 [6]),
- .O(\[1].[3].s_reqs[7][changed]_i_4__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[3].s_reqs[7][changed]_i_5
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [5]),
- .I1(\[1].[3].s_reqs_reg[7][value][11]_1 [5]),
- .I2(\[1].[3].s_reqs_reg[7][value][11] [4]),
- .I3(\[1].[3].s_reqs_reg[7][value][11]_1 [4]),
- .I4(\[1].[3].s_reqs_reg[7][value][11]_1 [3]),
- .I5(\[1].[3].s_reqs_reg[7][value][11] [3]),
- .O(\[1].[3].s_reqs[7][changed]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[3].s_reqs[7][changed]_i_5__0
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [5]),
- .I1(\[1].[3].s_reqs_reg[7][value][11]_2 [5]),
- .I2(\[1].[3].s_reqs_reg[7][value][11]_0 [4]),
- .I3(\[1].[3].s_reqs_reg[7][value][11]_2 [4]),
- .I4(\[1].[3].s_reqs_reg[7][value][11]_2 [3]),
- .I5(\[1].[3].s_reqs_reg[7][value][11]_0 [3]),
- .O(\[1].[3].s_reqs[7][changed]_i_5__0_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[3].s_reqs[7][changed]_i_6
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [2]),
- .I1(\[1].[3].s_reqs_reg[7][value][11]_1 [2]),
- .I2(\[1].[3].s_reqs_reg[7][value][11] [1]),
- .I3(\[1].[3].s_reqs_reg[7][value][11]_1 [1]),
- .I4(\[1].[3].s_reqs_reg[7][value][11]_1 [0]),
- .I5(\[1].[3].s_reqs_reg[7][value][11] [0]),
- .O(\[1].[3].s_reqs[7][changed]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- \[1].[3].s_reqs[7][changed]_i_6__0
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [2]),
- .I1(\[1].[3].s_reqs_reg[7][value][11]_2 [2]),
- .I2(\[1].[3].s_reqs_reg[7][value][11]_0 [1]),
- .I3(\[1].[3].s_reqs_reg[7][value][11]_2 [1]),
- .I4(\[1].[3].s_reqs_reg[7][value][11]_2 [0]),
- .I5(\[1].[3].s_reqs_reg[7][value][11]_0 [0]),
- .O(\[1].[3].s_reqs[7][changed]_i_6__0_n_0 ));
- CARRY4 \[1].[3].s_reqs_reg[7][changed]_i_2
- (.CI(1'b0),
- .CO({\[1].[3].s_reqs_reg[7][changed] ,\[1].[3].s_reqs_reg[7][changed]_i_2_n_1 ,\[1].[3].s_reqs_reg[7][changed]_i_2_n_2 ,\[1].[3].s_reqs_reg[7][changed]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[1].[3].s_reqs_reg[7][changed]_i_2_O_UNCONNECTED [3:0]),
- .S({\[1].[3].s_reqs[7][changed]_i_3_n_0 ,\[1].[3].s_reqs[7][changed]_i_4_n_0 ,\[1].[3].s_reqs[7][changed]_i_5_n_0 ,\[1].[3].s_reqs[7][changed]_i_6_n_0 }));
- CARRY4 \[1].[3].s_reqs_reg[7][changed]_i_2__0
- (.CI(1'b0),
- .CO({\[1].[3].s_reqs_reg[7][changed]_0 ,\[1].[3].s_reqs_reg[7][changed]_i_2__0_n_1 ,\[1].[3].s_reqs_reg[7][changed]_i_2__0_n_2 ,\[1].[3].s_reqs_reg[7][changed]_i_2__0_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(\NLW_[1].[3].s_reqs_reg[7][changed]_i_2__0_O_UNCONNECTED [3:0]),
- .S({\[1].[3].s_reqs[7][changed]_i_3__0_n_0 ,\[1].[3].s_reqs[7][changed]_i_4__0_n_0 ,\[1].[3].s_reqs[7][changed]_i_5__0_n_0 ,\[1].[3].s_reqs[7][changed]_i_6__0_n_0 }));
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[10]
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[8]),
- .Q(axi_araddr[10]),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[2]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[2]
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[0]),
- .Q(\axi_rdata_reg[23]_0 [0]),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[2]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[2]_rep
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[0]),
- .Q(\axi_rdata_reg[22]_1 ),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[2]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[2]_rep__0
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[0]),
- .Q(\axi_rdata_reg[17]_1 ),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[2]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[2]_rep__1
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[0]),
- .Q(\axi_rdata_reg[12]_0 ),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[2]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[2]_rep__2
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[0]),
- .Q(\axi_rdata_reg[7]_1 ),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[2]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[2]_rep__3
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[0]),
- .Q(\axi_rdata_reg[2]_1 ),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[3]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[3]
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[1]),
- .Q(\axi_rdata_reg[23]_0 [1]),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[3]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[3]_rep
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[1]),
- .Q(\axi_rdata_reg[22]_0 ),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[3]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[3]_rep__0
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[1]),
- .Q(\axi_rdata_reg[17]_0 ),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[3]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[3]_rep__1
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[1]),
- .Q(\axi_rdata_reg[12]_1 ),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[3]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[3]_rep__2
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[1]),
- .Q(\axi_rdata_reg[7]_0 ),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[3]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[3]_rep__3
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[1]),
- .Q(\axi_rdata_reg[2]_0 ),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[4]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[4]
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[2]),
- .Q(\axi_rdata_reg[23]_0 [2]),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[4]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[4]_rep
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[2]),
- .Q(\axi_rdata_reg[18]_0 ),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[4]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[4]_rep__0
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[2]),
- .Q(\axi_rdata_reg[9]_0 ),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[4]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[4]_rep__1
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[2]),
- .Q(\axi_rdata_reg[0]_0 ),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[5]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[5]
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[3]),
- .Q(\axi_rdata_reg[23]_0 [3]),
- .R(rst_i));
- (* ORIG_CELL_NAME = "axi_araddr_reg[5]" *)
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[5]_rep
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[3]),
- .Q(\axi_rdata_reg[10]_0 ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[6]
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[4]),
- .Q(axi_araddr[6]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[7]
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[5]),
- .Q(axi_araddr[7]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[8]
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[6]),
- .Q(axi_araddr[8]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \axi_araddr_reg[9]
- (.C(s00_axi_aclk),
- .CE(axi_arready_i_1_n_0),
- .D(s00_axi_araddr[7]),
- .Q(axi_araddr[9]),
- .R(rst_i));
- LUT2 #(
- .INIT(4'h2))
- axi_arready_i_1
- (.I0(s00_axi_arvalid),
- .I1(s00_axi_arready),
- .O(axi_arready_i_1_n_0));
- FDRE axi_arready_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(axi_arready_i_1_n_0),
- .Q(s00_axi_arready),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \axi_awaddr_reg[2]
- (.C(s00_axi_aclk),
- .CE(axi_awready_i_2_n_0),
- .D(s00_axi_awaddr[0]),
- .Q(sel0[0]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \axi_awaddr_reg[3]
- (.C(s00_axi_aclk),
- .CE(axi_awready_i_2_n_0),
- .D(s00_axi_awaddr[1]),
- .Q(sel0[1]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \axi_awaddr_reg[4]
- (.C(s00_axi_aclk),
- .CE(axi_awready_i_2_n_0),
- .D(s00_axi_awaddr[2]),
- .Q(sel0[2]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \axi_awaddr_reg[5]
- (.C(s00_axi_aclk),
- .CE(axi_awready_i_2_n_0),
- .D(s00_axi_awaddr[3]),
- .Q(sel0[3]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \axi_awaddr_reg[6]
- (.C(s00_axi_aclk),
- .CE(axi_awready_i_2_n_0),
- .D(s00_axi_awaddr[4]),
- .Q(sel0[4]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \axi_awaddr_reg[7]
- (.C(s00_axi_aclk),
- .CE(axi_awready_i_2_n_0),
- .D(s00_axi_awaddr[5]),
- .Q(sel0[5]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \axi_awaddr_reg[8]
- (.C(s00_axi_aclk),
- .CE(axi_awready_i_2_n_0),
- .D(s00_axi_awaddr[6]),
- .Q(sel0[6]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \axi_awaddr_reg[9]
- (.C(s00_axi_aclk),
- .CE(axi_awready_i_2_n_0),
- .D(s00_axi_awaddr[7]),
- .Q(sel0[7]),
- .R(rst_i));
- LUT3 #(
- .INIT(8'h08))
- axi_awready_i_2
- (.I0(s00_axi_awvalid),
- .I1(s00_axi_wvalid),
- .I2(s00_axi_awready),
- .O(axi_awready_i_2_n_0));
- FDRE axi_awready_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(axi_awready_i_2_n_0),
- .Q(s00_axi_awready),
- .R(rst_i));
- LUT6 #(
- .INIT(64'h002AFF2A00000000))
- \axi_bresp[1]_i_1
- (.I0(s00_axi_bresp),
- .I1(s00_axi_bvalid),
- .I2(s00_axi_bready),
- .I3(axi_bvalid04_out),
- .I4(\axi_bresp[1]_i_3_n_0 ),
- .I5(s00_axi_aresetn),
- .O(\axi_bresp[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT5 #(
- .INIT(32'h20000000))
- \axi_bresp[1]_i_2
- (.I0(s00_axi_awready),
- .I1(s00_axi_bvalid),
- .I2(s00_axi_wready),
- .I3(s00_axi_wvalid),
- .I4(s00_axi_awvalid),
- .O(axi_bvalid04_out));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT4 #(
- .INIT(16'h01FF))
- \axi_bresp[1]_i_3
- (.I0(sel0[5]),
- .I1(sel0[4]),
- .I2(sel0[6]),
- .I3(sel0[7]),
- .O(\axi_bresp[1]_i_3_n_0 ));
- FDRE \axi_bresp_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\axi_bresp[1]_i_1_n_0 ),
- .Q(s00_axi_bresp),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h0000FFFF80008000))
- axi_bvalid_i_1
- (.I0(s00_axi_awvalid),
- .I1(s00_axi_wvalid),
- .I2(s00_axi_wready),
- .I3(s00_axi_awready),
- .I4(s00_axi_bready),
- .I5(s00_axi_bvalid),
- .O(axi_bvalid_i_1_n_0));
- FDRE axi_bvalid_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(axi_bvalid_i_1_n_0),
- .Q(s00_axi_bvalid),
- .R(rst_i));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[0]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[0]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[0]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_rep_10 ),
- .O(\axi_rdata[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hEE55FA00EE00FA00))
- \axi_rdata[0]_i_14
- (.I0(\axi_rdata_reg[0]_0 ),
- .I1(\data_rw_o[3] [0]),
- .I2(gem_status_vector_i[0]),
- .I3(\axi_rdata_reg[2]_0 ),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\s_ins_reg[3] [0]),
- .O(\axi_rdata[0]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[0]_i_17
- (.I0(\axi_rdata[0]_i_35_n_0 ),
- .I1(\axi_rdata_reg[0]_0 ),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [0]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\axi_rdata_reg[10]_0 ),
- .O(\axi_rdata[0]_i_17_n_0 ));
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[0]_i_23
- (.I0(\axi_rdata_reg[2]_0 ),
- .I1(\dac_ch_o_reg[0][31] [0]),
- .I2(\axi_rdata_reg[2]_1 ),
- .I3(\axi_rdata_reg[0]_0 ),
- .O(\axi_rdata[0]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_29
- (.I0(\[2].[3].s_reqs_reg[11][value][11] [0]),
- .I1(\[2].[2].s_reqs_reg[10][value][11] [0]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11] [0]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11] [0]),
- .O(\axi_rdata[0]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_30
- (.I0(\[3].[3].s_reqs_reg[15][value][11] [0]),
- .I1(\[3].[2].s_reqs_reg[14][value][11] [0]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11] [0]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11] [0]),
- .O(\axi_rdata[0]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_31
- (.I0(Q[0]),
- .I1(\[0].[2].s_reqs_reg[2][value][11] [0]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11] [0]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [0]),
- .O(\axi_rdata[0]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_32
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [0]),
- .I1(\[1].[2].s_reqs_reg[6][value][11] [0]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11] [0]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [0]),
- .O(\axi_rdata[0]_i_32_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][0] ),
- .I1(\data_rw_o_reg_n_0_[10][0] ),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\data_o_reg[1][3] [0]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\s_datao_fmc1[0] [0]),
- .O(\axi_rdata[0]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_35
- (.I0(\[4].[3].s_reqs_reg[19][value][11] [0]),
- .I1(\[4].[2].s_reqs_reg[18][value][11] [0]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11] [0]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11] [0]),
- .O(\axi_rdata[0]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_36
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [0]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_0 [0]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_0 [0]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [0]),
- .O(\axi_rdata[0]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_37
- (.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [0]),
- .I1(\[2].[2].s_reqs_reg[10][value][11]_0 [0]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11]_0 [0]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11]_0 [0]),
- .O(\axi_rdata[0]_i_37_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_39
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [0]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_0 [0]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_0 [0]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [0]),
- .O(\axi_rdata[0]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_41
- (.I0(\data_rw_o_reg_n_0_[79][0] ),
- .I1(\data_rw_o_reg_n_0_[78][0] ),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\data_o_reg[1][3]_0 [0]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\s_datao_fmc2[0] [0]),
- .O(\axi_rdata[0]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_44
- (.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [0]),
- .I1(\[3].[2].s_reqs_reg[14][value][11]_0 [0]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11]_0 [0]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11]_0 [0]),
- .O(\axi_rdata[0]_i_44_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_45
- (.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [0]),
- .I1(\[4].[2].s_reqs_reg[18][value][11]_0 [0]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11]_0 [0]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11]_0 [0]),
- .O(\axi_rdata[0]_i_45_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_5
- (.I0(\axi_rdata_reg[0]_i_11_n_0 ),
- .I1(\axi_rdata_reg[0]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[0]_i_13_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata[0]_i_14_n_0 ),
- .O(\axi_rdata[0]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[0]_i_6
- (.I0(\axi_rdata_reg[10]_0 ),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][0] ),
- .I2(\axi_rdata_reg[0]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][0] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[0]_i_17_n_0 ),
- .O(\axi_rdata[0]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_7
- (.I0(\axi_rdata_reg[0]_i_18_n_0 ),
- .I1(\axi_rdata_reg[0]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[0]_i_20_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_araddr_reg[4]_rep__1_0 ),
- .O(\axi_rdata[0]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[0]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][0]_0 ),
- .I1(\axi_rdata_reg[0]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[0]_i_23_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata_reg[0]_i_24_n_0 ),
- .O(\axi_rdata[0]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[10]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[10]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[10]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_rep_0 ),
- .O(\axi_rdata[10]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h04FF0400))
- \axi_rdata[10]_i_13
- (.I0(\axi_rdata_reg[12]_0 ),
- .I1(\s_datao_fmc1[4] [2]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .I4(\axi_rdata[10]_i_33_n_0 ),
- .O(\axi_rdata[10]_i_13_n_0 ));
- LUT5 #(
- .INIT(32'hCC408840))
- \axi_rdata[10]_i_14
- (.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[12]_1 ),
- .I2(gem_status_vector_i[10]),
- .I3(\axi_rdata_reg[12]_0 ),
- .I4(\data_rw_o_reg_n_0_[3][10] ),
- .O(\axi_rdata[10]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[10]_i_17
- (.I0(\axi_rdata[10]_i_34_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\dac_ch_o_reg[0][31]_0 [10]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\axi_rdata_reg[10]_0 ),
- .O(\axi_rdata[10]_i_17_n_0 ));
- LUT5 #(
- .INIT(32'h88888B88))
- \axi_rdata[10]_i_19
- (.I0(\axi_rdata[10]_i_37_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[12]_0 ),
- .I3(\s_datao_fmc2[4] [2]),
- .I4(\axi_rdata_reg[12]_1 ),
- .O(\axi_rdata[10]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[10]_i_23
- (.I0(\axi_rdata_reg[12]_1 ),
- .I1(\dac_ch_o_reg[0][31] [10]),
- .I2(\axi_rdata_reg[12]_0 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .O(\axi_rdata[10]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_29
- (.I0(\[2].[3].s_reqs_reg[11][value][11] [10]),
- .I1(\[2].[2].s_reqs_reg[10][value][11] [10]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11] [10]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11] [10]),
- .O(\axi_rdata[10]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_30
- (.I0(\[3].[3].s_reqs_reg[15][value][11] [10]),
- .I1(\[3].[2].s_reqs_reg[14][value][11] [10]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11] [10]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11] [10]),
- .O(\axi_rdata[10]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_31
- (.I0(Q[10]),
- .I1(\[0].[2].s_reqs_reg[2][value][11] [10]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11] [10]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [10]),
- .O(\axi_rdata[10]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_32
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [10]),
- .I1(\[1].[2].s_reqs_reg[6][value][11] [10]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11] [10]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [10]),
- .O(\axi_rdata[10]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[10]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][10] ),
- .I1(\data_rw_o_reg_n_0_[10][10] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\s_datao_fmc1[0] [10]),
- .I4(\axi_rdata_reg[12]_0 ),
- .O(\axi_rdata[10]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_34
- (.I0(\[4].[3].s_reqs_reg[19][value][11] [10]),
- .I1(\[4].[2].s_reqs_reg[18][value][11] [10]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11] [10]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11] [10]),
- .O(\axi_rdata[10]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_35
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [10]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_0 [10]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_0 [10]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [10]),
- .O(\axi_rdata[10]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_36
- (.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [10]),
- .I1(\[2].[2].s_reqs_reg[10][value][11]_0 [10]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11]_0 [10]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11]_0 [10]),
- .O(\axi_rdata[10]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_37
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [10]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_0 [10]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_0 [10]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [10]),
- .O(\axi_rdata[10]_i_37_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[10]_i_39
- (.I0(\data_rw_o_reg_n_0_[79][10] ),
- .I1(\data_rw_o_reg_n_0_[78][10] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\s_datao_fmc2[0] [10]),
- .I4(\axi_rdata_reg[12]_0 ),
- .O(\axi_rdata[10]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_42
- (.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [10]),
- .I1(\[3].[2].s_reqs_reg[14][value][11]_0 [10]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11]_0 [10]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11]_0 [10]),
- .O(\axi_rdata[10]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_43
- (.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [10]),
- .I1(\[4].[2].s_reqs_reg[18][value][11]_0 [10]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11]_0 [10]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11]_0 [10]),
- .O(\axi_rdata[10]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_5
- (.I0(\axi_rdata_reg[10]_i_11_n_0 ),
- .I1(\axi_rdata_reg[10]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[10]_i_13_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata[10]_i_14_n_0 ),
- .O(\axi_rdata[10]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[10]_i_6
- (.I0(\axi_rdata_reg[10]_0 ),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][10] ),
- .I2(\axi_rdata_reg[18]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][10] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[10]_i_17_n_0 ),
- .O(\axi_rdata[10]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_7
- (.I0(\axi_rdata_reg[10]_i_18_n_0 ),
- .I1(\axi_rdata[10]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[10]_i_20_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_araddr_reg[4]_rep_0 ),
- .O(\axi_rdata[10]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[10]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][10]_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[10]_i_23_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata_reg[10]_i_24_n_0 ),
- .O(\axi_rdata[10]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[11]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[11]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[11]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_8 ),
- .O(\axi_rdata[11]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h04FF0400))
- \axi_rdata[11]_i_13
- (.I0(\axi_rdata_reg[12]_0 ),
- .I1(\s_datao_fmc1[4] [3]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .I4(\axi_rdata[11]_i_33_n_0 ),
- .O(\axi_rdata[11]_i_13_n_0 ));
- LUT5 #(
- .INIT(32'hCC408840))
- \axi_rdata[11]_i_14
- (.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[12]_1 ),
- .I2(gem_status_vector_i[11]),
- .I3(\axi_rdata_reg[12]_0 ),
- .I4(\data_rw_o_reg_n_0_[3][11] ),
- .O(\axi_rdata[11]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[11]_i_17
- (.I0(\axi_rdata[11]_i_34_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\dac_ch_o_reg[0][31]_0 [11]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[11]_i_17_n_0 ));
- LUT5 #(
- .INIT(32'h88888B88))
- \axi_rdata[11]_i_19
- (.I0(\axi_rdata[11]_i_37_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[12]_0 ),
- .I3(\s_datao_fmc2[4] [3]),
- .I4(\axi_rdata_reg[12]_1 ),
- .O(\axi_rdata[11]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[11]_i_23
- (.I0(\axi_rdata_reg[12]_1 ),
- .I1(\dac_ch_o_reg[0][31] [11]),
- .I2(\axi_rdata_reg[12]_0 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .O(\axi_rdata[11]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_29
- (.I0(\[2].[3].s_reqs_reg[11][value][11] [11]),
- .I1(\[2].[2].s_reqs_reg[10][value][11] [11]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11] [11]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11] [11]),
- .O(\axi_rdata[11]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_30
- (.I0(\[3].[3].s_reqs_reg[15][value][11] [11]),
- .I1(\[3].[2].s_reqs_reg[14][value][11] [11]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11] [11]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11] [11]),
- .O(\axi_rdata[11]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_31
- (.I0(Q[11]),
- .I1(\[0].[2].s_reqs_reg[2][value][11] [11]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11] [11]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [11]),
- .O(\axi_rdata[11]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_32
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [11]),
- .I1(\[1].[2].s_reqs_reg[6][value][11] [11]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11] [11]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [11]),
- .O(\axi_rdata[11]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[11]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][11] ),
- .I1(\data_rw_o_reg_n_0_[10][11] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\s_datao_fmc1[0] [11]),
- .I4(\axi_rdata_reg[12]_0 ),
- .O(\axi_rdata[11]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_34
- (.I0(\[4].[3].s_reqs_reg[19][value][11] [11]),
- .I1(\[4].[2].s_reqs_reg[18][value][11] [11]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11] [11]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11] [11]),
- .O(\axi_rdata[11]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_35
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [11]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_0 [11]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_0 [11]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [11]),
- .O(\axi_rdata[11]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_36
- (.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [11]),
- .I1(\[2].[2].s_reqs_reg[10][value][11]_0 [11]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11]_0 [11]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11]_0 [11]),
- .O(\axi_rdata[11]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_37
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [11]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_0 [11]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_0 [11]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [11]),
- .O(\axi_rdata[11]_i_37_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[11]_i_39
- (.I0(\data_rw_o_reg_n_0_[79][11] ),
- .I1(\data_rw_o_reg_n_0_[78][11] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\s_datao_fmc2[0] [11]),
- .I4(\axi_rdata_reg[12]_0 ),
- .O(\axi_rdata[11]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_42
- (.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [11]),
- .I1(\[3].[2].s_reqs_reg[14][value][11]_0 [11]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11]_0 [11]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11]_0 [11]),
- .O(\axi_rdata[11]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_43
- (.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [11]),
- .I1(\[4].[2].s_reqs_reg[18][value][11]_0 [11]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11]_0 [11]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11]_0 [11]),
- .O(\axi_rdata[11]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_5
- (.I0(\axi_rdata_reg[11]_i_11_n_0 ),
- .I1(\axi_rdata_reg[11]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[11]_i_13_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata[11]_i_14_n_0 ),
- .O(\axi_rdata[11]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[11]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][11] ),
- .I2(\axi_rdata_reg[18]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][11] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[11]_i_17_n_0 ),
- .O(\axi_rdata[11]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_7
- (.I0(\axi_rdata_reg[11]_i_18_n_0 ),
- .I1(\axi_rdata[11]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[11]_i_20_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_araddr_reg[4]_rep_1 ),
- .O(\axi_rdata[11]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[11]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][11]_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[11]_i_23_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[11]_i_24_n_0 ),
- .O(\axi_rdata[11]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[12]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[12]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[12]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_7 ),
- .O(\axi_rdata[12]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h04FF0400))
- \axi_rdata[12]_i_13
- (.I0(\axi_rdata_reg[12]_0 ),
- .I1(\s_datao_fmc1[4] [4]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .I4(\axi_rdata[12]_i_33_n_0 ),
- .O(\axi_rdata[12]_i_13_n_0 ));
- LUT5 #(
- .INIT(32'hCCC888C8))
- \axi_rdata[12]_i_14
- (.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[12]_1 ),
- .I2(gem_status_vector_i[12]),
- .I3(\axi_rdata_reg[12]_0 ),
- .I4(\data_rw_o_reg_n_0_[3][12] ),
- .O(\axi_rdata[12]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[12]_i_17
- (.I0(\axi_rdata[12]_i_34_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\dac_ch_o_reg[0][31]_0 [12]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[12]_i_17_n_0 ));
- LUT5 #(
- .INIT(32'h88888B88))
- \axi_rdata[12]_i_19
- (.I0(\axi_rdata[12]_i_37_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[12]_0 ),
- .I3(\s_datao_fmc2[4] [4]),
- .I4(\axi_rdata_reg[12]_1 ),
- .O(\axi_rdata[12]_i_19_n_0 ));
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[12]_i_23
- (.I0(\axi_rdata_reg[12]_1 ),
- .I1(\dac_ch_o_reg[0][31] [12]),
- .I2(\axi_rdata_reg[12]_0 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .O(\axi_rdata[12]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_29
- (.I0(\data_rw_o_reg_n_0_[27][12] ),
- .I1(\data_rw_o_reg_n_0_[26][12] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\data_rw_o_reg_n_0_[25][12] ),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\data_rw_o_reg_n_0_[24][12] ),
- .O(\axi_rdata[12]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_30
- (.I0(\data_rw_o_reg_n_0_[31][12] ),
- .I1(\data_rw_o_reg_n_0_[30][12] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\data_rw_o_reg_n_0_[29][12] ),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\data_rw_o_reg_n_0_[28][12] ),
- .O(\axi_rdata[12]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_31
- (.I0(\data_rw_o_reg_n_0_[19][12] ),
- .I1(\data_rw_o_reg_n_0_[18][12] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\data_rw_o_reg_n_0_[17][12] ),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\data_rw_o_reg_n_0_[16][12] ),
- .O(\axi_rdata[12]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_32
- (.I0(\data_rw_o_reg_n_0_[23][12] ),
- .I1(\data_rw_o_reg_n_0_[22][12] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\data_rw_o_reg_n_0_[21][12] ),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\data_rw_o_reg_n_0_[20][12] ),
- .O(\axi_rdata[12]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[12]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][12] ),
- .I1(\data_rw_o_reg_n_0_[10][12] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\s_datao_fmc1[0] [12]),
- .I4(\axi_rdata_reg[12]_0 ),
- .O(\axi_rdata[12]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_34
- (.I0(\data_rw_o_reg_n_0_[35][12] ),
- .I1(\data_rw_o_reg_n_0_[34][12] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\data_rw_o_reg_n_0_[33][12] ),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\data_rw_o_reg_n_0_[32][12] ),
- .O(\axi_rdata[12]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_35
- (.I0(\data_rw_o_reg_n_0_[91][12] ),
- .I1(\data_rw_o_reg_n_0_[90][12] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\data_rw_o_reg_n_0_[89][12] ),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\data_rw_o_reg_n_0_[88][12] ),
- .O(\axi_rdata[12]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_36
- (.I0(\data_rw_o_reg_n_0_[95][12] ),
- .I1(\data_rw_o_reg_n_0_[94][12] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\data_rw_o_reg_n_0_[93][12] ),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\data_rw_o_reg_n_0_[92][12] ),
- .O(\axi_rdata[12]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_37
- (.I0(\data_rw_o_reg_n_0_[87][12] ),
- .I1(\data_rw_o_reg_n_0_[86][12] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\data_rw_o_reg_n_0_[85][12] ),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\data_rw_o_reg_n_0_[84][12] ),
- .O(\axi_rdata[12]_i_37_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[12]_i_39
- (.I0(\data_rw_o_reg_n_0_[79][12] ),
- .I1(\data_rw_o_reg_n_0_[78][12] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\s_datao_fmc2[0] [12]),
- .I4(\axi_rdata_reg[12]_0 ),
- .O(\axi_rdata[12]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_42
- (.I0(\data_rw_o_reg_n_0_[99][12] ),
- .I1(\data_rw_o_reg_n_0_[98][12] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\data_rw_o_reg_n_0_[97][12] ),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\data_rw_o_reg_n_0_[96][12] ),
- .O(\axi_rdata[12]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_43
- (.I0(\data_rw_o_reg_n_0_[103][12] ),
- .I1(\data_rw_o_reg_n_0_[102][12] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\data_rw_o_reg_n_0_[101][12] ),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\data_rw_o_reg_n_0_[100][12] ),
- .O(\axi_rdata[12]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_5
- (.I0(\axi_rdata_reg[12]_i_11_n_0 ),
- .I1(\axi_rdata_reg[12]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[12]_i_13_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata[12]_i_14_n_0 ),
- .O(\axi_rdata[12]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[12]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][12] ),
- .I2(\axi_rdata_reg[18]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][12] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[12]_i_17_n_0 ),
- .O(\axi_rdata[12]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_7
- (.I0(\axi_rdata_reg[12]_i_18_n_0 ),
- .I1(\axi_rdata[12]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[12]_i_20_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_araddr_reg[4]_rep_2 ),
- .O(\axi_rdata[12]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[12]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][12]_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[12]_i_23_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[12]_i_24_n_0 ),
- .O(\axi_rdata[12]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[13]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[13]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[13]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_6 ),
- .O(\axi_rdata[13]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h04FF0400))
- \axi_rdata[13]_i_13
- (.I0(\axi_rdata_reg[17]_1 ),
- .I1(\s_datao_fmc1[4] [5]),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .I4(\axi_rdata[13]_i_33_n_0 ),
- .O(\axi_rdata[13]_i_13_n_0 ));
- LUT5 #(
- .INIT(32'h44C800C8))
- \axi_rdata[13]_i_14
- (.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[17]_0 ),
- .I2(gem_status_vector_i[13]),
- .I3(\axi_rdata_reg[17]_1 ),
- .I4(\data_rw_o_reg_n_0_[3][13] ),
- .O(\axi_rdata[13]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[13]_i_17
- (.I0(\axi_rdata[13]_i_34_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [13]),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[13]_i_17_n_0 ));
- LUT5 #(
- .INIT(32'h88888B88))
- \axi_rdata[13]_i_19
- (.I0(\axi_rdata[13]_i_37_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_1 ),
- .I3(\s_datao_fmc2[4] [5]),
- .I4(\axi_rdata_reg[17]_0 ),
- .O(\axi_rdata[13]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[13]_i_23
- (.I0(\axi_rdata_reg[17]_0 ),
- .I1(\dac_ch_o_reg[0][31] [13]),
- .I2(\axi_rdata_reg[17]_1 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .O(\axi_rdata[13]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_29
- (.I0(\data_rw_o_reg_n_0_[27][13] ),
- .I1(\data_rw_o_reg_n_0_[26][13] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[25][13] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[24][13] ),
- .O(\axi_rdata[13]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_30
- (.I0(\data_rw_o_reg_n_0_[31][13] ),
- .I1(\data_rw_o_reg_n_0_[30][13] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[29][13] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[28][13] ),
- .O(\axi_rdata[13]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_31
- (.I0(\data_rw_o_reg_n_0_[19][13] ),
- .I1(\data_rw_o_reg_n_0_[18][13] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[17][13] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[16][13] ),
- .O(\axi_rdata[13]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_32
- (.I0(\data_rw_o_reg_n_0_[23][13] ),
- .I1(\data_rw_o_reg_n_0_[22][13] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[21][13] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[20][13] ),
- .O(\axi_rdata[13]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[13]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][13] ),
- .I1(\data_rw_o_reg_n_0_[10][13] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\s_datao_fmc1[0] [13]),
- .I4(\axi_rdata_reg[17]_1 ),
- .O(\axi_rdata[13]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_34
- (.I0(\data_rw_o_reg_n_0_[35][13] ),
- .I1(\data_rw_o_reg_n_0_[34][13] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[33][13] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[32][13] ),
- .O(\axi_rdata[13]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_35
- (.I0(\data_rw_o_reg_n_0_[91][13] ),
- .I1(\data_rw_o_reg_n_0_[90][13] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[89][13] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[88][13] ),
- .O(\axi_rdata[13]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_36
- (.I0(\data_rw_o_reg_n_0_[95][13] ),
- .I1(\data_rw_o_reg_n_0_[94][13] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[93][13] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[92][13] ),
- .O(\axi_rdata[13]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_37
- (.I0(\data_rw_o_reg_n_0_[87][13] ),
- .I1(\data_rw_o_reg_n_0_[86][13] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[85][13] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[84][13] ),
- .O(\axi_rdata[13]_i_37_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[13]_i_39
- (.I0(\data_rw_o_reg_n_0_[79][13] ),
- .I1(\data_rw_o_reg_n_0_[78][13] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\s_datao_fmc2[0] [13]),
- .I4(\axi_rdata_reg[17]_1 ),
- .O(\axi_rdata[13]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_42
- (.I0(\data_rw_o_reg_n_0_[99][13] ),
- .I1(\data_rw_o_reg_n_0_[98][13] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[97][13] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[96][13] ),
- .O(\axi_rdata[13]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_43
- (.I0(\data_rw_o_reg_n_0_[103][13] ),
- .I1(\data_rw_o_reg_n_0_[102][13] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[101][13] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[100][13] ),
- .O(\axi_rdata[13]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_5
- (.I0(\axi_rdata_reg[13]_i_11_n_0 ),
- .I1(\axi_rdata_reg[13]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[13]_i_13_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata[13]_i_14_n_0 ),
- .O(\axi_rdata[13]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[13]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][13] ),
- .I2(\axi_rdata_reg[18]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][13] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[13]_i_17_n_0 ),
- .O(\axi_rdata[13]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_7
- (.I0(\axi_rdata_reg[13]_i_18_n_0 ),
- .I1(\axi_rdata[13]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[13]_i_20_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_araddr_reg[4]_rep_3 ),
- .O(\axi_rdata[13]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[13]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][13]_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[13]_i_23_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[13]_i_24_n_0 ),
- .O(\axi_rdata[13]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[14]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[14]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[14]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_5 ),
- .O(\axi_rdata[14]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h04FF0400))
- \axi_rdata[14]_i_13
- (.I0(\axi_rdata_reg[17]_1 ),
- .I1(\s_datao_fmc1[4] [6]),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .I4(\axi_rdata[14]_i_33_n_0 ),
- .O(\axi_rdata[14]_i_13_n_0 ));
- LUT5 #(
- .INIT(32'hCCC888C8))
- \axi_rdata[14]_i_14
- (.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[17]_0 ),
- .I2(gem_status_vector_i[14]),
- .I3(\axi_rdata_reg[17]_1 ),
- .I4(\data_rw_o_reg_n_0_[3][14] ),
- .O(\axi_rdata[14]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[14]_i_17
- (.I0(\axi_rdata[14]_i_34_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [14]),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[14]_i_17_n_0 ));
- LUT5 #(
- .INIT(32'h88888B88))
- \axi_rdata[14]_i_19
- (.I0(\axi_rdata[14]_i_37_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_1 ),
- .I3(\s_datao_fmc2[4] [6]),
- .I4(\axi_rdata_reg[17]_0 ),
- .O(\axi_rdata[14]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[14]_i_23
- (.I0(\axi_rdata_reg[17]_0 ),
- .I1(\dac_ch_o_reg[0][31] [14]),
- .I2(\axi_rdata_reg[17]_1 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .O(\axi_rdata[14]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_29
- (.I0(\data_rw_o_reg_n_0_[27][14] ),
- .I1(\data_rw_o_reg_n_0_[26][14] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[25][14] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[24][14] ),
- .O(\axi_rdata[14]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_30
- (.I0(\data_rw_o_reg_n_0_[31][14] ),
- .I1(\data_rw_o_reg_n_0_[30][14] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[29][14] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[28][14] ),
- .O(\axi_rdata[14]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_31
- (.I0(\data_rw_o_reg_n_0_[19][14] ),
- .I1(\data_rw_o_reg_n_0_[18][14] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[17][14] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[16][14] ),
- .O(\axi_rdata[14]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_32
- (.I0(\data_rw_o_reg_n_0_[23][14] ),
- .I1(\data_rw_o_reg_n_0_[22][14] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[21][14] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[20][14] ),
- .O(\axi_rdata[14]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[14]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][14] ),
- .I1(\data_rw_o_reg_n_0_[10][14] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\s_datao_fmc1[0] [14]),
- .I4(\axi_rdata_reg[17]_1 ),
- .O(\axi_rdata[14]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_34
- (.I0(\data_rw_o_reg_n_0_[35][14] ),
- .I1(\data_rw_o_reg_n_0_[34][14] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[33][14] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[32][14] ),
- .O(\axi_rdata[14]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_35
- (.I0(\data_rw_o_reg_n_0_[91][14] ),
- .I1(\data_rw_o_reg_n_0_[90][14] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[89][14] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[88][14] ),
- .O(\axi_rdata[14]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_36
- (.I0(\data_rw_o_reg_n_0_[95][14] ),
- .I1(\data_rw_o_reg_n_0_[94][14] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[93][14] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[92][14] ),
- .O(\axi_rdata[14]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_37
- (.I0(\data_rw_o_reg_n_0_[87][14] ),
- .I1(\data_rw_o_reg_n_0_[86][14] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[85][14] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[84][14] ),
- .O(\axi_rdata[14]_i_37_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[14]_i_39
- (.I0(\data_rw_o_reg_n_0_[79][14] ),
- .I1(\data_rw_o_reg_n_0_[78][14] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\s_datao_fmc2[0] [14]),
- .I4(\axi_rdata_reg[17]_1 ),
- .O(\axi_rdata[14]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_42
- (.I0(\data_rw_o_reg_n_0_[99][14] ),
- .I1(\data_rw_o_reg_n_0_[98][14] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[97][14] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[96][14] ),
- .O(\axi_rdata[14]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_43
- (.I0(\data_rw_o_reg_n_0_[103][14] ),
- .I1(\data_rw_o_reg_n_0_[102][14] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[101][14] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[100][14] ),
- .O(\axi_rdata[14]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_5
- (.I0(\axi_rdata_reg[14]_i_11_n_0 ),
- .I1(\axi_rdata_reg[14]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[14]_i_13_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata[14]_i_14_n_0 ),
- .O(\axi_rdata[14]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[14]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][14] ),
- .I2(\axi_rdata_reg[18]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][14] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[14]_i_17_n_0 ),
- .O(\axi_rdata[14]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_7
- (.I0(\axi_rdata_reg[14]_i_18_n_0 ),
- .I1(\axi_rdata[14]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[14]_i_20_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_araddr_reg[4]_rep_4 ),
- .O(\axi_rdata[14]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[14]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][14]_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[14]_i_23_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[14]_i_24_n_0 ),
- .O(\axi_rdata[14]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[15]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[15]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[15]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_4 ),
- .O(\axi_rdata[15]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h04FF0400))
- \axi_rdata[15]_i_13
- (.I0(\axi_rdata_reg[17]_1 ),
- .I1(\s_datao_fmc1[4] [7]),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .I4(\axi_rdata[15]_i_33_n_0 ),
- .O(\axi_rdata[15]_i_13_n_0 ));
- LUT5 #(
- .INIT(32'hCCC888C8))
- \axi_rdata[15]_i_14
- (.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[17]_0 ),
- .I2(gem_status_vector_i[15]),
- .I3(\axi_rdata_reg[17]_1 ),
- .I4(\data_rw_o_reg_n_0_[3][15] ),
- .O(\axi_rdata[15]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[15]_i_17
- (.I0(\axi_rdata[15]_i_34_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [15]),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[15]_i_17_n_0 ));
- LUT5 #(
- .INIT(32'h88888B88))
- \axi_rdata[15]_i_19
- (.I0(\axi_rdata[15]_i_37_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_1 ),
- .I3(\s_datao_fmc2[4] [7]),
- .I4(\axi_rdata_reg[17]_0 ),
- .O(\axi_rdata[15]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[15]_i_23
- (.I0(\axi_rdata_reg[17]_0 ),
- .I1(\dac_ch_o_reg[0][31] [15]),
- .I2(\axi_rdata_reg[17]_1 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .O(\axi_rdata[15]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_29
- (.I0(\data_rw_o_reg_n_0_[27][15] ),
- .I1(\data_rw_o_reg_n_0_[26][15] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[25][15] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[24][15] ),
- .O(\axi_rdata[15]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_30
- (.I0(\data_rw_o_reg_n_0_[31][15] ),
- .I1(\data_rw_o_reg_n_0_[30][15] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[29][15] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[28][15] ),
- .O(\axi_rdata[15]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_31
- (.I0(\data_rw_o_reg_n_0_[19][15] ),
- .I1(\data_rw_o_reg_n_0_[18][15] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[17][15] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[16][15] ),
- .O(\axi_rdata[15]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_32
- (.I0(\data_rw_o_reg_n_0_[23][15] ),
- .I1(\data_rw_o_reg_n_0_[22][15] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[21][15] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[20][15] ),
- .O(\axi_rdata[15]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[15]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][15] ),
- .I1(\data_rw_o_reg_n_0_[10][15] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\s_datao_fmc1[0] [15]),
- .I4(\axi_rdata_reg[17]_1 ),
- .O(\axi_rdata[15]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_34
- (.I0(\data_rw_o_reg_n_0_[35][15] ),
- .I1(\data_rw_o_reg_n_0_[34][15] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[33][15] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[32][15] ),
- .O(\axi_rdata[15]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_35
- (.I0(\data_rw_o_reg_n_0_[91][15] ),
- .I1(\data_rw_o_reg_n_0_[90][15] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[89][15] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[88][15] ),
- .O(\axi_rdata[15]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_36
- (.I0(\data_rw_o_reg_n_0_[95][15] ),
- .I1(\data_rw_o_reg_n_0_[94][15] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[93][15] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[92][15] ),
- .O(\axi_rdata[15]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_37
- (.I0(\data_rw_o_reg_n_0_[87][15] ),
- .I1(\data_rw_o_reg_n_0_[86][15] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[85][15] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[84][15] ),
- .O(\axi_rdata[15]_i_37_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[15]_i_39
- (.I0(\data_rw_o_reg_n_0_[79][15] ),
- .I1(\data_rw_o_reg_n_0_[78][15] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\s_datao_fmc2[0] [15]),
- .I4(\axi_rdata_reg[17]_1 ),
- .O(\axi_rdata[15]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_42
- (.I0(\data_rw_o_reg_n_0_[99][15] ),
- .I1(\data_rw_o_reg_n_0_[98][15] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[97][15] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[96][15] ),
- .O(\axi_rdata[15]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_43
- (.I0(\data_rw_o_reg_n_0_[103][15] ),
- .I1(\data_rw_o_reg_n_0_[102][15] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[101][15] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[100][15] ),
- .O(\axi_rdata[15]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_5
- (.I0(\axi_rdata_reg[15]_i_11_n_0 ),
- .I1(\axi_rdata_reg[15]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[15]_i_13_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata[15]_i_14_n_0 ),
- .O(\axi_rdata[15]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[15]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][15] ),
- .I2(\axi_rdata_reg[18]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][15] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[15]_i_17_n_0 ),
- .O(\axi_rdata[15]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_7
- (.I0(\axi_rdata_reg[15]_i_18_n_0 ),
- .I1(\axi_rdata[15]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[15]_i_20_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_araddr_reg[4]_rep_5 ),
- .O(\axi_rdata[15]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[15]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][15]_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[15]_i_23_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[15]_i_24_n_0 ),
- .O(\axi_rdata[15]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[16]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[16]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[16]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_3 ),
- .O(\axi_rdata[16]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h04FF0400))
- \axi_rdata[16]_i_13
- (.I0(\axi_rdata_reg[17]_1 ),
- .I1(\s_datao_fmc1[4] [8]),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .I4(\axi_rdata[16]_i_33_n_0 ),
- .O(\axi_rdata[16]_i_13_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT4 #(
- .INIT(16'hC888))
- \axi_rdata[16]_i_14
- (.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[17]_0 ),
- .I2(\data_rw_o_reg_n_0_[3][16] ),
- .I3(\axi_rdata_reg[17]_1 ),
- .O(\axi_rdata[16]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[16]_i_17
- (.I0(\axi_rdata[16]_i_34_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [16]),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[16]_i_17_n_0 ));
- LUT5 #(
- .INIT(32'h88888B88))
- \axi_rdata[16]_i_19
- (.I0(\axi_rdata[16]_i_37_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_1 ),
- .I3(\s_datao_fmc2[4] [8]),
- .I4(\axi_rdata_reg[17]_0 ),
- .O(\axi_rdata[16]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[16]_i_23
- (.I0(\axi_rdata_reg[17]_0 ),
- .I1(\dac_ch_o_reg[0][31] [16]),
- .I2(\axi_rdata_reg[17]_1 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .O(\axi_rdata[16]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_29
- (.I0(\data_rw_o_reg_n_0_[27][16] ),
- .I1(\data_rw_o_reg_n_0_[26][16] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[25][16] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[24][16] ),
- .O(\axi_rdata[16]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_30
- (.I0(\data_rw_o_reg_n_0_[31][16] ),
- .I1(\data_rw_o_reg_n_0_[30][16] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[29][16] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[28][16] ),
- .O(\axi_rdata[16]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_31
- (.I0(\data_rw_o_reg_n_0_[19][16] ),
- .I1(\data_rw_o_reg_n_0_[18][16] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[17][16] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[16][16] ),
- .O(\axi_rdata[16]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_32
- (.I0(\data_rw_o_reg_n_0_[23][16] ),
- .I1(\data_rw_o_reg_n_0_[22][16] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[21][16] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[20][16] ),
- .O(\axi_rdata[16]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[16]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][16] ),
- .I1(\data_rw_o_reg_n_0_[10][16] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\s_datao_fmc1[0] [16]),
- .I4(\axi_rdata_reg[17]_1 ),
- .O(\axi_rdata[16]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_34
- (.I0(\data_rw_o_reg_n_0_[35][16] ),
- .I1(\data_rw_o_reg_n_0_[34][16] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[33][16] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[32][16] ),
- .O(\axi_rdata[16]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_35
- (.I0(\data_rw_o_reg_n_0_[91][16] ),
- .I1(\data_rw_o_reg_n_0_[90][16] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[89][16] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[88][16] ),
- .O(\axi_rdata[16]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_36
- (.I0(\data_rw_o_reg_n_0_[95][16] ),
- .I1(\data_rw_o_reg_n_0_[94][16] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[93][16] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[92][16] ),
- .O(\axi_rdata[16]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_37
- (.I0(\data_rw_o_reg_n_0_[87][16] ),
- .I1(\data_rw_o_reg_n_0_[86][16] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[85][16] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[84][16] ),
- .O(\axi_rdata[16]_i_37_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[16]_i_39
- (.I0(\data_rw_o_reg_n_0_[79][16] ),
- .I1(\data_rw_o_reg_n_0_[78][16] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\s_datao_fmc2[0] [16]),
- .I4(\axi_rdata_reg[17]_1 ),
- .O(\axi_rdata[16]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_42
- (.I0(\data_rw_o_reg_n_0_[99][16] ),
- .I1(\data_rw_o_reg_n_0_[98][16] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[97][16] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[96][16] ),
- .O(\axi_rdata[16]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_43
- (.I0(\data_rw_o_reg_n_0_[103][16] ),
- .I1(\data_rw_o_reg_n_0_[102][16] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[101][16] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[100][16] ),
- .O(\axi_rdata[16]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_5
- (.I0(\axi_rdata_reg[16]_i_11_n_0 ),
- .I1(\axi_rdata_reg[16]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[16]_i_13_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata[16]_i_14_n_0 ),
- .O(\axi_rdata[16]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[16]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][16] ),
- .I2(\axi_rdata_reg[18]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][16] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[16]_i_17_n_0 ),
- .O(\axi_rdata[16]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_7
- (.I0(\axi_rdata_reg[16]_i_18_n_0 ),
- .I1(\axi_rdata[16]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[16]_i_20_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_araddr_reg[4]_rep_6 ),
- .O(\axi_rdata[16]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[16]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][16]_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[16]_i_23_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[16]_i_24_n_0 ),
- .O(\axi_rdata[16]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[17]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[17]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[17]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_2 ),
- .O(\axi_rdata[17]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h04FF0400))
- \axi_rdata[17]_i_13
- (.I0(\axi_rdata_reg[17]_1 ),
- .I1(\s_datao_fmc1[4] [9]),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .I4(\axi_rdata[17]_i_33_n_0 ),
- .O(\axi_rdata[17]_i_13_n_0 ));
- LUT4 #(
- .INIT(16'hC800))
- \axi_rdata[17]_i_14
- (.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[17]_0 ),
- .I2(\data_rw_o_reg_n_0_[3][17] ),
- .I3(\axi_rdata_reg[17]_1 ),
- .O(\axi_rdata[17]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[17]_i_17
- (.I0(\axi_rdata[17]_i_34_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [17]),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[17]_i_17_n_0 ));
- LUT5 #(
- .INIT(32'h88888B88))
- \axi_rdata[17]_i_19
- (.I0(\axi_rdata[17]_i_37_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[17]_1 ),
- .I3(\s_datao_fmc2[4] [9]),
- .I4(\axi_rdata_reg[17]_0 ),
- .O(\axi_rdata[17]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[17]_i_23
- (.I0(\axi_rdata_reg[17]_0 ),
- .I1(\dac_ch_o_reg[0][31] [17]),
- .I2(\axi_rdata_reg[17]_1 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .O(\axi_rdata[17]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_29
- (.I0(\data_rw_o_reg_n_0_[27][17] ),
- .I1(\data_rw_o_reg_n_0_[26][17] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[25][17] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[24][17] ),
- .O(\axi_rdata[17]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_30
- (.I0(\data_rw_o_reg_n_0_[31][17] ),
- .I1(\data_rw_o_reg_n_0_[30][17] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[29][17] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[28][17] ),
- .O(\axi_rdata[17]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_31
- (.I0(\data_rw_o_reg_n_0_[19][17] ),
- .I1(\data_rw_o_reg_n_0_[18][17] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[17][17] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[16][17] ),
- .O(\axi_rdata[17]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_32
- (.I0(\data_rw_o_reg_n_0_[23][17] ),
- .I1(\data_rw_o_reg_n_0_[22][17] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[21][17] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[20][17] ),
- .O(\axi_rdata[17]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[17]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][17] ),
- .I1(\data_rw_o_reg_n_0_[10][17] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\s_datao_fmc1[0] [17]),
- .I4(\axi_rdata_reg[17]_1 ),
- .O(\axi_rdata[17]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_34
- (.I0(\data_rw_o_reg_n_0_[35][17] ),
- .I1(\data_rw_o_reg_n_0_[34][17] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[33][17] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[32][17] ),
- .O(\axi_rdata[17]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_35
- (.I0(\data_rw_o_reg_n_0_[91][17] ),
- .I1(\data_rw_o_reg_n_0_[90][17] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[89][17] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[88][17] ),
- .O(\axi_rdata[17]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_36
- (.I0(\data_rw_o_reg_n_0_[95][17] ),
- .I1(\data_rw_o_reg_n_0_[94][17] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[93][17] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[92][17] ),
- .O(\axi_rdata[17]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_37
- (.I0(\data_rw_o_reg_n_0_[87][17] ),
- .I1(\data_rw_o_reg_n_0_[86][17] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[85][17] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[84][17] ),
- .O(\axi_rdata[17]_i_37_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[17]_i_39
- (.I0(\data_rw_o_reg_n_0_[79][17] ),
- .I1(\data_rw_o_reg_n_0_[78][17] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\s_datao_fmc2[0] [17]),
- .I4(\axi_rdata_reg[17]_1 ),
- .O(\axi_rdata[17]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_42
- (.I0(\data_rw_o_reg_n_0_[99][17] ),
- .I1(\data_rw_o_reg_n_0_[98][17] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[97][17] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[96][17] ),
- .O(\axi_rdata[17]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_43
- (.I0(\data_rw_o_reg_n_0_[103][17] ),
- .I1(\data_rw_o_reg_n_0_[102][17] ),
- .I2(\axi_rdata_reg[17]_0 ),
- .I3(\data_rw_o_reg_n_0_[101][17] ),
- .I4(\axi_rdata_reg[17]_1 ),
- .I5(\data_rw_o_reg_n_0_[100][17] ),
- .O(\axi_rdata[17]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_5
- (.I0(\axi_rdata_reg[17]_i_11_n_0 ),
- .I1(\axi_rdata_reg[17]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[17]_i_13_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata[17]_i_14_n_0 ),
- .O(\axi_rdata[17]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[17]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][17] ),
- .I2(\axi_rdata_reg[18]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][17] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[17]_i_17_n_0 ),
- .O(\axi_rdata[17]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_7
- (.I0(\axi_rdata_reg[17]_i_18_n_0 ),
- .I1(\axi_rdata[17]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[17]_i_20_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_araddr_reg[4]_rep_7 ),
- .O(\axi_rdata[17]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[17]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][17]_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[17]_i_23_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[17]_i_24_n_0 ),
- .O(\axi_rdata[17]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[18]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[18]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[18]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_1 ),
- .O(\axi_rdata[18]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h04FF0400))
- \axi_rdata[18]_i_13
- (.I0(\axi_rdata_reg[22]_1 ),
- .I1(\s_datao_fmc1[4] [10]),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .I4(\axi_rdata[18]_i_33_n_0 ),
- .O(\axi_rdata[18]_i_13_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT4 #(
- .INIT(16'h4088))
- \axi_rdata[18]_i_14
- (.I0(\axi_rdata_reg[18]_0 ),
- .I1(\axi_rdata_reg[22]_0 ),
- .I2(\data_rw_o_reg_n_0_[3][18] ),
- .I3(\axi_rdata_reg[22]_1 ),
- .O(\axi_rdata[18]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[18]_i_17
- (.I0(\axi_rdata[18]_i_34_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [18]),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[18]_i_17_n_0 ));
- LUT5 #(
- .INIT(32'h88888B88))
- \axi_rdata[18]_i_19
- (.I0(\axi_rdata[18]_i_37_n_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(\axi_rdata_reg[22]_1 ),
- .I3(\s_datao_fmc2[4] [10]),
- .I4(\axi_rdata_reg[22]_0 ),
- .O(\axi_rdata[18]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[18]_i_23
- (.I0(\axi_rdata_reg[22]_0 ),
- .I1(\dac_ch_o_reg[0][31] [18]),
- .I2(\axi_rdata_reg[22]_1 ),
- .I3(\axi_rdata_reg[18]_0 ),
- .O(\axi_rdata[18]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_29
- (.I0(\data_rw_o_reg_n_0_[27][18] ),
- .I1(\data_rw_o_reg_n_0_[26][18] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[25][18] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[24][18] ),
- .O(\axi_rdata[18]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_30
- (.I0(\data_rw_o_reg_n_0_[31][18] ),
- .I1(\data_rw_o_reg_n_0_[30][18] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[29][18] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[28][18] ),
- .O(\axi_rdata[18]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_31
- (.I0(\data_rw_o_reg_n_0_[19][18] ),
- .I1(\data_rw_o_reg_n_0_[18][18] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[17][18] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[16][18] ),
- .O(\axi_rdata[18]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_32
- (.I0(\data_rw_o_reg_n_0_[23][18] ),
- .I1(\data_rw_o_reg_n_0_[22][18] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[21][18] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[20][18] ),
- .O(\axi_rdata[18]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[18]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][18] ),
- .I1(\data_rw_o_reg_n_0_[10][18] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\s_datao_fmc1[0] [18]),
- .I4(\axi_rdata_reg[22]_1 ),
- .O(\axi_rdata[18]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_34
- (.I0(\data_rw_o_reg_n_0_[35][18] ),
- .I1(\data_rw_o_reg_n_0_[34][18] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[33][18] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[32][18] ),
- .O(\axi_rdata[18]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_35
- (.I0(\data_rw_o_reg_n_0_[91][18] ),
- .I1(\data_rw_o_reg_n_0_[90][18] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[89][18] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[88][18] ),
- .O(\axi_rdata[18]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_36
- (.I0(\data_rw_o_reg_n_0_[95][18] ),
- .I1(\data_rw_o_reg_n_0_[94][18] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[93][18] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[92][18] ),
- .O(\axi_rdata[18]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_37
- (.I0(\data_rw_o_reg_n_0_[87][18] ),
- .I1(\data_rw_o_reg_n_0_[86][18] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[85][18] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[84][18] ),
- .O(\axi_rdata[18]_i_37_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[18]_i_39
- (.I0(\data_rw_o_reg_n_0_[79][18] ),
- .I1(\data_rw_o_reg_n_0_[78][18] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\s_datao_fmc2[0] [18]),
- .I4(\axi_rdata_reg[22]_1 ),
- .O(\axi_rdata[18]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_42
- (.I0(\data_rw_o_reg_n_0_[99][18] ),
- .I1(\data_rw_o_reg_n_0_[98][18] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[97][18] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[96][18] ),
- .O(\axi_rdata[18]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_43
- (.I0(\data_rw_o_reg_n_0_[103][18] ),
- .I1(\data_rw_o_reg_n_0_[102][18] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[101][18] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[100][18] ),
- .O(\axi_rdata[18]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_5
- (.I0(\axi_rdata_reg[18]_i_11_n_0 ),
- .I1(\axi_rdata_reg[18]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[18]_i_13_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata[18]_i_14_n_0 ),
- .O(\axi_rdata[18]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[18]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][18] ),
- .I2(\axi_rdata_reg[18]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][18] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[18]_i_17_n_0 ),
- .O(\axi_rdata[18]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_7
- (.I0(\axi_rdata_reg[18]_i_18_n_0 ),
- .I1(\axi_rdata[18]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[18]_i_20_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_araddr_reg[4]_rep_8 ),
- .O(\axi_rdata[18]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[18]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][18]_0 ),
- .I1(\axi_rdata_reg[18]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[18]_i_23_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[18]_i_24_n_0 ),
- .O(\axi_rdata[18]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[19]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[19]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[19]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_0 ),
- .O(\axi_rdata[19]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h04FF0400))
- \axi_rdata[19]_i_13
- (.I0(\axi_rdata_reg[22]_1 ),
- .I1(\s_datao_fmc1[4] [11]),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata[19]_i_33_n_0 ),
- .O(\axi_rdata[19]_i_13_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT4 #(
- .INIT(16'hC888))
- \axi_rdata[19]_i_14
- (.I0(\axi_rdata_reg[23]_0 [2]),
- .I1(\axi_rdata_reg[22]_0 ),
- .I2(\data_rw_o_reg_n_0_[3][19] ),
- .I3(\axi_rdata_reg[22]_1 ),
- .O(\axi_rdata[19]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[19]_i_17
- (.I0(\axi_rdata[19]_i_34_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [19]),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[19]_i_17_n_0 ));
- LUT5 #(
- .INIT(32'h88888B88))
- \axi_rdata[19]_i_19
- (.I0(\axi_rdata[19]_i_37_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[22]_1 ),
- .I3(\s_datao_fmc2[4] [11]),
- .I4(\axi_rdata_reg[22]_0 ),
- .O(\axi_rdata[19]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[19]_i_23
- (.I0(\axi_rdata_reg[22]_0 ),
- .I1(\dac_ch_o_reg[0][31] [19]),
- .I2(\axi_rdata_reg[22]_1 ),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[19]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_29
- (.I0(\data_rw_o_reg_n_0_[27][19] ),
- .I1(\data_rw_o_reg_n_0_[26][19] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[25][19] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[24][19] ),
- .O(\axi_rdata[19]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_30
- (.I0(\data_rw_o_reg_n_0_[31][19] ),
- .I1(\data_rw_o_reg_n_0_[30][19] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[29][19] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[28][19] ),
- .O(\axi_rdata[19]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_31
- (.I0(\data_rw_o_reg_n_0_[19][19] ),
- .I1(\data_rw_o_reg_n_0_[18][19] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[17][19] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[16][19] ),
- .O(\axi_rdata[19]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_32
- (.I0(\data_rw_o_reg_n_0_[23][19] ),
- .I1(\data_rw_o_reg_n_0_[22][19] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[21][19] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[20][19] ),
- .O(\axi_rdata[19]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[19]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][19] ),
- .I1(\data_rw_o_reg_n_0_[10][19] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\s_datao_fmc1[0] [19]),
- .I4(\axi_rdata_reg[22]_1 ),
- .O(\axi_rdata[19]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_34
- (.I0(\data_rw_o_reg_n_0_[35][19] ),
- .I1(\data_rw_o_reg_n_0_[34][19] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[33][19] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[32][19] ),
- .O(\axi_rdata[19]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_35
- (.I0(\data_rw_o_reg_n_0_[91][19] ),
- .I1(\data_rw_o_reg_n_0_[90][19] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[89][19] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[88][19] ),
- .O(\axi_rdata[19]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_36
- (.I0(\data_rw_o_reg_n_0_[95][19] ),
- .I1(\data_rw_o_reg_n_0_[94][19] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[93][19] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[92][19] ),
- .O(\axi_rdata[19]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_37
- (.I0(\data_rw_o_reg_n_0_[87][19] ),
- .I1(\data_rw_o_reg_n_0_[86][19] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[85][19] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[84][19] ),
- .O(\axi_rdata[19]_i_37_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[19]_i_39
- (.I0(\data_rw_o_reg_n_0_[79][19] ),
- .I1(\data_rw_o_reg_n_0_[78][19] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\s_datao_fmc2[0] [19]),
- .I4(\axi_rdata_reg[22]_1 ),
- .O(\axi_rdata[19]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_42
- (.I0(\data_rw_o_reg_n_0_[99][19] ),
- .I1(\data_rw_o_reg_n_0_[98][19] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[97][19] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[96][19] ),
- .O(\axi_rdata[19]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_43
- (.I0(\data_rw_o_reg_n_0_[103][19] ),
- .I1(\data_rw_o_reg_n_0_[102][19] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[101][19] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[100][19] ),
- .O(\axi_rdata[19]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_5
- (.I0(\axi_rdata_reg[19]_i_11_n_0 ),
- .I1(\axi_rdata_reg[19]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[19]_i_13_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata[19]_i_14_n_0 ),
- .O(\axi_rdata[19]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[19]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][19] ),
- .I2(\axi_rdata_reg[23]_0 [2]),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][19] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[19]_i_17_n_0 ),
- .O(\axi_rdata[19]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_7
- (.I0(\axi_rdata_reg[19]_i_18_n_0 ),
- .I1(\axi_rdata[19]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[19]_i_20_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_araddr_reg[4]_0 ),
- .O(\axi_rdata[19]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[19]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][19]_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[19]_i_23_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[19]_i_24_n_0 ),
- .O(\axi_rdata[19]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[1]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[1]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[1]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_rep_9 ),
- .O(\axi_rdata[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h4455FA004400FA00))
- \axi_rdata[1]_i_14
- (.I0(\axi_rdata_reg[9]_0 ),
- .I1(\data_rw_o[3] [1]),
- .I2(gem_status_vector_i[1]),
- .I3(\axi_rdata_reg[2]_0 ),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\s_ins_reg[3] [1]),
- .O(\axi_rdata[1]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[1]_i_17
- (.I0(\axi_rdata[1]_i_35_n_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [1]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\axi_rdata_reg[10]_0 ),
- .O(\axi_rdata[1]_i_17_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[1]_i_23
- (.I0(\axi_rdata_reg[2]_0 ),
- .I1(\dac_ch_o_reg[0][31] [1]),
- .I2(\axi_rdata_reg[2]_1 ),
- .I3(\axi_rdata_reg[9]_0 ),
- .O(\axi_rdata[1]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_29
- (.I0(\[2].[3].s_reqs_reg[11][value][11] [1]),
- .I1(\[2].[2].s_reqs_reg[10][value][11] [1]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11] [1]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11] [1]),
- .O(\axi_rdata[1]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_30
- (.I0(\[3].[3].s_reqs_reg[15][value][11] [1]),
- .I1(\[3].[2].s_reqs_reg[14][value][11] [1]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11] [1]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11] [1]),
- .O(\axi_rdata[1]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_31
- (.I0(Q[1]),
- .I1(\[0].[2].s_reqs_reg[2][value][11] [1]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11] [1]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [1]),
- .O(\axi_rdata[1]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_32
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [1]),
- .I1(\[1].[2].s_reqs_reg[6][value][11] [1]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11] [1]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [1]),
- .O(\axi_rdata[1]_i_32_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_33
- (.I0(\v_dout_reg[7] [0]),
- .I1(\data_rw_o_reg_n_0_[10][1] ),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\data_o_reg[1][3] [1]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\s_datao_fmc1[0] [1]),
- .O(\axi_rdata[1]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_35
- (.I0(\[4].[3].s_reqs_reg[19][value][11] [1]),
- .I1(\[4].[2].s_reqs_reg[18][value][11] [1]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11] [1]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11] [1]),
- .O(\axi_rdata[1]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_36
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [1]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_0 [1]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_0 [1]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [1]),
- .O(\axi_rdata[1]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_37
- (.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [1]),
- .I1(\[2].[2].s_reqs_reg[10][value][11]_0 [1]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11]_0 [1]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11]_0 [1]),
- .O(\axi_rdata[1]_i_37_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_39
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [1]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_0 [1]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_0 [1]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [1]),
- .O(\axi_rdata[1]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_41
- (.I0(\v_dout_reg[7]_0 [0]),
- .I1(\data_rw_o_reg_n_0_[78][1] ),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\data_o_reg[1][3]_0 [1]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\s_datao_fmc2[0] [1]),
- .O(\axi_rdata[1]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_44
- (.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [1]),
- .I1(\[3].[2].s_reqs_reg[14][value][11]_0 [1]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11]_0 [1]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11]_0 [1]),
- .O(\axi_rdata[1]_i_44_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_45
- (.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [1]),
- .I1(\[4].[2].s_reqs_reg[18][value][11]_0 [1]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11]_0 [1]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11]_0 [1]),
- .O(\axi_rdata[1]_i_45_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_5
- (.I0(\axi_rdata_reg[1]_i_11_n_0 ),
- .I1(\axi_rdata_reg[1]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[1]_i_13_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata[1]_i_14_n_0 ),
- .O(\axi_rdata[1]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[1]_i_6
- (.I0(\axi_rdata_reg[10]_0 ),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][1] ),
- .I2(\axi_rdata_reg[9]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][1] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[1]_i_17_n_0 ),
- .O(\axi_rdata[1]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_7
- (.I0(\axi_rdata_reg[1]_i_18_n_0 ),
- .I1(\axi_rdata_reg[1]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[1]_i_20_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_araddr_reg[4]_rep__0_0 ),
- .O(\axi_rdata[1]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[1]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][1]_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[1]_i_23_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata_reg[1]_i_24_n_0 ),
- .O(\axi_rdata[1]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hA8A8A8080808A808))
- \axi_rdata[20]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata[20]_i_2_n_0 ),
- .I2(axi_araddr[9]),
- .I3(\axi_araddr_reg[4]_7 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_araddr_reg[4]_8 ),
- .O(\axi_rdata[20]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[20]_i_14
- (.I0(\axi_rdata_reg[22]_0 ),
- .I1(\dac_ch_o_reg[0][31] [20]),
- .I2(\axi_rdata_reg[22]_1 ),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[20]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_16
- (.I0(\axi_rdata[20]_i_27_n_0 ),
- .I1(\fmc_03287_channels[19].gen_chs.data_o_reg[67][20] ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\fmc_03287_channels[15].gen_chs.data_o_reg[63][20] ),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .I5(\fmc_03287_channels[11].gen_chs.data_o_reg[59][20] ),
- .O(\axi_rdata[20]_i_16_n_0 ));
- LUT5 #(
- .INIT(32'hAFC0A0C0))
- \axi_rdata[20]_i_17
- (.I0(\axi_rdata[20]_i_31_n_0 ),
- .I1(\axi_rdata[20]_i_32_n_0 ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata[20]_i_33_n_0 ),
- .O(\axi_rdata[20]_i_17_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_2
- (.I0(\axi_rdata[20]_i_5_n_0 ),
- .I1(\axi_rdata_reg[20]_i_6_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata[20]_i_7_n_0 ),
- .I4(axi_araddr[7]),
- .I5(\axi_rdata[20]_i_8_n_0 ),
- .O(\axi_rdata[20]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[20]_i_20
- (.I0(\axi_rdata[20]_i_34_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [20]),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[20]_i_20_n_0 ));
- LUT5 #(
- .INIT(32'h0000B800))
- \axi_rdata[20]_i_23
- (.I0(\data_rw_o_reg_n_0_[11][20] ),
- .I1(\axi_rdata_reg[22]_1 ),
- .I2(\data_rw_o_reg_n_0_[10][20] ),
- .I3(\axi_rdata_reg[22]_0 ),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[20]_i_23_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT4 #(
- .INIT(16'h4088))
- \axi_rdata[20]_i_24
- (.I0(\axi_rdata_reg[23]_0 [2]),
- .I1(\axi_rdata_reg[22]_0 ),
- .I2(\data_rw_o_reg_n_0_[3][20] ),
- .I3(\axi_rdata_reg[22]_1 ),
- .O(\axi_rdata[20]_i_24_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_25
- (.I0(\data_rw_o_reg_n_0_[99][20] ),
- .I1(\data_rw_o_reg_n_0_[98][20] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[97][20] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[96][20] ),
- .O(\axi_rdata[20]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_26
- (.I0(\data_rw_o_reg_n_0_[103][20] ),
- .I1(\data_rw_o_reg_n_0_[102][20] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[101][20] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[100][20] ),
- .O(\axi_rdata[20]_i_26_n_0 ));
- LUT4 #(
- .INIT(16'hA808))
- \axi_rdata[20]_i_27
- (.I0(\axi_rdata_reg[22]_0 ),
- .I1(\data_rw_o_reg_n_0_[78][20] ),
- .I2(\axi_rdata_reg[22]_1 ),
- .I3(\data_rw_o_reg_n_0_[79][20] ),
- .O(\axi_rdata[20]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_31
- (.I0(\data_rw_o_reg_n_0_[95][20] ),
- .I1(\data_rw_o_reg_n_0_[94][20] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[93][20] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[92][20] ),
- .O(\axi_rdata[20]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_32
- (.I0(\data_rw_o_reg_n_0_[91][20] ),
- .I1(\data_rw_o_reg_n_0_[90][20] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[89][20] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[88][20] ),
- .O(\axi_rdata[20]_i_32_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_33
- (.I0(\data_rw_o_reg_n_0_[87][20] ),
- .I1(\data_rw_o_reg_n_0_[86][20] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[85][20] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[84][20] ),
- .O(\axi_rdata[20]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_34
- (.I0(\data_rw_o_reg_n_0_[35][20] ),
- .I1(\data_rw_o_reg_n_0_[34][20] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[33][20] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[32][20] ),
- .O(\axi_rdata[20]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_35
- (.I0(\data_rw_o_reg_n_0_[27][20] ),
- .I1(\data_rw_o_reg_n_0_[26][20] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[25][20] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[24][20] ),
- .O(\axi_rdata[20]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_36
- (.I0(\data_rw_o_reg_n_0_[31][20] ),
- .I1(\data_rw_o_reg_n_0_[30][20] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[29][20] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[28][20] ),
- .O(\axi_rdata[20]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_37
- (.I0(\data_rw_o_reg_n_0_[19][20] ),
- .I1(\data_rw_o_reg_n_0_[18][20] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[17][20] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[16][20] ),
- .O(\axi_rdata[20]_i_37_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_38
- (.I0(\data_rw_o_reg_n_0_[23][20] ),
- .I1(\data_rw_o_reg_n_0_[22][20] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[21][20] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[20][20] ),
- .O(\axi_rdata[20]_i_38_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[20]_i_5
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][20]_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[20]_i_14_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[20]_i_15_n_0 ),
- .O(\axi_rdata[20]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[20]_i_7
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][20] ),
- .I2(\axi_rdata_reg[23]_0 [2]),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][20] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[20]_i_20_n_0 ),
- .O(\axi_rdata[20]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_8
- (.I0(\axi_rdata_reg[20]_i_21_n_0 ),
- .I1(\axi_rdata_reg[20]_i_22_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[20]_i_23_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata[20]_i_24_n_0 ),
- .O(\axi_rdata[20]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hA8A8A8080808A808))
- \axi_rdata[21]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata[21]_i_2_n_0 ),
- .I2(axi_araddr[9]),
- .I3(\axi_araddr_reg[4]_5 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_araddr_reg[4]_6 ),
- .O(\axi_rdata[21]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[21]_i_14
- (.I0(\axi_rdata_reg[22]_0 ),
- .I1(\dac_ch_o_reg[0][31] [21]),
- .I2(\axi_rdata_reg[22]_1 ),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[21]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_16
- (.I0(\axi_rdata[21]_i_27_n_0 ),
- .I1(\fmc_03287_channels[19].gen_chs.data_o_reg[67][21] ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\fmc_03287_channels[15].gen_chs.data_o_reg[63][21] ),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .I5(\fmc_03287_channels[11].gen_chs.data_o_reg[59][21] ),
- .O(\axi_rdata[21]_i_16_n_0 ));
- LUT5 #(
- .INIT(32'hAFC0A0C0))
- \axi_rdata[21]_i_17
- (.I0(\axi_rdata[21]_i_31_n_0 ),
- .I1(\axi_rdata[21]_i_32_n_0 ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata[21]_i_33_n_0 ),
- .O(\axi_rdata[21]_i_17_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_2
- (.I0(\axi_rdata[21]_i_5_n_0 ),
- .I1(\axi_rdata_reg[21]_i_6_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata[21]_i_7_n_0 ),
- .I4(axi_araddr[7]),
- .I5(\axi_rdata[21]_i_8_n_0 ),
- .O(\axi_rdata[21]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[21]_i_20
- (.I0(\axi_rdata[21]_i_34_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [21]),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[21]_i_20_n_0 ));
- LUT5 #(
- .INIT(32'h0000B800))
- \axi_rdata[21]_i_23
- (.I0(\data_rw_o_reg_n_0_[11][21] ),
- .I1(\axi_rdata_reg[22]_1 ),
- .I2(\data_rw_o_reg_n_0_[10][21] ),
- .I3(\axi_rdata_reg[22]_0 ),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[21]_i_23_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT4 #(
- .INIT(16'h0080))
- \axi_rdata[21]_i_24
- (.I0(\axi_rdata_reg[22]_1 ),
- .I1(\data_rw_o_reg_n_0_[3][21] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[21]_i_24_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_25
- (.I0(\data_rw_o_reg_n_0_[99][21] ),
- .I1(\data_rw_o_reg_n_0_[98][21] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[97][21] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[96][21] ),
- .O(\axi_rdata[21]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_26
- (.I0(\data_rw_o_reg_n_0_[103][21] ),
- .I1(\data_rw_o_reg_n_0_[102][21] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[101][21] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[100][21] ),
- .O(\axi_rdata[21]_i_26_n_0 ));
- LUT4 #(
- .INIT(16'hA808))
- \axi_rdata[21]_i_27
- (.I0(\axi_rdata_reg[22]_0 ),
- .I1(\data_rw_o_reg_n_0_[78][21] ),
- .I2(\axi_rdata_reg[22]_1 ),
- .I3(\data_rw_o_reg_n_0_[79][21] ),
- .O(\axi_rdata[21]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_31
- (.I0(\data_rw_o_reg_n_0_[95][21] ),
- .I1(\data_rw_o_reg_n_0_[94][21] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[93][21] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[92][21] ),
- .O(\axi_rdata[21]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_32
- (.I0(\data_rw_o_reg_n_0_[91][21] ),
- .I1(\data_rw_o_reg_n_0_[90][21] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[89][21] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[88][21] ),
- .O(\axi_rdata[21]_i_32_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_33
- (.I0(\data_rw_o_reg_n_0_[87][21] ),
- .I1(\data_rw_o_reg_n_0_[86][21] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[85][21] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[84][21] ),
- .O(\axi_rdata[21]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_34
- (.I0(\data_rw_o_reg_n_0_[35][21] ),
- .I1(\data_rw_o_reg_n_0_[34][21] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[33][21] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[32][21] ),
- .O(\axi_rdata[21]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_35
- (.I0(\data_rw_o_reg_n_0_[27][21] ),
- .I1(\data_rw_o_reg_n_0_[26][21] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[25][21] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[24][21] ),
- .O(\axi_rdata[21]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_36
- (.I0(\data_rw_o_reg_n_0_[31][21] ),
- .I1(\data_rw_o_reg_n_0_[30][21] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[29][21] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[28][21] ),
- .O(\axi_rdata[21]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_37
- (.I0(\data_rw_o_reg_n_0_[19][21] ),
- .I1(\data_rw_o_reg_n_0_[18][21] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[17][21] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[16][21] ),
- .O(\axi_rdata[21]_i_37_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_38
- (.I0(\data_rw_o_reg_n_0_[23][21] ),
- .I1(\data_rw_o_reg_n_0_[22][21] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[21][21] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[20][21] ),
- .O(\axi_rdata[21]_i_38_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[21]_i_5
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][21]_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[21]_i_14_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[21]_i_15_n_0 ),
- .O(\axi_rdata[21]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[21]_i_7
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][21] ),
- .I2(\axi_rdata_reg[23]_0 [2]),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][21] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[21]_i_20_n_0 ),
- .O(\axi_rdata[21]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_8
- (.I0(\axi_rdata_reg[21]_i_21_n_0 ),
- .I1(\axi_rdata_reg[21]_i_22_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[21]_i_23_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata[21]_i_24_n_0 ),
- .O(\axi_rdata[21]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hA8A8A8080808A808))
- \axi_rdata[22]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata[22]_i_2_n_0 ),
- .I2(axi_araddr[9]),
- .I3(\axi_araddr_reg[4]_3 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_araddr_reg[4]_4 ),
- .O(\axi_rdata[22]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[22]_i_14
- (.I0(\axi_rdata_reg[22]_0 ),
- .I1(\dac_ch_o_reg[0][31] [22]),
- .I2(\axi_rdata_reg[22]_1 ),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[22]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_16
- (.I0(\axi_rdata[22]_i_27_n_0 ),
- .I1(\fmc_03287_channels[19].gen_chs.data_o_reg[67][22] ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\fmc_03287_channels[15].gen_chs.data_o_reg[63][22] ),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .I5(\fmc_03287_channels[11].gen_chs.data_o_reg[59][22] ),
- .O(\axi_rdata[22]_i_16_n_0 ));
- LUT5 #(
- .INIT(32'hAFC0A0C0))
- \axi_rdata[22]_i_17
- (.I0(\axi_rdata[22]_i_31_n_0 ),
- .I1(\axi_rdata[22]_i_32_n_0 ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata[22]_i_33_n_0 ),
- .O(\axi_rdata[22]_i_17_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_2
- (.I0(\axi_rdata[22]_i_5_n_0 ),
- .I1(\axi_rdata_reg[22]_i_6_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata[22]_i_7_n_0 ),
- .I4(axi_araddr[7]),
- .I5(\axi_rdata[22]_i_8_n_0 ),
- .O(\axi_rdata[22]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[22]_i_20
- (.I0(\axi_rdata[22]_i_34_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [22]),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[22]_i_20_n_0 ));
- LUT5 #(
- .INIT(32'h0000B800))
- \axi_rdata[22]_i_23
- (.I0(\data_rw_o_reg_n_0_[11][22] ),
- .I1(\axi_rdata_reg[22]_1 ),
- .I2(\data_rw_o_reg_n_0_[10][22] ),
- .I3(\axi_rdata_reg[22]_0 ),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[22]_i_23_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT4 #(
- .INIT(16'h4088))
- \axi_rdata[22]_i_24
- (.I0(\axi_rdata_reg[23]_0 [2]),
- .I1(\axi_rdata_reg[22]_0 ),
- .I2(\data_rw_o_reg_n_0_[3][22] ),
- .I3(\axi_rdata_reg[22]_1 ),
- .O(\axi_rdata[22]_i_24_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_25
- (.I0(\data_rw_o_reg_n_0_[99][22] ),
- .I1(\data_rw_o_reg_n_0_[98][22] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[97][22] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[96][22] ),
- .O(\axi_rdata[22]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_26
- (.I0(\data_rw_o_reg_n_0_[103][22] ),
- .I1(\data_rw_o_reg_n_0_[102][22] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[101][22] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[100][22] ),
- .O(\axi_rdata[22]_i_26_n_0 ));
- LUT4 #(
- .INIT(16'hA808))
- \axi_rdata[22]_i_27
- (.I0(\axi_rdata_reg[22]_0 ),
- .I1(\data_rw_o_reg_n_0_[78][22] ),
- .I2(\axi_rdata_reg[22]_1 ),
- .I3(\data_rw_o_reg_n_0_[79][22] ),
- .O(\axi_rdata[22]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_31
- (.I0(\data_rw_o_reg_n_0_[95][22] ),
- .I1(\data_rw_o_reg_n_0_[94][22] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[93][22] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[92][22] ),
- .O(\axi_rdata[22]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_32
- (.I0(\data_rw_o_reg_n_0_[91][22] ),
- .I1(\data_rw_o_reg_n_0_[90][22] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[89][22] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[88][22] ),
- .O(\axi_rdata[22]_i_32_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_33
- (.I0(\data_rw_o_reg_n_0_[87][22] ),
- .I1(\data_rw_o_reg_n_0_[86][22] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[85][22] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[84][22] ),
- .O(\axi_rdata[22]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_34
- (.I0(\data_rw_o_reg_n_0_[35][22] ),
- .I1(\data_rw_o_reg_n_0_[34][22] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[33][22] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[32][22] ),
- .O(\axi_rdata[22]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_35
- (.I0(\data_rw_o_reg_n_0_[27][22] ),
- .I1(\data_rw_o_reg_n_0_[26][22] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[25][22] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[24][22] ),
- .O(\axi_rdata[22]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_36
- (.I0(\data_rw_o_reg_n_0_[31][22] ),
- .I1(\data_rw_o_reg_n_0_[30][22] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[29][22] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[28][22] ),
- .O(\axi_rdata[22]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_37
- (.I0(\data_rw_o_reg_n_0_[19][22] ),
- .I1(\data_rw_o_reg_n_0_[18][22] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[17][22] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[16][22] ),
- .O(\axi_rdata[22]_i_37_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_38
- (.I0(\data_rw_o_reg_n_0_[23][22] ),
- .I1(\data_rw_o_reg_n_0_[22][22] ),
- .I2(\axi_rdata_reg[22]_0 ),
- .I3(\data_rw_o_reg_n_0_[21][22] ),
- .I4(\axi_rdata_reg[22]_1 ),
- .I5(\data_rw_o_reg_n_0_[20][22] ),
- .O(\axi_rdata[22]_i_38_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[22]_i_5
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][22]_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[22]_i_14_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[22]_i_15_n_0 ),
- .O(\axi_rdata[22]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[22]_i_7
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][22] ),
- .I2(\axi_rdata_reg[23]_0 [2]),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][22] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[22]_i_20_n_0 ),
- .O(\axi_rdata[22]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_8
- (.I0(\axi_rdata_reg[22]_i_21_n_0 ),
- .I1(\axi_rdata_reg[22]_i_22_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[22]_i_23_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata[22]_i_24_n_0 ),
- .O(\axi_rdata[22]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hA8A8A8080808A808))
- \axi_rdata[23]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata[23]_i_3_n_0 ),
- .I2(axi_araddr[9]),
- .I3(\axi_araddr_reg[4]_1 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_araddr_reg[4]_2 ),
- .O(\axi_rdata[23]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[23]_i_15
- (.I0(\axi_rdata_reg[23]_0 [1]),
- .I1(\dac_ch_o_reg[0][31] [23]),
- .I2(\axi_rdata_reg[23]_0 [0]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[23]_i_15_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_17
- (.I0(\axi_rdata[23]_i_28_n_0 ),
- .I1(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] ),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .I5(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] ),
- .O(\axi_rdata[23]_i_17_n_0 ));
- LUT5 #(
- .INIT(32'hAFC0A0C0))
- \axi_rdata[23]_i_18
- (.I0(\axi_rdata[23]_i_32_n_0 ),
- .I1(\axi_rdata[23]_i_33_n_0 ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata[23]_i_34_n_0 ),
- .O(\axi_rdata[23]_i_18_n_0 ));
- LUT4 #(
- .INIT(16'h01FF))
- \axi_rdata[23]_i_2
- (.I0(axi_araddr[7]),
- .I1(axi_araddr[6]),
- .I2(axi_araddr[8]),
- .I3(axi_araddr[9]),
- .O(\axi_rdata[23]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[23]_i_21
- (.I0(\axi_rdata[23]_i_35_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\dac_ch_o_reg[0][31]_0 [23]),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[23]_i_21_n_0 ));
- LUT5 #(
- .INIT(32'h0000B800))
- \axi_rdata[23]_i_24
- (.I0(\data_rw_o_reg_n_0_[11][23] ),
- .I1(\axi_rdata_reg[23]_0 [0]),
- .I2(\data_rw_o_reg_n_0_[10][23] ),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[23]_i_24_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT4 #(
- .INIT(16'hC888))
- \axi_rdata[23]_i_25
- (.I0(\axi_rdata_reg[23]_0 [2]),
- .I1(\axi_rdata_reg[23]_0 [1]),
- .I2(\data_rw_o_reg_n_0_[3][23] ),
- .I3(\axi_rdata_reg[23]_0 [0]),
- .O(\axi_rdata[23]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_26
- (.I0(\data_rw_o_reg_n_0_[99][23] ),
- .I1(\data_rw_o_reg_n_0_[98][23] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[97][23] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[96][23] ),
- .O(\axi_rdata[23]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_27
- (.I0(\data_rw_o_reg_n_0_[103][23] ),
- .I1(\data_rw_o_reg_n_0_[102][23] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[101][23] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[100][23] ),
- .O(\axi_rdata[23]_i_27_n_0 ));
- LUT4 #(
- .INIT(16'hA808))
- \axi_rdata[23]_i_28
- (.I0(\axi_rdata_reg[23]_0 [1]),
- .I1(\data_rw_o_reg_n_0_[78][23] ),
- .I2(\axi_rdata_reg[23]_0 [0]),
- .I3(\data_rw_o_reg_n_0_[79][23] ),
- .O(\axi_rdata[23]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_3
- (.I0(\axi_rdata[23]_i_6_n_0 ),
- .I1(\axi_rdata_reg[23]_i_7_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata[23]_i_8_n_0 ),
- .I4(axi_araddr[7]),
- .I5(\axi_rdata[23]_i_9_n_0 ),
- .O(\axi_rdata[23]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_32
- (.I0(\data_rw_o_reg_n_0_[95][23] ),
- .I1(\data_rw_o_reg_n_0_[94][23] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[93][23] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[92][23] ),
- .O(\axi_rdata[23]_i_32_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_33
- (.I0(\data_rw_o_reg_n_0_[91][23] ),
- .I1(\data_rw_o_reg_n_0_[90][23] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[89][23] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[88][23] ),
- .O(\axi_rdata[23]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_34
- (.I0(\data_rw_o_reg_n_0_[87][23] ),
- .I1(\data_rw_o_reg_n_0_[86][23] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[85][23] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[84][23] ),
- .O(\axi_rdata[23]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_35
- (.I0(\data_rw_o_reg_n_0_[35][23] ),
- .I1(\data_rw_o_reg_n_0_[34][23] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[33][23] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[32][23] ),
- .O(\axi_rdata[23]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_36
- (.I0(\data_rw_o_reg_n_0_[27][23] ),
- .I1(\data_rw_o_reg_n_0_[26][23] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[25][23] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[24][23] ),
- .O(\axi_rdata[23]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_37
- (.I0(\data_rw_o_reg_n_0_[31][23] ),
- .I1(\data_rw_o_reg_n_0_[30][23] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[29][23] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[28][23] ),
- .O(\axi_rdata[23]_i_37_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_38
- (.I0(\data_rw_o_reg_n_0_[19][23] ),
- .I1(\data_rw_o_reg_n_0_[18][23] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[17][23] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[16][23] ),
- .O(\axi_rdata[23]_i_38_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_39
- (.I0(\data_rw_o_reg_n_0_[23][23] ),
- .I1(\data_rw_o_reg_n_0_[22][23] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[21][23] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[20][23] ),
- .O(\axi_rdata[23]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[23]_i_6
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23]_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[23]_i_15_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[23]_i_16_n_0 ),
- .O(\axi_rdata[23]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[23]_i_8
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] ),
- .I2(\axi_rdata_reg[23]_0 [2]),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[23]_i_21_n_0 ),
- .O(\axi_rdata[23]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_9
- (.I0(\axi_rdata_reg[23]_i_22_n_0 ),
- .I1(\axi_rdata_reg[23]_i_23_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[23]_i_24_n_0 ),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata[23]_i_25_n_0 ),
- .O(\axi_rdata[23]_i_9_n_0 ));
- LUT4 #(
- .INIT(16'h4540))
- \axi_rdata[24]_i_1
- (.I0(axi_araddr[9]),
- .I1(\axi_rdata[24]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata[24]_i_3_n_0 ),
- .O(\axi_rdata[24]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[24]_i_11
- (.I0(\data_rw_o_reg_n_0_[95][24] ),
- .I1(\data_rw_o_reg_n_0_[94][24] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[93][24] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[92][24] ),
- .O(\axi_rdata[24]_i_11_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[24]_i_12
- (.I0(\data_rw_o_reg_n_0_[91][24] ),
- .I1(\data_rw_o_reg_n_0_[90][24] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[89][24] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[88][24] ),
- .O(\axi_rdata[24]_i_12_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[24]_i_13
- (.I0(\data_rw_o_reg_n_0_[87][24] ),
- .I1(\data_rw_o_reg_n_0_[86][24] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[85][24] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[84][24] ),
- .O(\axi_rdata[24]_i_13_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[24]_i_14
- (.I0(\data_rw_o_reg_n_0_[35][24] ),
- .I1(\data_rw_o_reg_n_0_[34][24] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[33][24] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[32][24] ),
- .O(\axi_rdata[24]_i_14_n_0 ));
- LUT5 #(
- .INIT(32'h0000B800))
- \axi_rdata[24]_i_17
- (.I0(\data_rw_o_reg_n_0_[11][24] ),
- .I1(\axi_rdata_reg[23]_0 [0]),
- .I2(\data_rw_o_reg_n_0_[10][24] ),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[24]_i_17_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[24]_i_18
- (.I0(\data_rw_o_reg_n_0_[99][24] ),
- .I1(\data_rw_o_reg_n_0_[98][24] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[97][24] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[96][24] ),
- .O(\axi_rdata[24]_i_18_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[24]_i_19
- (.I0(\data_rw_o_reg_n_0_[103][24] ),
- .I1(\data_rw_o_reg_n_0_[102][24] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[101][24] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[100][24] ),
- .O(\axi_rdata[24]_i_19_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[24]_i_2
- (.I0(\axi_rdata[24]_i_4_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata[24]_i_5_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[24]_i_6_n_0 ),
- .O(\axi_rdata[24]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[24]_i_20
- (.I0(\data_rw_o_reg_n_0_[19][24] ),
- .I1(\data_rw_o_reg_n_0_[18][24] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[17][24] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[16][24] ),
- .O(\axi_rdata[24]_i_20_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[24]_i_21
- (.I0(\data_rw_o_reg_n_0_[23][24] ),
- .I1(\data_rw_o_reg_n_0_[22][24] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[21][24] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[20][24] ),
- .O(\axi_rdata[24]_i_21_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[24]_i_22
- (.I0(\data_rw_o_reg_n_0_[27][24] ),
- .I1(\data_rw_o_reg_n_0_[26][24] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[25][24] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[24][24] ),
- .O(\axi_rdata[24]_i_22_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[24]_i_23
- (.I0(\data_rw_o_reg_n_0_[31][24] ),
- .I1(\data_rw_o_reg_n_0_[30][24] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[29][24] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[28][24] ),
- .O(\axi_rdata[24]_i_23_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[24]_i_3
- (.I0(\axi_rdata[24]_i_7_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata_reg[24]_i_8_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[24]_i_9_n_0 ),
- .O(\axi_rdata[24]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h0004FFFF00040000))
- \axi_rdata[24]_i_4
- (.I0(\axi_rdata_reg[23]_0 [1]),
- .I1(\dac_ch_o_reg[0][31] [24]),
- .I2(\axi_rdata_reg[23]_0 [0]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[24]_i_10_n_0 ),
- .O(\axi_rdata[24]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hAFC0A0C0))
- \axi_rdata[24]_i_5
- (.I0(\axi_rdata[24]_i_11_n_0 ),
- .I1(\axi_rdata[24]_i_12_n_0 ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata[24]_i_13_n_0 ),
- .O(\axi_rdata[24]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h8880008000000000))
- \axi_rdata[24]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\axi_rdata_reg[23]_0 [1]),
- .I2(\data_rw_o_reg_n_0_[78][24] ),
- .I3(\axi_rdata_reg[23]_0 [0]),
- .I4(\data_rw_o_reg_n_0_[79][24] ),
- .I5(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[24]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[24]_i_7
- (.I0(\axi_rdata[24]_i_14_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\dac_ch_o_reg[0][31]_0 [24]),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[24]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8B888888B888B888))
- \axi_rdata[24]_i_9
- (.I0(\axi_rdata[24]_i_17_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [3]),
- .I2(\axi_rdata_reg[23]_0 [2]),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\data_rw_o_reg_n_0_[3][24] ),
- .I5(\axi_rdata_reg[23]_0 [0]),
- .O(\axi_rdata[24]_i_9_n_0 ));
- LUT4 #(
- .INIT(16'h4540))
- \axi_rdata[25]_i_1
- (.I0(axi_araddr[9]),
- .I1(\axi_rdata[25]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata[25]_i_3_n_0 ),
- .O(\axi_rdata[25]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[25]_i_11
- (.I0(\data_rw_o_reg_n_0_[95][25] ),
- .I1(\data_rw_o_reg_n_0_[94][25] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[93][25] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[92][25] ),
- .O(\axi_rdata[25]_i_11_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[25]_i_12
- (.I0(\data_rw_o_reg_n_0_[91][25] ),
- .I1(\data_rw_o_reg_n_0_[90][25] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[89][25] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[88][25] ),
- .O(\axi_rdata[25]_i_12_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[25]_i_13
- (.I0(\data_rw_o_reg_n_0_[87][25] ),
- .I1(\data_rw_o_reg_n_0_[86][25] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[85][25] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[84][25] ),
- .O(\axi_rdata[25]_i_13_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[25]_i_14
- (.I0(\data_rw_o_reg_n_0_[35][25] ),
- .I1(\data_rw_o_reg_n_0_[34][25] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[33][25] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[32][25] ),
- .O(\axi_rdata[25]_i_14_n_0 ));
- LUT5 #(
- .INIT(32'h0000B800))
- \axi_rdata[25]_i_17
- (.I0(\data_rw_o_reg_n_0_[11][25] ),
- .I1(\axi_rdata_reg[23]_0 [0]),
- .I2(\data_rw_o_reg_n_0_[10][25] ),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[25]_i_17_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[25]_i_18
- (.I0(\data_rw_o_reg_n_0_[99][25] ),
- .I1(\data_rw_o_reg_n_0_[98][25] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[97][25] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[96][25] ),
- .O(\axi_rdata[25]_i_18_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[25]_i_19
- (.I0(\data_rw_o_reg_n_0_[103][25] ),
- .I1(\data_rw_o_reg_n_0_[102][25] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[101][25] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[100][25] ),
- .O(\axi_rdata[25]_i_19_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[25]_i_2
- (.I0(\axi_rdata[25]_i_4_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata[25]_i_5_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[25]_i_6_n_0 ),
- .O(\axi_rdata[25]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[25]_i_20
- (.I0(\data_rw_o_reg_n_0_[19][25] ),
- .I1(\data_rw_o_reg_n_0_[18][25] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[17][25] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[16][25] ),
- .O(\axi_rdata[25]_i_20_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[25]_i_21
- (.I0(\data_rw_o_reg_n_0_[23][25] ),
- .I1(\data_rw_o_reg_n_0_[22][25] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[21][25] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[20][25] ),
- .O(\axi_rdata[25]_i_21_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[25]_i_22
- (.I0(\data_rw_o_reg_n_0_[27][25] ),
- .I1(\data_rw_o_reg_n_0_[26][25] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[25][25] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[24][25] ),
- .O(\axi_rdata[25]_i_22_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[25]_i_23
- (.I0(\data_rw_o_reg_n_0_[31][25] ),
- .I1(\data_rw_o_reg_n_0_[30][25] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[29][25] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[28][25] ),
- .O(\axi_rdata[25]_i_23_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[25]_i_3
- (.I0(\axi_rdata[25]_i_7_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata_reg[25]_i_8_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[25]_i_9_n_0 ),
- .O(\axi_rdata[25]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h0004FFFF00040000))
- \axi_rdata[25]_i_4
- (.I0(\axi_rdata_reg[23]_0 [1]),
- .I1(\dac_ch_o_reg[0][31] [25]),
- .I2(\axi_rdata_reg[23]_0 [0]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[25]_i_10_n_0 ),
- .O(\axi_rdata[25]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hAFC0A0C0))
- \axi_rdata[25]_i_5
- (.I0(\axi_rdata[25]_i_11_n_0 ),
- .I1(\axi_rdata[25]_i_12_n_0 ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata[25]_i_13_n_0 ),
- .O(\axi_rdata[25]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h8880008000000000))
- \axi_rdata[25]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\axi_rdata_reg[23]_0 [1]),
- .I2(\data_rw_o_reg_n_0_[78][25] ),
- .I3(\axi_rdata_reg[23]_0 [0]),
- .I4(\data_rw_o_reg_n_0_[79][25] ),
- .I5(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[25]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[25]_i_7
- (.I0(\axi_rdata[25]_i_14_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\dac_ch_o_reg[0][31]_0 [25]),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[25]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h88888888B8888888))
- \axi_rdata[25]_i_9
- (.I0(\axi_rdata[25]_i_17_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [3]),
- .I2(\axi_rdata_reg[23]_0 [0]),
- .I3(\data_rw_o_reg_n_0_[3][25] ),
- .I4(\axi_rdata_reg[23]_0 [1]),
- .I5(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[25]_i_9_n_0 ));
- LUT4 #(
- .INIT(16'h4540))
- \axi_rdata[26]_i_1
- (.I0(axi_araddr[9]),
- .I1(\axi_rdata[26]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata[26]_i_3_n_0 ),
- .O(\axi_rdata[26]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[26]_i_11
- (.I0(\data_rw_o_reg_n_0_[95][26] ),
- .I1(\data_rw_o_reg_n_0_[94][26] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[93][26] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[92][26] ),
- .O(\axi_rdata[26]_i_11_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[26]_i_12
- (.I0(\data_rw_o_reg_n_0_[91][26] ),
- .I1(\data_rw_o_reg_n_0_[90][26] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[89][26] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[88][26] ),
- .O(\axi_rdata[26]_i_12_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[26]_i_13
- (.I0(\data_rw_o_reg_n_0_[87][26] ),
- .I1(\data_rw_o_reg_n_0_[86][26] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[85][26] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[84][26] ),
- .O(\axi_rdata[26]_i_13_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[26]_i_14
- (.I0(\data_rw_o_reg_n_0_[35][26] ),
- .I1(\data_rw_o_reg_n_0_[34][26] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[33][26] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[32][26] ),
- .O(\axi_rdata[26]_i_14_n_0 ));
- LUT5 #(
- .INIT(32'h0000B800))
- \axi_rdata[26]_i_17
- (.I0(\data_rw_o_reg_n_0_[11][26] ),
- .I1(\axi_rdata_reg[23]_0 [0]),
- .I2(\data_rw_o_reg_n_0_[10][26] ),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[26]_i_17_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[26]_i_18
- (.I0(\data_rw_o_reg_n_0_[99][26] ),
- .I1(\data_rw_o_reg_n_0_[98][26] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[97][26] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[96][26] ),
- .O(\axi_rdata[26]_i_18_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[26]_i_19
- (.I0(\data_rw_o_reg_n_0_[103][26] ),
- .I1(\data_rw_o_reg_n_0_[102][26] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[101][26] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[100][26] ),
- .O(\axi_rdata[26]_i_19_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[26]_i_2
- (.I0(\axi_rdata[26]_i_4_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata[26]_i_5_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[26]_i_6_n_0 ),
- .O(\axi_rdata[26]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[26]_i_20
- (.I0(\data_rw_o_reg_n_0_[19][26] ),
- .I1(\data_rw_o_reg_n_0_[18][26] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[17][26] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[16][26] ),
- .O(\axi_rdata[26]_i_20_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[26]_i_21
- (.I0(\data_rw_o_reg_n_0_[23][26] ),
- .I1(\data_rw_o_reg_n_0_[22][26] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[21][26] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[20][26] ),
- .O(\axi_rdata[26]_i_21_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[26]_i_22
- (.I0(\data_rw_o_reg_n_0_[27][26] ),
- .I1(\data_rw_o_reg_n_0_[26][26] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[25][26] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[24][26] ),
- .O(\axi_rdata[26]_i_22_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[26]_i_23
- (.I0(\data_rw_o_reg_n_0_[31][26] ),
- .I1(\data_rw_o_reg_n_0_[30][26] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[29][26] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[28][26] ),
- .O(\axi_rdata[26]_i_23_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[26]_i_3
- (.I0(\axi_rdata[26]_i_7_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata_reg[26]_i_8_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[26]_i_9_n_0 ),
- .O(\axi_rdata[26]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h0004FFFF00040000))
- \axi_rdata[26]_i_4
- (.I0(\axi_rdata_reg[23]_0 [1]),
- .I1(\dac_ch_o_reg[0][31] [26]),
- .I2(\axi_rdata_reg[23]_0 [0]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[26]_i_10_n_0 ),
- .O(\axi_rdata[26]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hAFC0A0C0))
- \axi_rdata[26]_i_5
- (.I0(\axi_rdata[26]_i_11_n_0 ),
- .I1(\axi_rdata[26]_i_12_n_0 ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata[26]_i_13_n_0 ),
- .O(\axi_rdata[26]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h8880008000000000))
- \axi_rdata[26]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\axi_rdata_reg[23]_0 [1]),
- .I2(\data_rw_o_reg_n_0_[78][26] ),
- .I3(\axi_rdata_reg[23]_0 [0]),
- .I4(\data_rw_o_reg_n_0_[79][26] ),
- .I5(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[26]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[26]_i_7
- (.I0(\axi_rdata[26]_i_14_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\dac_ch_o_reg[0][31]_0 [26]),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[26]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h88888888B8888888))
- \axi_rdata[26]_i_9
- (.I0(\axi_rdata[26]_i_17_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [3]),
- .I2(\axi_rdata_reg[23]_0 [0]),
- .I3(\data_rw_o_reg_n_0_[3][26] ),
- .I4(\axi_rdata_reg[23]_0 [1]),
- .I5(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[26]_i_9_n_0 ));
- LUT4 #(
- .INIT(16'h4540))
- \axi_rdata[27]_i_1
- (.I0(axi_araddr[9]),
- .I1(\axi_rdata[27]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata[27]_i_3_n_0 ),
- .O(\axi_rdata[27]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[27]_i_11
- (.I0(\data_rw_o_reg_n_0_[95][27] ),
- .I1(\data_rw_o_reg_n_0_[94][27] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[93][27] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[92][27] ),
- .O(\axi_rdata[27]_i_11_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[27]_i_12
- (.I0(\data_rw_o_reg_n_0_[91][27] ),
- .I1(\data_rw_o_reg_n_0_[90][27] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[89][27] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[88][27] ),
- .O(\axi_rdata[27]_i_12_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[27]_i_13
- (.I0(\data_rw_o_reg_n_0_[87][27] ),
- .I1(\data_rw_o_reg_n_0_[86][27] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[85][27] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[84][27] ),
- .O(\axi_rdata[27]_i_13_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[27]_i_14
- (.I0(\data_rw_o_reg_n_0_[35][27] ),
- .I1(\data_rw_o_reg_n_0_[34][27] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[33][27] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[32][27] ),
- .O(\axi_rdata[27]_i_14_n_0 ));
- LUT5 #(
- .INIT(32'h0000B800))
- \axi_rdata[27]_i_17
- (.I0(\data_rw_o_reg_n_0_[11][27] ),
- .I1(\axi_rdata_reg[23]_0 [0]),
- .I2(\data_rw_o_reg_n_0_[10][27] ),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[27]_i_17_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[27]_i_18
- (.I0(\data_rw_o_reg_n_0_[99][27] ),
- .I1(\data_rw_o_reg_n_0_[98][27] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[97][27] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[96][27] ),
- .O(\axi_rdata[27]_i_18_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[27]_i_19
- (.I0(\data_rw_o_reg_n_0_[103][27] ),
- .I1(\data_rw_o_reg_n_0_[102][27] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[101][27] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[100][27] ),
- .O(\axi_rdata[27]_i_19_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[27]_i_2
- (.I0(\axi_rdata[27]_i_4_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata[27]_i_5_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[27]_i_6_n_0 ),
- .O(\axi_rdata[27]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[27]_i_20
- (.I0(\data_rw_o_reg_n_0_[19][27] ),
- .I1(\data_rw_o_reg_n_0_[18][27] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[17][27] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[16][27] ),
- .O(\axi_rdata[27]_i_20_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[27]_i_21
- (.I0(\data_rw_o_reg_n_0_[23][27] ),
- .I1(\data_rw_o_reg_n_0_[22][27] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[21][27] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[20][27] ),
- .O(\axi_rdata[27]_i_21_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[27]_i_22
- (.I0(\data_rw_o_reg_n_0_[27][27] ),
- .I1(\data_rw_o_reg_n_0_[26][27] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[25][27] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[24][27] ),
- .O(\axi_rdata[27]_i_22_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[27]_i_23
- (.I0(\data_rw_o_reg_n_0_[31][27] ),
- .I1(\data_rw_o_reg_n_0_[30][27] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[29][27] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[28][27] ),
- .O(\axi_rdata[27]_i_23_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[27]_i_3
- (.I0(\axi_rdata[27]_i_7_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata_reg[27]_i_8_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[27]_i_9_n_0 ),
- .O(\axi_rdata[27]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h0004FFFF00040000))
- \axi_rdata[27]_i_4
- (.I0(\axi_rdata_reg[23]_0 [1]),
- .I1(\dac_ch_o_reg[0][31] [27]),
- .I2(\axi_rdata_reg[23]_0 [0]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[27]_i_10_n_0 ),
- .O(\axi_rdata[27]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hAFC0A0C0))
- \axi_rdata[27]_i_5
- (.I0(\axi_rdata[27]_i_11_n_0 ),
- .I1(\axi_rdata[27]_i_12_n_0 ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata[27]_i_13_n_0 ),
- .O(\axi_rdata[27]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h8880008000000000))
- \axi_rdata[27]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\axi_rdata_reg[23]_0 [1]),
- .I2(\data_rw_o_reg_n_0_[78][27] ),
- .I3(\axi_rdata_reg[23]_0 [0]),
- .I4(\data_rw_o_reg_n_0_[79][27] ),
- .I5(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[27]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[27]_i_7
- (.I0(\axi_rdata[27]_i_14_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\dac_ch_o_reg[0][31]_0 [27]),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[27]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8B888888B888B888))
- \axi_rdata[27]_i_9
- (.I0(\axi_rdata[27]_i_17_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [3]),
- .I2(\axi_rdata_reg[23]_0 [2]),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\data_rw_o_reg_n_0_[3][27] ),
- .I5(\axi_rdata_reg[23]_0 [0]),
- .O(\axi_rdata[27]_i_9_n_0 ));
- LUT4 #(
- .INIT(16'h4540))
- \axi_rdata[28]_i_1
- (.I0(axi_araddr[9]),
- .I1(\axi_rdata[28]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata[28]_i_3_n_0 ),
- .O(\axi_rdata[28]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[28]_i_11
- (.I0(\data_rw_o_reg_n_0_[95][28] ),
- .I1(\data_rw_o_reg_n_0_[94][28] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[93][28] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[92][28] ),
- .O(\axi_rdata[28]_i_11_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[28]_i_12
- (.I0(\data_rw_o_reg_n_0_[91][28] ),
- .I1(\data_rw_o_reg_n_0_[90][28] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[89][28] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[88][28] ),
- .O(\axi_rdata[28]_i_12_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[28]_i_13
- (.I0(\data_rw_o_reg_n_0_[87][28] ),
- .I1(\data_rw_o_reg_n_0_[86][28] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[85][28] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[84][28] ),
- .O(\axi_rdata[28]_i_13_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[28]_i_14
- (.I0(\data_rw_o_reg_n_0_[35][28] ),
- .I1(\data_rw_o_reg_n_0_[34][28] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[33][28] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[32][28] ),
- .O(\axi_rdata[28]_i_14_n_0 ));
- LUT5 #(
- .INIT(32'h0000B800))
- \axi_rdata[28]_i_17
- (.I0(\data_rw_o_reg_n_0_[11][28] ),
- .I1(\axi_rdata_reg[23]_0 [0]),
- .I2(\data_rw_o_reg_n_0_[10][28] ),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[28]_i_17_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[28]_i_18
- (.I0(\data_rw_o_reg_n_0_[99][28] ),
- .I1(\data_rw_o_reg_n_0_[98][28] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[97][28] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[96][28] ),
- .O(\axi_rdata[28]_i_18_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[28]_i_19
- (.I0(\data_rw_o_reg_n_0_[103][28] ),
- .I1(\data_rw_o_reg_n_0_[102][28] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[101][28] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[100][28] ),
- .O(\axi_rdata[28]_i_19_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[28]_i_2
- (.I0(\axi_rdata[28]_i_4_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata[28]_i_5_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[28]_i_6_n_0 ),
- .O(\axi_rdata[28]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[28]_i_20
- (.I0(\data_rw_o_reg_n_0_[19][28] ),
- .I1(\data_rw_o_reg_n_0_[18][28] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[17][28] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[16][28] ),
- .O(\axi_rdata[28]_i_20_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[28]_i_21
- (.I0(\data_rw_o_reg_n_0_[23][28] ),
- .I1(\data_rw_o_reg_n_0_[22][28] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[21][28] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[20][28] ),
- .O(\axi_rdata[28]_i_21_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[28]_i_22
- (.I0(\data_rw_o_reg_n_0_[27][28] ),
- .I1(\data_rw_o_reg_n_0_[26][28] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[25][28] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[24][28] ),
- .O(\axi_rdata[28]_i_22_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[28]_i_23
- (.I0(\data_rw_o_reg_n_0_[31][28] ),
- .I1(\data_rw_o_reg_n_0_[30][28] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[29][28] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[28][28] ),
- .O(\axi_rdata[28]_i_23_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[28]_i_3
- (.I0(\axi_rdata[28]_i_7_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata_reg[28]_i_8_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[28]_i_9_n_0 ),
- .O(\axi_rdata[28]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h0004FFFF00040000))
- \axi_rdata[28]_i_4
- (.I0(\axi_rdata_reg[23]_0 [1]),
- .I1(\dac_ch_o_reg[0][31] [28]),
- .I2(\axi_rdata_reg[23]_0 [0]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[28]_i_10_n_0 ),
- .O(\axi_rdata[28]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hAFC0A0C0))
- \axi_rdata[28]_i_5
- (.I0(\axi_rdata[28]_i_11_n_0 ),
- .I1(\axi_rdata[28]_i_12_n_0 ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata[28]_i_13_n_0 ),
- .O(\axi_rdata[28]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h8880008000000000))
- \axi_rdata[28]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\axi_rdata_reg[23]_0 [1]),
- .I2(\data_rw_o_reg_n_0_[78][28] ),
- .I3(\axi_rdata_reg[23]_0 [0]),
- .I4(\data_rw_o_reg_n_0_[79][28] ),
- .I5(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[28]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[28]_i_7
- (.I0(\axi_rdata[28]_i_14_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\dac_ch_o_reg[0][31]_0 [28]),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[28]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'hBB88B888B888B888))
- \axi_rdata[28]_i_9
- (.I0(\axi_rdata[28]_i_17_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [3]),
- .I2(\axi_rdata_reg[23]_0 [2]),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\data_rw_o_reg_n_0_[3][28] ),
- .I5(\axi_rdata_reg[23]_0 [0]),
- .O(\axi_rdata[28]_i_9_n_0 ));
- LUT4 #(
- .INIT(16'h4540))
- \axi_rdata[29]_i_1
- (.I0(axi_araddr[9]),
- .I1(\axi_rdata[29]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata[29]_i_3_n_0 ),
- .O(\axi_rdata[29]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[29]_i_11
- (.I0(\data_rw_o_reg_n_0_[95][29] ),
- .I1(\data_rw_o_reg_n_0_[94][29] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[93][29] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[92][29] ),
- .O(\axi_rdata[29]_i_11_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[29]_i_12
- (.I0(\data_rw_o_reg_n_0_[91][29] ),
- .I1(\data_rw_o_reg_n_0_[90][29] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[89][29] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[88][29] ),
- .O(\axi_rdata[29]_i_12_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[29]_i_13
- (.I0(\data_rw_o_reg_n_0_[87][29] ),
- .I1(\data_rw_o_reg_n_0_[86][29] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[85][29] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[84][29] ),
- .O(\axi_rdata[29]_i_13_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[29]_i_14
- (.I0(\data_rw_o_reg_n_0_[35][29] ),
- .I1(\data_rw_o_reg_n_0_[34][29] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[33][29] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[32][29] ),
- .O(\axi_rdata[29]_i_14_n_0 ));
- LUT5 #(
- .INIT(32'h0000B800))
- \axi_rdata[29]_i_17
- (.I0(\data_rw_o_reg_n_0_[11][29] ),
- .I1(\axi_rdata_reg[23]_0 [0]),
- .I2(\data_rw_o_reg_n_0_[10][29] ),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[29]_i_17_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[29]_i_18
- (.I0(\data_rw_o_reg_n_0_[99][29] ),
- .I1(\data_rw_o_reg_n_0_[98][29] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[97][29] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[96][29] ),
- .O(\axi_rdata[29]_i_18_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[29]_i_19
- (.I0(\data_rw_o_reg_n_0_[103][29] ),
- .I1(\data_rw_o_reg_n_0_[102][29] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[101][29] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[100][29] ),
- .O(\axi_rdata[29]_i_19_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[29]_i_2
- (.I0(\axi_rdata[29]_i_4_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata[29]_i_5_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[29]_i_6_n_0 ),
- .O(\axi_rdata[29]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[29]_i_20
- (.I0(\data_rw_o_reg_n_0_[19][29] ),
- .I1(\data_rw_o_reg_n_0_[18][29] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[17][29] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[16][29] ),
- .O(\axi_rdata[29]_i_20_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[29]_i_21
- (.I0(\data_rw_o_reg_n_0_[23][29] ),
- .I1(\data_rw_o_reg_n_0_[22][29] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[21][29] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[20][29] ),
- .O(\axi_rdata[29]_i_21_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[29]_i_22
- (.I0(\data_rw_o_reg_n_0_[27][29] ),
- .I1(\data_rw_o_reg_n_0_[26][29] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[25][29] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[24][29] ),
- .O(\axi_rdata[29]_i_22_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[29]_i_23
- (.I0(\data_rw_o_reg_n_0_[31][29] ),
- .I1(\data_rw_o_reg_n_0_[30][29] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[29][29] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[28][29] ),
- .O(\axi_rdata[29]_i_23_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[29]_i_3
- (.I0(\axi_rdata[29]_i_7_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata_reg[29]_i_8_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[29]_i_9_n_0 ),
- .O(\axi_rdata[29]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h0004FFFF00040000))
- \axi_rdata[29]_i_4
- (.I0(\axi_rdata_reg[23]_0 [1]),
- .I1(\dac_ch_o_reg[0][31] [29]),
- .I2(\axi_rdata_reg[23]_0 [0]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[29]_i_10_n_0 ),
- .O(\axi_rdata[29]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hAFC0A0C0))
- \axi_rdata[29]_i_5
- (.I0(\axi_rdata[29]_i_11_n_0 ),
- .I1(\axi_rdata[29]_i_12_n_0 ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata[29]_i_13_n_0 ),
- .O(\axi_rdata[29]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h8880008000000000))
- \axi_rdata[29]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\axi_rdata_reg[23]_0 [1]),
- .I2(\data_rw_o_reg_n_0_[78][29] ),
- .I3(\axi_rdata_reg[23]_0 [0]),
- .I4(\data_rw_o_reg_n_0_[79][29] ),
- .I5(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[29]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[29]_i_7
- (.I0(\axi_rdata[29]_i_14_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\dac_ch_o_reg[0][31]_0 [29]),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[29]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'hBB88B88888888888))
- \axi_rdata[29]_i_9
- (.I0(\axi_rdata[29]_i_17_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [3]),
- .I2(\axi_rdata_reg[23]_0 [2]),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\data_rw_o_reg_n_0_[3][29] ),
- .I5(\axi_rdata_reg[23]_0 [0]),
- .O(\axi_rdata[29]_i_9_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[2]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[2]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[2]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_rep_8 ),
- .O(\axi_rdata[2]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hEE555000EE005000))
- \axi_rdata[2]_i_14
- (.I0(\axi_rdata_reg[9]_0 ),
- .I1(\data_rw_o_reg_n_0_[3][2] ),
- .I2(gem_status_vector_i[2]),
- .I3(\axi_rdata_reg[2]_0 ),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\s_ins_reg[3] [2]),
- .O(\axi_rdata[2]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[2]_i_17
- (.I0(\axi_rdata[2]_i_35_n_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [2]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\axi_rdata_reg[10]_0 ),
- .O(\axi_rdata[2]_i_17_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[2]_i_23
- (.I0(\axi_rdata_reg[2]_0 ),
- .I1(\dac_ch_o_reg[0][31] [2]),
- .I2(\axi_rdata_reg[2]_1 ),
- .I3(\axi_rdata_reg[9]_0 ),
- .O(\axi_rdata[2]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_29
- (.I0(\[2].[3].s_reqs_reg[11][value][11] [2]),
- .I1(\[2].[2].s_reqs_reg[10][value][11] [2]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11] [2]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11] [2]),
- .O(\axi_rdata[2]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_30
- (.I0(\[3].[3].s_reqs_reg[15][value][11] [2]),
- .I1(\[3].[2].s_reqs_reg[14][value][11] [2]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11] [2]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11] [2]),
- .O(\axi_rdata[2]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_31
- (.I0(Q[2]),
- .I1(\[0].[2].s_reqs_reg[2][value][11] [2]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11] [2]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [2]),
- .O(\axi_rdata[2]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_32
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [2]),
- .I1(\[1].[2].s_reqs_reg[6][value][11] [2]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11] [2]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [2]),
- .O(\axi_rdata[2]_i_32_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_33
- (.I0(\v_dout_reg[7] [1]),
- .I1(\data_rw_o_reg_n_0_[10][2] ),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\data_o_reg[1][3] [2]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\s_datao_fmc1[0] [2]),
- .O(\axi_rdata[2]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_35
- (.I0(\[4].[3].s_reqs_reg[19][value][11] [2]),
- .I1(\[4].[2].s_reqs_reg[18][value][11] [2]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11] [2]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11] [2]),
- .O(\axi_rdata[2]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_36
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [2]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_0 [2]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_0 [2]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [2]),
- .O(\axi_rdata[2]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_37
- (.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [2]),
- .I1(\[2].[2].s_reqs_reg[10][value][11]_0 [2]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11]_0 [2]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11]_0 [2]),
- .O(\axi_rdata[2]_i_37_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_39
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [2]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_0 [2]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_0 [2]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [2]),
- .O(\axi_rdata[2]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_41
- (.I0(\v_dout_reg[7]_0 [1]),
- .I1(\data_rw_o_reg_n_0_[78][2] ),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\data_o_reg[1][3]_0 [2]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\s_datao_fmc2[0] [2]),
- .O(\axi_rdata[2]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_44
- (.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [2]),
- .I1(\[3].[2].s_reqs_reg[14][value][11]_0 [2]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11]_0 [2]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11]_0 [2]),
- .O(\axi_rdata[2]_i_44_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_45
- (.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [2]),
- .I1(\[4].[2].s_reqs_reg[18][value][11]_0 [2]),
- .I2(\axi_rdata_reg[2]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11]_0 [2]),
- .I4(\axi_rdata_reg[2]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11]_0 [2]),
- .O(\axi_rdata[2]_i_45_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_5
- (.I0(\axi_rdata_reg[2]_i_11_n_0 ),
- .I1(\axi_rdata_reg[2]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[2]_i_13_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata[2]_i_14_n_0 ),
- .O(\axi_rdata[2]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[2]_i_6
- (.I0(\axi_rdata_reg[10]_0 ),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][2] ),
- .I2(\axi_rdata_reg[9]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][2] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[2]_i_17_n_0 ),
- .O(\axi_rdata[2]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_7
- (.I0(\axi_rdata_reg[2]_i_18_n_0 ),
- .I1(\axi_rdata_reg[2]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[2]_i_20_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_araddr_reg[4]_rep__0_1 ),
- .O(\axi_rdata[2]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[2]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][2]_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[2]_i_23_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata_reg[2]_i_24_n_0 ),
- .O(\axi_rdata[2]_i_8_n_0 ));
- LUT4 #(
- .INIT(16'h4540))
- \axi_rdata[30]_i_1
- (.I0(axi_araddr[9]),
- .I1(\axi_rdata[30]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata[30]_i_3_n_0 ),
- .O(\axi_rdata[30]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[30]_i_11
- (.I0(\data_rw_o_reg_n_0_[95][30] ),
- .I1(\data_rw_o_reg_n_0_[94][30] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[93][30] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[92][30] ),
- .O(\axi_rdata[30]_i_11_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[30]_i_12
- (.I0(\data_rw_o_reg_n_0_[91][30] ),
- .I1(\data_rw_o_reg_n_0_[90][30] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[89][30] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[88][30] ),
- .O(\axi_rdata[30]_i_12_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[30]_i_13
- (.I0(\data_rw_o_reg_n_0_[87][30] ),
- .I1(\data_rw_o_reg_n_0_[86][30] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[85][30] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[84][30] ),
- .O(\axi_rdata[30]_i_13_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[30]_i_14
- (.I0(\data_rw_o_reg_n_0_[35][30] ),
- .I1(\data_rw_o_reg_n_0_[34][30] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[33][30] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[32][30] ),
- .O(\axi_rdata[30]_i_14_n_0 ));
- LUT5 #(
- .INIT(32'h0000B800))
- \axi_rdata[30]_i_17
- (.I0(\data_rw_o_reg_n_0_[11][30] ),
- .I1(\axi_rdata_reg[23]_0 [0]),
- .I2(\data_rw_o_reg_n_0_[10][30] ),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[30]_i_17_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[30]_i_18
- (.I0(\data_rw_o_reg_n_0_[99][30] ),
- .I1(\data_rw_o_reg_n_0_[98][30] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[97][30] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[96][30] ),
- .O(\axi_rdata[30]_i_18_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[30]_i_19
- (.I0(\data_rw_o_reg_n_0_[103][30] ),
- .I1(\data_rw_o_reg_n_0_[102][30] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[101][30] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[100][30] ),
- .O(\axi_rdata[30]_i_19_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[30]_i_2
- (.I0(\axi_rdata[30]_i_4_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata[30]_i_5_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[30]_i_6_n_0 ),
- .O(\axi_rdata[30]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[30]_i_20
- (.I0(\data_rw_o_reg_n_0_[19][30] ),
- .I1(\data_rw_o_reg_n_0_[18][30] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[17][30] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[16][30] ),
- .O(\axi_rdata[30]_i_20_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[30]_i_21
- (.I0(\data_rw_o_reg_n_0_[23][30] ),
- .I1(\data_rw_o_reg_n_0_[22][30] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[21][30] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[20][30] ),
- .O(\axi_rdata[30]_i_21_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[30]_i_22
- (.I0(\data_rw_o_reg_n_0_[27][30] ),
- .I1(\data_rw_o_reg_n_0_[26][30] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[25][30] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[24][30] ),
- .O(\axi_rdata[30]_i_22_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[30]_i_23
- (.I0(\data_rw_o_reg_n_0_[31][30] ),
- .I1(\data_rw_o_reg_n_0_[30][30] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[29][30] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[28][30] ),
- .O(\axi_rdata[30]_i_23_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[30]_i_3
- (.I0(\axi_rdata[30]_i_7_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata_reg[30]_i_8_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[30]_i_9_n_0 ),
- .O(\axi_rdata[30]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h0004FFFF00040000))
- \axi_rdata[30]_i_4
- (.I0(\axi_rdata_reg[23]_0 [1]),
- .I1(\dac_ch_o_reg[0][31] [30]),
- .I2(\axi_rdata_reg[23]_0 [0]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[30]_i_10_n_0 ),
- .O(\axi_rdata[30]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hAFC0A0C0))
- \axi_rdata[30]_i_5
- (.I0(\axi_rdata[30]_i_11_n_0 ),
- .I1(\axi_rdata[30]_i_12_n_0 ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata[30]_i_13_n_0 ),
- .O(\axi_rdata[30]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h8880008000000000))
- \axi_rdata[30]_i_6
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\axi_rdata_reg[23]_0 [1]),
- .I2(\data_rw_o_reg_n_0_[78][30] ),
- .I3(\axi_rdata_reg[23]_0 [0]),
- .I4(\data_rw_o_reg_n_0_[79][30] ),
- .I5(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[30]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[30]_i_7
- (.I0(\axi_rdata[30]_i_14_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\dac_ch_o_reg[0][31]_0 [30]),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[30]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'hBB88B888B888B888))
- \axi_rdata[30]_i_9
- (.I0(\axi_rdata[30]_i_17_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [3]),
- .I2(\axi_rdata_reg[23]_0 [2]),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\data_rw_o_reg_n_0_[3][30] ),
- .I5(\axi_rdata_reg[23]_0 [0]),
- .O(\axi_rdata[30]_i_9_n_0 ));
- LUT3 #(
- .INIT(8'h08))
- \axi_rdata[31]_i_1
- (.I0(s00_axi_arready),
- .I1(s00_axi_arvalid),
- .I2(s00_axi_rvalid),
- .O(\axi_rdata[31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hBB88B88888888888))
- \axi_rdata[31]_i_10
- (.I0(\axi_rdata[31]_i_18_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [3]),
- .I2(\axi_rdata_reg[23]_0 [2]),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\data_rw_o_reg_n_0_[3][31] ),
- .I5(\axi_rdata_reg[23]_0 [0]),
- .O(\axi_rdata[31]_i_10_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[31]_i_12
- (.I0(\data_rw_o_reg_n_0_[95][31] ),
- .I1(\data_rw_o_reg_n_0_[94][31] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[93][31] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[92][31] ),
- .O(\axi_rdata[31]_i_12_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[31]_i_13
- (.I0(\data_rw_o_reg_n_0_[91][31] ),
- .I1(\data_rw_o_reg_n_0_[90][31] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[89][31] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[88][31] ),
- .O(\axi_rdata[31]_i_13_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[31]_i_14
- (.I0(\data_rw_o_reg_n_0_[87][31] ),
- .I1(\data_rw_o_reg_n_0_[86][31] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[85][31] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[84][31] ),
- .O(\axi_rdata[31]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[31]_i_15
- (.I0(\data_rw_o_reg_n_0_[35][31] ),
- .I1(\data_rw_o_reg_n_0_[34][31] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[33][31] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[32][31] ),
- .O(\axi_rdata[31]_i_15_n_0 ));
- LUT5 #(
- .INIT(32'h0000B800))
- \axi_rdata[31]_i_18
- (.I0(\data_rw_o_reg_n_0_[11][31] ),
- .I1(\axi_rdata_reg[23]_0 [0]),
- .I2(\data_rw_o_reg_n_0_[10][31] ),
- .I3(\axi_rdata_reg[23]_0 [1]),
- .I4(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[31]_i_18_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[31]_i_19
- (.I0(\data_rw_o_reg_n_0_[99][31] ),
- .I1(\data_rw_o_reg_n_0_[98][31] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[97][31] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[96][31] ),
- .O(\axi_rdata[31]_i_19_n_0 ));
- LUT4 #(
- .INIT(16'h4540))
- \axi_rdata[31]_i_2
- (.I0(axi_araddr[9]),
- .I1(\axi_rdata[31]_i_3_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata[31]_i_4_n_0 ),
- .O(\axi_rdata[31]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[31]_i_20
- (.I0(\data_rw_o_reg_n_0_[103][31] ),
- .I1(\data_rw_o_reg_n_0_[102][31] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[101][31] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[100][31] ),
- .O(\axi_rdata[31]_i_20_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[31]_i_21
- (.I0(\data_rw_o_reg_n_0_[19][31] ),
- .I1(\data_rw_o_reg_n_0_[18][31] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[17][31] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[16][31] ),
- .O(\axi_rdata[31]_i_21_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[31]_i_22
- (.I0(\data_rw_o_reg_n_0_[23][31] ),
- .I1(\data_rw_o_reg_n_0_[22][31] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[21][31] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[20][31] ),
- .O(\axi_rdata[31]_i_22_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[31]_i_23
- (.I0(\data_rw_o_reg_n_0_[27][31] ),
- .I1(\data_rw_o_reg_n_0_[26][31] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[25][31] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[24][31] ),
- .O(\axi_rdata[31]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[31]_i_24
- (.I0(\data_rw_o_reg_n_0_[31][31] ),
- .I1(\data_rw_o_reg_n_0_[30][31] ),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\data_rw_o_reg_n_0_[29][31] ),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\data_rw_o_reg_n_0_[28][31] ),
- .O(\axi_rdata[31]_i_24_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[31]_i_3
- (.I0(\axi_rdata[31]_i_5_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata[31]_i_6_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[31]_i_7_n_0 ),
- .O(\axi_rdata[31]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[31]_i_4
- (.I0(\axi_rdata[31]_i_8_n_0 ),
- .I1(axi_araddr[7]),
- .I2(\axi_rdata_reg[31]_i_9_n_0 ),
- .I3(axi_araddr[6]),
- .I4(\axi_rdata[31]_i_10_n_0 ),
- .O(\axi_rdata[31]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h0004FFFF00040000))
- \axi_rdata[31]_i_5
- (.I0(\axi_rdata_reg[23]_0 [1]),
- .I1(\dac_ch_o_reg[0][31] [31]),
- .I2(\axi_rdata_reg[23]_0 [0]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata_reg[23]_0 [3]),
- .I5(\axi_rdata_reg[31]_i_11_n_0 ),
- .O(\axi_rdata[31]_i_5_n_0 ));
- LUT5 #(
- .INIT(32'hAFC0A0C0))
- \axi_rdata[31]_i_6
- (.I0(\axi_rdata[31]_i_12_n_0 ),
- .I1(\axi_rdata[31]_i_13_n_0 ),
- .I2(\axi_rdata_reg[23]_0 [3]),
- .I3(\axi_rdata_reg[23]_0 [2]),
- .I4(\axi_rdata[31]_i_14_n_0 ),
- .O(\axi_rdata[31]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'h8880008000000000))
- \axi_rdata[31]_i_7
- (.I0(\axi_rdata_reg[23]_0 [3]),
- .I1(\axi_rdata_reg[23]_0 [1]),
- .I2(\data_rw_o_reg_n_0_[78][31] ),
- .I3(\axi_rdata_reg[23]_0 [0]),
- .I4(\data_rw_o_reg_n_0_[79][31] ),
- .I5(\axi_rdata_reg[23]_0 [2]),
- .O(\axi_rdata[31]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[31]_i_8
- (.I0(\axi_rdata[31]_i_15_n_0 ),
- .I1(\axi_rdata_reg[23]_0 [2]),
- .I2(\axi_rdata_reg[23]_0 [1]),
- .I3(\dac_ch_o_reg[0][31]_0 [31]),
- .I4(\axi_rdata_reg[23]_0 [0]),
- .I5(\axi_rdata_reg[23]_0 [3]),
- .O(\axi_rdata[31]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[3]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[3]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[3]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_rep_7 ),
- .O(\axi_rdata[3]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h00000000F8C83808))
- \axi_rdata[3]_i_14
- (.I0(\s_ins_reg[3] [3]),
- .I1(\axi_rdata_reg[7]_1 ),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(gem_status_vector_i[3]),
- .I4(\data_rw_o_reg_n_0_[3][3] ),
- .I5(\axi_rdata_reg[9]_0 ),
- .O(\axi_rdata[3]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[3]_i_17
- (.I0(\axi_rdata[3]_i_35_n_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [3]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\axi_rdata_reg[10]_0 ),
- .O(\axi_rdata[3]_i_17_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[3]_i_23
- (.I0(\axi_rdata_reg[7]_0 ),
- .I1(\dac_ch_o_reg[0][31] [3]),
- .I2(\axi_rdata_reg[7]_1 ),
- .I3(\axi_rdata_reg[9]_0 ),
- .O(\axi_rdata[3]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_29
- (.I0(\[2].[3].s_reqs_reg[11][value][11] [3]),
- .I1(\[2].[2].s_reqs_reg[10][value][11] [3]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11] [3]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11] [3]),
- .O(\axi_rdata[3]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_30
- (.I0(\[3].[3].s_reqs_reg[15][value][11] [3]),
- .I1(\[3].[2].s_reqs_reg[14][value][11] [3]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11] [3]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11] [3]),
- .O(\axi_rdata[3]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_31
- (.I0(Q[3]),
- .I1(\[0].[2].s_reqs_reg[2][value][11] [3]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11] [3]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [3]),
- .O(\axi_rdata[3]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_32
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [3]),
- .I1(\[1].[2].s_reqs_reg[6][value][11] [3]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11] [3]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [3]),
- .O(\axi_rdata[3]_i_32_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][3] ),
- .I1(\data_rw_o_reg_n_0_[10][3] ),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\data_o_reg[1][3] [3]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\s_datao_fmc1[0] [3]),
- .O(\axi_rdata[3]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_35
- (.I0(\[4].[3].s_reqs_reg[19][value][11] [3]),
- .I1(\[4].[2].s_reqs_reg[18][value][11] [3]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11] [3]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11] [3]),
- .O(\axi_rdata[3]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_36
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [3]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_0 [3]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_0 [3]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [3]),
- .O(\axi_rdata[3]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_37
- (.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [3]),
- .I1(\[2].[2].s_reqs_reg[10][value][11]_0 [3]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11]_0 [3]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11]_0 [3]),
- .O(\axi_rdata[3]_i_37_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_39
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [3]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_0 [3]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_0 [3]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [3]),
- .O(\axi_rdata[3]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_41
- (.I0(\data_rw_o_reg_n_0_[79][3] ),
- .I1(\data_rw_o_reg_n_0_[78][3] ),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\data_o_reg[1][3]_0 [3]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\s_datao_fmc2[0] [3]),
- .O(\axi_rdata[3]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_44
- (.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [3]),
- .I1(\[3].[2].s_reqs_reg[14][value][11]_0 [3]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11]_0 [3]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11]_0 [3]),
- .O(\axi_rdata[3]_i_44_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_45
- (.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [3]),
- .I1(\[4].[2].s_reqs_reg[18][value][11]_0 [3]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11]_0 [3]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11]_0 [3]),
- .O(\axi_rdata[3]_i_45_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_5
- (.I0(\axi_rdata_reg[3]_i_11_n_0 ),
- .I1(\axi_rdata_reg[3]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[3]_i_13_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata[3]_i_14_n_0 ),
- .O(\axi_rdata[3]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[3]_i_6
- (.I0(\axi_rdata_reg[10]_0 ),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][3] ),
- .I2(\axi_rdata_reg[9]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][3] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[3]_i_17_n_0 ),
- .O(\axi_rdata[3]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_7
- (.I0(\axi_rdata_reg[3]_i_18_n_0 ),
- .I1(\axi_rdata_reg[3]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[3]_i_20_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_araddr_reg[4]_rep__0_2 ),
- .O(\axi_rdata[3]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[3]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][3]_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[3]_i_23_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata_reg[3]_i_24_n_0 ),
- .O(\axi_rdata[3]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[4]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[4]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[4]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_rep_6 ),
- .O(\axi_rdata[4]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hCC408840))
- \axi_rdata[4]_i_14
- (.I0(\axi_rdata_reg[9]_0 ),
- .I1(\axi_rdata_reg[7]_0 ),
- .I2(gem_status_vector_i[4]),
- .I3(\axi_rdata_reg[7]_1 ),
- .I4(\data_rw_o_reg_n_0_[3][4] ),
- .O(\axi_rdata[4]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[4]_i_17
- (.I0(\axi_rdata[4]_i_35_n_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [4]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\axi_rdata_reg[10]_0 ),
- .O(\axi_rdata[4]_i_17_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[4]_i_23
- (.I0(\axi_rdata_reg[7]_0 ),
- .I1(\dac_ch_o_reg[0][31] [4]),
- .I2(\axi_rdata_reg[7]_1 ),
- .I3(\axi_rdata_reg[9]_0 ),
- .O(\axi_rdata[4]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_29
- (.I0(\[2].[3].s_reqs_reg[11][value][11] [4]),
- .I1(\[2].[2].s_reqs_reg[10][value][11] [4]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11] [4]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11] [4]),
- .O(\axi_rdata[4]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_30
- (.I0(\[3].[3].s_reqs_reg[15][value][11] [4]),
- .I1(\[3].[2].s_reqs_reg[14][value][11] [4]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11] [4]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11] [4]),
- .O(\axi_rdata[4]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_31
- (.I0(Q[4]),
- .I1(\[0].[2].s_reqs_reg[2][value][11] [4]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11] [4]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [4]),
- .O(\axi_rdata[4]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_32
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [4]),
- .I1(\[1].[2].s_reqs_reg[6][value][11] [4]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11] [4]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [4]),
- .O(\axi_rdata[4]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[4]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][4] ),
- .I1(\data_rw_o[10] [4]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\s_datao_fmc1[0] [4]),
- .I4(\axi_rdata_reg[7]_1 ),
- .O(\axi_rdata[4]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_35
- (.I0(\[4].[3].s_reqs_reg[19][value][11] [4]),
- .I1(\[4].[2].s_reqs_reg[18][value][11] [4]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11] [4]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11] [4]),
- .O(\axi_rdata[4]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_36
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [4]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_0 [4]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_0 [4]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [4]),
- .O(\axi_rdata[4]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_37
- (.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [4]),
- .I1(\[2].[2].s_reqs_reg[10][value][11]_0 [4]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11]_0 [4]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11]_0 [4]),
- .O(\axi_rdata[4]_i_37_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_39
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [4]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_0 [4]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_0 [4]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [4]),
- .O(\axi_rdata[4]_i_39_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[4]_i_41
- (.I0(\data_rw_o_reg_n_0_[79][4] ),
- .I1(\data_rw_o[78] [4]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\s_datao_fmc2[0] [4]),
- .I4(\axi_rdata_reg[7]_1 ),
- .O(\axi_rdata[4]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_44
- (.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [4]),
- .I1(\[3].[2].s_reqs_reg[14][value][11]_0 [4]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11]_0 [4]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11]_0 [4]),
- .O(\axi_rdata[4]_i_44_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_45
- (.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [4]),
- .I1(\[4].[2].s_reqs_reg[18][value][11]_0 [4]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11]_0 [4]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11]_0 [4]),
- .O(\axi_rdata[4]_i_45_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_5
- (.I0(\axi_rdata_reg[4]_i_11_n_0 ),
- .I1(\axi_rdata_reg[4]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[4]_i_13_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata[4]_i_14_n_0 ),
- .O(\axi_rdata[4]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[4]_i_6
- (.I0(\axi_rdata_reg[10]_0 ),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][4] ),
- .I2(\axi_rdata_reg[9]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][4] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[4]_i_17_n_0 ),
- .O(\axi_rdata[4]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_7
- (.I0(\axi_rdata_reg[4]_i_18_n_0 ),
- .I1(\axi_rdata_reg[4]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[4]_i_20_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_araddr_reg[4]_rep__0_3 ),
- .O(\axi_rdata[4]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[4]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][4]_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[4]_i_23_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata_reg[4]_i_24_n_0 ),
- .O(\axi_rdata[4]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[5]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[5]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[5]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_rep_5 ),
- .O(\axi_rdata[5]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h0000B800))
- \axi_rdata[5]_i_14
- (.I0(\data_rw_o_reg_n_0_[3][5] ),
- .I1(\axi_rdata_reg[7]_1 ),
- .I2(gem_status_vector_i[5]),
- .I3(\axi_rdata_reg[7]_0 ),
- .I4(\axi_rdata_reg[9]_0 ),
- .O(\axi_rdata[5]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[5]_i_17
- (.I0(\axi_rdata[5]_i_35_n_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [5]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\axi_rdata_reg[10]_0 ),
- .O(\axi_rdata[5]_i_17_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[5]_i_23
- (.I0(\axi_rdata_reg[7]_0 ),
- .I1(\dac_ch_o_reg[0][31] [5]),
- .I2(\axi_rdata_reg[7]_1 ),
- .I3(\axi_rdata_reg[9]_0 ),
- .O(\axi_rdata[5]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_29
- (.I0(\[2].[3].s_reqs_reg[11][value][11] [5]),
- .I1(\[2].[2].s_reqs_reg[10][value][11] [5]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11] [5]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11] [5]),
- .O(\axi_rdata[5]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_30
- (.I0(\[3].[3].s_reqs_reg[15][value][11] [5]),
- .I1(\[3].[2].s_reqs_reg[14][value][11] [5]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11] [5]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11] [5]),
- .O(\axi_rdata[5]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_31
- (.I0(Q[5]),
- .I1(\[0].[2].s_reqs_reg[2][value][11] [5]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11] [5]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [5]),
- .O(\axi_rdata[5]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_32
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [5]),
- .I1(\[1].[2].s_reqs_reg[6][value][11] [5]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11] [5]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [5]),
- .O(\axi_rdata[5]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[5]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][5] ),
- .I1(\data_rw_o[10] [5]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\s_datao_fmc1[0] [5]),
- .I4(\axi_rdata_reg[7]_1 ),
- .O(\axi_rdata[5]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_35
- (.I0(\[4].[3].s_reqs_reg[19][value][11] [5]),
- .I1(\[4].[2].s_reqs_reg[18][value][11] [5]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11] [5]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11] [5]),
- .O(\axi_rdata[5]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_36
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [5]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_0 [5]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_0 [5]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [5]),
- .O(\axi_rdata[5]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_37
- (.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [5]),
- .I1(\[2].[2].s_reqs_reg[10][value][11]_0 [5]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11]_0 [5]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11]_0 [5]),
- .O(\axi_rdata[5]_i_37_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_39
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [5]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_0 [5]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_0 [5]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [5]),
- .O(\axi_rdata[5]_i_39_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[5]_i_41
- (.I0(\data_rw_o_reg_n_0_[79][5] ),
- .I1(\data_rw_o[78] [5]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\s_datao_fmc2[0] [5]),
- .I4(\axi_rdata_reg[7]_1 ),
- .O(\axi_rdata[5]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_44
- (.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [5]),
- .I1(\[3].[2].s_reqs_reg[14][value][11]_0 [5]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11]_0 [5]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11]_0 [5]),
- .O(\axi_rdata[5]_i_44_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_45
- (.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [5]),
- .I1(\[4].[2].s_reqs_reg[18][value][11]_0 [5]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11]_0 [5]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11]_0 [5]),
- .O(\axi_rdata[5]_i_45_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_5
- (.I0(\axi_rdata_reg[5]_i_11_n_0 ),
- .I1(\axi_rdata_reg[5]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[5]_i_13_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata[5]_i_14_n_0 ),
- .O(\axi_rdata[5]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[5]_i_6
- (.I0(\axi_rdata_reg[10]_0 ),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][5] ),
- .I2(\axi_rdata_reg[9]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][5] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[5]_i_17_n_0 ),
- .O(\axi_rdata[5]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_7
- (.I0(\axi_rdata_reg[5]_i_18_n_0 ),
- .I1(\axi_rdata_reg[5]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[5]_i_20_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_araddr_reg[4]_rep__0_4 ),
- .O(\axi_rdata[5]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[5]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][5]_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[5]_i_23_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata_reg[5]_i_24_n_0 ),
- .O(\axi_rdata[5]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[6]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[6]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[6]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_rep_4 ),
- .O(\axi_rdata[6]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h44C800C8))
- \axi_rdata[6]_i_14
- (.I0(\axi_rdata_reg[9]_0 ),
- .I1(\axi_rdata_reg[7]_0 ),
- .I2(gem_status_vector_i[6]),
- .I3(\axi_rdata_reg[7]_1 ),
- .I4(\data_rw_o_reg_n_0_[3][6] ),
- .O(\axi_rdata[6]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[6]_i_17
- (.I0(\axi_rdata[6]_i_35_n_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [6]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\axi_rdata_reg[10]_0 ),
- .O(\axi_rdata[6]_i_17_n_0 ));
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[6]_i_23
- (.I0(\axi_rdata_reg[7]_0 ),
- .I1(\dac_ch_o_reg[0][31] [6]),
- .I2(\axi_rdata_reg[7]_1 ),
- .I3(\axi_rdata_reg[9]_0 ),
- .O(\axi_rdata[6]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_29
- (.I0(\[2].[3].s_reqs_reg[11][value][11] [6]),
- .I1(\[2].[2].s_reqs_reg[10][value][11] [6]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11] [6]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11] [6]),
- .O(\axi_rdata[6]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_30
- (.I0(\[3].[3].s_reqs_reg[15][value][11] [6]),
- .I1(\[3].[2].s_reqs_reg[14][value][11] [6]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11] [6]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11] [6]),
- .O(\axi_rdata[6]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_31
- (.I0(Q[6]),
- .I1(\[0].[2].s_reqs_reg[2][value][11] [6]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11] [6]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [6]),
- .O(\axi_rdata[6]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_32
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [6]),
- .I1(\[1].[2].s_reqs_reg[6][value][11] [6]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11] [6]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [6]),
- .O(\axi_rdata[6]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[6]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][6] ),
- .I1(\data_rw_o[10] [6]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\s_datao_fmc1[0] [6]),
- .I4(\axi_rdata_reg[7]_1 ),
- .O(\axi_rdata[6]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_35
- (.I0(\[4].[3].s_reqs_reg[19][value][11] [6]),
- .I1(\[4].[2].s_reqs_reg[18][value][11] [6]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11] [6]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11] [6]),
- .O(\axi_rdata[6]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_36
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [6]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_0 [6]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_0 [6]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [6]),
- .O(\axi_rdata[6]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_37
- (.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [6]),
- .I1(\[2].[2].s_reqs_reg[10][value][11]_0 [6]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11]_0 [6]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11]_0 [6]),
- .O(\axi_rdata[6]_i_37_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_39
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [6]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_0 [6]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_0 [6]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [6]),
- .O(\axi_rdata[6]_i_39_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[6]_i_41
- (.I0(\data_rw_o_reg_n_0_[79][6] ),
- .I1(\data_rw_o[78] [6]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\s_datao_fmc2[0] [6]),
- .I4(\axi_rdata_reg[7]_1 ),
- .O(\axi_rdata[6]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_44
- (.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [6]),
- .I1(\[3].[2].s_reqs_reg[14][value][11]_0 [6]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11]_0 [6]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11]_0 [6]),
- .O(\axi_rdata[6]_i_44_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_45
- (.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [6]),
- .I1(\[4].[2].s_reqs_reg[18][value][11]_0 [6]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11]_0 [6]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11]_0 [6]),
- .O(\axi_rdata[6]_i_45_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_5
- (.I0(\axi_rdata_reg[6]_i_11_n_0 ),
- .I1(\axi_rdata_reg[6]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[6]_i_13_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata[6]_i_14_n_0 ),
- .O(\axi_rdata[6]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[6]_i_6
- (.I0(\axi_rdata_reg[10]_0 ),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][6] ),
- .I2(\axi_rdata_reg[9]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][6] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[6]_i_17_n_0 ),
- .O(\axi_rdata[6]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_7
- (.I0(\axi_rdata_reg[6]_i_18_n_0 ),
- .I1(\axi_rdata_reg[6]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[6]_i_20_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_araddr_reg[4]_rep__0_5 ),
- .O(\axi_rdata[6]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[6]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][6]_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[6]_i_23_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata_reg[6]_i_24_n_0 ),
- .O(\axi_rdata[6]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[7]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[7]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[7]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_rep_3 ),
- .O(\axi_rdata[7]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hCC408840))
- \axi_rdata[7]_i_14
- (.I0(\axi_rdata_reg[9]_0 ),
- .I1(\axi_rdata_reg[7]_0 ),
- .I2(gem_status_vector_i[7]),
- .I3(\axi_rdata_reg[7]_1 ),
- .I4(\data_rw_o_reg_n_0_[3][7] ),
- .O(\axi_rdata[7]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[7]_i_17
- (.I0(\axi_rdata[7]_i_35_n_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\dac_ch_o_reg[0][31]_0 [7]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\axi_rdata_reg[10]_0 ),
- .O(\axi_rdata[7]_i_17_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[7]_i_23
- (.I0(\axi_rdata_reg[7]_0 ),
- .I1(\dac_ch_o_reg[0][31] [7]),
- .I2(\axi_rdata_reg[7]_1 ),
- .I3(\axi_rdata_reg[9]_0 ),
- .O(\axi_rdata[7]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_29
- (.I0(\[2].[3].s_reqs_reg[11][value][11] [7]),
- .I1(\[2].[2].s_reqs_reg[10][value][11] [7]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11] [7]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11] [7]),
- .O(\axi_rdata[7]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_30
- (.I0(\[3].[3].s_reqs_reg[15][value][11] [7]),
- .I1(\[3].[2].s_reqs_reg[14][value][11] [7]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11] [7]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11] [7]),
- .O(\axi_rdata[7]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_31
- (.I0(Q[7]),
- .I1(\[0].[2].s_reqs_reg[2][value][11] [7]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11] [7]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [7]),
- .O(\axi_rdata[7]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_32
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [7]),
- .I1(\[1].[2].s_reqs_reg[6][value][11] [7]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11] [7]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [7]),
- .O(\axi_rdata[7]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[7]_i_33
- (.I0(\v_dout_reg[7] [2]),
- .I1(\data_rw_o[10] [7]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\s_datao_fmc1[0] [7]),
- .I4(\axi_rdata_reg[7]_1 ),
- .O(\axi_rdata[7]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_35
- (.I0(\[4].[3].s_reqs_reg[19][value][11] [7]),
- .I1(\[4].[2].s_reqs_reg[18][value][11] [7]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11] [7]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11] [7]),
- .O(\axi_rdata[7]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_36
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [7]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_0 [7]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_0 [7]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [7]),
- .O(\axi_rdata[7]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_37
- (.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [7]),
- .I1(\[2].[2].s_reqs_reg[10][value][11]_0 [7]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11]_0 [7]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11]_0 [7]),
- .O(\axi_rdata[7]_i_37_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_39
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [7]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_0 [7]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_0 [7]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [7]),
- .O(\axi_rdata[7]_i_39_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[7]_i_41
- (.I0(\v_dout_reg[7]_0 [2]),
- .I1(\data_rw_o[78] [7]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\s_datao_fmc2[0] [7]),
- .I4(\axi_rdata_reg[7]_1 ),
- .O(\axi_rdata[7]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_44
- (.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [7]),
- .I1(\[3].[2].s_reqs_reg[14][value][11]_0 [7]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11]_0 [7]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11]_0 [7]),
- .O(\axi_rdata[7]_i_44_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_45
- (.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [7]),
- .I1(\[4].[2].s_reqs_reg[18][value][11]_0 [7]),
- .I2(\axi_rdata_reg[7]_0 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11]_0 [7]),
- .I4(\axi_rdata_reg[7]_1 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11]_0 [7]),
- .O(\axi_rdata[7]_i_45_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_5
- (.I0(\axi_rdata_reg[7]_i_11_n_0 ),
- .I1(\axi_rdata_reg[7]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[7]_i_13_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata[7]_i_14_n_0 ),
- .O(\axi_rdata[7]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[7]_i_6
- (.I0(\axi_rdata_reg[10]_0 ),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][7] ),
- .I2(\axi_rdata_reg[9]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][7] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[7]_i_17_n_0 ),
- .O(\axi_rdata[7]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_7
- (.I0(\axi_rdata_reg[7]_i_18_n_0 ),
- .I1(\axi_rdata_reg[7]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[7]_i_20_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_araddr_reg[4]_rep__0_6 ),
- .O(\axi_rdata[7]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[7]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][7]_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[7]_i_23_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata_reg[7]_i_24_n_0 ),
- .O(\axi_rdata[7]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[8]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[8]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[8]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_rep_2 ),
- .O(\axi_rdata[8]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h04FF0400))
- \axi_rdata[8]_i_13
- (.I0(\axi_rdata_reg[12]_0 ),
- .I1(\s_datao_fmc1[4] [0]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\axi_rdata_reg[9]_0 ),
- .I4(\axi_rdata[8]_i_33_n_0 ),
- .O(\axi_rdata[8]_i_13_n_0 ));
- LUT5 #(
- .INIT(32'h0000B800))
- \axi_rdata[8]_i_14
- (.I0(\data_rw_o_reg_n_0_[3][8] ),
- .I1(\axi_rdata_reg[12]_0 ),
- .I2(gem_status_vector_i[8]),
- .I3(\axi_rdata_reg[12]_1 ),
- .I4(\axi_rdata_reg[9]_0 ),
- .O(\axi_rdata[8]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[8]_i_17
- (.I0(\axi_rdata[8]_i_34_n_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\dac_ch_o_reg[0][31]_0 [8]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\axi_rdata_reg[10]_0 ),
- .O(\axi_rdata[8]_i_17_n_0 ));
- LUT5 #(
- .INIT(32'h88888B88))
- \axi_rdata[8]_i_19
- (.I0(\axi_rdata[8]_i_37_n_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[12]_0 ),
- .I3(\s_datao_fmc2[4] [0]),
- .I4(\axi_rdata_reg[12]_1 ),
- .O(\axi_rdata[8]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[8]_i_23
- (.I0(\axi_rdata_reg[12]_1 ),
- .I1(\dac_ch_o_reg[0][31] [8]),
- .I2(\axi_rdata_reg[12]_0 ),
- .I3(\axi_rdata_reg[9]_0 ),
- .O(\axi_rdata[8]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_29
- (.I0(\[2].[3].s_reqs_reg[11][value][11] [8]),
- .I1(\[2].[2].s_reqs_reg[10][value][11] [8]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11] [8]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11] [8]),
- .O(\axi_rdata[8]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_30
- (.I0(\[3].[3].s_reqs_reg[15][value][11] [8]),
- .I1(\[3].[2].s_reqs_reg[14][value][11] [8]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11] [8]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11] [8]),
- .O(\axi_rdata[8]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_31
- (.I0(Q[8]),
- .I1(\[0].[2].s_reqs_reg[2][value][11] [8]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11] [8]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [8]),
- .O(\axi_rdata[8]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_32
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [8]),
- .I1(\[1].[2].s_reqs_reg[6][value][11] [8]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11] [8]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [8]),
- .O(\axi_rdata[8]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[8]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][8] ),
- .I1(\data_rw_o_reg_n_0_[10][8] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\s_datao_fmc1[0] [8]),
- .I4(\axi_rdata_reg[12]_0 ),
- .O(\axi_rdata[8]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_34
- (.I0(\[4].[3].s_reqs_reg[19][value][11] [8]),
- .I1(\[4].[2].s_reqs_reg[18][value][11] [8]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11] [8]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11] [8]),
- .O(\axi_rdata[8]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_35
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [8]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_0 [8]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_0 [8]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [8]),
- .O(\axi_rdata[8]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_36
- (.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [8]),
- .I1(\[2].[2].s_reqs_reg[10][value][11]_0 [8]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11]_0 [8]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11]_0 [8]),
- .O(\axi_rdata[8]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_37
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [8]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_0 [8]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_0 [8]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [8]),
- .O(\axi_rdata[8]_i_37_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[8]_i_39
- (.I0(\data_rw_o_reg_n_0_[79][8] ),
- .I1(\data_rw_o_reg_n_0_[78][8] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\s_datao_fmc2[0] [8]),
- .I4(\axi_rdata_reg[12]_0 ),
- .O(\axi_rdata[8]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_42
- (.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [8]),
- .I1(\[3].[2].s_reqs_reg[14][value][11]_0 [8]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11]_0 [8]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11]_0 [8]),
- .O(\axi_rdata[8]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_43
- (.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [8]),
- .I1(\[4].[2].s_reqs_reg[18][value][11]_0 [8]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11]_0 [8]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11]_0 [8]),
- .O(\axi_rdata[8]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_5
- (.I0(\axi_rdata_reg[8]_i_11_n_0 ),
- .I1(\axi_rdata_reg[8]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[8]_i_13_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata[8]_i_14_n_0 ),
- .O(\axi_rdata[8]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[8]_i_6
- (.I0(\axi_rdata_reg[10]_0 ),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][8] ),
- .I2(\axi_rdata_reg[9]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][8] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[8]_i_17_n_0 ),
- .O(\axi_rdata[8]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_7
- (.I0(\axi_rdata_reg[8]_i_18_n_0 ),
- .I1(\axi_rdata[8]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[8]_i_20_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_araddr_reg[4]_rep__0_7 ),
- .O(\axi_rdata[8]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[8]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][8]_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[8]_i_23_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata_reg[8]_i_24_n_0 ),
- .O(\axi_rdata[8]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAA8080000A808))
- \axi_rdata[9]_i_1
- (.I0(\axi_rdata[23]_i_2_n_0 ),
- .I1(\axi_rdata_reg[9]_i_2_n_0 ),
- .I2(axi_araddr[8]),
- .I3(\axi_rdata_reg[9]_i_3_n_0 ),
- .I4(axi_araddr[9]),
- .I5(\axi_araddr_reg[5]_rep_1 ),
- .O(\axi_rdata[9]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h04FF0400))
- \axi_rdata[9]_i_13
- (.I0(\axi_rdata_reg[12]_0 ),
- .I1(\s_datao_fmc1[4] [1]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\axi_rdata_reg[9]_0 ),
- .I4(\axi_rdata[9]_i_33_n_0 ),
- .O(\axi_rdata[9]_i_13_n_0 ));
- LUT5 #(
- .INIT(32'hCC408840))
- \axi_rdata[9]_i_14
- (.I0(\axi_rdata_reg[9]_0 ),
- .I1(\axi_rdata_reg[12]_1 ),
- .I2(gem_status_vector_i[9]),
- .I3(\axi_rdata_reg[12]_0 ),
- .I4(\data_rw_o_reg_n_0_[3][9] ),
- .O(\axi_rdata[9]_i_14_n_0 ));
- LUT6 #(
- .INIT(64'h0000000022222E22))
- \axi_rdata[9]_i_17
- (.I0(\axi_rdata[9]_i_34_n_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\dac_ch_o_reg[0][31]_0 [9]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\axi_rdata_reg[10]_0 ),
- .O(\axi_rdata[9]_i_17_n_0 ));
- LUT5 #(
- .INIT(32'h88888B88))
- \axi_rdata[9]_i_19
- (.I0(\axi_rdata[9]_i_37_n_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(\axi_rdata_reg[12]_0 ),
- .I3(\s_datao_fmc2[4] [1]),
- .I4(\axi_rdata_reg[12]_1 ),
- .O(\axi_rdata[9]_i_19_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT4 #(
- .INIT(16'h0004))
- \axi_rdata[9]_i_23
- (.I0(\axi_rdata_reg[12]_1 ),
- .I1(\dac_ch_o_reg[0][31] [9]),
- .I2(\axi_rdata_reg[12]_0 ),
- .I3(\axi_rdata_reg[9]_0 ),
- .O(\axi_rdata[9]_i_23_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_29
- (.I0(\[2].[3].s_reqs_reg[11][value][11] [9]),
- .I1(\[2].[2].s_reqs_reg[10][value][11] [9]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11] [9]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11] [9]),
- .O(\axi_rdata[9]_i_29_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_30
- (.I0(\[3].[3].s_reqs_reg[15][value][11] [9]),
- .I1(\[3].[2].s_reqs_reg[14][value][11] [9]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11] [9]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11] [9]),
- .O(\axi_rdata[9]_i_30_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_31
- (.I0(Q[9]),
- .I1(\[0].[2].s_reqs_reg[2][value][11] [9]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11] [9]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11] [9]),
- .O(\axi_rdata[9]_i_31_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_32
- (.I0(\[1].[3].s_reqs_reg[7][value][11] [9]),
- .I1(\[1].[2].s_reqs_reg[6][value][11] [9]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11] [9]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11] [9]),
- .O(\axi_rdata[9]_i_32_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[9]_i_33
- (.I0(\data_rw_o_reg_n_0_[11][9] ),
- .I1(\data_rw_o_reg_n_0_[10][9] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\s_datao_fmc1[0] [9]),
- .I4(\axi_rdata_reg[12]_0 ),
- .O(\axi_rdata[9]_i_33_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_34
- (.I0(\[4].[3].s_reqs_reg[19][value][11] [9]),
- .I1(\[4].[2].s_reqs_reg[18][value][11] [9]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11] [9]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11] [9]),
- .O(\axi_rdata[9]_i_34_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_35
- (.I0(\[1].[3].s_reqs_reg[7][value][11]_0 [9]),
- .I1(\[1].[2].s_reqs_reg[6][value][11]_0 [9]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[1].[1].s_reqs_reg[5][value][11]_0 [9]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[1].[0].s_reqs_reg[4][value][11]_0 [9]),
- .O(\axi_rdata[9]_i_35_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_36
- (.I0(\[2].[3].s_reqs_reg[11][value][11]_0 [9]),
- .I1(\[2].[2].s_reqs_reg[10][value][11]_0 [9]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[2].[1].s_reqs_reg[9][value][11]_0 [9]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[2].[0].s_reqs_reg[8][value][11]_0 [9]),
- .O(\axi_rdata[9]_i_36_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_37
- (.I0(\[0].[3].s_reqs_reg[3][value][11] [9]),
- .I1(\[0].[2].s_reqs_reg[2][value][11]_0 [9]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[0].[1].s_reqs_reg[1][value][11]_0 [9]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[0].[0].s_reqs_reg[0][value][11]_0 [9]),
- .O(\axi_rdata[9]_i_37_n_0 ));
- LUT5 #(
- .INIT(32'hA0A0CFC0))
- \axi_rdata[9]_i_39
- (.I0(\data_rw_o_reg_n_0_[79][9] ),
- .I1(\data_rw_o_reg_n_0_[78][9] ),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\s_datao_fmc2[0] [9]),
- .I4(\axi_rdata_reg[12]_0 ),
- .O(\axi_rdata[9]_i_39_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_42
- (.I0(\[3].[3].s_reqs_reg[15][value][11]_0 [9]),
- .I1(\[3].[2].s_reqs_reg[14][value][11]_0 [9]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[3].[1].s_reqs_reg[13][value][11]_0 [9]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[3].[0].s_reqs_reg[12][value][11]_0 [9]),
- .O(\axi_rdata[9]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_43
- (.I0(\[4].[3].s_reqs_reg[19][value][11]_0 [9]),
- .I1(\[4].[2].s_reqs_reg[18][value][11]_0 [9]),
- .I2(\axi_rdata_reg[12]_1 ),
- .I3(\[4].[1].s_reqs_reg[17][value][11]_0 [9]),
- .I4(\axi_rdata_reg[12]_0 ),
- .I5(\[4].[0].s_reqs_reg[16][value][11]_0 [9]),
- .O(\axi_rdata[9]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_5
- (.I0(\axi_rdata_reg[9]_i_11_n_0 ),
- .I1(\axi_rdata_reg[9]_i_12_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[9]_i_13_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata[9]_i_14_n_0 ),
- .O(\axi_rdata[9]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hA808FFFFA8080000))
- \axi_rdata[9]_i_6
- (.I0(\axi_rdata_reg[10]_0 ),
- .I1(\fmc_03287_channels[3].gen_chs.data_o_reg[51][9] ),
- .I2(\axi_rdata_reg[9]_0 ),
- .I3(\fmc_03287_channels[7].gen_chs.data_o_reg[55][9] ),
- .I4(axi_araddr[6]),
- .I5(\axi_rdata[9]_i_17_n_0 ),
- .O(\axi_rdata[9]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_7
- (.I0(\axi_rdata_reg[9]_i_18_n_0 ),
- .I1(\axi_rdata[9]_i_19_n_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata_reg[9]_i_20_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_araddr_reg[4]_rep__0_8 ),
- .O(\axi_rdata[9]_i_7_n_0 ));
- LUT6 #(
- .INIT(64'h8F800F0F8F800000))
- \axi_rdata[9]_i_8
- (.I0(\fmc_03287_channels[3].gen_chs.data_o_reg[51][9]_0 ),
- .I1(\axi_rdata_reg[9]_0 ),
- .I2(axi_araddr[6]),
- .I3(\axi_rdata[9]_i_23_n_0 ),
- .I4(\axi_rdata_reg[10]_0 ),
- .I5(\axi_rdata_reg[9]_i_24_n_0 ),
- .O(\axi_rdata[9]_i_8_n_0 ));
- FDRE \axi_rdata_reg[0]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[0]_i_1_n_0 ),
- .Q(s00_axi_rdata[0]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[0]_i_11
- (.I0(\axi_rdata[0]_i_29_n_0 ),
- .I1(\axi_rdata[0]_i_30_n_0 ),
- .O(\axi_rdata_reg[0]_i_11_n_0 ),
- .S(\axi_rdata_reg[0]_0 ));
- MUXF7 \axi_rdata_reg[0]_i_12
- (.I0(\axi_rdata[0]_i_31_n_0 ),
- .I1(\axi_rdata[0]_i_32_n_0 ),
- .O(\axi_rdata_reg[0]_i_12_n_0 ),
- .S(\axi_rdata_reg[0]_0 ));
- MUXF7 \axi_rdata_reg[0]_i_13
- (.I0(\axi_rdata[0]_i_33_n_0 ),
- .I1(\data_o_reg[6][0] ),
- .O(\axi_rdata_reg[0]_i_13_n_0 ),
- .S(\axi_rdata_reg[0]_0 ));
- MUXF7 \axi_rdata_reg[0]_i_18
- (.I0(\axi_rdata[0]_i_36_n_0 ),
- .I1(\axi_rdata[0]_i_37_n_0 ),
- .O(\axi_rdata_reg[0]_i_18_n_0 ),
- .S(\axi_rdata_reg[0]_0 ));
- MUXF7 \axi_rdata_reg[0]_i_19
- (.I0(\data_o_reg[6][0]_0 ),
- .I1(\axi_rdata[0]_i_39_n_0 ),
- .O(\axi_rdata_reg[0]_i_19_n_0 ),
- .S(\axi_rdata_reg[0]_0 ));
- MUXF7 \axi_rdata_reg[0]_i_2
- (.I0(\axi_rdata[0]_i_5_n_0 ),
- .I1(\axi_rdata[0]_i_6_n_0 ),
- .O(\axi_rdata_reg[0]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[0]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][0] ),
- .I1(\axi_rdata[0]_i_41_n_0 ),
- .O(\axi_rdata_reg[0]_i_20_n_0 ),
- .S(\axi_rdata_reg[0]_0 ));
- MUXF7 \axi_rdata_reg[0]_i_24
- (.I0(\axi_rdata[0]_i_44_n_0 ),
- .I1(\axi_rdata[0]_i_45_n_0 ),
- .O(\axi_rdata_reg[0]_i_24_n_0 ),
- .S(\axi_rdata_reg[0]_0 ));
- MUXF7 \axi_rdata_reg[0]_i_3
- (.I0(\axi_rdata[0]_i_7_n_0 ),
- .I1(\axi_rdata[0]_i_8_n_0 ),
- .O(\axi_rdata_reg[0]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[10]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[10]_i_1_n_0 ),
- .Q(s00_axi_rdata[10]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[10]_i_11
- (.I0(\axi_rdata[10]_i_29_n_0 ),
- .I1(\axi_rdata[10]_i_30_n_0 ),
- .O(\axi_rdata_reg[10]_i_11_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[10]_i_12
- (.I0(\axi_rdata[10]_i_31_n_0 ),
- .I1(\axi_rdata[10]_i_32_n_0 ),
- .O(\axi_rdata_reg[10]_i_12_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[10]_i_18
- (.I0(\axi_rdata[10]_i_35_n_0 ),
- .I1(\axi_rdata[10]_i_36_n_0 ),
- .O(\axi_rdata_reg[10]_i_18_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[10]_i_2
- (.I0(\axi_rdata[10]_i_5_n_0 ),
- .I1(\axi_rdata[10]_i_6_n_0 ),
- .O(\axi_rdata_reg[10]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[10]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][10] ),
- .I1(\axi_rdata[10]_i_39_n_0 ),
- .O(\axi_rdata_reg[10]_i_20_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[10]_i_24
- (.I0(\axi_rdata[10]_i_42_n_0 ),
- .I1(\axi_rdata[10]_i_43_n_0 ),
- .O(\axi_rdata_reg[10]_i_24_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[10]_i_3
- (.I0(\axi_rdata[10]_i_7_n_0 ),
- .I1(\axi_rdata[10]_i_8_n_0 ),
- .O(\axi_rdata_reg[10]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[11]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[11]_i_1_n_0 ),
- .Q(s00_axi_rdata[11]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[11]_i_11
- (.I0(\axi_rdata[11]_i_29_n_0 ),
- .I1(\axi_rdata[11]_i_30_n_0 ),
- .O(\axi_rdata_reg[11]_i_11_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[11]_i_12
- (.I0(\axi_rdata[11]_i_31_n_0 ),
- .I1(\axi_rdata[11]_i_32_n_0 ),
- .O(\axi_rdata_reg[11]_i_12_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[11]_i_18
- (.I0(\axi_rdata[11]_i_35_n_0 ),
- .I1(\axi_rdata[11]_i_36_n_0 ),
- .O(\axi_rdata_reg[11]_i_18_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[11]_i_2
- (.I0(\axi_rdata[11]_i_5_n_0 ),
- .I1(\axi_rdata[11]_i_6_n_0 ),
- .O(\axi_rdata_reg[11]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[11]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][11] ),
- .I1(\axi_rdata[11]_i_39_n_0 ),
- .O(\axi_rdata_reg[11]_i_20_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[11]_i_24
- (.I0(\axi_rdata[11]_i_42_n_0 ),
- .I1(\axi_rdata[11]_i_43_n_0 ),
- .O(\axi_rdata_reg[11]_i_24_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[11]_i_3
- (.I0(\axi_rdata[11]_i_7_n_0 ),
- .I1(\axi_rdata[11]_i_8_n_0 ),
- .O(\axi_rdata_reg[11]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[12]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[12]_i_1_n_0 ),
- .Q(s00_axi_rdata[12]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[12]_i_11
- (.I0(\axi_rdata[12]_i_29_n_0 ),
- .I1(\axi_rdata[12]_i_30_n_0 ),
- .O(\axi_rdata_reg[12]_i_11_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[12]_i_12
- (.I0(\axi_rdata[12]_i_31_n_0 ),
- .I1(\axi_rdata[12]_i_32_n_0 ),
- .O(\axi_rdata_reg[12]_i_12_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[12]_i_18
- (.I0(\axi_rdata[12]_i_35_n_0 ),
- .I1(\axi_rdata[12]_i_36_n_0 ),
- .O(\axi_rdata_reg[12]_i_18_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[12]_i_2
- (.I0(\axi_rdata[12]_i_5_n_0 ),
- .I1(\axi_rdata[12]_i_6_n_0 ),
- .O(\axi_rdata_reg[12]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[12]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][12] ),
- .I1(\axi_rdata[12]_i_39_n_0 ),
- .O(\axi_rdata_reg[12]_i_20_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[12]_i_24
- (.I0(\axi_rdata[12]_i_42_n_0 ),
- .I1(\axi_rdata[12]_i_43_n_0 ),
- .O(\axi_rdata_reg[12]_i_24_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[12]_i_3
- (.I0(\axi_rdata[12]_i_7_n_0 ),
- .I1(\axi_rdata[12]_i_8_n_0 ),
- .O(\axi_rdata_reg[12]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[13]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[13]_i_1_n_0 ),
- .Q(s00_axi_rdata[13]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[13]_i_11
- (.I0(\axi_rdata[13]_i_29_n_0 ),
- .I1(\axi_rdata[13]_i_30_n_0 ),
- .O(\axi_rdata_reg[13]_i_11_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[13]_i_12
- (.I0(\axi_rdata[13]_i_31_n_0 ),
- .I1(\axi_rdata[13]_i_32_n_0 ),
- .O(\axi_rdata_reg[13]_i_12_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[13]_i_18
- (.I0(\axi_rdata[13]_i_35_n_0 ),
- .I1(\axi_rdata[13]_i_36_n_0 ),
- .O(\axi_rdata_reg[13]_i_18_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[13]_i_2
- (.I0(\axi_rdata[13]_i_5_n_0 ),
- .I1(\axi_rdata[13]_i_6_n_0 ),
- .O(\axi_rdata_reg[13]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[13]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][13] ),
- .I1(\axi_rdata[13]_i_39_n_0 ),
- .O(\axi_rdata_reg[13]_i_20_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[13]_i_24
- (.I0(\axi_rdata[13]_i_42_n_0 ),
- .I1(\axi_rdata[13]_i_43_n_0 ),
- .O(\axi_rdata_reg[13]_i_24_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[13]_i_3
- (.I0(\axi_rdata[13]_i_7_n_0 ),
- .I1(\axi_rdata[13]_i_8_n_0 ),
- .O(\axi_rdata_reg[13]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[14]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[14]_i_1_n_0 ),
- .Q(s00_axi_rdata[14]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[14]_i_11
- (.I0(\axi_rdata[14]_i_29_n_0 ),
- .I1(\axi_rdata[14]_i_30_n_0 ),
- .O(\axi_rdata_reg[14]_i_11_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[14]_i_12
- (.I0(\axi_rdata[14]_i_31_n_0 ),
- .I1(\axi_rdata[14]_i_32_n_0 ),
- .O(\axi_rdata_reg[14]_i_12_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[14]_i_18
- (.I0(\axi_rdata[14]_i_35_n_0 ),
- .I1(\axi_rdata[14]_i_36_n_0 ),
- .O(\axi_rdata_reg[14]_i_18_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[14]_i_2
- (.I0(\axi_rdata[14]_i_5_n_0 ),
- .I1(\axi_rdata[14]_i_6_n_0 ),
- .O(\axi_rdata_reg[14]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[14]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][14] ),
- .I1(\axi_rdata[14]_i_39_n_0 ),
- .O(\axi_rdata_reg[14]_i_20_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[14]_i_24
- (.I0(\axi_rdata[14]_i_42_n_0 ),
- .I1(\axi_rdata[14]_i_43_n_0 ),
- .O(\axi_rdata_reg[14]_i_24_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[14]_i_3
- (.I0(\axi_rdata[14]_i_7_n_0 ),
- .I1(\axi_rdata[14]_i_8_n_0 ),
- .O(\axi_rdata_reg[14]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[15]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[15]_i_1_n_0 ),
- .Q(s00_axi_rdata[15]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[15]_i_11
- (.I0(\axi_rdata[15]_i_29_n_0 ),
- .I1(\axi_rdata[15]_i_30_n_0 ),
- .O(\axi_rdata_reg[15]_i_11_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[15]_i_12
- (.I0(\axi_rdata[15]_i_31_n_0 ),
- .I1(\axi_rdata[15]_i_32_n_0 ),
- .O(\axi_rdata_reg[15]_i_12_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[15]_i_18
- (.I0(\axi_rdata[15]_i_35_n_0 ),
- .I1(\axi_rdata[15]_i_36_n_0 ),
- .O(\axi_rdata_reg[15]_i_18_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[15]_i_2
- (.I0(\axi_rdata[15]_i_5_n_0 ),
- .I1(\axi_rdata[15]_i_6_n_0 ),
- .O(\axi_rdata_reg[15]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[15]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][15] ),
- .I1(\axi_rdata[15]_i_39_n_0 ),
- .O(\axi_rdata_reg[15]_i_20_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[15]_i_24
- (.I0(\axi_rdata[15]_i_42_n_0 ),
- .I1(\axi_rdata[15]_i_43_n_0 ),
- .O(\axi_rdata_reg[15]_i_24_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[15]_i_3
- (.I0(\axi_rdata[15]_i_7_n_0 ),
- .I1(\axi_rdata[15]_i_8_n_0 ),
- .O(\axi_rdata_reg[15]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[16]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[16]_i_1_n_0 ),
- .Q(s00_axi_rdata[16]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[16]_i_11
- (.I0(\axi_rdata[16]_i_29_n_0 ),
- .I1(\axi_rdata[16]_i_30_n_0 ),
- .O(\axi_rdata_reg[16]_i_11_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[16]_i_12
- (.I0(\axi_rdata[16]_i_31_n_0 ),
- .I1(\axi_rdata[16]_i_32_n_0 ),
- .O(\axi_rdata_reg[16]_i_12_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[16]_i_18
- (.I0(\axi_rdata[16]_i_35_n_0 ),
- .I1(\axi_rdata[16]_i_36_n_0 ),
- .O(\axi_rdata_reg[16]_i_18_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[16]_i_2
- (.I0(\axi_rdata[16]_i_5_n_0 ),
- .I1(\axi_rdata[16]_i_6_n_0 ),
- .O(\axi_rdata_reg[16]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[16]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][16] ),
- .I1(\axi_rdata[16]_i_39_n_0 ),
- .O(\axi_rdata_reg[16]_i_20_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[16]_i_24
- (.I0(\axi_rdata[16]_i_42_n_0 ),
- .I1(\axi_rdata[16]_i_43_n_0 ),
- .O(\axi_rdata_reg[16]_i_24_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[16]_i_3
- (.I0(\axi_rdata[16]_i_7_n_0 ),
- .I1(\axi_rdata[16]_i_8_n_0 ),
- .O(\axi_rdata_reg[16]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[17]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[17]_i_1_n_0 ),
- .Q(s00_axi_rdata[17]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[17]_i_11
- (.I0(\axi_rdata[17]_i_29_n_0 ),
- .I1(\axi_rdata[17]_i_30_n_0 ),
- .O(\axi_rdata_reg[17]_i_11_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[17]_i_12
- (.I0(\axi_rdata[17]_i_31_n_0 ),
- .I1(\axi_rdata[17]_i_32_n_0 ),
- .O(\axi_rdata_reg[17]_i_12_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[17]_i_18
- (.I0(\axi_rdata[17]_i_35_n_0 ),
- .I1(\axi_rdata[17]_i_36_n_0 ),
- .O(\axi_rdata_reg[17]_i_18_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[17]_i_2
- (.I0(\axi_rdata[17]_i_5_n_0 ),
- .I1(\axi_rdata[17]_i_6_n_0 ),
- .O(\axi_rdata_reg[17]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[17]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][17] ),
- .I1(\axi_rdata[17]_i_39_n_0 ),
- .O(\axi_rdata_reg[17]_i_20_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[17]_i_24
- (.I0(\axi_rdata[17]_i_42_n_0 ),
- .I1(\axi_rdata[17]_i_43_n_0 ),
- .O(\axi_rdata_reg[17]_i_24_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[17]_i_3
- (.I0(\axi_rdata[17]_i_7_n_0 ),
- .I1(\axi_rdata[17]_i_8_n_0 ),
- .O(\axi_rdata_reg[17]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[18]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[18]_i_1_n_0 ),
- .Q(s00_axi_rdata[18]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[18]_i_11
- (.I0(\axi_rdata[18]_i_29_n_0 ),
- .I1(\axi_rdata[18]_i_30_n_0 ),
- .O(\axi_rdata_reg[18]_i_11_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[18]_i_12
- (.I0(\axi_rdata[18]_i_31_n_0 ),
- .I1(\axi_rdata[18]_i_32_n_0 ),
- .O(\axi_rdata_reg[18]_i_12_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[18]_i_18
- (.I0(\axi_rdata[18]_i_35_n_0 ),
- .I1(\axi_rdata[18]_i_36_n_0 ),
- .O(\axi_rdata_reg[18]_i_18_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[18]_i_2
- (.I0(\axi_rdata[18]_i_5_n_0 ),
- .I1(\axi_rdata[18]_i_6_n_0 ),
- .O(\axi_rdata_reg[18]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[18]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][18] ),
- .I1(\axi_rdata[18]_i_39_n_0 ),
- .O(\axi_rdata_reg[18]_i_20_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[18]_i_24
- (.I0(\axi_rdata[18]_i_42_n_0 ),
- .I1(\axi_rdata[18]_i_43_n_0 ),
- .O(\axi_rdata_reg[18]_i_24_n_0 ),
- .S(\axi_rdata_reg[18]_0 ));
- MUXF7 \axi_rdata_reg[18]_i_3
- (.I0(\axi_rdata[18]_i_7_n_0 ),
- .I1(\axi_rdata[18]_i_8_n_0 ),
- .O(\axi_rdata_reg[18]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[19]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[19]_i_1_n_0 ),
- .Q(s00_axi_rdata[19]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[19]_i_11
- (.I0(\axi_rdata[19]_i_29_n_0 ),
- .I1(\axi_rdata[19]_i_30_n_0 ),
- .O(\axi_rdata_reg[19]_i_11_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[19]_i_12
- (.I0(\axi_rdata[19]_i_31_n_0 ),
- .I1(\axi_rdata[19]_i_32_n_0 ),
- .O(\axi_rdata_reg[19]_i_12_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[19]_i_18
- (.I0(\axi_rdata[19]_i_35_n_0 ),
- .I1(\axi_rdata[19]_i_36_n_0 ),
- .O(\axi_rdata_reg[19]_i_18_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[19]_i_2
- (.I0(\axi_rdata[19]_i_5_n_0 ),
- .I1(\axi_rdata[19]_i_6_n_0 ),
- .O(\axi_rdata_reg[19]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[19]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][19] ),
- .I1(\axi_rdata[19]_i_39_n_0 ),
- .O(\axi_rdata_reg[19]_i_20_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[19]_i_24
- (.I0(\axi_rdata[19]_i_42_n_0 ),
- .I1(\axi_rdata[19]_i_43_n_0 ),
- .O(\axi_rdata_reg[19]_i_24_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[19]_i_3
- (.I0(\axi_rdata[19]_i_7_n_0 ),
- .I1(\axi_rdata[19]_i_8_n_0 ),
- .O(\axi_rdata_reg[19]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[1]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[1]_i_1_n_0 ),
- .Q(s00_axi_rdata[1]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[1]_i_11
- (.I0(\axi_rdata[1]_i_29_n_0 ),
- .I1(\axi_rdata[1]_i_30_n_0 ),
- .O(\axi_rdata_reg[1]_i_11_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[1]_i_12
- (.I0(\axi_rdata[1]_i_31_n_0 ),
- .I1(\axi_rdata[1]_i_32_n_0 ),
- .O(\axi_rdata_reg[1]_i_12_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[1]_i_13
- (.I0(\axi_rdata[1]_i_33_n_0 ),
- .I1(\data_o_reg[6][1] ),
- .O(\axi_rdata_reg[1]_i_13_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[1]_i_18
- (.I0(\axi_rdata[1]_i_36_n_0 ),
- .I1(\axi_rdata[1]_i_37_n_0 ),
- .O(\axi_rdata_reg[1]_i_18_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[1]_i_19
- (.I0(\data_o_reg[6][1]_0 ),
- .I1(\axi_rdata[1]_i_39_n_0 ),
- .O(\axi_rdata_reg[1]_i_19_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[1]_i_2
- (.I0(\axi_rdata[1]_i_5_n_0 ),
- .I1(\axi_rdata[1]_i_6_n_0 ),
- .O(\axi_rdata_reg[1]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[1]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][1] ),
- .I1(\axi_rdata[1]_i_41_n_0 ),
- .O(\axi_rdata_reg[1]_i_20_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[1]_i_24
- (.I0(\axi_rdata[1]_i_44_n_0 ),
- .I1(\axi_rdata[1]_i_45_n_0 ),
- .O(\axi_rdata_reg[1]_i_24_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[1]_i_3
- (.I0(\axi_rdata[1]_i_7_n_0 ),
- .I1(\axi_rdata[1]_i_8_n_0 ),
- .O(\axi_rdata_reg[1]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[20]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[20]_i_1_n_0 ),
- .Q(s00_axi_rdata[20]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[20]_i_15
- (.I0(\axi_rdata[20]_i_25_n_0 ),
- .I1(\axi_rdata[20]_i_26_n_0 ),
- .O(\axi_rdata_reg[20]_i_15_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[20]_i_21
- (.I0(\axi_rdata[20]_i_35_n_0 ),
- .I1(\axi_rdata[20]_i_36_n_0 ),
- .O(\axi_rdata_reg[20]_i_21_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[20]_i_22
- (.I0(\axi_rdata[20]_i_37_n_0 ),
- .I1(\axi_rdata[20]_i_38_n_0 ),
- .O(\axi_rdata_reg[20]_i_22_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[20]_i_6
- (.I0(\axi_rdata[20]_i_16_n_0 ),
- .I1(\axi_rdata[20]_i_17_n_0 ),
- .O(\axi_rdata_reg[20]_i_6_n_0 ),
- .S(axi_araddr[6]));
- FDRE \axi_rdata_reg[21]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[21]_i_1_n_0 ),
- .Q(s00_axi_rdata[21]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[21]_i_15
- (.I0(\axi_rdata[21]_i_25_n_0 ),
- .I1(\axi_rdata[21]_i_26_n_0 ),
- .O(\axi_rdata_reg[21]_i_15_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[21]_i_21
- (.I0(\axi_rdata[21]_i_35_n_0 ),
- .I1(\axi_rdata[21]_i_36_n_0 ),
- .O(\axi_rdata_reg[21]_i_21_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[21]_i_22
- (.I0(\axi_rdata[21]_i_37_n_0 ),
- .I1(\axi_rdata[21]_i_38_n_0 ),
- .O(\axi_rdata_reg[21]_i_22_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[21]_i_6
- (.I0(\axi_rdata[21]_i_16_n_0 ),
- .I1(\axi_rdata[21]_i_17_n_0 ),
- .O(\axi_rdata_reg[21]_i_6_n_0 ),
- .S(axi_araddr[6]));
- FDRE \axi_rdata_reg[22]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[22]_i_1_n_0 ),
- .Q(s00_axi_rdata[22]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[22]_i_15
- (.I0(\axi_rdata[22]_i_25_n_0 ),
- .I1(\axi_rdata[22]_i_26_n_0 ),
- .O(\axi_rdata_reg[22]_i_15_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[22]_i_21
- (.I0(\axi_rdata[22]_i_35_n_0 ),
- .I1(\axi_rdata[22]_i_36_n_0 ),
- .O(\axi_rdata_reg[22]_i_21_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[22]_i_22
- (.I0(\axi_rdata[22]_i_37_n_0 ),
- .I1(\axi_rdata[22]_i_38_n_0 ),
- .O(\axi_rdata_reg[22]_i_22_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[22]_i_6
- (.I0(\axi_rdata[22]_i_16_n_0 ),
- .I1(\axi_rdata[22]_i_17_n_0 ),
- .O(\axi_rdata_reg[22]_i_6_n_0 ),
- .S(axi_araddr[6]));
- FDRE \axi_rdata_reg[23]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[23]_i_1_n_0 ),
- .Q(s00_axi_rdata[23]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[23]_i_16
- (.I0(\axi_rdata[23]_i_26_n_0 ),
- .I1(\axi_rdata[23]_i_27_n_0 ),
- .O(\axi_rdata_reg[23]_i_16_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[23]_i_22
- (.I0(\axi_rdata[23]_i_36_n_0 ),
- .I1(\axi_rdata[23]_i_37_n_0 ),
- .O(\axi_rdata_reg[23]_i_22_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[23]_i_23
- (.I0(\axi_rdata[23]_i_38_n_0 ),
- .I1(\axi_rdata[23]_i_39_n_0 ),
- .O(\axi_rdata_reg[23]_i_23_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[23]_i_7
- (.I0(\axi_rdata[23]_i_17_n_0 ),
- .I1(\axi_rdata[23]_i_18_n_0 ),
- .O(\axi_rdata_reg[23]_i_7_n_0 ),
- .S(axi_araddr[6]));
- FDRE \axi_rdata_reg[24]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[24]_i_1_n_0 ),
- .Q(s00_axi_rdata[24]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[24]_i_10
- (.I0(\axi_rdata[24]_i_18_n_0 ),
- .I1(\axi_rdata[24]_i_19_n_0 ),
- .O(\axi_rdata_reg[24]_i_10_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[24]_i_15
- (.I0(\axi_rdata[24]_i_20_n_0 ),
- .I1(\axi_rdata[24]_i_21_n_0 ),
- .O(\axi_rdata_reg[24]_i_15_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[24]_i_16
- (.I0(\axi_rdata[24]_i_22_n_0 ),
- .I1(\axi_rdata[24]_i_23_n_0 ),
- .O(\axi_rdata_reg[24]_i_16_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF8 \axi_rdata_reg[24]_i_8
- (.I0(\axi_rdata_reg[24]_i_15_n_0 ),
- .I1(\axi_rdata_reg[24]_i_16_n_0 ),
- .O(\axi_rdata_reg[24]_i_8_n_0 ),
- .S(\axi_rdata_reg[23]_0 [3]));
- FDRE \axi_rdata_reg[25]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[25]_i_1_n_0 ),
- .Q(s00_axi_rdata[25]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[25]_i_10
- (.I0(\axi_rdata[25]_i_18_n_0 ),
- .I1(\axi_rdata[25]_i_19_n_0 ),
- .O(\axi_rdata_reg[25]_i_10_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[25]_i_15
- (.I0(\axi_rdata[25]_i_20_n_0 ),
- .I1(\axi_rdata[25]_i_21_n_0 ),
- .O(\axi_rdata_reg[25]_i_15_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[25]_i_16
- (.I0(\axi_rdata[25]_i_22_n_0 ),
- .I1(\axi_rdata[25]_i_23_n_0 ),
- .O(\axi_rdata_reg[25]_i_16_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF8 \axi_rdata_reg[25]_i_8
- (.I0(\axi_rdata_reg[25]_i_15_n_0 ),
- .I1(\axi_rdata_reg[25]_i_16_n_0 ),
- .O(\axi_rdata_reg[25]_i_8_n_0 ),
- .S(\axi_rdata_reg[23]_0 [3]));
- FDRE \axi_rdata_reg[26]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[26]_i_1_n_0 ),
- .Q(s00_axi_rdata[26]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[26]_i_10
- (.I0(\axi_rdata[26]_i_18_n_0 ),
- .I1(\axi_rdata[26]_i_19_n_0 ),
- .O(\axi_rdata_reg[26]_i_10_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[26]_i_15
- (.I0(\axi_rdata[26]_i_20_n_0 ),
- .I1(\axi_rdata[26]_i_21_n_0 ),
- .O(\axi_rdata_reg[26]_i_15_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[26]_i_16
- (.I0(\axi_rdata[26]_i_22_n_0 ),
- .I1(\axi_rdata[26]_i_23_n_0 ),
- .O(\axi_rdata_reg[26]_i_16_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF8 \axi_rdata_reg[26]_i_8
- (.I0(\axi_rdata_reg[26]_i_15_n_0 ),
- .I1(\axi_rdata_reg[26]_i_16_n_0 ),
- .O(\axi_rdata_reg[26]_i_8_n_0 ),
- .S(\axi_rdata_reg[23]_0 [3]));
- FDRE \axi_rdata_reg[27]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[27]_i_1_n_0 ),
- .Q(s00_axi_rdata[27]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[27]_i_10
- (.I0(\axi_rdata[27]_i_18_n_0 ),
- .I1(\axi_rdata[27]_i_19_n_0 ),
- .O(\axi_rdata_reg[27]_i_10_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[27]_i_15
- (.I0(\axi_rdata[27]_i_20_n_0 ),
- .I1(\axi_rdata[27]_i_21_n_0 ),
- .O(\axi_rdata_reg[27]_i_15_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[27]_i_16
- (.I0(\axi_rdata[27]_i_22_n_0 ),
- .I1(\axi_rdata[27]_i_23_n_0 ),
- .O(\axi_rdata_reg[27]_i_16_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF8 \axi_rdata_reg[27]_i_8
- (.I0(\axi_rdata_reg[27]_i_15_n_0 ),
- .I1(\axi_rdata_reg[27]_i_16_n_0 ),
- .O(\axi_rdata_reg[27]_i_8_n_0 ),
- .S(\axi_rdata_reg[23]_0 [3]));
- FDRE \axi_rdata_reg[28]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[28]_i_1_n_0 ),
- .Q(s00_axi_rdata[28]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[28]_i_10
- (.I0(\axi_rdata[28]_i_18_n_0 ),
- .I1(\axi_rdata[28]_i_19_n_0 ),
- .O(\axi_rdata_reg[28]_i_10_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[28]_i_15
- (.I0(\axi_rdata[28]_i_20_n_0 ),
- .I1(\axi_rdata[28]_i_21_n_0 ),
- .O(\axi_rdata_reg[28]_i_15_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[28]_i_16
- (.I0(\axi_rdata[28]_i_22_n_0 ),
- .I1(\axi_rdata[28]_i_23_n_0 ),
- .O(\axi_rdata_reg[28]_i_16_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF8 \axi_rdata_reg[28]_i_8
- (.I0(\axi_rdata_reg[28]_i_15_n_0 ),
- .I1(\axi_rdata_reg[28]_i_16_n_0 ),
- .O(\axi_rdata_reg[28]_i_8_n_0 ),
- .S(\axi_rdata_reg[23]_0 [3]));
- FDRE \axi_rdata_reg[29]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[29]_i_1_n_0 ),
- .Q(s00_axi_rdata[29]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[29]_i_10
- (.I0(\axi_rdata[29]_i_18_n_0 ),
- .I1(\axi_rdata[29]_i_19_n_0 ),
- .O(\axi_rdata_reg[29]_i_10_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[29]_i_15
- (.I0(\axi_rdata[29]_i_20_n_0 ),
- .I1(\axi_rdata[29]_i_21_n_0 ),
- .O(\axi_rdata_reg[29]_i_15_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[29]_i_16
- (.I0(\axi_rdata[29]_i_22_n_0 ),
- .I1(\axi_rdata[29]_i_23_n_0 ),
- .O(\axi_rdata_reg[29]_i_16_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF8 \axi_rdata_reg[29]_i_8
- (.I0(\axi_rdata_reg[29]_i_15_n_0 ),
- .I1(\axi_rdata_reg[29]_i_16_n_0 ),
- .O(\axi_rdata_reg[29]_i_8_n_0 ),
- .S(\axi_rdata_reg[23]_0 [3]));
- FDRE \axi_rdata_reg[2]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[2]_i_1_n_0 ),
- .Q(s00_axi_rdata[2]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[2]_i_11
- (.I0(\axi_rdata[2]_i_29_n_0 ),
- .I1(\axi_rdata[2]_i_30_n_0 ),
- .O(\axi_rdata_reg[2]_i_11_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[2]_i_12
- (.I0(\axi_rdata[2]_i_31_n_0 ),
- .I1(\axi_rdata[2]_i_32_n_0 ),
- .O(\axi_rdata_reg[2]_i_12_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[2]_i_13
- (.I0(\axi_rdata[2]_i_33_n_0 ),
- .I1(\data_o_reg[6][2] ),
- .O(\axi_rdata_reg[2]_i_13_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[2]_i_18
- (.I0(\axi_rdata[2]_i_36_n_0 ),
- .I1(\axi_rdata[2]_i_37_n_0 ),
- .O(\axi_rdata_reg[2]_i_18_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[2]_i_19
- (.I0(\data_o_reg[6][2]_0 ),
- .I1(\axi_rdata[2]_i_39_n_0 ),
- .O(\axi_rdata_reg[2]_i_19_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[2]_i_2
- (.I0(\axi_rdata[2]_i_5_n_0 ),
- .I1(\axi_rdata[2]_i_6_n_0 ),
- .O(\axi_rdata_reg[2]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[2]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][2] ),
- .I1(\axi_rdata[2]_i_41_n_0 ),
- .O(\axi_rdata_reg[2]_i_20_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[2]_i_24
- (.I0(\axi_rdata[2]_i_44_n_0 ),
- .I1(\axi_rdata[2]_i_45_n_0 ),
- .O(\axi_rdata_reg[2]_i_24_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[2]_i_3
- (.I0(\axi_rdata[2]_i_7_n_0 ),
- .I1(\axi_rdata[2]_i_8_n_0 ),
- .O(\axi_rdata_reg[2]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[30]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[30]_i_1_n_0 ),
- .Q(s00_axi_rdata[30]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[30]_i_10
- (.I0(\axi_rdata[30]_i_18_n_0 ),
- .I1(\axi_rdata[30]_i_19_n_0 ),
- .O(\axi_rdata_reg[30]_i_10_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[30]_i_15
- (.I0(\axi_rdata[30]_i_20_n_0 ),
- .I1(\axi_rdata[30]_i_21_n_0 ),
- .O(\axi_rdata_reg[30]_i_15_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[30]_i_16
- (.I0(\axi_rdata[30]_i_22_n_0 ),
- .I1(\axi_rdata[30]_i_23_n_0 ),
- .O(\axi_rdata_reg[30]_i_16_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF8 \axi_rdata_reg[30]_i_8
- (.I0(\axi_rdata_reg[30]_i_15_n_0 ),
- .I1(\axi_rdata_reg[30]_i_16_n_0 ),
- .O(\axi_rdata_reg[30]_i_8_n_0 ),
- .S(\axi_rdata_reg[23]_0 [3]));
- FDRE \axi_rdata_reg[31]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[31]_i_2_n_0 ),
- .Q(s00_axi_rdata[31]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[31]_i_11
- (.I0(\axi_rdata[31]_i_19_n_0 ),
- .I1(\axi_rdata[31]_i_20_n_0 ),
- .O(\axi_rdata_reg[31]_i_11_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[31]_i_16
- (.I0(\axi_rdata[31]_i_21_n_0 ),
- .I1(\axi_rdata[31]_i_22_n_0 ),
- .O(\axi_rdata_reg[31]_i_16_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF7 \axi_rdata_reg[31]_i_17
- (.I0(\axi_rdata[31]_i_23_n_0 ),
- .I1(\axi_rdata[31]_i_24_n_0 ),
- .O(\axi_rdata_reg[31]_i_17_n_0 ),
- .S(\axi_rdata_reg[23]_0 [2]));
- MUXF8 \axi_rdata_reg[31]_i_9
- (.I0(\axi_rdata_reg[31]_i_16_n_0 ),
- .I1(\axi_rdata_reg[31]_i_17_n_0 ),
- .O(\axi_rdata_reg[31]_i_9_n_0 ),
- .S(\axi_rdata_reg[23]_0 [3]));
- FDRE \axi_rdata_reg[3]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[3]_i_1_n_0 ),
- .Q(s00_axi_rdata[3]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[3]_i_11
- (.I0(\axi_rdata[3]_i_29_n_0 ),
- .I1(\axi_rdata[3]_i_30_n_0 ),
- .O(\axi_rdata_reg[3]_i_11_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[3]_i_12
- (.I0(\axi_rdata[3]_i_31_n_0 ),
- .I1(\axi_rdata[3]_i_32_n_0 ),
- .O(\axi_rdata_reg[3]_i_12_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[3]_i_13
- (.I0(\axi_rdata[3]_i_33_n_0 ),
- .I1(\data_o_reg[6][3] ),
- .O(\axi_rdata_reg[3]_i_13_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[3]_i_18
- (.I0(\axi_rdata[3]_i_36_n_0 ),
- .I1(\axi_rdata[3]_i_37_n_0 ),
- .O(\axi_rdata_reg[3]_i_18_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[3]_i_19
- (.I0(\data_o_reg[6][3]_0 ),
- .I1(\axi_rdata[3]_i_39_n_0 ),
- .O(\axi_rdata_reg[3]_i_19_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[3]_i_2
- (.I0(\axi_rdata[3]_i_5_n_0 ),
- .I1(\axi_rdata[3]_i_6_n_0 ),
- .O(\axi_rdata_reg[3]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[3]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][3] ),
- .I1(\axi_rdata[3]_i_41_n_0 ),
- .O(\axi_rdata_reg[3]_i_20_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[3]_i_24
- (.I0(\axi_rdata[3]_i_44_n_0 ),
- .I1(\axi_rdata[3]_i_45_n_0 ),
- .O(\axi_rdata_reg[3]_i_24_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[3]_i_3
- (.I0(\axi_rdata[3]_i_7_n_0 ),
- .I1(\axi_rdata[3]_i_8_n_0 ),
- .O(\axi_rdata_reg[3]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[4]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[4]_i_1_n_0 ),
- .Q(s00_axi_rdata[4]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[4]_i_11
- (.I0(\axi_rdata[4]_i_29_n_0 ),
- .I1(\axi_rdata[4]_i_30_n_0 ),
- .O(\axi_rdata_reg[4]_i_11_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[4]_i_12
- (.I0(\axi_rdata[4]_i_31_n_0 ),
- .I1(\axi_rdata[4]_i_32_n_0 ),
- .O(\axi_rdata_reg[4]_i_12_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[4]_i_13
- (.I0(\axi_rdata[4]_i_33_n_0 ),
- .I1(\data_o_reg[6][4] ),
- .O(\axi_rdata_reg[4]_i_13_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[4]_i_18
- (.I0(\axi_rdata[4]_i_36_n_0 ),
- .I1(\axi_rdata[4]_i_37_n_0 ),
- .O(\axi_rdata_reg[4]_i_18_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[4]_i_19
- (.I0(\data_o_reg[6][4]_0 ),
- .I1(\axi_rdata[4]_i_39_n_0 ),
- .O(\axi_rdata_reg[4]_i_19_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[4]_i_2
- (.I0(\axi_rdata[4]_i_5_n_0 ),
- .I1(\axi_rdata[4]_i_6_n_0 ),
- .O(\axi_rdata_reg[4]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[4]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][4] ),
- .I1(\axi_rdata[4]_i_41_n_0 ),
- .O(\axi_rdata_reg[4]_i_20_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[4]_i_24
- (.I0(\axi_rdata[4]_i_44_n_0 ),
- .I1(\axi_rdata[4]_i_45_n_0 ),
- .O(\axi_rdata_reg[4]_i_24_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[4]_i_3
- (.I0(\axi_rdata[4]_i_7_n_0 ),
- .I1(\axi_rdata[4]_i_8_n_0 ),
- .O(\axi_rdata_reg[4]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[5]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[5]_i_1_n_0 ),
- .Q(s00_axi_rdata[5]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[5]_i_11
- (.I0(\axi_rdata[5]_i_29_n_0 ),
- .I1(\axi_rdata[5]_i_30_n_0 ),
- .O(\axi_rdata_reg[5]_i_11_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[5]_i_12
- (.I0(\axi_rdata[5]_i_31_n_0 ),
- .I1(\axi_rdata[5]_i_32_n_0 ),
- .O(\axi_rdata_reg[5]_i_12_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[5]_i_13
- (.I0(\axi_rdata[5]_i_33_n_0 ),
- .I1(\data_o_reg[6][5] ),
- .O(\axi_rdata_reg[5]_i_13_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[5]_i_18
- (.I0(\axi_rdata[5]_i_36_n_0 ),
- .I1(\axi_rdata[5]_i_37_n_0 ),
- .O(\axi_rdata_reg[5]_i_18_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[5]_i_19
- (.I0(\data_o_reg[6][5]_0 ),
- .I1(\axi_rdata[5]_i_39_n_0 ),
- .O(\axi_rdata_reg[5]_i_19_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[5]_i_2
- (.I0(\axi_rdata[5]_i_5_n_0 ),
- .I1(\axi_rdata[5]_i_6_n_0 ),
- .O(\axi_rdata_reg[5]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[5]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][5] ),
- .I1(\axi_rdata[5]_i_41_n_0 ),
- .O(\axi_rdata_reg[5]_i_20_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[5]_i_24
- (.I0(\axi_rdata[5]_i_44_n_0 ),
- .I1(\axi_rdata[5]_i_45_n_0 ),
- .O(\axi_rdata_reg[5]_i_24_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[5]_i_3
- (.I0(\axi_rdata[5]_i_7_n_0 ),
- .I1(\axi_rdata[5]_i_8_n_0 ),
- .O(\axi_rdata_reg[5]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[6]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[6]_i_1_n_0 ),
- .Q(s00_axi_rdata[6]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[6]_i_11
- (.I0(\axi_rdata[6]_i_29_n_0 ),
- .I1(\axi_rdata[6]_i_30_n_0 ),
- .O(\axi_rdata_reg[6]_i_11_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[6]_i_12
- (.I0(\axi_rdata[6]_i_31_n_0 ),
- .I1(\axi_rdata[6]_i_32_n_0 ),
- .O(\axi_rdata_reg[6]_i_12_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[6]_i_13
- (.I0(\axi_rdata[6]_i_33_n_0 ),
- .I1(\data_o_reg[6][6] ),
- .O(\axi_rdata_reg[6]_i_13_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[6]_i_18
- (.I0(\axi_rdata[6]_i_36_n_0 ),
- .I1(\axi_rdata[6]_i_37_n_0 ),
- .O(\axi_rdata_reg[6]_i_18_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[6]_i_19
- (.I0(\data_o_reg[6][6]_0 ),
- .I1(\axi_rdata[6]_i_39_n_0 ),
- .O(\axi_rdata_reg[6]_i_19_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[6]_i_2
- (.I0(\axi_rdata[6]_i_5_n_0 ),
- .I1(\axi_rdata[6]_i_6_n_0 ),
- .O(\axi_rdata_reg[6]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[6]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][6] ),
- .I1(\axi_rdata[6]_i_41_n_0 ),
- .O(\axi_rdata_reg[6]_i_20_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[6]_i_24
- (.I0(\axi_rdata[6]_i_44_n_0 ),
- .I1(\axi_rdata[6]_i_45_n_0 ),
- .O(\axi_rdata_reg[6]_i_24_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[6]_i_3
- (.I0(\axi_rdata[6]_i_7_n_0 ),
- .I1(\axi_rdata[6]_i_8_n_0 ),
- .O(\axi_rdata_reg[6]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[7]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[7]_i_1_n_0 ),
- .Q(s00_axi_rdata[7]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[7]_i_11
- (.I0(\axi_rdata[7]_i_29_n_0 ),
- .I1(\axi_rdata[7]_i_30_n_0 ),
- .O(\axi_rdata_reg[7]_i_11_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[7]_i_12
- (.I0(\axi_rdata[7]_i_31_n_0 ),
- .I1(\axi_rdata[7]_i_32_n_0 ),
- .O(\axi_rdata_reg[7]_i_12_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[7]_i_13
- (.I0(\axi_rdata[7]_i_33_n_0 ),
- .I1(\data_o_reg[6][7] ),
- .O(\axi_rdata_reg[7]_i_13_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[7]_i_18
- (.I0(\axi_rdata[7]_i_36_n_0 ),
- .I1(\axi_rdata[7]_i_37_n_0 ),
- .O(\axi_rdata_reg[7]_i_18_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[7]_i_19
- (.I0(\data_o_reg[6][7]_0 ),
- .I1(\axi_rdata[7]_i_39_n_0 ),
- .O(\axi_rdata_reg[7]_i_19_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[7]_i_2
- (.I0(\axi_rdata[7]_i_5_n_0 ),
- .I1(\axi_rdata[7]_i_6_n_0 ),
- .O(\axi_rdata_reg[7]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[7]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][7] ),
- .I1(\axi_rdata[7]_i_41_n_0 ),
- .O(\axi_rdata_reg[7]_i_20_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[7]_i_24
- (.I0(\axi_rdata[7]_i_44_n_0 ),
- .I1(\axi_rdata[7]_i_45_n_0 ),
- .O(\axi_rdata_reg[7]_i_24_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[7]_i_3
- (.I0(\axi_rdata[7]_i_7_n_0 ),
- .I1(\axi_rdata[7]_i_8_n_0 ),
- .O(\axi_rdata_reg[7]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[8]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[8]_i_1_n_0 ),
- .Q(s00_axi_rdata[8]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[8]_i_11
- (.I0(\axi_rdata[8]_i_29_n_0 ),
- .I1(\axi_rdata[8]_i_30_n_0 ),
- .O(\axi_rdata_reg[8]_i_11_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[8]_i_12
- (.I0(\axi_rdata[8]_i_31_n_0 ),
- .I1(\axi_rdata[8]_i_32_n_0 ),
- .O(\axi_rdata_reg[8]_i_12_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[8]_i_18
- (.I0(\axi_rdata[8]_i_35_n_0 ),
- .I1(\axi_rdata[8]_i_36_n_0 ),
- .O(\axi_rdata_reg[8]_i_18_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[8]_i_2
- (.I0(\axi_rdata[8]_i_5_n_0 ),
- .I1(\axi_rdata[8]_i_6_n_0 ),
- .O(\axi_rdata_reg[8]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[8]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][8] ),
- .I1(\axi_rdata[8]_i_39_n_0 ),
- .O(\axi_rdata_reg[8]_i_20_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[8]_i_24
- (.I0(\axi_rdata[8]_i_42_n_0 ),
- .I1(\axi_rdata[8]_i_43_n_0 ),
- .O(\axi_rdata_reg[8]_i_24_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[8]_i_3
- (.I0(\axi_rdata[8]_i_7_n_0 ),
- .I1(\axi_rdata[8]_i_8_n_0 ),
- .O(\axi_rdata_reg[8]_i_3_n_0 ),
- .S(axi_araddr[7]));
- FDRE \axi_rdata_reg[9]
- (.C(s00_axi_aclk),
- .CE(\axi_rdata[31]_i_1_n_0 ),
- .D(\axi_rdata[9]_i_1_n_0 ),
- .Q(s00_axi_rdata[9]),
- .R(rst_i));
- MUXF7 \axi_rdata_reg[9]_i_11
- (.I0(\axi_rdata[9]_i_29_n_0 ),
- .I1(\axi_rdata[9]_i_30_n_0 ),
- .O(\axi_rdata_reg[9]_i_11_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[9]_i_12
- (.I0(\axi_rdata[9]_i_31_n_0 ),
- .I1(\axi_rdata[9]_i_32_n_0 ),
- .O(\axi_rdata_reg[9]_i_12_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[9]_i_18
- (.I0(\axi_rdata[9]_i_35_n_0 ),
- .I1(\axi_rdata[9]_i_36_n_0 ),
- .O(\axi_rdata_reg[9]_i_18_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[9]_i_2
- (.I0(\axi_rdata[9]_i_5_n_0 ),
- .I1(\axi_rdata[9]_i_6_n_0 ),
- .O(\axi_rdata_reg[9]_i_2_n_0 ),
- .S(axi_araddr[7]));
- MUXF7 \axi_rdata_reg[9]_i_20
- (.I0(\fmc_03287_channels[19].gen_chs.data_o_reg[67][9] ),
- .I1(\axi_rdata[9]_i_39_n_0 ),
- .O(\axi_rdata_reg[9]_i_20_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[9]_i_24
- (.I0(\axi_rdata[9]_i_42_n_0 ),
- .I1(\axi_rdata[9]_i_43_n_0 ),
- .O(\axi_rdata_reg[9]_i_24_n_0 ),
- .S(\axi_rdata_reg[9]_0 ));
- MUXF7 \axi_rdata_reg[9]_i_3
- (.I0(\axi_rdata[9]_i_7_n_0 ),
- .I1(\axi_rdata[9]_i_8_n_0 ),
- .O(\axi_rdata_reg[9]_i_3_n_0 ),
- .S(axi_araddr[7]));
- LUT6 #(
- .INIT(64'hF202F2F200000000))
- \axi_rresp[1]_i_1
- (.I0(s00_axi_rresp),
- .I1(axi_rvalid0),
- .I2(\axi_rdata[31]_i_1_n_0 ),
- .I3(axi_araddr[10]),
- .I4(\axi_rdata[23]_i_2_n_0 ),
- .I5(s00_axi_aresetn),
- .O(\axi_rresp[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT2 #(
- .INIT(4'h8))
- \axi_rresp[1]_i_2
- (.I0(s00_axi_rready),
- .I1(s00_axi_rvalid),
- .O(axi_rvalid0));
- FDRE \axi_rresp_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\axi_rresp[1]_i_1_n_0 ),
- .Q(s00_axi_rresp),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT4 #(
- .INIT(16'h08F8))
- axi_rvalid_i_1
- (.I0(s00_axi_arvalid),
- .I1(s00_axi_arready),
- .I2(s00_axi_rvalid),
- .I3(s00_axi_rready),
- .O(axi_rvalid_i_1_n_0));
- FDRE axi_rvalid_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(axi_rvalid_i_1_n_0),
- .Q(s00_axi_rvalid),
- .R(rst_i));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT3 #(
- .INIT(8'h08))
- axi_wready_i_1
- (.I0(s00_axi_awvalid),
- .I1(s00_axi_wvalid),
- .I2(s00_axi_wready),
- .O(axi_wready_i_1_n_0));
- FDRE axi_wready_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(axi_wready_i_1_n_0),
- .Q(s00_axi_wready),
- .R(rst_i));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[100][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[100][31]_i_2_n_0 ),
- .O(\data_rw_o[100][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[100][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[100][31]_i_2_n_0 ),
- .O(\data_rw_o[100][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[100][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[100][31]_i_2_n_0 ),
- .O(\data_rw_o[100][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFF7FFFFFF))
- \data_rw_o[100][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[6]),
- .I2(sel0[3]),
- .I3(sel0[5]),
- .I4(sel0[2]),
- .I5(\data_rw_o[96][31]_i_3_n_0 ),
- .O(\data_rw_o[100][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[100][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[100][31]_i_2_n_0 ),
- .O(\data_rw_o[100][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[101][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[101][31]_i_2_n_0 ),
- .O(\data_rw_o[101][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[101][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[101][31]_i_2_n_0 ),
- .O(\data_rw_o[101][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[101][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[101][31]_i_2_n_0 ),
- .O(\data_rw_o[101][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFD))
- \data_rw_o[101][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[78][31]_i_3_n_0 ),
- .I2(\data_rw_o[33][31]_i_3_n_0 ),
- .I3(\data_rw_o[85][31]_i_4_n_0 ),
- .I4(sel0[4]),
- .I5(sel0[1]),
- .O(\data_rw_o[101][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[101][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[101][31]_i_2_n_0 ),
- .O(\data_rw_o[101][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[102][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[102][31]_i_2_n_0 ),
- .O(\data_rw_o[102][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[102][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[102][31]_i_2_n_0 ),
- .O(\data_rw_o[102][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[102][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[102][31]_i_2_n_0 ),
- .O(\data_rw_o[102][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFDFFF))
- \data_rw_o[102][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[78][31]_i_3_n_0 ),
- .I2(sel0[5]),
- .I3(sel0[1]),
- .I4(\data_rw_o[85][31]_i_4_n_0 ),
- .I5(\data_rw_o[32][31]_i_4_n_0 ),
- .O(\data_rw_o[102][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[102][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[102][31]_i_2_n_0 ),
- .O(\data_rw_o[102][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[103][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[103][31]_i_2_n_0 ),
- .O(\data_rw_o[103][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[103][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[103][31]_i_2_n_0 ),
- .O(\data_rw_o[103][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[103][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[103][31]_i_2_n_0 ),
- .O(\data_rw_o[103][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFF7F))
- \data_rw_o[103][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[2]),
- .I2(sel0[5]),
- .I3(\data_rw_o[23][31]_i_4_n_0 ),
- .I4(\data_rw_o[103][31]_i_3_n_0 ),
- .I5(\data_rw_o[97][31]_i_3_n_0 ),
- .O(\data_rw_o[103][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
- LUT2 #(
- .INIT(4'hE))
- \data_rw_o[103][31]_i_3
- (.I0(sel0[4]),
- .I1(sel0[7]),
- .O(\data_rw_o[103][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[103][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[103][31]_i_2_n_0 ),
- .O(\data_rw_o[103][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[10][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[10][31]_i_2_n_0 ),
- .O(\data_rw_o[10][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[10][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[10][31]_i_2_n_0 ),
- .O(\data_rw_o[10][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[10][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[10][31]_i_2_n_0 ),
- .O(\data_rw_o[10][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFDFFFFFF))
- \data_rw_o[10][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[2]),
- .I2(sel0[0]),
- .I3(sel0[1]),
- .I4(sel0[3]),
- .I5(\data_rw_o[3][31]_i_7_n_0 ),
- .O(\data_rw_o[10][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[10][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[10][31]_i_2_n_0 ),
- .O(\data_rw_o[10][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[11][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[11][31]_i_2_n_0 ),
- .O(\data_rw_o[11][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[11][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[11][31]_i_2_n_0 ),
- .O(\data_rw_o[11][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[11][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[11][31]_i_2_n_0 ),
- .O(\data_rw_o[11][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFF7FFFFFF))
- \data_rw_o[11][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[3]),
- .I2(sel0[2]),
- .I3(sel0[0]),
- .I4(sel0[1]),
- .I5(\data_rw_o[3][31]_i_7_n_0 ),
- .O(\data_rw_o[11][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[11][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[11][31]_i_2_n_0 ),
- .O(\data_rw_o[11][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[16][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[16][31]_i_2_n_0 ),
- .O(\data_rw_o[16][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[16][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[16][31]_i_2_n_0 ),
- .O(\data_rw_o[16][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[16][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[16][31]_i_2_n_0 ),
- .O(\data_rw_o[16][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFDFF))
- \data_rw_o[16][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[2]),
- .I2(sel0[3]),
- .I3(sel0[4]),
- .I4(sel0[1]),
- .I5(\data_rw_o[16][31]_i_3_n_0 ),
- .O(\data_rw_o[16][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \data_rw_o[16][31]_i_3
- (.I0(sel0[7]),
- .I1(sel0[6]),
- .I2(sel0[0]),
- .I3(sel0[5]),
- .O(\data_rw_o[16][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[16][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[16][31]_i_2_n_0 ),
- .O(\data_rw_o[16][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[17][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[17][31]_i_2_n_0 ),
- .O(\data_rw_o[17][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[17][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[17][31]_i_2_n_0 ),
- .O(\data_rw_o[17][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[17][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[17][31]_i_2_n_0 ),
- .O(\data_rw_o[17][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFDFFFFFF))
- \data_rw_o[17][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[2]),
- .I2(sel0[3]),
- .I3(sel0[0]),
- .I4(sel0[4]),
- .I5(\data_rw_o[17][31]_i_3_n_0 ),
- .O(\data_rw_o[17][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \data_rw_o[17][31]_i_3
- (.I0(sel0[7]),
- .I1(sel0[6]),
- .I2(sel0[1]),
- .I3(sel0[5]),
- .O(\data_rw_o[17][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[17][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[17][31]_i_2_n_0 ),
- .O(\data_rw_o[17][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[18][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[18][31]_i_2_n_0 ),
- .O(\data_rw_o[18][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[18][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[18][31]_i_2_n_0 ),
- .O(\data_rw_o[18][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[18][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[18][31]_i_2_n_0 ),
- .O(\data_rw_o[18][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFDFFFFFF))
- \data_rw_o[18][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[2]),
- .I2(sel0[3]),
- .I3(sel0[1]),
- .I4(sel0[4]),
- .I5(\data_rw_o[16][31]_i_3_n_0 ),
- .O(\data_rw_o[18][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[18][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[18][31]_i_2_n_0 ),
- .O(\data_rw_o[18][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[19][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[19][31]_i_2_n_0 ),
- .O(\data_rw_o[19][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[19][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[19][31]_i_2_n_0 ),
- .O(\data_rw_o[19][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[19][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[19][31]_i_2_n_0 ),
- .O(\data_rw_o[19][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFF7FFFFFF))
- \data_rw_o[19][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[4]),
- .I2(sel0[3]),
- .I3(sel0[0]),
- .I4(sel0[1]),
- .I5(\data_rw_o[19][31]_i_3_n_0 ),
- .O(\data_rw_o[19][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair19" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \data_rw_o[19][31]_i_3
- (.I0(sel0[7]),
- .I1(sel0[6]),
- .I2(sel0[2]),
- .I3(sel0[5]),
- .O(\data_rw_o[19][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[19][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[19][31]_i_2_n_0 ),
- .O(\data_rw_o[19][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[20][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[20][31]_i_2_n_0 ),
- .O(\data_rw_o[20][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[20][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[20][31]_i_2_n_0 ),
- .O(\data_rw_o[20][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[20][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[20][31]_i_2_n_0 ),
- .O(\data_rw_o[20][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFDFFFFFF))
- \data_rw_o[20][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[0]),
- .I2(sel0[3]),
- .I3(sel0[2]),
- .I4(sel0[4]),
- .I5(\data_rw_o[17][31]_i_3_n_0 ),
- .O(\data_rw_o[20][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[20][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[20][31]_i_2_n_0 ),
- .O(\data_rw_o[20][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[21][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[21][31]_i_2_n_0 ),
- .O(\data_rw_o[21][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[21][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[21][31]_i_2_n_0 ),
- .O(\data_rw_o[21][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[21][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[21][31]_i_2_n_0 ),
- .O(\data_rw_o[21][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFF7FFFFFF))
- \data_rw_o[21][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[4]),
- .I2(sel0[3]),
- .I3(sel0[0]),
- .I4(sel0[2]),
- .I5(\data_rw_o[17][31]_i_3_n_0 ),
- .O(\data_rw_o[21][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[21][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[21][31]_i_2_n_0 ),
- .O(\data_rw_o[21][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[22][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[22][31]_i_2_n_0 ),
- .O(\data_rw_o[22][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[22][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[22][31]_i_2_n_0 ),
- .O(\data_rw_o[22][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[22][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[22][31]_i_2_n_0 ),
- .O(\data_rw_o[22][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFF7FFFFFF))
- \data_rw_o[22][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[4]),
- .I2(sel0[3]),
- .I3(sel0[2]),
- .I4(sel0[1]),
- .I5(\data_rw_o[16][31]_i_3_n_0 ),
- .O(\data_rw_o[22][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[22][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[22][31]_i_2_n_0 ),
- .O(\data_rw_o[22][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[23][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[23][31]_i_2_n_0 ),
- .O(\data_rw_o[23][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[23][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[23][31]_i_2_n_0 ),
- .O(\data_rw_o[23][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[23][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[23][31]_i_2_n_0 ),
- .O(\data_rw_o[23][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFD))
- \data_rw_o[23][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[23][31]_i_3_n_0 ),
- .I2(\data_rw_o[23][31]_i_4_n_0 ),
- .I3(\data_rw_o[23][31]_i_5_n_0 ),
- .I4(sel0[3]),
- .I5(sel0[5]),
- .O(\data_rw_o[23][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
- LUT2 #(
- .INIT(4'h7))
- \data_rw_o[23][31]_i_3
- (.I0(sel0[4]),
- .I1(sel0[2]),
- .O(\data_rw_o[23][31]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
- LUT2 #(
- .INIT(4'h7))
- \data_rw_o[23][31]_i_4
- (.I0(sel0[1]),
- .I1(sel0[0]),
- .O(\data_rw_o[23][31]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair23" *)
- LUT2 #(
- .INIT(4'hE))
- \data_rw_o[23][31]_i_5
- (.I0(sel0[6]),
- .I1(sel0[7]),
- .O(\data_rw_o[23][31]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[23][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[23][31]_i_2_n_0 ),
- .O(\data_rw_o[23][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[24][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[24][31]_i_2_n_0 ),
- .O(\data_rw_o[24][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[24][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[24][31]_i_2_n_0 ),
- .O(\data_rw_o[24][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[24][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[24][31]_i_2_n_0 ),
- .O(\data_rw_o[24][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFDFFFFFF))
- \data_rw_o[24][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[2]),
- .I2(sel0[0]),
- .I3(sel0[3]),
- .I4(sel0[4]),
- .I5(\data_rw_o[17][31]_i_3_n_0 ),
- .O(\data_rw_o[24][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[24][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[24][31]_i_2_n_0 ),
- .O(\data_rw_o[24][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[25][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[25][31]_i_2_n_0 ),
- .O(\data_rw_o[25][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[25][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[25][31]_i_2_n_0 ),
- .O(\data_rw_o[25][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[25][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[25][31]_i_2_n_0 ),
- .O(\data_rw_o[25][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFF7FFFFFF))
- \data_rw_o[25][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[4]),
- .I2(sel0[1]),
- .I3(sel0[0]),
- .I4(sel0[3]),
- .I5(\data_rw_o[19][31]_i_3_n_0 ),
- .O(\data_rw_o[25][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[25][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[25][31]_i_2_n_0 ),
- .O(\data_rw_o[25][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[26][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[26][31]_i_2_n_0 ),
- .O(\data_rw_o[26][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[26][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[26][31]_i_2_n_0 ),
- .O(\data_rw_o[26][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[26][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[26][31]_i_2_n_0 ),
- .O(\data_rw_o[26][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFF7FFFFFF))
- \data_rw_o[26][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[4]),
- .I2(sel0[0]),
- .I3(sel0[3]),
- .I4(sel0[1]),
- .I5(\data_rw_o[19][31]_i_3_n_0 ),
- .O(\data_rw_o[26][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[26][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[26][31]_i_2_n_0 ),
- .O(\data_rw_o[26][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[27][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[27][31]_i_2_n_0 ),
- .O(\data_rw_o[27][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[27][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[27][31]_i_2_n_0 ),
- .O(\data_rw_o[27][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[27][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[27][31]_i_2_n_0 ),
- .O(\data_rw_o[27][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF7FFFFFFF))
- \data_rw_o[27][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[3]),
- .I2(sel0[4]),
- .I3(sel0[0]),
- .I4(sel0[1]),
- .I5(\data_rw_o[19][31]_i_3_n_0 ),
- .O(\data_rw_o[27][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[27][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[27][31]_i_2_n_0 ),
- .O(\data_rw_o[27][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[28][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[28][31]_i_2_n_0 ),
- .O(\data_rw_o[28][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[28][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[28][31]_i_2_n_0 ),
- .O(\data_rw_o[28][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[28][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[28][31]_i_2_n_0 ),
- .O(\data_rw_o[28][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFF7FFFFFF))
- \data_rw_o[28][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[4]),
- .I2(sel0[0]),
- .I3(sel0[3]),
- .I4(sel0[2]),
- .I5(\data_rw_o[17][31]_i_3_n_0 ),
- .O(\data_rw_o[28][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[28][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[28][31]_i_2_n_0 ),
- .O(\data_rw_o[28][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[29][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[29][31]_i_2_n_0 ),
- .O(\data_rw_o[29][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[29][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[29][31]_i_2_n_0 ),
- .O(\data_rw_o[29][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[29][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[29][31]_i_2_n_0 ),
- .O(\data_rw_o[29][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF7FFFFFFF))
- \data_rw_o[29][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[2]),
- .I2(sel0[4]),
- .I3(sel0[0]),
- .I4(sel0[3]),
- .I5(\data_rw_o[17][31]_i_3_n_0 ),
- .O(\data_rw_o[29][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[29][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[29][31]_i_2_n_0 ),
- .O(\data_rw_o[29][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[30][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[30][31]_i_2_n_0 ),
- .O(\data_rw_o[30][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[30][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[30][31]_i_2_n_0 ),
- .O(\data_rw_o[30][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[30][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[30][31]_i_2_n_0 ),
- .O(\data_rw_o[30][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF7FFFFFFF))
- \data_rw_o[30][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[2]),
- .I2(sel0[4]),
- .I3(sel0[3]),
- .I4(sel0[1]),
- .I5(\data_rw_o[16][31]_i_3_n_0 ),
- .O(\data_rw_o[30][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[30][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[30][31]_i_2_n_0 ),
- .O(\data_rw_o[30][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[31][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[31][31]_i_2_n_0 ),
- .O(\data_rw_o[31][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[31][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[31][31]_i_2_n_0 ),
- .O(\data_rw_o[31][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[31][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[31][31]_i_2_n_0 ),
- .O(\data_rw_o[31][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFDFFFF))
- \data_rw_o[31][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[31][31]_i_3_n_0 ),
- .I2(sel0[7]),
- .I3(sel0[6]),
- .I4(sel0[4]),
- .I5(sel0[5]),
- .O(\data_rw_o[31][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
- LUT4 #(
- .INIT(16'h7FFF))
- \data_rw_o[31][31]_i_3
- (.I0(sel0[2]),
- .I1(sel0[3]),
- .I2(sel0[0]),
- .I3(sel0[1]),
- .O(\data_rw_o[31][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[31][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[31][31]_i_2_n_0 ),
- .O(\data_rw_o[31][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[32][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[32][31]_i_2_n_0 ),
- .O(\data_rw_o[32][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[32][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[32][31]_i_2_n_0 ),
- .O(\data_rw_o[32][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[32][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[32][31]_i_2_n_0 ),
- .O(\data_rw_o[32][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFDF))
- \data_rw_o[32][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[32][31]_i_3_n_0 ),
- .I2(sel0[5]),
- .I3(sel0[1]),
- .I4(\data_rw_o[23][31]_i_5_n_0 ),
- .I5(\data_rw_o[32][31]_i_4_n_0 ),
- .O(\data_rw_o[32][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT2 #(
- .INIT(4'hE))
- \data_rw_o[32][31]_i_3
- (.I0(sel0[3]),
- .I1(sel0[2]),
- .O(\data_rw_o[32][31]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
- LUT2 #(
- .INIT(4'hE))
- \data_rw_o[32][31]_i_4
- (.I0(sel0[0]),
- .I1(sel0[4]),
- .O(\data_rw_o[32][31]_i_4_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[32][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[32][31]_i_2_n_0 ),
- .O(\data_rw_o[32][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[33][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[33][31]_i_2_n_0 ),
- .O(\data_rw_o[33][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[33][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[33][31]_i_2_n_0 ),
- .O(\data_rw_o[33][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[33][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[33][31]_i_2_n_0 ),
- .O(\data_rw_o[33][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFD))
- \data_rw_o[33][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[32][31]_i_3_n_0 ),
- .I2(\data_rw_o[33][31]_i_3_n_0 ),
- .I3(\data_rw_o[23][31]_i_5_n_0 ),
- .I4(sel0[4]),
- .I5(sel0[1]),
- .O(\data_rw_o[33][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair30" *)
- LUT2 #(
- .INIT(4'h7))
- \data_rw_o[33][31]_i_3
- (.I0(sel0[5]),
- .I1(sel0[0]),
- .O(\data_rw_o[33][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[33][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[33][31]_i_2_n_0 ),
- .O(\data_rw_o[33][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[34][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[34][31]_i_2_n_0 ),
- .O(\data_rw_o[34][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[34][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[34][31]_i_2_n_0 ),
- .O(\data_rw_o[34][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[34][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[34][31]_i_2_n_0 ),
- .O(\data_rw_o[34][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFDFFF))
- \data_rw_o[34][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[32][31]_i_3_n_0 ),
- .I2(sel0[1]),
- .I3(sel0[5]),
- .I4(\data_rw_o[23][31]_i_5_n_0 ),
- .I5(\data_rw_o[32][31]_i_4_n_0 ),
- .O(\data_rw_o[34][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[34][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[34][31]_i_2_n_0 ),
- .O(\data_rw_o[34][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[35][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[35][31]_i_2_n_0 ),
- .O(\data_rw_o[35][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[35][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[35][31]_i_2_n_0 ),
- .O(\data_rw_o[35][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[35][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[35][31]_i_2_n_0 ),
- .O(\data_rw_o[35][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFF7))
- \data_rw_o[35][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[5]),
- .I2(sel0[3]),
- .I3(\data_rw_o[23][31]_i_4_n_0 ),
- .I4(\data_rw_o[23][31]_i_5_n_0 ),
- .I5(\data_rw_o[35][31]_i_3_n_0 ),
- .O(\data_rw_o[35][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair27" *)
- LUT2 #(
- .INIT(4'hE))
- \data_rw_o[35][31]_i_3
- (.I0(sel0[2]),
- .I1(sel0[4]),
- .O(\data_rw_o[35][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[35][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[35][31]_i_2_n_0 ),
- .O(\data_rw_o[35][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[3][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[3][31]_i_3_n_0 ),
- .O(\data_rw_o[3][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[3][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[3][31]_i_3_n_0 ),
- .O(\data_rw_o[3][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[3][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[3][31]_i_3_n_0 ),
- .O(\data_rw_o[3][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0F001F1F0F001010))
- \data_rw_o[3][31]_i_2
- (.I0(sel0[5]),
- .I1(sel0[4]),
- .I2(sel0[7]),
- .I3(\data_rw_o[3][31]_i_4_n_0 ),
- .I4(sel0[6]),
- .I5(\data_rw_o[3][31]_i_5_n_0 ),
- .O(\data_rw_o[3][31]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFDFFFFFF))
- \data_rw_o[3][31]_i_3
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[2]),
- .I2(sel0[3]),
- .I3(sel0[0]),
- .I4(sel0[1]),
- .I5(\data_rw_o[3][31]_i_7_n_0 ),
- .O(\data_rw_o[3][31]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'hFFF0037F))
- \data_rw_o[3][31]_i_4
- (.I0(sel0[1]),
- .I1(sel0[2]),
- .I2(sel0[3]),
- .I3(sel0[4]),
- .I4(sel0[5]),
- .O(\data_rw_o[3][31]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFAA0000AFBF))
- \data_rw_o[3][31]_i_5
- (.I0(sel0[2]),
- .I1(sel0[0]),
- .I2(sel0[1]),
- .I3(sel0[3]),
- .I4(sel0[4]),
- .I5(sel0[5]),
- .O(\data_rw_o[3][31]_i_5_n_0 ));
- LUT5 #(
- .INIT(32'h80000000))
- \data_rw_o[3][31]_i_6
- (.I0(s00_axi_awready),
- .I1(\axi_bresp[1]_i_3_n_0 ),
- .I2(s00_axi_wready),
- .I3(s00_axi_wvalid),
- .I4(s00_axi_awvalid),
- .O(\data_rw_o[0]1 ));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \data_rw_o[3][31]_i_7
- (.I0(sel0[7]),
- .I1(sel0[6]),
- .I2(sel0[4]),
- .I3(sel0[5]),
- .O(\data_rw_o[3][31]_i_7_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[3][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[3][31]_i_3_n_0 ),
- .O(\data_rw_o[3][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[78][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[78][31]_i_2_n_0 ),
- .O(\data_rw_o[78][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[78][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[78][31]_i_2_n_0 ),
- .O(\data_rw_o[78][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[78][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[78][31]_i_2_n_0 ),
- .O(\data_rw_o[78][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFD))
- \data_rw_o[78][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[78][31]_i_3_n_0 ),
- .I2(\data_rw_o[78][31]_i_4_n_0 ),
- .I3(sel0[7]),
- .I4(sel0[0]),
- .I5(\data_rw_o[78][31]_i_5_n_0 ),
- .O(\data_rw_o[78][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
- LUT2 #(
- .INIT(4'h7))
- \data_rw_o[78][31]_i_3
- (.I0(sel0[6]),
- .I1(sel0[2]),
- .O(\data_rw_o[78][31]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
- LUT2 #(
- .INIT(4'h7))
- \data_rw_o[78][31]_i_4
- (.I0(sel0[1]),
- .I1(sel0[3]),
- .O(\data_rw_o[78][31]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
- LUT2 #(
- .INIT(4'hE))
- \data_rw_o[78][31]_i_5
- (.I0(sel0[5]),
- .I1(sel0[4]),
- .O(\data_rw_o[78][31]_i_5_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[78][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[78][31]_i_2_n_0 ),
- .O(\data_rw_o[78][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[79][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[79][31]_i_2_n_0 ),
- .O(\data_rw_o[79][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[79][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[79][31]_i_2_n_0 ),
- .O(\data_rw_o[79][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[79][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[79][31]_i_2_n_0 ),
- .O(\data_rw_o[79][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFDFFFF))
- \data_rw_o[79][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[31][31]_i_3_n_0 ),
- .I2(sel0[7]),
- .I3(sel0[4]),
- .I4(sel0[6]),
- .I5(sel0[5]),
- .O(\data_rw_o[79][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[79][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[79][31]_i_2_n_0 ),
- .O(\data_rw_o[79][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[84][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[84][31]_i_2_n_0 ),
- .O(\data_rw_o[84][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[84][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[84][31]_i_2_n_0 ),
- .O(\data_rw_o[84][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[84][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[84][31]_i_2_n_0 ),
- .O(\data_rw_o[84][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFF7FFFFFF))
- \data_rw_o[84][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[6]),
- .I2(sel0[3]),
- .I3(sel0[4]),
- .I4(sel0[2]),
- .I5(\data_rw_o[84][31]_i_3_n_0 ),
- .O(\data_rw_o[84][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \data_rw_o[84][31]_i_3
- (.I0(sel0[7]),
- .I1(sel0[1]),
- .I2(sel0[0]),
- .I3(sel0[5]),
- .O(\data_rw_o[84][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[84][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[84][31]_i_2_n_0 ),
- .O(\data_rw_o[84][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[85][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[85][31]_i_2_n_0 ),
- .O(\data_rw_o[85][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[85][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[85][31]_i_2_n_0 ),
- .O(\data_rw_o[85][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[85][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[85][31]_i_2_n_0 ),
- .O(\data_rw_o[85][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFD))
- \data_rw_o[85][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[78][31]_i_3_n_0 ),
- .I2(\data_rw_o[85][31]_i_3_n_0 ),
- .I3(\data_rw_o[85][31]_i_4_n_0 ),
- .I4(sel0[1]),
- .I5(sel0[5]),
- .O(\data_rw_o[85][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair24" *)
- LUT2 #(
- .INIT(4'h7))
- \data_rw_o[85][31]_i_3
- (.I0(sel0[4]),
- .I1(sel0[0]),
- .O(\data_rw_o[85][31]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair31" *)
- LUT2 #(
- .INIT(4'hE))
- \data_rw_o[85][31]_i_4
- (.I0(sel0[3]),
- .I1(sel0[7]),
- .O(\data_rw_o[85][31]_i_4_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[85][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[85][31]_i_2_n_0 ),
- .O(\data_rw_o[85][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[86][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[86][31]_i_2_n_0 ),
- .O(\data_rw_o[86][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[86][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[86][31]_i_2_n_0 ),
- .O(\data_rw_o[86][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[86][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[86][31]_i_2_n_0 ),
- .O(\data_rw_o[86][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFDFFF))
- \data_rw_o[86][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[78][31]_i_3_n_0 ),
- .I2(sel0[4]),
- .I3(sel0[1]),
- .I4(\data_rw_o[85][31]_i_4_n_0 ),
- .I5(\data_rw_o[86][31]_i_3_n_0 ),
- .O(\data_rw_o[86][31]_i_2_n_0 ));
- LUT2 #(
- .INIT(4'hE))
- \data_rw_o[86][31]_i_3
- (.I0(sel0[5]),
- .I1(sel0[0]),
- .O(\data_rw_o[86][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[86][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[86][31]_i_2_n_0 ),
- .O(\data_rw_o[86][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[87][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[87][31]_i_2_n_0 ),
- .O(\data_rw_o[87][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[87][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[87][31]_i_2_n_0 ),
- .O(\data_rw_o[87][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[87][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[87][31]_i_2_n_0 ),
- .O(\data_rw_o[87][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFF7F))
- \data_rw_o[87][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[2]),
- .I2(sel0[4]),
- .I3(\data_rw_o[23][31]_i_4_n_0 ),
- .I4(\data_rw_o[85][31]_i_4_n_0 ),
- .I5(\data_rw_o[87][31]_i_3_n_0 ),
- .O(\data_rw_o[87][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
- LUT2 #(
- .INIT(4'hB))
- \data_rw_o[87][31]_i_3
- (.I0(sel0[5]),
- .I1(sel0[6]),
- .O(\data_rw_o[87][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[87][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[87][31]_i_2_n_0 ),
- .O(\data_rw_o[87][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[88][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[88][31]_i_2_n_0 ),
- .O(\data_rw_o[88][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[88][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[88][31]_i_2_n_0 ),
- .O(\data_rw_o[88][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[88][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[88][31]_i_2_n_0 ),
- .O(\data_rw_o[88][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFF7FFFFFF))
- \data_rw_o[88][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[6]),
- .I2(sel0[1]),
- .I3(sel0[4]),
- .I4(sel0[3]),
- .I5(\data_rw_o[88][31]_i_3_n_0 ),
- .O(\data_rw_o[88][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \data_rw_o[88][31]_i_3
- (.I0(sel0[7]),
- .I1(sel0[2]),
- .I2(sel0[0]),
- .I3(sel0[5]),
- .O(\data_rw_o[88][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[88][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[88][31]_i_2_n_0 ),
- .O(\data_rw_o[88][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[89][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[89][31]_i_2_n_0 ),
- .O(\data_rw_o[89][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[89][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[89][31]_i_2_n_0 ),
- .O(\data_rw_o[89][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[89][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[89][31]_i_2_n_0 ),
- .O(\data_rw_o[89][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFF7F))
- \data_rw_o[89][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[3]),
- .I2(sel0[6]),
- .I3(\data_rw_o[85][31]_i_3_n_0 ),
- .I4(\data_rw_o[89][31]_i_3_n_0 ),
- .I5(\data_rw_o[89][31]_i_4_n_0 ),
- .O(\data_rw_o[89][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair22" *)
- LUT2 #(
- .INIT(4'hE))
- \data_rw_o[89][31]_i_3
- (.I0(sel0[2]),
- .I1(sel0[7]),
- .O(\data_rw_o[89][31]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair25" *)
- LUT2 #(
- .INIT(4'hE))
- \data_rw_o[89][31]_i_4
- (.I0(sel0[5]),
- .I1(sel0[1]),
- .O(\data_rw_o[89][31]_i_4_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[89][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[89][31]_i_2_n_0 ),
- .O(\data_rw_o[89][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[90][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[90][31]_i_2_n_0 ),
- .O(\data_rw_o[90][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[90][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[90][31]_i_2_n_0 ),
- .O(\data_rw_o[90][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[90][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[90][31]_i_2_n_0 ),
- .O(\data_rw_o[90][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF7FFFFFFF))
- \data_rw_o[90][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[3]),
- .I2(sel0[6]),
- .I3(sel0[4]),
- .I4(sel0[1]),
- .I5(\data_rw_o[88][31]_i_3_n_0 ),
- .O(\data_rw_o[90][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[90][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[90][31]_i_2_n_0 ),
- .O(\data_rw_o[90][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[91][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[91][31]_i_2_n_0 ),
- .O(\data_rw_o[91][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[91][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[91][31]_i_2_n_0 ),
- .O(\data_rw_o[91][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[91][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[91][31]_i_2_n_0 ),
- .O(\data_rw_o[91][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFF7F))
- \data_rw_o[91][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[4]),
- .I2(sel0[3]),
- .I3(\data_rw_o[23][31]_i_4_n_0 ),
- .I4(\data_rw_o[89][31]_i_3_n_0 ),
- .I5(\data_rw_o[87][31]_i_3_n_0 ),
- .O(\data_rw_o[91][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[91][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[91][31]_i_2_n_0 ),
- .O(\data_rw_o[91][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[92][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[92][31]_i_2_n_0 ),
- .O(\data_rw_o[92][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[92][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[92][31]_i_2_n_0 ),
- .O(\data_rw_o[92][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[92][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[92][31]_i_2_n_0 ),
- .O(\data_rw_o[92][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF7FFFFFFF))
- \data_rw_o[92][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[2]),
- .I2(sel0[6]),
- .I3(sel0[4]),
- .I4(sel0[3]),
- .I5(\data_rw_o[84][31]_i_3_n_0 ),
- .O(\data_rw_o[92][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[92][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[92][31]_i_2_n_0 ),
- .O(\data_rw_o[92][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[93][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[93][31]_i_2_n_0 ),
- .O(\data_rw_o[93][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[93][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[93][31]_i_2_n_0 ),
- .O(\data_rw_o[93][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[93][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[93][31]_i_2_n_0 ),
- .O(\data_rw_o[93][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFD))
- \data_rw_o[93][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[93][31]_i_3_n_0 ),
- .I2(\data_rw_o[85][31]_i_3_n_0 ),
- .I3(sel0[7]),
- .I4(sel0[1]),
- .I5(\data_rw_o[87][31]_i_3_n_0 ),
- .O(\data_rw_o[93][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair20" *)
- LUT2 #(
- .INIT(4'h7))
- \data_rw_o[93][31]_i_3
- (.I0(sel0[3]),
- .I1(sel0[2]),
- .O(\data_rw_o[93][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[93][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[93][31]_i_2_n_0 ),
- .O(\data_rw_o[93][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[94][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[94][31]_i_2_n_0 ),
- .O(\data_rw_o[94][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[94][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[94][31]_i_2_n_0 ),
- .O(\data_rw_o[94][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[94][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[94][31]_i_2_n_0 ),
- .O(\data_rw_o[94][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFD))
- \data_rw_o[94][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[93][31]_i_3_n_0 ),
- .I2(\data_rw_o[94][31]_i_3_n_0 ),
- .I3(sel0[7]),
- .I4(sel0[0]),
- .I5(\data_rw_o[87][31]_i_3_n_0 ),
- .O(\data_rw_o[94][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair29" *)
- LUT2 #(
- .INIT(4'h7))
- \data_rw_o[94][31]_i_3
- (.I0(sel0[1]),
- .I1(sel0[4]),
- .O(\data_rw_o[94][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[94][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[94][31]_i_2_n_0 ),
- .O(\data_rw_o[94][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[95][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[95][31]_i_2_n_0 ),
- .O(\data_rw_o[95][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[95][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[95][31]_i_2_n_0 ),
- .O(\data_rw_o[95][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[95][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[95][31]_i_2_n_0 ),
- .O(\data_rw_o[95][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFDFFFFFFFFFFFF))
- \data_rw_o[95][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[31][31]_i_3_n_0 ),
- .I2(sel0[7]),
- .I3(sel0[5]),
- .I4(sel0[4]),
- .I5(sel0[6]),
- .O(\data_rw_o[95][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[95][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[95][31]_i_2_n_0 ),
- .O(\data_rw_o[95][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[96][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[96][31]_i_2_n_0 ),
- .O(\data_rw_o[96][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[96][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[96][31]_i_2_n_0 ),
- .O(\data_rw_o[96][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[96][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[96][31]_i_2_n_0 ),
- .O(\data_rw_o[96][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFDFFFFFF))
- \data_rw_o[96][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(sel0[2]),
- .I2(sel0[3]),
- .I3(sel0[5]),
- .I4(sel0[6]),
- .I5(\data_rw_o[96][31]_i_3_n_0 ),
- .O(\data_rw_o[96][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair21" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \data_rw_o[96][31]_i_3
- (.I0(sel0[7]),
- .I1(sel0[1]),
- .I2(sel0[4]),
- .I3(sel0[0]),
- .O(\data_rw_o[96][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[96][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[96][31]_i_2_n_0 ),
- .O(\data_rw_o[96][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[97][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[97][31]_i_2_n_0 ),
- .O(\data_rw_o[97][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[97][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[97][31]_i_2_n_0 ),
- .O(\data_rw_o[97][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[97][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[97][31]_i_2_n_0 ),
- .O(\data_rw_o[97][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFD))
- \data_rw_o[97][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[97][31]_i_3_n_0 ),
- .I2(\data_rw_o[33][31]_i_3_n_0 ),
- .I3(\data_rw_o[89][31]_i_3_n_0 ),
- .I4(sel0[4]),
- .I5(sel0[1]),
- .O(\data_rw_o[97][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair28" *)
- LUT2 #(
- .INIT(4'hB))
- \data_rw_o[97][31]_i_3
- (.I0(sel0[3]),
- .I1(sel0[6]),
- .O(\data_rw_o[97][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[97][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[97][31]_i_2_n_0 ),
- .O(\data_rw_o[97][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[98][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[98][31]_i_2_n_0 ),
- .O(\data_rw_o[98][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[98][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[98][31]_i_2_n_0 ),
- .O(\data_rw_o[98][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[98][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[98][31]_i_2_n_0 ),
- .O(\data_rw_o[98][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFDFFF))
- \data_rw_o[98][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[97][31]_i_3_n_0 ),
- .I2(sel0[5]),
- .I3(sel0[1]),
- .I4(\data_rw_o[89][31]_i_3_n_0 ),
- .I5(\data_rw_o[32][31]_i_4_n_0 ),
- .O(\data_rw_o[98][31]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[98][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[98][31]_i_2_n_0 ),
- .O(\data_rw_o[98][7]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[99][15]_i_1
- (.I0(s00_axi_wstrb[1]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[99][31]_i_2_n_0 ),
- .O(\data_rw_o[99][15]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[99][23]_i_1
- (.I0(s00_axi_wstrb[2]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[99][31]_i_2_n_0 ),
- .O(\data_rw_o[99][23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[99][31]_i_1
- (.I0(s00_axi_wstrb[3]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[99][31]_i_2_n_0 ),
- .O(\data_rw_o[99][31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFD))
- \data_rw_o[99][31]_i_2
- (.I0(\data_rw_o[0]1 ),
- .I1(\data_rw_o[99][31]_i_3_n_0 ),
- .I2(\data_rw_o[23][31]_i_4_n_0 ),
- .I3(\data_rw_o[85][31]_i_4_n_0 ),
- .I4(sel0[4]),
- .I5(sel0[2]),
- .O(\data_rw_o[99][31]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair26" *)
- LUT2 #(
- .INIT(4'h7))
- \data_rw_o[99][31]_i_3
- (.I0(sel0[6]),
- .I1(sel0[5]),
- .O(\data_rw_o[99][31]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h02))
- \data_rw_o[99][7]_i_1
- (.I0(s00_axi_wstrb[0]),
- .I1(\data_rw_o[3][31]_i_2_n_0 ),
- .I2(\data_rw_o[99][31]_i_2_n_0 ),
- .O(\data_rw_o[99][7]_i_1_n_0 ));
- FDSE \data_rw_o_reg[100][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[4].[0].s_reqs_reg[16][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[100][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[4].[0].s_reqs_reg[16][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[4].[0].s_reqs_reg[16][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[100][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[100][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[100][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[100][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[100][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[100][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[100][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[100][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[100][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[4].[0].s_reqs_reg[16][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[100][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[100][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[100][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[100][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[100][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[100][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[100][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[100][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[100][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[100][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[100][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[100][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[4].[0].s_reqs_reg[16][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[100][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[100][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[100][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[100][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[100][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[4].[0].s_reqs_reg[16][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[100][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[4].[0].s_reqs_reg[16][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[100][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[4].[0].s_reqs_reg[16][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[100][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[4].[0].s_reqs_reg[16][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[100][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[4].[0].s_reqs_reg[16][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[100][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[4].[0].s_reqs_reg[16][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[100][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[100][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[4].[0].s_reqs_reg[16][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[101][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[4].[1].s_reqs_reg[17][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[101][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[4].[1].s_reqs_reg[17][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[4].[1].s_reqs_reg[17][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[101][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[101][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[101][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[101][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[101][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[101][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[101][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[101][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[101][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[4].[1].s_reqs_reg[17][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[101][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[101][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[101][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[101][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[101][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[101][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[101][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[101][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[101][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[101][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[101][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[101][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[4].[1].s_reqs_reg[17][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[101][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[101][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[101][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[101][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[101][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[4].[1].s_reqs_reg[17][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[101][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[4].[1].s_reqs_reg[17][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[101][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[4].[1].s_reqs_reg[17][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[101][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[4].[1].s_reqs_reg[17][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[101][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[4].[1].s_reqs_reg[17][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[101][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[4].[1].s_reqs_reg[17][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[101][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[101][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[4].[1].s_reqs_reg[17][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[102][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[4].[2].s_reqs_reg[18][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[102][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[4].[2].s_reqs_reg[18][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[4].[2].s_reqs_reg[18][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[102][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[102][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[102][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[102][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[102][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[102][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[102][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[102][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[102][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[4].[2].s_reqs_reg[18][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[102][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[102][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[102][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[102][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[102][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[102][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[102][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[102][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[102][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[102][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[102][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[102][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[4].[2].s_reqs_reg[18][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[102][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[102][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[102][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[102][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[102][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[4].[2].s_reqs_reg[18][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[102][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[4].[2].s_reqs_reg[18][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[102][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[4].[2].s_reqs_reg[18][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[102][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[4].[2].s_reqs_reg[18][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[102][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[4].[2].s_reqs_reg[18][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[102][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[4].[2].s_reqs_reg[18][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[102][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[102][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[4].[2].s_reqs_reg[18][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[103][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[4].[3].s_reqs_reg[19][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[103][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[4].[3].s_reqs_reg[19][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[4].[3].s_reqs_reg[19][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[103][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[103][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[103][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[103][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[103][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[103][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[103][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[103][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[103][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[4].[3].s_reqs_reg[19][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[103][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[103][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[103][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[103][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[103][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[103][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[103][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[103][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[103][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[103][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[103][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[103][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[4].[3].s_reqs_reg[19][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[103][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[103][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[103][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[103][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[103][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[4].[3].s_reqs_reg[19][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[103][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[4].[3].s_reqs_reg[19][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[103][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[4].[3].s_reqs_reg[19][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[103][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[4].[3].s_reqs_reg[19][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[103][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[4].[3].s_reqs_reg[19][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[103][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[4].[3].s_reqs_reg[19][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[103][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[103][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[4].[3].s_reqs_reg[19][value][11]_0 [9]),
- .S(rst_i));
- FDRE \data_rw_o_reg[10][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\data_rw_o_reg_n_0_[10][0] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\data_rw_o_reg_n_0_[10][10] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\data_rw_o_reg_n_0_[10][11] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[10][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[10][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[10][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[10][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[10][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[10][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[10][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[10][19] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\data_rw_o_reg_n_0_[10][1] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[10][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[10][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[10][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[10][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[10][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[10][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[10][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[10][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[10][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[10][29] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\data_rw_o_reg_n_0_[10][2] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[10][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[10][31] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\data_rw_o_reg_n_0_[10][3] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\data_rw_o[10] [4]),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\data_rw_o[10] [5]),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\data_rw_o[10] [6]),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\data_rw_o[10] [7]),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\data_rw_o_reg_n_0_[10][8] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[10][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[10][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\data_rw_o_reg_n_0_[10][9] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\data_rw_o_reg_n_0_[11][0] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\data_rw_o_reg_n_0_[11][10] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\data_rw_o_reg_n_0_[11][11] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[11][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[11][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[11][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[11][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[11][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[11][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[11][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[11][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[11][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\v_dout_reg[7] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[11][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[11][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[11][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[11][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[11][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[11][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[11][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[11][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[11][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[11][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[11][29] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\v_dout_reg[7] [1]),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[11][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[11][31] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\data_rw_o_reg_n_0_[11][3] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\data_rw_o_reg_n_0_[11][4] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\data_rw_o_reg_n_0_[11][5] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\data_rw_o_reg_n_0_[11][6] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\v_dout_reg[7] [2]),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\data_rw_o_reg_n_0_[11][8] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[11][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[11][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\data_rw_o_reg_n_0_[11][9] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[16][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[0].[0].s_reqs_reg[0][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[16][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[0].[0].s_reqs_reg[0][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[0].[0].s_reqs_reg[0][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[16][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[16][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[16][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[16][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[16][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[16][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[16][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[16][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[16][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[0].[0].s_reqs_reg[0][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[16][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[16][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[16][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[16][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[16][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[16][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[16][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[16][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[16][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[16][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[16][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[16][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[0].[0].s_reqs_reg[0][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[16][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[16][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[16][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[16][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[16][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[0].[0].s_reqs_reg[0][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[16][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[0].[0].s_reqs_reg[0][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[16][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[0].[0].s_reqs_reg[0][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[16][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[0].[0].s_reqs_reg[0][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[16][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[0].[0].s_reqs_reg[0][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[16][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[0].[0].s_reqs_reg[0][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[16][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[16][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[0].[0].s_reqs_reg[0][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[17][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[0].[1].s_reqs_reg[1][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[17][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[0].[1].s_reqs_reg[1][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[0].[1].s_reqs_reg[1][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[17][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[17][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[17][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[17][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[17][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[17][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[17][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[17][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[17][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[0].[1].s_reqs_reg[1][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[17][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[17][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[17][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[17][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[17][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[17][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[17][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[17][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[17][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[17][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[17][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[17][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[0].[1].s_reqs_reg[1][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[17][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[17][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[17][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[17][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[17][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[0].[1].s_reqs_reg[1][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[17][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[0].[1].s_reqs_reg[1][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[17][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[0].[1].s_reqs_reg[1][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[17][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[0].[1].s_reqs_reg[1][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[17][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[0].[1].s_reqs_reg[1][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[17][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[0].[1].s_reqs_reg[1][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[17][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[17][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[0].[1].s_reqs_reg[1][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[18][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[0].[2].s_reqs_reg[2][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[18][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[0].[2].s_reqs_reg[2][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[0].[2].s_reqs_reg[2][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[18][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[18][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[18][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[18][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[18][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[18][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[18][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[18][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[18][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[0].[2].s_reqs_reg[2][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[18][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[18][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[18][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[18][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[18][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[18][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[18][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[18][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[18][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[18][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[18][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[18][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[0].[2].s_reqs_reg[2][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[18][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[18][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[18][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[18][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[18][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[0].[2].s_reqs_reg[2][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[18][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[0].[2].s_reqs_reg[2][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[18][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[0].[2].s_reqs_reg[2][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[18][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[0].[2].s_reqs_reg[2][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[18][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[0].[2].s_reqs_reg[2][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[18][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[0].[2].s_reqs_reg[2][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[18][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[18][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[0].[2].s_reqs_reg[2][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[19][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(Q[0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[19][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(Q[10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(Q[11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[19][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[19][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[19][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[19][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[19][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[19][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[19][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[19][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[19][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(Q[1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[19][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[19][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[19][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[19][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[19][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[19][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[19][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[19][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[19][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[19][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[19][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[19][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(Q[2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[19][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[19][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[19][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[19][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[19][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(Q[3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[19][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(Q[4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[19][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(Q[5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[19][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(Q[6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[19][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(Q[7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[19][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(Q[8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[19][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[19][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(Q[9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[20][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[1].[0].s_reqs_reg[4][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[20][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[1].[0].s_reqs_reg[4][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[1].[0].s_reqs_reg[4][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[20][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[20][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[20][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[20][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[20][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[20][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[20][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[20][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[20][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[1].[0].s_reqs_reg[4][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[20][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[20][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[20][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[20][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[20][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[20][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[20][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[20][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[20][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[20][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[20][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[20][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[1].[0].s_reqs_reg[4][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[20][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[20][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[20][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[20][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[20][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[1].[0].s_reqs_reg[4][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[20][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[1].[0].s_reqs_reg[4][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[20][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[1].[0].s_reqs_reg[4][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[20][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[1].[0].s_reqs_reg[4][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[20][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[1].[0].s_reqs_reg[4][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[20][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[1].[0].s_reqs_reg[4][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[20][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[20][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[1].[0].s_reqs_reg[4][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[21][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[1].[1].s_reqs_reg[5][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[21][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[1].[1].s_reqs_reg[5][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[1].[1].s_reqs_reg[5][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[21][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[21][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[21][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[21][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[21][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[21][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[21][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[21][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[21][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[1].[1].s_reqs_reg[5][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[21][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[21][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[21][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[21][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[21][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[21][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[21][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[21][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[21][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[21][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[21][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[21][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[1].[1].s_reqs_reg[5][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[21][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[21][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[21][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[21][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[21][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[1].[1].s_reqs_reg[5][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[21][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[1].[1].s_reqs_reg[5][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[21][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[1].[1].s_reqs_reg[5][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[21][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[1].[1].s_reqs_reg[5][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[21][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[1].[1].s_reqs_reg[5][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[21][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[1].[1].s_reqs_reg[5][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[21][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[21][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[1].[1].s_reqs_reg[5][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[22][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[1].[2].s_reqs_reg[6][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[22][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[1].[2].s_reqs_reg[6][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[1].[2].s_reqs_reg[6][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[22][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[22][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[22][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[22][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[22][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[22][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[22][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[22][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[22][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[1].[2].s_reqs_reg[6][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[22][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[22][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[22][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[22][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[22][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[22][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[22][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[22][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[22][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[22][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[22][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[22][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[1].[2].s_reqs_reg[6][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[22][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[22][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[22][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[22][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[22][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[1].[2].s_reqs_reg[6][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[22][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[1].[2].s_reqs_reg[6][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[22][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[1].[2].s_reqs_reg[6][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[22][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[1].[2].s_reqs_reg[6][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[22][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[1].[2].s_reqs_reg[6][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[22][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[1].[2].s_reqs_reg[6][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[22][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[22][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[1].[2].s_reqs_reg[6][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[23][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[1].[3].s_reqs_reg[7][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[23][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[1].[3].s_reqs_reg[7][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[1].[3].s_reqs_reg[7][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[23][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[23][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[23][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[23][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[23][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[23][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[23][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[23][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[23][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[1].[3].s_reqs_reg[7][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[23][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[23][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[23][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[23][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[23][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[23][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[23][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[23][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[23][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[23][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[23][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[23][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[1].[3].s_reqs_reg[7][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[23][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[23][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[23][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[23][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[23][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[1].[3].s_reqs_reg[7][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[23][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[1].[3].s_reqs_reg[7][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[23][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[1].[3].s_reqs_reg[7][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[23][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[1].[3].s_reqs_reg[7][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[23][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[1].[3].s_reqs_reg[7][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[23][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[1].[3].s_reqs_reg[7][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[23][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[23][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[1].[3].s_reqs_reg[7][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[24][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[2].[0].s_reqs_reg[8][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[24][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[2].[0].s_reqs_reg[8][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[2].[0].s_reqs_reg[8][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[24][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[24][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[24][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[24][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[24][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[24][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[24][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[24][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[24][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[2].[0].s_reqs_reg[8][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[24][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[24][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[24][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[24][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[24][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[24][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[24][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[24][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[24][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[24][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[24][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[24][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[2].[0].s_reqs_reg[8][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[24][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[24][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[24][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[24][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[24][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[2].[0].s_reqs_reg[8][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[24][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[2].[0].s_reqs_reg[8][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[24][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[2].[0].s_reqs_reg[8][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[24][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[2].[0].s_reqs_reg[8][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[24][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[2].[0].s_reqs_reg[8][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[24][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[2].[0].s_reqs_reg[8][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[24][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[24][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[2].[0].s_reqs_reg[8][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[25][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[2].[1].s_reqs_reg[9][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[25][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[2].[1].s_reqs_reg[9][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[2].[1].s_reqs_reg[9][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[25][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[25][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[25][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[25][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[25][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[25][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[25][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[25][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[25][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[2].[1].s_reqs_reg[9][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[25][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[25][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[25][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[25][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[25][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[25][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[25][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[25][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[25][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[25][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[25][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[25][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[2].[1].s_reqs_reg[9][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[25][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[25][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[25][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[25][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[25][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[2].[1].s_reqs_reg[9][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[25][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[2].[1].s_reqs_reg[9][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[25][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[2].[1].s_reqs_reg[9][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[25][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[2].[1].s_reqs_reg[9][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[25][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[2].[1].s_reqs_reg[9][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[25][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[2].[1].s_reqs_reg[9][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[25][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[25][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[2].[1].s_reqs_reg[9][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[26][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[2].[2].s_reqs_reg[10][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[26][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[2].[2].s_reqs_reg[10][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[2].[2].s_reqs_reg[10][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[26][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[26][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[26][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[26][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[26][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[26][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[26][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[26][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[26][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[2].[2].s_reqs_reg[10][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[26][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[26][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[26][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[26][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[26][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[26][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[26][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[26][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[26][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[26][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[26][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[26][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[2].[2].s_reqs_reg[10][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[26][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[26][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[26][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[26][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[26][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[2].[2].s_reqs_reg[10][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[26][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[2].[2].s_reqs_reg[10][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[26][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[2].[2].s_reqs_reg[10][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[26][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[2].[2].s_reqs_reg[10][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[26][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[2].[2].s_reqs_reg[10][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[26][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[2].[2].s_reqs_reg[10][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[26][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[26][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[2].[2].s_reqs_reg[10][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[27][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[2].[3].s_reqs_reg[11][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[27][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[2].[3].s_reqs_reg[11][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[2].[3].s_reqs_reg[11][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[27][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[27][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[27][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[27][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[27][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[27][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[27][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[27][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[27][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[2].[3].s_reqs_reg[11][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[27][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[27][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[27][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[27][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[27][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[27][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[27][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[27][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[27][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[27][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[27][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[27][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[2].[3].s_reqs_reg[11][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[27][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[27][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[27][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[27][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[27][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[2].[3].s_reqs_reg[11][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[27][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[2].[3].s_reqs_reg[11][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[27][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[2].[3].s_reqs_reg[11][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[27][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[2].[3].s_reqs_reg[11][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[27][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[2].[3].s_reqs_reg[11][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[27][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[2].[3].s_reqs_reg[11][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[27][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[27][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[2].[3].s_reqs_reg[11][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[28][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[3].[0].s_reqs_reg[12][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[28][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[3].[0].s_reqs_reg[12][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[3].[0].s_reqs_reg[12][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[28][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[28][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[28][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[28][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[28][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[28][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[28][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[28][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[28][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[3].[0].s_reqs_reg[12][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[28][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[28][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[28][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[28][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[28][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[28][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[28][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[28][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[28][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[28][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[28][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[28][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[3].[0].s_reqs_reg[12][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[28][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[28][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[28][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[28][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[28][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[3].[0].s_reqs_reg[12][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[28][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[3].[0].s_reqs_reg[12][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[28][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[3].[0].s_reqs_reg[12][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[28][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[3].[0].s_reqs_reg[12][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[28][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[3].[0].s_reqs_reg[12][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[28][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[3].[0].s_reqs_reg[12][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[28][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[28][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[3].[0].s_reqs_reg[12][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[29][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[3].[1].s_reqs_reg[13][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[29][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[3].[1].s_reqs_reg[13][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[3].[1].s_reqs_reg[13][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[29][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[29][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[29][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[29][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[29][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[29][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[29][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[29][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[29][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[3].[1].s_reqs_reg[13][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[29][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[29][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[29][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[29][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[29][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[29][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[29][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[29][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[29][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[29][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[29][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[29][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[3].[1].s_reqs_reg[13][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[29][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[29][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[29][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[29][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[29][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[3].[1].s_reqs_reg[13][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[29][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[3].[1].s_reqs_reg[13][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[29][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[3].[1].s_reqs_reg[13][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[29][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[3].[1].s_reqs_reg[13][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[29][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[3].[1].s_reqs_reg[13][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[29][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[3].[1].s_reqs_reg[13][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[29][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[29][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[3].[1].s_reqs_reg[13][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[30][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[3].[2].s_reqs_reg[14][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[30][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[3].[2].s_reqs_reg[14][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[3].[2].s_reqs_reg[14][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[30][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[30][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[30][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[30][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[30][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[30][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[30][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[30][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[30][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[3].[2].s_reqs_reg[14][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[30][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[30][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[30][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[30][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[30][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[30][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[30][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[30][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[30][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[30][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[30][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[30][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[3].[2].s_reqs_reg[14][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[30][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[30][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[30][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[30][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[30][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[3].[2].s_reqs_reg[14][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[30][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[3].[2].s_reqs_reg[14][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[30][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[3].[2].s_reqs_reg[14][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[30][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[3].[2].s_reqs_reg[14][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[30][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[3].[2].s_reqs_reg[14][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[30][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[3].[2].s_reqs_reg[14][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[30][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[30][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[3].[2].s_reqs_reg[14][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[31][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[3].[3].s_reqs_reg[15][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[31][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[3].[3].s_reqs_reg[15][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[3].[3].s_reqs_reg[15][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[31][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[31][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[31][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[31][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[31][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[31][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[31][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[31][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[31][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[3].[3].s_reqs_reg[15][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[31][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[31][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[31][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[31][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[31][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[31][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[31][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[31][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[31][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[31][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[31][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[31][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[3].[3].s_reqs_reg[15][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[31][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[31][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[31][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[31][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[31][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[3].[3].s_reqs_reg[15][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[31][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[3].[3].s_reqs_reg[15][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[31][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[3].[3].s_reqs_reg[15][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[31][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[3].[3].s_reqs_reg[15][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[31][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[3].[3].s_reqs_reg[15][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[31][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[3].[3].s_reqs_reg[15][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[31][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[31][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[3].[3].s_reqs_reg[15][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[32][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[4].[0].s_reqs_reg[16][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[32][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[4].[0].s_reqs_reg[16][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[4].[0].s_reqs_reg[16][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[32][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[32][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[32][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[32][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[32][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[32][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[32][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[32][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[32][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[4].[0].s_reqs_reg[16][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[32][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[32][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[32][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[32][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[32][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[32][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[32][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[32][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[32][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[32][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[32][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[32][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[4].[0].s_reqs_reg[16][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[32][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[32][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[32][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[32][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[32][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[4].[0].s_reqs_reg[16][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[32][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[4].[0].s_reqs_reg[16][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[32][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[4].[0].s_reqs_reg[16][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[32][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[4].[0].s_reqs_reg[16][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[32][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[4].[0].s_reqs_reg[16][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[32][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[4].[0].s_reqs_reg[16][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[32][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[32][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[4].[0].s_reqs_reg[16][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[33][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[4].[1].s_reqs_reg[17][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[33][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[4].[1].s_reqs_reg[17][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[4].[1].s_reqs_reg[17][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[33][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[33][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[33][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[33][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[33][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[33][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[33][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[33][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[33][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[4].[1].s_reqs_reg[17][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[33][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[33][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[33][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[33][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[33][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[33][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[33][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[33][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[33][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[33][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[33][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[33][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[4].[1].s_reqs_reg[17][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[33][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[33][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[33][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[33][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[33][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[4].[1].s_reqs_reg[17][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[33][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[4].[1].s_reqs_reg[17][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[33][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[4].[1].s_reqs_reg[17][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[33][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[4].[1].s_reqs_reg[17][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[33][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[4].[1].s_reqs_reg[17][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[33][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[4].[1].s_reqs_reg[17][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[33][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[33][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[4].[1].s_reqs_reg[17][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[34][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[4].[2].s_reqs_reg[18][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[34][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[4].[2].s_reqs_reg[18][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[4].[2].s_reqs_reg[18][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[34][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[34][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[34][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[34][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[34][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[34][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[34][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[34][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[34][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[4].[2].s_reqs_reg[18][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[34][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[34][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[34][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[34][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[34][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[34][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[34][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[34][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[34][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[34][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[34][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[34][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[4].[2].s_reqs_reg[18][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[34][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[34][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[34][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[34][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[34][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[4].[2].s_reqs_reg[18][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[34][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[4].[2].s_reqs_reg[18][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[34][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[4].[2].s_reqs_reg[18][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[34][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[4].[2].s_reqs_reg[18][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[34][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[4].[2].s_reqs_reg[18][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[34][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[4].[2].s_reqs_reg[18][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[34][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[34][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[4].[2].s_reqs_reg[18][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[35][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[4].[3].s_reqs_reg[19][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[35][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[4].[3].s_reqs_reg[19][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[4].[3].s_reqs_reg[19][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[35][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[35][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[35][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[35][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[35][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[35][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[35][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[35][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[35][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[4].[3].s_reqs_reg[19][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[35][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[35][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[35][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[35][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[35][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[35][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[35][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[35][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[35][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[35][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[35][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[35][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[4].[3].s_reqs_reg[19][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[35][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[35][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[35][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[35][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[35][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[4].[3].s_reqs_reg[19][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[35][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[4].[3].s_reqs_reg[19][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[35][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[4].[3].s_reqs_reg[19][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[35][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[4].[3].s_reqs_reg[19][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[35][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[4].[3].s_reqs_reg[19][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[35][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[4].[3].s_reqs_reg[19][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[35][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[35][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[4].[3].s_reqs_reg[19][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[3][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\data_rw_o[3] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[3][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\data_rw_o_reg_n_0_[3][10] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\data_rw_o_reg_n_0_[3][11] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[3][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[3][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[3][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[3][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[3][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[3][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[3][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[3][19] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\data_rw_o[3] [1]),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[3][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[3][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[3][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[3][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[3][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[3][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[3][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[3][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[3][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[3][29] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\data_rw_o_reg_n_0_[3][2] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[3][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[3][31] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\data_rw_o_reg_n_0_[3][3] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\data_rw_o_reg_n_0_[3][4] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\data_rw_o_reg_n_0_[3][5] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\data_rw_o_reg_n_0_[3][6] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\data_rw_o_reg_n_0_[3][7] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\data_rw_o_reg_n_0_[3][8] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[3][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[3][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\data_rw_o_reg_n_0_[3][9] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\data_rw_o_reg_n_0_[78][0] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\data_rw_o_reg_n_0_[78][10] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\data_rw_o_reg_n_0_[78][11] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[78][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[78][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[78][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[78][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[78][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[78][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[78][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[78][19] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\data_rw_o_reg_n_0_[78][1] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[78][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[78][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[78][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[78][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[78][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[78][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[78][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[78][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[78][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[78][29] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\data_rw_o_reg_n_0_[78][2] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[78][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[78][31] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\data_rw_o_reg_n_0_[78][3] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\data_rw_o[78] [4]),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\data_rw_o[78] [5]),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\data_rw_o[78] [6]),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\data_rw_o[78] [7]),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\data_rw_o_reg_n_0_[78][8] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[78][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[78][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\data_rw_o_reg_n_0_[78][9] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\data_rw_o_reg_n_0_[79][0] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\data_rw_o_reg_n_0_[79][10] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\data_rw_o_reg_n_0_[79][11] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[79][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[79][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[79][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[79][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[79][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[79][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[79][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[79][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[79][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\v_dout_reg[7]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[79][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[79][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[79][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[79][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[79][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[79][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[79][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[79][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[79][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[79][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[79][29] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\v_dout_reg[7]_0 [1]),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[79][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[79][31] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\data_rw_o_reg_n_0_[79][3] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\data_rw_o_reg_n_0_[79][4] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\data_rw_o_reg_n_0_[79][5] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\data_rw_o_reg_n_0_[79][6] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\v_dout_reg[7]_0 [2]),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\data_rw_o_reg_n_0_[79][8] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[79][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[79][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\data_rw_o_reg_n_0_[79][9] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[84][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[0].[0].s_reqs_reg[0][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[84][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[0].[0].s_reqs_reg[0][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[0].[0].s_reqs_reg[0][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[84][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[84][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[84][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[84][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[84][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[84][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[84][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[84][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[84][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[0].[0].s_reqs_reg[0][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[84][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[84][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[84][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[84][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[84][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[84][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[84][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[84][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[84][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[84][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[84][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[84][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[0].[0].s_reqs_reg[0][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[84][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[84][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[84][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[84][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[84][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[0].[0].s_reqs_reg[0][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[84][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[0].[0].s_reqs_reg[0][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[84][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[0].[0].s_reqs_reg[0][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[84][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[0].[0].s_reqs_reg[0][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[84][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[0].[0].s_reqs_reg[0][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[84][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[0].[0].s_reqs_reg[0][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[84][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[84][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[0].[0].s_reqs_reg[0][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[85][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[0].[1].s_reqs_reg[1][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[85][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[0].[1].s_reqs_reg[1][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[0].[1].s_reqs_reg[1][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[85][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[85][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[85][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[85][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[85][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[85][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[85][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[85][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[85][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[0].[1].s_reqs_reg[1][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[85][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[85][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[85][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[85][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[85][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[85][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[85][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[85][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[85][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[85][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[85][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[85][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[0].[1].s_reqs_reg[1][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[85][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[85][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[85][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[85][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[85][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[0].[1].s_reqs_reg[1][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[85][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[0].[1].s_reqs_reg[1][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[85][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[0].[1].s_reqs_reg[1][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[85][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[0].[1].s_reqs_reg[1][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[85][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[0].[1].s_reqs_reg[1][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[85][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[0].[1].s_reqs_reg[1][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[85][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[85][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[0].[1].s_reqs_reg[1][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[86][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[0].[2].s_reqs_reg[2][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[86][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[0].[2].s_reqs_reg[2][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[0].[2].s_reqs_reg[2][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[86][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[86][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[86][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[86][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[86][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[86][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[86][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[86][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[86][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[0].[2].s_reqs_reg[2][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[86][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[86][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[86][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[86][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[86][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[86][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[86][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[86][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[86][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[86][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[86][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[86][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[0].[2].s_reqs_reg[2][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[86][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[86][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[86][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[86][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[86][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[0].[2].s_reqs_reg[2][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[86][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[0].[2].s_reqs_reg[2][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[86][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[0].[2].s_reqs_reg[2][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[86][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[0].[2].s_reqs_reg[2][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[86][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[0].[2].s_reqs_reg[2][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[86][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[0].[2].s_reqs_reg[2][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[86][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[86][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[0].[2].s_reqs_reg[2][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[87][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[0].[3].s_reqs_reg[3][value][11] [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[87][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[0].[3].s_reqs_reg[3][value][11] [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[0].[3].s_reqs_reg[3][value][11] [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[87][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[87][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[87][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[87][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[87][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[87][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[87][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[87][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[87][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[0].[3].s_reqs_reg[3][value][11] [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[87][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[87][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[87][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[87][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[87][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[87][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[87][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[87][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[87][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[87][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[87][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[87][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[0].[3].s_reqs_reg[3][value][11] [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[87][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[87][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[87][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[87][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[87][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[0].[3].s_reqs_reg[3][value][11] [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[87][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[0].[3].s_reqs_reg[3][value][11] [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[87][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[0].[3].s_reqs_reg[3][value][11] [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[87][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[0].[3].s_reqs_reg[3][value][11] [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[87][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[0].[3].s_reqs_reg[3][value][11] [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[87][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[0].[3].s_reqs_reg[3][value][11] [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[87][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[87][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[0].[3].s_reqs_reg[3][value][11] [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[88][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[1].[0].s_reqs_reg[4][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[88][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[1].[0].s_reqs_reg[4][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[1].[0].s_reqs_reg[4][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[88][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[88][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[88][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[88][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[88][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[88][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[88][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[88][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[88][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[1].[0].s_reqs_reg[4][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[88][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[88][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[88][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[88][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[88][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[88][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[88][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[88][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[88][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[88][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[88][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[88][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[1].[0].s_reqs_reg[4][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[88][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[88][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[88][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[88][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[88][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[1].[0].s_reqs_reg[4][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[88][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[1].[0].s_reqs_reg[4][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[88][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[1].[0].s_reqs_reg[4][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[88][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[1].[0].s_reqs_reg[4][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[88][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[1].[0].s_reqs_reg[4][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[88][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[1].[0].s_reqs_reg[4][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[88][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[88][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[1].[0].s_reqs_reg[4][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[89][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[1].[1].s_reqs_reg[5][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[89][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[1].[1].s_reqs_reg[5][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[1].[1].s_reqs_reg[5][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[89][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[89][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[89][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[89][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[89][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[89][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[89][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[89][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[89][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[1].[1].s_reqs_reg[5][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[89][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[89][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[89][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[89][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[89][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[89][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[89][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[89][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[89][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[89][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[89][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[89][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[1].[1].s_reqs_reg[5][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[89][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[89][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[89][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[89][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[89][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[1].[1].s_reqs_reg[5][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[89][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[1].[1].s_reqs_reg[5][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[89][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[1].[1].s_reqs_reg[5][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[89][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[1].[1].s_reqs_reg[5][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[89][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[1].[1].s_reqs_reg[5][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[89][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[1].[1].s_reqs_reg[5][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[89][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[89][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[1].[1].s_reqs_reg[5][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[90][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[1].[2].s_reqs_reg[6][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[90][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[1].[2].s_reqs_reg[6][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[1].[2].s_reqs_reg[6][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[90][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[90][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[90][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[90][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[90][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[90][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[90][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[90][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[90][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[1].[2].s_reqs_reg[6][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[90][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[90][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[90][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[90][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[90][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[90][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[90][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[90][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[90][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[90][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[90][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[90][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[1].[2].s_reqs_reg[6][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[90][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[90][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[90][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[90][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[90][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[1].[2].s_reqs_reg[6][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[90][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[1].[2].s_reqs_reg[6][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[90][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[1].[2].s_reqs_reg[6][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[90][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[1].[2].s_reqs_reg[6][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[90][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[1].[2].s_reqs_reg[6][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[90][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[1].[2].s_reqs_reg[6][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[90][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[90][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[1].[2].s_reqs_reg[6][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[91][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[1].[3].s_reqs_reg[7][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[91][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[1].[3].s_reqs_reg[7][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[1].[3].s_reqs_reg[7][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[91][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[91][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[91][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[91][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[91][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[91][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[91][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[91][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[91][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[1].[3].s_reqs_reg[7][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[91][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[91][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[91][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[91][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[91][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[91][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[91][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[91][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[91][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[91][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[91][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[91][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[1].[3].s_reqs_reg[7][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[91][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[91][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[91][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[91][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[91][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[1].[3].s_reqs_reg[7][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[91][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[1].[3].s_reqs_reg[7][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[91][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[1].[3].s_reqs_reg[7][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[91][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[1].[3].s_reqs_reg[7][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[91][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[1].[3].s_reqs_reg[7][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[91][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[1].[3].s_reqs_reg[7][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[91][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[91][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[1].[3].s_reqs_reg[7][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[92][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[2].[0].s_reqs_reg[8][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[92][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[2].[0].s_reqs_reg[8][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[2].[0].s_reqs_reg[8][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[92][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[92][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[92][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[92][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[92][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[92][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[92][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[92][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[92][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[2].[0].s_reqs_reg[8][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[92][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[92][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[92][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[92][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[92][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[92][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[92][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[92][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[92][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[92][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[92][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[92][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[2].[0].s_reqs_reg[8][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[92][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[92][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[92][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[92][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[92][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[2].[0].s_reqs_reg[8][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[92][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[2].[0].s_reqs_reg[8][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[92][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[2].[0].s_reqs_reg[8][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[92][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[2].[0].s_reqs_reg[8][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[92][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[2].[0].s_reqs_reg[8][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[92][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[2].[0].s_reqs_reg[8][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[92][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[92][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[2].[0].s_reqs_reg[8][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[93][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[2].[1].s_reqs_reg[9][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[93][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[2].[1].s_reqs_reg[9][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[2].[1].s_reqs_reg[9][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[93][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[93][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[93][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[93][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[93][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[93][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[93][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[93][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[93][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[2].[1].s_reqs_reg[9][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[93][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[93][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[93][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[93][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[93][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[93][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[93][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[93][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[93][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[93][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[93][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[93][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[2].[1].s_reqs_reg[9][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[93][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[93][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[93][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[93][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[93][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[2].[1].s_reqs_reg[9][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[93][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[2].[1].s_reqs_reg[9][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[93][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[2].[1].s_reqs_reg[9][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[93][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[2].[1].s_reqs_reg[9][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[93][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[2].[1].s_reqs_reg[9][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[93][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[2].[1].s_reqs_reg[9][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[93][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[93][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[2].[1].s_reqs_reg[9][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[94][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[2].[2].s_reqs_reg[10][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[94][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[2].[2].s_reqs_reg[10][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[2].[2].s_reqs_reg[10][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[94][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[94][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[94][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[94][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[94][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[94][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[94][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[94][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[94][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[2].[2].s_reqs_reg[10][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[94][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[94][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[94][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[94][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[94][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[94][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[94][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[94][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[94][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[94][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[94][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[94][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[2].[2].s_reqs_reg[10][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[94][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[94][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[94][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[94][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[94][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[2].[2].s_reqs_reg[10][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[94][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[2].[2].s_reqs_reg[10][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[94][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[2].[2].s_reqs_reg[10][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[94][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[2].[2].s_reqs_reg[10][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[94][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[2].[2].s_reqs_reg[10][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[94][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[2].[2].s_reqs_reg[10][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[94][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[94][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[2].[2].s_reqs_reg[10][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[95][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[2].[3].s_reqs_reg[11][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[95][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[2].[3].s_reqs_reg[11][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[2].[3].s_reqs_reg[11][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[95][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[95][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[95][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[95][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[95][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[95][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[95][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[95][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[95][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[2].[3].s_reqs_reg[11][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[95][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[95][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[95][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[95][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[95][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[95][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[95][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[95][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[95][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[95][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[95][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[95][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[2].[3].s_reqs_reg[11][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[95][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[95][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[95][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[95][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[95][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[2].[3].s_reqs_reg[11][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[95][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[2].[3].s_reqs_reg[11][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[95][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[2].[3].s_reqs_reg[11][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[95][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[2].[3].s_reqs_reg[11][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[95][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[2].[3].s_reqs_reg[11][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[95][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[2].[3].s_reqs_reg[11][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[95][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[95][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[2].[3].s_reqs_reg[11][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[96][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[3].[0].s_reqs_reg[12][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[96][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[3].[0].s_reqs_reg[12][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[3].[0].s_reqs_reg[12][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[96][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[96][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[96][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[96][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[96][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[96][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[96][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[96][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[96][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[3].[0].s_reqs_reg[12][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[96][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[96][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[96][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[96][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[96][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[96][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[96][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[96][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[96][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[96][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[96][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[96][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[3].[0].s_reqs_reg[12][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[96][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[96][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[96][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[96][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[96][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[3].[0].s_reqs_reg[12][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[96][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[3].[0].s_reqs_reg[12][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[96][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[3].[0].s_reqs_reg[12][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[96][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[3].[0].s_reqs_reg[12][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[96][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[3].[0].s_reqs_reg[12][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[96][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[3].[0].s_reqs_reg[12][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[96][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[96][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[3].[0].s_reqs_reg[12][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[97][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[3].[1].s_reqs_reg[13][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[97][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[3].[1].s_reqs_reg[13][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[3].[1].s_reqs_reg[13][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[97][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[97][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[97][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[97][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[97][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[97][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[97][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[97][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[97][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[3].[1].s_reqs_reg[13][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[97][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[97][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[97][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[97][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[97][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[97][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[97][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[97][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[97][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[97][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[97][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[97][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[3].[1].s_reqs_reg[13][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[97][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[97][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[97][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[97][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[97][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[3].[1].s_reqs_reg[13][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[97][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[3].[1].s_reqs_reg[13][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[97][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[3].[1].s_reqs_reg[13][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[97][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[3].[1].s_reqs_reg[13][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[97][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[3].[1].s_reqs_reg[13][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[97][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[3].[1].s_reqs_reg[13][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[97][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[97][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[3].[1].s_reqs_reg[13][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[98][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[3].[2].s_reqs_reg[14][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[98][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[3].[2].s_reqs_reg[14][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[3].[2].s_reqs_reg[14][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[98][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[98][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[98][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[98][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[98][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[98][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[98][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[98][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[98][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[3].[2].s_reqs_reg[14][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[98][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[98][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[98][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[98][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[98][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[98][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[98][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[98][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[98][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[98][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[98][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[98][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[3].[2].s_reqs_reg[14][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[98][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[98][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[98][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[98][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[98][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[3].[2].s_reqs_reg[14][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[98][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[3].[2].s_reqs_reg[14][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[98][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[3].[2].s_reqs_reg[14][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[98][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[3].[2].s_reqs_reg[14][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[98][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[3].[2].s_reqs_reg[14][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[98][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[3].[2].s_reqs_reg[14][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[98][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[98][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[3].[2].s_reqs_reg[14][value][11]_0 [9]),
- .S(rst_i));
- FDSE \data_rw_o_reg[99][0]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][7]_i_1_n_0 ),
- .D(s00_axi_wdata[0]),
- .Q(\[3].[3].s_reqs_reg[15][value][11]_0 [0]),
- .S(rst_i));
- FDRE \data_rw_o_reg[99][10]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][15]_i_1_n_0 ),
- .D(s00_axi_wdata[10]),
- .Q(\[3].[3].s_reqs_reg[15][value][11]_0 [10]),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][11]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][15]_i_1_n_0 ),
- .D(s00_axi_wdata[11]),
- .Q(\[3].[3].s_reqs_reg[15][value][11]_0 [11]),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][12]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][15]_i_1_n_0 ),
- .D(s00_axi_wdata[12]),
- .Q(\data_rw_o_reg_n_0_[99][12] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][13]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][15]_i_1_n_0 ),
- .D(s00_axi_wdata[13]),
- .Q(\data_rw_o_reg_n_0_[99][13] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][14]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][15]_i_1_n_0 ),
- .D(s00_axi_wdata[14]),
- .Q(\data_rw_o_reg_n_0_[99][14] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][15]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][15]_i_1_n_0 ),
- .D(s00_axi_wdata[15]),
- .Q(\data_rw_o_reg_n_0_[99][15] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][16]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][23]_i_1_n_0 ),
- .D(s00_axi_wdata[16]),
- .Q(\data_rw_o_reg_n_0_[99][16] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][17]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][23]_i_1_n_0 ),
- .D(s00_axi_wdata[17]),
- .Q(\data_rw_o_reg_n_0_[99][17] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][18]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][23]_i_1_n_0 ),
- .D(s00_axi_wdata[18]),
- .Q(\data_rw_o_reg_n_0_[99][18] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][19]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][23]_i_1_n_0 ),
- .D(s00_axi_wdata[19]),
- .Q(\data_rw_o_reg_n_0_[99][19] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[99][1]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][7]_i_1_n_0 ),
- .D(s00_axi_wdata[1]),
- .Q(\[3].[3].s_reqs_reg[15][value][11]_0 [1]),
- .S(rst_i));
- FDRE \data_rw_o_reg[99][20]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][23]_i_1_n_0 ),
- .D(s00_axi_wdata[20]),
- .Q(\data_rw_o_reg_n_0_[99][20] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][21]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][23]_i_1_n_0 ),
- .D(s00_axi_wdata[21]),
- .Q(\data_rw_o_reg_n_0_[99][21] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][22]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][23]_i_1_n_0 ),
- .D(s00_axi_wdata[22]),
- .Q(\data_rw_o_reg_n_0_[99][22] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][23]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][23]_i_1_n_0 ),
- .D(s00_axi_wdata[23]),
- .Q(\data_rw_o_reg_n_0_[99][23] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][24]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][31]_i_1_n_0 ),
- .D(s00_axi_wdata[24]),
- .Q(\data_rw_o_reg_n_0_[99][24] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][25]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][31]_i_1_n_0 ),
- .D(s00_axi_wdata[25]),
- .Q(\data_rw_o_reg_n_0_[99][25] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][26]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][31]_i_1_n_0 ),
- .D(s00_axi_wdata[26]),
- .Q(\data_rw_o_reg_n_0_[99][26] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][27]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][31]_i_1_n_0 ),
- .D(s00_axi_wdata[27]),
- .Q(\data_rw_o_reg_n_0_[99][27] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][28]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][31]_i_1_n_0 ),
- .D(s00_axi_wdata[28]),
- .Q(\data_rw_o_reg_n_0_[99][28] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][29]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][31]_i_1_n_0 ),
- .D(s00_axi_wdata[29]),
- .Q(\data_rw_o_reg_n_0_[99][29] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[99][2]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][7]_i_1_n_0 ),
- .D(s00_axi_wdata[2]),
- .Q(\[3].[3].s_reqs_reg[15][value][11]_0 [2]),
- .S(rst_i));
- FDRE \data_rw_o_reg[99][30]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][31]_i_1_n_0 ),
- .D(s00_axi_wdata[30]),
- .Q(\data_rw_o_reg_n_0_[99][30] ),
- .R(rst_i));
- FDRE \data_rw_o_reg[99][31]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][31]_i_1_n_0 ),
- .D(s00_axi_wdata[31]),
- .Q(\data_rw_o_reg_n_0_[99][31] ),
- .R(rst_i));
- FDSE \data_rw_o_reg[99][3]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][7]_i_1_n_0 ),
- .D(s00_axi_wdata[3]),
- .Q(\[3].[3].s_reqs_reg[15][value][11]_0 [3]),
- .S(rst_i));
- FDSE \data_rw_o_reg[99][4]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][7]_i_1_n_0 ),
- .D(s00_axi_wdata[4]),
- .Q(\[3].[3].s_reqs_reg[15][value][11]_0 [4]),
- .S(rst_i));
- FDSE \data_rw_o_reg[99][5]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][7]_i_1_n_0 ),
- .D(s00_axi_wdata[5]),
- .Q(\[3].[3].s_reqs_reg[15][value][11]_0 [5]),
- .S(rst_i));
- FDSE \data_rw_o_reg[99][6]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][7]_i_1_n_0 ),
- .D(s00_axi_wdata[6]),
- .Q(\[3].[3].s_reqs_reg[15][value][11]_0 [6]),
- .S(rst_i));
- FDSE \data_rw_o_reg[99][7]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][7]_i_1_n_0 ),
- .D(s00_axi_wdata[7]),
- .Q(\[3].[3].s_reqs_reg[15][value][11]_0 [7]),
- .S(rst_i));
- FDSE \data_rw_o_reg[99][8]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][15]_i_1_n_0 ),
- .D(s00_axi_wdata[8]),
- .Q(\[3].[3].s_reqs_reg[15][value][11]_0 [8]),
- .S(rst_i));
- FDSE \data_rw_o_reg[99][9]
- (.C(s00_axi_aclk),
- .CE(\data_rw_o[99][15]_i_1_n_0 ),
- .D(s00_axi_wdata[9]),
- .Q(\[3].[3].s_reqs_reg[15][value][11]_0 [9]),
- .S(rst_i));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT4 #(
- .INIT(16'h4777))
- dig_out6_n_INST_0
- (.I0(\s_ins_reg[3] [0]),
- .I1(\data_rw_o[3] [0]),
- .I2(\data_rw_o[3] [1]),
- .I3(s_tick),
- .O(dig_out6_n));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT4 #(
- .INIT(16'hF808))
- \dig_outs_i[0]_INST_0
- (.I0(s_tick),
- .I1(\data_rw_o[3] [1]),
- .I2(\data_rw_o[3] [0]),
- .I3(\s_ins_reg[3] [0]),
- .O(dig_outs_i));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
- LUT2 #(
- .INIT(4'h2))
- \v_dout[4]_i_1
- (.I0(\data_rw_o[10] [4]),
- .I1(\v_dout_reg[7] [2]),
- .O(\v_dout_reg[4] ));
- (* SOFT_HLUTNM = "soft_lutpair35" *)
- LUT2 #(
- .INIT(4'h2))
- \v_dout[4]_i_1__0
- (.I0(\data_rw_o[78] [4]),
- .I1(\v_dout_reg[7]_0 [2]),
- .O(\v_dout_reg[4]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair33" *)
- LUT2 #(
- .INIT(4'h2))
- \v_dout[5]_i_1
- (.I0(\data_rw_o[10] [5]),
- .I1(\v_dout_reg[7] [2]),
- .O(\v_dout_reg[5] ));
- (* SOFT_HLUTNM = "soft_lutpair35" *)
- LUT2 #(
- .INIT(4'h2))
- \v_dout[5]_i_1__0
- (.I0(\data_rw_o[78] [5]),
- .I1(\v_dout_reg[7]_0 [2]),
- .O(\v_dout_reg[5]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
- LUT2 #(
- .INIT(4'h2))
- \v_dout[6]_i_1
- (.I0(\data_rw_o[10] [6]),
- .I1(\v_dout_reg[7] [2]),
- .O(\v_dout_reg[6] ));
- (* SOFT_HLUTNM = "soft_lutpair34" *)
- LUT2 #(
- .INIT(4'h2))
- \v_dout[6]_i_1__0
- (.I0(\data_rw_o[78] [6]),
- .I1(\v_dout_reg[7]_0 [2]),
- .O(\v_dout_reg[6]_0 ));
- (* SOFT_HLUTNM = "soft_lutpair32" *)
- LUT2 #(
- .INIT(4'h2))
- \v_dout[7]_i_2
- (.I0(\data_rw_o[10] [7]),
- .I1(\v_dout_reg[7] [2]),
- .O(\v_dout_reg[7]_1 ));
- (* SOFT_HLUTNM = "soft_lutpair34" *)
- LUT2 #(
- .INIT(4'h2))
- \v_dout[7]_i_2__0
- (.I0(\data_rw_o[78] [7]),
- .I1(\v_dout_reg[7]_0 [2]),
- .O(\v_dout_reg[7]_2 ));
-endmodule
-
-(* ORIG_REF_NAME = "clockDivider" *)
-module system_design_fasec_hwtest_0_0_clockDivider
- (watchdog_pl_o,
- ps_clk_i,
- rst_i);
- output watchdog_pl_o;
- input ps_clk_i;
- input rst_i;
-
- wire I;
- wire [31:1]data0;
- wire ps_clk_i;
- wire rst_i;
- wire [31:0]s_counter;
- wire \s_counter[31]_i_10_n_0 ;
- wire \s_counter[31]_i_2_n_0 ;
- wire \s_counter[31]_i_3_n_0 ;
- wire \s_counter[31]_i_4_n_0 ;
- wire \s_counter[31]_i_5_n_0 ;
- wire \s_counter[31]_i_7_n_0 ;
- wire \s_counter[31]_i_8_n_0 ;
- wire \s_counter[31]_i_9_n_0 ;
- wire [31:0]s_counter_0;
- wire \s_counter_reg[12]_i_2_n_0 ;
- wire \s_counter_reg[12]_i_2_n_1 ;
- wire \s_counter_reg[12]_i_2_n_2 ;
- wire \s_counter_reg[12]_i_2_n_3 ;
- wire \s_counter_reg[16]_i_2_n_0 ;
- wire \s_counter_reg[16]_i_2_n_1 ;
- wire \s_counter_reg[16]_i_2_n_2 ;
- wire \s_counter_reg[16]_i_2_n_3 ;
- wire \s_counter_reg[20]_i_2_n_0 ;
- wire \s_counter_reg[20]_i_2_n_1 ;
- wire \s_counter_reg[20]_i_2_n_2 ;
- wire \s_counter_reg[20]_i_2_n_3 ;
- wire \s_counter_reg[24]_i_2_n_0 ;
- wire \s_counter_reg[24]_i_2_n_1 ;
- wire \s_counter_reg[24]_i_2_n_2 ;
- wire \s_counter_reg[24]_i_2_n_3 ;
- wire \s_counter_reg[28]_i_2_n_0 ;
- wire \s_counter_reg[28]_i_2_n_1 ;
- wire \s_counter_reg[28]_i_2_n_2 ;
- wire \s_counter_reg[28]_i_2_n_3 ;
- wire \s_counter_reg[31]_i_6_n_2 ;
- wire \s_counter_reg[31]_i_6_n_3 ;
- wire \s_counter_reg[4]_i_2_n_0 ;
- wire \s_counter_reg[4]_i_2_n_1 ;
- wire \s_counter_reg[4]_i_2_n_2 ;
- wire \s_counter_reg[4]_i_2_n_3 ;
- wire \s_counter_reg[8]_i_2_n_0 ;
- wire \s_counter_reg[8]_i_2_n_1 ;
- wire \s_counter_reg[8]_i_2_n_2 ;
- wire \s_counter_reg[8]_i_2_n_3 ;
- wire s_temp_i_1_n_0;
- wire watchdog_pl_o;
- wire [3:2]\NLW_s_counter_reg[31]_i_6_CO_UNCONNECTED ;
- wire [3:3]\NLW_s_counter_reg[31]_i_6_O_UNCONNECTED ;
-
- (* box_type = "PRIMITIVE" *)
- BUFG cmp_BUFG
- (.I(I),
- .O(watchdog_pl_o));
- LUT1 #(
- .INIT(2'h1))
- \s_counter[0]_i_1__1
- (.I0(s_counter[0]),
- .O(s_counter_0[0]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[10]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[10]),
- .O(s_counter_0[10]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[11]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[11]),
- .O(s_counter_0[11]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[12]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[12]),
- .O(s_counter_0[12]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[13]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[13]),
- .O(s_counter_0[13]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[14]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[14]),
- .O(s_counter_0[14]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[15]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[15]),
- .O(s_counter_0[15]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[16]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[16]),
- .O(s_counter_0[16]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[17]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[17]),
- .O(s_counter_0[17]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[18]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[18]),
- .O(s_counter_0[18]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[19]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[19]),
- .O(s_counter_0[19]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[1]_i_1__1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[1]),
- .O(s_counter_0[1]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[20]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[20]),
- .O(s_counter_0[20]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[21]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[21]),
- .O(s_counter_0[21]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[22]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[22]),
- .O(s_counter_0[22]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[23]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[23]),
- .O(s_counter_0[23]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[24]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[24]),
- .O(s_counter_0[24]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[25]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[25]),
- .O(s_counter_0[25]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[26]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[26]),
- .O(s_counter_0[26]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[27]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[27]),
- .O(s_counter_0[27]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[28]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[28]),
- .O(s_counter_0[28]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[29]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[29]),
- .O(s_counter_0[29]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[2]_i_1__1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[2]),
- .O(s_counter_0[2]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[30]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[30]),
- .O(s_counter_0[30]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[31]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[31]),
- .O(s_counter_0[31]));
- LUT4 #(
- .INIT(16'hFFFE))
- \s_counter[31]_i_10
- (.I0(s_counter[21]),
- .I1(s_counter[20]),
- .I2(s_counter[23]),
- .I3(s_counter[22]),
- .O(\s_counter[31]_i_10_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- \s_counter[31]_i_2
- (.I0(s_counter[11]),
- .I1(s_counter[10]),
- .I2(s_counter[8]),
- .I3(s_counter[9]),
- .I4(\s_counter[31]_i_7_n_0 ),
- .O(\s_counter[31]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF7FFF))
- \s_counter[31]_i_3
- (.I0(s_counter[2]),
- .I1(s_counter[3]),
- .I2(s_counter[0]),
- .I3(s_counter[1]),
- .I4(\s_counter[31]_i_8_n_0 ),
- .O(\s_counter[31]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \s_counter[31]_i_4
- (.I0(s_counter[26]),
- .I1(s_counter[27]),
- .I2(s_counter[24]),
- .I3(s_counter[25]),
- .I4(\s_counter[31]_i_9_n_0 ),
- .O(\s_counter[31]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFFEFF))
- \s_counter[31]_i_5
- (.I0(s_counter[18]),
- .I1(s_counter[19]),
- .I2(s_counter[17]),
- .I3(s_counter[16]),
- .I4(\s_counter[31]_i_10_n_0 ),
- .O(\s_counter[31]_i_5_n_0 ));
- LUT4 #(
- .INIT(16'hFFEF))
- \s_counter[31]_i_7
- (.I0(s_counter[13]),
- .I1(s_counter[12]),
- .I2(s_counter[15]),
- .I3(s_counter[14]),
- .O(\s_counter[31]_i_7_n_0 ));
- LUT4 #(
- .INIT(16'hFFDF))
- \s_counter[31]_i_8
- (.I0(s_counter[4]),
- .I1(s_counter[5]),
- .I2(s_counter[7]),
- .I3(s_counter[6]),
- .O(\s_counter[31]_i_8_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \s_counter[31]_i_9
- (.I0(s_counter[29]),
- .I1(s_counter[28]),
- .I2(s_counter[31]),
- .I3(s_counter[30]),
- .O(\s_counter[31]_i_9_n_0 ));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[3]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[3]),
- .O(s_counter_0[3]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[4]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[4]),
- .O(s_counter_0[4]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[5]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[5]),
- .O(s_counter_0[5]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[6]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[6]),
- .O(s_counter_0[6]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[7]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[7]),
- .O(s_counter_0[7]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[8]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[8]),
- .O(s_counter_0[8]));
- LUT5 #(
- .INIT(32'hFFFE0000))
- \s_counter[9]_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(data0[9]),
- .O(s_counter_0[9]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[0]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[0]),
- .Q(s_counter[0]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[10]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[10]),
- .Q(s_counter[10]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[11]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[11]),
- .Q(s_counter[11]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[12]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[12]),
- .Q(s_counter[12]));
- CARRY4 \s_counter_reg[12]_i_2
- (.CI(\s_counter_reg[8]_i_2_n_0 ),
- .CO({\s_counter_reg[12]_i_2_n_0 ,\s_counter_reg[12]_i_2_n_1 ,\s_counter_reg[12]_i_2_n_2 ,\s_counter_reg[12]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(data0[12:9]),
- .S(s_counter[12:9]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[13]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[13]),
- .Q(s_counter[13]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[14]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[14]),
- .Q(s_counter[14]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[15]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[15]),
- .Q(s_counter[15]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[16]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[16]),
- .Q(s_counter[16]));
- CARRY4 \s_counter_reg[16]_i_2
- (.CI(\s_counter_reg[12]_i_2_n_0 ),
- .CO({\s_counter_reg[16]_i_2_n_0 ,\s_counter_reg[16]_i_2_n_1 ,\s_counter_reg[16]_i_2_n_2 ,\s_counter_reg[16]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(data0[16:13]),
- .S(s_counter[16:13]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[17]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[17]),
- .Q(s_counter[17]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[18]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[18]),
- .Q(s_counter[18]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[19]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[19]),
- .Q(s_counter[19]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[1]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[1]),
- .Q(s_counter[1]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[20]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[20]),
- .Q(s_counter[20]));
- CARRY4 \s_counter_reg[20]_i_2
- (.CI(\s_counter_reg[16]_i_2_n_0 ),
- .CO({\s_counter_reg[20]_i_2_n_0 ,\s_counter_reg[20]_i_2_n_1 ,\s_counter_reg[20]_i_2_n_2 ,\s_counter_reg[20]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(data0[20:17]),
- .S(s_counter[20:17]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[21]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[21]),
- .Q(s_counter[21]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[22]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[22]),
- .Q(s_counter[22]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[23]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[23]),
- .Q(s_counter[23]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[24]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[24]),
- .Q(s_counter[24]));
- CARRY4 \s_counter_reg[24]_i_2
- (.CI(\s_counter_reg[20]_i_2_n_0 ),
- .CO({\s_counter_reg[24]_i_2_n_0 ,\s_counter_reg[24]_i_2_n_1 ,\s_counter_reg[24]_i_2_n_2 ,\s_counter_reg[24]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(data0[24:21]),
- .S(s_counter[24:21]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[25]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[25]),
- .Q(s_counter[25]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[26]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[26]),
- .Q(s_counter[26]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[27]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[27]),
- .Q(s_counter[27]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[28]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[28]),
- .Q(s_counter[28]));
- CARRY4 \s_counter_reg[28]_i_2
- (.CI(\s_counter_reg[24]_i_2_n_0 ),
- .CO({\s_counter_reg[28]_i_2_n_0 ,\s_counter_reg[28]_i_2_n_1 ,\s_counter_reg[28]_i_2_n_2 ,\s_counter_reg[28]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(data0[28:25]),
- .S(s_counter[28:25]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[29]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[29]),
- .Q(s_counter[29]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[2]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[2]),
- .Q(s_counter[2]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[30]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[30]),
- .Q(s_counter[30]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[31]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[31]),
- .Q(s_counter[31]));
- CARRY4 \s_counter_reg[31]_i_6
- (.CI(\s_counter_reg[28]_i_2_n_0 ),
- .CO({\NLW_s_counter_reg[31]_i_6_CO_UNCONNECTED [3:2],\s_counter_reg[31]_i_6_n_2 ,\s_counter_reg[31]_i_6_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\NLW_s_counter_reg[31]_i_6_O_UNCONNECTED [3],data0[31:29]}),
- .S({1'b0,s_counter[31:29]}));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[3]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[3]),
- .Q(s_counter[3]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[4]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[4]),
- .Q(s_counter[4]));
- CARRY4 \s_counter_reg[4]_i_2
- (.CI(1'b0),
- .CO({\s_counter_reg[4]_i_2_n_0 ,\s_counter_reg[4]_i_2_n_1 ,\s_counter_reg[4]_i_2_n_2 ,\s_counter_reg[4]_i_2_n_3 }),
- .CYINIT(s_counter[0]),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(data0[4:1]),
- .S(s_counter[4:1]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[5]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[5]),
- .Q(s_counter[5]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[6]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[6]),
- .Q(s_counter[6]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[7]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[7]),
- .Q(s_counter[7]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[8]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[8]),
- .Q(s_counter[8]));
- CARRY4 \s_counter_reg[8]_i_2
- (.CI(\s_counter_reg[4]_i_2_n_0 ),
- .CO({\s_counter_reg[8]_i_2_n_0 ,\s_counter_reg[8]_i_2_n_1 ,\s_counter_reg[8]_i_2_n_2 ,\s_counter_reg[8]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O(data0[8:5]),
- .S(s_counter[8:5]));
- FDCE #(
- .INIT(1'b0))
- \s_counter_reg[9]
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_counter_0[9]),
- .Q(s_counter[9]));
- LUT5 #(
- .INIT(32'hFFFE0001))
- s_temp_i_1
- (.I0(\s_counter[31]_i_2_n_0 ),
- .I1(\s_counter[31]_i_3_n_0 ),
- .I2(\s_counter[31]_i_4_n_0 ),
- .I3(\s_counter[31]_i_5_n_0 ),
- .I4(I),
- .O(s_temp_i_1_n_0));
- FDCE #(
- .INIT(1'b1))
- s_temp_reg
- (.C(ps_clk_i),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_temp_i_1_n_0),
- .Q(I));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_147
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_150
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_153
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_156
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_159
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_162
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_165
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_168
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_171
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_174
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_177
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_180
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_183
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_186
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_189
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_192
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_195
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_198
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_201
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_204
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_44
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_47
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_50
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_53
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_56
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_59
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_62
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_65
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_68
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_71
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_74
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_77
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_80
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_83
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_86
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_89
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_92
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_95
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown_98
- (count_o,
- s_buff2_reg,
- s00_axi_aclk,
- E);
- output [23:0]count_o;
- input s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]E;
-
- wire [0:0]E;
- wire [23:0]count_o;
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:24]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_buff2_reg),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:24],count_o}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(E),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__54_n_0;
- wire s_pulseLed_i_2__54_n_0;
- wire s_pulseLed_i_3__54_n_0;
- wire s_pulseLed_i_4__54_n_0;
- wire s_pulseLed_i_5__54_n_0;
- wire s_pulseLed_i_7__54_n_0;
- wire s_pulseLed_i_8__54_n_0;
- wire s_pulseLed_i_9__54_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__54
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__54_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__54
- (.I0(s_pulseLed_i_2__54_n_0),
- .I1(s_pulseLed_i_3__54_n_0),
- .I2(s_pulseLed_i_4__54_n_0),
- .I3(s_pulseLed_i_5__54_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__54
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__54_n_0),
- .O(s_pulseLed_i_2__54_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__54
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__54_n_0),
- .O(s_pulseLed_i_3__54_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__54
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__54_n_0),
- .O(s_pulseLed_i_4__54_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__54
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__54_n_0),
- .O(s_pulseLed_i_5__54_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__54
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__54_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__54
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__54_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__54
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__54_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_131
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__26_n_0;
- wire s_pulseLed_i_2__26_n_0;
- wire s_pulseLed_i_3__26_n_0;
- wire s_pulseLed_i_4__26_n_0;
- wire s_pulseLed_i_5__26_n_0;
- wire s_pulseLed_i_7__26_n_0;
- wire s_pulseLed_i_8__26_n_0;
- wire s_pulseLed_i_9__26_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__26
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__26_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__26
- (.I0(s_pulseLed_i_2__26_n_0),
- .I1(s_pulseLed_i_3__26_n_0),
- .I2(s_pulseLed_i_4__26_n_0),
- .I3(s_pulseLed_i_5__26_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__26
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__26_n_0),
- .O(s_pulseLed_i_2__26_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__26
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__26_n_0),
- .O(s_pulseLed_i_3__26_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__26
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__26_n_0),
- .O(s_pulseLed_i_4__26_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__26
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__26_n_0),
- .O(s_pulseLed_i_5__26_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__26
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__26_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__26
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__26_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__26
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__26_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_133
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__25_n_0;
- wire s_pulseLed_i_2__25_n_0;
- wire s_pulseLed_i_3__25_n_0;
- wire s_pulseLed_i_4__25_n_0;
- wire s_pulseLed_i_5__25_n_0;
- wire s_pulseLed_i_7__25_n_0;
- wire s_pulseLed_i_8__25_n_0;
- wire s_pulseLed_i_9__25_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__25
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__25_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__25
- (.I0(s_pulseLed_i_2__25_n_0),
- .I1(s_pulseLed_i_3__25_n_0),
- .I2(s_pulseLed_i_4__25_n_0),
- .I3(s_pulseLed_i_5__25_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__25
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__25_n_0),
- .O(s_pulseLed_i_2__25_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__25
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__25_n_0),
- .O(s_pulseLed_i_3__25_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__25
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__25_n_0),
- .O(s_pulseLed_i_4__25_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__25
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__25_n_0),
- .O(s_pulseLed_i_5__25_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__25
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__25_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__25
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__25_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__25
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__25_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_135
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__24_n_0;
- wire s_pulseLed_i_2__24_n_0;
- wire s_pulseLed_i_3__24_n_0;
- wire s_pulseLed_i_4__24_n_0;
- wire s_pulseLed_i_5__24_n_0;
- wire s_pulseLed_i_7__24_n_0;
- wire s_pulseLed_i_8__24_n_0;
- wire s_pulseLed_i_9__24_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__24
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__24_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__24
- (.I0(s_pulseLed_i_2__24_n_0),
- .I1(s_pulseLed_i_3__24_n_0),
- .I2(s_pulseLed_i_4__24_n_0),
- .I3(s_pulseLed_i_5__24_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__24
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__24_n_0),
- .O(s_pulseLed_i_2__24_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__24
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__24_n_0),
- .O(s_pulseLed_i_3__24_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__24
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__24_n_0),
- .O(s_pulseLed_i_4__24_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__24
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__24_n_0),
- .O(s_pulseLed_i_5__24_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__24
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__24_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__24
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__24_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__24
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__24_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_137
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__23_n_0;
- wire s_pulseLed_i_2__23_n_0;
- wire s_pulseLed_i_3__23_n_0;
- wire s_pulseLed_i_4__23_n_0;
- wire s_pulseLed_i_5__23_n_0;
- wire s_pulseLed_i_7__23_n_0;
- wire s_pulseLed_i_8__23_n_0;
- wire s_pulseLed_i_9__23_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__23
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__23_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__23
- (.I0(s_pulseLed_i_2__23_n_0),
- .I1(s_pulseLed_i_3__23_n_0),
- .I2(s_pulseLed_i_4__23_n_0),
- .I3(s_pulseLed_i_5__23_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__23
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__23_n_0),
- .O(s_pulseLed_i_2__23_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__23
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__23_n_0),
- .O(s_pulseLed_i_3__23_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__23
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__23_n_0),
- .O(s_pulseLed_i_4__23_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__23
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__23_n_0),
- .O(s_pulseLed_i_5__23_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__23
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__23_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__23
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__23_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__23
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__23_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_139
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__22_n_0;
- wire s_pulseLed_i_2__22_n_0;
- wire s_pulseLed_i_3__22_n_0;
- wire s_pulseLed_i_4__22_n_0;
- wire s_pulseLed_i_5__22_n_0;
- wire s_pulseLed_i_7__22_n_0;
- wire s_pulseLed_i_8__22_n_0;
- wire s_pulseLed_i_9__22_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__22
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__22_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__22
- (.I0(s_pulseLed_i_2__22_n_0),
- .I1(s_pulseLed_i_3__22_n_0),
- .I2(s_pulseLed_i_4__22_n_0),
- .I3(s_pulseLed_i_5__22_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__22
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__22_n_0),
- .O(s_pulseLed_i_2__22_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__22
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__22_n_0),
- .O(s_pulseLed_i_3__22_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__22
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__22_n_0),
- .O(s_pulseLed_i_4__22_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__22
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__22_n_0),
- .O(s_pulseLed_i_5__22_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__22
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__22_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__22
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__22_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__22
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__22_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_141
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__21_n_0;
- wire s_pulseLed_i_2__21_n_0;
- wire s_pulseLed_i_3__21_n_0;
- wire s_pulseLed_i_4__21_n_0;
- wire s_pulseLed_i_5__21_n_0;
- wire s_pulseLed_i_7__21_n_0;
- wire s_pulseLed_i_8__21_n_0;
- wire s_pulseLed_i_9__21_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__21
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__21_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__21
- (.I0(s_pulseLed_i_2__21_n_0),
- .I1(s_pulseLed_i_3__21_n_0),
- .I2(s_pulseLed_i_4__21_n_0),
- .I3(s_pulseLed_i_5__21_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__21
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__21_n_0),
- .O(s_pulseLed_i_2__21_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__21
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__21_n_0),
- .O(s_pulseLed_i_3__21_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__21
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__21_n_0),
- .O(s_pulseLed_i_4__21_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__21
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__21_n_0),
- .O(s_pulseLed_i_5__21_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__21
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__21_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__21
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__21_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__21
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__21_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_143
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__20_n_0;
- wire s_pulseLed_i_2__20_n_0;
- wire s_pulseLed_i_3__20_n_0;
- wire s_pulseLed_i_4__20_n_0;
- wire s_pulseLed_i_5__20_n_0;
- wire s_pulseLed_i_7__20_n_0;
- wire s_pulseLed_i_8__20_n_0;
- wire s_pulseLed_i_9__20_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__20
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__20_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__20
- (.I0(s_pulseLed_i_2__20_n_0),
- .I1(s_pulseLed_i_3__20_n_0),
- .I2(s_pulseLed_i_4__20_n_0),
- .I3(s_pulseLed_i_5__20_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__20
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__20_n_0),
- .O(s_pulseLed_i_2__20_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__20
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__20_n_0),
- .O(s_pulseLed_i_3__20_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__20
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__20_n_0),
- .O(s_pulseLed_i_4__20_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__20
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__20_n_0),
- .O(s_pulseLed_i_5__20_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__20
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__20_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__20
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__20_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__20
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__20_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_145
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__19_n_0;
- wire s_pulseLed_i_2__19_n_0;
- wire s_pulseLed_i_3__19_n_0;
- wire s_pulseLed_i_4__19_n_0;
- wire s_pulseLed_i_5__19_n_0;
- wire s_pulseLed_i_7__19_n_0;
- wire s_pulseLed_i_8__19_n_0;
- wire s_pulseLed_i_9__19_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__19
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__19_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__19
- (.I0(s_pulseLed_i_2__19_n_0),
- .I1(s_pulseLed_i_3__19_n_0),
- .I2(s_pulseLed_i_4__19_n_0),
- .I3(s_pulseLed_i_5__19_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__19
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__19_n_0),
- .O(s_pulseLed_i_2__19_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__19
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__19_n_0),
- .O(s_pulseLed_i_3__19_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__19
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__19_n_0),
- .O(s_pulseLed_i_4__19_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__19
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__19_n_0),
- .O(s_pulseLed_i_5__19_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__19
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__19_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__19
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__19_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__19
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__19_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_148
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__8_n_0;
- wire s_pulseLed_i_2__8_n_0;
- wire s_pulseLed_i_3__8_n_0;
- wire s_pulseLed_i_4__8_n_0;
- wire s_pulseLed_i_5__8_n_0;
- wire s_pulseLed_i_7__8_n_0;
- wire s_pulseLed_i_8__8_n_0;
- wire s_pulseLed_i_9__8_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__8
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__8_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__8
- (.I0(s_pulseLed_i_2__8_n_0),
- .I1(s_pulseLed_i_3__8_n_0),
- .I2(s_pulseLed_i_4__8_n_0),
- .I3(s_pulseLed_i_5__8_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__8
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__8_n_0),
- .O(s_pulseLed_i_2__8_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__8
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__8_n_0),
- .O(s_pulseLed_i_3__8_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__8
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__8_n_0),
- .O(s_pulseLed_i_4__8_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__8
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__8_n_0),
- .O(s_pulseLed_i_5__8_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__8
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__8_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__8
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__8_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__8
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__8_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_151
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__7_n_0;
- wire s_pulseLed_i_2__7_n_0;
- wire s_pulseLed_i_3__7_n_0;
- wire s_pulseLed_i_4__7_n_0;
- wire s_pulseLed_i_5__7_n_0;
- wire s_pulseLed_i_7__7_n_0;
- wire s_pulseLed_i_8__7_n_0;
- wire s_pulseLed_i_9__7_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__7
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__7_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__7
- (.I0(s_pulseLed_i_2__7_n_0),
- .I1(s_pulseLed_i_3__7_n_0),
- .I2(s_pulseLed_i_4__7_n_0),
- .I3(s_pulseLed_i_5__7_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__7
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__7_n_0),
- .O(s_pulseLed_i_2__7_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__7
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__7_n_0),
- .O(s_pulseLed_i_3__7_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__7
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__7_n_0),
- .O(s_pulseLed_i_4__7_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__7
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__7_n_0),
- .O(s_pulseLed_i_5__7_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__7
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__7_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__7
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__7_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__7
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__7_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_154
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__6_n_0;
- wire s_pulseLed_i_2__6_n_0;
- wire s_pulseLed_i_3__6_n_0;
- wire s_pulseLed_i_4__6_n_0;
- wire s_pulseLed_i_5__6_n_0;
- wire s_pulseLed_i_7__6_n_0;
- wire s_pulseLed_i_8__6_n_0;
- wire s_pulseLed_i_9__6_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__6
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__6_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__6
- (.I0(s_pulseLed_i_2__6_n_0),
- .I1(s_pulseLed_i_3__6_n_0),
- .I2(s_pulseLed_i_4__6_n_0),
- .I3(s_pulseLed_i_5__6_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__6
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__6_n_0),
- .O(s_pulseLed_i_2__6_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__6
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__6_n_0),
- .O(s_pulseLed_i_3__6_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__6
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__6_n_0),
- .O(s_pulseLed_i_4__6_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__6
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__6_n_0),
- .O(s_pulseLed_i_5__6_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__6
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__6_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__6
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__6_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__6
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__6_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_157
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__5_n_0;
- wire s_pulseLed_i_2__5_n_0;
- wire s_pulseLed_i_3__5_n_0;
- wire s_pulseLed_i_4__5_n_0;
- wire s_pulseLed_i_5__5_n_0;
- wire s_pulseLed_i_7__5_n_0;
- wire s_pulseLed_i_8__5_n_0;
- wire s_pulseLed_i_9__5_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__5
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__5_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__5
- (.I0(s_pulseLed_i_2__5_n_0),
- .I1(s_pulseLed_i_3__5_n_0),
- .I2(s_pulseLed_i_4__5_n_0),
- .I3(s_pulseLed_i_5__5_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__5
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__5_n_0),
- .O(s_pulseLed_i_2__5_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__5
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__5_n_0),
- .O(s_pulseLed_i_3__5_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__5
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__5_n_0),
- .O(s_pulseLed_i_4__5_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__5
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__5_n_0),
- .O(s_pulseLed_i_5__5_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__5
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__5_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__5
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__5_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__5
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__5_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_160
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__4_n_0;
- wire s_pulseLed_i_2__4_n_0;
- wire s_pulseLed_i_3__4_n_0;
- wire s_pulseLed_i_4__4_n_0;
- wire s_pulseLed_i_5__4_n_0;
- wire s_pulseLed_i_7__4_n_0;
- wire s_pulseLed_i_8__4_n_0;
- wire s_pulseLed_i_9__4_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__4
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__4_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__4
- (.I0(s_pulseLed_i_2__4_n_0),
- .I1(s_pulseLed_i_3__4_n_0),
- .I2(s_pulseLed_i_4__4_n_0),
- .I3(s_pulseLed_i_5__4_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__4
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__4_n_0),
- .O(s_pulseLed_i_2__4_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__4
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__4_n_0),
- .O(s_pulseLed_i_3__4_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__4
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__4_n_0),
- .O(s_pulseLed_i_4__4_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__4
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__4_n_0),
- .O(s_pulseLed_i_5__4_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__4
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__4_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__4
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__4_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__4
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__4_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_163
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__3_n_0;
- wire s_pulseLed_i_2__3_n_0;
- wire s_pulseLed_i_3__3_n_0;
- wire s_pulseLed_i_4__3_n_0;
- wire s_pulseLed_i_5__3_n_0;
- wire s_pulseLed_i_7__3_n_0;
- wire s_pulseLed_i_8__3_n_0;
- wire s_pulseLed_i_9__3_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__3
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__3_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__3
- (.I0(s_pulseLed_i_2__3_n_0),
- .I1(s_pulseLed_i_3__3_n_0),
- .I2(s_pulseLed_i_4__3_n_0),
- .I3(s_pulseLed_i_5__3_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__3
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__3_n_0),
- .O(s_pulseLed_i_2__3_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__3
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__3_n_0),
- .O(s_pulseLed_i_3__3_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__3
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__3_n_0),
- .O(s_pulseLed_i_4__3_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__3
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__3_n_0),
- .O(s_pulseLed_i_5__3_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__3
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__3_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__3
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__3_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__3
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__3_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_166
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__2_n_0;
- wire s_pulseLed_i_2__2_n_0;
- wire s_pulseLed_i_3__2_n_0;
- wire s_pulseLed_i_4__2_n_0;
- wire s_pulseLed_i_5__2_n_0;
- wire s_pulseLed_i_7__2_n_0;
- wire s_pulseLed_i_8__2_n_0;
- wire s_pulseLed_i_9__2_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__2
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__2_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__2
- (.I0(s_pulseLed_i_2__2_n_0),
- .I1(s_pulseLed_i_3__2_n_0),
- .I2(s_pulseLed_i_4__2_n_0),
- .I3(s_pulseLed_i_5__2_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__2
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__2_n_0),
- .O(s_pulseLed_i_2__2_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__2
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__2_n_0),
- .O(s_pulseLed_i_3__2_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__2
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__2_n_0),
- .O(s_pulseLed_i_4__2_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__2
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__2_n_0),
- .O(s_pulseLed_i_5__2_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__2
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__2_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__2
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__2_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__2
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__2_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_169
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__1_n_0;
- wire s_pulseLed_i_2__1_n_0;
- wire s_pulseLed_i_3__1_n_0;
- wire s_pulseLed_i_4__1_n_0;
- wire s_pulseLed_i_5__1_n_0;
- wire s_pulseLed_i_7__1_n_0;
- wire s_pulseLed_i_8__1_n_0;
- wire s_pulseLed_i_9__1_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__1
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__1_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__1
- (.I0(s_pulseLed_i_2__1_n_0),
- .I1(s_pulseLed_i_3__1_n_0),
- .I2(s_pulseLed_i_4__1_n_0),
- .I3(s_pulseLed_i_5__1_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__1
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__1_n_0),
- .O(s_pulseLed_i_2__1_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__1
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__1_n_0),
- .O(s_pulseLed_i_3__1_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__1
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__1_n_0),
- .O(s_pulseLed_i_4__1_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__1
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__1_n_0),
- .O(s_pulseLed_i_5__1_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__1
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__1_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__1
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__1_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__1
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__1_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_172
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__0_n_0;
- wire s_pulseLed_i_2__0_n_0;
- wire s_pulseLed_i_3__0_n_0;
- wire s_pulseLed_i_4__0_n_0;
- wire s_pulseLed_i_5__0_n_0;
- wire s_pulseLed_i_7__0_n_0;
- wire s_pulseLed_i_8__0_n_0;
- wire s_pulseLed_i_9__0_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__0
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__0_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__0
- (.I0(s_pulseLed_i_2__0_n_0),
- .I1(s_pulseLed_i_3__0_n_0),
- .I2(s_pulseLed_i_4__0_n_0),
- .I3(s_pulseLed_i_5__0_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__0
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__0_n_0),
- .O(s_pulseLed_i_2__0_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__0
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__0_n_0),
- .O(s_pulseLed_i_3__0_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__0
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__0_n_0),
- .O(s_pulseLed_i_4__0_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__0
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__0_n_0),
- .O(s_pulseLed_i_5__0_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__0
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__0_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__0
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__0_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__0
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__0_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_175
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__18_n_0;
- wire s_pulseLed_i_2__18_n_0;
- wire s_pulseLed_i_3__18_n_0;
- wire s_pulseLed_i_4__18_n_0;
- wire s_pulseLed_i_5__18_n_0;
- wire s_pulseLed_i_7__18_n_0;
- wire s_pulseLed_i_8__18_n_0;
- wire s_pulseLed_i_9__18_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__18
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__18_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__18
- (.I0(s_pulseLed_i_2__18_n_0),
- .I1(s_pulseLed_i_3__18_n_0),
- .I2(s_pulseLed_i_4__18_n_0),
- .I3(s_pulseLed_i_5__18_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__18
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__18_n_0),
- .O(s_pulseLed_i_2__18_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__18
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__18_n_0),
- .O(s_pulseLed_i_3__18_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__18
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__18_n_0),
- .O(s_pulseLed_i_4__18_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__18
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__18_n_0),
- .O(s_pulseLed_i_5__18_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__18
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__18_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__18
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__18_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__18
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__18_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_178
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__17_n_0;
- wire s_pulseLed_i_2__17_n_0;
- wire s_pulseLed_i_3__17_n_0;
- wire s_pulseLed_i_4__17_n_0;
- wire s_pulseLed_i_5__17_n_0;
- wire s_pulseLed_i_7__17_n_0;
- wire s_pulseLed_i_8__17_n_0;
- wire s_pulseLed_i_9__17_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__17
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__17_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__17
- (.I0(s_pulseLed_i_2__17_n_0),
- .I1(s_pulseLed_i_3__17_n_0),
- .I2(s_pulseLed_i_4__17_n_0),
- .I3(s_pulseLed_i_5__17_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__17
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__17_n_0),
- .O(s_pulseLed_i_2__17_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__17
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__17_n_0),
- .O(s_pulseLed_i_3__17_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__17
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__17_n_0),
- .O(s_pulseLed_i_4__17_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__17
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__17_n_0),
- .O(s_pulseLed_i_5__17_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__17
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__17_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__17
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__17_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__17
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__17_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_181
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__16_n_0;
- wire s_pulseLed_i_2__16_n_0;
- wire s_pulseLed_i_3__16_n_0;
- wire s_pulseLed_i_4__16_n_0;
- wire s_pulseLed_i_5__16_n_0;
- wire s_pulseLed_i_7__16_n_0;
- wire s_pulseLed_i_8__16_n_0;
- wire s_pulseLed_i_9__16_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__16
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__16_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__16
- (.I0(s_pulseLed_i_2__16_n_0),
- .I1(s_pulseLed_i_3__16_n_0),
- .I2(s_pulseLed_i_4__16_n_0),
- .I3(s_pulseLed_i_5__16_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__16
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__16_n_0),
- .O(s_pulseLed_i_2__16_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__16
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__16_n_0),
- .O(s_pulseLed_i_3__16_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__16
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__16_n_0),
- .O(s_pulseLed_i_4__16_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__16
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__16_n_0),
- .O(s_pulseLed_i_5__16_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__16
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__16_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__16
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__16_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__16
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__16_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_184
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__15_n_0;
- wire s_pulseLed_i_2__15_n_0;
- wire s_pulseLed_i_3__15_n_0;
- wire s_pulseLed_i_4__15_n_0;
- wire s_pulseLed_i_5__15_n_0;
- wire s_pulseLed_i_7__15_n_0;
- wire s_pulseLed_i_8__15_n_0;
- wire s_pulseLed_i_9__15_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__15
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__15_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__15
- (.I0(s_pulseLed_i_2__15_n_0),
- .I1(s_pulseLed_i_3__15_n_0),
- .I2(s_pulseLed_i_4__15_n_0),
- .I3(s_pulseLed_i_5__15_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__15
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__15_n_0),
- .O(s_pulseLed_i_2__15_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__15
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__15_n_0),
- .O(s_pulseLed_i_3__15_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__15
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__15_n_0),
- .O(s_pulseLed_i_4__15_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__15
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__15_n_0),
- .O(s_pulseLed_i_5__15_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__15
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__15_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__15
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__15_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__15
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__15_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_187
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__14_n_0;
- wire s_pulseLed_i_2__14_n_0;
- wire s_pulseLed_i_3__14_n_0;
- wire s_pulseLed_i_4__14_n_0;
- wire s_pulseLed_i_5__14_n_0;
- wire s_pulseLed_i_7__14_n_0;
- wire s_pulseLed_i_8__14_n_0;
- wire s_pulseLed_i_9__14_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__14
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__14_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__14
- (.I0(s_pulseLed_i_2__14_n_0),
- .I1(s_pulseLed_i_3__14_n_0),
- .I2(s_pulseLed_i_4__14_n_0),
- .I3(s_pulseLed_i_5__14_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__14
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__14_n_0),
- .O(s_pulseLed_i_2__14_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__14
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__14_n_0),
- .O(s_pulseLed_i_3__14_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__14
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__14_n_0),
- .O(s_pulseLed_i_4__14_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__14
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__14_n_0),
- .O(s_pulseLed_i_5__14_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__14
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__14_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__14
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__14_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__14
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__14_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_190
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__13_n_0;
- wire s_pulseLed_i_2__13_n_0;
- wire s_pulseLed_i_3__13_n_0;
- wire s_pulseLed_i_4__13_n_0;
- wire s_pulseLed_i_5__13_n_0;
- wire s_pulseLed_i_7__13_n_0;
- wire s_pulseLed_i_8__13_n_0;
- wire s_pulseLed_i_9__13_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__13
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__13_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__13
- (.I0(s_pulseLed_i_2__13_n_0),
- .I1(s_pulseLed_i_3__13_n_0),
- .I2(s_pulseLed_i_4__13_n_0),
- .I3(s_pulseLed_i_5__13_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__13
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__13_n_0),
- .O(s_pulseLed_i_2__13_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__13
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__13_n_0),
- .O(s_pulseLed_i_3__13_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__13
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__13_n_0),
- .O(s_pulseLed_i_4__13_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__13
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__13_n_0),
- .O(s_pulseLed_i_5__13_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__13
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__13_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__13
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__13_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__13
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__13_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_193
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__12_n_0;
- wire s_pulseLed_i_2__12_n_0;
- wire s_pulseLed_i_3__12_n_0;
- wire s_pulseLed_i_4__12_n_0;
- wire s_pulseLed_i_5__12_n_0;
- wire s_pulseLed_i_7__12_n_0;
- wire s_pulseLed_i_8__12_n_0;
- wire s_pulseLed_i_9__12_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__12
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__12_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__12
- (.I0(s_pulseLed_i_2__12_n_0),
- .I1(s_pulseLed_i_3__12_n_0),
- .I2(s_pulseLed_i_4__12_n_0),
- .I3(s_pulseLed_i_5__12_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__12
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__12_n_0),
- .O(s_pulseLed_i_2__12_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__12
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__12_n_0),
- .O(s_pulseLed_i_3__12_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__12
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__12_n_0),
- .O(s_pulseLed_i_4__12_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__12
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__12_n_0),
- .O(s_pulseLed_i_5__12_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__12
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__12_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__12
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__12_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__12
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__12_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_196
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__11_n_0;
- wire s_pulseLed_i_2__11_n_0;
- wire s_pulseLed_i_3__11_n_0;
- wire s_pulseLed_i_4__11_n_0;
- wire s_pulseLed_i_5__11_n_0;
- wire s_pulseLed_i_7__11_n_0;
- wire s_pulseLed_i_8__11_n_0;
- wire s_pulseLed_i_9__11_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__11
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__11_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__11
- (.I0(s_pulseLed_i_2__11_n_0),
- .I1(s_pulseLed_i_3__11_n_0),
- .I2(s_pulseLed_i_4__11_n_0),
- .I3(s_pulseLed_i_5__11_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__11
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__11_n_0),
- .O(s_pulseLed_i_2__11_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__11
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__11_n_0),
- .O(s_pulseLed_i_3__11_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__11
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__11_n_0),
- .O(s_pulseLed_i_4__11_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__11
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__11_n_0),
- .O(s_pulseLed_i_5__11_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__11
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__11_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__11
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__11_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__11
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__11_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_199
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__10_n_0;
- wire s_pulseLed_i_2__10_n_0;
- wire s_pulseLed_i_3__10_n_0;
- wire s_pulseLed_i_4__10_n_0;
- wire s_pulseLed_i_5__10_n_0;
- wire s_pulseLed_i_7__10_n_0;
- wire s_pulseLed_i_8__10_n_0;
- wire s_pulseLed_i_9__10_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__10
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__10_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__10
- (.I0(s_pulseLed_i_2__10_n_0),
- .I1(s_pulseLed_i_3__10_n_0),
- .I2(s_pulseLed_i_4__10_n_0),
- .I3(s_pulseLed_i_5__10_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__10
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__10_n_0),
- .O(s_pulseLed_i_2__10_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__10
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__10_n_0),
- .O(s_pulseLed_i_3__10_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__10
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__10_n_0),
- .O(s_pulseLed_i_4__10_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__10
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__10_n_0),
- .O(s_pulseLed_i_5__10_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__10
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__10_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__10
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__10_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__10
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__10_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_202
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__9_n_0;
- wire s_pulseLed_i_2__9_n_0;
- wire s_pulseLed_i_3__9_n_0;
- wire s_pulseLed_i_4__9_n_0;
- wire s_pulseLed_i_5__9_n_0;
- wire s_pulseLed_i_7__9_n_0;
- wire s_pulseLed_i_8__9_n_0;
- wire s_pulseLed_i_9__9_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__9
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__9_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__9
- (.I0(s_pulseLed_i_2__9_n_0),
- .I1(s_pulseLed_i_3__9_n_0),
- .I2(s_pulseLed_i_4__9_n_0),
- .I3(s_pulseLed_i_5__9_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__9
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__9_n_0),
- .O(s_pulseLed_i_2__9_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__9
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__9_n_0),
- .O(s_pulseLed_i_3__9_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__9
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__9_n_0),
- .O(s_pulseLed_i_4__9_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__9
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__9_n_0),
- .O(s_pulseLed_i_5__9_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__9
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__9_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__9
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__9_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__9
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__9_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_205
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10_n_0;
- wire s_pulseLed_i_2_n_0;
- wire s_pulseLed_i_3_n_0;
- wire s_pulseLed_i_4_n_0;
- wire s_pulseLed_i_5_n_0;
- wire s_pulseLed_i_7_n_0;
- wire s_pulseLed_i_8_n_0;
- wire s_pulseLed_i_9_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1
- (.I0(s_pulseLed_i_2_n_0),
- .I1(s_pulseLed_i_3_n_0),
- .I2(s_pulseLed_i_4_n_0),
- .I3(s_pulseLed_i_5_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7_n_0),
- .O(s_pulseLed_i_2_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8_n_0),
- .O(s_pulseLed_i_3_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9_n_0),
- .O(s_pulseLed_i_4_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10_n_0),
- .O(s_pulseLed_i_5_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_28
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__53_n_0;
- wire s_pulseLed_i_2__53_n_0;
- wire s_pulseLed_i_3__53_n_0;
- wire s_pulseLed_i_4__53_n_0;
- wire s_pulseLed_i_5__53_n_0;
- wire s_pulseLed_i_7__53_n_0;
- wire s_pulseLed_i_8__53_n_0;
- wire s_pulseLed_i_9__53_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__53
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__53_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__53
- (.I0(s_pulseLed_i_2__53_n_0),
- .I1(s_pulseLed_i_3__53_n_0),
- .I2(s_pulseLed_i_4__53_n_0),
- .I3(s_pulseLed_i_5__53_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__53
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__53_n_0),
- .O(s_pulseLed_i_2__53_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__53
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__53_n_0),
- .O(s_pulseLed_i_3__53_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__53
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__53_n_0),
- .O(s_pulseLed_i_4__53_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__53
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__53_n_0),
- .O(s_pulseLed_i_5__53_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__53
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__53_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__53
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__53_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__53
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__53_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_30
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__52_n_0;
- wire s_pulseLed_i_2__52_n_0;
- wire s_pulseLed_i_3__52_n_0;
- wire s_pulseLed_i_4__52_n_0;
- wire s_pulseLed_i_5__52_n_0;
- wire s_pulseLed_i_7__52_n_0;
- wire s_pulseLed_i_8__52_n_0;
- wire s_pulseLed_i_9__52_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__52
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__52_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__52
- (.I0(s_pulseLed_i_2__52_n_0),
- .I1(s_pulseLed_i_3__52_n_0),
- .I2(s_pulseLed_i_4__52_n_0),
- .I3(s_pulseLed_i_5__52_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__52
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__52_n_0),
- .O(s_pulseLed_i_2__52_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__52
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__52_n_0),
- .O(s_pulseLed_i_3__52_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__52
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__52_n_0),
- .O(s_pulseLed_i_4__52_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__52
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__52_n_0),
- .O(s_pulseLed_i_5__52_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__52
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__52_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__52
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__52_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__52
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__52_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_32
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__51_n_0;
- wire s_pulseLed_i_2__51_n_0;
- wire s_pulseLed_i_3__51_n_0;
- wire s_pulseLed_i_4__51_n_0;
- wire s_pulseLed_i_5__51_n_0;
- wire s_pulseLed_i_7__51_n_0;
- wire s_pulseLed_i_8__51_n_0;
- wire s_pulseLed_i_9__51_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__51
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__51_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__51
- (.I0(s_pulseLed_i_2__51_n_0),
- .I1(s_pulseLed_i_3__51_n_0),
- .I2(s_pulseLed_i_4__51_n_0),
- .I3(s_pulseLed_i_5__51_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__51
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__51_n_0),
- .O(s_pulseLed_i_2__51_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__51
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__51_n_0),
- .O(s_pulseLed_i_3__51_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__51
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__51_n_0),
- .O(s_pulseLed_i_4__51_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__51
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__51_n_0),
- .O(s_pulseLed_i_5__51_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__51
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__51_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__51
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__51_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__51
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__51_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_34
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__50_n_0;
- wire s_pulseLed_i_2__50_n_0;
- wire s_pulseLed_i_3__50_n_0;
- wire s_pulseLed_i_4__50_n_0;
- wire s_pulseLed_i_5__50_n_0;
- wire s_pulseLed_i_7__50_n_0;
- wire s_pulseLed_i_8__50_n_0;
- wire s_pulseLed_i_9__50_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__50
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__50_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__50
- (.I0(s_pulseLed_i_2__50_n_0),
- .I1(s_pulseLed_i_3__50_n_0),
- .I2(s_pulseLed_i_4__50_n_0),
- .I3(s_pulseLed_i_5__50_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__50
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__50_n_0),
- .O(s_pulseLed_i_2__50_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__50
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__50_n_0),
- .O(s_pulseLed_i_3__50_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__50
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__50_n_0),
- .O(s_pulseLed_i_4__50_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__50
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__50_n_0),
- .O(s_pulseLed_i_5__50_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__50
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__50_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__50
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__50_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__50
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__50_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_36
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__49_n_0;
- wire s_pulseLed_i_2__49_n_0;
- wire s_pulseLed_i_3__49_n_0;
- wire s_pulseLed_i_4__49_n_0;
- wire s_pulseLed_i_5__49_n_0;
- wire s_pulseLed_i_7__49_n_0;
- wire s_pulseLed_i_8__49_n_0;
- wire s_pulseLed_i_9__49_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__49
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__49_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__49
- (.I0(s_pulseLed_i_2__49_n_0),
- .I1(s_pulseLed_i_3__49_n_0),
- .I2(s_pulseLed_i_4__49_n_0),
- .I3(s_pulseLed_i_5__49_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__49
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__49_n_0),
- .O(s_pulseLed_i_2__49_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__49
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__49_n_0),
- .O(s_pulseLed_i_3__49_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__49
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__49_n_0),
- .O(s_pulseLed_i_4__49_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__49
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__49_n_0),
- .O(s_pulseLed_i_5__49_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__49
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__49_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__49
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__49_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__49
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__49_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_38
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__48_n_0;
- wire s_pulseLed_i_2__48_n_0;
- wire s_pulseLed_i_3__48_n_0;
- wire s_pulseLed_i_4__48_n_0;
- wire s_pulseLed_i_5__48_n_0;
- wire s_pulseLed_i_7__48_n_0;
- wire s_pulseLed_i_8__48_n_0;
- wire s_pulseLed_i_9__48_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__48
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__48_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__48
- (.I0(s_pulseLed_i_2__48_n_0),
- .I1(s_pulseLed_i_3__48_n_0),
- .I2(s_pulseLed_i_4__48_n_0),
- .I3(s_pulseLed_i_5__48_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__48
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__48_n_0),
- .O(s_pulseLed_i_2__48_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__48
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__48_n_0),
- .O(s_pulseLed_i_3__48_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__48
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__48_n_0),
- .O(s_pulseLed_i_4__48_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__48
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__48_n_0),
- .O(s_pulseLed_i_5__48_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__48
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__48_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__48
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__48_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__48
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__48_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_40
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__47_n_0;
- wire s_pulseLed_i_2__47_n_0;
- wire s_pulseLed_i_3__47_n_0;
- wire s_pulseLed_i_4__47_n_0;
- wire s_pulseLed_i_5__47_n_0;
- wire s_pulseLed_i_7__47_n_0;
- wire s_pulseLed_i_8__47_n_0;
- wire s_pulseLed_i_9__47_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__47
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__47_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__47
- (.I0(s_pulseLed_i_2__47_n_0),
- .I1(s_pulseLed_i_3__47_n_0),
- .I2(s_pulseLed_i_4__47_n_0),
- .I3(s_pulseLed_i_5__47_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__47
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__47_n_0),
- .O(s_pulseLed_i_2__47_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__47
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__47_n_0),
- .O(s_pulseLed_i_3__47_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__47
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__47_n_0),
- .O(s_pulseLed_i_4__47_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__47
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__47_n_0),
- .O(s_pulseLed_i_5__47_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__47
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__47_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__47
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__47_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__47
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__47_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_42
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__36_n_0;
- wire s_pulseLed_i_2__36_n_0;
- wire s_pulseLed_i_3__36_n_0;
- wire s_pulseLed_i_4__36_n_0;
- wire s_pulseLed_i_5__36_n_0;
- wire s_pulseLed_i_7__36_n_0;
- wire s_pulseLed_i_8__36_n_0;
- wire s_pulseLed_i_9__36_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__36
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__36_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__36
- (.I0(s_pulseLed_i_2__36_n_0),
- .I1(s_pulseLed_i_3__36_n_0),
- .I2(s_pulseLed_i_4__36_n_0),
- .I3(s_pulseLed_i_5__36_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__36
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__36_n_0),
- .O(s_pulseLed_i_2__36_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__36
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__36_n_0),
- .O(s_pulseLed_i_3__36_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__36
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__36_n_0),
- .O(s_pulseLed_i_4__36_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__36
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__36_n_0),
- .O(s_pulseLed_i_5__36_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__36
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__36_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__36
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__36_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__36
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__36_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_45
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__35_n_0;
- wire s_pulseLed_i_2__35_n_0;
- wire s_pulseLed_i_3__35_n_0;
- wire s_pulseLed_i_4__35_n_0;
- wire s_pulseLed_i_5__35_n_0;
- wire s_pulseLed_i_7__35_n_0;
- wire s_pulseLed_i_8__35_n_0;
- wire s_pulseLed_i_9__35_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__35
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__35_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__35
- (.I0(s_pulseLed_i_2__35_n_0),
- .I1(s_pulseLed_i_3__35_n_0),
- .I2(s_pulseLed_i_4__35_n_0),
- .I3(s_pulseLed_i_5__35_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__35
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__35_n_0),
- .O(s_pulseLed_i_2__35_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__35
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__35_n_0),
- .O(s_pulseLed_i_3__35_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__35
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__35_n_0),
- .O(s_pulseLed_i_4__35_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__35
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__35_n_0),
- .O(s_pulseLed_i_5__35_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__35
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__35_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__35
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__35_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__35
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__35_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_48
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__34_n_0;
- wire s_pulseLed_i_2__34_n_0;
- wire s_pulseLed_i_3__34_n_0;
- wire s_pulseLed_i_4__34_n_0;
- wire s_pulseLed_i_5__34_n_0;
- wire s_pulseLed_i_7__34_n_0;
- wire s_pulseLed_i_8__34_n_0;
- wire s_pulseLed_i_9__34_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__34
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__34_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__34
- (.I0(s_pulseLed_i_2__34_n_0),
- .I1(s_pulseLed_i_3__34_n_0),
- .I2(s_pulseLed_i_4__34_n_0),
- .I3(s_pulseLed_i_5__34_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__34
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__34_n_0),
- .O(s_pulseLed_i_2__34_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__34
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__34_n_0),
- .O(s_pulseLed_i_3__34_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__34
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__34_n_0),
- .O(s_pulseLed_i_4__34_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__34
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__34_n_0),
- .O(s_pulseLed_i_5__34_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__34
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__34_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__34
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__34_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__34
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__34_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_51
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__33_n_0;
- wire s_pulseLed_i_2__33_n_0;
- wire s_pulseLed_i_3__33_n_0;
- wire s_pulseLed_i_4__33_n_0;
- wire s_pulseLed_i_5__33_n_0;
- wire s_pulseLed_i_7__33_n_0;
- wire s_pulseLed_i_8__33_n_0;
- wire s_pulseLed_i_9__33_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__33
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__33_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__33
- (.I0(s_pulseLed_i_2__33_n_0),
- .I1(s_pulseLed_i_3__33_n_0),
- .I2(s_pulseLed_i_4__33_n_0),
- .I3(s_pulseLed_i_5__33_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__33
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__33_n_0),
- .O(s_pulseLed_i_2__33_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__33
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__33_n_0),
- .O(s_pulseLed_i_3__33_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__33
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__33_n_0),
- .O(s_pulseLed_i_4__33_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__33
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__33_n_0),
- .O(s_pulseLed_i_5__33_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__33
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__33_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__33
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__33_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__33
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__33_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_54
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__32_n_0;
- wire s_pulseLed_i_2__32_n_0;
- wire s_pulseLed_i_3__32_n_0;
- wire s_pulseLed_i_4__32_n_0;
- wire s_pulseLed_i_5__32_n_0;
- wire s_pulseLed_i_7__32_n_0;
- wire s_pulseLed_i_8__32_n_0;
- wire s_pulseLed_i_9__32_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__32
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__32_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__32
- (.I0(s_pulseLed_i_2__32_n_0),
- .I1(s_pulseLed_i_3__32_n_0),
- .I2(s_pulseLed_i_4__32_n_0),
- .I3(s_pulseLed_i_5__32_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__32
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__32_n_0),
- .O(s_pulseLed_i_2__32_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__32
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__32_n_0),
- .O(s_pulseLed_i_3__32_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__32
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__32_n_0),
- .O(s_pulseLed_i_4__32_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__32
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__32_n_0),
- .O(s_pulseLed_i_5__32_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__32
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__32_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__32
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__32_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__32
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__32_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_57
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__31_n_0;
- wire s_pulseLed_i_2__31_n_0;
- wire s_pulseLed_i_3__31_n_0;
- wire s_pulseLed_i_4__31_n_0;
- wire s_pulseLed_i_5__31_n_0;
- wire s_pulseLed_i_7__31_n_0;
- wire s_pulseLed_i_8__31_n_0;
- wire s_pulseLed_i_9__31_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__31
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__31_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__31
- (.I0(s_pulseLed_i_2__31_n_0),
- .I1(s_pulseLed_i_3__31_n_0),
- .I2(s_pulseLed_i_4__31_n_0),
- .I3(s_pulseLed_i_5__31_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__31
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__31_n_0),
- .O(s_pulseLed_i_2__31_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__31
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__31_n_0),
- .O(s_pulseLed_i_3__31_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__31
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__31_n_0),
- .O(s_pulseLed_i_4__31_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__31
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__31_n_0),
- .O(s_pulseLed_i_5__31_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__31
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__31_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__31
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__31_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__31
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__31_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_60
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__30_n_0;
- wire s_pulseLed_i_2__30_n_0;
- wire s_pulseLed_i_3__30_n_0;
- wire s_pulseLed_i_4__30_n_0;
- wire s_pulseLed_i_5__30_n_0;
- wire s_pulseLed_i_7__30_n_0;
- wire s_pulseLed_i_8__30_n_0;
- wire s_pulseLed_i_9__30_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__30
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__30_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__30
- (.I0(s_pulseLed_i_2__30_n_0),
- .I1(s_pulseLed_i_3__30_n_0),
- .I2(s_pulseLed_i_4__30_n_0),
- .I3(s_pulseLed_i_5__30_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__30
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__30_n_0),
- .O(s_pulseLed_i_2__30_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__30
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__30_n_0),
- .O(s_pulseLed_i_3__30_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__30
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__30_n_0),
- .O(s_pulseLed_i_4__30_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__30
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__30_n_0),
- .O(s_pulseLed_i_5__30_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__30
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__30_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__30
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__30_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__30
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__30_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_63
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__29_n_0;
- wire s_pulseLed_i_2__29_n_0;
- wire s_pulseLed_i_3__29_n_0;
- wire s_pulseLed_i_4__29_n_0;
- wire s_pulseLed_i_5__29_n_0;
- wire s_pulseLed_i_7__29_n_0;
- wire s_pulseLed_i_8__29_n_0;
- wire s_pulseLed_i_9__29_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__29
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__29_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__29
- (.I0(s_pulseLed_i_2__29_n_0),
- .I1(s_pulseLed_i_3__29_n_0),
- .I2(s_pulseLed_i_4__29_n_0),
- .I3(s_pulseLed_i_5__29_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__29
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__29_n_0),
- .O(s_pulseLed_i_2__29_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__29
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__29_n_0),
- .O(s_pulseLed_i_3__29_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__29
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__29_n_0),
- .O(s_pulseLed_i_4__29_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__29
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__29_n_0),
- .O(s_pulseLed_i_5__29_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__29
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__29_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__29
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__29_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__29
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__29_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_66
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__28_n_0;
- wire s_pulseLed_i_2__28_n_0;
- wire s_pulseLed_i_3__28_n_0;
- wire s_pulseLed_i_4__28_n_0;
- wire s_pulseLed_i_5__28_n_0;
- wire s_pulseLed_i_7__28_n_0;
- wire s_pulseLed_i_8__28_n_0;
- wire s_pulseLed_i_9__28_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__28
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__28_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__28
- (.I0(s_pulseLed_i_2__28_n_0),
- .I1(s_pulseLed_i_3__28_n_0),
- .I2(s_pulseLed_i_4__28_n_0),
- .I3(s_pulseLed_i_5__28_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__28
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__28_n_0),
- .O(s_pulseLed_i_2__28_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__28
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__28_n_0),
- .O(s_pulseLed_i_3__28_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__28
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__28_n_0),
- .O(s_pulseLed_i_4__28_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__28
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__28_n_0),
- .O(s_pulseLed_i_5__28_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__28
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__28_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__28
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__28_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__28
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__28_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_69
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__46_n_0;
- wire s_pulseLed_i_2__46_n_0;
- wire s_pulseLed_i_3__46_n_0;
- wire s_pulseLed_i_4__46_n_0;
- wire s_pulseLed_i_5__46_n_0;
- wire s_pulseLed_i_7__46_n_0;
- wire s_pulseLed_i_8__46_n_0;
- wire s_pulseLed_i_9__46_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__46
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__46_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__46
- (.I0(s_pulseLed_i_2__46_n_0),
- .I1(s_pulseLed_i_3__46_n_0),
- .I2(s_pulseLed_i_4__46_n_0),
- .I3(s_pulseLed_i_5__46_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__46
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__46_n_0),
- .O(s_pulseLed_i_2__46_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__46
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__46_n_0),
- .O(s_pulseLed_i_3__46_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__46
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__46_n_0),
- .O(s_pulseLed_i_4__46_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__46
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__46_n_0),
- .O(s_pulseLed_i_5__46_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__46
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__46_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__46
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__46_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__46
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__46_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_72
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__45_n_0;
- wire s_pulseLed_i_2__45_n_0;
- wire s_pulseLed_i_3__45_n_0;
- wire s_pulseLed_i_4__45_n_0;
- wire s_pulseLed_i_5__45_n_0;
- wire s_pulseLed_i_7__45_n_0;
- wire s_pulseLed_i_8__45_n_0;
- wire s_pulseLed_i_9__45_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__45
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__45_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__45
- (.I0(s_pulseLed_i_2__45_n_0),
- .I1(s_pulseLed_i_3__45_n_0),
- .I2(s_pulseLed_i_4__45_n_0),
- .I3(s_pulseLed_i_5__45_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__45
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__45_n_0),
- .O(s_pulseLed_i_2__45_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__45
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__45_n_0),
- .O(s_pulseLed_i_3__45_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__45
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__45_n_0),
- .O(s_pulseLed_i_4__45_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__45
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__45_n_0),
- .O(s_pulseLed_i_5__45_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__45
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__45_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__45
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__45_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__45
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__45_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_75
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__44_n_0;
- wire s_pulseLed_i_2__44_n_0;
- wire s_pulseLed_i_3__44_n_0;
- wire s_pulseLed_i_4__44_n_0;
- wire s_pulseLed_i_5__44_n_0;
- wire s_pulseLed_i_7__44_n_0;
- wire s_pulseLed_i_8__44_n_0;
- wire s_pulseLed_i_9__44_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__44
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__44_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__44
- (.I0(s_pulseLed_i_2__44_n_0),
- .I1(s_pulseLed_i_3__44_n_0),
- .I2(s_pulseLed_i_4__44_n_0),
- .I3(s_pulseLed_i_5__44_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__44
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__44_n_0),
- .O(s_pulseLed_i_2__44_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__44
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__44_n_0),
- .O(s_pulseLed_i_3__44_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__44
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__44_n_0),
- .O(s_pulseLed_i_4__44_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__44
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__44_n_0),
- .O(s_pulseLed_i_5__44_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__44
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__44_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__44
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__44_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__44
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__44_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_78
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__43_n_0;
- wire s_pulseLed_i_2__43_n_0;
- wire s_pulseLed_i_3__43_n_0;
- wire s_pulseLed_i_4__43_n_0;
- wire s_pulseLed_i_5__43_n_0;
- wire s_pulseLed_i_7__43_n_0;
- wire s_pulseLed_i_8__43_n_0;
- wire s_pulseLed_i_9__43_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__43
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__43_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__43
- (.I0(s_pulseLed_i_2__43_n_0),
- .I1(s_pulseLed_i_3__43_n_0),
- .I2(s_pulseLed_i_4__43_n_0),
- .I3(s_pulseLed_i_5__43_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__43
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__43_n_0),
- .O(s_pulseLed_i_2__43_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__43
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__43_n_0),
- .O(s_pulseLed_i_3__43_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__43
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__43_n_0),
- .O(s_pulseLed_i_4__43_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__43
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__43_n_0),
- .O(s_pulseLed_i_5__43_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__43
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__43_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__43
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__43_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__43
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__43_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_81
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__42_n_0;
- wire s_pulseLed_i_2__42_n_0;
- wire s_pulseLed_i_3__42_n_0;
- wire s_pulseLed_i_4__42_n_0;
- wire s_pulseLed_i_5__42_n_0;
- wire s_pulseLed_i_7__42_n_0;
- wire s_pulseLed_i_8__42_n_0;
- wire s_pulseLed_i_9__42_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__42
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__42_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__42
- (.I0(s_pulseLed_i_2__42_n_0),
- .I1(s_pulseLed_i_3__42_n_0),
- .I2(s_pulseLed_i_4__42_n_0),
- .I3(s_pulseLed_i_5__42_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__42
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__42_n_0),
- .O(s_pulseLed_i_2__42_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__42
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__42_n_0),
- .O(s_pulseLed_i_3__42_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__42
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__42_n_0),
- .O(s_pulseLed_i_4__42_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__42
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__42_n_0),
- .O(s_pulseLed_i_5__42_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__42
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__42_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__42
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__42_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__42
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__42_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_84
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__41_n_0;
- wire s_pulseLed_i_2__41_n_0;
- wire s_pulseLed_i_3__41_n_0;
- wire s_pulseLed_i_4__41_n_0;
- wire s_pulseLed_i_5__41_n_0;
- wire s_pulseLed_i_7__41_n_0;
- wire s_pulseLed_i_8__41_n_0;
- wire s_pulseLed_i_9__41_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__41
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__41_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__41
- (.I0(s_pulseLed_i_2__41_n_0),
- .I1(s_pulseLed_i_3__41_n_0),
- .I2(s_pulseLed_i_4__41_n_0),
- .I3(s_pulseLed_i_5__41_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__41
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__41_n_0),
- .O(s_pulseLed_i_2__41_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__41
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__41_n_0),
- .O(s_pulseLed_i_3__41_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__41
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__41_n_0),
- .O(s_pulseLed_i_4__41_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__41
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__41_n_0),
- .O(s_pulseLed_i_5__41_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__41
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__41_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__41
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__41_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__41
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__41_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_87
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__40_n_0;
- wire s_pulseLed_i_2__40_n_0;
- wire s_pulseLed_i_3__40_n_0;
- wire s_pulseLed_i_4__40_n_0;
- wire s_pulseLed_i_5__40_n_0;
- wire s_pulseLed_i_7__40_n_0;
- wire s_pulseLed_i_8__40_n_0;
- wire s_pulseLed_i_9__40_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__40
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__40_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__40
- (.I0(s_pulseLed_i_2__40_n_0),
- .I1(s_pulseLed_i_3__40_n_0),
- .I2(s_pulseLed_i_4__40_n_0),
- .I3(s_pulseLed_i_5__40_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__40
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__40_n_0),
- .O(s_pulseLed_i_2__40_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__40
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__40_n_0),
- .O(s_pulseLed_i_3__40_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__40
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__40_n_0),
- .O(s_pulseLed_i_4__40_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__40
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__40_n_0),
- .O(s_pulseLed_i_5__40_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__40
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__40_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__40
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__40_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__40
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__40_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_90
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__39_n_0;
- wire s_pulseLed_i_2__39_n_0;
- wire s_pulseLed_i_3__39_n_0;
- wire s_pulseLed_i_4__39_n_0;
- wire s_pulseLed_i_5__39_n_0;
- wire s_pulseLed_i_7__39_n_0;
- wire s_pulseLed_i_8__39_n_0;
- wire s_pulseLed_i_9__39_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__39
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__39_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__39
- (.I0(s_pulseLed_i_2__39_n_0),
- .I1(s_pulseLed_i_3__39_n_0),
- .I2(s_pulseLed_i_4__39_n_0),
- .I3(s_pulseLed_i_5__39_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__39
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__39_n_0),
- .O(s_pulseLed_i_2__39_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__39
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__39_n_0),
- .O(s_pulseLed_i_3__39_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__39
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__39_n_0),
- .O(s_pulseLed_i_4__39_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__39
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__39_n_0),
- .O(s_pulseLed_i_5__39_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__39
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__39_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__39
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__39_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__39
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__39_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_93
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__38_n_0;
- wire s_pulseLed_i_2__38_n_0;
- wire s_pulseLed_i_3__38_n_0;
- wire s_pulseLed_i_4__38_n_0;
- wire s_pulseLed_i_5__38_n_0;
- wire s_pulseLed_i_7__38_n_0;
- wire s_pulseLed_i_8__38_n_0;
- wire s_pulseLed_i_9__38_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__38
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__38_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__38
- (.I0(s_pulseLed_i_2__38_n_0),
- .I1(s_pulseLed_i_3__38_n_0),
- .I2(s_pulseLed_i_4__38_n_0),
- .I3(s_pulseLed_i_5__38_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__38
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__38_n_0),
- .O(s_pulseLed_i_2__38_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__38
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__38_n_0),
- .O(s_pulseLed_i_3__38_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__38
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__38_n_0),
- .O(s_pulseLed_i_4__38_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__38
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__38_n_0),
- .O(s_pulseLed_i_5__38_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__38
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__38_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__38
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__38_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__38
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__38_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_96
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__37_n_0;
- wire s_pulseLed_i_2__37_n_0;
- wire s_pulseLed_i_3__37_n_0;
- wire s_pulseLed_i_4__37_n_0;
- wire s_pulseLed_i_5__37_n_0;
- wire s_pulseLed_i_7__37_n_0;
- wire s_pulseLed_i_8__37_n_0;
- wire s_pulseLed_i_9__37_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__37
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__37_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__37
- (.I0(s_pulseLed_i_2__37_n_0),
- .I1(s_pulseLed_i_3__37_n_0),
- .I2(s_pulseLed_i_4__37_n_0),
- .I3(s_pulseLed_i_5__37_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__37
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__37_n_0),
- .O(s_pulseLed_i_2__37_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__37
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__37_n_0),
- .O(s_pulseLed_i_3__37_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__37
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__37_n_0),
- .O(s_pulseLed_i_4__37_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__37
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__37_n_0),
- .O(s_pulseLed_i_5__37_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__37
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__37_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__37
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__37_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__37
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__37_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "counterUpDown" *)
-module system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_99
- (s_pulseLed_reg,
- s_pulseLed_reg_0,
- s00_axi_aclk,
- s_buff2_reg,
- s_buff3_reg);
- output s_pulseLed_reg;
- input s_pulseLed_reg_0;
- input s00_axi_aclk;
- input s_buff2_reg;
- input s_buff3_reg;
-
- wire s00_axi_aclk;
- wire s_buff2_reg;
- wire s_buff3_reg;
- wire s_count_reg_n_100;
- wire s_count_reg_n_101;
- wire s_count_reg_n_102;
- wire s_count_reg_n_103;
- wire s_count_reg_n_104;
- wire s_count_reg_n_105;
- wire s_count_reg_n_74;
- wire s_count_reg_n_75;
- wire s_count_reg_n_76;
- wire s_count_reg_n_77;
- wire s_count_reg_n_78;
- wire s_count_reg_n_79;
- wire s_count_reg_n_80;
- wire s_count_reg_n_81;
- wire s_count_reg_n_82;
- wire s_count_reg_n_83;
- wire s_count_reg_n_84;
- wire s_count_reg_n_85;
- wire s_count_reg_n_86;
- wire s_count_reg_n_87;
- wire s_count_reg_n_88;
- wire s_count_reg_n_89;
- wire s_count_reg_n_90;
- wire s_count_reg_n_91;
- wire s_count_reg_n_92;
- wire s_count_reg_n_93;
- wire s_count_reg_n_94;
- wire s_count_reg_n_95;
- wire s_count_reg_n_96;
- wire s_count_reg_n_97;
- wire s_count_reg_n_98;
- wire s_count_reg_n_99;
- wire s_pulseLed_i_10__27_n_0;
- wire s_pulseLed_i_2__27_n_0;
- wire s_pulseLed_i_3__27_n_0;
- wire s_pulseLed_i_4__27_n_0;
- wire s_pulseLed_i_5__27_n_0;
- wire s_pulseLed_i_7__27_n_0;
- wire s_pulseLed_i_8__27_n_0;
- wire s_pulseLed_i_9__27_n_0;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED;
- wire NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED;
- wire NLW_s_count_reg_OVERFLOW_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED;
- wire NLW_s_count_reg_PATTERNDETECT_UNCONNECTED;
- wire NLW_s_count_reg_UNDERFLOW_UNCONNECTED;
- wire [29:0]NLW_s_count_reg_ACOUT_UNCONNECTED;
- wire [17:0]NLW_s_count_reg_BCOUT_UNCONNECTED;
- wire [3:0]NLW_s_count_reg_CARRYOUT_UNCONNECTED;
- wire [47:32]NLW_s_count_reg_P_UNCONNECTED;
- wire [47:0]NLW_s_count_reg_PCOUT_UNCONNECTED;
-
- (* METHODOLOGY_DRC_VIOS = "{SYNTH-12 {cell *THIS*}}" *)
- DSP48E1 #(
- .ACASCREG(1),
- .ADREG(1),
- .ALUMODEREG(0),
- .AREG(1),
- .AUTORESET_PATDET("NO_RESET"),
- .A_INPUT("DIRECT"),
- .BCASCREG(1),
- .BREG(1),
- .B_INPUT("DIRECT"),
- .CARRYINREG(0),
- .CARRYINSELREG(0),
- .CREG(0),
- .DREG(1),
- .INMODEREG(0),
- .MASK(48'h3FFFFFFFFFFF),
- .MREG(0),
- .OPMODEREG(0),
- .PATTERN(48'h000000000000),
- .PREG(1),
- .SEL_MASK("MASK"),
- .SEL_PATTERN("PATTERN"),
- .USE_DPORT("FALSE"),
- .USE_MULT("NONE"),
- .USE_PATTERN_DETECT("NO_PATDET"),
- .USE_SIMD("ONE48"))
- s_count_reg
- (.A({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ACOUT(NLW_s_count_reg_ACOUT_UNCONNECTED[29:0]),
- .ALUMODE({1'b0,1'b0,1'b0,1'b0}),
- .B({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
- .BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .BCOUT(NLW_s_count_reg_BCOUT_UNCONNECTED[17:0]),
- .C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
- .CARRYCASCIN(1'b0),
- .CARRYCASCOUT(NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED),
- .CARRYIN(1'b0),
- .CARRYINSEL({1'b0,1'b0,1'b0}),
- .CARRYOUT(NLW_s_count_reg_CARRYOUT_UNCONNECTED[3:0]),
- .CEA1(1'b0),
- .CEA2(1'b0),
- .CEAD(1'b0),
- .CEALUMODE(1'b0),
- .CEB1(1'b0),
- .CEB2(1'b0),
- .CEC(1'b0),
- .CECARRYIN(1'b0),
- .CECTRL(1'b0),
- .CED(1'b0),
- .CEINMODE(1'b0),
- .CEM(1'b0),
- .CEP(s_pulseLed_reg_0),
- .CLK(s00_axi_aclk),
- .D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .MULTSIGNIN(1'b0),
- .MULTSIGNOUT(NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED),
- .OPMODE({1'b0,1'b1,1'b1,1'b0,1'b0,1'b1,1'b0}),
- .OVERFLOW(NLW_s_count_reg_OVERFLOW_UNCONNECTED),
- .P({NLW_s_count_reg_P_UNCONNECTED[47:32],s_count_reg_n_74,s_count_reg_n_75,s_count_reg_n_76,s_count_reg_n_77,s_count_reg_n_78,s_count_reg_n_79,s_count_reg_n_80,s_count_reg_n_81,s_count_reg_n_82,s_count_reg_n_83,s_count_reg_n_84,s_count_reg_n_85,s_count_reg_n_86,s_count_reg_n_87,s_count_reg_n_88,s_count_reg_n_89,s_count_reg_n_90,s_count_reg_n_91,s_count_reg_n_92,s_count_reg_n_93,s_count_reg_n_94,s_count_reg_n_95,s_count_reg_n_96,s_count_reg_n_97,s_count_reg_n_98,s_count_reg_n_99,s_count_reg_n_100,s_count_reg_n_101,s_count_reg_n_102,s_count_reg_n_103,s_count_reg_n_104,s_count_reg_n_105}),
- .PATTERNBDETECT(NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED),
- .PATTERNDETECT(NLW_s_count_reg_PATTERNDETECT_UNCONNECTED),
- .PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .PCOUT(NLW_s_count_reg_PCOUT_UNCONNECTED[47:0]),
- .RSTA(1'b0),
- .RSTALLCARRYIN(1'b0),
- .RSTALUMODE(1'b0),
- .RSTB(1'b0),
- .RSTC(1'b0),
- .RSTCTRL(1'b0),
- .RSTD(1'b0),
- .RSTINMODE(1'b0),
- .RSTM(1'b0),
- .RSTP(s_buff2_reg),
- .UNDERFLOW(NLW_s_count_reg_UNDERFLOW_UNCONNECTED));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_10__27
- (.I0(s_count_reg_n_93),
- .I1(s_count_reg_n_92),
- .I2(s_count_reg_n_90),
- .I3(s_count_reg_n_91),
- .O(s_pulseLed_i_10__27_n_0));
- LUT6 #(
- .INIT(64'hFFFEFFFE0000FFFE))
- s_pulseLed_i_1__27
- (.I0(s_pulseLed_i_2__27_n_0),
- .I1(s_pulseLed_i_3__27_n_0),
- .I2(s_pulseLed_i_4__27_n_0),
- .I3(s_pulseLed_i_5__27_n_0),
- .I4(s_buff3_reg),
- .I5(s_pulseLed_reg_0),
- .O(s_pulseLed_reg));
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- s_pulseLed_i_2__27
- (.I0(s_count_reg_n_87),
- .I1(s_count_reg_n_86),
- .I2(s_count_reg_n_89),
- .I3(s_count_reg_n_88),
- .I4(s_pulseLed_i_7__27_n_0),
- .O(s_pulseLed_i_2__27_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_3__27
- (.I0(s_count_reg_n_79),
- .I1(s_count_reg_n_78),
- .I2(s_count_reg_n_81),
- .I3(s_count_reg_n_80),
- .I4(s_pulseLed_i_8__27_n_0),
- .O(s_pulseLed_i_3__27_n_0));
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- s_pulseLed_i_4__27
- (.I0(s_count_reg_n_103),
- .I1(s_count_reg_n_102),
- .I2(s_count_reg_n_105),
- .I3(s_count_reg_n_104),
- .I4(s_pulseLed_i_9__27_n_0),
- .O(s_pulseLed_i_4__27_n_0));
- LUT5 #(
- .INIT(32'hFFFFFBFF))
- s_pulseLed_i_5__27
- (.I0(s_count_reg_n_94),
- .I1(s_count_reg_n_95),
- .I2(s_count_reg_n_97),
- .I3(s_count_reg_n_96),
- .I4(s_pulseLed_i_10__27_n_0),
- .O(s_pulseLed_i_5__27_n_0));
- LUT4 #(
- .INIT(16'hFFDF))
- s_pulseLed_i_7__27
- (.I0(s_count_reg_n_85),
- .I1(s_count_reg_n_84),
- .I2(s_count_reg_n_82),
- .I3(s_count_reg_n_83),
- .O(s_pulseLed_i_7__27_n_0));
- LUT4 #(
- .INIT(16'hFFFE))
- s_pulseLed_i_8__27
- (.I0(s_count_reg_n_76),
- .I1(s_count_reg_n_77),
- .I2(s_count_reg_n_74),
- .I3(s_count_reg_n_75),
- .O(s_pulseLed_i_8__27_n_0));
- LUT4 #(
- .INIT(16'hFFEF))
- s_pulseLed_i_9__27
- (.I0(s_count_reg_n_100),
- .I1(s_count_reg_n_101),
- .I2(s_count_reg_n_98),
- .I3(s_count_reg_n_99),
- .O(s_pulseLed_i_9__27_n_0));
-endmodule
-
-(* ORIG_REF_NAME = "dac7716_spi" *)
-module system_design_fasec_hwtest_0_0_dac7716_spi
- (s_start,
- \dac_ch_o_reg[0][0]_0 ,
- \dac_ch_o_reg[0][0]_1 ,
- Q,
- \s_tx_data_reg[111]_0 ,
- \s_tx_data_reg[15]_0 ,
- \s_tx_data_reg[15]_1 ,
- \s_tx_data_reg[39]_0 ,
- \s_tx_data_reg[39]_1 ,
- \s_tx_data_reg[39]_2 ,
- \s_tx_data_reg[39]_3 ,
- \s_counter_reg[2] ,
- \axi_rdata_reg[31] ,
- s_spi_mosi,
- s_spi_cs_n,
- rst_i,
- s_start_reg_0,
- s00_axi_aclk,
- s00_axi_aresetn,
- \data_rw_o_reg[79][2] ,
- \data_rw_o_reg[87][11] ,
- \data_rw_o_reg[87][11]_0 ,
- \data_rw_o_reg[86][11] ,
- \data_rw_o_reg[86][11]_0 ,
- \data_rw_o_reg[85][11] ,
- \data_rw_o_reg[85][11]_0 ,
- \data_rw_o_reg[84][11] ,
- \data_rw_o_reg[84][11]_0 ,
- \data_rw_o_reg[88][11] ,
- \data_rw_o_reg[88][11]_0 ,
- \data_rw_o_reg[89][11] ,
- \data_rw_o_reg[89][11]_0 ,
- \data_rw_o_reg[90][11] ,
- \data_rw_o_reg[90][11]_0 ,
- \data_rw_o_reg[91][11] ,
- \data_rw_o_reg[91][11]_0 ,
- \data_rw_o_reg[92][11] ,
- \data_rw_o_reg[93][11] ,
- \data_rw_o_reg[94][11] ,
- \data_rw_o_reg[95][11] ,
- \data_rw_o_reg[96][11] ,
- \data_rw_o_reg[97][11] ,
- \data_rw_o_reg[98][11] ,
- \data_rw_o_reg[99][11] ,
- \data_rw_o_reg[100][11] ,
- \data_rw_o_reg[101][11] ,
- \data_rw_o_reg[102][11] ,
- \data_rw_o_reg[103][11] ,
- D);
- output s_start;
- output \dac_ch_o_reg[0][0]_0 ;
- output \dac_ch_o_reg[0][0]_1 ;
- output [11:0]Q;
- output [11:0]\s_tx_data_reg[111]_0 ;
- output [11:0]\s_tx_data_reg[15]_0 ;
- output [11:0]\s_tx_data_reg[15]_1 ;
- output [11:0]\s_tx_data_reg[39]_0 ;
- output [11:0]\s_tx_data_reg[39]_1 ;
- output [11:0]\s_tx_data_reg[39]_2 ;
- output [11:0]\s_tx_data_reg[39]_3 ;
- output [0:0]\s_counter_reg[2] ;
- output [31:0]\axi_rdata_reg[31] ;
- output s_spi_mosi;
- output s_spi_cs_n;
- input rst_i;
- input s_start_reg_0;
- input s00_axi_aclk;
- input s00_axi_aresetn;
- input [1:0]\data_rw_o_reg[79][2] ;
- input [11:0]\data_rw_o_reg[87][11] ;
- input [0:0]\data_rw_o_reg[87][11]_0 ;
- input [11:0]\data_rw_o_reg[86][11] ;
- input [0:0]\data_rw_o_reg[86][11]_0 ;
- input [11:0]\data_rw_o_reg[85][11] ;
- input [0:0]\data_rw_o_reg[85][11]_0 ;
- input [11:0]\data_rw_o_reg[84][11] ;
- input [0:0]\data_rw_o_reg[84][11]_0 ;
- input [11:0]\data_rw_o_reg[88][11] ;
- input [0:0]\data_rw_o_reg[88][11]_0 ;
- input [11:0]\data_rw_o_reg[89][11] ;
- input [0:0]\data_rw_o_reg[89][11]_0 ;
- input [11:0]\data_rw_o_reg[90][11] ;
- input [0:0]\data_rw_o_reg[90][11]_0 ;
- input [11:0]\data_rw_o_reg[91][11] ;
- input [0:0]\data_rw_o_reg[91][11]_0 ;
- input [11:0]\data_rw_o_reg[92][11] ;
- input [11:0]\data_rw_o_reg[93][11] ;
- input [11:0]\data_rw_o_reg[94][11] ;
- input [11:0]\data_rw_o_reg[95][11] ;
- input [11:0]\data_rw_o_reg[96][11] ;
- input [11:0]\data_rw_o_reg[97][11] ;
- input [11:0]\data_rw_o_reg[98][11] ;
- input [11:0]\data_rw_o_reg[99][11] ;
- input [11:0]\data_rw_o_reg[100][11] ;
- input [11:0]\data_rw_o_reg[101][11] ;
- input [11:0]\data_rw_o_reg[102][11] ;
- input [11:0]\data_rw_o_reg[103][11] ;
- input [0:0]D;
-
- wire [0:0]D;
- wire [11:0]Q;
- wire \[0].[0].s_reqs[0][changed]_i_1__0_n_0 ;
- wire \[0].[0].s_reqs_reg[0][changed_n_0_] ;
- wire \[0].[1].s_reqs[1][changed]_i_1__0_n_0 ;
- wire \[0].[1].s_reqs_reg[1][changed_n_0_] ;
- wire \[0].[2].s_reqs[2][changed]_i_1__0_n_0 ;
- wire \[0].[2].s_reqs_reg[2][changed_n_0_] ;
- wire \[0].[3].s_reqs[3][changed]_i_1__0_n_0 ;
- wire \[0].[3].s_reqs_reg[3][changed_n_0_] ;
- wire \[1].[0].s_reqs[4][changed]_i_1__0_n_0 ;
- wire \[1].[0].s_reqs_reg[4][changed]__1 ;
- wire \[1].[1].s_reqs[5][changed]_i_1__0_n_0 ;
- wire \[1].[1].s_reqs_reg[5][changed]__1 ;
- wire \[1].[2].s_reqs[6][changed]_i_1__0_n_0 ;
- wire \[1].[2].s_reqs_reg[6][changed]__1 ;
- wire \[1].[3].s_reqs[7][changed]_i_1__0_n_0 ;
- wire \[1].[3].s_reqs_reg[7][changed]__1 ;
- wire [11:0]\[2].[0].s_reqs_reg[8][value]__0__0 ;
- wire [11:0]\[2].[1].s_reqs_reg[9][value]__0__0 ;
- wire [11:0]\[2].[2].s_reqs_reg[10][value]__0__0 ;
- wire [11:0]\[2].[3].s_reqs_reg[11][value]__0__0 ;
- wire [11:0]\[3].[0].s_reqs_reg[12][value]__0__0 ;
- wire [11:0]\[3].[1].s_reqs_reg[13][value]__0__0 ;
- wire [11:0]\[3].[2].s_reqs_reg[14][value]__0__0 ;
- wire [11:0]\[3].[3].s_reqs_reg[15][value]__0__0 ;
- wire [11:0]\[4].[0].s_reqs_reg[16][value]__0__0 ;
- wire [11:0]\[4].[1].s_reqs_reg[17][value]__0__0 ;
- wire [11:0]\[4].[2].s_reqs_reg[18][value]__0__0 ;
- wire [11:0]\[4].[3].s_reqs_reg[19][value]__0__0 ;
- wire [31:0]\axi_rdata_reg[31] ;
- wire [1:0]ch_address;
- wire cmp_spi_n_0;
- wire cmp_spi_n_1;
- wire cmp_spi_n_2;
- wire cmp_spi_n_3;
- wire cmp_spi_n_4;
- wire \dac_ch_o[0][31]_i_2__0_n_0 ;
- wire \dac_ch_o_reg[0][0]_0 ;
- wire \dac_ch_o_reg[0][0]_1 ;
- wire [11:0]\data_rw_o_reg[100][11] ;
- wire [11:0]\data_rw_o_reg[101][11] ;
- wire [11:0]\data_rw_o_reg[102][11] ;
- wire [11:0]\data_rw_o_reg[103][11] ;
- wire [1:0]\data_rw_o_reg[79][2] ;
- wire [11:0]\data_rw_o_reg[84][11] ;
- wire [0:0]\data_rw_o_reg[84][11]_0 ;
- wire [11:0]\data_rw_o_reg[85][11] ;
- wire [0:0]\data_rw_o_reg[85][11]_0 ;
- wire [11:0]\data_rw_o_reg[86][11] ;
- wire [0:0]\data_rw_o_reg[86][11]_0 ;
- wire [11:0]\data_rw_o_reg[87][11] ;
- wire [0:0]\data_rw_o_reg[87][11]_0 ;
- wire [11:0]\data_rw_o_reg[88][11] ;
- wire [0:0]\data_rw_o_reg[88][11]_0 ;
- wire [11:0]\data_rw_o_reg[89][11] ;
- wire [0:0]\data_rw_o_reg[89][11]_0 ;
- wire [11:0]\data_rw_o_reg[90][11] ;
- wire [0:0]\data_rw_o_reg[90][11]_0 ;
- wire [11:0]\data_rw_o_reg[91][11] ;
- wire [0:0]\data_rw_o_reg[91][11]_0 ;
- wire [11:0]\data_rw_o_reg[92][11] ;
- wire [11:0]\data_rw_o_reg[93][11] ;
- wire [11:0]\data_rw_o_reg[94][11] ;
- wire [11:0]\data_rw_o_reg[95][11] ;
- wire [11:0]\data_rw_o_reg[96][11] ;
- wire [11:0]\data_rw_o_reg[97][11] ;
- wire [11:0]\data_rw_o_reg[98][11] ;
- wire [11:0]\data_rw_o_reg[99][11] ;
- wire p_0_in;
- wire p_1_in;
- wire p_2_in;
- wire rst_i;
- wire [31:0]rx_data_o;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]\s_counter_reg[2] ;
- wire \s_flag_reset[0]_i_1__0_n_0 ;
- wire \s_flag_reset[1]_i_1__0_n_0 ;
- wire \s_flag_reset[2]_i_1__0_n_0 ;
- wire \s_flag_reset[3]_i_1__0_n_0 ;
- wire \s_flag_reset_reg_n_0_[0] ;
- wire [11:0]\s_reqs[0][value] ;
- wire s_spi_cs_n;
- wire s_spi_mosi;
- wire s_start;
- wire s_start_reg_0;
- wire \s_state[1]_i_2__0_n_0 ;
- wire \s_state[1]_i_3__0_n_0 ;
- wire \s_state[1]_i_5__0_n_0 ;
- wire \s_tx_data[100]_i_1__0_n_0 ;
- wire \s_tx_data[100]_i_2__0_n_0 ;
- wire \s_tx_data[101]_i_1__0_n_0 ;
- wire \s_tx_data[101]_i_2__0_n_0 ;
- wire \s_tx_data[102]_i_1__0_n_0 ;
- wire \s_tx_data[102]_i_2__0_n_0 ;
- wire \s_tx_data[103]_i_1__0_n_0 ;
- wire \s_tx_data[103]_i_2__0_n_0 ;
- wire \s_tx_data[104]_i_1__0_n_0 ;
- wire \s_tx_data[104]_i_2__0_n_0 ;
- wire \s_tx_data[105]_i_1__0_n_0 ;
- wire \s_tx_data[105]_i_2__0_n_0 ;
- wire \s_tx_data[106]_i_1__0_n_0 ;
- wire \s_tx_data[106]_i_2__0_n_0 ;
- wire \s_tx_data[107]_i_1__0_n_0 ;
- wire \s_tx_data[107]_i_2__0_n_0 ;
- wire \s_tx_data[108]_i_1__0_n_0 ;
- wire \s_tx_data[108]_i_2__0_n_0 ;
- wire \s_tx_data[109]_i_1__0_n_0 ;
- wire \s_tx_data[109]_i_2__0_n_0 ;
- wire \s_tx_data[10]_i_2__0_n_0 ;
- wire \s_tx_data[110]_i_1__0_n_0 ;
- wire \s_tx_data[110]_i_2__0_n_0 ;
- wire \s_tx_data[111]_i_1__0_n_0 ;
- wire \s_tx_data[111]_i_2__0_n_0 ;
- wire \s_tx_data[113]_i_1__0_n_0 ;
- wire \s_tx_data[11]_i_2__0_n_0 ;
- wire \s_tx_data[12]_i_2__0_n_0 ;
- wire \s_tx_data[13]_i_2__0_n_0 ;
- wire \s_tx_data[14]_i_2__0_n_0 ;
- wire \s_tx_data[15]_i_2__0_n_0 ;
- wire \s_tx_data[28]_i_1__0_n_0 ;
- wire \s_tx_data[28]_i_2__0_n_0 ;
- wire \s_tx_data[29]_i_1__0_n_0 ;
- wire \s_tx_data[29]_i_2__0_n_0 ;
- wire \s_tx_data[30]_i_1__0_n_0 ;
- wire \s_tx_data[30]_i_2__0_n_0 ;
- wire \s_tx_data[31]_i_1__0_n_0 ;
- wire \s_tx_data[31]_i_2__0_n_0 ;
- wire \s_tx_data[32]_i_1__0_n_0 ;
- wire \s_tx_data[32]_i_2__0_n_0 ;
- wire \s_tx_data[33]_i_1__0_n_0 ;
- wire \s_tx_data[33]_i_2__0_n_0 ;
- wire \s_tx_data[34]_i_1__0_n_0 ;
- wire \s_tx_data[34]_i_2__0_n_0 ;
- wire \s_tx_data[35]_i_1__0_n_0 ;
- wire \s_tx_data[35]_i_2__0_n_0 ;
- wire \s_tx_data[36]_i_1__0_n_0 ;
- wire \s_tx_data[36]_i_2__0_n_0 ;
- wire \s_tx_data[37]_i_1__0_n_0 ;
- wire \s_tx_data[37]_i_2__0_n_0 ;
- wire \s_tx_data[38]_i_1__0_n_0 ;
- wire \s_tx_data[38]_i_2__0_n_0 ;
- wire \s_tx_data[39]_i_1__0_n_0 ;
- wire \s_tx_data[39]_i_2__0_n_0 ;
- wire \s_tx_data[4]_i_2__0_n_0 ;
- wire \s_tx_data[52]_i_1__0_n_0 ;
- wire \s_tx_data[52]_i_2__0_n_0 ;
- wire \s_tx_data[53]_i_1__0_n_0 ;
- wire \s_tx_data[53]_i_2__0_n_0 ;
- wire \s_tx_data[54]_i_1__0_n_0 ;
- wire \s_tx_data[54]_i_2__0_n_0 ;
- wire \s_tx_data[55]_i_1__0_n_0 ;
- wire \s_tx_data[55]_i_2__0_n_0 ;
- wire \s_tx_data[56]_i_1__0_n_0 ;
- wire \s_tx_data[56]_i_2__0_n_0 ;
- wire \s_tx_data[57]_i_1__0_n_0 ;
- wire \s_tx_data[57]_i_2__0_n_0 ;
- wire \s_tx_data[58]_i_1__0_n_0 ;
- wire \s_tx_data[58]_i_2__0_n_0 ;
- wire \s_tx_data[59]_i_1__0_n_0 ;
- wire \s_tx_data[59]_i_2__0_n_0 ;
- wire \s_tx_data[5]_i_2__0_n_0 ;
- wire \s_tx_data[60]_i_1__0_n_0 ;
- wire \s_tx_data[60]_i_2__0_n_0 ;
- wire \s_tx_data[61]_i_1__0_n_0 ;
- wire \s_tx_data[61]_i_2__0_n_0 ;
- wire \s_tx_data[62]_i_1__0_n_0 ;
- wire \s_tx_data[62]_i_2__0_n_0 ;
- wire \s_tx_data[63]_i_1__0_n_0 ;
- wire \s_tx_data[63]_i_2__0_n_0 ;
- wire \s_tx_data[6]_i_2__0_n_0 ;
- wire \s_tx_data[76]_i_1__0_n_0 ;
- wire \s_tx_data[76]_i_2__0_n_0 ;
- wire \s_tx_data[77]_i_1__0_n_0 ;
- wire \s_tx_data[77]_i_2__0_n_0 ;
- wire \s_tx_data[78]_i_1__0_n_0 ;
- wire \s_tx_data[78]_i_2__0_n_0 ;
- wire \s_tx_data[79]_i_1__0_n_0 ;
- wire \s_tx_data[79]_i_2__0_n_0 ;
- wire \s_tx_data[7]_i_2__0_n_0 ;
- wire \s_tx_data[80]_i_1__0_n_0 ;
- wire \s_tx_data[80]_i_2__0_n_0 ;
- wire \s_tx_data[81]_i_1__0_n_0 ;
- wire \s_tx_data[81]_i_2__0_n_0 ;
- wire \s_tx_data[82]_i_1__0_n_0 ;
- wire \s_tx_data[82]_i_2__0_n_0 ;
- wire \s_tx_data[83]_i_1__0_n_0 ;
- wire \s_tx_data[83]_i_2__0_n_0 ;
- wire \s_tx_data[84]_i_1__0_n_0 ;
- wire \s_tx_data[84]_i_2__0_n_0 ;
- wire \s_tx_data[85]_i_1__0_n_0 ;
- wire \s_tx_data[85]_i_2__0_n_0 ;
- wire \s_tx_data[86]_i_1__0_n_0 ;
- wire \s_tx_data[86]_i_2__0_n_0 ;
- wire \s_tx_data[87]_i_1__0_n_0 ;
- wire \s_tx_data[87]_i_2__0_n_0 ;
- wire \s_tx_data[8]_i_2__0_n_0 ;
- wire \s_tx_data[9]_i_2__0_n_0 ;
- wire [11:0]\s_tx_data_reg[111]_0 ;
- wire [11:0]\s_tx_data_reg[15]_0 ;
- wire [11:0]\s_tx_data_reg[15]_1 ;
- wire [11:0]\s_tx_data_reg[39]_0 ;
- wire [11:0]\s_tx_data_reg[39]_1 ;
- wire [11:0]\s_tx_data_reg[39]_2 ;
- wire [11:0]\s_tx_data_reg[39]_3 ;
- wire \s_tx_data_reg_n_0_[100] ;
- wire \s_tx_data_reg_n_0_[101] ;
- wire \s_tx_data_reg_n_0_[102] ;
- wire \s_tx_data_reg_n_0_[103] ;
- wire \s_tx_data_reg_n_0_[104] ;
- wire \s_tx_data_reg_n_0_[105] ;
- wire \s_tx_data_reg_n_0_[106] ;
- wire \s_tx_data_reg_n_0_[107] ;
- wire \s_tx_data_reg_n_0_[108] ;
- wire \s_tx_data_reg_n_0_[109] ;
- wire \s_tx_data_reg_n_0_[10] ;
- wire \s_tx_data_reg_n_0_[110] ;
- wire \s_tx_data_reg_n_0_[111] ;
- wire \s_tx_data_reg_n_0_[112] ;
- wire \s_tx_data_reg_n_0_[113] ;
- wire \s_tx_data_reg_n_0_[11] ;
- wire \s_tx_data_reg_n_0_[12] ;
- wire \s_tx_data_reg_n_0_[13] ;
- wire \s_tx_data_reg_n_0_[14] ;
- wire \s_tx_data_reg_n_0_[15] ;
- wire \s_tx_data_reg_n_0_[28] ;
- wire \s_tx_data_reg_n_0_[29] ;
- wire \s_tx_data_reg_n_0_[30] ;
- wire \s_tx_data_reg_n_0_[31] ;
- wire \s_tx_data_reg_n_0_[32] ;
- wire \s_tx_data_reg_n_0_[33] ;
- wire \s_tx_data_reg_n_0_[34] ;
- wire \s_tx_data_reg_n_0_[35] ;
- wire \s_tx_data_reg_n_0_[36] ;
- wire \s_tx_data_reg_n_0_[37] ;
- wire \s_tx_data_reg_n_0_[38] ;
- wire \s_tx_data_reg_n_0_[39] ;
- wire \s_tx_data_reg_n_0_[4] ;
- wire \s_tx_data_reg_n_0_[52] ;
- wire \s_tx_data_reg_n_0_[53] ;
- wire \s_tx_data_reg_n_0_[54] ;
- wire \s_tx_data_reg_n_0_[55] ;
- wire \s_tx_data_reg_n_0_[56] ;
- wire \s_tx_data_reg_n_0_[57] ;
- wire \s_tx_data_reg_n_0_[58] ;
- wire \s_tx_data_reg_n_0_[59] ;
- wire \s_tx_data_reg_n_0_[5] ;
- wire \s_tx_data_reg_n_0_[60] ;
- wire \s_tx_data_reg_n_0_[61] ;
- wire \s_tx_data_reg_n_0_[62] ;
- wire \s_tx_data_reg_n_0_[63] ;
- wire \s_tx_data_reg_n_0_[6] ;
- wire \s_tx_data_reg_n_0_[76] ;
- wire \s_tx_data_reg_n_0_[77] ;
- wire \s_tx_data_reg_n_0_[78] ;
- wire \s_tx_data_reg_n_0_[79] ;
- wire \s_tx_data_reg_n_0_[7] ;
- wire \s_tx_data_reg_n_0_[80] ;
- wire \s_tx_data_reg_n_0_[81] ;
- wire \s_tx_data_reg_n_0_[82] ;
- wire \s_tx_data_reg_n_0_[83] ;
- wire \s_tx_data_reg_n_0_[84] ;
- wire \s_tx_data_reg_n_0_[85] ;
- wire \s_tx_data_reg_n_0_[86] ;
- wire \s_tx_data_reg_n_0_[87] ;
- wire \s_tx_data_reg_n_0_[8] ;
- wire \s_tx_data_reg_n_0_[9] ;
- wire \v_ch_address[1]_i_3__0_n_0 ;
- wire \v_ch_address[1]_i_5__0_n_0 ;
-
- (* SOFT_HLUTNM = "soft_lutpair56" *)
- LUT3 #(
- .INIT(8'h0E))
- \[0].[0].s_reqs[0][changed]_i_1__0
- (.I0(\[0].[0].s_reqs_reg[0][changed_n_0_] ),
- .I1(\data_rw_o_reg[84][11]_0 ),
- .I2(\s_flag_reset_reg_n_0_[0] ),
- .O(\[0].[0].s_reqs[0][changed]_i_1__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[0].[0].s_reqs[0][changed]_i_1__0_n_0 ),
- .Q(\[0].[0].s_reqs_reg[0][changed_n_0_] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[84][11] [0]),
- .Q(\s_tx_data_reg[111]_0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[84][11] [10]),
- .Q(\s_tx_data_reg[111]_0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[84][11] [11]),
- .Q(\s_tx_data_reg[111]_0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[84][11] [1]),
- .Q(\s_tx_data_reg[111]_0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[84][11] [2]),
- .Q(\s_tx_data_reg[111]_0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[84][11] [3]),
- .Q(\s_tx_data_reg[111]_0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[84][11] [4]),
- .Q(\s_tx_data_reg[111]_0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[84][11] [5]),
- .Q(\s_tx_data_reg[111]_0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[84][11] [6]),
- .Q(\s_tx_data_reg[111]_0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[84][11] [7]),
- .Q(\s_tx_data_reg[111]_0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[84][11] [8]),
- .Q(\s_tx_data_reg[111]_0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[84][11] [9]),
- .Q(\s_tx_data_reg[111]_0 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair54" *)
- LUT3 #(
- .INIT(8'h0E))
- \[0].[1].s_reqs[1][changed]_i_1__0
- (.I0(\[0].[1].s_reqs_reg[1][changed_n_0_] ),
- .I1(\data_rw_o_reg[85][11]_0 ),
- .I2(p_2_in),
- .O(\[0].[1].s_reqs[1][changed]_i_1__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[0].[1].s_reqs[1][changed]_i_1__0_n_0 ),
- .Q(\[0].[1].s_reqs_reg[1][changed_n_0_] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[85][11] [0]),
- .Q(\s_tx_data_reg[15]_0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[85][11] [10]),
- .Q(\s_tx_data_reg[15]_0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[85][11] [11]),
- .Q(\s_tx_data_reg[15]_0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[85][11] [1]),
- .Q(\s_tx_data_reg[15]_0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[85][11] [2]),
- .Q(\s_tx_data_reg[15]_0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[85][11] [3]),
- .Q(\s_tx_data_reg[15]_0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[85][11] [4]),
- .Q(\s_tx_data_reg[15]_0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[85][11] [5]),
- .Q(\s_tx_data_reg[15]_0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[85][11] [6]),
- .Q(\s_tx_data_reg[15]_0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[85][11] [7]),
- .Q(\s_tx_data_reg[15]_0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[85][11] [8]),
- .Q(\s_tx_data_reg[15]_0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[85][11] [9]),
- .Q(\s_tx_data_reg[15]_0 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair55" *)
- LUT3 #(
- .INIT(8'h0E))
- \[0].[2].s_reqs[2][changed]_i_1__0
- (.I0(\[0].[2].s_reqs_reg[2][changed_n_0_] ),
- .I1(\data_rw_o_reg[86][11]_0 ),
- .I2(p_1_in),
- .O(\[0].[2].s_reqs[2][changed]_i_1__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[0].[2].s_reqs[2][changed]_i_1__0_n_0 ),
- .Q(\[0].[2].s_reqs_reg[2][changed_n_0_] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[86][11] [0]),
- .Q(\s_tx_data_reg[15]_1 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[86][11] [10]),
- .Q(\s_tx_data_reg[15]_1 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[86][11] [11]),
- .Q(\s_tx_data_reg[15]_1 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[86][11] [1]),
- .Q(\s_tx_data_reg[15]_1 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[86][11] [2]),
- .Q(\s_tx_data_reg[15]_1 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[86][11] [3]),
- .Q(\s_tx_data_reg[15]_1 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[86][11] [4]),
- .Q(\s_tx_data_reg[15]_1 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[86][11] [5]),
- .Q(\s_tx_data_reg[15]_1 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[86][11] [6]),
- .Q(\s_tx_data_reg[15]_1 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[86][11] [7]),
- .Q(\s_tx_data_reg[15]_1 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[86][11] [8]),
- .Q(\s_tx_data_reg[15]_1 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[86][11] [9]),
- .Q(\s_tx_data_reg[15]_1 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair57" *)
- LUT3 #(
- .INIT(8'h0E))
- \[0].[3].s_reqs[3][changed]_i_1__0
- (.I0(\[0].[3].s_reqs_reg[3][changed_n_0_] ),
- .I1(\data_rw_o_reg[87][11]_0 ),
- .I2(p_0_in),
- .O(\[0].[3].s_reqs[3][changed]_i_1__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[0].[3].s_reqs[3][changed]_i_1__0_n_0 ),
- .Q(\[0].[3].s_reqs_reg[3][changed_n_0_] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[87][11] [0]),
- .Q(Q[0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[87][11] [10]),
- .Q(Q[10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[87][11] [11]),
- .Q(Q[11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[87][11] [1]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[87][11] [2]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[87][11] [3]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[87][11] [4]),
- .Q(Q[4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[87][11] [5]),
- .Q(Q[5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[87][11] [6]),
- .Q(Q[6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[87][11] [7]),
- .Q(Q[7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[87][11] [8]),
- .Q(Q[8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[87][11] [9]),
- .Q(Q[9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair56" *)
- LUT3 #(
- .INIT(8'h0E))
- \[1].[0].s_reqs[4][changed]_i_1__0
- (.I0(\[1].[0].s_reqs_reg[4][changed]__1 ),
- .I1(\data_rw_o_reg[88][11]_0 ),
- .I2(\s_flag_reset_reg_n_0_[0] ),
- .O(\[1].[0].s_reqs[4][changed]_i_1__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[1].[0].s_reqs[4][changed]_i_1__0_n_0 ),
- .Q(\[1].[0].s_reqs_reg[4][changed]__1 ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[88][11] [0]),
- .Q(\s_tx_data_reg[39]_1 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[88][11] [10]),
- .Q(\s_tx_data_reg[39]_1 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[88][11] [11]),
- .Q(\s_tx_data_reg[39]_1 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[88][11] [1]),
- .Q(\s_tx_data_reg[39]_1 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[88][11] [2]),
- .Q(\s_tx_data_reg[39]_1 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[88][11] [3]),
- .Q(\s_tx_data_reg[39]_1 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[88][11] [4]),
- .Q(\s_tx_data_reg[39]_1 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[88][11] [5]),
- .Q(\s_tx_data_reg[39]_1 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[88][11] [6]),
- .Q(\s_tx_data_reg[39]_1 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[88][11] [7]),
- .Q(\s_tx_data_reg[39]_1 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[88][11] [8]),
- .Q(\s_tx_data_reg[39]_1 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[88][11] [9]),
- .Q(\s_tx_data_reg[39]_1 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair54" *)
- LUT3 #(
- .INIT(8'h0E))
- \[1].[1].s_reqs[5][changed]_i_1__0
- (.I0(\[1].[1].s_reqs_reg[5][changed]__1 ),
- .I1(\data_rw_o_reg[89][11]_0 ),
- .I2(p_2_in),
- .O(\[1].[1].s_reqs[5][changed]_i_1__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[1].[1].s_reqs[5][changed]_i_1__0_n_0 ),
- .Q(\[1].[1].s_reqs_reg[5][changed]__1 ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[89][11] [0]),
- .Q(\s_tx_data_reg[39]_2 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[89][11] [10]),
- .Q(\s_tx_data_reg[39]_2 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[89][11] [11]),
- .Q(\s_tx_data_reg[39]_2 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[89][11] [1]),
- .Q(\s_tx_data_reg[39]_2 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[89][11] [2]),
- .Q(\s_tx_data_reg[39]_2 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[89][11] [3]),
- .Q(\s_tx_data_reg[39]_2 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[89][11] [4]),
- .Q(\s_tx_data_reg[39]_2 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[89][11] [5]),
- .Q(\s_tx_data_reg[39]_2 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[89][11] [6]),
- .Q(\s_tx_data_reg[39]_2 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[89][11] [7]),
- .Q(\s_tx_data_reg[39]_2 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[89][11] [8]),
- .Q(\s_tx_data_reg[39]_2 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[89][11] [9]),
- .Q(\s_tx_data_reg[39]_2 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair55" *)
- LUT3 #(
- .INIT(8'h0E))
- \[1].[2].s_reqs[6][changed]_i_1__0
- (.I0(\[1].[2].s_reqs_reg[6][changed]__1 ),
- .I1(\data_rw_o_reg[90][11]_0 ),
- .I2(p_1_in),
- .O(\[1].[2].s_reqs[6][changed]_i_1__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[1].[2].s_reqs[6][changed]_i_1__0_n_0 ),
- .Q(\[1].[2].s_reqs_reg[6][changed]__1 ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[90][11] [0]),
- .Q(\s_tx_data_reg[39]_3 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[90][11] [10]),
- .Q(\s_tx_data_reg[39]_3 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[90][11] [11]),
- .Q(\s_tx_data_reg[39]_3 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[90][11] [1]),
- .Q(\s_tx_data_reg[39]_3 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[90][11] [2]),
- .Q(\s_tx_data_reg[39]_3 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[90][11] [3]),
- .Q(\s_tx_data_reg[39]_3 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[90][11] [4]),
- .Q(\s_tx_data_reg[39]_3 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[90][11] [5]),
- .Q(\s_tx_data_reg[39]_3 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[90][11] [6]),
- .Q(\s_tx_data_reg[39]_3 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[90][11] [7]),
- .Q(\s_tx_data_reg[39]_3 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[90][11] [8]),
- .Q(\s_tx_data_reg[39]_3 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[90][11] [9]),
- .Q(\s_tx_data_reg[39]_3 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair57" *)
- LUT3 #(
- .INIT(8'h0E))
- \[1].[3].s_reqs[7][changed]_i_1__0
- (.I0(\[1].[3].s_reqs_reg[7][changed]__1 ),
- .I1(\data_rw_o_reg[91][11]_0 ),
- .I2(p_0_in),
- .O(\[1].[3].s_reqs[7][changed]_i_1__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[1].[3].s_reqs[7][changed]_i_1__0_n_0 ),
- .Q(\[1].[3].s_reqs_reg[7][changed]__1 ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[91][11] [0]),
- .Q(\s_tx_data_reg[39]_0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[91][11] [10]),
- .Q(\s_tx_data_reg[39]_0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[91][11] [11]),
- .Q(\s_tx_data_reg[39]_0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[91][11] [1]),
- .Q(\s_tx_data_reg[39]_0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[91][11] [2]),
- .Q(\s_tx_data_reg[39]_0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[91][11] [3]),
- .Q(\s_tx_data_reg[39]_0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[91][11] [4]),
- .Q(\s_tx_data_reg[39]_0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[91][11] [5]),
- .Q(\s_tx_data_reg[39]_0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[91][11] [6]),
- .Q(\s_tx_data_reg[39]_0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[91][11] [7]),
- .Q(\s_tx_data_reg[39]_0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[91][11] [8]),
- .Q(\s_tx_data_reg[39]_0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[91][11] [9]),
- .Q(\s_tx_data_reg[39]_0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[92][11] [0]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[92][11] [10]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[92][11] [11]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[92][11] [1]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[92][11] [2]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[92][11] [3]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[92][11] [4]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[92][11] [5]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[92][11] [6]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[92][11] [7]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[92][11] [8]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[92][11] [9]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[93][11] [0]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[93][11] [10]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[93][11] [11]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[93][11] [1]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[93][11] [2]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[93][11] [3]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[93][11] [4]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[93][11] [5]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[93][11] [6]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[93][11] [7]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[93][11] [8]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[93][11] [9]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[94][11] [0]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[94][11] [10]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[94][11] [11]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[94][11] [1]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[94][11] [2]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[94][11] [3]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[94][11] [4]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[94][11] [5]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[94][11] [6]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[94][11] [7]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[94][11] [8]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[94][11] [9]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[95][11] [0]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[95][11] [10]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[95][11] [11]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[95][11] [1]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[95][11] [2]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[95][11] [3]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[95][11] [4]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[95][11] [5]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[95][11] [6]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[95][11] [7]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[95][11] [8]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[95][11] [9]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[96][11] [0]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[96][11] [10]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[96][11] [11]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[96][11] [1]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[96][11] [2]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[96][11] [3]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[96][11] [4]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[96][11] [5]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[96][11] [6]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[96][11] [7]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[96][11] [8]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[96][11] [9]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[97][11] [0]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[97][11] [10]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[97][11] [11]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[97][11] [1]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[97][11] [2]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[97][11] [3]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[97][11] [4]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[97][11] [5]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[97][11] [6]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[97][11] [7]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[97][11] [8]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[97][11] [9]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[98][11] [0]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[98][11] [10]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[98][11] [11]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[98][11] [1]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[98][11] [2]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[98][11] [3]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[98][11] [4]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[98][11] [5]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[98][11] [6]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[98][11] [7]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[98][11] [8]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[98][11] [9]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[99][11] [0]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[99][11] [10]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[99][11] [11]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[99][11] [1]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[99][11] [2]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[99][11] [3]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[99][11] [4]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[99][11] [5]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[99][11] [6]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[99][11] [7]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[99][11] [8]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[99][11] [9]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[100][11] [0]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[100][11] [10]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[100][11] [11]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[100][11] [1]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[100][11] [2]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[100][11] [3]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[100][11] [4]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[100][11] [5]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[100][11] [6]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[100][11] [7]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[100][11] [8]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[100][11] [9]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[101][11] [0]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[101][11] [10]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[101][11] [11]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[101][11] [1]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[101][11] [2]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[101][11] [3]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[101][11] [4]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[101][11] [5]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[101][11] [6]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[101][11] [7]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[101][11] [8]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[101][11] [9]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[102][11] [0]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[102][11] [10]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[102][11] [11]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[102][11] [1]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[102][11] [2]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[102][11] [3]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[102][11] [4]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[102][11] [5]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[102][11] [6]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[102][11] [7]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[102][11] [8]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[102][11] [9]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[103][11] [0]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[103][11] [10]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[103][11] [11]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[103][11] [1]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[103][11] [2]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[103][11] [3]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[103][11] [4]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[103][11] [5]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[103][11] [6]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[103][11] [7]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[103][11] [8]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[103][11] [9]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0__0 [9]),
- .R(1'b0));
- system_design_fasec_hwtest_0_0_spi_transceiver cmp_spi
- (.D(D),
- .E(cmp_spi_n_0),
- .Q(\s_counter_reg[2] ),
- .\[0].[2].s_reqs_reg[2][changed] (\[0].[2].s_reqs_reg[2][changed_n_0_] ),
- .\[0].[2].s_reqs_reg[2][changed]_0 (\s_state[1]_i_2__0_n_0 ),
- .\[0].[3].s_reqs_reg[3][changed] (\s_state[1]_i_3__0_n_0 ),
- .ch_address(ch_address),
- .\dac_ch_o_reg[0][31] (rx_data_o),
- .\data_rw_o_reg[79][1] (\v_ch_address[1]_i_3__0_n_0 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_spi_cs_n(s_spi_cs_n),
- .s_spi_mosi(s_spi_mosi),
- .s_start_reg(s_start),
- .\s_state_reg[0] (cmp_spi_n_3),
- .\s_state_reg[0]_0 (\dac_ch_o_reg[0][0]_1 ),
- .\s_state_reg[1] (cmp_spi_n_4),
- .\s_state_reg[1]_0 (\dac_ch_o_reg[0][0]_0 ),
- .\s_tx_data_reg[113] ({\s_tx_data_reg_n_0_[113] ,\s_tx_data_reg_n_0_[112] ,\s_tx_data_reg_n_0_[111] ,\s_tx_data_reg_n_0_[110] ,\s_tx_data_reg_n_0_[109] ,\s_tx_data_reg_n_0_[108] ,\s_tx_data_reg_n_0_[107] ,\s_tx_data_reg_n_0_[106] ,\s_tx_data_reg_n_0_[105] ,\s_tx_data_reg_n_0_[104] ,\s_tx_data_reg_n_0_[103] ,\s_tx_data_reg_n_0_[102] ,\s_tx_data_reg_n_0_[101] ,\s_tx_data_reg_n_0_[100] ,\s_tx_data_reg_n_0_[87] ,\s_tx_data_reg_n_0_[86] ,\s_tx_data_reg_n_0_[85] ,\s_tx_data_reg_n_0_[84] ,\s_tx_data_reg_n_0_[83] ,\s_tx_data_reg_n_0_[82] ,\s_tx_data_reg_n_0_[81] ,\s_tx_data_reg_n_0_[80] ,\s_tx_data_reg_n_0_[79] ,\s_tx_data_reg_n_0_[78] ,\s_tx_data_reg_n_0_[77] ,\s_tx_data_reg_n_0_[76] ,\s_tx_data_reg_n_0_[63] ,\s_tx_data_reg_n_0_[62] ,\s_tx_data_reg_n_0_[61] ,\s_tx_data_reg_n_0_[60] ,\s_tx_data_reg_n_0_[59] ,\s_tx_data_reg_n_0_[58] ,\s_tx_data_reg_n_0_[57] ,\s_tx_data_reg_n_0_[56] ,\s_tx_data_reg_n_0_[55] ,\s_tx_data_reg_n_0_[54] ,\s_tx_data_reg_n_0_[53] ,\s_tx_data_reg_n_0_[52] ,\s_tx_data_reg_n_0_[39] ,\s_tx_data_reg_n_0_[38] ,\s_tx_data_reg_n_0_[37] ,\s_tx_data_reg_n_0_[36] ,\s_tx_data_reg_n_0_[35] ,\s_tx_data_reg_n_0_[34] ,\s_tx_data_reg_n_0_[33] ,\s_tx_data_reg_n_0_[32] ,\s_tx_data_reg_n_0_[31] ,\s_tx_data_reg_n_0_[30] ,\s_tx_data_reg_n_0_[29] ,\s_tx_data_reg_n_0_[28] ,\s_tx_data_reg_n_0_[15] ,\s_tx_data_reg_n_0_[14] ,\s_tx_data_reg_n_0_[13] ,\s_tx_data_reg_n_0_[12] ,\s_tx_data_reg_n_0_[11] ,\s_tx_data_reg_n_0_[10] ,\s_tx_data_reg_n_0_[9] ,\s_tx_data_reg_n_0_[8] ,\s_tx_data_reg_n_0_[7] ,\s_tx_data_reg_n_0_[6] ,\s_tx_data_reg_n_0_[5] ,\s_tx_data_reg_n_0_[4] }),
- .\v_ch_address_reg[0] (cmp_spi_n_1),
- .\v_ch_address_reg[0]_0 (\dac_ch_o[0][31]_i_2__0_n_0 ),
- .\v_ch_address_reg[1] (cmp_spi_n_2));
- (* SOFT_HLUTNM = "soft_lutpair53" *)
- LUT2 #(
- .INIT(4'h7))
- \dac_ch_o[0][31]_i_2__0
- (.I0(ch_address[0]),
- .I1(ch_address[1]),
- .O(\dac_ch_o[0][31]_i_2__0_n_0 ));
- FDRE \dac_ch_o_reg[0][0]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[0]),
- .Q(\axi_rdata_reg[31] [0]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][10]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[10]),
- .Q(\axi_rdata_reg[31] [10]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][11]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[11]),
- .Q(\axi_rdata_reg[31] [11]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][12]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[12]),
- .Q(\axi_rdata_reg[31] [12]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][13]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[13]),
- .Q(\axi_rdata_reg[31] [13]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][14]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[14]),
- .Q(\axi_rdata_reg[31] [14]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][15]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[15]),
- .Q(\axi_rdata_reg[31] [15]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][16]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[16]),
- .Q(\axi_rdata_reg[31] [16]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][17]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[17]),
- .Q(\axi_rdata_reg[31] [17]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][18]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[18]),
- .Q(\axi_rdata_reg[31] [18]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][19]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[19]),
- .Q(\axi_rdata_reg[31] [19]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][1]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[1]),
- .Q(\axi_rdata_reg[31] [1]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][20]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[20]),
- .Q(\axi_rdata_reg[31] [20]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][21]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[21]),
- .Q(\axi_rdata_reg[31] [21]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][22]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[22]),
- .Q(\axi_rdata_reg[31] [22]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][23]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[23]),
- .Q(\axi_rdata_reg[31] [23]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][24]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[24]),
- .Q(\axi_rdata_reg[31] [24]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][25]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[25]),
- .Q(\axi_rdata_reg[31] [25]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][26]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[26]),
- .Q(\axi_rdata_reg[31] [26]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][27]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[27]),
- .Q(\axi_rdata_reg[31] [27]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][28]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[28]),
- .Q(\axi_rdata_reg[31] [28]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][29]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[29]),
- .Q(\axi_rdata_reg[31] [29]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][2]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[2]),
- .Q(\axi_rdata_reg[31] [2]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][30]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[30]),
- .Q(\axi_rdata_reg[31] [30]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][31]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[31]),
- .Q(\axi_rdata_reg[31] [31]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][3]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[3]),
- .Q(\axi_rdata_reg[31] [3]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][4]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[4]),
- .Q(\axi_rdata_reg[31] [4]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][5]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[5]),
- .Q(\axi_rdata_reg[31] [5]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][6]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[6]),
- .Q(\axi_rdata_reg[31] [6]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][7]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[7]),
- .Q(\axi_rdata_reg[31] [7]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][8]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[8]),
- .Q(\axi_rdata_reg[31] [8]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][9]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[9]),
- .Q(\axi_rdata_reg[31] [9]),
- .R(1'b0));
- LUT5 #(
- .INIT(32'hFFF70004))
- \s_flag_reset[0]_i_1__0
- (.I0(\dac_ch_o_reg[0][0]_1 ),
- .I1(\dac_ch_o_reg[0][0]_0 ),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_flag_reset_reg_n_0_[0] ),
- .O(\s_flag_reset[0]_i_1__0_n_0 ));
- LUT5 #(
- .INIT(32'hDFFF1000))
- \s_flag_reset[1]_i_1__0
- (.I0(\dac_ch_o_reg[0][0]_1 ),
- .I1(ch_address[1]),
- .I2(\dac_ch_o_reg[0][0]_0 ),
- .I3(ch_address[0]),
- .I4(p_2_in),
- .O(\s_flag_reset[1]_i_1__0_n_0 ));
- LUT5 #(
- .INIT(32'hFF7F0040))
- \s_flag_reset[2]_i_1__0
- (.I0(\dac_ch_o_reg[0][0]_1 ),
- .I1(\dac_ch_o_reg[0][0]_0 ),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(p_1_in),
- .O(\s_flag_reset[2]_i_1__0_n_0 ));
- LUT5 #(
- .INIT(32'h7FFF4000))
- \s_flag_reset[3]_i_1__0
- (.I0(\dac_ch_o_reg[0][0]_1 ),
- .I1(\dac_ch_o_reg[0][0]_0 ),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(p_0_in),
- .O(\s_flag_reset[3]_i_1__0_n_0 ));
- FDRE \s_flag_reset_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_flag_reset[0]_i_1__0_n_0 ),
- .Q(\s_flag_reset_reg_n_0_[0] ),
- .R(rst_i));
- FDRE \s_flag_reset_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_flag_reset[1]_i_1__0_n_0 ),
- .Q(p_2_in),
- .R(rst_i));
- FDRE \s_flag_reset_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_flag_reset[2]_i_1__0_n_0 ),
- .Q(p_1_in),
- .R(rst_i));
- FDRE \s_flag_reset_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_flag_reset[3]_i_1__0_n_0 ),
- .Q(p_0_in),
- .R(rst_i));
- FDRE s_start_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_start_reg_0),
- .Q(s_start),
- .R(rst_i));
- LUT6 #(
- .INIT(64'h0C00080808080808))
- \s_state[1]_i_2__0
- (.I0(\[0].[2].s_reqs_reg[2][changed_n_0_] ),
- .I1(\dac_ch_o_reg[0][0]_1 ),
- .I2(\dac_ch_o_reg[0][0]_0 ),
- .I3(\[1].[3].s_reqs_reg[7][changed]__1 ),
- .I4(ch_address[1]),
- .I5(ch_address[0]),
- .O(\s_state[1]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'h0000FFFE00000000))
- \s_state[1]_i_3__0
- (.I0(\[0].[3].s_reqs_reg[3][changed_n_0_] ),
- .I1(\[1].[0].s_reqs_reg[4][changed]__1 ),
- .I2(\data_rw_o_reg[79][2] [0]),
- .I3(\s_state[1]_i_5__0_n_0 ),
- .I4(\dac_ch_o_reg[0][0]_0 ),
- .I5(\dac_ch_o_reg[0][0]_1 ),
- .O(\s_state[1]_i_3__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFE2F0F0FFE2))
- \s_state[1]_i_5__0
- (.I0(\[0].[0].s_reqs_reg[0][changed_n_0_] ),
- .I1(ch_address[0]),
- .I2(\[1].[1].s_reqs_reg[5][changed]__1 ),
- .I3(\[0].[1].s_reqs_reg[1][changed_n_0_] ),
- .I4(ch_address[1]),
- .I5(\[1].[2].s_reqs_reg[6][changed]__1 ),
- .O(\s_state[1]_i_5__0_n_0 ));
- FDRE \s_state_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(cmp_spi_n_3),
- .Q(\dac_ch_o_reg[0][0]_1 ),
- .R(rst_i));
- FDRE \s_state_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(cmp_spi_n_4),
- .Q(\dac_ch_o_reg[0][0]_0 ),
- .R(rst_i));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[100]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [0]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0__0 [0]),
- .I5(\s_tx_data[100]_i_2__0_n_0 ),
- .O(\s_tx_data[100]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[100]_i_2__0
- (.I0(\[4].[0].s_reqs_reg[16][value]__0__0 [0]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0__0 [0]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0__0 [0]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[100]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[101]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [1]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0__0 [1]),
- .I5(\s_tx_data[101]_i_2__0_n_0 ),
- .O(\s_tx_data[101]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[101]_i_2__0
- (.I0(\[4].[0].s_reqs_reg[16][value]__0__0 [1]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0__0 [1]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0__0 [1]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[101]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[102]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [2]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0__0 [2]),
- .I5(\s_tx_data[102]_i_2__0_n_0 ),
- .O(\s_tx_data[102]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[102]_i_2__0
- (.I0(\[4].[0].s_reqs_reg[16][value]__0__0 [2]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0__0 [2]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0__0 [2]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[102]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[103]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [3]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0__0 [3]),
- .I5(\s_tx_data[103]_i_2__0_n_0 ),
- .O(\s_tx_data[103]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[103]_i_2__0
- (.I0(\[4].[0].s_reqs_reg[16][value]__0__0 [3]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0__0 [3]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0__0 [3]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[103]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[104]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [4]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0__0 [4]),
- .I5(\s_tx_data[104]_i_2__0_n_0 ),
- .O(\s_tx_data[104]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[104]_i_2__0
- (.I0(\[4].[0].s_reqs_reg[16][value]__0__0 [4]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0__0 [4]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0__0 [4]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[104]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[105]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [5]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0__0 [5]),
- .I5(\s_tx_data[105]_i_2__0_n_0 ),
- .O(\s_tx_data[105]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[105]_i_2__0
- (.I0(\[4].[0].s_reqs_reg[16][value]__0__0 [5]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0__0 [5]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0__0 [5]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[105]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[106]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [6]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0__0 [6]),
- .I5(\s_tx_data[106]_i_2__0_n_0 ),
- .O(\s_tx_data[106]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[106]_i_2__0
- (.I0(\[4].[0].s_reqs_reg[16][value]__0__0 [6]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0__0 [6]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0__0 [6]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[106]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[107]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [7]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0__0 [7]),
- .I5(\s_tx_data[107]_i_2__0_n_0 ),
- .O(\s_tx_data[107]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[107]_i_2__0
- (.I0(\[4].[0].s_reqs_reg[16][value]__0__0 [7]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0__0 [7]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0__0 [7]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[107]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[108]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [8]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0__0 [8]),
- .I5(\s_tx_data[108]_i_2__0_n_0 ),
- .O(\s_tx_data[108]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[108]_i_2__0
- (.I0(\[4].[0].s_reqs_reg[16][value]__0__0 [8]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0__0 [8]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0__0 [8]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[108]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[109]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [9]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0__0 [9]),
- .I5(\s_tx_data[109]_i_2__0_n_0 ),
- .O(\s_tx_data[109]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[109]_i_2__0
- (.I0(\[4].[0].s_reqs_reg[16][value]__0__0 [9]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0__0 [9]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0__0 [9]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[109]_i_2__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[10]_i_1__0
- (.I0(Q[6]),
- .I1(\data_rw_o_reg[79][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[10]_i_2__0_n_0 ),
- .O(\s_reqs[0][value] [6]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[10]_i_2__0
- (.I0(\s_tx_data_reg[111]_0 [6]),
- .I1(\s_tx_data_reg[15]_0 [6]),
- .I2(\s_tx_data_reg[15]_1 [6]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[10]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[110]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [10]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0__0 [10]),
- .I5(\s_tx_data[110]_i_2__0_n_0 ),
- .O(\s_tx_data[110]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[110]_i_2__0
- (.I0(\[4].[0].s_reqs_reg[16][value]__0__0 [10]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0__0 [10]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0__0 [10]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[110]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[111]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [11]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0__0 [11]),
- .I5(\s_tx_data[111]_i_2__0_n_0 ),
- .O(\s_tx_data[111]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[111]_i_2__0
- (.I0(\[4].[0].s_reqs_reg[16][value]__0__0 [11]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0__0 [11]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0__0 [11]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[111]_i_2__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_tx_data[113]_i_1__0
- (.I0(\dac_ch_o_reg[0][0]_1 ),
- .I1(\dac_ch_o_reg[0][0]_0 ),
- .I2(s00_axi_aresetn),
- .O(\s_tx_data[113]_i_1__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[11]_i_1__0
- (.I0(Q[7]),
- .I1(\data_rw_o_reg[79][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[11]_i_2__0_n_0 ),
- .O(\s_reqs[0][value] [7]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[11]_i_2__0
- (.I0(\s_tx_data_reg[111]_0 [7]),
- .I1(\s_tx_data_reg[15]_0 [7]),
- .I2(\s_tx_data_reg[15]_1 [7]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[11]_i_2__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[12]_i_1__0
- (.I0(Q[8]),
- .I1(\data_rw_o_reg[79][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[12]_i_2__0_n_0 ),
- .O(\s_reqs[0][value] [8]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[12]_i_2__0
- (.I0(\s_tx_data_reg[111]_0 [8]),
- .I1(\s_tx_data_reg[15]_0 [8]),
- .I2(\s_tx_data_reg[15]_1 [8]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[12]_i_2__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[13]_i_1__0
- (.I0(Q[9]),
- .I1(\data_rw_o_reg[79][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[13]_i_2__0_n_0 ),
- .O(\s_reqs[0][value] [9]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[13]_i_2__0
- (.I0(\s_tx_data_reg[111]_0 [9]),
- .I1(\s_tx_data_reg[15]_0 [9]),
- .I2(\s_tx_data_reg[15]_1 [9]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[13]_i_2__0_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair53" *)
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[14]_i_1__0
- (.I0(Q[10]),
- .I1(\data_rw_o_reg[79][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[14]_i_2__0_n_0 ),
- .O(\s_reqs[0][value] [10]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[14]_i_2__0
- (.I0(\s_tx_data_reg[111]_0 [10]),
- .I1(\s_tx_data_reg[15]_0 [10]),
- .I2(\s_tx_data_reg[15]_1 [10]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[14]_i_2__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[15]_i_1__0
- (.I0(Q[11]),
- .I1(\data_rw_o_reg[79][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[15]_i_2__0_n_0 ),
- .O(\s_reqs[0][value] [11]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[15]_i_2__0
- (.I0(\s_tx_data_reg[111]_0 [11]),
- .I1(\s_tx_data_reg[15]_0 [11]),
- .I2(\s_tx_data_reg[15]_1 [11]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[15]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[28]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [0]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [0]),
- .I5(\s_tx_data[28]_i_2__0_n_0 ),
- .O(\s_tx_data[28]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[28]_i_2__0
- (.I0(\s_tx_data_reg[39]_1 [0]),
- .I1(\s_tx_data_reg[39]_2 [0]),
- .I2(\s_tx_data_reg[39]_3 [0]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[28]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[29]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [1]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [1]),
- .I5(\s_tx_data[29]_i_2__0_n_0 ),
- .O(\s_tx_data[29]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[29]_i_2__0
- (.I0(\s_tx_data_reg[39]_1 [1]),
- .I1(\s_tx_data_reg[39]_2 [1]),
- .I2(\s_tx_data_reg[39]_3 [1]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[29]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[30]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [2]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [2]),
- .I5(\s_tx_data[30]_i_2__0_n_0 ),
- .O(\s_tx_data[30]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[30]_i_2__0
- (.I0(\s_tx_data_reg[39]_1 [2]),
- .I1(\s_tx_data_reg[39]_2 [2]),
- .I2(\s_tx_data_reg[39]_3 [2]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[30]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[31]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [3]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [3]),
- .I5(\s_tx_data[31]_i_2__0_n_0 ),
- .O(\s_tx_data[31]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[31]_i_2__0
- (.I0(\s_tx_data_reg[39]_1 [3]),
- .I1(\s_tx_data_reg[39]_2 [3]),
- .I2(\s_tx_data_reg[39]_3 [3]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[31]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[32]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [4]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [4]),
- .I5(\s_tx_data[32]_i_2__0_n_0 ),
- .O(\s_tx_data[32]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[32]_i_2__0
- (.I0(\s_tx_data_reg[39]_1 [4]),
- .I1(\s_tx_data_reg[39]_2 [4]),
- .I2(\s_tx_data_reg[39]_3 [4]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[32]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[33]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [5]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [5]),
- .I5(\s_tx_data[33]_i_2__0_n_0 ),
- .O(\s_tx_data[33]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[33]_i_2__0
- (.I0(\s_tx_data_reg[39]_1 [5]),
- .I1(\s_tx_data_reg[39]_2 [5]),
- .I2(\s_tx_data_reg[39]_3 [5]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[33]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[34]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [6]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [6]),
- .I5(\s_tx_data[34]_i_2__0_n_0 ),
- .O(\s_tx_data[34]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[34]_i_2__0
- (.I0(\s_tx_data_reg[39]_1 [6]),
- .I1(\s_tx_data_reg[39]_2 [6]),
- .I2(\s_tx_data_reg[39]_3 [6]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[34]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[35]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [7]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [7]),
- .I5(\s_tx_data[35]_i_2__0_n_0 ),
- .O(\s_tx_data[35]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[35]_i_2__0
- (.I0(\s_tx_data_reg[39]_1 [7]),
- .I1(\s_tx_data_reg[39]_2 [7]),
- .I2(\s_tx_data_reg[39]_3 [7]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[35]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[36]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [8]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [8]),
- .I5(\s_tx_data[36]_i_2__0_n_0 ),
- .O(\s_tx_data[36]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[36]_i_2__0
- (.I0(\s_tx_data_reg[39]_1 [8]),
- .I1(\s_tx_data_reg[39]_2 [8]),
- .I2(\s_tx_data_reg[39]_3 [8]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[36]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[37]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [9]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [9]),
- .I5(\s_tx_data[37]_i_2__0_n_0 ),
- .O(\s_tx_data[37]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[37]_i_2__0
- (.I0(\s_tx_data_reg[39]_1 [9]),
- .I1(\s_tx_data_reg[39]_2 [9]),
- .I2(\s_tx_data_reg[39]_3 [9]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[37]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[38]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [10]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [10]),
- .I5(\s_tx_data[38]_i_2__0_n_0 ),
- .O(\s_tx_data[38]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[38]_i_2__0
- (.I0(\s_tx_data_reg[39]_1 [10]),
- .I1(\s_tx_data_reg[39]_2 [10]),
- .I2(\s_tx_data_reg[39]_3 [10]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[38]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[39]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [11]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [11]),
- .I5(\s_tx_data[39]_i_2__0_n_0 ),
- .O(\s_tx_data[39]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[39]_i_2__0
- (.I0(\s_tx_data_reg[39]_1 [11]),
- .I1(\s_tx_data_reg[39]_2 [11]),
- .I2(\s_tx_data_reg[39]_3 [11]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[39]_i_2__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[4]_i_1__0
- (.I0(Q[0]),
- .I1(\data_rw_o_reg[79][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[4]_i_2__0_n_0 ),
- .O(\s_reqs[0][value] [0]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[4]_i_2__0
- (.I0(\s_tx_data_reg[111]_0 [0]),
- .I1(\s_tx_data_reg[15]_0 [0]),
- .I2(\s_tx_data_reg[15]_1 [0]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[4]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[52]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [0]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0__0 [0]),
- .I5(\s_tx_data[52]_i_2__0_n_0 ),
- .O(\s_tx_data[52]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[52]_i_2__0
- (.I0(\[2].[0].s_reqs_reg[8][value]__0__0 [0]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0__0 [0]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0__0 [0]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[52]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[53]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [1]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0__0 [1]),
- .I5(\s_tx_data[53]_i_2__0_n_0 ),
- .O(\s_tx_data[53]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[53]_i_2__0
- (.I0(\[2].[0].s_reqs_reg[8][value]__0__0 [1]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0__0 [1]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0__0 [1]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[53]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[54]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [2]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0__0 [2]),
- .I5(\s_tx_data[54]_i_2__0_n_0 ),
- .O(\s_tx_data[54]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[54]_i_2__0
- (.I0(\[2].[0].s_reqs_reg[8][value]__0__0 [2]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0__0 [2]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0__0 [2]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[54]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[55]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [3]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0__0 [3]),
- .I5(\s_tx_data[55]_i_2__0_n_0 ),
- .O(\s_tx_data[55]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[55]_i_2__0
- (.I0(\[2].[0].s_reqs_reg[8][value]__0__0 [3]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0__0 [3]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0__0 [3]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[55]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[56]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [4]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0__0 [4]),
- .I5(\s_tx_data[56]_i_2__0_n_0 ),
- .O(\s_tx_data[56]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[56]_i_2__0
- (.I0(\[2].[0].s_reqs_reg[8][value]__0__0 [4]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0__0 [4]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0__0 [4]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[56]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[57]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [5]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0__0 [5]),
- .I5(\s_tx_data[57]_i_2__0_n_0 ),
- .O(\s_tx_data[57]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[57]_i_2__0
- (.I0(\[2].[0].s_reqs_reg[8][value]__0__0 [5]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0__0 [5]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0__0 [5]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[57]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[58]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [6]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0__0 [6]),
- .I5(\s_tx_data[58]_i_2__0_n_0 ),
- .O(\s_tx_data[58]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[58]_i_2__0
- (.I0(\[2].[0].s_reqs_reg[8][value]__0__0 [6]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0__0 [6]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0__0 [6]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[58]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[59]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [7]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0__0 [7]),
- .I5(\s_tx_data[59]_i_2__0_n_0 ),
- .O(\s_tx_data[59]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[59]_i_2__0
- (.I0(\[2].[0].s_reqs_reg[8][value]__0__0 [7]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0__0 [7]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0__0 [7]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[59]_i_2__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[5]_i_1__0
- (.I0(Q[1]),
- .I1(\data_rw_o_reg[79][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[5]_i_2__0_n_0 ),
- .O(\s_reqs[0][value] [1]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[5]_i_2__0
- (.I0(\s_tx_data_reg[111]_0 [1]),
- .I1(\s_tx_data_reg[15]_0 [1]),
- .I2(\s_tx_data_reg[15]_1 [1]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[5]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[60]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [8]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0__0 [8]),
- .I5(\s_tx_data[60]_i_2__0_n_0 ),
- .O(\s_tx_data[60]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[60]_i_2__0
- (.I0(\[2].[0].s_reqs_reg[8][value]__0__0 [8]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0__0 [8]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0__0 [8]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[60]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[61]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [9]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0__0 [9]),
- .I5(\s_tx_data[61]_i_2__0_n_0 ),
- .O(\s_tx_data[61]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[61]_i_2__0
- (.I0(\[2].[0].s_reqs_reg[8][value]__0__0 [9]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0__0 [9]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0__0 [9]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[61]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[62]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [10]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0__0 [10]),
- .I5(\s_tx_data[62]_i_2__0_n_0 ),
- .O(\s_tx_data[62]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[62]_i_2__0
- (.I0(\[2].[0].s_reqs_reg[8][value]__0__0 [10]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0__0 [10]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0__0 [10]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[62]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[63]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [11]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0__0 [11]),
- .I5(\s_tx_data[63]_i_2__0_n_0 ),
- .O(\s_tx_data[63]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[63]_i_2__0
- (.I0(\[2].[0].s_reqs_reg[8][value]__0__0 [11]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0__0 [11]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0__0 [11]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[63]_i_2__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[6]_i_1__0
- (.I0(Q[2]),
- .I1(\data_rw_o_reg[79][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[6]_i_2__0_n_0 ),
- .O(\s_reqs[0][value] [2]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[6]_i_2__0
- (.I0(\s_tx_data_reg[111]_0 [2]),
- .I1(\s_tx_data_reg[15]_0 [2]),
- .I2(\s_tx_data_reg[15]_1 [2]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[6]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[76]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [0]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0__0 [0]),
- .I5(\s_tx_data[76]_i_2__0_n_0 ),
- .O(\s_tx_data[76]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[76]_i_2__0
- (.I0(\[3].[0].s_reqs_reg[12][value]__0__0 [0]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0__0 [0]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0__0 [0]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[76]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[77]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [1]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0__0 [1]),
- .I5(\s_tx_data[77]_i_2__0_n_0 ),
- .O(\s_tx_data[77]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[77]_i_2__0
- (.I0(\[3].[0].s_reqs_reg[12][value]__0__0 [1]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0__0 [1]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0__0 [1]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[77]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[78]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [2]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0__0 [2]),
- .I5(\s_tx_data[78]_i_2__0_n_0 ),
- .O(\s_tx_data[78]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[78]_i_2__0
- (.I0(\[3].[0].s_reqs_reg[12][value]__0__0 [2]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0__0 [2]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0__0 [2]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[78]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[79]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [3]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0__0 [3]),
- .I5(\s_tx_data[79]_i_2__0_n_0 ),
- .O(\s_tx_data[79]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[79]_i_2__0
- (.I0(\[3].[0].s_reqs_reg[12][value]__0__0 [3]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0__0 [3]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0__0 [3]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[79]_i_2__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[7]_i_1__0
- (.I0(Q[3]),
- .I1(\data_rw_o_reg[79][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[7]_i_2__0_n_0 ),
- .O(\s_reqs[0][value] [3]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[7]_i_2__0
- (.I0(\s_tx_data_reg[111]_0 [3]),
- .I1(\s_tx_data_reg[15]_0 [3]),
- .I2(\s_tx_data_reg[15]_1 [3]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[7]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[80]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [4]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0__0 [4]),
- .I5(\s_tx_data[80]_i_2__0_n_0 ),
- .O(\s_tx_data[80]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[80]_i_2__0
- (.I0(\[3].[0].s_reqs_reg[12][value]__0__0 [4]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0__0 [4]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0__0 [4]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[80]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[81]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [5]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0__0 [5]),
- .I5(\s_tx_data[81]_i_2__0_n_0 ),
- .O(\s_tx_data[81]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[81]_i_2__0
- (.I0(\[3].[0].s_reqs_reg[12][value]__0__0 [5]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0__0 [5]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0__0 [5]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[81]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[82]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [6]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0__0 [6]),
- .I5(\s_tx_data[82]_i_2__0_n_0 ),
- .O(\s_tx_data[82]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[82]_i_2__0
- (.I0(\[3].[0].s_reqs_reg[12][value]__0__0 [6]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0__0 [6]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0__0 [6]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[82]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[83]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [7]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0__0 [7]),
- .I5(\s_tx_data[83]_i_2__0_n_0 ),
- .O(\s_tx_data[83]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[83]_i_2__0
- (.I0(\[3].[0].s_reqs_reg[12][value]__0__0 [7]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0__0 [7]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0__0 [7]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[83]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[84]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [8]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0__0 [8]),
- .I5(\s_tx_data[84]_i_2__0_n_0 ),
- .O(\s_tx_data[84]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[84]_i_2__0
- (.I0(\[3].[0].s_reqs_reg[12][value]__0__0 [8]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0__0 [8]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0__0 [8]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[84]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[85]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [9]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0__0 [9]),
- .I5(\s_tx_data[85]_i_2__0_n_0 ),
- .O(\s_tx_data[85]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[85]_i_2__0
- (.I0(\[3].[0].s_reqs_reg[12][value]__0__0 [9]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0__0 [9]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0__0 [9]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[85]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[86]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [10]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0__0 [10]),
- .I5(\s_tx_data[86]_i_2__0_n_0 ),
- .O(\s_tx_data[86]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[86]_i_2__0
- (.I0(\[3].[0].s_reqs_reg[12][value]__0__0 [10]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0__0 [10]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0__0 [10]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[86]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[87]_i_1__0
- (.I0(\data_rw_o_reg[79][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [11]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0__0 [11]),
- .I5(\s_tx_data[87]_i_2__0_n_0 ),
- .O(\s_tx_data[87]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[87]_i_2__0
- (.I0(\[3].[0].s_reqs_reg[12][value]__0__0 [11]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0__0 [11]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0__0 [11]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[87]_i_2__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[8]_i_1__0
- (.I0(Q[4]),
- .I1(\data_rw_o_reg[79][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[8]_i_2__0_n_0 ),
- .O(\s_reqs[0][value] [4]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[8]_i_2__0
- (.I0(\s_tx_data_reg[111]_0 [4]),
- .I1(\s_tx_data_reg[15]_0 [4]),
- .I2(\s_tx_data_reg[15]_1 [4]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[8]_i_2__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[9]_i_1__0
- (.I0(Q[5]),
- .I1(\data_rw_o_reg[79][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[9]_i_2__0_n_0 ),
- .O(\s_reqs[0][value] [5]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[9]_i_2__0
- (.I0(\s_tx_data_reg[111]_0 [5]),
- .I1(\s_tx_data_reg[15]_0 [5]),
- .I2(\s_tx_data_reg[15]_1 [5]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[79][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[9]_i_2__0_n_0 ));
- FDRE \s_tx_data_reg[100]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[100]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[100] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[101]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[101]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[101] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[102]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[102]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[102] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[103]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[103]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[103] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[104]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[104]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[104] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[105]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[105]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[105] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[106]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[106]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[106] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[107]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[107]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[107] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[108]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[108]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[108] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[109]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[109]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[109] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[10]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_reqs[0][value] [6]),
- .Q(\s_tx_data_reg_n_0_[10] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[110]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[110]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[110] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[111]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[111]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[111] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[112]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(ch_address[0]),
- .Q(\s_tx_data_reg_n_0_[112] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[113]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(ch_address[1]),
- .Q(\s_tx_data_reg_n_0_[113] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[11]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_reqs[0][value] [7]),
- .Q(\s_tx_data_reg_n_0_[11] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[12]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_reqs[0][value] [8]),
- .Q(\s_tx_data_reg_n_0_[12] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[13]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_reqs[0][value] [9]),
- .Q(\s_tx_data_reg_n_0_[13] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[14]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_reqs[0][value] [10]),
- .Q(\s_tx_data_reg_n_0_[14] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[15]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_reqs[0][value] [11]),
- .Q(\s_tx_data_reg_n_0_[15] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[28]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[28]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[28] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[29]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[29]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[29] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[30]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[30]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[30] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[31]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[31]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[31] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[32]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[32]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[32] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[33]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[33]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[33] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[34]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[34]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[34] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[35]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[35]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[35] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[36]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[36]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[36] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[37]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[37]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[37] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[38]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[38]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[38] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[39]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[39]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[39] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[4]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_reqs[0][value] [0]),
- .Q(\s_tx_data_reg_n_0_[4] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[52]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[52]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[52] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[53]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[53]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[53] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[54]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[54]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[54] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[55]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[55]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[55] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[56]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[56]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[56] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[57]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[57]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[57] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[58]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[58]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[58] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[59]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[59]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[59] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[5]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_reqs[0][value] [1]),
- .Q(\s_tx_data_reg_n_0_[5] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[60]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[60]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[60] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[61]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[61]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[61] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[62]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[62]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[62] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[63]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[63]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[63] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[6]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_reqs[0][value] [2]),
- .Q(\s_tx_data_reg_n_0_[6] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[76]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[76]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[76] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[77]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[77]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[77] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[78]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[78]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[78] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[79]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[79]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[79] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[7]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_reqs[0][value] [3]),
- .Q(\s_tx_data_reg_n_0_[7] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[80]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[80]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[80] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[81]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[81]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[81] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[82]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[82]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[82] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[83]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[83]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[83] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[84]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[84]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[84] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[85]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[85]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[85] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[86]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[86]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[86] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[87]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_tx_data[87]_i_1__0_n_0 ),
- .Q(\s_tx_data_reg_n_0_[87] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[8]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_reqs[0][value] [4]),
- .Q(\s_tx_data_reg_n_0_[8] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[9]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1__0_n_0 ),
- .D(\s_reqs[0][value] [5]),
- .Q(\s_tx_data_reg_n_0_[9] ),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h00000002FFFFFFFF))
- \v_ch_address[1]_i_3__0
- (.I0(\v_ch_address[1]_i_5__0_n_0 ),
- .I1(\data_rw_o_reg[79][2] [0]),
- .I2(\[1].[0].s_reqs_reg[4][changed]__1 ),
- .I3(\[0].[3].s_reqs_reg[3][changed_n_0_] ),
- .I4(\[0].[2].s_reqs_reg[2][changed_n_0_] ),
- .I5(\dac_ch_o_reg[0][0]_1 ),
- .O(\v_ch_address[1]_i_3__0_n_0 ));
- LUT6 #(
- .INIT(64'h0003000000033355))
- \v_ch_address[1]_i_5__0
- (.I0(\[0].[0].s_reqs_reg[0][changed_n_0_] ),
- .I1(\[1].[1].s_reqs_reg[5][changed]__1 ),
- .I2(\[1].[2].s_reqs_reg[6][changed]__1 ),
- .I3(ch_address[0]),
- .I4(ch_address[1]),
- .I5(\[0].[1].s_reqs_reg[1][changed_n_0_] ),
- .O(\v_ch_address[1]_i_5__0_n_0 ));
- FDRE \v_ch_address_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(cmp_spi_n_1),
- .Q(ch_address[0]),
- .R(1'b0));
- FDRE \v_ch_address_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(cmp_spi_n_2),
- .Q(ch_address[1]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "dac7716_spi" *)
-module system_design_fasec_hwtest_0_0_dac7716_spi_129
- (s_start,
- \dac_ch_o_reg[0][0]_0 ,
- \dac_ch_o_reg[0][0]_1 ,
- Q,
- \s_tx_data_reg[111]_0 ,
- \s_tx_data_reg[15]_0 ,
- \s_tx_data_reg[15]_1 ,
- \s_tx_data_reg[39]_0 ,
- \s_tx_data_reg[39]_1 ,
- \s_tx_data_reg[39]_2 ,
- \s_tx_data_reg[39]_3 ,
- \s_counter_reg[2] ,
- \axi_rdata_reg[31] ,
- s_spi_mosi,
- s_spi_cs_n,
- SR,
- s_start_reg_0,
- s00_axi_aclk,
- s00_axi_aresetn,
- \data_rw_o_reg[11][2] ,
- \data_rw_o_reg[19][11] ,
- CO,
- \data_rw_o_reg[18][11] ,
- \data_rw_o_reg[18][11]_0 ,
- \data_rw_o_reg[17][11] ,
- \data_rw_o_reg[17][11]_0 ,
- \data_rw_o_reg[16][11] ,
- \data_rw_o_reg[16][11]_0 ,
- \data_rw_o_reg[20][11] ,
- \data_rw_o_reg[20][11]_0 ,
- \data_rw_o_reg[21][11] ,
- \data_rw_o_reg[21][11]_0 ,
- \data_rw_o_reg[22][11] ,
- \data_rw_o_reg[22][11]_0 ,
- \data_rw_o_reg[23][11] ,
- \data_rw_o_reg[23][11]_0 ,
- \data_rw_o_reg[24][11] ,
- \data_rw_o_reg[25][11] ,
- \data_rw_o_reg[26][11] ,
- \data_rw_o_reg[27][11] ,
- \data_rw_o_reg[28][11] ,
- \data_rw_o_reg[29][11] ,
- \data_rw_o_reg[30][11] ,
- \data_rw_o_reg[31][11] ,
- \data_rw_o_reg[32][11] ,
- \data_rw_o_reg[33][11] ,
- \data_rw_o_reg[34][11] ,
- \data_rw_o_reg[35][11] ,
- D);
- output s_start;
- output \dac_ch_o_reg[0][0]_0 ;
- output \dac_ch_o_reg[0][0]_1 ;
- output [11:0]Q;
- output [11:0]\s_tx_data_reg[111]_0 ;
- output [11:0]\s_tx_data_reg[15]_0 ;
- output [11:0]\s_tx_data_reg[15]_1 ;
- output [11:0]\s_tx_data_reg[39]_0 ;
- output [11:0]\s_tx_data_reg[39]_1 ;
- output [11:0]\s_tx_data_reg[39]_2 ;
- output [11:0]\s_tx_data_reg[39]_3 ;
- output [0:0]\s_counter_reg[2] ;
- output [31:0]\axi_rdata_reg[31] ;
- output s_spi_mosi;
- output s_spi_cs_n;
- input [0:0]SR;
- input s_start_reg_0;
- input s00_axi_aclk;
- input s00_axi_aresetn;
- input [1:0]\data_rw_o_reg[11][2] ;
- input [11:0]\data_rw_o_reg[19][11] ;
- input [0:0]CO;
- input [11:0]\data_rw_o_reg[18][11] ;
- input [0:0]\data_rw_o_reg[18][11]_0 ;
- input [11:0]\data_rw_o_reg[17][11] ;
- input [0:0]\data_rw_o_reg[17][11]_0 ;
- input [11:0]\data_rw_o_reg[16][11] ;
- input [0:0]\data_rw_o_reg[16][11]_0 ;
- input [11:0]\data_rw_o_reg[20][11] ;
- input [0:0]\data_rw_o_reg[20][11]_0 ;
- input [11:0]\data_rw_o_reg[21][11] ;
- input [0:0]\data_rw_o_reg[21][11]_0 ;
- input [11:0]\data_rw_o_reg[22][11] ;
- input [0:0]\data_rw_o_reg[22][11]_0 ;
- input [11:0]\data_rw_o_reg[23][11] ;
- input [0:0]\data_rw_o_reg[23][11]_0 ;
- input [11:0]\data_rw_o_reg[24][11] ;
- input [11:0]\data_rw_o_reg[25][11] ;
- input [11:0]\data_rw_o_reg[26][11] ;
- input [11:0]\data_rw_o_reg[27][11] ;
- input [11:0]\data_rw_o_reg[28][11] ;
- input [11:0]\data_rw_o_reg[29][11] ;
- input [11:0]\data_rw_o_reg[30][11] ;
- input [11:0]\data_rw_o_reg[31][11] ;
- input [11:0]\data_rw_o_reg[32][11] ;
- input [11:0]\data_rw_o_reg[33][11] ;
- input [11:0]\data_rw_o_reg[34][11] ;
- input [11:0]\data_rw_o_reg[35][11] ;
- input [0:0]D;
-
- wire [0:0]CO;
- wire [0:0]D;
- wire [11:0]Q;
- wire [0:0]SR;
- wire \[0].[0].s_reqs[0][changed]_i_1_n_0 ;
- wire \[0].[0].s_reqs_reg[0][changed_n_0_] ;
- wire \[0].[1].s_reqs[1][changed]_i_1_n_0 ;
- wire \[0].[1].s_reqs_reg[1][changed_n_0_] ;
- wire \[0].[2].s_reqs[2][changed]_i_1_n_0 ;
- wire \[0].[2].s_reqs_reg[2][changed_n_0_] ;
- wire \[0].[3].s_reqs[3][changed]_i_1_n_0 ;
- wire \[0].[3].s_reqs_reg[3][changed_n_0_] ;
- wire \[1].[0].s_reqs[4][changed]_i_1_n_0 ;
- wire \[1].[0].s_reqs_reg[4][changed]__1 ;
- wire \[1].[1].s_reqs[5][changed]_i_1_n_0 ;
- wire \[1].[1].s_reqs_reg[5][changed]__1 ;
- wire \[1].[2].s_reqs[6][changed]_i_1_n_0 ;
- wire \[1].[2].s_reqs_reg[6][changed]__1 ;
- wire \[1].[3].s_reqs[7][changed]_i_1_n_0 ;
- wire \[1].[3].s_reqs_reg[7][changed]__1 ;
- wire [11:0]\[2].[0].s_reqs_reg[8][value]__0 ;
- wire [11:0]\[2].[1].s_reqs_reg[9][value]__0 ;
- wire [11:0]\[2].[2].s_reqs_reg[10][value]__0 ;
- wire [11:0]\[2].[3].s_reqs_reg[11][value]__0 ;
- wire [11:0]\[3].[0].s_reqs_reg[12][value]__0 ;
- wire [11:0]\[3].[1].s_reqs_reg[13][value]__0 ;
- wire [11:0]\[3].[2].s_reqs_reg[14][value]__0 ;
- wire [11:0]\[3].[3].s_reqs_reg[15][value]__0 ;
- wire [11:0]\[4].[0].s_reqs_reg[16][value]__0 ;
- wire [11:0]\[4].[1].s_reqs_reg[17][value]__0 ;
- wire [11:0]\[4].[2].s_reqs_reg[18][value]__0 ;
- wire [11:0]\[4].[3].s_reqs_reg[19][value]__0 ;
- wire [31:0]\axi_rdata_reg[31] ;
- wire [1:0]ch_address;
- wire cmp_spi_n_0;
- wire cmp_spi_n_1;
- wire cmp_spi_n_2;
- wire cmp_spi_n_3;
- wire cmp_spi_n_4;
- wire \dac_ch_o[0][31]_i_2_n_0 ;
- wire \dac_ch_o_reg[0][0]_0 ;
- wire \dac_ch_o_reg[0][0]_1 ;
- wire [1:0]\data_rw_o_reg[11][2] ;
- wire [11:0]\data_rw_o_reg[16][11] ;
- wire [0:0]\data_rw_o_reg[16][11]_0 ;
- wire [11:0]\data_rw_o_reg[17][11] ;
- wire [0:0]\data_rw_o_reg[17][11]_0 ;
- wire [11:0]\data_rw_o_reg[18][11] ;
- wire [0:0]\data_rw_o_reg[18][11]_0 ;
- wire [11:0]\data_rw_o_reg[19][11] ;
- wire [11:0]\data_rw_o_reg[20][11] ;
- wire [0:0]\data_rw_o_reg[20][11]_0 ;
- wire [11:0]\data_rw_o_reg[21][11] ;
- wire [0:0]\data_rw_o_reg[21][11]_0 ;
- wire [11:0]\data_rw_o_reg[22][11] ;
- wire [0:0]\data_rw_o_reg[22][11]_0 ;
- wire [11:0]\data_rw_o_reg[23][11] ;
- wire [0:0]\data_rw_o_reg[23][11]_0 ;
- wire [11:0]\data_rw_o_reg[24][11] ;
- wire [11:0]\data_rw_o_reg[25][11] ;
- wire [11:0]\data_rw_o_reg[26][11] ;
- wire [11:0]\data_rw_o_reg[27][11] ;
- wire [11:0]\data_rw_o_reg[28][11] ;
- wire [11:0]\data_rw_o_reg[29][11] ;
- wire [11:0]\data_rw_o_reg[30][11] ;
- wire [11:0]\data_rw_o_reg[31][11] ;
- wire [11:0]\data_rw_o_reg[32][11] ;
- wire [11:0]\data_rw_o_reg[33][11] ;
- wire [11:0]\data_rw_o_reg[34][11] ;
- wire [11:0]\data_rw_o_reg[35][11] ;
- wire p_0_in;
- wire p_1_in;
- wire p_2_in;
- wire [31:0]rx_data_o;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]\s_counter_reg[2] ;
- wire \s_flag_reset[0]_i_1_n_0 ;
- wire \s_flag_reset[1]_i_1_n_0 ;
- wire \s_flag_reset[2]_i_1_n_0 ;
- wire \s_flag_reset[3]_i_1_n_0 ;
- wire \s_flag_reset_reg_n_0_[0] ;
- wire [11:0]\s_reqs[0][value] ;
- wire s_spi_cs_n;
- wire s_spi_mosi;
- wire s_start;
- wire s_start_reg_0;
- wire \s_state[1]_i_2_n_0 ;
- wire \s_state[1]_i_3_n_0 ;
- wire \s_state[1]_i_5_n_0 ;
- wire \s_tx_data[100]_i_1_n_0 ;
- wire \s_tx_data[100]_i_2_n_0 ;
- wire \s_tx_data[101]_i_1_n_0 ;
- wire \s_tx_data[101]_i_2_n_0 ;
- wire \s_tx_data[102]_i_1_n_0 ;
- wire \s_tx_data[102]_i_2_n_0 ;
- wire \s_tx_data[103]_i_1_n_0 ;
- wire \s_tx_data[103]_i_2_n_0 ;
- wire \s_tx_data[104]_i_1_n_0 ;
- wire \s_tx_data[104]_i_2_n_0 ;
- wire \s_tx_data[105]_i_1_n_0 ;
- wire \s_tx_data[105]_i_2_n_0 ;
- wire \s_tx_data[106]_i_1_n_0 ;
- wire \s_tx_data[106]_i_2_n_0 ;
- wire \s_tx_data[107]_i_1_n_0 ;
- wire \s_tx_data[107]_i_2_n_0 ;
- wire \s_tx_data[108]_i_1_n_0 ;
- wire \s_tx_data[108]_i_2_n_0 ;
- wire \s_tx_data[109]_i_1_n_0 ;
- wire \s_tx_data[109]_i_2_n_0 ;
- wire \s_tx_data[10]_i_2_n_0 ;
- wire \s_tx_data[110]_i_1_n_0 ;
- wire \s_tx_data[110]_i_2_n_0 ;
- wire \s_tx_data[111]_i_1_n_0 ;
- wire \s_tx_data[111]_i_2_n_0 ;
- wire \s_tx_data[113]_i_1_n_0 ;
- wire \s_tx_data[11]_i_2_n_0 ;
- wire \s_tx_data[12]_i_2_n_0 ;
- wire \s_tx_data[13]_i_2_n_0 ;
- wire \s_tx_data[14]_i_2_n_0 ;
- wire \s_tx_data[15]_i_2_n_0 ;
- wire \s_tx_data[28]_i_1_n_0 ;
- wire \s_tx_data[28]_i_2_n_0 ;
- wire \s_tx_data[29]_i_1_n_0 ;
- wire \s_tx_data[29]_i_2_n_0 ;
- wire \s_tx_data[30]_i_1_n_0 ;
- wire \s_tx_data[30]_i_2_n_0 ;
- wire \s_tx_data[31]_i_1_n_0 ;
- wire \s_tx_data[31]_i_2_n_0 ;
- wire \s_tx_data[32]_i_1_n_0 ;
- wire \s_tx_data[32]_i_2_n_0 ;
- wire \s_tx_data[33]_i_1_n_0 ;
- wire \s_tx_data[33]_i_2_n_0 ;
- wire \s_tx_data[34]_i_1_n_0 ;
- wire \s_tx_data[34]_i_2_n_0 ;
- wire \s_tx_data[35]_i_1_n_0 ;
- wire \s_tx_data[35]_i_2_n_0 ;
- wire \s_tx_data[36]_i_1_n_0 ;
- wire \s_tx_data[36]_i_2_n_0 ;
- wire \s_tx_data[37]_i_1_n_0 ;
- wire \s_tx_data[37]_i_2_n_0 ;
- wire \s_tx_data[38]_i_1_n_0 ;
- wire \s_tx_data[38]_i_2_n_0 ;
- wire \s_tx_data[39]_i_1_n_0 ;
- wire \s_tx_data[39]_i_2_n_0 ;
- wire \s_tx_data[4]_i_2_n_0 ;
- wire \s_tx_data[52]_i_1_n_0 ;
- wire \s_tx_data[52]_i_2_n_0 ;
- wire \s_tx_data[53]_i_1_n_0 ;
- wire \s_tx_data[53]_i_2_n_0 ;
- wire \s_tx_data[54]_i_1_n_0 ;
- wire \s_tx_data[54]_i_2_n_0 ;
- wire \s_tx_data[55]_i_1_n_0 ;
- wire \s_tx_data[55]_i_2_n_0 ;
- wire \s_tx_data[56]_i_1_n_0 ;
- wire \s_tx_data[56]_i_2_n_0 ;
- wire \s_tx_data[57]_i_1_n_0 ;
- wire \s_tx_data[57]_i_2_n_0 ;
- wire \s_tx_data[58]_i_1_n_0 ;
- wire \s_tx_data[58]_i_2_n_0 ;
- wire \s_tx_data[59]_i_1_n_0 ;
- wire \s_tx_data[59]_i_2_n_0 ;
- wire \s_tx_data[5]_i_2_n_0 ;
- wire \s_tx_data[60]_i_1_n_0 ;
- wire \s_tx_data[60]_i_2_n_0 ;
- wire \s_tx_data[61]_i_1_n_0 ;
- wire \s_tx_data[61]_i_2_n_0 ;
- wire \s_tx_data[62]_i_1_n_0 ;
- wire \s_tx_data[62]_i_2_n_0 ;
- wire \s_tx_data[63]_i_1_n_0 ;
- wire \s_tx_data[63]_i_2_n_0 ;
- wire \s_tx_data[6]_i_2_n_0 ;
- wire \s_tx_data[76]_i_1_n_0 ;
- wire \s_tx_data[76]_i_2_n_0 ;
- wire \s_tx_data[77]_i_1_n_0 ;
- wire \s_tx_data[77]_i_2_n_0 ;
- wire \s_tx_data[78]_i_1_n_0 ;
- wire \s_tx_data[78]_i_2_n_0 ;
- wire \s_tx_data[79]_i_1_n_0 ;
- wire \s_tx_data[79]_i_2_n_0 ;
- wire \s_tx_data[7]_i_2_n_0 ;
- wire \s_tx_data[80]_i_1_n_0 ;
- wire \s_tx_data[80]_i_2_n_0 ;
- wire \s_tx_data[81]_i_1_n_0 ;
- wire \s_tx_data[81]_i_2_n_0 ;
- wire \s_tx_data[82]_i_1_n_0 ;
- wire \s_tx_data[82]_i_2_n_0 ;
- wire \s_tx_data[83]_i_1_n_0 ;
- wire \s_tx_data[83]_i_2_n_0 ;
- wire \s_tx_data[84]_i_1_n_0 ;
- wire \s_tx_data[84]_i_2_n_0 ;
- wire \s_tx_data[85]_i_1_n_0 ;
- wire \s_tx_data[85]_i_2_n_0 ;
- wire \s_tx_data[86]_i_1_n_0 ;
- wire \s_tx_data[86]_i_2_n_0 ;
- wire \s_tx_data[87]_i_1_n_0 ;
- wire \s_tx_data[87]_i_2_n_0 ;
- wire \s_tx_data[8]_i_2_n_0 ;
- wire \s_tx_data[9]_i_2_n_0 ;
- wire [11:0]\s_tx_data_reg[111]_0 ;
- wire [11:0]\s_tx_data_reg[15]_0 ;
- wire [11:0]\s_tx_data_reg[15]_1 ;
- wire [11:0]\s_tx_data_reg[39]_0 ;
- wire [11:0]\s_tx_data_reg[39]_1 ;
- wire [11:0]\s_tx_data_reg[39]_2 ;
- wire [11:0]\s_tx_data_reg[39]_3 ;
- wire \s_tx_data_reg_n_0_[100] ;
- wire \s_tx_data_reg_n_0_[101] ;
- wire \s_tx_data_reg_n_0_[102] ;
- wire \s_tx_data_reg_n_0_[103] ;
- wire \s_tx_data_reg_n_0_[104] ;
- wire \s_tx_data_reg_n_0_[105] ;
- wire \s_tx_data_reg_n_0_[106] ;
- wire \s_tx_data_reg_n_0_[107] ;
- wire \s_tx_data_reg_n_0_[108] ;
- wire \s_tx_data_reg_n_0_[109] ;
- wire \s_tx_data_reg_n_0_[10] ;
- wire \s_tx_data_reg_n_0_[110] ;
- wire \s_tx_data_reg_n_0_[111] ;
- wire \s_tx_data_reg_n_0_[112] ;
- wire \s_tx_data_reg_n_0_[113] ;
- wire \s_tx_data_reg_n_0_[11] ;
- wire \s_tx_data_reg_n_0_[12] ;
- wire \s_tx_data_reg_n_0_[13] ;
- wire \s_tx_data_reg_n_0_[14] ;
- wire \s_tx_data_reg_n_0_[15] ;
- wire \s_tx_data_reg_n_0_[28] ;
- wire \s_tx_data_reg_n_0_[29] ;
- wire \s_tx_data_reg_n_0_[30] ;
- wire \s_tx_data_reg_n_0_[31] ;
- wire \s_tx_data_reg_n_0_[32] ;
- wire \s_tx_data_reg_n_0_[33] ;
- wire \s_tx_data_reg_n_0_[34] ;
- wire \s_tx_data_reg_n_0_[35] ;
- wire \s_tx_data_reg_n_0_[36] ;
- wire \s_tx_data_reg_n_0_[37] ;
- wire \s_tx_data_reg_n_0_[38] ;
- wire \s_tx_data_reg_n_0_[39] ;
- wire \s_tx_data_reg_n_0_[4] ;
- wire \s_tx_data_reg_n_0_[52] ;
- wire \s_tx_data_reg_n_0_[53] ;
- wire \s_tx_data_reg_n_0_[54] ;
- wire \s_tx_data_reg_n_0_[55] ;
- wire \s_tx_data_reg_n_0_[56] ;
- wire \s_tx_data_reg_n_0_[57] ;
- wire \s_tx_data_reg_n_0_[58] ;
- wire \s_tx_data_reg_n_0_[59] ;
- wire \s_tx_data_reg_n_0_[5] ;
- wire \s_tx_data_reg_n_0_[60] ;
- wire \s_tx_data_reg_n_0_[61] ;
- wire \s_tx_data_reg_n_0_[62] ;
- wire \s_tx_data_reg_n_0_[63] ;
- wire \s_tx_data_reg_n_0_[6] ;
- wire \s_tx_data_reg_n_0_[76] ;
- wire \s_tx_data_reg_n_0_[77] ;
- wire \s_tx_data_reg_n_0_[78] ;
- wire \s_tx_data_reg_n_0_[79] ;
- wire \s_tx_data_reg_n_0_[7] ;
- wire \s_tx_data_reg_n_0_[80] ;
- wire \s_tx_data_reg_n_0_[81] ;
- wire \s_tx_data_reg_n_0_[82] ;
- wire \s_tx_data_reg_n_0_[83] ;
- wire \s_tx_data_reg_n_0_[84] ;
- wire \s_tx_data_reg_n_0_[85] ;
- wire \s_tx_data_reg_n_0_[86] ;
- wire \s_tx_data_reg_n_0_[87] ;
- wire \s_tx_data_reg_n_0_[8] ;
- wire \s_tx_data_reg_n_0_[9] ;
- wire \v_ch_address[1]_i_3_n_0 ;
- wire \v_ch_address[1]_i_5_n_0 ;
-
- (* SOFT_HLUTNM = "soft_lutpair45" *)
- LUT3 #(
- .INIT(8'h0E))
- \[0].[0].s_reqs[0][changed]_i_1
- (.I0(\[0].[0].s_reqs_reg[0][changed_n_0_] ),
- .I1(\data_rw_o_reg[16][11]_0 ),
- .I2(\s_flag_reset_reg_n_0_[0] ),
- .O(\[0].[0].s_reqs[0][changed]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[0].[0].s_reqs[0][changed]_i_1_n_0 ),
- .Q(\[0].[0].s_reqs_reg[0][changed_n_0_] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[16][11] [0]),
- .Q(\s_tx_data_reg[111]_0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[16][11] [10]),
- .Q(\s_tx_data_reg[111]_0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[16][11] [11]),
- .Q(\s_tx_data_reg[111]_0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[16][11] [1]),
- .Q(\s_tx_data_reg[111]_0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[16][11] [2]),
- .Q(\s_tx_data_reg[111]_0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[16][11] [3]),
- .Q(\s_tx_data_reg[111]_0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[16][11] [4]),
- .Q(\s_tx_data_reg[111]_0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[16][11] [5]),
- .Q(\s_tx_data_reg[111]_0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[16][11] [6]),
- .Q(\s_tx_data_reg[111]_0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[16][11] [7]),
- .Q(\s_tx_data_reg[111]_0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[16][11] [8]),
- .Q(\s_tx_data_reg[111]_0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[0].s_reqs_reg[0][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[16][11] [9]),
- .Q(\s_tx_data_reg[111]_0 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair43" *)
- LUT3 #(
- .INIT(8'h0E))
- \[0].[1].s_reqs[1][changed]_i_1
- (.I0(\[0].[1].s_reqs_reg[1][changed_n_0_] ),
- .I1(\data_rw_o_reg[17][11]_0 ),
- .I2(p_2_in),
- .O(\[0].[1].s_reqs[1][changed]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[0].[1].s_reqs[1][changed]_i_1_n_0 ),
- .Q(\[0].[1].s_reqs_reg[1][changed_n_0_] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[17][11] [0]),
- .Q(\s_tx_data_reg[15]_0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[17][11] [10]),
- .Q(\s_tx_data_reg[15]_0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[17][11] [11]),
- .Q(\s_tx_data_reg[15]_0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[17][11] [1]),
- .Q(\s_tx_data_reg[15]_0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[17][11] [2]),
- .Q(\s_tx_data_reg[15]_0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[17][11] [3]),
- .Q(\s_tx_data_reg[15]_0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[17][11] [4]),
- .Q(\s_tx_data_reg[15]_0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[17][11] [5]),
- .Q(\s_tx_data_reg[15]_0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[17][11] [6]),
- .Q(\s_tx_data_reg[15]_0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[17][11] [7]),
- .Q(\s_tx_data_reg[15]_0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[17][11] [8]),
- .Q(\s_tx_data_reg[15]_0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[1].s_reqs_reg[1][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[17][11] [9]),
- .Q(\s_tx_data_reg[15]_0 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair44" *)
- LUT3 #(
- .INIT(8'h0E))
- \[0].[2].s_reqs[2][changed]_i_1
- (.I0(\[0].[2].s_reqs_reg[2][changed_n_0_] ),
- .I1(\data_rw_o_reg[18][11]_0 ),
- .I2(p_1_in),
- .O(\[0].[2].s_reqs[2][changed]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[0].[2].s_reqs[2][changed]_i_1_n_0 ),
- .Q(\[0].[2].s_reqs_reg[2][changed_n_0_] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[18][11] [0]),
- .Q(\s_tx_data_reg[15]_1 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[18][11] [10]),
- .Q(\s_tx_data_reg[15]_1 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[18][11] [11]),
- .Q(\s_tx_data_reg[15]_1 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[18][11] [1]),
- .Q(\s_tx_data_reg[15]_1 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[18][11] [2]),
- .Q(\s_tx_data_reg[15]_1 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[18][11] [3]),
- .Q(\s_tx_data_reg[15]_1 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[18][11] [4]),
- .Q(\s_tx_data_reg[15]_1 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[18][11] [5]),
- .Q(\s_tx_data_reg[15]_1 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[18][11] [6]),
- .Q(\s_tx_data_reg[15]_1 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[18][11] [7]),
- .Q(\s_tx_data_reg[15]_1 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[18][11] [8]),
- .Q(\s_tx_data_reg[15]_1 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[2].s_reqs_reg[2][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[18][11] [9]),
- .Q(\s_tx_data_reg[15]_1 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair46" *)
- LUT3 #(
- .INIT(8'h0E))
- \[0].[3].s_reqs[3][changed]_i_1
- (.I0(\[0].[3].s_reqs_reg[3][changed_n_0_] ),
- .I1(CO),
- .I2(p_0_in),
- .O(\[0].[3].s_reqs[3][changed]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[0].[3].s_reqs[3][changed]_i_1_n_0 ),
- .Q(\[0].[3].s_reqs_reg[3][changed_n_0_] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[19][11] [0]),
- .Q(Q[0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[19][11] [10]),
- .Q(Q[10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[19][11] [11]),
- .Q(Q[11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[19][11] [1]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[19][11] [2]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[19][11] [3]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[19][11] [4]),
- .Q(Q[4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[19][11] [5]),
- .Q(Q[5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[19][11] [6]),
- .Q(Q[6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[19][11] [7]),
- .Q(Q[7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[19][11] [8]),
- .Q(Q[8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[0].[3].s_reqs_reg[3][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[19][11] [9]),
- .Q(Q[9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair45" *)
- LUT3 #(
- .INIT(8'h0E))
- \[1].[0].s_reqs[4][changed]_i_1
- (.I0(\[1].[0].s_reqs_reg[4][changed]__1 ),
- .I1(\data_rw_o_reg[20][11]_0 ),
- .I2(\s_flag_reset_reg_n_0_[0] ),
- .O(\[1].[0].s_reqs[4][changed]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[1].[0].s_reqs[4][changed]_i_1_n_0 ),
- .Q(\[1].[0].s_reqs_reg[4][changed]__1 ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[20][11] [0]),
- .Q(\s_tx_data_reg[39]_1 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[20][11] [10]),
- .Q(\s_tx_data_reg[39]_1 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[20][11] [11]),
- .Q(\s_tx_data_reg[39]_1 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[20][11] [1]),
- .Q(\s_tx_data_reg[39]_1 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[20][11] [2]),
- .Q(\s_tx_data_reg[39]_1 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[20][11] [3]),
- .Q(\s_tx_data_reg[39]_1 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[20][11] [4]),
- .Q(\s_tx_data_reg[39]_1 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[20][11] [5]),
- .Q(\s_tx_data_reg[39]_1 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[20][11] [6]),
- .Q(\s_tx_data_reg[39]_1 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[20][11] [7]),
- .Q(\s_tx_data_reg[39]_1 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[20][11] [8]),
- .Q(\s_tx_data_reg[39]_1 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[0].s_reqs_reg[4][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[20][11] [9]),
- .Q(\s_tx_data_reg[39]_1 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair43" *)
- LUT3 #(
- .INIT(8'h0E))
- \[1].[1].s_reqs[5][changed]_i_1
- (.I0(\[1].[1].s_reqs_reg[5][changed]__1 ),
- .I1(\data_rw_o_reg[21][11]_0 ),
- .I2(p_2_in),
- .O(\[1].[1].s_reqs[5][changed]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[1].[1].s_reqs[5][changed]_i_1_n_0 ),
- .Q(\[1].[1].s_reqs_reg[5][changed]__1 ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[21][11] [0]),
- .Q(\s_tx_data_reg[39]_2 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[21][11] [10]),
- .Q(\s_tx_data_reg[39]_2 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[21][11] [11]),
- .Q(\s_tx_data_reg[39]_2 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[21][11] [1]),
- .Q(\s_tx_data_reg[39]_2 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[21][11] [2]),
- .Q(\s_tx_data_reg[39]_2 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[21][11] [3]),
- .Q(\s_tx_data_reg[39]_2 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[21][11] [4]),
- .Q(\s_tx_data_reg[39]_2 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[21][11] [5]),
- .Q(\s_tx_data_reg[39]_2 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[21][11] [6]),
- .Q(\s_tx_data_reg[39]_2 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[21][11] [7]),
- .Q(\s_tx_data_reg[39]_2 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[21][11] [8]),
- .Q(\s_tx_data_reg[39]_2 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[1].s_reqs_reg[5][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[21][11] [9]),
- .Q(\s_tx_data_reg[39]_2 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair44" *)
- LUT3 #(
- .INIT(8'h0E))
- \[1].[2].s_reqs[6][changed]_i_1
- (.I0(\[1].[2].s_reqs_reg[6][changed]__1 ),
- .I1(\data_rw_o_reg[22][11]_0 ),
- .I2(p_1_in),
- .O(\[1].[2].s_reqs[6][changed]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[1].[2].s_reqs[6][changed]_i_1_n_0 ),
- .Q(\[1].[2].s_reqs_reg[6][changed]__1 ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[22][11] [0]),
- .Q(\s_tx_data_reg[39]_3 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[22][11] [10]),
- .Q(\s_tx_data_reg[39]_3 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[22][11] [11]),
- .Q(\s_tx_data_reg[39]_3 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[22][11] [1]),
- .Q(\s_tx_data_reg[39]_3 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[22][11] [2]),
- .Q(\s_tx_data_reg[39]_3 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[22][11] [3]),
- .Q(\s_tx_data_reg[39]_3 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[22][11] [4]),
- .Q(\s_tx_data_reg[39]_3 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[22][11] [5]),
- .Q(\s_tx_data_reg[39]_3 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[22][11] [6]),
- .Q(\s_tx_data_reg[39]_3 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[22][11] [7]),
- .Q(\s_tx_data_reg[39]_3 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[22][11] [8]),
- .Q(\s_tx_data_reg[39]_3 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[2].s_reqs_reg[6][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[22][11] [9]),
- .Q(\s_tx_data_reg[39]_3 [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair46" *)
- LUT3 #(
- .INIT(8'h0E))
- \[1].[3].s_reqs[7][changed]_i_1
- (.I0(\[1].[3].s_reqs_reg[7][changed]__1 ),
- .I1(\data_rw_o_reg[23][11]_0 ),
- .I2(p_0_in),
- .O(\[1].[3].s_reqs[7][changed]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][changed]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\[1].[3].s_reqs[7][changed]_i_1_n_0 ),
- .Q(\[1].[3].s_reqs_reg[7][changed]__1 ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[23][11] [0]),
- .Q(\s_tx_data_reg[39]_0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[23][11] [10]),
- .Q(\s_tx_data_reg[39]_0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[23][11] [11]),
- .Q(\s_tx_data_reg[39]_0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[23][11] [1]),
- .Q(\s_tx_data_reg[39]_0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[23][11] [2]),
- .Q(\s_tx_data_reg[39]_0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[23][11] [3]),
- .Q(\s_tx_data_reg[39]_0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[23][11] [4]),
- .Q(\s_tx_data_reg[39]_0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[23][11] [5]),
- .Q(\s_tx_data_reg[39]_0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[23][11] [6]),
- .Q(\s_tx_data_reg[39]_0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[23][11] [7]),
- .Q(\s_tx_data_reg[39]_0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[23][11] [8]),
- .Q(\s_tx_data_reg[39]_0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[1].[3].s_reqs_reg[7][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[23][11] [9]),
- .Q(\s_tx_data_reg[39]_0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[24][11] [0]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[24][11] [10]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[24][11] [11]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[24][11] [1]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[24][11] [2]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[24][11] [3]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[24][11] [4]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[24][11] [5]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[24][11] [6]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[24][11] [7]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[24][11] [8]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[0].s_reqs_reg[8][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[24][11] [9]),
- .Q(\[2].[0].s_reqs_reg[8][value]__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[25][11] [0]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[25][11] [10]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[25][11] [11]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[25][11] [1]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[25][11] [2]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[25][11] [3]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[25][11] [4]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[25][11] [5]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[25][11] [6]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[25][11] [7]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[25][11] [8]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[1].s_reqs_reg[9][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[25][11] [9]),
- .Q(\[2].[1].s_reqs_reg[9][value]__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[26][11] [0]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[26][11] [10]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[26][11] [11]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[26][11] [1]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[26][11] [2]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[26][11] [3]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[26][11] [4]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[26][11] [5]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[26][11] [6]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[26][11] [7]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[26][11] [8]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[2].s_reqs_reg[10][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[26][11] [9]),
- .Q(\[2].[2].s_reqs_reg[10][value]__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[27][11] [0]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[27][11] [10]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[27][11] [11]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[27][11] [1]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[27][11] [2]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[27][11] [3]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[27][11] [4]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[27][11] [5]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[27][11] [6]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[27][11] [7]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[27][11] [8]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[2].[3].s_reqs_reg[11][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[27][11] [9]),
- .Q(\[2].[3].s_reqs_reg[11][value]__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[28][11] [0]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[28][11] [10]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[28][11] [11]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[28][11] [1]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[28][11] [2]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[28][11] [3]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[28][11] [4]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[28][11] [5]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[28][11] [6]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[28][11] [7]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[28][11] [8]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[0].s_reqs_reg[12][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[28][11] [9]),
- .Q(\[3].[0].s_reqs_reg[12][value]__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[29][11] [0]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[29][11] [10]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[29][11] [11]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[29][11] [1]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[29][11] [2]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[29][11] [3]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[29][11] [4]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[29][11] [5]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[29][11] [6]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[29][11] [7]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[29][11] [8]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[1].s_reqs_reg[13][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[29][11] [9]),
- .Q(\[3].[1].s_reqs_reg[13][value]__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[30][11] [0]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[30][11] [10]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[30][11] [11]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[30][11] [1]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[30][11] [2]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[30][11] [3]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[30][11] [4]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[30][11] [5]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[30][11] [6]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[30][11] [7]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[30][11] [8]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[2].s_reqs_reg[14][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[30][11] [9]),
- .Q(\[3].[2].s_reqs_reg[14][value]__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[31][11] [0]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[31][11] [10]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[31][11] [11]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[31][11] [1]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[31][11] [2]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[31][11] [3]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[31][11] [4]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[31][11] [5]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[31][11] [6]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[31][11] [7]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[31][11] [8]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[3].[3].s_reqs_reg[15][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[31][11] [9]),
- .Q(\[3].[3].s_reqs_reg[15][value]__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[32][11] [0]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[32][11] [10]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[32][11] [11]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[32][11] [1]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[32][11] [2]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[32][11] [3]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[32][11] [4]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[32][11] [5]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[32][11] [6]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[32][11] [7]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[32][11] [8]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[0].s_reqs_reg[16][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[32][11] [9]),
- .Q(\[4].[0].s_reqs_reg[16][value]__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[33][11] [0]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[33][11] [10]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[33][11] [11]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[33][11] [1]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[33][11] [2]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[33][11] [3]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[33][11] [4]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[33][11] [5]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[33][11] [6]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[33][11] [7]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[33][11] [8]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[1].s_reqs_reg[17][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[33][11] [9]),
- .Q(\[4].[1].s_reqs_reg[17][value]__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[34][11] [0]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[34][11] [10]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[34][11] [11]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[34][11] [1]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[34][11] [2]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[34][11] [3]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[34][11] [4]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[34][11] [5]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[34][11] [6]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[34][11] [7]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[34][11] [8]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[2].s_reqs_reg[18][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[34][11] [9]),
- .Q(\[4].[2].s_reqs_reg[18][value]__0 [9]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[35][11] [0]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0 [0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[35][11] [10]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0 [10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[35][11] [11]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0 [11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[35][11] [1]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0 [1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[35][11] [2]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0 [2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[35][11] [3]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0 [3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[35][11] [4]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0 [4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[35][11] [5]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0 [5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[35][11] [6]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0 [6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[35][11] [7]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0 [7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[35][11] [8]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0 [8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \[4].[3].s_reqs_reg[19][value][9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[35][11] [9]),
- .Q(\[4].[3].s_reqs_reg[19][value]__0 [9]),
- .R(1'b0));
- system_design_fasec_hwtest_0_0_spi_transceiver_130 cmp_spi
- (.D(D),
- .E(cmp_spi_n_0),
- .Q(\s_counter_reg[2] ),
- .SR(SR),
- .\[0].[2].s_reqs_reg[2][changed] (\[0].[2].s_reqs_reg[2][changed_n_0_] ),
- .\[0].[2].s_reqs_reg[2][changed]_0 (\s_state[1]_i_2_n_0 ),
- .\[0].[3].s_reqs_reg[3][changed] (\s_state[1]_i_3_n_0 ),
- .ch_address(ch_address),
- .\dac_ch_o_reg[0][31] (rx_data_o),
- .\data_rw_o_reg[11][1] (\v_ch_address[1]_i_3_n_0 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_spi_cs_n(s_spi_cs_n),
- .s_spi_mosi(s_spi_mosi),
- .s_start_reg(s_start),
- .\s_state_reg[0] (cmp_spi_n_3),
- .\s_state_reg[0]_0 (\dac_ch_o_reg[0][0]_1 ),
- .\s_state_reg[1] (cmp_spi_n_4),
- .\s_state_reg[1]_0 (\dac_ch_o_reg[0][0]_0 ),
- .\s_tx_data_reg[113] ({\s_tx_data_reg_n_0_[113] ,\s_tx_data_reg_n_0_[112] ,\s_tx_data_reg_n_0_[111] ,\s_tx_data_reg_n_0_[110] ,\s_tx_data_reg_n_0_[109] ,\s_tx_data_reg_n_0_[108] ,\s_tx_data_reg_n_0_[107] ,\s_tx_data_reg_n_0_[106] ,\s_tx_data_reg_n_0_[105] ,\s_tx_data_reg_n_0_[104] ,\s_tx_data_reg_n_0_[103] ,\s_tx_data_reg_n_0_[102] ,\s_tx_data_reg_n_0_[101] ,\s_tx_data_reg_n_0_[100] ,\s_tx_data_reg_n_0_[87] ,\s_tx_data_reg_n_0_[86] ,\s_tx_data_reg_n_0_[85] ,\s_tx_data_reg_n_0_[84] ,\s_tx_data_reg_n_0_[83] ,\s_tx_data_reg_n_0_[82] ,\s_tx_data_reg_n_0_[81] ,\s_tx_data_reg_n_0_[80] ,\s_tx_data_reg_n_0_[79] ,\s_tx_data_reg_n_0_[78] ,\s_tx_data_reg_n_0_[77] ,\s_tx_data_reg_n_0_[76] ,\s_tx_data_reg_n_0_[63] ,\s_tx_data_reg_n_0_[62] ,\s_tx_data_reg_n_0_[61] ,\s_tx_data_reg_n_0_[60] ,\s_tx_data_reg_n_0_[59] ,\s_tx_data_reg_n_0_[58] ,\s_tx_data_reg_n_0_[57] ,\s_tx_data_reg_n_0_[56] ,\s_tx_data_reg_n_0_[55] ,\s_tx_data_reg_n_0_[54] ,\s_tx_data_reg_n_0_[53] ,\s_tx_data_reg_n_0_[52] ,\s_tx_data_reg_n_0_[39] ,\s_tx_data_reg_n_0_[38] ,\s_tx_data_reg_n_0_[37] ,\s_tx_data_reg_n_0_[36] ,\s_tx_data_reg_n_0_[35] ,\s_tx_data_reg_n_0_[34] ,\s_tx_data_reg_n_0_[33] ,\s_tx_data_reg_n_0_[32] ,\s_tx_data_reg_n_0_[31] ,\s_tx_data_reg_n_0_[30] ,\s_tx_data_reg_n_0_[29] ,\s_tx_data_reg_n_0_[28] ,\s_tx_data_reg_n_0_[15] ,\s_tx_data_reg_n_0_[14] ,\s_tx_data_reg_n_0_[13] ,\s_tx_data_reg_n_0_[12] ,\s_tx_data_reg_n_0_[11] ,\s_tx_data_reg_n_0_[10] ,\s_tx_data_reg_n_0_[9] ,\s_tx_data_reg_n_0_[8] ,\s_tx_data_reg_n_0_[7] ,\s_tx_data_reg_n_0_[6] ,\s_tx_data_reg_n_0_[5] ,\s_tx_data_reg_n_0_[4] }),
- .\v_ch_address_reg[0] (cmp_spi_n_1),
- .\v_ch_address_reg[0]_0 (\dac_ch_o[0][31]_i_2_n_0 ),
- .\v_ch_address_reg[1] (cmp_spi_n_2));
- (* SOFT_HLUTNM = "soft_lutpair42" *)
- LUT2 #(
- .INIT(4'h7))
- \dac_ch_o[0][31]_i_2
- (.I0(ch_address[0]),
- .I1(ch_address[1]),
- .O(\dac_ch_o[0][31]_i_2_n_0 ));
- FDRE \dac_ch_o_reg[0][0]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[0]),
- .Q(\axi_rdata_reg[31] [0]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][10]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[10]),
- .Q(\axi_rdata_reg[31] [10]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][11]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[11]),
- .Q(\axi_rdata_reg[31] [11]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][12]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[12]),
- .Q(\axi_rdata_reg[31] [12]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][13]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[13]),
- .Q(\axi_rdata_reg[31] [13]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][14]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[14]),
- .Q(\axi_rdata_reg[31] [14]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][15]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[15]),
- .Q(\axi_rdata_reg[31] [15]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][16]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[16]),
- .Q(\axi_rdata_reg[31] [16]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][17]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[17]),
- .Q(\axi_rdata_reg[31] [17]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][18]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[18]),
- .Q(\axi_rdata_reg[31] [18]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][19]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[19]),
- .Q(\axi_rdata_reg[31] [19]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][1]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[1]),
- .Q(\axi_rdata_reg[31] [1]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][20]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[20]),
- .Q(\axi_rdata_reg[31] [20]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][21]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[21]),
- .Q(\axi_rdata_reg[31] [21]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][22]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[22]),
- .Q(\axi_rdata_reg[31] [22]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][23]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[23]),
- .Q(\axi_rdata_reg[31] [23]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][24]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[24]),
- .Q(\axi_rdata_reg[31] [24]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][25]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[25]),
- .Q(\axi_rdata_reg[31] [25]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][26]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[26]),
- .Q(\axi_rdata_reg[31] [26]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][27]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[27]),
- .Q(\axi_rdata_reg[31] [27]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][28]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[28]),
- .Q(\axi_rdata_reg[31] [28]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][29]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[29]),
- .Q(\axi_rdata_reg[31] [29]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][2]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[2]),
- .Q(\axi_rdata_reg[31] [2]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][30]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[30]),
- .Q(\axi_rdata_reg[31] [30]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][31]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[31]),
- .Q(\axi_rdata_reg[31] [31]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][3]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[3]),
- .Q(\axi_rdata_reg[31] [3]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][4]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[4]),
- .Q(\axi_rdata_reg[31] [4]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][5]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[5]),
- .Q(\axi_rdata_reg[31] [5]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][6]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[6]),
- .Q(\axi_rdata_reg[31] [6]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][7]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[7]),
- .Q(\axi_rdata_reg[31] [7]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][8]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[8]),
- .Q(\axi_rdata_reg[31] [8]),
- .R(1'b0));
- FDRE \dac_ch_o_reg[0][9]
- (.C(s00_axi_aclk),
- .CE(cmp_spi_n_0),
- .D(rx_data_o[9]),
- .Q(\axi_rdata_reg[31] [9]),
- .R(1'b0));
- LUT5 #(
- .INIT(32'hFFF70004))
- \s_flag_reset[0]_i_1
- (.I0(\dac_ch_o_reg[0][0]_1 ),
- .I1(\dac_ch_o_reg[0][0]_0 ),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_flag_reset_reg_n_0_[0] ),
- .O(\s_flag_reset[0]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hDFFF1000))
- \s_flag_reset[1]_i_1
- (.I0(\dac_ch_o_reg[0][0]_1 ),
- .I1(ch_address[1]),
- .I2(\dac_ch_o_reg[0][0]_0 ),
- .I3(ch_address[0]),
- .I4(p_2_in),
- .O(\s_flag_reset[1]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hFF7F0040))
- \s_flag_reset[2]_i_1
- (.I0(\dac_ch_o_reg[0][0]_1 ),
- .I1(\dac_ch_o_reg[0][0]_0 ),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(p_1_in),
- .O(\s_flag_reset[2]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h7FFF4000))
- \s_flag_reset[3]_i_1
- (.I0(\dac_ch_o_reg[0][0]_1 ),
- .I1(\dac_ch_o_reg[0][0]_0 ),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(p_0_in),
- .O(\s_flag_reset[3]_i_1_n_0 ));
- FDRE \s_flag_reset_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_flag_reset[0]_i_1_n_0 ),
- .Q(\s_flag_reset_reg_n_0_[0] ),
- .R(SR));
- FDRE \s_flag_reset_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_flag_reset[1]_i_1_n_0 ),
- .Q(p_2_in),
- .R(SR));
- FDRE \s_flag_reset_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_flag_reset[2]_i_1_n_0 ),
- .Q(p_1_in),
- .R(SR));
- FDRE \s_flag_reset_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_flag_reset[3]_i_1_n_0 ),
- .Q(p_0_in),
- .R(SR));
- FDRE s_start_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_start_reg_0),
- .Q(s_start),
- .R(SR));
- LUT6 #(
- .INIT(64'h0C00080808080808))
- \s_state[1]_i_2
- (.I0(\[0].[2].s_reqs_reg[2][changed_n_0_] ),
- .I1(\dac_ch_o_reg[0][0]_1 ),
- .I2(\dac_ch_o_reg[0][0]_0 ),
- .I3(\[1].[3].s_reqs_reg[7][changed]__1 ),
- .I4(ch_address[1]),
- .I5(ch_address[0]),
- .O(\s_state[1]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0000FFFE00000000))
- \s_state[1]_i_3
- (.I0(\[0].[3].s_reqs_reg[3][changed_n_0_] ),
- .I1(\[1].[0].s_reqs_reg[4][changed]__1 ),
- .I2(\data_rw_o_reg[11][2] [0]),
- .I3(\s_state[1]_i_5_n_0 ),
- .I4(\dac_ch_o_reg[0][0]_0 ),
- .I5(\dac_ch_o_reg[0][0]_1 ),
- .O(\s_state[1]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFE2F0F0FFE2))
- \s_state[1]_i_5
- (.I0(\[0].[0].s_reqs_reg[0][changed_n_0_] ),
- .I1(ch_address[0]),
- .I2(\[1].[1].s_reqs_reg[5][changed]__1 ),
- .I3(\[0].[1].s_reqs_reg[1][changed_n_0_] ),
- .I4(ch_address[1]),
- .I5(\[1].[2].s_reqs_reg[6][changed]__1 ),
- .O(\s_state[1]_i_5_n_0 ));
- FDRE \s_state_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(cmp_spi_n_3),
- .Q(\dac_ch_o_reg[0][0]_1 ),
- .R(SR));
- FDRE \s_state_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(cmp_spi_n_4),
- .Q(\dac_ch_o_reg[0][0]_0 ),
- .R(SR));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[100]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [0]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0 [0]),
- .I5(\s_tx_data[100]_i_2_n_0 ),
- .O(\s_tx_data[100]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[100]_i_2
- (.I0(\[4].[0].s_reqs_reg[16][value]__0 [0]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0 [0]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0 [0]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[100]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[101]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [1]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0 [1]),
- .I5(\s_tx_data[101]_i_2_n_0 ),
- .O(\s_tx_data[101]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[101]_i_2
- (.I0(\[4].[0].s_reqs_reg[16][value]__0 [1]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0 [1]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0 [1]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[101]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[102]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [2]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0 [2]),
- .I5(\s_tx_data[102]_i_2_n_0 ),
- .O(\s_tx_data[102]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[102]_i_2
- (.I0(\[4].[0].s_reqs_reg[16][value]__0 [2]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0 [2]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0 [2]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[102]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[103]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [3]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0 [3]),
- .I5(\s_tx_data[103]_i_2_n_0 ),
- .O(\s_tx_data[103]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[103]_i_2
- (.I0(\[4].[0].s_reqs_reg[16][value]__0 [3]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0 [3]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0 [3]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[103]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[104]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [4]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0 [4]),
- .I5(\s_tx_data[104]_i_2_n_0 ),
- .O(\s_tx_data[104]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[104]_i_2
- (.I0(\[4].[0].s_reqs_reg[16][value]__0 [4]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0 [4]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0 [4]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[104]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[105]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [5]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0 [5]),
- .I5(\s_tx_data[105]_i_2_n_0 ),
- .O(\s_tx_data[105]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[105]_i_2
- (.I0(\[4].[0].s_reqs_reg[16][value]__0 [5]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0 [5]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0 [5]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[105]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[106]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [6]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0 [6]),
- .I5(\s_tx_data[106]_i_2_n_0 ),
- .O(\s_tx_data[106]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[106]_i_2
- (.I0(\[4].[0].s_reqs_reg[16][value]__0 [6]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0 [6]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0 [6]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[106]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[107]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [7]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0 [7]),
- .I5(\s_tx_data[107]_i_2_n_0 ),
- .O(\s_tx_data[107]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[107]_i_2
- (.I0(\[4].[0].s_reqs_reg[16][value]__0 [7]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0 [7]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0 [7]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[107]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[108]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [8]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0 [8]),
- .I5(\s_tx_data[108]_i_2_n_0 ),
- .O(\s_tx_data[108]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[108]_i_2
- (.I0(\[4].[0].s_reqs_reg[16][value]__0 [8]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0 [8]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0 [8]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[108]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[109]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [9]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0 [9]),
- .I5(\s_tx_data[109]_i_2_n_0 ),
- .O(\s_tx_data[109]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[109]_i_2
- (.I0(\[4].[0].s_reqs_reg[16][value]__0 [9]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0 [9]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0 [9]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[109]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[10]_i_1
- (.I0(Q[6]),
- .I1(\data_rw_o_reg[11][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[10]_i_2_n_0 ),
- .O(\s_reqs[0][value] [6]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[10]_i_2
- (.I0(\s_tx_data_reg[111]_0 [6]),
- .I1(\s_tx_data_reg[15]_0 [6]),
- .I2(\s_tx_data_reg[15]_1 [6]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[10]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[110]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [10]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0 [10]),
- .I5(\s_tx_data[110]_i_2_n_0 ),
- .O(\s_tx_data[110]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[110]_i_2
- (.I0(\[4].[0].s_reqs_reg[16][value]__0 [10]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0 [10]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0 [10]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[110]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[111]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [11]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[4].[3].s_reqs_reg[19][value]__0 [11]),
- .I5(\s_tx_data[111]_i_2_n_0 ),
- .O(\s_tx_data[111]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[111]_i_2
- (.I0(\[4].[0].s_reqs_reg[16][value]__0 [11]),
- .I1(\[4].[1].s_reqs_reg[17][value]__0 [11]),
- .I2(\[4].[2].s_reqs_reg[18][value]__0 [11]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[111]_i_2_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_tx_data[113]_i_1
- (.I0(\dac_ch_o_reg[0][0]_1 ),
- .I1(\dac_ch_o_reg[0][0]_0 ),
- .I2(s00_axi_aresetn),
- .O(\s_tx_data[113]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[11]_i_1
- (.I0(Q[7]),
- .I1(\data_rw_o_reg[11][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[11]_i_2_n_0 ),
- .O(\s_reqs[0][value] [7]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[11]_i_2
- (.I0(\s_tx_data_reg[111]_0 [7]),
- .I1(\s_tx_data_reg[15]_0 [7]),
- .I2(\s_tx_data_reg[15]_1 [7]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[11]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[12]_i_1
- (.I0(Q[8]),
- .I1(\data_rw_o_reg[11][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[12]_i_2_n_0 ),
- .O(\s_reqs[0][value] [8]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[12]_i_2
- (.I0(\s_tx_data_reg[111]_0 [8]),
- .I1(\s_tx_data_reg[15]_0 [8]),
- .I2(\s_tx_data_reg[15]_1 [8]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[12]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[13]_i_1
- (.I0(Q[9]),
- .I1(\data_rw_o_reg[11][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[13]_i_2_n_0 ),
- .O(\s_reqs[0][value] [9]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[13]_i_2
- (.I0(\s_tx_data_reg[111]_0 [9]),
- .I1(\s_tx_data_reg[15]_0 [9]),
- .I2(\s_tx_data_reg[15]_1 [9]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[13]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair42" *)
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[14]_i_1
- (.I0(Q[10]),
- .I1(\data_rw_o_reg[11][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[14]_i_2_n_0 ),
- .O(\s_reqs[0][value] [10]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[14]_i_2
- (.I0(\s_tx_data_reg[111]_0 [10]),
- .I1(\s_tx_data_reg[15]_0 [10]),
- .I2(\s_tx_data_reg[15]_1 [10]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[14]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[15]_i_1
- (.I0(Q[11]),
- .I1(\data_rw_o_reg[11][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[15]_i_2_n_0 ),
- .O(\s_reqs[0][value] [11]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[15]_i_2
- (.I0(\s_tx_data_reg[111]_0 [11]),
- .I1(\s_tx_data_reg[15]_0 [11]),
- .I2(\s_tx_data_reg[15]_1 [11]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[15]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[28]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [0]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [0]),
- .I5(\s_tx_data[28]_i_2_n_0 ),
- .O(\s_tx_data[28]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[28]_i_2
- (.I0(\s_tx_data_reg[39]_1 [0]),
- .I1(\s_tx_data_reg[39]_2 [0]),
- .I2(\s_tx_data_reg[39]_3 [0]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[28]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[29]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [1]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [1]),
- .I5(\s_tx_data[29]_i_2_n_0 ),
- .O(\s_tx_data[29]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[29]_i_2
- (.I0(\s_tx_data_reg[39]_1 [1]),
- .I1(\s_tx_data_reg[39]_2 [1]),
- .I2(\s_tx_data_reg[39]_3 [1]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[29]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[30]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [2]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [2]),
- .I5(\s_tx_data[30]_i_2_n_0 ),
- .O(\s_tx_data[30]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[30]_i_2
- (.I0(\s_tx_data_reg[39]_1 [2]),
- .I1(\s_tx_data_reg[39]_2 [2]),
- .I2(\s_tx_data_reg[39]_3 [2]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[30]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[31]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [3]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [3]),
- .I5(\s_tx_data[31]_i_2_n_0 ),
- .O(\s_tx_data[31]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[31]_i_2
- (.I0(\s_tx_data_reg[39]_1 [3]),
- .I1(\s_tx_data_reg[39]_2 [3]),
- .I2(\s_tx_data_reg[39]_3 [3]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[31]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[32]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [4]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [4]),
- .I5(\s_tx_data[32]_i_2_n_0 ),
- .O(\s_tx_data[32]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[32]_i_2
- (.I0(\s_tx_data_reg[39]_1 [4]),
- .I1(\s_tx_data_reg[39]_2 [4]),
- .I2(\s_tx_data_reg[39]_3 [4]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[32]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[33]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [5]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [5]),
- .I5(\s_tx_data[33]_i_2_n_0 ),
- .O(\s_tx_data[33]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[33]_i_2
- (.I0(\s_tx_data_reg[39]_1 [5]),
- .I1(\s_tx_data_reg[39]_2 [5]),
- .I2(\s_tx_data_reg[39]_3 [5]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[33]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[34]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [6]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [6]),
- .I5(\s_tx_data[34]_i_2_n_0 ),
- .O(\s_tx_data[34]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[34]_i_2
- (.I0(\s_tx_data_reg[39]_1 [6]),
- .I1(\s_tx_data_reg[39]_2 [6]),
- .I2(\s_tx_data_reg[39]_3 [6]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[34]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[35]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [7]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [7]),
- .I5(\s_tx_data[35]_i_2_n_0 ),
- .O(\s_tx_data[35]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[35]_i_2
- (.I0(\s_tx_data_reg[39]_1 [7]),
- .I1(\s_tx_data_reg[39]_2 [7]),
- .I2(\s_tx_data_reg[39]_3 [7]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[35]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[36]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [8]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [8]),
- .I5(\s_tx_data[36]_i_2_n_0 ),
- .O(\s_tx_data[36]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[36]_i_2
- (.I0(\s_tx_data_reg[39]_1 [8]),
- .I1(\s_tx_data_reg[39]_2 [8]),
- .I2(\s_tx_data_reg[39]_3 [8]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[36]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[37]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [9]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [9]),
- .I5(\s_tx_data[37]_i_2_n_0 ),
- .O(\s_tx_data[37]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[37]_i_2
- (.I0(\s_tx_data_reg[39]_1 [9]),
- .I1(\s_tx_data_reg[39]_2 [9]),
- .I2(\s_tx_data_reg[39]_3 [9]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[37]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[38]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [10]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [10]),
- .I5(\s_tx_data[38]_i_2_n_0 ),
- .O(\s_tx_data[38]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[38]_i_2
- (.I0(\s_tx_data_reg[39]_1 [10]),
- .I1(\s_tx_data_reg[39]_2 [10]),
- .I2(\s_tx_data_reg[39]_3 [10]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[38]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[39]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [11]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\s_tx_data_reg[39]_0 [11]),
- .I5(\s_tx_data[39]_i_2_n_0 ),
- .O(\s_tx_data[39]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[39]_i_2
- (.I0(\s_tx_data_reg[39]_1 [11]),
- .I1(\s_tx_data_reg[39]_2 [11]),
- .I2(\s_tx_data_reg[39]_3 [11]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[39]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[4]_i_1
- (.I0(Q[0]),
- .I1(\data_rw_o_reg[11][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[4]_i_2_n_0 ),
- .O(\s_reqs[0][value] [0]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[4]_i_2
- (.I0(\s_tx_data_reg[111]_0 [0]),
- .I1(\s_tx_data_reg[15]_0 [0]),
- .I2(\s_tx_data_reg[15]_1 [0]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[4]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[52]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [0]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0 [0]),
- .I5(\s_tx_data[52]_i_2_n_0 ),
- .O(\s_tx_data[52]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[52]_i_2
- (.I0(\[2].[0].s_reqs_reg[8][value]__0 [0]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0 [0]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0 [0]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[52]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[53]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [1]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0 [1]),
- .I5(\s_tx_data[53]_i_2_n_0 ),
- .O(\s_tx_data[53]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[53]_i_2
- (.I0(\[2].[0].s_reqs_reg[8][value]__0 [1]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0 [1]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0 [1]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[53]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[54]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [2]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0 [2]),
- .I5(\s_tx_data[54]_i_2_n_0 ),
- .O(\s_tx_data[54]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[54]_i_2
- (.I0(\[2].[0].s_reqs_reg[8][value]__0 [2]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0 [2]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0 [2]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[54]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[55]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [3]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0 [3]),
- .I5(\s_tx_data[55]_i_2_n_0 ),
- .O(\s_tx_data[55]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[55]_i_2
- (.I0(\[2].[0].s_reqs_reg[8][value]__0 [3]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0 [3]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0 [3]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[55]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[56]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [4]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0 [4]),
- .I5(\s_tx_data[56]_i_2_n_0 ),
- .O(\s_tx_data[56]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[56]_i_2
- (.I0(\[2].[0].s_reqs_reg[8][value]__0 [4]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0 [4]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0 [4]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[56]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[57]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [5]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0 [5]),
- .I5(\s_tx_data[57]_i_2_n_0 ),
- .O(\s_tx_data[57]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[57]_i_2
- (.I0(\[2].[0].s_reqs_reg[8][value]__0 [5]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0 [5]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0 [5]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[57]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[58]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [6]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0 [6]),
- .I5(\s_tx_data[58]_i_2_n_0 ),
- .O(\s_tx_data[58]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[58]_i_2
- (.I0(\[2].[0].s_reqs_reg[8][value]__0 [6]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0 [6]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0 [6]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[58]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[59]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [7]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0 [7]),
- .I5(\s_tx_data[59]_i_2_n_0 ),
- .O(\s_tx_data[59]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[59]_i_2
- (.I0(\[2].[0].s_reqs_reg[8][value]__0 [7]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0 [7]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0 [7]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[59]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[5]_i_1
- (.I0(Q[1]),
- .I1(\data_rw_o_reg[11][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[5]_i_2_n_0 ),
- .O(\s_reqs[0][value] [1]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[5]_i_2
- (.I0(\s_tx_data_reg[111]_0 [1]),
- .I1(\s_tx_data_reg[15]_0 [1]),
- .I2(\s_tx_data_reg[15]_1 [1]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[5]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[60]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [8]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0 [8]),
- .I5(\s_tx_data[60]_i_2_n_0 ),
- .O(\s_tx_data[60]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[60]_i_2
- (.I0(\[2].[0].s_reqs_reg[8][value]__0 [8]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0 [8]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0 [8]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[60]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[61]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [9]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0 [9]),
- .I5(\s_tx_data[61]_i_2_n_0 ),
- .O(\s_tx_data[61]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[61]_i_2
- (.I0(\[2].[0].s_reqs_reg[8][value]__0 [9]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0 [9]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0 [9]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[61]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[62]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [10]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0 [10]),
- .I5(\s_tx_data[62]_i_2_n_0 ),
- .O(\s_tx_data[62]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[62]_i_2
- (.I0(\[2].[0].s_reqs_reg[8][value]__0 [10]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0 [10]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0 [10]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[62]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[63]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [11]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[2].[3].s_reqs_reg[11][value]__0 [11]),
- .I5(\s_tx_data[63]_i_2_n_0 ),
- .O(\s_tx_data[63]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[63]_i_2
- (.I0(\[2].[0].s_reqs_reg[8][value]__0 [11]),
- .I1(\[2].[1].s_reqs_reg[9][value]__0 [11]),
- .I2(\[2].[2].s_reqs_reg[10][value]__0 [11]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[63]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[6]_i_1
- (.I0(Q[2]),
- .I1(\data_rw_o_reg[11][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[6]_i_2_n_0 ),
- .O(\s_reqs[0][value] [2]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[6]_i_2
- (.I0(\s_tx_data_reg[111]_0 [2]),
- .I1(\s_tx_data_reg[15]_0 [2]),
- .I2(\s_tx_data_reg[15]_1 [2]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[6]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[76]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [0]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0 [0]),
- .I5(\s_tx_data[76]_i_2_n_0 ),
- .O(\s_tx_data[76]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[76]_i_2
- (.I0(\[3].[0].s_reqs_reg[12][value]__0 [0]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0 [0]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0 [0]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[76]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[77]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [1]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0 [1]),
- .I5(\s_tx_data[77]_i_2_n_0 ),
- .O(\s_tx_data[77]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[77]_i_2
- (.I0(\[3].[0].s_reqs_reg[12][value]__0 [1]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0 [1]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0 [1]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[77]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[78]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [2]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0 [2]),
- .I5(\s_tx_data[78]_i_2_n_0 ),
- .O(\s_tx_data[78]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[78]_i_2
- (.I0(\[3].[0].s_reqs_reg[12][value]__0 [2]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0 [2]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0 [2]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[78]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[79]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [3]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0 [3]),
- .I5(\s_tx_data[79]_i_2_n_0 ),
- .O(\s_tx_data[79]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[79]_i_2
- (.I0(\[3].[0].s_reqs_reg[12][value]__0 [3]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0 [3]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0 [3]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[79]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[7]_i_1
- (.I0(Q[3]),
- .I1(\data_rw_o_reg[11][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[7]_i_2_n_0 ),
- .O(\s_reqs[0][value] [3]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[7]_i_2
- (.I0(\s_tx_data_reg[111]_0 [3]),
- .I1(\s_tx_data_reg[15]_0 [3]),
- .I2(\s_tx_data_reg[15]_1 [3]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[7]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[80]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [4]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0 [4]),
- .I5(\s_tx_data[80]_i_2_n_0 ),
- .O(\s_tx_data[80]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[80]_i_2
- (.I0(\[3].[0].s_reqs_reg[12][value]__0 [4]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0 [4]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0 [4]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[80]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[81]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [5]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0 [5]),
- .I5(\s_tx_data[81]_i_2_n_0 ),
- .O(\s_tx_data[81]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[81]_i_2
- (.I0(\[3].[0].s_reqs_reg[12][value]__0 [5]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0 [5]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0 [5]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[81]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[82]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [6]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0 [6]),
- .I5(\s_tx_data[82]_i_2_n_0 ),
- .O(\s_tx_data[82]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[82]_i_2
- (.I0(\[3].[0].s_reqs_reg[12][value]__0 [6]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0 [6]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0 [6]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[82]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[83]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [7]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0 [7]),
- .I5(\s_tx_data[83]_i_2_n_0 ),
- .O(\s_tx_data[83]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[83]_i_2
- (.I0(\[3].[0].s_reqs_reg[12][value]__0 [7]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0 [7]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0 [7]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[83]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[84]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [8]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0 [8]),
- .I5(\s_tx_data[84]_i_2_n_0 ),
- .O(\s_tx_data[84]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[84]_i_2
- (.I0(\[3].[0].s_reqs_reg[12][value]__0 [8]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0 [8]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0 [8]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[84]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[85]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [9]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0 [9]),
- .I5(\s_tx_data[85]_i_2_n_0 ),
- .O(\s_tx_data[85]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[85]_i_2
- (.I0(\[3].[0].s_reqs_reg[12][value]__0 [9]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0 [9]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0 [9]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[85]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[86]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [10]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0 [10]),
- .I5(\s_tx_data[86]_i_2_n_0 ),
- .O(\s_tx_data[86]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[86]_i_2
- (.I0(\[3].[0].s_reqs_reg[12][value]__0 [10]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0 [10]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0 [10]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[86]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFD8888888))
- \s_tx_data[87]_i_1
- (.I0(\data_rw_o_reg[11][2] [1]),
- .I1(\s_tx_data_reg[111]_0 [11]),
- .I2(ch_address[1]),
- .I3(ch_address[0]),
- .I4(\[3].[3].s_reqs_reg[15][value]__0 [11]),
- .I5(\s_tx_data[87]_i_2_n_0 ),
- .O(\s_tx_data[87]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h000000F00000CCAA))
- \s_tx_data[87]_i_2
- (.I0(\[3].[0].s_reqs_reg[12][value]__0 [11]),
- .I1(\[3].[1].s_reqs_reg[13][value]__0 [11]),
- .I2(\[3].[2].s_reqs_reg[14][value]__0 [11]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[87]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[8]_i_1
- (.I0(Q[4]),
- .I1(\data_rw_o_reg[11][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[8]_i_2_n_0 ),
- .O(\s_reqs[0][value] [4]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[8]_i_2
- (.I0(\s_tx_data_reg[111]_0 [4]),
- .I1(\s_tx_data_reg[15]_0 [4]),
- .I2(\s_tx_data_reg[15]_1 [4]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[8]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2000))
- \s_tx_data[9]_i_1
- (.I0(Q[5]),
- .I1(\data_rw_o_reg[11][2] [1]),
- .I2(ch_address[0]),
- .I3(ch_address[1]),
- .I4(\s_tx_data[9]_i_2_n_0 ),
- .O(\s_reqs[0][value] [5]));
- LUT6 #(
- .INIT(64'hAAAA00F0AAAACCAA))
- \s_tx_data[9]_i_2
- (.I0(\s_tx_data_reg[111]_0 [5]),
- .I1(\s_tx_data_reg[15]_0 [5]),
- .I2(\s_tx_data_reg[15]_1 [5]),
- .I3(ch_address[0]),
- .I4(\data_rw_o_reg[11][2] [1]),
- .I5(ch_address[1]),
- .O(\s_tx_data[9]_i_2_n_0 ));
- FDRE \s_tx_data_reg[100]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[100]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[100] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[101]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[101]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[101] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[102]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[102]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[102] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[103]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[103]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[103] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[104]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[104]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[104] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[105]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[105]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[105] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[106]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[106]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[106] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[107]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[107]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[107] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[108]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[108]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[108] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[109]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[109]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[109] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[10]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_reqs[0][value] [6]),
- .Q(\s_tx_data_reg_n_0_[10] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[110]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[110]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[110] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[111]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[111]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[111] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[112]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(ch_address[0]),
- .Q(\s_tx_data_reg_n_0_[112] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[113]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(ch_address[1]),
- .Q(\s_tx_data_reg_n_0_[113] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[11]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_reqs[0][value] [7]),
- .Q(\s_tx_data_reg_n_0_[11] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[12]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_reqs[0][value] [8]),
- .Q(\s_tx_data_reg_n_0_[12] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[13]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_reqs[0][value] [9]),
- .Q(\s_tx_data_reg_n_0_[13] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[14]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_reqs[0][value] [10]),
- .Q(\s_tx_data_reg_n_0_[14] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[15]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_reqs[0][value] [11]),
- .Q(\s_tx_data_reg_n_0_[15] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[28]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[28]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[28] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[29]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[29]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[29] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[30]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[30]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[30] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[31]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[31]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[31] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[32]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[32]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[32] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[33]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[33]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[33] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[34]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[34]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[34] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[35]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[35]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[35] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[36]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[36]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[36] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[37]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[37]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[37] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[38]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[38]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[38] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[39]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[39]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[39] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[4]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_reqs[0][value] [0]),
- .Q(\s_tx_data_reg_n_0_[4] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[52]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[52]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[52] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[53]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[53]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[53] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[54]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[54]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[54] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[55]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[55]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[55] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[56]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[56]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[56] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[57]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[57]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[57] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[58]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[58]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[58] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[59]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[59]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[59] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[5]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_reqs[0][value] [1]),
- .Q(\s_tx_data_reg_n_0_[5] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[60]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[60]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[60] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[61]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[61]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[61] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[62]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[62]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[62] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[63]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[63]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[63] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[6]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_reqs[0][value] [2]),
- .Q(\s_tx_data_reg_n_0_[6] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[76]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[76]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[76] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[77]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[77]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[77] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[78]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[78]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[78] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[79]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[79]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[79] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[7]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_reqs[0][value] [3]),
- .Q(\s_tx_data_reg_n_0_[7] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[80]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[80]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[80] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[81]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[81]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[81] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[82]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[82]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[82] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[83]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[83]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[83] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[84]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[84]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[84] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[85]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[85]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[85] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[86]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[86]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[86] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[87]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_tx_data[87]_i_1_n_0 ),
- .Q(\s_tx_data_reg_n_0_[87] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[8]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_reqs[0][value] [4]),
- .Q(\s_tx_data_reg_n_0_[8] ),
- .R(1'b0));
- FDRE \s_tx_data_reg[9]
- (.C(s00_axi_aclk),
- .CE(\s_tx_data[113]_i_1_n_0 ),
- .D(\s_reqs[0][value] [5]),
- .Q(\s_tx_data_reg_n_0_[9] ),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h00000002FFFFFFFF))
- \v_ch_address[1]_i_3
- (.I0(\v_ch_address[1]_i_5_n_0 ),
- .I1(\data_rw_o_reg[11][2] [0]),
- .I2(\[1].[0].s_reqs_reg[4][changed]__1 ),
- .I3(\[0].[3].s_reqs_reg[3][changed_n_0_] ),
- .I4(\[0].[2].s_reqs_reg[2][changed_n_0_] ),
- .I5(\dac_ch_o_reg[0][0]_1 ),
- .O(\v_ch_address[1]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h0003000000033355))
- \v_ch_address[1]_i_5
- (.I0(\[0].[0].s_reqs_reg[0][changed_n_0_] ),
- .I1(\[1].[1].s_reqs_reg[5][changed]__1 ),
- .I2(\[1].[2].s_reqs_reg[6][changed]__1 ),
- .I3(ch_address[0]),
- .I4(ch_address[1]),
- .I5(\[0].[1].s_reqs_reg[1][changed_n_0_] ),
- .O(\v_ch_address[1]_i_5_n_0 ));
- FDRE \v_ch_address_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(cmp_spi_n_1),
- .Q(ch_address[0]),
- .R(1'b0));
- FDRE \v_ch_address_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(cmp_spi_n_2),
- .Q(ch_address[1]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- Q,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input [0:0]Q;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(Q),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__94
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__54
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_100
- (s_buff3_reg_0,
- s_count_reg,
- \v_dout_reg[7] ,
- intr_o_reg,
- E,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_0,
- s_pulseLed_reg_0,
- \data_rw_o_reg[79][7] ,
- \v_cmp_reg[2] ,
- s_buff2_reg_1,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output \v_dout_reg[7] ;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_0;
- input s_pulseLed_reg_0;
- input [0:0]\data_rw_o_reg[79][7] ;
- input [2:0]\v_cmp_reg[2] ;
- input [1:0]s_buff2_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [0:0]\data_rw_o_reg[79][7] ;
- wire [0:0]intr_o_reg;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__19_n_0;
- wire [4:0]s_buff2_reg_0;
- wire [1:0]s_buff2_reg_1;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire [2:0]\v_cmp_reg[2] ;
- wire \v_dout_reg[7] ;
-
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_o_i_9__0
- (.I0(\v_cmp_reg[2] [0]),
- .I1(s_buff3_reg_0),
- .I2(s_buff2_reg_1[1]),
- .I3(\v_cmp_reg[2] [2]),
- .I4(s_buff2_reg_1[0]),
- .I5(\v_cmp_reg[2] [1]),
- .O(intr_o_reg));
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__19
- (.I0(s_comparators_i_0),
- .O(s_buff1_i_1__19_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__19_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__19
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__67
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair47" *)
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__27
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
- (* SOFT_HLUTNM = "soft_lutpair47" *)
- LUT2 #(
- .INIT(4'h8))
- \v_dout[7]_i_1__0
- (.I0(s_buff3_reg_0),
- .I1(\data_rw_o_reg[79][7] ),
- .O(\v_dout_reg[7] ));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_132
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- Q,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input [0:0]Q;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(Q),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__66
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__26
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_134
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- Q,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input [0:0]Q;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(Q),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__65
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__25
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_136
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- Q,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input [0:0]Q;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(Q),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__64
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__24
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_138
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- Q,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input [0:0]Q;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(Q),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__63
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__23
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_140
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- D,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input [0:0]D;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__62
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__22
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_142
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- D,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input [0:0]D;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__61
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__21
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_144
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- D,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input [0:0]D;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__60
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__20
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_146
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- D,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input [0:0]D;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__59
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__19
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_149
- (s_buff3_reg_0,
- s_count_reg,
- CO,
- E,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_9,
- s_pulseLed_reg_0,
- \v_cmp_reg[6] ,
- \v_cmp_reg[18] ,
- \v_cmp_reg[11] ,
- s_buff2_reg_1,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]CO;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_9;
- input s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[6] ;
- input [2:0]\v_cmp_reg[18] ;
- input [2:0]\v_cmp_reg[11] ;
- input [1:0]s_buff2_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]CO;
- wire [0:0]E;
- wire [0:0]SR;
- wire intr_o_i_6_n_0;
- wire intr_o_reg_i_1_n_2;
- wire intr_o_reg_i_1_n_3;
- wire intr_o_reg_i_2_n_0;
- wire intr_o_reg_i_2_n_1;
- wire intr_o_reg_i_2_n_2;
- wire intr_o_reg_i_2_n_3;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__8_n_0;
- wire [4:0]s_buff2_reg_0;
- wire [1:0]s_buff2_reg_1;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_9;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire [2:0]\v_cmp_reg[11] ;
- wire [2:0]\v_cmp_reg[18] ;
- wire [2:0]\v_cmp_reg[6] ;
- wire [3:3]NLW_intr_o_reg_i_1_CO_UNCONNECTED;
- wire [3:0]NLW_intr_o_reg_i_1_O_UNCONNECTED;
- wire [3:0]NLW_intr_o_reg_i_2_O_UNCONNECTED;
-
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_o_i_6
- (.I0(\v_cmp_reg[11] [0]),
- .I1(s_buff3_reg_0),
- .I2(s_buff2_reg_1[1]),
- .I3(\v_cmp_reg[11] [2]),
- .I4(s_buff2_reg_1[0]),
- .I5(\v_cmp_reg[11] [1]),
- .O(intr_o_i_6_n_0));
- CARRY4 intr_o_reg_i_1
- (.CI(intr_o_reg_i_2_n_0),
- .CO({NLW_intr_o_reg_i_1_CO_UNCONNECTED[3],CO,intr_o_reg_i_1_n_2,intr_o_reg_i_1_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b1,1'b1,1'b1}),
- .O(NLW_intr_o_reg_i_1_O_UNCONNECTED[3:0]),
- .S({1'b0,\v_cmp_reg[18] }));
- CARRY4 intr_o_reg_i_2
- (.CI(1'b0),
- .CO({intr_o_reg_i_2_n_0,intr_o_reg_i_2_n_1,intr_o_reg_i_2_n_2,intr_o_reg_i_2_n_3}),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(NLW_intr_o_reg_i_2_O_UNCONNECTED[3:0]),
- .S({intr_o_i_6_n_0,\v_cmp_reg[6] }));
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__8
- (.I0(s_comparators_i_9),
- .O(s_buff1_i_1__8_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__8_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__48
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__8
- (.I0(s_buff3_reg_0),
- .O(E));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__8
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_152
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_8,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_8;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__7_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_8;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__7
- (.I0(s_comparators_i_8),
- .O(s_buff1_i_1__7_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__7_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__47
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__7
- (.I0(s_buff3_reg_0),
- .O(E));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__7
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_155
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_7,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_7;
- input [0:0]s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__6_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_7;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire [0:0]s_pulseLed_reg_0;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__6
- (.I0(s_comparators_i_7),
- .O(s_buff1_i_1__6_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__6_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__46
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__6
- (.I0(s_buff3_reg_0),
- .O(E));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__6
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_158
- (s_buff3_reg_0,
- s_count_reg,
- intr_o_reg,
- E,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_6,
- s_pulseLed_reg_0,
- \v_cmp_reg[8] ,
- s_buff2_reg_1,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_6;
- input s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[8] ;
- input [1:0]s_buff2_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [0:0]SR;
- wire [0:0]intr_o_reg;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__5_n_0;
- wire [4:0]s_buff2_reg_0;
- wire [1:0]s_buff2_reg_1;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_6;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire [2:0]\v_cmp_reg[8] ;
-
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_o_i_7
- (.I0(\v_cmp_reg[8] [0]),
- .I1(s_buff3_reg_0),
- .I2(s_buff2_reg_1[1]),
- .I3(\v_cmp_reg[8] [2]),
- .I4(s_buff2_reg_1[0]),
- .I5(\v_cmp_reg[8] [1]),
- .O(intr_o_reg));
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__5
- (.I0(s_comparators_i_6),
- .O(s_buff1_i_1__5_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__5_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__45
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__5
- (.I0(s_buff3_reg_0),
- .O(E));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__5
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_161
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_5,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_5;
- input [0:0]s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__4_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_5;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire [0:0]s_pulseLed_reg_0;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__4
- (.I0(s_comparators_i_5),
- .O(s_buff1_i_1__4_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__4_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__4
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__44
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__4
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_164
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_4,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_4;
- input [0:0]s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__3_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_4;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire [0:0]s_pulseLed_reg_0;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__3
- (.I0(s_comparators_i_4),
- .O(s_buff1_i_1__3_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__3_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__3
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__43
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__3
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_167
- (s_buff3_reg_0,
- s_count_reg,
- intr_o_reg,
- E,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_3,
- s_pulseLed_reg_0,
- \v_cmp_reg[5] ,
- s_buff2_reg_1,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_3;
- input s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[5] ;
- input [1:0]s_buff2_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [0:0]SR;
- wire [0:0]intr_o_reg;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__2_n_0;
- wire [4:0]s_buff2_reg_0;
- wire [1:0]s_buff2_reg_1;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_3;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire [2:0]\v_cmp_reg[5] ;
-
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_o_i_8
- (.I0(\v_cmp_reg[5] [0]),
- .I1(s_buff3_reg_0),
- .I2(s_buff2_reg_1[1]),
- .I3(\v_cmp_reg[5] [2]),
- .I4(s_buff2_reg_1[0]),
- .I5(\v_cmp_reg[5] [1]),
- .O(intr_o_reg));
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__2
- (.I0(s_comparators_i_3),
- .O(s_buff1_i_1__2_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__2_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__2
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__42
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__2
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_170
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_2,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_2;
- input [0:0]s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__1_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_2;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire [0:0]s_pulseLed_reg_0;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__1
- (.I0(s_comparators_i_2),
- .O(s_buff1_i_1__1_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__1_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__1
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__41
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__1
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_173
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_1,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_1;
- input [0:0]s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__0_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_1;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire [0:0]s_pulseLed_reg_0;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__0
- (.I0(s_comparators_i_1),
- .O(s_buff1_i_1__0_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__0_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__0
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__40
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__0
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_176
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_19,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_19;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire pulse_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_19;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__18
- (.I0(s_comparators_i_19),
- .O(pulse_i));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(pulse_i),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__18
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__58
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__18
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_179
- (s_buff3_reg_0,
- s_count_reg,
- intr_o_reg,
- E,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_18,
- s_pulseLed_reg_0,
- \v_cmp_reg[19] ,
- s_buff2_reg_1,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_18;
- input s_pulseLed_reg_0;
- input [1:0]\v_cmp_reg[19] ;
- input [0:0]s_buff2_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [0:0]SR;
- wire [0:0]intr_o_reg;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__17_n_0;
- wire [4:0]s_buff2_reg_0;
- wire [0:0]s_buff2_reg_1;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_18;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire [1:0]\v_cmp_reg[19] ;
-
- LUT4 #(
- .INIT(16'h9009))
- intr_o_i_3
- (.I0(\v_cmp_reg[19] [0]),
- .I1(s_buff3_reg_0),
- .I2(\v_cmp_reg[19] [1]),
- .I3(s_buff2_reg_1),
- .O(intr_o_reg));
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__17
- (.I0(s_comparators_i_18),
- .O(s_buff1_i_1__17_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__17_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__17
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__57
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__17
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_182
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_17,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_17;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__16_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_17;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__16
- (.I0(s_comparators_i_17),
- .O(s_buff1_i_1__16_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__16_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__16
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__56
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__16
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_185
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_16,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_16;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__15_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_16;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__15
- (.I0(s_comparators_i_16),
- .O(s_buff1_i_1__15_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__15_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__15
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__55
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__15
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_188
- (s_buff3_reg_0,
- s_count_reg,
- intr_o_reg,
- E,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_15,
- s_pulseLed_reg_0,
- \v_cmp_reg[17] ,
- s_buff2_reg_1,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_15;
- input s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[17] ;
- input [1:0]s_buff2_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [0:0]SR;
- wire [0:0]intr_o_reg;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__14_n_0;
- wire [4:0]s_buff2_reg_0;
- wire [1:0]s_buff2_reg_1;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_15;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire [2:0]\v_cmp_reg[17] ;
-
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_o_i_4
- (.I0(\v_cmp_reg[17] [0]),
- .I1(s_buff3_reg_0),
- .I2(s_buff2_reg_1[1]),
- .I3(\v_cmp_reg[17] [2]),
- .I4(s_buff2_reg_1[0]),
- .I5(\v_cmp_reg[17] [1]),
- .O(intr_o_reg));
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__14
- (.I0(s_comparators_i_15),
- .O(s_buff1_i_1__14_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__14_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__14
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__54
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__14
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_191
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_14,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_14;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__13_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_14;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__13
- (.I0(s_comparators_i_14),
- .O(s_buff1_i_1__13_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__13_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__13
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__53
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__13
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_194
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_13,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_13;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__12_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_13;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__12
- (.I0(s_comparators_i_13),
- .O(s_buff1_i_1__12_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__12_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__12
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__52
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__12
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_197
- (s_buff3_reg_0,
- s_count_reg,
- intr_o_reg,
- E,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_12,
- s_pulseLed_reg_0,
- \v_cmp_reg[14] ,
- s_buff2_reg_1,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_12;
- input s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[14] ;
- input [1:0]s_buff2_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [0:0]SR;
- wire [0:0]intr_o_reg;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__11_n_0;
- wire [4:0]s_buff2_reg_0;
- wire [1:0]s_buff2_reg_1;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_12;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire [2:0]\v_cmp_reg[14] ;
-
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_o_i_5
- (.I0(\v_cmp_reg[14] [0]),
- .I1(s_buff3_reg_0),
- .I2(s_buff2_reg_1[1]),
- .I3(\v_cmp_reg[14] [2]),
- .I4(s_buff2_reg_1[0]),
- .I5(\v_cmp_reg[14] [1]),
- .O(intr_o_reg));
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__11
- (.I0(s_comparators_i_12),
- .O(s_buff1_i_1__11_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__11_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__11
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__51
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__11
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_200
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_11,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_11;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__10_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_11;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__10
- (.I0(s_comparators_i_11),
- .O(s_buff1_i_1__10_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__10_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__10
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__50
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__10
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_203
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_10,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_10;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__9_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_10;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__9
- (.I0(s_comparators_i_10),
- .O(s_buff1_i_1__9_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__9_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__49
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__9
- (.I0(s_buff3_reg_0),
- .O(E));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__9
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_206
- (s_buff3_reg_0,
- s_count_reg,
- \v_dout_reg[7] ,
- intr_o_reg,
- E,
- s_pulseLed_reg,
- s_buff2_reg_0,
- SR,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_0,
- s_pulseLed_reg_0,
- \data_rw_o_reg[11][7] ,
- \v_cmp_reg[2] ,
- s_buff2_reg_1,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output \v_dout_reg[7] ;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input [0:0]SR;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_0;
- input s_pulseLed_reg_0;
- input [0:0]\data_rw_o_reg[11][7] ;
- input [2:0]\v_cmp_reg[2] ;
- input [1:0]s_buff2_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [0:0]SR;
- wire [0:0]\data_rw_o_reg[11][7] ;
- wire [0:0]intr_o_reg;
- wire [0:0]p_1_in;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1_n_0;
- wire [4:0]s_buff2_reg_0;
- wire [1:0]s_buff2_reg_1;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire [2:0]\v_cmp_reg[2] ;
- wire \v_dout_reg[7] ;
-
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_o_i_9
- (.I0(\v_cmp_reg[2] [0]),
- .I1(s_buff3_reg_0),
- .I2(s_buff2_reg_1[1]),
- .I3(\v_cmp_reg[2] [2]),
- .I4(s_buff2_reg_1[0]),
- .I5(\v_cmp_reg[2] [1]),
- .O(intr_o_reg));
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1
- (.I0(s_comparators_i_0),
- .O(s_buff1_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1_n_0),
- .Q(p_1_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(SR));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__39
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair36" *)
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
- (* SOFT_HLUTNM = "soft_lutpair36" *)
- LUT2 #(
- .INIT(4'h8))
- \v_dout[7]_i_1
- (.I0(s_buff3_reg_0),
- .I1(\data_rw_o_reg[11][7] ),
- .O(\v_dout_reg[7] ));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_29
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- Q,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input [0:0]Q;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(Q),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__93
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__53
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_31
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- Q,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input [0:0]Q;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(Q),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__92
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__52
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_33
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- Q,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input [0:0]Q;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(Q),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__91
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__51
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_35
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- D,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input [0:0]D;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__90
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__50
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_37
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- D,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input [0:0]D;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__89
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__49
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_39
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- D,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input [0:0]D;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__88
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__48
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_41
- (s_buff3_reg_0,
- s_count_reg,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- D,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input [0:0]D;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
-
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__87
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__47
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_43
- (s_buff3_reg_0,
- s_count_reg,
- CO,
- E,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_9,
- s_pulseLed_reg_0,
- \v_cmp_reg[6] ,
- \v_cmp_reg[18] ,
- \v_cmp_reg[11] ,
- s_buff2_reg_1,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]CO;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_9;
- input s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[6] ;
- input [2:0]\v_cmp_reg[18] ;
- input [2:0]\v_cmp_reg[11] ;
- input [1:0]s_buff2_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]CO;
- wire [0:0]E;
- wire intr_o_i_6__0_n_0;
- wire intr_o_reg_i_1__0_n_2;
- wire intr_o_reg_i_1__0_n_3;
- wire intr_o_reg_i_2__0_n_0;
- wire intr_o_reg_i_2__0_n_1;
- wire intr_o_reg_i_2__0_n_2;
- wire intr_o_reg_i_2__0_n_3;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__28_n_0;
- wire [4:0]s_buff2_reg_0;
- wire [1:0]s_buff2_reg_1;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_9;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire [2:0]\v_cmp_reg[11] ;
- wire [2:0]\v_cmp_reg[18] ;
- wire [2:0]\v_cmp_reg[6] ;
- wire [3:3]NLW_intr_o_reg_i_1__0_CO_UNCONNECTED;
- wire [3:0]NLW_intr_o_reg_i_1__0_O_UNCONNECTED;
- wire [3:0]NLW_intr_o_reg_i_2__0_O_UNCONNECTED;
-
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_o_i_6__0
- (.I0(\v_cmp_reg[11] [0]),
- .I1(s_buff3_reg_0),
- .I2(s_buff2_reg_1[1]),
- .I3(\v_cmp_reg[11] [2]),
- .I4(s_buff2_reg_1[0]),
- .I5(\v_cmp_reg[11] [1]),
- .O(intr_o_i_6__0_n_0));
- CARRY4 intr_o_reg_i_1__0
- (.CI(intr_o_reg_i_2__0_n_0),
- .CO({NLW_intr_o_reg_i_1__0_CO_UNCONNECTED[3],CO,intr_o_reg_i_1__0_n_2,intr_o_reg_i_1__0_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b1,1'b1,1'b1}),
- .O(NLW_intr_o_reg_i_1__0_O_UNCONNECTED[3:0]),
- .S({1'b0,\v_cmp_reg[18] }));
- CARRY4 intr_o_reg_i_2__0
- (.CI(1'b0),
- .CO({intr_o_reg_i_2__0_n_0,intr_o_reg_i_2__0_n_1,intr_o_reg_i_2__0_n_2,intr_o_reg_i_2__0_n_3}),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(NLW_intr_o_reg_i_2__0_O_UNCONNECTED[3:0]),
- .S({intr_o_i_6__0_n_0,\v_cmp_reg[6] }));
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__28
- (.I0(s_comparators_i_9),
- .O(s_buff1_i_1__28_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__28_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__28
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__76
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__36
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_46
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_8,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_8;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__27_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_8;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__27
- (.I0(s_comparators_i_8),
- .O(s_buff1_i_1__27_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__27_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__27
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__75
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__35
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_49
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_7,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_7;
- input [0:0]s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__26_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_7;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire [0:0]s_pulseLed_reg_0;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__26
- (.I0(s_comparators_i_7),
- .O(s_buff1_i_1__26_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__26_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__26
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__74
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__34
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_52
- (s_buff3_reg_0,
- s_count_reg,
- intr_o_reg,
- E,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_6,
- s_pulseLed_reg_0,
- \v_cmp_reg[8] ,
- s_buff2_reg_1,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_6;
- input s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[8] ;
- input [1:0]s_buff2_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [0:0]intr_o_reg;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__25_n_0;
- wire [4:0]s_buff2_reg_0;
- wire [1:0]s_buff2_reg_1;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_6;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire [2:0]\v_cmp_reg[8] ;
-
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_o_i_7__0
- (.I0(\v_cmp_reg[8] [0]),
- .I1(s_buff3_reg_0),
- .I2(s_buff2_reg_1[1]),
- .I3(\v_cmp_reg[8] [2]),
- .I4(s_buff2_reg_1[0]),
- .I5(\v_cmp_reg[8] [1]),
- .O(intr_o_reg));
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__25
- (.I0(s_comparators_i_6),
- .O(s_buff1_i_1__25_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__25_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__25
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__73
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__33
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_55
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_5,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_5;
- input [0:0]s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__24_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_5;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire [0:0]s_pulseLed_reg_0;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__24
- (.I0(s_comparators_i_5),
- .O(s_buff1_i_1__24_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__24_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__24
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__72
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__32
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_58
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_4,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_4;
- input [0:0]s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__23_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_4;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire [0:0]s_pulseLed_reg_0;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__23
- (.I0(s_comparators_i_4),
- .O(s_buff1_i_1__23_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__23_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__23
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__71
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__31
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_61
- (s_buff3_reg_0,
- s_count_reg,
- intr_o_reg,
- E,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_3,
- s_pulseLed_reg_0,
- \v_cmp_reg[5] ,
- s_buff2_reg_1,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_3;
- input s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[5] ;
- input [1:0]s_buff2_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [0:0]intr_o_reg;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__22_n_0;
- wire [4:0]s_buff2_reg_0;
- wire [1:0]s_buff2_reg_1;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_3;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire [2:0]\v_cmp_reg[5] ;
-
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_o_i_8__0
- (.I0(\v_cmp_reg[5] [0]),
- .I1(s_buff3_reg_0),
- .I2(s_buff2_reg_1[1]),
- .I3(\v_cmp_reg[5] [2]),
- .I4(s_buff2_reg_1[0]),
- .I5(\v_cmp_reg[5] [1]),
- .O(intr_o_reg));
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__22
- (.I0(s_comparators_i_3),
- .O(s_buff1_i_1__22_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__22_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__22
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__70
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__30
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_64
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_2,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_2;
- input [0:0]s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__21_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_2;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire [0:0]s_pulseLed_reg_0;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__21
- (.I0(s_comparators_i_2),
- .O(s_buff1_i_1__21_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__21_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__21
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__69
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__29
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_67
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_1,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_1;
- input [0:0]s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__20_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_1;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire [0:0]s_pulseLed_reg_0;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__20
- (.I0(s_comparators_i_1),
- .O(s_buff1_i_1__20_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__20_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__20
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__68
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__28
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_70
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_19,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_19;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]p_1_in;
- wire pulse_i;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_19;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__38
- (.I0(s_comparators_i_19),
- .O(pulse_i));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(pulse_i),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__38
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__86
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__46
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_73
- (s_buff3_reg_0,
- s_count_reg,
- intr_o_reg,
- E,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_18,
- s_pulseLed_reg_0,
- \v_cmp_reg[19] ,
- s_buff2_reg_1,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_18;
- input s_pulseLed_reg_0;
- input [1:0]\v_cmp_reg[19] ;
- input [0:0]s_buff2_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [0:0]intr_o_reg;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__37_n_0;
- wire [4:0]s_buff2_reg_0;
- wire [0:0]s_buff2_reg_1;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_18;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire [1:0]\v_cmp_reg[19] ;
-
- LUT4 #(
- .INIT(16'h9009))
- intr_o_i_3__0
- (.I0(\v_cmp_reg[19] [0]),
- .I1(s_buff3_reg_0),
- .I2(\v_cmp_reg[19] [1]),
- .I3(s_buff2_reg_1),
- .O(intr_o_reg));
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__37
- (.I0(s_comparators_i_18),
- .O(s_buff1_i_1__37_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__37_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__37
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__85
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__45
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_76
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_17,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_17;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__36_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_17;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__36
- (.I0(s_comparators_i_17),
- .O(s_buff1_i_1__36_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__36_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__36
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__84
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__44
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_79
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_16,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_16;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__35_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_16;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__35
- (.I0(s_comparators_i_16),
- .O(s_buff1_i_1__35_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__35_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__35
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__83
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__43
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_82
- (s_buff3_reg_0,
- s_count_reg,
- intr_o_reg,
- E,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_15,
- s_pulseLed_reg_0,
- \v_cmp_reg[17] ,
- s_buff2_reg_1,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_15;
- input s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[17] ;
- input [1:0]s_buff2_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [0:0]intr_o_reg;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__34_n_0;
- wire [4:0]s_buff2_reg_0;
- wire [1:0]s_buff2_reg_1;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_15;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire [2:0]\v_cmp_reg[17] ;
-
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_o_i_4__0
- (.I0(\v_cmp_reg[17] [0]),
- .I1(s_buff3_reg_0),
- .I2(s_buff2_reg_1[1]),
- .I3(\v_cmp_reg[17] [2]),
- .I4(s_buff2_reg_1[0]),
- .I5(\v_cmp_reg[17] [1]),
- .O(intr_o_reg));
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__34
- (.I0(s_comparators_i_15),
- .O(s_buff1_i_1__34_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__34_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__34
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__82
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__42
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_85
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_14,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_14;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__33_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_14;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__33
- (.I0(s_comparators_i_14),
- .O(s_buff1_i_1__33_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__33_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__33
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__81
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__41
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_88
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_13,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_13;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__32_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_13;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__32
- (.I0(s_comparators_i_13),
- .O(s_buff1_i_1__32_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__32_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__32
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__80
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__40
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_91
- (s_buff3_reg_0,
- s_count_reg,
- intr_o_reg,
- E,
- s_pulseLed_reg,
- s_buff2_reg_0,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_12,
- s_pulseLed_reg_0,
- \v_cmp_reg[14] ,
- s_buff2_reg_1,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]s_buff2_reg_0;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_12;
- input s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[14] ;
- input [1:0]s_buff2_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]E;
- wire [0:0]intr_o_reg;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__31_n_0;
- wire [4:0]s_buff2_reg_0;
- wire [1:0]s_buff2_reg_1;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_12;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
- wire s_pulseLed_reg_0;
- wire [2:0]\v_cmp_reg[14] ;
-
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_o_i_5__0
- (.I0(\v_cmp_reg[14] [0]),
- .I1(s_buff3_reg_0),
- .I2(s_buff2_reg_1[1]),
- .I3(\v_cmp_reg[14] [2]),
- .I4(s_buff2_reg_1[0]),
- .I5(\v_cmp_reg[14] [1]),
- .O(intr_o_reg));
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__31
- (.I0(s_comparators_i_12),
- .O(s_buff1_i_1__31_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__31_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__31
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__79
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(s_pulseLed_reg_0),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(s_buff2_reg_0[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[0]),
- .Q(s_buff2_reg_0[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[1]),
- .Q(s_buff2_reg_0[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[2]),
- .Q(s_buff2_reg_0[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(s_buff2_reg_0[3]),
- .Q(s_buff2_reg_0[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__39
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_94
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_11,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_11;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__30_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_11;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__30
- (.I0(s_comparators_i_11),
- .O(s_buff1_i_1__30_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__30_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__30
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__78
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__38
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "doubleBufferEdge" *)
-module system_design_fasec_hwtest_0_0_doubleBufferEdge_97
- (s_buff3_reg_0,
- s_count_reg,
- E,
- s_pulseLed_reg,
- Q,
- rst_i,
- s00_axi_aclk,
- \s_debounce_reg[1]_0 ,
- s_comparators_i_10,
- D,
- s00_axi_aresetn);
- output s_buff3_reg_0;
- output s_count_reg;
- output [0:0]E;
- output s_pulseLed_reg;
- output [4:0]Q;
- input rst_i;
- input s00_axi_aclk;
- input \s_debounce_reg[1]_0 ;
- input s_comparators_i_10;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]p_1_in;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff1_i_1__29_n_0;
- wire s_buff3;
- wire s_buff3_reg_0;
- wire s_comparators_i_10;
- wire s_count_reg;
- wire \s_debounce_reg[1]_0 ;
- wire s_pulseLed_reg;
-
- LUT1 #(
- .INIT(2'h1))
- s_buff1_i_1__29
- (.I0(s_comparators_i_10),
- .O(s_buff1_i_1__29_n_0));
- FDRE #(
- .INIT(1'b0))
- s_buff1_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff1_i_1__29_n_0),
- .Q(p_1_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff2_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_debounce_reg[1]_0 ),
- .Q(s_buff3_reg_0),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- s_buff3_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_buff3_reg_0),
- .Q(s_buff3),
- .R(rst_i));
- LUT1 #(
- .INIT(2'h1))
- s_count_reg_i_1__29
- (.I0(s_buff3_reg_0),
- .O(E));
- LUT3 #(
- .INIT(8'h2F))
- s_count_reg_i_1__77
- (.I0(s_buff3_reg_0),
- .I1(s_buff3),
- .I2(D),
- .O(s_count_reg));
- FDRE \s_debounce_reg[0]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(p_1_in),
- .Q(Q[0]),
- .R(1'b0));
- FDRE \s_debounce_reg[1]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[0]),
- .Q(Q[1]),
- .R(1'b0));
- FDRE \s_debounce_reg[2]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[1]),
- .Q(Q[2]),
- .R(1'b0));
- FDRE \s_debounce_reg[3]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[2]),
- .Q(Q[3]),
- .R(1'b0));
- FDRE \s_debounce_reg[4]
- (.C(s00_axi_aclk),
- .CE(s00_axi_aresetn),
- .D(Q[3]),
- .Q(Q[4]),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hB))
- s_pulseLed_i_6__37
- (.I0(s_buff3),
- .I1(s_buff3_reg_0),
- .O(s_pulseLed_reg));
-endmodule
-
-(* ORIG_REF_NAME = "fasec_hwtest" *) (* g_FMC1 = "EDA-03287" *) (* g_FMC2 = "EDA-03287" *)
-(* g_S00_AXI_ADDR_WIDTH = "32" *) (* g_S00_AXI_DATA_WIDTH = "32" *) (* g_USE_GEM_LEDS = "FALSE" *)
-module system_design_fasec_hwtest_0_0_fasec_hwtest
- (ps_clk_i,
- osc100_clk_i,
- FMC2_LA_P_b,
- FMC2_LA_N_b,
- FMC1_LA_P_b,
- FMC1_LA_N_b,
- FMC2_PRSNTM2C_n_i,
- FMC2_CLK0M2C_P_i,
- FMC2_CLK0M2C_N_i,
- FMC2_CLK0C2M_P_o,
- FMC2_CLK0C2M_N_o,
- FMC2_GP0_i,
- FMC2_GP1_i,
- FMC2_GP2_i,
- FMC2_GP3_b,
- FMC1_PRSNTM2C_n_i,
- FMC1_CLK0M2C_P_i,
- FMC1_CLK0M2C_N_i,
- FMC1_CLK0C2M_P_o,
- FMC1_CLK0C2M_N_o,
- FMC1_GP0_i,
- FMC1_GP1_i,
- FMC1_GP2_i,
- FMC1_GP3_b,
- pb_gp_n_i,
- led_col_pl_o,
- led_line_en_pl_o,
- led_line_pl_o,
- watchdog_pl_o,
- dig_in1_i,
- dig_in2_i,
- dig_in3_n_i,
- dig_in4_n_i,
- dig_outs_i,
- dig_out5_n,
- dig_out6_n,
- gem_status_vector_i,
- intr_o,
- intr_led_o,
- s00_axi_aclk,
- s00_axi_aresetn,
- s00_axi_awaddr,
- s00_axi_awprot,
- s00_axi_awvalid,
- s00_axi_awready,
- s00_axi_wdata,
- s00_axi_wstrb,
- s00_axi_wvalid,
- s00_axi_wready,
- s00_axi_bresp,
- s00_axi_bvalid,
- s00_axi_bready,
- s00_axi_araddr,
- s00_axi_arprot,
- s00_axi_arvalid,
- s00_axi_arready,
- s00_axi_rdata,
- s00_axi_rresp,
- s00_axi_rvalid,
- s00_axi_rready);
- input ps_clk_i;
- input osc100_clk_i;
- inout [33:0]FMC2_LA_P_b;
- inout [33:0]FMC2_LA_N_b;
- inout [33:0]FMC1_LA_P_b;
- inout [33:0]FMC1_LA_N_b;
- input FMC2_PRSNTM2C_n_i;
- input FMC2_CLK0M2C_P_i;
- input FMC2_CLK0M2C_N_i;
- output FMC2_CLK0C2M_P_o;
- output FMC2_CLK0C2M_N_o;
- input FMC2_GP0_i;
- input FMC2_GP1_i;
- input FMC2_GP2_i;
- inout FMC2_GP3_b;
- input FMC1_PRSNTM2C_n_i;
- input FMC1_CLK0M2C_P_i;
- input FMC1_CLK0M2C_N_i;
- output FMC1_CLK0C2M_P_o;
- output FMC1_CLK0C2M_N_o;
- input FMC1_GP0_i;
- input FMC1_GP1_i;
- input FMC1_GP2_i;
- inout FMC1_GP3_b;
- input pb_gp_n_i;
- output [3:0]led_col_pl_o;
- output led_line_en_pl_o;
- output led_line_pl_o;
- output watchdog_pl_o;
- input dig_in1_i;
- input dig_in2_i;
- input dig_in3_n_i;
- input dig_in4_n_i;
- output [3:0]dig_outs_i;
- output dig_out5_n;
- output dig_out6_n;
- input [15:0]gem_status_vector_i;
- output intr_o;
- output intr_led_o;
- input s00_axi_aclk;
- input s00_axi_aresetn;
- input [31:0]s00_axi_awaddr;
- input [2:0]s00_axi_awprot;
- input s00_axi_awvalid;
- output s00_axi_awready;
- input [31:0]s00_axi_wdata;
- input [3:0]s00_axi_wstrb;
- input s00_axi_wvalid;
- output s00_axi_wready;
- output [1:0]s00_axi_bresp;
- output s00_axi_bvalid;
- input s00_axi_bready;
- input [31:0]s00_axi_araddr;
- input [2:0]s00_axi_arprot;
- input s00_axi_arvalid;
- output s00_axi_arready;
- output [31:0]s00_axi_rdata;
- output [1:0]s00_axi_rresp;
- output s00_axi_rvalid;
- input s00_axi_rready;
-
- wire \<const0> ;
- wire \<const1> ;
- wire FMC1_GP0_i;
- wire FMC1_GP1_i;
- wire FMC1_GP2_i;
- wire FMC1_GP3_b;
- wire [33:0]FMC1_LA_N_b;
- wire [33:0]FMC1_LA_P_b;
- wire FMC2_GP0_i;
- wire FMC2_GP1_i;
- wire FMC2_GP2_i;
- wire FMC2_GP3_b;
- wire [33:0]FMC2_LA_N_b;
- wire [33:0]FMC2_LA_P_b;
- wire [5:2]axi_araddr;
- wire clear;
- wire cmp_axi4lite_slave_n_217;
- wire cmp_axi4lite_slave_n_218;
- wire cmp_axi4lite_slave_n_219;
- wire cmp_axi4lite_slave_n_220;
- wire cmp_axi4lite_slave_n_509;
- wire cmp_axi4lite_slave_n_516;
- wire cmp_axi4lite_slave_n_517;
- wire cmp_axi4lite_slave_n_518;
- wire cmp_axi4lite_slave_n_519;
- wire cmp_axi4lite_slave_n_520;
- wire cmp_axi4lite_slave_n_521;
- wire cmp_axi4lite_slave_n_522;
- wire cmp_axi4lite_slave_n_523;
- wire cmp_axi4lite_slave_n_524;
- wire cmp_axi4lite_slave_n_527;
- wire cmp_axi4lite_slave_n_528;
- wire cmp_axi4lite_slave_n_529;
- wire cmp_axi4lite_slave_n_530;
- wire cmp_axi4lite_slave_n_531;
- wire cmp_axi4lite_slave_n_532;
- wire cmp_axi4lite_slave_n_533;
- wire cmp_axi4lite_slave_n_534;
- wire cmp_general_fmc1_n_113;
- wire cmp_general_fmc1_n_126;
- wire cmp_general_fmc1_n_127;
- wire cmp_general_fmc1_n_128;
- wire cmp_general_fmc1_n_129;
- wire cmp_general_fmc1_n_130;
- wire cmp_general_fmc1_n_131;
- wire cmp_general_fmc1_n_132;
- wire cmp_general_fmc1_n_133;
- wire cmp_general_fmc1_n_134;
- wire cmp_general_fmc1_n_135;
- wire cmp_general_fmc1_n_136;
- wire cmp_general_fmc1_n_137;
- wire cmp_general_fmc1_n_138;
- wire cmp_general_fmc1_n_139;
- wire cmp_general_fmc1_n_140;
- wire cmp_general_fmc1_n_141;
- wire cmp_general_fmc1_n_142;
- wire cmp_general_fmc1_n_143;
- wire cmp_general_fmc1_n_144;
- wire cmp_general_fmc1_n_145;
- wire cmp_general_fmc1_n_146;
- wire cmp_general_fmc1_n_147;
- wire cmp_general_fmc1_n_148;
- wire cmp_general_fmc1_n_149;
- wire cmp_general_fmc1_n_150;
- wire cmp_general_fmc1_n_151;
- wire cmp_general_fmc1_n_152;
- wire cmp_general_fmc1_n_153;
- wire cmp_general_fmc1_n_154;
- wire cmp_general_fmc1_n_155;
- wire cmp_general_fmc1_n_156;
- wire cmp_general_fmc1_n_157;
- wire cmp_general_fmc1_n_158;
- wire cmp_general_fmc1_n_159;
- wire cmp_general_fmc1_n_160;
- wire cmp_general_fmc1_n_161;
- wire cmp_general_fmc1_n_162;
- wire cmp_general_fmc1_n_163;
- wire cmp_general_fmc1_n_164;
- wire cmp_general_fmc1_n_165;
- wire cmp_general_fmc1_n_166;
- wire cmp_general_fmc1_n_167;
- wire cmp_general_fmc1_n_168;
- wire cmp_general_fmc1_n_169;
- wire cmp_general_fmc1_n_170;
- wire cmp_general_fmc1_n_171;
- wire cmp_general_fmc1_n_172;
- wire cmp_general_fmc1_n_173;
- wire cmp_general_fmc1_n_174;
- wire cmp_general_fmc1_n_175;
- wire cmp_general_fmc1_n_176;
- wire cmp_general_fmc1_n_177;
- wire cmp_general_fmc1_n_178;
- wire cmp_general_fmc1_n_179;
- wire cmp_general_fmc1_n_180;
- wire cmp_general_fmc1_n_181;
- wire cmp_general_fmc1_n_182;
- wire cmp_general_fmc1_n_183;
- wire cmp_general_fmc1_n_184;
- wire cmp_general_fmc1_n_185;
- wire cmp_general_fmc1_n_186;
- wire cmp_general_fmc1_n_187;
- wire cmp_general_fmc1_n_188;
- wire cmp_general_fmc1_n_189;
- wire cmp_general_fmc1_n_190;
- wire cmp_general_fmc1_n_191;
- wire cmp_general_fmc1_n_192;
- wire cmp_general_fmc1_n_193;
- wire cmp_general_fmc1_n_194;
- wire cmp_general_fmc1_n_195;
- wire cmp_general_fmc1_n_196;
- wire cmp_general_fmc1_n_197;
- wire cmp_general_fmc1_n_198;
- wire cmp_general_fmc1_n_199;
- wire cmp_general_fmc1_n_200;
- wire cmp_general_fmc1_n_201;
- wire cmp_general_fmc1_n_202;
- wire cmp_general_fmc1_n_203;
- wire cmp_general_fmc1_n_204;
- wire cmp_general_fmc1_n_205;
- wire cmp_general_fmc1_n_206;
- wire cmp_general_fmc1_n_207;
- wire cmp_general_fmc1_n_208;
- wire cmp_general_fmc1_n_209;
- wire cmp_general_fmc1_n_210;
- wire cmp_general_fmc1_n_211;
- wire cmp_general_fmc1_n_212;
- wire cmp_general_fmc1_n_213;
- wire cmp_general_fmc1_n_214;
- wire cmp_general_fmc1_n_215;
- wire cmp_general_fmc1_n_216;
- wire cmp_general_fmc1_n_217;
- wire cmp_general_fmc1_n_218;
- wire cmp_general_fmc1_n_219;
- wire cmp_general_fmc1_n_220;
- wire cmp_general_fmc1_n_221;
- wire cmp_general_fmc1_n_222;
- wire cmp_general_fmc1_n_223;
- wire cmp_general_fmc1_n_224;
- wire cmp_general_fmc1_n_225;
- wire cmp_general_fmc1_n_226;
- wire cmp_general_fmc1_n_227;
- wire cmp_general_fmc1_n_228;
- wire cmp_general_fmc1_n_229;
- wire cmp_general_fmc1_n_230;
- wire cmp_general_fmc1_n_231;
- wire cmp_general_fmc1_n_232;
- wire cmp_general_fmc2_n_114;
- wire cmp_general_fmc2_n_127;
- wire cmp_general_fmc2_n_128;
- wire cmp_general_fmc2_n_129;
- wire cmp_general_fmc2_n_130;
- wire cmp_general_fmc2_n_131;
- wire cmp_general_fmc2_n_132;
- wire cmp_general_fmc2_n_133;
- wire cmp_general_fmc2_n_134;
- wire cmp_general_fmc2_n_135;
- wire cmp_general_fmc2_n_136;
- wire cmp_general_fmc2_n_137;
- wire cmp_general_fmc2_n_138;
- wire cmp_general_fmc2_n_139;
- wire cmp_general_fmc2_n_140;
- wire cmp_general_fmc2_n_141;
- wire cmp_general_fmc2_n_142;
- wire cmp_general_fmc2_n_143;
- wire cmp_general_fmc2_n_144;
- wire cmp_general_fmc2_n_145;
- wire cmp_general_fmc2_n_146;
- wire cmp_general_fmc2_n_147;
- wire cmp_general_fmc2_n_148;
- wire cmp_general_fmc2_n_149;
- wire cmp_general_fmc2_n_150;
- wire cmp_general_fmc2_n_151;
- wire cmp_general_fmc2_n_152;
- wire cmp_general_fmc2_n_153;
- wire cmp_general_fmc2_n_154;
- wire cmp_general_fmc2_n_155;
- wire cmp_general_fmc2_n_156;
- wire cmp_general_fmc2_n_157;
- wire cmp_general_fmc2_n_158;
- wire cmp_general_fmc2_n_159;
- wire cmp_general_fmc2_n_160;
- wire cmp_general_fmc2_n_161;
- wire cmp_general_fmc2_n_162;
- wire cmp_general_fmc2_n_163;
- wire cmp_general_fmc2_n_164;
- wire cmp_general_fmc2_n_165;
- wire cmp_general_fmc2_n_166;
- wire cmp_general_fmc2_n_167;
- wire cmp_general_fmc2_n_168;
- wire cmp_general_fmc2_n_169;
- wire cmp_general_fmc2_n_170;
- wire cmp_general_fmc2_n_171;
- wire cmp_general_fmc2_n_172;
- wire cmp_general_fmc2_n_173;
- wire cmp_general_fmc2_n_174;
- wire cmp_general_fmc2_n_175;
- wire cmp_general_fmc2_n_176;
- wire cmp_general_fmc2_n_177;
- wire cmp_general_fmc2_n_178;
- wire cmp_general_fmc2_n_179;
- wire cmp_general_fmc2_n_180;
- wire cmp_general_fmc2_n_181;
- wire cmp_general_fmc2_n_182;
- wire cmp_general_fmc2_n_183;
- wire cmp_general_fmc2_n_184;
- wire cmp_general_fmc2_n_185;
- wire [11:0]\data_rw_o[100] ;
- wire [11:0]\data_rw_o[101] ;
- wire [11:0]\data_rw_o[102] ;
- wire [11:0]\data_rw_o[103] ;
- wire [7:1]\data_rw_o[11] ;
- wire [11:0]\data_rw_o[16] ;
- wire [11:0]\data_rw_o[17] ;
- wire [11:0]\data_rw_o[18] ;
- wire [11:0]\data_rw_o[19] ;
- wire [11:0]\data_rw_o[20] ;
- wire [11:0]\data_rw_o[21] ;
- wire [11:0]\data_rw_o[22] ;
- wire [11:0]\data_rw_o[23] ;
- wire [11:0]\data_rw_o[24] ;
- wire [11:0]\data_rw_o[25] ;
- wire [11:0]\data_rw_o[26] ;
- wire [11:0]\data_rw_o[27] ;
- wire [11:0]\data_rw_o[28] ;
- wire [11:0]\data_rw_o[29] ;
- wire [11:0]\data_rw_o[30] ;
- wire [11:0]\data_rw_o[31] ;
- wire [11:0]\data_rw_o[32] ;
- wire [11:0]\data_rw_o[33] ;
- wire [11:0]\data_rw_o[34] ;
- wire [11:0]\data_rw_o[35] ;
- wire [7:1]\data_rw_o[79] ;
- wire [11:0]\data_rw_o[84] ;
- wire [11:0]\data_rw_o[85] ;
- wire [11:0]\data_rw_o[86] ;
- wire [11:0]\data_rw_o[87] ;
- wire [11:0]\data_rw_o[88] ;
- wire [11:0]\data_rw_o[89] ;
- wire [11:0]\data_rw_o[90] ;
- wire [11:0]\data_rw_o[91] ;
- wire [11:0]\data_rw_o[92] ;
- wire [11:0]\data_rw_o[93] ;
- wire [11:0]\data_rw_o[94] ;
- wire [11:0]\data_rw_o[95] ;
- wire [11:0]\data_rw_o[96] ;
- wire [11:0]\data_rw_o[97] ;
- wire [11:0]\data_rw_o[98] ;
- wire [11:0]\data_rw_o[99] ;
- wire dig_in1_i;
- wire dig_in2_i;
- wire dig_in3_n_i;
- wire dig_in4_n_i;
- wire dig_out6_n;
- wire [0:0]\^dig_outs_i ;
- wire fmc2_intr;
- wire fmc2_intr_led;
- wire [15:0]gem_status_vector_i;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[0].[0].s_reqs_reg[0][value]__0 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[0].[0].s_reqs_reg[0][value]__0_14 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[0].[1].s_reqs_reg[1][value]__0 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[0].[1].s_reqs_reg[1][value]__0_13 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[0].[2].s_reqs_reg[2][value]__0 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[0].[2].s_reqs_reg[2][value]__0_12 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0_15 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[1].[0].s_reqs_reg[4][value]__0 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[1].[0].s_reqs_reg[4][value]__0_10 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[1].[1].s_reqs_reg[5][value]__0 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[1].[1].s_reqs_reg[5][value]__0_9 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[1].[2].s_reqs_reg[6][value]__0 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[1].[2].s_reqs_reg[6][value]__0_8 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[1].[3].s_reqs_reg[7][value]__0 ;
- wire [11:0]\gen_spi.cmp_dac7716_spi/[1].[3].s_reqs_reg[7][value]__0_11 ;
- wire \gen_spi.cmp_dac7716_spi/p_12_out ;
- wire \gen_spi.cmp_dac7716_spi/p_12_out_0 ;
- wire \gen_spi.cmp_dac7716_spi/p_13_out ;
- wire \gen_spi.cmp_dac7716_spi/p_13_out_1 ;
- wire \gen_spi.cmp_dac7716_spi/p_14_out ;
- wire \gen_spi.cmp_dac7716_spi/p_14_out_2 ;
- wire \gen_spi.cmp_dac7716_spi/p_15_out ;
- wire \gen_spi.cmp_dac7716_spi/p_15_out_3 ;
- wire \gen_spi.cmp_dac7716_spi/p_16_out ;
- wire \gen_spi.cmp_dac7716_spi/p_16_out_7 ;
- wire \gen_spi.cmp_dac7716_spi/p_17_out ;
- wire \gen_spi.cmp_dac7716_spi/p_17_out_6 ;
- wire \gen_spi.cmp_dac7716_spi/p_18_out ;
- wire \gen_spi.cmp_dac7716_spi/p_18_out_5 ;
- wire \gen_spi.cmp_dac7716_spi/p_19_out ;
- wire \gen_spi.cmp_dac7716_spi/p_19_out_4 ;
- wire intr_led_o;
- wire intr_o;
- wire [3:0]led_col_pl_o;
- wire led_line_pl_o;
- wire [3:0]p_0_in;
- wire [3:2]p_0_out;
- wire p_2_in;
- wire pb_gp_n_i;
- wire ps_clk_i;
- wire rst_i;
- wire s00_axi_aclk;
- wire [31:0]s00_axi_araddr;
- wire s00_axi_aresetn;
- wire s00_axi_arready;
- wire s00_axi_arvalid;
- wire [31:0]s00_axi_awaddr;
- wire s00_axi_awready;
- wire s00_axi_awvalid;
- wire s00_axi_bready;
- wire [1:1]\^s00_axi_bresp ;
- wire s00_axi_bvalid;
- wire [31:0]s00_axi_rdata;
- wire s00_axi_rready;
- wire [1:1]\^s00_axi_rresp ;
- wire s00_axi_rvalid;
- wire [31:0]s00_axi_wdata;
- wire s00_axi_wready;
- wire [3:0]s00_axi_wstrb;
- wire s00_axi_wvalid;
- wire [19:0]\s_datao_fmc1[0] ;
- wire [3:0]\s_datao_fmc1[1] ;
- wire [31:0]\s_datao_fmc1[28] ;
- wire [19:8]\s_datao_fmc1[4] ;
- wire [19:0]\s_datao_fmc2[0] ;
- wire [3:0]\s_datao_fmc2[1] ;
- wire [31:0]\s_datao_fmc2[28] ;
- wire [19:8]\s_datao_fmc2[4] ;
- wire \s_ins_reg_n_0_[0] ;
- wire \s_ins_reg_n_0_[1] ;
- wire \s_ins_reg_n_0_[2] ;
- wire \s_ins_reg_n_0_[3] ;
- wire s_led_line_i_1_n_0;
- wire s_led_line_i_2_n_0;
- wire \s_leds[0]_i_1_n_0 ;
- wire \s_leds[1]_i_1_n_0 ;
- wire \s_leds[2]_i_1_n_0 ;
- wire \s_leds[3]_i_1_n_0 ;
- wire \s_leds[3]_i_2_n_0 ;
- wire \s_leds[3]_i_3_n_0 ;
- wire \s_leds[3]_i_4_n_0 ;
- wire \s_leds[3]_i_5_n_0 ;
- wire s_tick;
- wire s_tick_i_1_n_0;
- wire \v_cntr[0]_i_10_n_0 ;
- wire \v_cntr[0]_i_11_n_0 ;
- wire \v_cntr[0]_i_3_n_0 ;
- wire \v_cntr[0]_i_4_n_0 ;
- wire \v_cntr[0]_i_5_n_0 ;
- wire \v_cntr[0]_i_9_n_0 ;
- wire [31:9]v_cntr_reg;
- wire \v_cntr_reg[0]_i_2_n_0 ;
- wire \v_cntr_reg[0]_i_2_n_1 ;
- wire \v_cntr_reg[0]_i_2_n_2 ;
- wire \v_cntr_reg[0]_i_2_n_3 ;
- wire \v_cntr_reg[0]_i_2_n_4 ;
- wire \v_cntr_reg[0]_i_2_n_5 ;
- wire \v_cntr_reg[0]_i_2_n_6 ;
- wire \v_cntr_reg[0]_i_2_n_7 ;
- wire \v_cntr_reg[12]_i_1_n_0 ;
- wire \v_cntr_reg[12]_i_1_n_1 ;
- wire \v_cntr_reg[12]_i_1_n_2 ;
- wire \v_cntr_reg[12]_i_1_n_3 ;
- wire \v_cntr_reg[12]_i_1_n_4 ;
- wire \v_cntr_reg[12]_i_1_n_5 ;
- wire \v_cntr_reg[12]_i_1_n_6 ;
- wire \v_cntr_reg[12]_i_1_n_7 ;
- wire \v_cntr_reg[16]_i_1_n_0 ;
- wire \v_cntr_reg[16]_i_1_n_1 ;
- wire \v_cntr_reg[16]_i_1_n_2 ;
- wire \v_cntr_reg[16]_i_1_n_3 ;
- wire \v_cntr_reg[16]_i_1_n_4 ;
- wire \v_cntr_reg[16]_i_1_n_5 ;
- wire \v_cntr_reg[16]_i_1_n_6 ;
- wire \v_cntr_reg[16]_i_1_n_7 ;
- wire \v_cntr_reg[20]_i_1_n_0 ;
- wire \v_cntr_reg[20]_i_1_n_1 ;
- wire \v_cntr_reg[20]_i_1_n_2 ;
- wire \v_cntr_reg[20]_i_1_n_3 ;
- wire \v_cntr_reg[20]_i_1_n_4 ;
- wire \v_cntr_reg[20]_i_1_n_5 ;
- wire \v_cntr_reg[20]_i_1_n_6 ;
- wire \v_cntr_reg[20]_i_1_n_7 ;
- wire \v_cntr_reg[24]_i_1_n_0 ;
- wire \v_cntr_reg[24]_i_1_n_1 ;
- wire \v_cntr_reg[24]_i_1_n_2 ;
- wire \v_cntr_reg[24]_i_1_n_3 ;
- wire \v_cntr_reg[24]_i_1_n_4 ;
- wire \v_cntr_reg[24]_i_1_n_5 ;
- wire \v_cntr_reg[24]_i_1_n_6 ;
- wire \v_cntr_reg[24]_i_1_n_7 ;
- wire \v_cntr_reg[28]_i_1_n_1 ;
- wire \v_cntr_reg[28]_i_1_n_2 ;
- wire \v_cntr_reg[28]_i_1_n_3 ;
- wire \v_cntr_reg[28]_i_1_n_4 ;
- wire \v_cntr_reg[28]_i_1_n_5 ;
- wire \v_cntr_reg[28]_i_1_n_6 ;
- wire \v_cntr_reg[28]_i_1_n_7 ;
- wire \v_cntr_reg[4]_i_1_n_0 ;
- wire \v_cntr_reg[4]_i_1_n_1 ;
- wire \v_cntr_reg[4]_i_1_n_2 ;
- wire \v_cntr_reg[4]_i_1_n_3 ;
- wire \v_cntr_reg[4]_i_1_n_4 ;
- wire \v_cntr_reg[4]_i_1_n_5 ;
- wire \v_cntr_reg[4]_i_1_n_6 ;
- wire \v_cntr_reg[4]_i_1_n_7 ;
- wire \v_cntr_reg[8]_i_1_n_0 ;
- wire \v_cntr_reg[8]_i_1_n_1 ;
- wire \v_cntr_reg[8]_i_1_n_2 ;
- wire \v_cntr_reg[8]_i_1_n_3 ;
- wire \v_cntr_reg[8]_i_1_n_4 ;
- wire \v_cntr_reg[8]_i_1_n_5 ;
- wire \v_cntr_reg[8]_i_1_n_6 ;
- wire \v_cntr_reg[8]_i_1_n_7 ;
- wire \v_cntr_reg_n_0_[0] ;
- wire \v_cntr_reg_n_0_[1] ;
- wire \v_cntr_reg_n_0_[2] ;
- wire \v_cntr_reg_n_0_[3] ;
- wire \v_cntr_reg_n_0_[4] ;
- wire \v_cntr_reg_n_0_[5] ;
- wire \v_cntr_reg_n_0_[6] ;
- wire \v_cntr_reg_n_0_[7] ;
- wire \v_cntr_reg_n_0_[8] ;
- wire [3:0]v_ins;
- wire \v_pbreg_reg_n_0_[0] ;
- wire [7:0]v_shift;
- wire \v_shift[0]_i_1_n_0 ;
- wire \v_shift[1]_i_1_n_0 ;
- wire \v_shift[2]_i_1_n_0 ;
- wire \v_shift[3]_i_1_n_0 ;
- wire watchdog_pl_o;
- wire [3:3]\NLW_v_cntr_reg[28]_i_1_CO_UNCONNECTED ;
-
- assign FMC1_CLK0C2M_N_o = \<const0> ;
- assign FMC1_CLK0C2M_P_o = \<const0> ;
- assign FMC2_CLK0C2M_N_o = \<const0> ;
- assign FMC2_CLK0C2M_P_o = \<const0> ;
- assign dig_out5_n = dig_out6_n;
- assign dig_outs_i[3] = \^dig_outs_i [0];
- assign dig_outs_i[2] = \^dig_outs_i [0];
- assign dig_outs_i[1] = \^dig_outs_i [0];
- assign dig_outs_i[0] = \^dig_outs_i [0];
- assign led_line_en_pl_o = \<const1> ;
- assign s00_axi_bresp[1] = \^s00_axi_bresp [1];
- assign s00_axi_bresp[0] = \<const0> ;
- assign s00_axi_rresp[1] = \^s00_axi_rresp [1];
- assign s00_axi_rresp[0] = \<const0> ;
- GND GND
- (.G(\<const0> ));
- VCC VCC
- (.P(\<const1> ));
- system_design_fasec_hwtest_0_0_axi4lite_slave cmp_axi4lite_slave
- (.CO(\gen_spi.cmp_dac7716_spi/p_16_out_7 ),
- .Q(\data_rw_o[19] ),
- .\[0].[0].s_reqs_reg[0][changed] (\gen_spi.cmp_dac7716_spi/p_19_out_4 ),
- .\[0].[0].s_reqs_reg[0][changed]_0 (\gen_spi.cmp_dac7716_spi/p_19_out ),
- .\[0].[0].s_reqs_reg[0][value][11] (\data_rw_o[16] ),
- .\[0].[0].s_reqs_reg[0][value][11]_0 (\data_rw_o[84] ),
- .\[0].[0].s_reqs_reg[0][value][11]_1 (\gen_spi.cmp_dac7716_spi/[0].[0].s_reqs_reg[0][value]__0 ),
- .\[0].[0].s_reqs_reg[0][value][11]_2 (\gen_spi.cmp_dac7716_spi/[0].[0].s_reqs_reg[0][value]__0_14 ),
- .\[0].[1].s_reqs_reg[1][changed] (\gen_spi.cmp_dac7716_spi/p_18_out_5 ),
- .\[0].[1].s_reqs_reg[1][changed]_0 (\gen_spi.cmp_dac7716_spi/p_18_out ),
- .\[0].[1].s_reqs_reg[1][value][11] (\data_rw_o[17] ),
- .\[0].[1].s_reqs_reg[1][value][11]_0 (\data_rw_o[85] ),
- .\[0].[1].s_reqs_reg[1][value][11]_1 (\gen_spi.cmp_dac7716_spi/[0].[1].s_reqs_reg[1][value]__0 ),
- .\[0].[1].s_reqs_reg[1][value][11]_2 (\gen_spi.cmp_dac7716_spi/[0].[1].s_reqs_reg[1][value]__0_13 ),
- .\[0].[2].s_reqs_reg[2][changed] (\gen_spi.cmp_dac7716_spi/p_17_out_6 ),
- .\[0].[2].s_reqs_reg[2][changed]_0 (\gen_spi.cmp_dac7716_spi/p_17_out ),
- .\[0].[2].s_reqs_reg[2][value][11] (\data_rw_o[18] ),
- .\[0].[2].s_reqs_reg[2][value][11]_0 (\data_rw_o[86] ),
- .\[0].[2].s_reqs_reg[2][value][11]_1 (\gen_spi.cmp_dac7716_spi/[0].[2].s_reqs_reg[2][value]__0 ),
- .\[0].[2].s_reqs_reg[2][value][11]_2 (\gen_spi.cmp_dac7716_spi/[0].[2].s_reqs_reg[2][value]__0_12 ),
- .\[0].[3].s_reqs_reg[3][changed] (\gen_spi.cmp_dac7716_spi/p_16_out ),
- .\[0].[3].s_reqs_reg[3][value][11] (\data_rw_o[87] ),
- .\[0].[3].s_reqs_reg[3][value][11]_0 (\gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0 ),
- .\[0].[3].s_reqs_reg[3][value][11]_1 (\gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0_15 ),
- .\[1].[0].s_reqs_reg[4][changed] (\gen_spi.cmp_dac7716_spi/p_15_out_3 ),
- .\[1].[0].s_reqs_reg[4][changed]_0 (\gen_spi.cmp_dac7716_spi/p_15_out ),
- .\[1].[0].s_reqs_reg[4][value][11] (\data_rw_o[20] ),
- .\[1].[0].s_reqs_reg[4][value][11]_0 (\data_rw_o[88] ),
- .\[1].[0].s_reqs_reg[4][value][11]_1 (\gen_spi.cmp_dac7716_spi/[1].[0].s_reqs_reg[4][value]__0 ),
- .\[1].[0].s_reqs_reg[4][value][11]_2 (\gen_spi.cmp_dac7716_spi/[1].[0].s_reqs_reg[4][value]__0_10 ),
- .\[1].[1].s_reqs_reg[5][changed] (\gen_spi.cmp_dac7716_spi/p_14_out_2 ),
- .\[1].[1].s_reqs_reg[5][changed]_0 (\gen_spi.cmp_dac7716_spi/p_14_out ),
- .\[1].[1].s_reqs_reg[5][value][11] (\data_rw_o[21] ),
- .\[1].[1].s_reqs_reg[5][value][11]_0 (\data_rw_o[89] ),
- .\[1].[1].s_reqs_reg[5][value][11]_1 (\gen_spi.cmp_dac7716_spi/[1].[1].s_reqs_reg[5][value]__0 ),
- .\[1].[1].s_reqs_reg[5][value][11]_2 (\gen_spi.cmp_dac7716_spi/[1].[1].s_reqs_reg[5][value]__0_9 ),
- .\[1].[2].s_reqs_reg[6][changed] (\gen_spi.cmp_dac7716_spi/p_13_out_1 ),
- .\[1].[2].s_reqs_reg[6][changed]_0 (\gen_spi.cmp_dac7716_spi/p_13_out ),
- .\[1].[2].s_reqs_reg[6][value][11] (\data_rw_o[22] ),
- .\[1].[2].s_reqs_reg[6][value][11]_0 (\data_rw_o[90] ),
- .\[1].[2].s_reqs_reg[6][value][11]_1 (\gen_spi.cmp_dac7716_spi/[1].[2].s_reqs_reg[6][value]__0 ),
- .\[1].[2].s_reqs_reg[6][value][11]_2 (\gen_spi.cmp_dac7716_spi/[1].[2].s_reqs_reg[6][value]__0_8 ),
- .\[1].[3].s_reqs_reg[7][changed] (\gen_spi.cmp_dac7716_spi/p_12_out_0 ),
- .\[1].[3].s_reqs_reg[7][changed]_0 (\gen_spi.cmp_dac7716_spi/p_12_out ),
- .\[1].[3].s_reqs_reg[7][value][11] (\data_rw_o[23] ),
- .\[1].[3].s_reqs_reg[7][value][11]_0 (\data_rw_o[91] ),
- .\[1].[3].s_reqs_reg[7][value][11]_1 (\gen_spi.cmp_dac7716_spi/[1].[3].s_reqs_reg[7][value]__0 ),
- .\[1].[3].s_reqs_reg[7][value][11]_2 (\gen_spi.cmp_dac7716_spi/[1].[3].s_reqs_reg[7][value]__0_11 ),
- .\[2].[0].s_reqs_reg[8][value][11] (\data_rw_o[24] ),
- .\[2].[0].s_reqs_reg[8][value][11]_0 (\data_rw_o[92] ),
- .\[2].[1].s_reqs_reg[9][value][11] (\data_rw_o[25] ),
- .\[2].[1].s_reqs_reg[9][value][11]_0 (\data_rw_o[93] ),
- .\[2].[2].s_reqs_reg[10][value][11] (\data_rw_o[26] ),
- .\[2].[2].s_reqs_reg[10][value][11]_0 (\data_rw_o[94] ),
- .\[2].[3].s_reqs_reg[11][value][11] (\data_rw_o[27] ),
- .\[2].[3].s_reqs_reg[11][value][11]_0 (\data_rw_o[95] ),
- .\[3].[0].s_reqs_reg[12][value][11] (\data_rw_o[28] ),
- .\[3].[0].s_reqs_reg[12][value][11]_0 (\data_rw_o[96] ),
- .\[3].[1].s_reqs_reg[13][value][11] (\data_rw_o[29] ),
- .\[3].[1].s_reqs_reg[13][value][11]_0 (\data_rw_o[97] ),
- .\[3].[2].s_reqs_reg[14][value][11] (\data_rw_o[30] ),
- .\[3].[2].s_reqs_reg[14][value][11]_0 (\data_rw_o[98] ),
- .\[3].[3].s_reqs_reg[15][value][11] (\data_rw_o[31] ),
- .\[3].[3].s_reqs_reg[15][value][11]_0 (\data_rw_o[99] ),
- .\[4].[0].s_reqs_reg[16][value][11] (\data_rw_o[32] ),
- .\[4].[0].s_reqs_reg[16][value][11]_0 (\data_rw_o[100] ),
- .\[4].[1].s_reqs_reg[17][value][11] (\data_rw_o[33] ),
- .\[4].[1].s_reqs_reg[17][value][11]_0 (\data_rw_o[101] ),
- .\[4].[2].s_reqs_reg[18][value][11] (\data_rw_o[34] ),
- .\[4].[2].s_reqs_reg[18][value][11]_0 (\data_rw_o[102] ),
- .\[4].[3].s_reqs_reg[19][value][11] (\data_rw_o[35] ),
- .\[4].[3].s_reqs_reg[19][value][11]_0 (\data_rw_o[103] ),
- .\axi_araddr_reg[4]_0 (cmp_general_fmc1_n_211),
- .\axi_araddr_reg[4]_1 (cmp_general_fmc2_n_184),
- .\axi_araddr_reg[4]_2 (cmp_general_fmc2_n_185),
- .\axi_araddr_reg[4]_3 (cmp_general_fmc2_n_181),
- .\axi_araddr_reg[4]_4 (cmp_general_fmc2_n_182),
- .\axi_araddr_reg[4]_5 (cmp_general_fmc2_n_178),
- .\axi_araddr_reg[4]_6 (cmp_general_fmc2_n_179),
- .\axi_araddr_reg[4]_7 (cmp_general_fmc2_n_175),
- .\axi_araddr_reg[4]_8 (cmp_general_fmc2_n_176),
- .\axi_araddr_reg[4]_rep_0 (cmp_general_fmc1_n_175),
- .\axi_araddr_reg[4]_rep_1 (cmp_general_fmc1_n_179),
- .\axi_araddr_reg[4]_rep_2 (cmp_general_fmc1_n_183),
- .\axi_araddr_reg[4]_rep_3 (cmp_general_fmc1_n_187),
- .\axi_araddr_reg[4]_rep_4 (cmp_general_fmc1_n_191),
- .\axi_araddr_reg[4]_rep_5 (cmp_general_fmc1_n_195),
- .\axi_araddr_reg[4]_rep_6 (cmp_general_fmc1_n_199),
- .\axi_araddr_reg[4]_rep_7 (cmp_general_fmc1_n_203),
- .\axi_araddr_reg[4]_rep_8 (cmp_general_fmc1_n_207),
- .\axi_araddr_reg[4]_rep__0_0 (cmp_general_fmc1_n_133),
- .\axi_araddr_reg[4]_rep__0_1 (cmp_general_fmc1_n_138),
- .\axi_araddr_reg[4]_rep__0_2 (cmp_general_fmc1_n_143),
- .\axi_araddr_reg[4]_rep__0_3 (cmp_general_fmc1_n_148),
- .\axi_araddr_reg[4]_rep__0_4 (cmp_general_fmc1_n_153),
- .\axi_araddr_reg[4]_rep__0_5 (cmp_general_fmc1_n_158),
- .\axi_araddr_reg[4]_rep__0_6 (cmp_general_fmc1_n_163),
- .\axi_araddr_reg[4]_rep__0_7 (cmp_general_fmc1_n_167),
- .\axi_araddr_reg[4]_rep__0_8 (cmp_general_fmc1_n_171),
- .\axi_araddr_reg[4]_rep__1_0 (cmp_general_fmc1_n_128),
- .\axi_araddr_reg[5]_0 (cmp_general_fmc2_n_173),
- .\axi_araddr_reg[5]_1 (cmp_general_fmc2_n_171),
- .\axi_araddr_reg[5]_2 (cmp_general_fmc2_n_169),
- .\axi_araddr_reg[5]_3 (cmp_general_fmc2_n_167),
- .\axi_araddr_reg[5]_4 (cmp_general_fmc2_n_165),
- .\axi_araddr_reg[5]_5 (cmp_general_fmc2_n_163),
- .\axi_araddr_reg[5]_6 (cmp_general_fmc2_n_161),
- .\axi_araddr_reg[5]_7 (cmp_general_fmc2_n_159),
- .\axi_araddr_reg[5]_8 (cmp_general_fmc2_n_157),
- .\axi_araddr_reg[5]_rep_0 (cmp_general_fmc2_n_155),
- .\axi_araddr_reg[5]_rep_1 (cmp_general_fmc2_n_153),
- .\axi_araddr_reg[5]_rep_10 (cmp_general_fmc2_n_128),
- .\axi_araddr_reg[5]_rep_2 (cmp_general_fmc2_n_151),
- .\axi_araddr_reg[5]_rep_3 (cmp_general_fmc2_n_149),
- .\axi_araddr_reg[5]_rep_4 (cmp_general_fmc2_n_146),
- .\axi_araddr_reg[5]_rep_5 (cmp_general_fmc2_n_143),
- .\axi_araddr_reg[5]_rep_6 (cmp_general_fmc2_n_140),
- .\axi_araddr_reg[5]_rep_7 (cmp_general_fmc2_n_137),
- .\axi_araddr_reg[5]_rep_8 (cmp_general_fmc2_n_134),
- .\axi_araddr_reg[5]_rep_9 (cmp_general_fmc2_n_131),
- .\axi_rdata_reg[0]_0 (cmp_axi4lite_slave_n_218),
- .\axi_rdata_reg[10]_0 (cmp_axi4lite_slave_n_217),
- .\axi_rdata_reg[12]_0 (cmp_axi4lite_slave_n_518),
- .\axi_rdata_reg[12]_1 (cmp_axi4lite_slave_n_519),
- .\axi_rdata_reg[17]_0 (cmp_axi4lite_slave_n_521),
- .\axi_rdata_reg[17]_1 (cmp_axi4lite_slave_n_522),
- .\axi_rdata_reg[18]_0 (cmp_axi4lite_slave_n_520),
- .\axi_rdata_reg[22]_0 (cmp_axi4lite_slave_n_523),
- .\axi_rdata_reg[22]_1 (cmp_axi4lite_slave_n_524),
- .\axi_rdata_reg[23]_0 (axi_araddr),
- .\axi_rdata_reg[2]_0 (cmp_axi4lite_slave_n_219),
- .\axi_rdata_reg[2]_1 (cmp_axi4lite_slave_n_220),
- .\axi_rdata_reg[7]_0 (cmp_axi4lite_slave_n_516),
- .\axi_rdata_reg[7]_1 (cmp_axi4lite_slave_n_517),
- .\axi_rdata_reg[9]_0 (cmp_axi4lite_slave_n_509),
- .\dac_ch_o_reg[0][31] (\s_datao_fmc2[28] ),
- .\dac_ch_o_reg[0][31]_0 (\s_datao_fmc1[28] ),
- .\data_o_reg[1][3] (\s_datao_fmc1[1] ),
- .\data_o_reg[1][3]_0 (\s_datao_fmc2[1] ),
- .\data_o_reg[6][0] (cmp_general_fmc1_n_113),
- .\data_o_reg[6][0]_0 (cmp_general_fmc2_n_114),
- .\data_o_reg[6][1] (cmp_general_fmc1_n_130),
- .\data_o_reg[6][1]_0 (cmp_general_fmc2_n_129),
- .\data_o_reg[6][2] (cmp_general_fmc1_n_135),
- .\data_o_reg[6][2]_0 (cmp_general_fmc2_n_132),
- .\data_o_reg[6][3] (cmp_general_fmc1_n_140),
- .\data_o_reg[6][3]_0 (cmp_general_fmc2_n_135),
- .\data_o_reg[6][4] (cmp_general_fmc1_n_145),
- .\data_o_reg[6][4]_0 (cmp_general_fmc2_n_138),
- .\data_o_reg[6][5] (cmp_general_fmc1_n_150),
- .\data_o_reg[6][5]_0 (cmp_general_fmc2_n_141),
- .\data_o_reg[6][6] (cmp_general_fmc1_n_155),
- .\data_o_reg[6][6]_0 (cmp_general_fmc2_n_144),
- .\data_o_reg[6][7] (cmp_general_fmc1_n_160),
- .\data_o_reg[6][7]_0 (cmp_general_fmc2_n_147),
- .dig_out6_n(dig_out6_n),
- .dig_outs_i(\^dig_outs_i ),
- .\fmc_03287_channels[11].gen_chs.data_o_reg[59][20] (cmp_general_fmc1_n_215),
- .\fmc_03287_channels[11].gen_chs.data_o_reg[59][21] (cmp_general_fmc1_n_220),
- .\fmc_03287_channels[11].gen_chs.data_o_reg[59][22] (cmp_general_fmc1_n_225),
- .\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] (cmp_general_fmc1_n_230),
- .\fmc_03287_channels[15].gen_chs.data_o_reg[63][20] (cmp_general_fmc1_n_216),
- .\fmc_03287_channels[15].gen_chs.data_o_reg[63][21] (cmp_general_fmc1_n_221),
- .\fmc_03287_channels[15].gen_chs.data_o_reg[63][22] (cmp_general_fmc1_n_226),
- .\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] (cmp_general_fmc1_n_231),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][0] (cmp_general_fmc1_n_129),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][10] (cmp_general_fmc1_n_176),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][11] (cmp_general_fmc1_n_180),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][12] (cmp_general_fmc1_n_184),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][13] (cmp_general_fmc1_n_188),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][14] (cmp_general_fmc1_n_192),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][15] (cmp_general_fmc1_n_196),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][16] (cmp_general_fmc1_n_200),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][17] (cmp_general_fmc1_n_204),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][18] (cmp_general_fmc1_n_208),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][19] (cmp_general_fmc1_n_212),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][1] (cmp_general_fmc1_n_134),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][20] (cmp_general_fmc1_n_217),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][21] (cmp_general_fmc1_n_222),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][22] (cmp_general_fmc1_n_227),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] (cmp_general_fmc1_n_232),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][2] (cmp_general_fmc1_n_139),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][3] (cmp_general_fmc1_n_144),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][4] (cmp_general_fmc1_n_149),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][5] (cmp_general_fmc1_n_154),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][6] (cmp_general_fmc1_n_159),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][7] (cmp_general_fmc1_n_164),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][8] (cmp_general_fmc1_n_168),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][9] (cmp_general_fmc1_n_172),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][0] (cmp_general_fmc1_n_126),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][0]_0 (cmp_general_fmc2_n_127),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][10] (cmp_general_fmc1_n_173),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][10]_0 (cmp_general_fmc2_n_154),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][11] (cmp_general_fmc1_n_177),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][11]_0 (cmp_general_fmc2_n_156),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][12] (cmp_general_fmc1_n_181),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][12]_0 (cmp_general_fmc2_n_158),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][13] (cmp_general_fmc1_n_185),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][13]_0 (cmp_general_fmc2_n_160),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][14] (cmp_general_fmc1_n_189),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][14]_0 (cmp_general_fmc2_n_162),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][15] (cmp_general_fmc1_n_193),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][15]_0 (cmp_general_fmc2_n_164),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][16] (cmp_general_fmc1_n_197),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][16]_0 (cmp_general_fmc2_n_166),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][17] (cmp_general_fmc1_n_201),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][17]_0 (cmp_general_fmc2_n_168),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][18] (cmp_general_fmc1_n_205),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][18]_0 (cmp_general_fmc2_n_170),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][19] (cmp_general_fmc1_n_209),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][19]_0 (cmp_general_fmc2_n_172),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][1] (cmp_general_fmc1_n_131),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][1]_0 (cmp_general_fmc2_n_130),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][20] (cmp_general_fmc1_n_213),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][20]_0 (cmp_general_fmc2_n_174),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][21] (cmp_general_fmc1_n_218),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][21]_0 (cmp_general_fmc2_n_177),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][22] (cmp_general_fmc1_n_223),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][22]_0 (cmp_general_fmc2_n_180),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] (cmp_general_fmc1_n_228),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][23]_0 (cmp_general_fmc2_n_183),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][2] (cmp_general_fmc1_n_136),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][2]_0 (cmp_general_fmc2_n_133),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][3] (cmp_general_fmc1_n_141),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][3]_0 (cmp_general_fmc2_n_136),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][4] (cmp_general_fmc1_n_146),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][4]_0 (cmp_general_fmc2_n_139),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][5] (cmp_general_fmc1_n_151),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][5]_0 (cmp_general_fmc2_n_142),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][6] (cmp_general_fmc1_n_156),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][6]_0 (cmp_general_fmc2_n_145),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][7] (cmp_general_fmc1_n_161),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][7]_0 (cmp_general_fmc2_n_148),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][8] (cmp_general_fmc1_n_165),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][8]_0 (cmp_general_fmc2_n_150),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][9] (cmp_general_fmc1_n_169),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][9]_0 (cmp_general_fmc2_n_152),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][0] (cmp_general_fmc1_n_127),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][10] (cmp_general_fmc1_n_174),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][11] (cmp_general_fmc1_n_178),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][12] (cmp_general_fmc1_n_182),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][13] (cmp_general_fmc1_n_186),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][14] (cmp_general_fmc1_n_190),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][15] (cmp_general_fmc1_n_194),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][16] (cmp_general_fmc1_n_198),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][17] (cmp_general_fmc1_n_202),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][18] (cmp_general_fmc1_n_206),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][19] (cmp_general_fmc1_n_210),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][1] (cmp_general_fmc1_n_132),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][20] (cmp_general_fmc1_n_214),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][21] (cmp_general_fmc1_n_219),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][22] (cmp_general_fmc1_n_224),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] (cmp_general_fmc1_n_229),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][2] (cmp_general_fmc1_n_137),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][3] (cmp_general_fmc1_n_142),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][4] (cmp_general_fmc1_n_147),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][5] (cmp_general_fmc1_n_152),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][6] (cmp_general_fmc1_n_157),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][7] (cmp_general_fmc1_n_162),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][8] (cmp_general_fmc1_n_166),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][9] (cmp_general_fmc1_n_170),
- .gem_status_vector_i(gem_status_vector_i),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_araddr(s00_axi_araddr[10:2]),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s00_axi_arready(s00_axi_arready),
- .s00_axi_arvalid(s00_axi_arvalid),
- .s00_axi_awaddr(s00_axi_awaddr[9:2]),
- .s00_axi_awready(s00_axi_awready),
- .s00_axi_awvalid(s00_axi_awvalid),
- .s00_axi_bready(s00_axi_bready),
- .s00_axi_bresp(\^s00_axi_bresp ),
- .s00_axi_bvalid(s00_axi_bvalid),
- .s00_axi_rdata(s00_axi_rdata),
- .s00_axi_rready(s00_axi_rready),
- .s00_axi_rresp(\^s00_axi_rresp ),
- .s00_axi_rvalid(s00_axi_rvalid),
- .s00_axi_wdata(s00_axi_wdata),
- .s00_axi_wready(s00_axi_wready),
- .s00_axi_wstrb(s00_axi_wstrb),
- .s00_axi_wvalid(s00_axi_wvalid),
- .\s_datao_fmc1[0] (\s_datao_fmc1[0] ),
- .\s_datao_fmc1[4] (\s_datao_fmc1[4] ),
- .\s_datao_fmc2[0] (\s_datao_fmc2[0] ),
- .\s_datao_fmc2[4] (\s_datao_fmc2[4] ),
- .\s_ins_reg[3] ({\s_ins_reg_n_0_[3] ,\s_ins_reg_n_0_[2] ,\s_ins_reg_n_0_[1] ,\s_ins_reg_n_0_[0] }),
- .s_tick(s_tick),
- .\v_dout_reg[4] (cmp_axi4lite_slave_n_530),
- .\v_dout_reg[4]_0 (cmp_axi4lite_slave_n_534),
- .\v_dout_reg[5] (cmp_axi4lite_slave_n_529),
- .\v_dout_reg[5]_0 (cmp_axi4lite_slave_n_533),
- .\v_dout_reg[6] (cmp_axi4lite_slave_n_528),
- .\v_dout_reg[6]_0 (cmp_axi4lite_slave_n_532),
- .\v_dout_reg[7] ({\data_rw_o[11] [7],\data_rw_o[11] [2:1]}),
- .\v_dout_reg[7]_0 ({\data_rw_o[79] [7],\data_rw_o[79] [2:1]}),
- .\v_dout_reg[7]_1 (cmp_axi4lite_slave_n_527),
- .\v_dout_reg[7]_2 (cmp_axi4lite_slave_n_531));
- system_design_fasec_hwtest_0_0_general_fmc cmp_general_fmc1
- (.CO(\gen_spi.cmp_dac7716_spi/p_16_out_7 ),
- .D({FMC1_GP3_b,FMC1_GP2_i,FMC1_GP1_i,FMC1_GP0_i}),
- .FMC1_LA_N_b(FMC1_LA_N_b[29:28]),
- .\FMC1_LA_N_b[27] (FMC1_LA_N_b[27:20]),
- .\FMC1_LA_N_b[32] ({FMC1_LA_N_b[32:31],FMC1_LA_N_b[19:0]}),
- .FMC1_LA_P_b(FMC1_LA_P_b[29:28]),
- .\FMC1_LA_P_b[27] (FMC1_LA_P_b[27:20]),
- .\FMC1_LA_P_b[32] ({FMC1_LA_P_b[32:31],FMC1_LA_P_b[19:0]}),
- .Q(\gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0 ),
- .\axi_araddr_reg[2]_rep (cmp_axi4lite_slave_n_524),
- .\axi_araddr_reg[2]_rep__0 (cmp_axi4lite_slave_n_522),
- .\axi_araddr_reg[2]_rep__1 (cmp_axi4lite_slave_n_518),
- .\axi_araddr_reg[2]_rep__2 (cmp_axi4lite_slave_n_517),
- .\axi_araddr_reg[2]_rep__3 (cmp_axi4lite_slave_n_220),
- .\axi_araddr_reg[3]_rep (cmp_axi4lite_slave_n_523),
- .\axi_araddr_reg[3]_rep__0 (cmp_axi4lite_slave_n_521),
- .\axi_araddr_reg[3]_rep__1 (cmp_axi4lite_slave_n_519),
- .\axi_araddr_reg[3]_rep__2 (cmp_axi4lite_slave_n_516),
- .\axi_araddr_reg[3]_rep__3 (cmp_axi4lite_slave_n_219),
- .\axi_araddr_reg[4] (axi_araddr[4:2]),
- .\axi_araddr_reg[4]_rep (cmp_axi4lite_slave_n_520),
- .\axi_araddr_reg[4]_rep__0 (cmp_axi4lite_slave_n_509),
- .\axi_araddr_reg[4]_rep__1 (cmp_axi4lite_slave_n_218),
- .\axi_rdata_reg[0] (cmp_general_fmc1_n_113),
- .\axi_rdata_reg[0]_0 (cmp_general_fmc1_n_126),
- .\axi_rdata_reg[0]_1 (cmp_general_fmc1_n_127),
- .\axi_rdata_reg[0]_2 (cmp_general_fmc1_n_128),
- .\axi_rdata_reg[0]_3 (cmp_general_fmc1_n_129),
- .\axi_rdata_reg[10] (cmp_general_fmc1_n_173),
- .\axi_rdata_reg[10]_0 (cmp_general_fmc1_n_174),
- .\axi_rdata_reg[10]_1 (cmp_general_fmc1_n_175),
- .\axi_rdata_reg[10]_2 (cmp_general_fmc1_n_176),
- .\axi_rdata_reg[11] (cmp_general_fmc1_n_177),
- .\axi_rdata_reg[11]_0 (cmp_general_fmc1_n_178),
- .\axi_rdata_reg[11]_1 (cmp_general_fmc1_n_179),
- .\axi_rdata_reg[11]_2 (cmp_general_fmc1_n_180),
- .\axi_rdata_reg[12] (cmp_general_fmc1_n_181),
- .\axi_rdata_reg[12]_0 (cmp_general_fmc1_n_182),
- .\axi_rdata_reg[12]_1 (cmp_general_fmc1_n_183),
- .\axi_rdata_reg[12]_2 (cmp_general_fmc1_n_184),
- .\axi_rdata_reg[13] (cmp_general_fmc1_n_185),
- .\axi_rdata_reg[13]_0 (cmp_general_fmc1_n_186),
- .\axi_rdata_reg[13]_1 (cmp_general_fmc1_n_187),
- .\axi_rdata_reg[13]_2 (cmp_general_fmc1_n_188),
- .\axi_rdata_reg[14] (cmp_general_fmc1_n_189),
- .\axi_rdata_reg[14]_0 (cmp_general_fmc1_n_190),
- .\axi_rdata_reg[14]_1 (cmp_general_fmc1_n_191),
- .\axi_rdata_reg[14]_2 (cmp_general_fmc1_n_192),
- .\axi_rdata_reg[15] (cmp_general_fmc1_n_193),
- .\axi_rdata_reg[15]_0 (cmp_general_fmc1_n_194),
- .\axi_rdata_reg[15]_1 (cmp_general_fmc1_n_195),
- .\axi_rdata_reg[15]_2 (cmp_general_fmc1_n_196),
- .\axi_rdata_reg[16] (cmp_general_fmc1_n_197),
- .\axi_rdata_reg[16]_0 (cmp_general_fmc1_n_198),
- .\axi_rdata_reg[16]_1 (cmp_general_fmc1_n_199),
- .\axi_rdata_reg[16]_2 (cmp_general_fmc1_n_200),
- .\axi_rdata_reg[17] (cmp_general_fmc1_n_201),
- .\axi_rdata_reg[17]_0 (cmp_general_fmc1_n_202),
- .\axi_rdata_reg[17]_1 (cmp_general_fmc1_n_203),
- .\axi_rdata_reg[17]_2 (cmp_general_fmc1_n_204),
- .\axi_rdata_reg[18] (cmp_general_fmc1_n_205),
- .\axi_rdata_reg[18]_0 (cmp_general_fmc1_n_206),
- .\axi_rdata_reg[18]_1 (cmp_general_fmc1_n_207),
- .\axi_rdata_reg[18]_2 (cmp_general_fmc1_n_208),
- .\axi_rdata_reg[19] (cmp_general_fmc1_n_209),
- .\axi_rdata_reg[19]_0 (cmp_general_fmc1_n_210),
- .\axi_rdata_reg[19]_1 (cmp_general_fmc1_n_211),
- .\axi_rdata_reg[19]_2 (cmp_general_fmc1_n_212),
- .\axi_rdata_reg[1] (cmp_general_fmc1_n_130),
- .\axi_rdata_reg[1]_0 (cmp_general_fmc1_n_131),
- .\axi_rdata_reg[1]_1 (cmp_general_fmc1_n_132),
- .\axi_rdata_reg[1]_2 (cmp_general_fmc1_n_133),
- .\axi_rdata_reg[1]_3 (cmp_general_fmc1_n_134),
- .\axi_rdata_reg[20] (cmp_general_fmc1_n_213),
- .\axi_rdata_reg[20]_0 (cmp_general_fmc1_n_214),
- .\axi_rdata_reg[20]_1 (cmp_general_fmc1_n_215),
- .\axi_rdata_reg[20]_2 (cmp_general_fmc1_n_216),
- .\axi_rdata_reg[20]_3 (cmp_general_fmc1_n_217),
- .\axi_rdata_reg[21] (cmp_general_fmc1_n_218),
- .\axi_rdata_reg[21]_0 (cmp_general_fmc1_n_219),
- .\axi_rdata_reg[21]_1 (cmp_general_fmc1_n_220),
- .\axi_rdata_reg[21]_2 (cmp_general_fmc1_n_221),
- .\axi_rdata_reg[21]_3 (cmp_general_fmc1_n_222),
- .\axi_rdata_reg[22] (cmp_general_fmc1_n_223),
- .\axi_rdata_reg[22]_0 (cmp_general_fmc1_n_224),
- .\axi_rdata_reg[22]_1 (cmp_general_fmc1_n_225),
- .\axi_rdata_reg[22]_2 (cmp_general_fmc1_n_226),
- .\axi_rdata_reg[22]_3 (cmp_general_fmc1_n_227),
- .\axi_rdata_reg[23] (cmp_general_fmc1_n_228),
- .\axi_rdata_reg[23]_0 (cmp_general_fmc1_n_229),
- .\axi_rdata_reg[23]_1 (cmp_general_fmc1_n_230),
- .\axi_rdata_reg[23]_2 (cmp_general_fmc1_n_231),
- .\axi_rdata_reg[23]_3 (cmp_general_fmc1_n_232),
- .\axi_rdata_reg[2] (cmp_general_fmc1_n_135),
- .\axi_rdata_reg[2]_0 (cmp_general_fmc1_n_136),
- .\axi_rdata_reg[2]_1 (cmp_general_fmc1_n_137),
- .\axi_rdata_reg[2]_2 (cmp_general_fmc1_n_138),
- .\axi_rdata_reg[2]_3 (cmp_general_fmc1_n_139),
- .\axi_rdata_reg[31] (\s_datao_fmc1[28] ),
- .\axi_rdata_reg[3] (cmp_general_fmc1_n_140),
- .\axi_rdata_reg[3]_0 (cmp_general_fmc1_n_141),
- .\axi_rdata_reg[3]_1 (cmp_general_fmc1_n_142),
- .\axi_rdata_reg[3]_2 (cmp_general_fmc1_n_143),
- .\axi_rdata_reg[3]_3 (cmp_general_fmc1_n_144),
- .\axi_rdata_reg[3]_4 (\s_datao_fmc1[1] ),
- .\axi_rdata_reg[4] (cmp_general_fmc1_n_145),
- .\axi_rdata_reg[4]_0 (cmp_general_fmc1_n_146),
- .\axi_rdata_reg[4]_1 (cmp_general_fmc1_n_147),
- .\axi_rdata_reg[4]_2 (cmp_general_fmc1_n_148),
- .\axi_rdata_reg[4]_3 (cmp_general_fmc1_n_149),
- .\axi_rdata_reg[5] (cmp_general_fmc1_n_150),
- .\axi_rdata_reg[5]_0 (cmp_general_fmc1_n_151),
- .\axi_rdata_reg[5]_1 (cmp_general_fmc1_n_152),
- .\axi_rdata_reg[5]_2 (cmp_general_fmc1_n_153),
- .\axi_rdata_reg[5]_3 (cmp_general_fmc1_n_154),
- .\axi_rdata_reg[6] (cmp_general_fmc1_n_155),
- .\axi_rdata_reg[6]_0 (cmp_general_fmc1_n_156),
- .\axi_rdata_reg[6]_1 (cmp_general_fmc1_n_157),
- .\axi_rdata_reg[6]_2 (cmp_general_fmc1_n_158),
- .\axi_rdata_reg[6]_3 (cmp_general_fmc1_n_159),
- .\axi_rdata_reg[7] (cmp_general_fmc1_n_160),
- .\axi_rdata_reg[7]_0 (cmp_general_fmc1_n_161),
- .\axi_rdata_reg[7]_1 (cmp_general_fmc1_n_162),
- .\axi_rdata_reg[7]_2 (cmp_general_fmc1_n_163),
- .\axi_rdata_reg[7]_3 (cmp_general_fmc1_n_164),
- .\axi_rdata_reg[8] (cmp_general_fmc1_n_165),
- .\axi_rdata_reg[8]_0 (cmp_general_fmc1_n_166),
- .\axi_rdata_reg[8]_1 (cmp_general_fmc1_n_167),
- .\axi_rdata_reg[8]_2 (cmp_general_fmc1_n_168),
- .\axi_rdata_reg[9] (cmp_general_fmc1_n_169),
- .\axi_rdata_reg[9]_0 (cmp_general_fmc1_n_170),
- .\axi_rdata_reg[9]_1 (cmp_general_fmc1_n_171),
- .\axi_rdata_reg[9]_2 (cmp_general_fmc1_n_172),
- .\data_rw_o_reg[10][4] (cmp_axi4lite_slave_n_530),
- .\data_rw_o_reg[10][5] (cmp_axi4lite_slave_n_529),
- .\data_rw_o_reg[10][6] (cmp_axi4lite_slave_n_528),
- .\data_rw_o_reg[10][7] (cmp_axi4lite_slave_n_527),
- .\data_rw_o_reg[11][7] ({\data_rw_o[11] [7],\data_rw_o[11] [2:1]}),
- .\data_rw_o_reg[16][11] (\data_rw_o[16] ),
- .\data_rw_o_reg[16][11]_0 (\gen_spi.cmp_dac7716_spi/p_19_out_4 ),
- .\data_rw_o_reg[17][11] (\data_rw_o[17] ),
- .\data_rw_o_reg[17][11]_0 (\gen_spi.cmp_dac7716_spi/p_18_out_5 ),
- .\data_rw_o_reg[18][11] (\data_rw_o[18] ),
- .\data_rw_o_reg[18][11]_0 (\gen_spi.cmp_dac7716_spi/p_17_out_6 ),
- .\data_rw_o_reg[19][11] (\data_rw_o[19] ),
- .\data_rw_o_reg[20][11] (\data_rw_o[20] ),
- .\data_rw_o_reg[20][11]_0 (\gen_spi.cmp_dac7716_spi/p_15_out_3 ),
- .\data_rw_o_reg[21][11] (\data_rw_o[21] ),
- .\data_rw_o_reg[21][11]_0 (\gen_spi.cmp_dac7716_spi/p_14_out_2 ),
- .\data_rw_o_reg[22][11] (\data_rw_o[22] ),
- .\data_rw_o_reg[22][11]_0 (\gen_spi.cmp_dac7716_spi/p_13_out_1 ),
- .\data_rw_o_reg[23][11] (\data_rw_o[23] ),
- .\data_rw_o_reg[23][11]_0 (\gen_spi.cmp_dac7716_spi/p_12_out_0 ),
- .\data_rw_o_reg[24][11] (\data_rw_o[24] ),
- .\data_rw_o_reg[25][11] (\data_rw_o[25] ),
- .\data_rw_o_reg[26][11] (\data_rw_o[26] ),
- .\data_rw_o_reg[27][11] (\data_rw_o[27] ),
- .\data_rw_o_reg[28][11] (\data_rw_o[28] ),
- .\data_rw_o_reg[29][11] (\data_rw_o[29] ),
- .\data_rw_o_reg[30][11] (\data_rw_o[30] ),
- .\data_rw_o_reg[31][11] (\data_rw_o[31] ),
- .\data_rw_o_reg[32][11] (\data_rw_o[32] ),
- .\data_rw_o_reg[33][11] (\data_rw_o[33] ),
- .\data_rw_o_reg[34][11] (\data_rw_o[34] ),
- .\data_rw_o_reg[35][11] (\data_rw_o[35] ),
- .fmc2_intr(fmc2_intr),
- .fmc2_intr_led(fmc2_intr_led),
- .intr_led_o(intr_led_o),
- .intr_o(intr_o),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_count_reg(\s_datao_fmc1[4] ),
- .\s_datao_fmc1[0] (\s_datao_fmc1[0] ),
- .\s_tx_data_reg[111] (\gen_spi.cmp_dac7716_spi/[0].[0].s_reqs_reg[0][value]__0 ),
- .\s_tx_data_reg[15] (\gen_spi.cmp_dac7716_spi/[0].[1].s_reqs_reg[1][value]__0 ),
- .\s_tx_data_reg[15]_0 (\gen_spi.cmp_dac7716_spi/[0].[2].s_reqs_reg[2][value]__0 ),
- .\s_tx_data_reg[39] (\gen_spi.cmp_dac7716_spi/[1].[3].s_reqs_reg[7][value]__0 ),
- .\s_tx_data_reg[39]_0 (\gen_spi.cmp_dac7716_spi/[1].[0].s_reqs_reg[4][value]__0 ),
- .\s_tx_data_reg[39]_1 (\gen_spi.cmp_dac7716_spi/[1].[1].s_reqs_reg[5][value]__0 ),
- .\s_tx_data_reg[39]_2 (\gen_spi.cmp_dac7716_spi/[1].[2].s_reqs_reg[6][value]__0 ));
- system_design_fasec_hwtest_0_0_general_fmc_0 cmp_general_fmc2
- (.D({FMC2_GP3_b,FMC2_GP2_i,FMC2_GP1_i,FMC2_GP0_i}),
- .FMC2_LA_N_b(FMC2_LA_N_b[29:28]),
- .\FMC2_LA_N_b[27] (FMC2_LA_N_b[27:20]),
- .\FMC2_LA_N_b[32] ({FMC2_LA_N_b[32:31],FMC2_LA_N_b[19:0]}),
- .FMC2_LA_P_b(FMC2_LA_P_b[29:28]),
- .\FMC2_LA_P_b[27] (FMC2_LA_P_b[27:20]),
- .\FMC2_LA_P_b[32] ({FMC2_LA_P_b[32:31],FMC2_LA_P_b[19:0]}),
- .Q(\gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0_15 ),
- .\axi_araddr_reg[2]_rep (cmp_axi4lite_slave_n_524),
- .\axi_araddr_reg[2]_rep__0 (cmp_axi4lite_slave_n_522),
- .\axi_araddr_reg[2]_rep__1 (cmp_axi4lite_slave_n_518),
- .\axi_araddr_reg[2]_rep__2 (cmp_axi4lite_slave_n_517),
- .\axi_araddr_reg[2]_rep__3 (cmp_axi4lite_slave_n_220),
- .\axi_araddr_reg[3]_rep (cmp_axi4lite_slave_n_523),
- .\axi_araddr_reg[3]_rep__0 (cmp_axi4lite_slave_n_521),
- .\axi_araddr_reg[3]_rep__1 (cmp_axi4lite_slave_n_519),
- .\axi_araddr_reg[3]_rep__2 (cmp_axi4lite_slave_n_516),
- .\axi_araddr_reg[3]_rep__3 (cmp_axi4lite_slave_n_219),
- .\axi_araddr_reg[4]_rep (cmp_axi4lite_slave_n_520),
- .\axi_araddr_reg[4]_rep__0 (cmp_axi4lite_slave_n_509),
- .\axi_araddr_reg[4]_rep__1 (cmp_axi4lite_slave_n_218),
- .\axi_araddr_reg[5] (axi_araddr),
- .\axi_araddr_reg[5]_rep (cmp_axi4lite_slave_n_217),
- .\axi_rdata_reg[0] (cmp_general_fmc2_n_114),
- .\axi_rdata_reg[0]_0 (cmp_general_fmc2_n_127),
- .\axi_rdata_reg[0]_1 (cmp_general_fmc2_n_128),
- .\axi_rdata_reg[10] (cmp_general_fmc2_n_154),
- .\axi_rdata_reg[10]_0 (cmp_general_fmc2_n_155),
- .\axi_rdata_reg[11] (cmp_general_fmc2_n_156),
- .\axi_rdata_reg[11]_0 (cmp_general_fmc2_n_157),
- .\axi_rdata_reg[12] (cmp_general_fmc2_n_158),
- .\axi_rdata_reg[12]_0 (cmp_general_fmc2_n_159),
- .\axi_rdata_reg[13] (cmp_general_fmc2_n_160),
- .\axi_rdata_reg[13]_0 (cmp_general_fmc2_n_161),
- .\axi_rdata_reg[14] (cmp_general_fmc2_n_162),
- .\axi_rdata_reg[14]_0 (cmp_general_fmc2_n_163),
- .\axi_rdata_reg[15] (cmp_general_fmc2_n_164),
- .\axi_rdata_reg[15]_0 (cmp_general_fmc2_n_165),
- .\axi_rdata_reg[16] (cmp_general_fmc2_n_166),
- .\axi_rdata_reg[16]_0 (cmp_general_fmc2_n_167),
- .\axi_rdata_reg[17] (cmp_general_fmc2_n_168),
- .\axi_rdata_reg[17]_0 (cmp_general_fmc2_n_169),
- .\axi_rdata_reg[18] (cmp_general_fmc2_n_170),
- .\axi_rdata_reg[18]_0 (cmp_general_fmc2_n_171),
- .\axi_rdata_reg[19] (cmp_general_fmc2_n_172),
- .\axi_rdata_reg[19]_0 (cmp_general_fmc2_n_173),
- .\axi_rdata_reg[1] (cmp_general_fmc2_n_129),
- .\axi_rdata_reg[1]_0 (cmp_general_fmc2_n_130),
- .\axi_rdata_reg[1]_1 (cmp_general_fmc2_n_131),
- .\axi_rdata_reg[20] (cmp_general_fmc2_n_174),
- .\axi_rdata_reg[20]_0 (cmp_general_fmc2_n_175),
- .\axi_rdata_reg[20]_1 (cmp_general_fmc2_n_176),
- .\axi_rdata_reg[21] (cmp_general_fmc2_n_177),
- .\axi_rdata_reg[21]_0 (cmp_general_fmc2_n_178),
- .\axi_rdata_reg[21]_1 (cmp_general_fmc2_n_179),
- .\axi_rdata_reg[22] (cmp_general_fmc2_n_180),
- .\axi_rdata_reg[22]_0 (cmp_general_fmc2_n_181),
- .\axi_rdata_reg[22]_1 (cmp_general_fmc2_n_182),
- .\axi_rdata_reg[23] (cmp_general_fmc2_n_183),
- .\axi_rdata_reg[23]_0 (cmp_general_fmc2_n_184),
- .\axi_rdata_reg[23]_1 (cmp_general_fmc2_n_185),
- .\axi_rdata_reg[2] (cmp_general_fmc2_n_132),
- .\axi_rdata_reg[2]_0 (cmp_general_fmc2_n_133),
- .\axi_rdata_reg[2]_1 (cmp_general_fmc2_n_134),
- .\axi_rdata_reg[31] (\s_datao_fmc2[28] ),
- .\axi_rdata_reg[3] (cmp_general_fmc2_n_135),
- .\axi_rdata_reg[3]_0 (cmp_general_fmc2_n_136),
- .\axi_rdata_reg[3]_1 (cmp_general_fmc2_n_137),
- .\axi_rdata_reg[3]_2 (\s_datao_fmc2[1] ),
- .\axi_rdata_reg[4] (cmp_general_fmc2_n_138),
- .\axi_rdata_reg[4]_0 (cmp_general_fmc2_n_139),
- .\axi_rdata_reg[4]_1 (cmp_general_fmc2_n_140),
- .\axi_rdata_reg[5] (cmp_general_fmc2_n_141),
- .\axi_rdata_reg[5]_0 (cmp_general_fmc2_n_142),
- .\axi_rdata_reg[5]_1 (cmp_general_fmc2_n_143),
- .\axi_rdata_reg[6] (cmp_general_fmc2_n_144),
- .\axi_rdata_reg[6]_0 (cmp_general_fmc2_n_145),
- .\axi_rdata_reg[6]_1 (cmp_general_fmc2_n_146),
- .\axi_rdata_reg[7] (cmp_general_fmc2_n_147),
- .\axi_rdata_reg[7]_0 (cmp_general_fmc2_n_148),
- .\axi_rdata_reg[7]_1 (cmp_general_fmc2_n_149),
- .\axi_rdata_reg[8] (cmp_general_fmc2_n_150),
- .\axi_rdata_reg[8]_0 (cmp_general_fmc2_n_151),
- .\axi_rdata_reg[9] (cmp_general_fmc2_n_152),
- .\axi_rdata_reg[9]_0 (cmp_general_fmc2_n_153),
- .\data_rw_o_reg[100][11] (\data_rw_o[100] ),
- .\data_rw_o_reg[101][11] (\data_rw_o[101] ),
- .\data_rw_o_reg[102][11] (\data_rw_o[102] ),
- .\data_rw_o_reg[103][11] (\data_rw_o[103] ),
- .\data_rw_o_reg[78][4] (cmp_axi4lite_slave_n_534),
- .\data_rw_o_reg[78][5] (cmp_axi4lite_slave_n_533),
- .\data_rw_o_reg[78][6] (cmp_axi4lite_slave_n_532),
- .\data_rw_o_reg[78][7] (cmp_axi4lite_slave_n_531),
- .\data_rw_o_reg[79][7] ({\data_rw_o[79] [7],\data_rw_o[79] [2:1]}),
- .\data_rw_o_reg[84][11] (\data_rw_o[84] ),
- .\data_rw_o_reg[84][11]_0 (\gen_spi.cmp_dac7716_spi/p_19_out ),
- .\data_rw_o_reg[85][11] (\data_rw_o[85] ),
- .\data_rw_o_reg[85][11]_0 (\gen_spi.cmp_dac7716_spi/p_18_out ),
- .\data_rw_o_reg[86][11] (\data_rw_o[86] ),
- .\data_rw_o_reg[86][11]_0 (\gen_spi.cmp_dac7716_spi/p_17_out ),
- .\data_rw_o_reg[87][11] (\data_rw_o[87] ),
- .\data_rw_o_reg[87][11]_0 (\gen_spi.cmp_dac7716_spi/p_16_out ),
- .\data_rw_o_reg[88][11] (\data_rw_o[88] ),
- .\data_rw_o_reg[88][11]_0 (\gen_spi.cmp_dac7716_spi/p_15_out ),
- .\data_rw_o_reg[89][11] (\data_rw_o[89] ),
- .\data_rw_o_reg[89][11]_0 (\gen_spi.cmp_dac7716_spi/p_14_out ),
- .\data_rw_o_reg[90][11] (\data_rw_o[90] ),
- .\data_rw_o_reg[90][11]_0 (\gen_spi.cmp_dac7716_spi/p_13_out ),
- .\data_rw_o_reg[91][11] (\data_rw_o[91] ),
- .\data_rw_o_reg[91][11]_0 (\gen_spi.cmp_dac7716_spi/p_12_out ),
- .\data_rw_o_reg[92][11] (\data_rw_o[92] ),
- .\data_rw_o_reg[93][11] (\data_rw_o[93] ),
- .\data_rw_o_reg[94][11] (\data_rw_o[94] ),
- .\data_rw_o_reg[95][11] (\data_rw_o[95] ),
- .\data_rw_o_reg[96][11] (\data_rw_o[96] ),
- .\data_rw_o_reg[97][11] (\data_rw_o[97] ),
- .\data_rw_o_reg[98][11] (\data_rw_o[98] ),
- .\data_rw_o_reg[99][11] (\data_rw_o[99] ),
- .fmc2_intr(fmc2_intr),
- .fmc2_intr_led(fmc2_intr_led),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_count_reg(\s_datao_fmc2[4] ),
- .\s_datao_fmc2[0] (\s_datao_fmc2[0] ),
- .\s_tx_data_reg[111] (\gen_spi.cmp_dac7716_spi/[0].[0].s_reqs_reg[0][value]__0_14 ),
- .\s_tx_data_reg[15] (\gen_spi.cmp_dac7716_spi/[0].[1].s_reqs_reg[1][value]__0_13 ),
- .\s_tx_data_reg[15]_0 (\gen_spi.cmp_dac7716_spi/[0].[2].s_reqs_reg[2][value]__0_12 ),
- .\s_tx_data_reg[39] (\gen_spi.cmp_dac7716_spi/[1].[3].s_reqs_reg[7][value]__0_11 ),
- .\s_tx_data_reg[39]_0 (\gen_spi.cmp_dac7716_spi/[1].[0].s_reqs_reg[4][value]__0_10 ),
- .\s_tx_data_reg[39]_1 (\gen_spi.cmp_dac7716_spi/[1].[1].s_reqs_reg[5][value]__0_9 ),
- .\s_tx_data_reg[39]_2 (\gen_spi.cmp_dac7716_spi/[1].[2].s_reqs_reg[6][value]__0_8 ));
- system_design_fasec_hwtest_0_0_clockDivider cmp_watchdog
- (.ps_clk_i(ps_clk_i),
- .rst_i(rst_i),
- .watchdog_pl_o(watchdog_pl_o));
- FDRE #(
- .INIT(1'b0))
- \s_ins_reg[0]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(v_ins[0]),
- .Q(\s_ins_reg_n_0_[0] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \s_ins_reg[1]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(v_ins[1]),
- .Q(\s_ins_reg_n_0_[1] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \s_ins_reg[2]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(v_ins[2]),
- .Q(\s_ins_reg_n_0_[2] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \s_ins_reg[3]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(v_ins[3]),
- .Q(\s_ins_reg_n_0_[3] ),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair58" *)
- LUT5 #(
- .INIT(32'h77777775))
- s_led_line_i_1
- (.I0(p_2_in),
- .I1(\s_leds[3]_i_5_n_0 ),
- .I2(led_line_pl_o),
- .I3(s_led_line_i_2_n_0),
- .I4(\s_leds[3]_i_4_n_0 ),
- .O(s_led_line_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair59" *)
- LUT4 #(
- .INIT(16'hFFAC))
- s_led_line_i_2
- (.I0(v_shift[3]),
- .I1(v_shift[5]),
- .I2(s_tick),
- .I3(v_shift[4]),
- .O(s_led_line_i_2_n_0));
- FDRE #(
- .INIT(1'b1))
- s_led_line_reg
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(s_led_line_i_1_n_0),
- .Q(led_line_pl_o),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hB8B800FF00000000))
- \s_leds[0]_i_1
- (.I0(v_shift[7]),
- .I1(s_tick),
- .I2(v_shift[0]),
- .I3(p_0_in[0]),
- .I4(\s_leds[3]_i_5_n_0 ),
- .I5(p_2_in),
- .O(\s_leds[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hB8B800FF00000000))
- \s_leds[1]_i_1
- (.I0(v_shift[0]),
- .I1(s_tick),
- .I2(v_shift[1]),
- .I3(p_0_in[1]),
- .I4(\s_leds[3]_i_5_n_0 ),
- .I5(p_2_in),
- .O(\s_leds[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hB8B800FF00000000))
- \s_leds[2]_i_1
- (.I0(v_shift[1]),
- .I1(s_tick),
- .I2(v_shift[2]),
- .I3(p_0_in[2]),
- .I4(\s_leds[3]_i_5_n_0 ),
- .I5(p_2_in),
- .O(\s_leds[2]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFEEFA))
- \s_leds[3]_i_1
- (.I0(\s_leds[3]_i_3_n_0 ),
- .I1(v_shift[3]),
- .I2(v_shift[5]),
- .I3(s_tick),
- .I4(v_shift[4]),
- .I5(\s_leds[3]_i_4_n_0 ),
- .O(\s_leds[3]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hB8B800FF00000000))
- \s_leds[3]_i_2
- (.I0(v_shift[2]),
- .I1(s_tick),
- .I2(v_shift[3]),
- .I3(p_0_in[3]),
- .I4(\s_leds[3]_i_5_n_0 ),
- .I5(p_2_in),
- .O(\s_leds[3]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair58" *)
- LUT2 #(
- .INIT(4'hB))
- \s_leds[3]_i_3
- (.I0(\s_leds[3]_i_5_n_0 ),
- .I1(p_2_in),
- .O(\s_leds[3]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair60" *)
- LUT4 #(
- .INIT(16'hFECE))
- \s_leds[3]_i_4
- (.I0(v_shift[7]),
- .I1(v_shift[6]),
- .I2(s_tick),
- .I3(v_shift[5]),
- .O(\s_leds[3]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hFFFEFFFEFFFFFFFC))
- \s_leds[3]_i_5
- (.I0(v_shift[7]),
- .I1(v_shift[1]),
- .I2(v_shift[2]),
- .I3(v_shift[0]),
- .I4(v_shift[3]),
- .I5(s_tick),
- .O(\s_leds[3]_i_5_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \s_leds_reg[0]
- (.C(ps_clk_i),
- .CE(\s_leds[3]_i_1_n_0 ),
- .D(\s_leds[0]_i_1_n_0 ),
- .Q(led_col_pl_o[0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \s_leds_reg[1]
- (.C(ps_clk_i),
- .CE(\s_leds[3]_i_1_n_0 ),
- .D(\s_leds[1]_i_1_n_0 ),
- .Q(led_col_pl_o[1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \s_leds_reg[2]
- (.C(ps_clk_i),
- .CE(\s_leds[3]_i_1_n_0 ),
- .D(\s_leds[2]_i_1_n_0 ),
- .Q(led_col_pl_o[2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \s_leds_reg[3]
- (.C(ps_clk_i),
- .CE(\s_leds[3]_i_1_n_0 ),
- .D(\s_leds[3]_i_2_n_0 ),
- .Q(led_col_pl_o[3]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair61" *)
- LUT2 #(
- .INIT(4'h6))
- s_tick_i_1
- (.I0(clear),
- .I1(s_tick),
- .O(s_tick_i_1_n_0));
- FDRE s_tick_reg
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(s_tick_i_1_n_0),
- .Q(s_tick),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFEEFEEE))
- \v_cntr[0]_i_1
- (.I0(\v_cntr[0]_i_3_n_0 ),
- .I1(\v_cntr[0]_i_4_n_0 ),
- .I2(v_cntr_reg[24]),
- .I3(v_cntr_reg[25]),
- .I4(v_cntr_reg[23]),
- .I5(\v_cntr[0]_i_5_n_0 ),
- .O(clear));
- LUT3 #(
- .INIT(8'h80))
- \v_cntr[0]_i_10
- (.I0(v_cntr_reg[22]),
- .I1(v_cntr_reg[21]),
- .I2(v_cntr_reg[25]),
- .O(\v_cntr[0]_i_10_n_0 ));
- LUT6 #(
- .INIT(64'hEAEAEAAA00000000))
- \v_cntr[0]_i_11
- (.I0(v_cntr_reg[13]),
- .I1(v_cntr_reg[12]),
- .I2(v_cntr_reg[11]),
- .I3(v_cntr_reg[10]),
- .I4(v_cntr_reg[9]),
- .I5(v_cntr_reg[14]),
- .O(\v_cntr[0]_i_11_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \v_cntr[0]_i_3
- (.I0(v_cntr_reg[27]),
- .I1(v_cntr_reg[26]),
- .I2(v_cntr_reg[29]),
- .I3(v_cntr_reg[28]),
- .O(\v_cntr[0]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'h88888880))
- \v_cntr[0]_i_4
- (.I0(v_cntr_reg[17]),
- .I1(\v_cntr[0]_i_10_n_0 ),
- .I2(v_cntr_reg[15]),
- .I3(v_cntr_reg[16]),
- .I4(\v_cntr[0]_i_11_n_0 ),
- .O(\v_cntr[0]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hFFFCFFFCFFFCFEFC))
- \v_cntr[0]_i_5
- (.I0(v_cntr_reg[18]),
- .I1(v_cntr_reg[30]),
- .I2(v_cntr_reg[31]),
- .I3(\v_cntr[0]_i_10_n_0 ),
- .I4(v_cntr_reg[20]),
- .I5(v_cntr_reg[19]),
- .O(\v_cntr[0]_i_5_n_0 ));
- LUT1 #(
- .INIT(2'h1))
- \v_cntr[0]_i_9
- (.I0(\v_cntr_reg_n_0_[0] ),
- .O(\v_cntr[0]_i_9_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[0]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[0]_i_2_n_7 ),
- .Q(\v_cntr_reg_n_0_[0] ),
- .R(clear));
- CARRY4 \v_cntr_reg[0]_i_2
- (.CI(1'b0),
- .CO({\v_cntr_reg[0]_i_2_n_0 ,\v_cntr_reg[0]_i_2_n_1 ,\v_cntr_reg[0]_i_2_n_2 ,\v_cntr_reg[0]_i_2_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b1}),
- .O({\v_cntr_reg[0]_i_2_n_4 ,\v_cntr_reg[0]_i_2_n_5 ,\v_cntr_reg[0]_i_2_n_6 ,\v_cntr_reg[0]_i_2_n_7 }),
- .S({\v_cntr_reg_n_0_[3] ,\v_cntr_reg_n_0_[2] ,\v_cntr_reg_n_0_[1] ,\v_cntr[0]_i_9_n_0 }));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[10]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[8]_i_1_n_5 ),
- .Q(v_cntr_reg[10]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[11]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[8]_i_1_n_4 ),
- .Q(v_cntr_reg[11]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[12]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[12]_i_1_n_7 ),
- .Q(v_cntr_reg[12]),
- .R(clear));
- CARRY4 \v_cntr_reg[12]_i_1
- (.CI(\v_cntr_reg[8]_i_1_n_0 ),
- .CO({\v_cntr_reg[12]_i_1_n_0 ,\v_cntr_reg[12]_i_1_n_1 ,\v_cntr_reg[12]_i_1_n_2 ,\v_cntr_reg[12]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\v_cntr_reg[12]_i_1_n_4 ,\v_cntr_reg[12]_i_1_n_5 ,\v_cntr_reg[12]_i_1_n_6 ,\v_cntr_reg[12]_i_1_n_7 }),
- .S(v_cntr_reg[15:12]));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[13]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[12]_i_1_n_6 ),
- .Q(v_cntr_reg[13]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[14]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[12]_i_1_n_5 ),
- .Q(v_cntr_reg[14]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[15]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[12]_i_1_n_4 ),
- .Q(v_cntr_reg[15]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[16]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[16]_i_1_n_7 ),
- .Q(v_cntr_reg[16]),
- .R(clear));
- CARRY4 \v_cntr_reg[16]_i_1
- (.CI(\v_cntr_reg[12]_i_1_n_0 ),
- .CO({\v_cntr_reg[16]_i_1_n_0 ,\v_cntr_reg[16]_i_1_n_1 ,\v_cntr_reg[16]_i_1_n_2 ,\v_cntr_reg[16]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\v_cntr_reg[16]_i_1_n_4 ,\v_cntr_reg[16]_i_1_n_5 ,\v_cntr_reg[16]_i_1_n_6 ,\v_cntr_reg[16]_i_1_n_7 }),
- .S(v_cntr_reg[19:16]));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[17]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[16]_i_1_n_6 ),
- .Q(v_cntr_reg[17]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[18]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[16]_i_1_n_5 ),
- .Q(v_cntr_reg[18]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[19]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[16]_i_1_n_4 ),
- .Q(v_cntr_reg[19]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[1]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[0]_i_2_n_6 ),
- .Q(\v_cntr_reg_n_0_[1] ),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[20]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[20]_i_1_n_7 ),
- .Q(v_cntr_reg[20]),
- .R(clear));
- CARRY4 \v_cntr_reg[20]_i_1
- (.CI(\v_cntr_reg[16]_i_1_n_0 ),
- .CO({\v_cntr_reg[20]_i_1_n_0 ,\v_cntr_reg[20]_i_1_n_1 ,\v_cntr_reg[20]_i_1_n_2 ,\v_cntr_reg[20]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\v_cntr_reg[20]_i_1_n_4 ,\v_cntr_reg[20]_i_1_n_5 ,\v_cntr_reg[20]_i_1_n_6 ,\v_cntr_reg[20]_i_1_n_7 }),
- .S(v_cntr_reg[23:20]));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[21]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[20]_i_1_n_6 ),
- .Q(v_cntr_reg[21]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[22]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[20]_i_1_n_5 ),
- .Q(v_cntr_reg[22]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[23]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[20]_i_1_n_4 ),
- .Q(v_cntr_reg[23]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[24]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[24]_i_1_n_7 ),
- .Q(v_cntr_reg[24]),
- .R(clear));
- CARRY4 \v_cntr_reg[24]_i_1
- (.CI(\v_cntr_reg[20]_i_1_n_0 ),
- .CO({\v_cntr_reg[24]_i_1_n_0 ,\v_cntr_reg[24]_i_1_n_1 ,\v_cntr_reg[24]_i_1_n_2 ,\v_cntr_reg[24]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\v_cntr_reg[24]_i_1_n_4 ,\v_cntr_reg[24]_i_1_n_5 ,\v_cntr_reg[24]_i_1_n_6 ,\v_cntr_reg[24]_i_1_n_7 }),
- .S(v_cntr_reg[27:24]));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[25]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[24]_i_1_n_6 ),
- .Q(v_cntr_reg[25]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[26]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[24]_i_1_n_5 ),
- .Q(v_cntr_reg[26]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[27]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[24]_i_1_n_4 ),
- .Q(v_cntr_reg[27]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[28]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[28]_i_1_n_7 ),
- .Q(v_cntr_reg[28]),
- .R(clear));
- CARRY4 \v_cntr_reg[28]_i_1
- (.CI(\v_cntr_reg[24]_i_1_n_0 ),
- .CO({\NLW_v_cntr_reg[28]_i_1_CO_UNCONNECTED [3],\v_cntr_reg[28]_i_1_n_1 ,\v_cntr_reg[28]_i_1_n_2 ,\v_cntr_reg[28]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\v_cntr_reg[28]_i_1_n_4 ,\v_cntr_reg[28]_i_1_n_5 ,\v_cntr_reg[28]_i_1_n_6 ,\v_cntr_reg[28]_i_1_n_7 }),
- .S(v_cntr_reg[31:28]));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[29]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[28]_i_1_n_6 ),
- .Q(v_cntr_reg[29]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[2]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[0]_i_2_n_5 ),
- .Q(\v_cntr_reg_n_0_[2] ),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[30]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[28]_i_1_n_5 ),
- .Q(v_cntr_reg[30]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[31]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[28]_i_1_n_4 ),
- .Q(v_cntr_reg[31]),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[3]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[0]_i_2_n_4 ),
- .Q(\v_cntr_reg_n_0_[3] ),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[4]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[4]_i_1_n_7 ),
- .Q(\v_cntr_reg_n_0_[4] ),
- .R(clear));
- CARRY4 \v_cntr_reg[4]_i_1
- (.CI(\v_cntr_reg[0]_i_2_n_0 ),
- .CO({\v_cntr_reg[4]_i_1_n_0 ,\v_cntr_reg[4]_i_1_n_1 ,\v_cntr_reg[4]_i_1_n_2 ,\v_cntr_reg[4]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\v_cntr_reg[4]_i_1_n_4 ,\v_cntr_reg[4]_i_1_n_5 ,\v_cntr_reg[4]_i_1_n_6 ,\v_cntr_reg[4]_i_1_n_7 }),
- .S({\v_cntr_reg_n_0_[7] ,\v_cntr_reg_n_0_[6] ,\v_cntr_reg_n_0_[5] ,\v_cntr_reg_n_0_[4] }));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[5]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[4]_i_1_n_6 ),
- .Q(\v_cntr_reg_n_0_[5] ),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[6]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[4]_i_1_n_5 ),
- .Q(\v_cntr_reg_n_0_[6] ),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[7]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[4]_i_1_n_4 ),
- .Q(\v_cntr_reg_n_0_[7] ),
- .R(clear));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[8]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[8]_i_1_n_7 ),
- .Q(\v_cntr_reg_n_0_[8] ),
- .R(clear));
- CARRY4 \v_cntr_reg[8]_i_1
- (.CI(\v_cntr_reg[4]_i_1_n_0 ),
- .CO({\v_cntr_reg[8]_i_1_n_0 ,\v_cntr_reg[8]_i_1_n_1 ,\v_cntr_reg[8]_i_1_n_2 ,\v_cntr_reg[8]_i_1_n_3 }),
- .CYINIT(1'b0),
- .DI({1'b0,1'b0,1'b0,1'b0}),
- .O({\v_cntr_reg[8]_i_1_n_4 ,\v_cntr_reg[8]_i_1_n_5 ,\v_cntr_reg[8]_i_1_n_6 ,\v_cntr_reg[8]_i_1_n_7 }),
- .S({v_cntr_reg[11:9],\v_cntr_reg_n_0_[8] }));
- FDRE #(
- .INIT(1'b0))
- \v_cntr_reg[9]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_cntr_reg[8]_i_1_n_6 ),
- .Q(v_cntr_reg[9]),
- .R(clear));
- LUT1 #(
- .INIT(2'h1))
- \v_ins[2]_i_1
- (.I0(dig_in3_n_i),
- .O(p_0_out[2]));
- LUT1 #(
- .INIT(2'h1))
- \v_ins[3]_i_1
- (.I0(dig_in4_n_i),
- .O(p_0_out[3]));
- FDRE #(
- .INIT(1'b0))
- \v_ins_reg[0]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(dig_in1_i),
- .Q(v_ins[0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \v_ins_reg[1]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(dig_in2_i),
- .Q(v_ins[1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \v_ins_reg[2]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(p_0_out[2]),
- .Q(v_ins[2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \v_ins_reg[3]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(p_0_out[3]),
- .Q(v_ins[3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \v_pbreg_reg[0]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(pb_gp_n_i),
- .Q(\v_pbreg_reg_n_0_[0] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \v_pbreg_reg[1]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_pbreg_reg_n_0_[0] ),
- .Q(p_2_in),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair62" *)
- LUT3 #(
- .INIT(8'hB8))
- \v_shift[0]_i_1
- (.I0(v_shift[7]),
- .I1(s_tick),
- .I2(v_shift[0]),
- .O(\v_shift[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair62" *)
- LUT3 #(
- .INIT(8'hB8))
- \v_shift[1]_i_1
- (.I0(v_shift[0]),
- .I1(s_tick),
- .I2(v_shift[1]),
- .O(\v_shift[1]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'hB8))
- \v_shift[2]_i_1
- (.I0(v_shift[1]),
- .I1(s_tick),
- .I2(v_shift[2]),
- .O(\v_shift[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair63" *)
- LUT3 #(
- .INIT(8'hB8))
- \v_shift[3]_i_1
- (.I0(v_shift[2]),
- .I1(s_tick),
- .I2(v_shift[3]),
- .O(\v_shift[3]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair63" *)
- LUT3 #(
- .INIT(8'hB8))
- \v_shift[4]_i_1
- (.I0(v_shift[3]),
- .I1(s_tick),
- .I2(v_shift[4]),
- .O(p_0_in[0]));
- (* SOFT_HLUTNM = "soft_lutpair59" *)
- LUT3 #(
- .INIT(8'hB8))
- \v_shift[5]_i_1
- (.I0(v_shift[4]),
- .I1(s_tick),
- .I2(v_shift[5]),
- .O(p_0_in[1]));
- (* SOFT_HLUTNM = "soft_lutpair61" *)
- LUT3 #(
- .INIT(8'hB8))
- \v_shift[6]_i_1
- (.I0(v_shift[5]),
- .I1(s_tick),
- .I2(v_shift[6]),
- .O(p_0_in[2]));
- (* SOFT_HLUTNM = "soft_lutpair60" *)
- LUT3 #(
- .INIT(8'hB8))
- \v_shift[7]_i_1
- (.I0(v_shift[6]),
- .I1(s_tick),
- .I2(v_shift[7]),
- .O(p_0_in[3]));
- FDRE #(
- .INIT(1'b1))
- \v_shift_reg[0]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_shift[0]_i_1_n_0 ),
- .Q(v_shift[0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \v_shift_reg[1]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_shift[1]_i_1_n_0 ),
- .Q(v_shift[1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \v_shift_reg[2]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_shift[2]_i_1_n_0 ),
- .Q(v_shift[2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \v_shift_reg[3]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(\v_shift[3]_i_1_n_0 ),
- .Q(v_shift[3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \v_shift_reg[4]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(p_0_in[0]),
- .Q(v_shift[4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \v_shift_reg[5]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(p_0_in[1]),
- .Q(v_shift[5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \v_shift_reg[6]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(p_0_in[2]),
- .Q(v_shift[6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \v_shift_reg[7]
- (.C(ps_clk_i),
- .CE(1'b1),
- .D(p_0_in[3]),
- .Q(v_shift[7]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "general_fmc" *)
-module system_design_fasec_hwtest_0_0_general_fmc
- (\FMC1_LA_P_b[27] ,
- \FMC1_LA_N_b[27] ,
- rst_i,
- Q,
- \s_tx_data_reg[111] ,
- \s_tx_data_reg[15] ,
- \s_tx_data_reg[15]_0 ,
- \s_tx_data_reg[39] ,
- \s_tx_data_reg[39]_0 ,
- \s_tx_data_reg[39]_1 ,
- \s_tx_data_reg[39]_2 ,
- \axi_rdata_reg[0] ,
- s_count_reg,
- \axi_rdata_reg[0]_0 ,
- \axi_rdata_reg[0]_1 ,
- \axi_rdata_reg[0]_2 ,
- \axi_rdata_reg[0]_3 ,
- \axi_rdata_reg[1] ,
- \axi_rdata_reg[1]_0 ,
- \axi_rdata_reg[1]_1 ,
- \axi_rdata_reg[1]_2 ,
- \axi_rdata_reg[1]_3 ,
- \axi_rdata_reg[2] ,
- \axi_rdata_reg[2]_0 ,
- \axi_rdata_reg[2]_1 ,
- \axi_rdata_reg[2]_2 ,
- \axi_rdata_reg[2]_3 ,
- \axi_rdata_reg[3] ,
- \axi_rdata_reg[3]_0 ,
- \axi_rdata_reg[3]_1 ,
- \axi_rdata_reg[3]_2 ,
- \axi_rdata_reg[3]_3 ,
- \axi_rdata_reg[4] ,
- \axi_rdata_reg[4]_0 ,
- \axi_rdata_reg[4]_1 ,
- \axi_rdata_reg[4]_2 ,
- \axi_rdata_reg[4]_3 ,
- \axi_rdata_reg[5] ,
- \axi_rdata_reg[5]_0 ,
- \axi_rdata_reg[5]_1 ,
- \axi_rdata_reg[5]_2 ,
- \axi_rdata_reg[5]_3 ,
- \axi_rdata_reg[6] ,
- \axi_rdata_reg[6]_0 ,
- \axi_rdata_reg[6]_1 ,
- \axi_rdata_reg[6]_2 ,
- \axi_rdata_reg[6]_3 ,
- \axi_rdata_reg[7] ,
- \axi_rdata_reg[7]_0 ,
- \axi_rdata_reg[7]_1 ,
- \axi_rdata_reg[7]_2 ,
- \axi_rdata_reg[7]_3 ,
- \axi_rdata_reg[8] ,
- \axi_rdata_reg[8]_0 ,
- \axi_rdata_reg[8]_1 ,
- \axi_rdata_reg[8]_2 ,
- \axi_rdata_reg[9] ,
- \axi_rdata_reg[9]_0 ,
- \axi_rdata_reg[9]_1 ,
- \axi_rdata_reg[9]_2 ,
- \axi_rdata_reg[10] ,
- \axi_rdata_reg[10]_0 ,
- \axi_rdata_reg[10]_1 ,
- \axi_rdata_reg[10]_2 ,
- \axi_rdata_reg[11] ,
- \axi_rdata_reg[11]_0 ,
- \axi_rdata_reg[11]_1 ,
- \axi_rdata_reg[11]_2 ,
- \axi_rdata_reg[12] ,
- \axi_rdata_reg[12]_0 ,
- \axi_rdata_reg[12]_1 ,
- \axi_rdata_reg[12]_2 ,
- \axi_rdata_reg[13] ,
- \axi_rdata_reg[13]_0 ,
- \axi_rdata_reg[13]_1 ,
- \axi_rdata_reg[13]_2 ,
- \axi_rdata_reg[14] ,
- \axi_rdata_reg[14]_0 ,
- \axi_rdata_reg[14]_1 ,
- \axi_rdata_reg[14]_2 ,
- \axi_rdata_reg[15] ,
- \axi_rdata_reg[15]_0 ,
- \axi_rdata_reg[15]_1 ,
- \axi_rdata_reg[15]_2 ,
- \axi_rdata_reg[16] ,
- \axi_rdata_reg[16]_0 ,
- \axi_rdata_reg[16]_1 ,
- \axi_rdata_reg[16]_2 ,
- \axi_rdata_reg[17] ,
- \axi_rdata_reg[17]_0 ,
- \axi_rdata_reg[17]_1 ,
- \axi_rdata_reg[17]_2 ,
- \axi_rdata_reg[18] ,
- \axi_rdata_reg[18]_0 ,
- \axi_rdata_reg[18]_1 ,
- \axi_rdata_reg[18]_2 ,
- \axi_rdata_reg[19] ,
- \axi_rdata_reg[19]_0 ,
- \axi_rdata_reg[19]_1 ,
- \axi_rdata_reg[19]_2 ,
- \axi_rdata_reg[20] ,
- \axi_rdata_reg[20]_0 ,
- \axi_rdata_reg[20]_1 ,
- \axi_rdata_reg[20]_2 ,
- \axi_rdata_reg[20]_3 ,
- \axi_rdata_reg[21] ,
- \axi_rdata_reg[21]_0 ,
- \axi_rdata_reg[21]_1 ,
- \axi_rdata_reg[21]_2 ,
- \axi_rdata_reg[21]_3 ,
- \axi_rdata_reg[22] ,
- \axi_rdata_reg[22]_0 ,
- \axi_rdata_reg[22]_1 ,
- \axi_rdata_reg[22]_2 ,
- \axi_rdata_reg[22]_3 ,
- \axi_rdata_reg[23] ,
- \axi_rdata_reg[23]_0 ,
- \axi_rdata_reg[23]_1 ,
- \axi_rdata_reg[23]_2 ,
- \axi_rdata_reg[23]_3 ,
- \s_datao_fmc1[0] ,
- intr_o,
- intr_led_o,
- \axi_rdata_reg[31] ,
- \axi_rdata_reg[3]_4 ,
- FMC1_LA_P_b,
- FMC1_LA_N_b,
- \FMC1_LA_P_b[32] ,
- \FMC1_LA_N_b[32] ,
- D,
- s00_axi_aclk,
- s00_axi_aresetn,
- \data_rw_o_reg[11][7] ,
- \axi_araddr_reg[3]_rep__3 ,
- \axi_araddr_reg[2]_rep__3 ,
- \axi_araddr_reg[4]_rep__1 ,
- \axi_araddr_reg[4]_rep__0 ,
- \axi_araddr_reg[3]_rep__2 ,
- \axi_araddr_reg[2]_rep__2 ,
- \axi_araddr_reg[3]_rep__1 ,
- \axi_araddr_reg[2]_rep__1 ,
- \axi_araddr_reg[4]_rep ,
- \axi_araddr_reg[3]_rep__0 ,
- \axi_araddr_reg[2]_rep__0 ,
- \axi_araddr_reg[3]_rep ,
- \axi_araddr_reg[2]_rep ,
- \axi_araddr_reg[4] ,
- fmc2_intr,
- fmc2_intr_led,
- \data_rw_o_reg[19][11] ,
- CO,
- \data_rw_o_reg[18][11] ,
- \data_rw_o_reg[18][11]_0 ,
- \data_rw_o_reg[17][11] ,
- \data_rw_o_reg[17][11]_0 ,
- \data_rw_o_reg[16][11] ,
- \data_rw_o_reg[16][11]_0 ,
- \data_rw_o_reg[20][11] ,
- \data_rw_o_reg[20][11]_0 ,
- \data_rw_o_reg[21][11] ,
- \data_rw_o_reg[21][11]_0 ,
- \data_rw_o_reg[22][11] ,
- \data_rw_o_reg[22][11]_0 ,
- \data_rw_o_reg[23][11] ,
- \data_rw_o_reg[23][11]_0 ,
- \data_rw_o_reg[24][11] ,
- \data_rw_o_reg[25][11] ,
- \data_rw_o_reg[26][11] ,
- \data_rw_o_reg[27][11] ,
- \data_rw_o_reg[28][11] ,
- \data_rw_o_reg[29][11] ,
- \data_rw_o_reg[30][11] ,
- \data_rw_o_reg[31][11] ,
- \data_rw_o_reg[32][11] ,
- \data_rw_o_reg[33][11] ,
- \data_rw_o_reg[34][11] ,
- \data_rw_o_reg[35][11] ,
- \data_rw_o_reg[10][7] ,
- \data_rw_o_reg[10][6] ,
- \data_rw_o_reg[10][5] ,
- \data_rw_o_reg[10][4] );
- output [7:0]\FMC1_LA_P_b[27] ;
- output [7:0]\FMC1_LA_N_b[27] ;
- output rst_i;
- output [11:0]Q;
- output [11:0]\s_tx_data_reg[111] ;
- output [11:0]\s_tx_data_reg[15] ;
- output [11:0]\s_tx_data_reg[15]_0 ;
- output [11:0]\s_tx_data_reg[39] ;
- output [11:0]\s_tx_data_reg[39]_0 ;
- output [11:0]\s_tx_data_reg[39]_1 ;
- output [11:0]\s_tx_data_reg[39]_2 ;
- output \axi_rdata_reg[0] ;
- output [11:0]s_count_reg;
- output \axi_rdata_reg[0]_0 ;
- output \axi_rdata_reg[0]_1 ;
- output \axi_rdata_reg[0]_2 ;
- output \axi_rdata_reg[0]_3 ;
- output \axi_rdata_reg[1] ;
- output \axi_rdata_reg[1]_0 ;
- output \axi_rdata_reg[1]_1 ;
- output \axi_rdata_reg[1]_2 ;
- output \axi_rdata_reg[1]_3 ;
- output \axi_rdata_reg[2] ;
- output \axi_rdata_reg[2]_0 ;
- output \axi_rdata_reg[2]_1 ;
- output \axi_rdata_reg[2]_2 ;
- output \axi_rdata_reg[2]_3 ;
- output \axi_rdata_reg[3] ;
- output \axi_rdata_reg[3]_0 ;
- output \axi_rdata_reg[3]_1 ;
- output \axi_rdata_reg[3]_2 ;
- output \axi_rdata_reg[3]_3 ;
- output \axi_rdata_reg[4] ;
- output \axi_rdata_reg[4]_0 ;
- output \axi_rdata_reg[4]_1 ;
- output \axi_rdata_reg[4]_2 ;
- output \axi_rdata_reg[4]_3 ;
- output \axi_rdata_reg[5] ;
- output \axi_rdata_reg[5]_0 ;
- output \axi_rdata_reg[5]_1 ;
- output \axi_rdata_reg[5]_2 ;
- output \axi_rdata_reg[5]_3 ;
- output \axi_rdata_reg[6] ;
- output \axi_rdata_reg[6]_0 ;
- output \axi_rdata_reg[6]_1 ;
- output \axi_rdata_reg[6]_2 ;
- output \axi_rdata_reg[6]_3 ;
- output \axi_rdata_reg[7] ;
- output \axi_rdata_reg[7]_0 ;
- output \axi_rdata_reg[7]_1 ;
- output \axi_rdata_reg[7]_2 ;
- output \axi_rdata_reg[7]_3 ;
- output \axi_rdata_reg[8] ;
- output \axi_rdata_reg[8]_0 ;
- output \axi_rdata_reg[8]_1 ;
- output \axi_rdata_reg[8]_2 ;
- output \axi_rdata_reg[9] ;
- output \axi_rdata_reg[9]_0 ;
- output \axi_rdata_reg[9]_1 ;
- output \axi_rdata_reg[9]_2 ;
- output \axi_rdata_reg[10] ;
- output \axi_rdata_reg[10]_0 ;
- output \axi_rdata_reg[10]_1 ;
- output \axi_rdata_reg[10]_2 ;
- output \axi_rdata_reg[11] ;
- output \axi_rdata_reg[11]_0 ;
- output \axi_rdata_reg[11]_1 ;
- output \axi_rdata_reg[11]_2 ;
- output \axi_rdata_reg[12] ;
- output \axi_rdata_reg[12]_0 ;
- output \axi_rdata_reg[12]_1 ;
- output \axi_rdata_reg[12]_2 ;
- output \axi_rdata_reg[13] ;
- output \axi_rdata_reg[13]_0 ;
- output \axi_rdata_reg[13]_1 ;
- output \axi_rdata_reg[13]_2 ;
- output \axi_rdata_reg[14] ;
- output \axi_rdata_reg[14]_0 ;
- output \axi_rdata_reg[14]_1 ;
- output \axi_rdata_reg[14]_2 ;
- output \axi_rdata_reg[15] ;
- output \axi_rdata_reg[15]_0 ;
- output \axi_rdata_reg[15]_1 ;
- output \axi_rdata_reg[15]_2 ;
- output \axi_rdata_reg[16] ;
- output \axi_rdata_reg[16]_0 ;
- output \axi_rdata_reg[16]_1 ;
- output \axi_rdata_reg[16]_2 ;
- output \axi_rdata_reg[17] ;
- output \axi_rdata_reg[17]_0 ;
- output \axi_rdata_reg[17]_1 ;
- output \axi_rdata_reg[17]_2 ;
- output \axi_rdata_reg[18] ;
- output \axi_rdata_reg[18]_0 ;
- output \axi_rdata_reg[18]_1 ;
- output \axi_rdata_reg[18]_2 ;
- output \axi_rdata_reg[19] ;
- output \axi_rdata_reg[19]_0 ;
- output \axi_rdata_reg[19]_1 ;
- output \axi_rdata_reg[19]_2 ;
- output \axi_rdata_reg[20] ;
- output \axi_rdata_reg[20]_0 ;
- output \axi_rdata_reg[20]_1 ;
- output \axi_rdata_reg[20]_2 ;
- output \axi_rdata_reg[20]_3 ;
- output \axi_rdata_reg[21] ;
- output \axi_rdata_reg[21]_0 ;
- output \axi_rdata_reg[21]_1 ;
- output \axi_rdata_reg[21]_2 ;
- output \axi_rdata_reg[21]_3 ;
- output \axi_rdata_reg[22] ;
- output \axi_rdata_reg[22]_0 ;
- output \axi_rdata_reg[22]_1 ;
- output \axi_rdata_reg[22]_2 ;
- output \axi_rdata_reg[22]_3 ;
- output \axi_rdata_reg[23] ;
- output \axi_rdata_reg[23]_0 ;
- output \axi_rdata_reg[23]_1 ;
- output \axi_rdata_reg[23]_2 ;
- output \axi_rdata_reg[23]_3 ;
- output [19:0]\s_datao_fmc1[0] ;
- output intr_o;
- output intr_led_o;
- output [31:0]\axi_rdata_reg[31] ;
- output [3:0]\axi_rdata_reg[3]_4 ;
- inout [1:0]FMC1_LA_P_b;
- inout [1:0]FMC1_LA_N_b;
- input [21:0]\FMC1_LA_P_b[32] ;
- input [21:0]\FMC1_LA_N_b[32] ;
- input [3:0]D;
- input s00_axi_aclk;
- input s00_axi_aresetn;
- input [2:0]\data_rw_o_reg[11][7] ;
- input \axi_araddr_reg[3]_rep__3 ;
- input \axi_araddr_reg[2]_rep__3 ;
- input \axi_araddr_reg[4]_rep__1 ;
- input \axi_araddr_reg[4]_rep__0 ;
- input \axi_araddr_reg[3]_rep__2 ;
- input \axi_araddr_reg[2]_rep__2 ;
- input \axi_araddr_reg[3]_rep__1 ;
- input \axi_araddr_reg[2]_rep__1 ;
- input \axi_araddr_reg[4]_rep ;
- input \axi_araddr_reg[3]_rep__0 ;
- input \axi_araddr_reg[2]_rep__0 ;
- input \axi_araddr_reg[3]_rep ;
- input \axi_araddr_reg[2]_rep ;
- input [2:0]\axi_araddr_reg[4] ;
- input fmc2_intr;
- input fmc2_intr_led;
- input [11:0]\data_rw_o_reg[19][11] ;
- input [0:0]CO;
- input [11:0]\data_rw_o_reg[18][11] ;
- input [0:0]\data_rw_o_reg[18][11]_0 ;
- input [11:0]\data_rw_o_reg[17][11] ;
- input [0:0]\data_rw_o_reg[17][11]_0 ;
- input [11:0]\data_rw_o_reg[16][11] ;
- input [0:0]\data_rw_o_reg[16][11]_0 ;
- input [11:0]\data_rw_o_reg[20][11] ;
- input [0:0]\data_rw_o_reg[20][11]_0 ;
- input [11:0]\data_rw_o_reg[21][11] ;
- input [0:0]\data_rw_o_reg[21][11]_0 ;
- input [11:0]\data_rw_o_reg[22][11] ;
- input [0:0]\data_rw_o_reg[22][11]_0 ;
- input [11:0]\data_rw_o_reg[23][11] ;
- input [0:0]\data_rw_o_reg[23][11]_0 ;
- input [11:0]\data_rw_o_reg[24][11] ;
- input [11:0]\data_rw_o_reg[25][11] ;
- input [11:0]\data_rw_o_reg[26][11] ;
- input [11:0]\data_rw_o_reg[27][11] ;
- input [11:0]\data_rw_o_reg[28][11] ;
- input [11:0]\data_rw_o_reg[29][11] ;
- input [11:0]\data_rw_o_reg[30][11] ;
- input [11:0]\data_rw_o_reg[31][11] ;
- input [11:0]\data_rw_o_reg[32][11] ;
- input [11:0]\data_rw_o_reg[33][11] ;
- input [11:0]\data_rw_o_reg[34][11] ;
- input [11:0]\data_rw_o_reg[35][11] ;
- input \data_rw_o_reg[10][7] ;
- input \data_rw_o_reg[10][6] ;
- input \data_rw_o_reg[10][5] ;
- input \data_rw_o_reg[10][4] ;
-
- wire [0:0]CO;
- wire [3:0]D;
- wire [1:0]FMC1_LA_N_b;
- wire [7:0]\FMC1_LA_N_b[27] ;
- wire [21:0]\FMC1_LA_N_b[32] ;
- wire [1:0]FMC1_LA_P_b;
- wire [7:0]\FMC1_LA_P_b[27] ;
- wire [21:0]\FMC1_LA_P_b[32] ;
- wire [11:0]Q;
- wire \axi_araddr_reg[2]_rep ;
- wire \axi_araddr_reg[2]_rep__0 ;
- wire \axi_araddr_reg[2]_rep__1 ;
- wire \axi_araddr_reg[2]_rep__2 ;
- wire \axi_araddr_reg[2]_rep__3 ;
- wire \axi_araddr_reg[3]_rep ;
- wire \axi_araddr_reg[3]_rep__0 ;
- wire \axi_araddr_reg[3]_rep__1 ;
- wire \axi_araddr_reg[3]_rep__2 ;
- wire \axi_araddr_reg[3]_rep__3 ;
- wire [2:0]\axi_araddr_reg[4] ;
- wire \axi_araddr_reg[4]_rep ;
- wire \axi_araddr_reg[4]_rep__0 ;
- wire \axi_araddr_reg[4]_rep__1 ;
- wire \axi_rdata[0]_i_42_n_0 ;
- wire \axi_rdata[0]_i_43_n_0 ;
- wire \axi_rdata[10]_i_40_n_0 ;
- wire \axi_rdata[10]_i_41_n_0 ;
- wire \axi_rdata[11]_i_40_n_0 ;
- wire \axi_rdata[11]_i_41_n_0 ;
- wire \axi_rdata[12]_i_40_n_0 ;
- wire \axi_rdata[12]_i_41_n_0 ;
- wire \axi_rdata[13]_i_40_n_0 ;
- wire \axi_rdata[13]_i_41_n_0 ;
- wire \axi_rdata[14]_i_40_n_0 ;
- wire \axi_rdata[14]_i_41_n_0 ;
- wire \axi_rdata[15]_i_40_n_0 ;
- wire \axi_rdata[15]_i_41_n_0 ;
- wire \axi_rdata[16]_i_40_n_0 ;
- wire \axi_rdata[16]_i_41_n_0 ;
- wire \axi_rdata[17]_i_40_n_0 ;
- wire \axi_rdata[17]_i_41_n_0 ;
- wire \axi_rdata[18]_i_40_n_0 ;
- wire \axi_rdata[18]_i_41_n_0 ;
- wire \axi_rdata[19]_i_40_n_0 ;
- wire \axi_rdata[19]_i_41_n_0 ;
- wire \axi_rdata[1]_i_42_n_0 ;
- wire \axi_rdata[1]_i_43_n_0 ;
- wire \axi_rdata[2]_i_42_n_0 ;
- wire \axi_rdata[2]_i_43_n_0 ;
- wire \axi_rdata[3]_i_42_n_0 ;
- wire \axi_rdata[3]_i_43_n_0 ;
- wire \axi_rdata[4]_i_42_n_0 ;
- wire \axi_rdata[4]_i_43_n_0 ;
- wire \axi_rdata[5]_i_42_n_0 ;
- wire \axi_rdata[5]_i_43_n_0 ;
- wire \axi_rdata[6]_i_42_n_0 ;
- wire \axi_rdata[6]_i_43_n_0 ;
- wire \axi_rdata[7]_i_42_n_0 ;
- wire \axi_rdata[7]_i_43_n_0 ;
- wire \axi_rdata[8]_i_40_n_0 ;
- wire \axi_rdata[8]_i_41_n_0 ;
- wire \axi_rdata[9]_i_40_n_0 ;
- wire \axi_rdata[9]_i_41_n_0 ;
- wire \axi_rdata_reg[0] ;
- wire \axi_rdata_reg[0]_0 ;
- wire \axi_rdata_reg[0]_1 ;
- wire \axi_rdata_reg[0]_2 ;
- wire \axi_rdata_reg[0]_3 ;
- wire \axi_rdata_reg[10] ;
- wire \axi_rdata_reg[10]_0 ;
- wire \axi_rdata_reg[10]_1 ;
- wire \axi_rdata_reg[10]_2 ;
- wire \axi_rdata_reg[11] ;
- wire \axi_rdata_reg[11]_0 ;
- wire \axi_rdata_reg[11]_1 ;
- wire \axi_rdata_reg[11]_2 ;
- wire \axi_rdata_reg[12] ;
- wire \axi_rdata_reg[12]_0 ;
- wire \axi_rdata_reg[12]_1 ;
- wire \axi_rdata_reg[12]_2 ;
- wire \axi_rdata_reg[13] ;
- wire \axi_rdata_reg[13]_0 ;
- wire \axi_rdata_reg[13]_1 ;
- wire \axi_rdata_reg[13]_2 ;
- wire \axi_rdata_reg[14] ;
- wire \axi_rdata_reg[14]_0 ;
- wire \axi_rdata_reg[14]_1 ;
- wire \axi_rdata_reg[14]_2 ;
- wire \axi_rdata_reg[15] ;
- wire \axi_rdata_reg[15]_0 ;
- wire \axi_rdata_reg[15]_1 ;
- wire \axi_rdata_reg[15]_2 ;
- wire \axi_rdata_reg[16] ;
- wire \axi_rdata_reg[16]_0 ;
- wire \axi_rdata_reg[16]_1 ;
- wire \axi_rdata_reg[16]_2 ;
- wire \axi_rdata_reg[17] ;
- wire \axi_rdata_reg[17]_0 ;
- wire \axi_rdata_reg[17]_1 ;
- wire \axi_rdata_reg[17]_2 ;
- wire \axi_rdata_reg[18] ;
- wire \axi_rdata_reg[18]_0 ;
- wire \axi_rdata_reg[18]_1 ;
- wire \axi_rdata_reg[18]_2 ;
- wire \axi_rdata_reg[19] ;
- wire \axi_rdata_reg[19]_0 ;
- wire \axi_rdata_reg[19]_1 ;
- wire \axi_rdata_reg[19]_2 ;
- wire \axi_rdata_reg[1] ;
- wire \axi_rdata_reg[1]_0 ;
- wire \axi_rdata_reg[1]_1 ;
- wire \axi_rdata_reg[1]_2 ;
- wire \axi_rdata_reg[1]_3 ;
- wire \axi_rdata_reg[20] ;
- wire \axi_rdata_reg[20]_0 ;
- wire \axi_rdata_reg[20]_1 ;
- wire \axi_rdata_reg[20]_2 ;
- wire \axi_rdata_reg[20]_3 ;
- wire \axi_rdata_reg[21] ;
- wire \axi_rdata_reg[21]_0 ;
- wire \axi_rdata_reg[21]_1 ;
- wire \axi_rdata_reg[21]_2 ;
- wire \axi_rdata_reg[21]_3 ;
- wire \axi_rdata_reg[22] ;
- wire \axi_rdata_reg[22]_0 ;
- wire \axi_rdata_reg[22]_1 ;
- wire \axi_rdata_reg[22]_2 ;
- wire \axi_rdata_reg[22]_3 ;
- wire \axi_rdata_reg[23] ;
- wire \axi_rdata_reg[23]_0 ;
- wire \axi_rdata_reg[23]_1 ;
- wire \axi_rdata_reg[23]_2 ;
- wire \axi_rdata_reg[23]_3 ;
- wire \axi_rdata_reg[2] ;
- wire \axi_rdata_reg[2]_0 ;
- wire \axi_rdata_reg[2]_1 ;
- wire \axi_rdata_reg[2]_2 ;
- wire \axi_rdata_reg[2]_3 ;
- wire [31:0]\axi_rdata_reg[31] ;
- wire \axi_rdata_reg[3] ;
- wire \axi_rdata_reg[3]_0 ;
- wire \axi_rdata_reg[3]_1 ;
- wire \axi_rdata_reg[3]_2 ;
- wire \axi_rdata_reg[3]_3 ;
- wire [3:0]\axi_rdata_reg[3]_4 ;
- wire \axi_rdata_reg[4] ;
- wire \axi_rdata_reg[4]_0 ;
- wire \axi_rdata_reg[4]_1 ;
- wire \axi_rdata_reg[4]_2 ;
- wire \axi_rdata_reg[4]_3 ;
- wire \axi_rdata_reg[5] ;
- wire \axi_rdata_reg[5]_0 ;
- wire \axi_rdata_reg[5]_1 ;
- wire \axi_rdata_reg[5]_2 ;
- wire \axi_rdata_reg[5]_3 ;
- wire \axi_rdata_reg[6] ;
- wire \axi_rdata_reg[6]_0 ;
- wire \axi_rdata_reg[6]_1 ;
- wire \axi_rdata_reg[6]_2 ;
- wire \axi_rdata_reg[6]_3 ;
- wire \axi_rdata_reg[7] ;
- wire \axi_rdata_reg[7]_0 ;
- wire \axi_rdata_reg[7]_1 ;
- wire \axi_rdata_reg[7]_2 ;
- wire \axi_rdata_reg[7]_3 ;
- wire \axi_rdata_reg[8] ;
- wire \axi_rdata_reg[8]_0 ;
- wire \axi_rdata_reg[8]_1 ;
- wire \axi_rdata_reg[8]_2 ;
- wire \axi_rdata_reg[9] ;
- wire \axi_rdata_reg[9]_0 ;
- wire \axi_rdata_reg[9]_1 ;
- wire \axi_rdata_reg[9]_2 ;
- wire \cmp_lengthCounter/RSTP ;
- wire \cmp_lengthCounter/RSTP_1 ;
- wire \cmp_lengthCounter/RSTP_11 ;
- wire \cmp_lengthCounter/RSTP_13 ;
- wire \cmp_lengthCounter/RSTP_15 ;
- wire \cmp_lengthCounter/RSTP_17 ;
- wire \cmp_lengthCounter/RSTP_19 ;
- wire \cmp_lengthCounter/RSTP_21 ;
- wire \cmp_lengthCounter/RSTP_23 ;
- wire \cmp_lengthCounter/RSTP_25 ;
- wire \cmp_lengthCounter/RSTP_27 ;
- wire \cmp_lengthCounter/RSTP_29 ;
- wire \cmp_lengthCounter/RSTP_3 ;
- wire \cmp_lengthCounter/RSTP_31 ;
- wire \cmp_lengthCounter/RSTP_33 ;
- wire \cmp_lengthCounter/RSTP_35 ;
- wire \cmp_lengthCounter/RSTP_37 ;
- wire \cmp_lengthCounter/RSTP_5 ;
- wire \cmp_lengthCounter/RSTP_7 ;
- wire \cmp_lengthCounter/RSTP_9 ;
- wire [4:0]\cmp_pulseSync/s_debounce ;
- wire [4:0]\cmp_pulseSync/s_debounce_0 ;
- wire [4:0]\cmp_pulseSync/s_debounce_10 ;
- wire [4:0]\cmp_pulseSync/s_debounce_12 ;
- wire [4:0]\cmp_pulseSync/s_debounce_14 ;
- wire [4:0]\cmp_pulseSync/s_debounce_16 ;
- wire [4:0]\cmp_pulseSync/s_debounce_18 ;
- wire [4:0]\cmp_pulseSync/s_debounce_2 ;
- wire [4:0]\cmp_pulseSync/s_debounce_20 ;
- wire [4:0]\cmp_pulseSync/s_debounce_22 ;
- wire [4:0]\cmp_pulseSync/s_debounce_24 ;
- wire [4:0]\cmp_pulseSync/s_debounce_26 ;
- wire [4:0]\cmp_pulseSync/s_debounce_28 ;
- wire [4:0]\cmp_pulseSync/s_debounce_30 ;
- wire [4:0]\cmp_pulseSync/s_debounce_32 ;
- wire [4:0]\cmp_pulseSync/s_debounce_34 ;
- wire [4:0]\cmp_pulseSync/s_debounce_36 ;
- wire [4:0]\cmp_pulseSync/s_debounce_38 ;
- wire [4:0]\cmp_pulseSync/s_debounce_39 ;
- wire [4:0]\cmp_pulseSync/s_debounce_4 ;
- wire [4:0]\cmp_pulseSync/s_debounce_40 ;
- wire [4:0]\cmp_pulseSync/s_debounce_41 ;
- wire [4:0]\cmp_pulseSync/s_debounce_42 ;
- wire [4:0]\cmp_pulseSync/s_debounce_43 ;
- wire [4:0]\cmp_pulseSync/s_debounce_44 ;
- wire [4:0]\cmp_pulseSync/s_debounce_45 ;
- wire [4:0]\cmp_pulseSync/s_debounce_6 ;
- wire [4:0]\cmp_pulseSync/s_debounce_8 ;
- wire \data_rw_o_reg[10][4] ;
- wire \data_rw_o_reg[10][5] ;
- wire \data_rw_o_reg[10][6] ;
- wire \data_rw_o_reg[10][7] ;
- wire [2:0]\data_rw_o_reg[11][7] ;
- wire [11:0]\data_rw_o_reg[16][11] ;
- wire [0:0]\data_rw_o_reg[16][11]_0 ;
- wire [11:0]\data_rw_o_reg[17][11] ;
- wire [0:0]\data_rw_o_reg[17][11]_0 ;
- wire [11:0]\data_rw_o_reg[18][11] ;
- wire [0:0]\data_rw_o_reg[18][11]_0 ;
- wire [11:0]\data_rw_o_reg[19][11] ;
- wire [11:0]\data_rw_o_reg[20][11] ;
- wire [0:0]\data_rw_o_reg[20][11]_0 ;
- wire [11:0]\data_rw_o_reg[21][11] ;
- wire [0:0]\data_rw_o_reg[21][11]_0 ;
- wire [11:0]\data_rw_o_reg[22][11] ;
- wire [0:0]\data_rw_o_reg[22][11]_0 ;
- wire [11:0]\data_rw_o_reg[23][11] ;
- wire [0:0]\data_rw_o_reg[23][11]_0 ;
- wire [11:0]\data_rw_o_reg[24][11] ;
- wire [11:0]\data_rw_o_reg[25][11] ;
- wire [11:0]\data_rw_o_reg[26][11] ;
- wire [11:0]\data_rw_o_reg[27][11] ;
- wire [11:0]\data_rw_o_reg[28][11] ;
- wire [11:0]\data_rw_o_reg[29][11] ;
- wire [11:0]\data_rw_o_reg[30][11] ;
- wire [11:0]\data_rw_o_reg[31][11] ;
- wire [11:0]\data_rw_o_reg[32][11] ;
- wire [11:0]\data_rw_o_reg[33][11] ;
- wire [11:0]\data_rw_o_reg[34][11] ;
- wire [11:0]\data_rw_o_reg[35][11] ;
- wire fmc1_intr;
- wire fmc1_intr_led;
- wire fmc2_intr;
- wire fmc2_intr_led;
- wire \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2 ;
- wire \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_3 ;
- wire \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_4 ;
- wire \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_2 ;
- wire \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_3 ;
- wire \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_2 ;
- wire \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_3 ;
- wire \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_2 ;
- wire \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_3 ;
- wire \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_2 ;
- wire \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_3 ;
- wire \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_2 ;
- wire \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_3 ;
- wire \fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure_n_2 ;
- wire \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_3 ;
- wire \fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_3 ;
- wire \fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_3 ;
- wire \gen_spi.cmp_dac7716_spi_n_1 ;
- wire \gen_spi.cmp_dac7716_spi_n_2 ;
- wire intr_led_o;
- wire intr_o;
- wire intr_o0;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff2_i_1__0_n_0;
- wire s_buff2_i_1__10_n_0;
- wire s_buff2_i_1__11_n_0;
- wire s_buff2_i_1__12_n_0;
- wire s_buff2_i_1__13_n_0;
- wire s_buff2_i_1__14_n_0;
- wire s_buff2_i_1__15_n_0;
- wire s_buff2_i_1__16_n_0;
- wire s_buff2_i_1__17_n_0;
- wire s_buff2_i_1__18_n_0;
- wire s_buff2_i_1__19_n_0;
- wire s_buff2_i_1__1_n_0;
- wire s_buff2_i_1__20_n_0;
- wire s_buff2_i_1__21_n_0;
- wire s_buff2_i_1__22_n_0;
- wire s_buff2_i_1__23_n_0;
- wire s_buff2_i_1__24_n_0;
- wire s_buff2_i_1__25_n_0;
- wire s_buff2_i_1__26_n_0;
- wire s_buff2_i_1__2_n_0;
- wire s_buff2_i_1__3_n_0;
- wire s_buff2_i_1__4_n_0;
- wire s_buff2_i_1__5_n_0;
- wire s_buff2_i_1__6_n_0;
- wire s_buff2_i_1__7_n_0;
- wire s_buff2_i_1__8_n_0;
- wire s_buff2_i_1__9_n_0;
- wire s_buff2_i_1_n_0;
- wire [23:0]\s_cmp_lengths[0]_0 ;
- wire [23:0]\s_cmp_lengths[10]_10 ;
- wire [23:0]\s_cmp_lengths[11]_11 ;
- wire [23:0]\s_cmp_lengths[12]_12 ;
- wire [23:0]\s_cmp_lengths[13]_13 ;
- wire [23:0]\s_cmp_lengths[14]_14 ;
- wire [23:0]\s_cmp_lengths[15]_15 ;
- wire [23:0]\s_cmp_lengths[16]_16 ;
- wire [23:0]\s_cmp_lengths[17]_17 ;
- wire [23:0]\s_cmp_lengths[18]_18 ;
- wire [23:0]\s_cmp_lengths[19]_19 ;
- wire [23:0]\s_cmp_lengths[1]_1 ;
- wire [23:0]\s_cmp_lengths[2]_2 ;
- wire [23:0]\s_cmp_lengths[3]_3 ;
- wire [23:0]\s_cmp_lengths[4]_4 ;
- wire [23:0]\s_cmp_lengths[5]_5 ;
- wire [23:0]\s_cmp_lengths[6]_6 ;
- wire [23:0]\s_cmp_lengths[7]_7 ;
- wire [23:0]\s_cmp_lengths[8]_8 ;
- wire [23:0]\s_cmp_lengths[9]_9 ;
- wire s_comparators_i_0;
- wire s_comparators_i_1;
- wire s_comparators_i_10;
- wire s_comparators_i_11;
- wire s_comparators_i_12;
- wire s_comparators_i_13;
- wire s_comparators_i_14;
- wire s_comparators_i_15;
- wire s_comparators_i_16;
- wire s_comparators_i_17;
- wire s_comparators_i_18;
- wire s_comparators_i_19;
- wire s_comparators_i_2;
- wire s_comparators_i_3;
- wire s_comparators_i_4;
- wire s_comparators_i_5;
- wire s_comparators_i_6;
- wire s_comparators_i_7;
- wire s_comparators_i_8;
- wire s_comparators_i_9;
- wire [11:0]s_count_reg;
- wire [19:0]\s_datao_fmc1[0] ;
- wire [23:0]\s_datao_fmc1[48] ;
- wire [23:0]\s_datao_fmc1[49] ;
- wire [7:0]\s_datao_fmc1[4] ;
- wire [23:0]\s_datao_fmc1[50] ;
- wire [23:0]\s_datao_fmc1[51] ;
- wire [23:0]\s_datao_fmc1[52] ;
- wire [23:0]\s_datao_fmc1[53] ;
- wire [23:0]\s_datao_fmc1[54] ;
- wire [23:0]\s_datao_fmc1[55] ;
- wire [23:0]\s_datao_fmc1[56] ;
- wire [23:0]\s_datao_fmc1[57] ;
- wire [23:0]\s_datao_fmc1[58] ;
- wire [23:0]\s_datao_fmc1[59] ;
- wire [7:0]\s_datao_fmc1[5] ;
- wire [23:0]\s_datao_fmc1[60] ;
- wire [23:0]\s_datao_fmc1[61] ;
- wire [23:0]\s_datao_fmc1[62] ;
- wire [23:0]\s_datao_fmc1[63] ;
- wire [23:0]\s_datao_fmc1[64] ;
- wire [23:0]\s_datao_fmc1[65] ;
- wire [23:0]\s_datao_fmc1[66] ;
- wire [23:0]\s_datao_fmc1[67] ;
- wire [7:0]\s_datao_fmc1[6] ;
- wire [7:4]s_diffouts_o;
- wire s_spi_cs_n;
- wire s_spi_mosi;
- wire s_spi_sclk;
- wire s_start;
- wire s_start_i_1_n_0;
- wire [11:0]\s_tx_data_reg[111] ;
- wire [11:0]\s_tx_data_reg[15] ;
- wire [11:0]\s_tx_data_reg[15]_0 ;
- wire [11:0]\s_tx_data_reg[39] ;
- wire [11:0]\s_tx_data_reg[39]_0 ;
- wire [11:0]\s_tx_data_reg[39]_1 ;
- wire [11:0]\s_tx_data_reg[39]_2 ;
- wire spi_sdo_i;
- wire [19:0]v_cmp;
- wire [19:0]v_cmpled;
- wire [7:4]v_dout;
- wire [3:0]v_fbd;
- wire [7:0]v_outleds;
- wire \NLW_gen_spi.cmp_spi_cs_n_iobuf_O_UNCONNECTED ;
- wire \NLW_gen_spi.cmp_spi_mosi_iobuf_O_UNCONNECTED ;
- wire \NLW_gen_spi.cmp_spi_sclk_iobuf_O_UNCONNECTED ;
-
- LUT1 #(
- .INIT(2'h1))
- axi_awready_i_1
- (.I0(s00_axi_aresetn),
- .O(rst_i));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_15
- (.I0(\s_datao_fmc1[51] [0]),
- .I1(\s_datao_fmc1[50] [0]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[49] [0]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[48] [0]),
- .O(\axi_rdata_reg[0]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_16
- (.I0(\s_datao_fmc1[55] [0]),
- .I1(\s_datao_fmc1[54] [0]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[53] [0]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[52] [0]),
- .O(\axi_rdata_reg[0]_1 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_40
- (.I0(\s_datao_fmc1[67] [0]),
- .I1(\s_datao_fmc1[66] [0]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[65] [0]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[64] [0]),
- .O(\axi_rdata_reg[0]_3 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_42
- (.I0(\s_datao_fmc1[59] [0]),
- .I1(\s_datao_fmc1[58] [0]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[57] [0]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[56] [0]),
- .O(\axi_rdata[0]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_43
- (.I0(\s_datao_fmc1[63] [0]),
- .I1(\s_datao_fmc1[62] [0]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[61] [0]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[60] [0]),
- .O(\axi_rdata[0]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_15
- (.I0(\s_datao_fmc1[51] [10]),
- .I1(\s_datao_fmc1[50] [10]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[49] [10]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[48] [10]),
- .O(\axi_rdata_reg[10] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_16
- (.I0(\s_datao_fmc1[55] [10]),
- .I1(\s_datao_fmc1[54] [10]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[53] [10]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[52] [10]),
- .O(\axi_rdata_reg[10]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_38
- (.I0(\s_datao_fmc1[67] [10]),
- .I1(\s_datao_fmc1[66] [10]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[65] [10]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[64] [10]),
- .O(\axi_rdata_reg[10]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_40
- (.I0(\s_datao_fmc1[59] [10]),
- .I1(\s_datao_fmc1[58] [10]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[57] [10]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[56] [10]),
- .O(\axi_rdata[10]_i_40_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_41
- (.I0(\s_datao_fmc1[63] [10]),
- .I1(\s_datao_fmc1[62] [10]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[61] [10]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[60] [10]),
- .O(\axi_rdata[10]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_15
- (.I0(\s_datao_fmc1[51] [11]),
- .I1(\s_datao_fmc1[50] [11]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[49] [11]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[48] [11]),
- .O(\axi_rdata_reg[11] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_16
- (.I0(\s_datao_fmc1[55] [11]),
- .I1(\s_datao_fmc1[54] [11]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[53] [11]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[52] [11]),
- .O(\axi_rdata_reg[11]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_38
- (.I0(\s_datao_fmc1[67] [11]),
- .I1(\s_datao_fmc1[66] [11]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[65] [11]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[64] [11]),
- .O(\axi_rdata_reg[11]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_40
- (.I0(\s_datao_fmc1[59] [11]),
- .I1(\s_datao_fmc1[58] [11]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[57] [11]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[56] [11]),
- .O(\axi_rdata[11]_i_40_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_41
- (.I0(\s_datao_fmc1[63] [11]),
- .I1(\s_datao_fmc1[62] [11]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[61] [11]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[60] [11]),
- .O(\axi_rdata[11]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_15
- (.I0(\s_datao_fmc1[51] [12]),
- .I1(\s_datao_fmc1[50] [12]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[49] [12]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[48] [12]),
- .O(\axi_rdata_reg[12] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_16
- (.I0(\s_datao_fmc1[55] [12]),
- .I1(\s_datao_fmc1[54] [12]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[53] [12]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[52] [12]),
- .O(\axi_rdata_reg[12]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_38
- (.I0(\s_datao_fmc1[67] [12]),
- .I1(\s_datao_fmc1[66] [12]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[65] [12]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[64] [12]),
- .O(\axi_rdata_reg[12]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_40
- (.I0(\s_datao_fmc1[59] [12]),
- .I1(\s_datao_fmc1[58] [12]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[57] [12]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[56] [12]),
- .O(\axi_rdata[12]_i_40_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_41
- (.I0(\s_datao_fmc1[63] [12]),
- .I1(\s_datao_fmc1[62] [12]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[61] [12]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[60] [12]),
- .O(\axi_rdata[12]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_15
- (.I0(\s_datao_fmc1[51] [13]),
- .I1(\s_datao_fmc1[50] [13]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[49] [13]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[48] [13]),
- .O(\axi_rdata_reg[13] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_16
- (.I0(\s_datao_fmc1[55] [13]),
- .I1(\s_datao_fmc1[54] [13]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[53] [13]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[52] [13]),
- .O(\axi_rdata_reg[13]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_38
- (.I0(\s_datao_fmc1[67] [13]),
- .I1(\s_datao_fmc1[66] [13]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[65] [13]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[64] [13]),
- .O(\axi_rdata_reg[13]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_40
- (.I0(\s_datao_fmc1[59] [13]),
- .I1(\s_datao_fmc1[58] [13]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[57] [13]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[56] [13]),
- .O(\axi_rdata[13]_i_40_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_41
- (.I0(\s_datao_fmc1[63] [13]),
- .I1(\s_datao_fmc1[62] [13]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[61] [13]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[60] [13]),
- .O(\axi_rdata[13]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_15
- (.I0(\s_datao_fmc1[51] [14]),
- .I1(\s_datao_fmc1[50] [14]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[49] [14]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[48] [14]),
- .O(\axi_rdata_reg[14] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_16
- (.I0(\s_datao_fmc1[55] [14]),
- .I1(\s_datao_fmc1[54] [14]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[53] [14]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[52] [14]),
- .O(\axi_rdata_reg[14]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_38
- (.I0(\s_datao_fmc1[67] [14]),
- .I1(\s_datao_fmc1[66] [14]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[65] [14]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[64] [14]),
- .O(\axi_rdata_reg[14]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_40
- (.I0(\s_datao_fmc1[59] [14]),
- .I1(\s_datao_fmc1[58] [14]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[57] [14]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[56] [14]),
- .O(\axi_rdata[14]_i_40_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_41
- (.I0(\s_datao_fmc1[63] [14]),
- .I1(\s_datao_fmc1[62] [14]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[61] [14]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[60] [14]),
- .O(\axi_rdata[14]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_15
- (.I0(\s_datao_fmc1[51] [15]),
- .I1(\s_datao_fmc1[50] [15]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[49] [15]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[48] [15]),
- .O(\axi_rdata_reg[15] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_16
- (.I0(\s_datao_fmc1[55] [15]),
- .I1(\s_datao_fmc1[54] [15]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[53] [15]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[52] [15]),
- .O(\axi_rdata_reg[15]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_38
- (.I0(\s_datao_fmc1[67] [15]),
- .I1(\s_datao_fmc1[66] [15]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[65] [15]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[64] [15]),
- .O(\axi_rdata_reg[15]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_40
- (.I0(\s_datao_fmc1[59] [15]),
- .I1(\s_datao_fmc1[58] [15]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[57] [15]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[56] [15]),
- .O(\axi_rdata[15]_i_40_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_41
- (.I0(\s_datao_fmc1[63] [15]),
- .I1(\s_datao_fmc1[62] [15]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[61] [15]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[60] [15]),
- .O(\axi_rdata[15]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_15
- (.I0(\s_datao_fmc1[51] [16]),
- .I1(\s_datao_fmc1[50] [16]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[49] [16]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[48] [16]),
- .O(\axi_rdata_reg[16] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_16
- (.I0(\s_datao_fmc1[55] [16]),
- .I1(\s_datao_fmc1[54] [16]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[53] [16]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[52] [16]),
- .O(\axi_rdata_reg[16]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_38
- (.I0(\s_datao_fmc1[67] [16]),
- .I1(\s_datao_fmc1[66] [16]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[65] [16]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[64] [16]),
- .O(\axi_rdata_reg[16]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_40
- (.I0(\s_datao_fmc1[59] [16]),
- .I1(\s_datao_fmc1[58] [16]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[57] [16]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[56] [16]),
- .O(\axi_rdata[16]_i_40_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_41
- (.I0(\s_datao_fmc1[63] [16]),
- .I1(\s_datao_fmc1[62] [16]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[61] [16]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[60] [16]),
- .O(\axi_rdata[16]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_15
- (.I0(\s_datao_fmc1[51] [17]),
- .I1(\s_datao_fmc1[50] [17]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[49] [17]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[48] [17]),
- .O(\axi_rdata_reg[17] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_16
- (.I0(\s_datao_fmc1[55] [17]),
- .I1(\s_datao_fmc1[54] [17]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[53] [17]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[52] [17]),
- .O(\axi_rdata_reg[17]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_38
- (.I0(\s_datao_fmc1[67] [17]),
- .I1(\s_datao_fmc1[66] [17]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[65] [17]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[64] [17]),
- .O(\axi_rdata_reg[17]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_40
- (.I0(\s_datao_fmc1[59] [17]),
- .I1(\s_datao_fmc1[58] [17]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[57] [17]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[56] [17]),
- .O(\axi_rdata[17]_i_40_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_41
- (.I0(\s_datao_fmc1[63] [17]),
- .I1(\s_datao_fmc1[62] [17]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc1[61] [17]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc1[60] [17]),
- .O(\axi_rdata[17]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_15
- (.I0(\s_datao_fmc1[51] [18]),
- .I1(\s_datao_fmc1[50] [18]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[49] [18]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[48] [18]),
- .O(\axi_rdata_reg[18] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_16
- (.I0(\s_datao_fmc1[55] [18]),
- .I1(\s_datao_fmc1[54] [18]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[53] [18]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[52] [18]),
- .O(\axi_rdata_reg[18]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_38
- (.I0(\s_datao_fmc1[67] [18]),
- .I1(\s_datao_fmc1[66] [18]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[65] [18]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[64] [18]),
- .O(\axi_rdata_reg[18]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_40
- (.I0(\s_datao_fmc1[59] [18]),
- .I1(\s_datao_fmc1[58] [18]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[57] [18]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[56] [18]),
- .O(\axi_rdata[18]_i_40_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_41
- (.I0(\s_datao_fmc1[63] [18]),
- .I1(\s_datao_fmc1[62] [18]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[61] [18]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[60] [18]),
- .O(\axi_rdata[18]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_15
- (.I0(\s_datao_fmc1[51] [19]),
- .I1(\s_datao_fmc1[50] [19]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[49] [19]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[48] [19]),
- .O(\axi_rdata_reg[19] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_16
- (.I0(\s_datao_fmc1[55] [19]),
- .I1(\s_datao_fmc1[54] [19]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[53] [19]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[52] [19]),
- .O(\axi_rdata_reg[19]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_38
- (.I0(\s_datao_fmc1[67] [19]),
- .I1(\s_datao_fmc1[66] [19]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[65] [19]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[64] [19]),
- .O(\axi_rdata_reg[19]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_40
- (.I0(\s_datao_fmc1[59] [19]),
- .I1(\s_datao_fmc1[58] [19]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[57] [19]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[56] [19]),
- .O(\axi_rdata[19]_i_40_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_41
- (.I0(\s_datao_fmc1[63] [19]),
- .I1(\s_datao_fmc1[62] [19]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[61] [19]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[60] [19]),
- .O(\axi_rdata[19]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_15
- (.I0(\s_datao_fmc1[51] [1]),
- .I1(\s_datao_fmc1[50] [1]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[49] [1]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[48] [1]),
- .O(\axi_rdata_reg[1]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_16
- (.I0(\s_datao_fmc1[55] [1]),
- .I1(\s_datao_fmc1[54] [1]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[53] [1]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[52] [1]),
- .O(\axi_rdata_reg[1]_1 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_40
- (.I0(\s_datao_fmc1[67] [1]),
- .I1(\s_datao_fmc1[66] [1]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[65] [1]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[64] [1]),
- .O(\axi_rdata_reg[1]_3 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_42
- (.I0(\s_datao_fmc1[59] [1]),
- .I1(\s_datao_fmc1[58] [1]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[57] [1]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[56] [1]),
- .O(\axi_rdata[1]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_43
- (.I0(\s_datao_fmc1[63] [1]),
- .I1(\s_datao_fmc1[62] [1]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[61] [1]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[60] [1]),
- .O(\axi_rdata[1]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_18
- (.I0(\s_datao_fmc1[51] [20]),
- .I1(\s_datao_fmc1[50] [20]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[49] [20]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[48] [20]),
- .O(\axi_rdata_reg[20] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_19
- (.I0(\s_datao_fmc1[55] [20]),
- .I1(\s_datao_fmc1[54] [20]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[53] [20]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[52] [20]),
- .O(\axi_rdata_reg[20]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_28
- (.I0(\s_datao_fmc1[67] [20]),
- .I1(\s_datao_fmc1[66] [20]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[65] [20]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[64] [20]),
- .O(\axi_rdata_reg[20]_3 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_29
- (.I0(\s_datao_fmc1[63] [20]),
- .I1(\s_datao_fmc1[62] [20]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[61] [20]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[60] [20]),
- .O(\axi_rdata_reg[20]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_30
- (.I0(\s_datao_fmc1[59] [20]),
- .I1(\s_datao_fmc1[58] [20]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[57] [20]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[56] [20]),
- .O(\axi_rdata_reg[20]_1 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_18
- (.I0(\s_datao_fmc1[51] [21]),
- .I1(\s_datao_fmc1[50] [21]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[49] [21]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[48] [21]),
- .O(\axi_rdata_reg[21] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_19
- (.I0(\s_datao_fmc1[55] [21]),
- .I1(\s_datao_fmc1[54] [21]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[53] [21]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[52] [21]),
- .O(\axi_rdata_reg[21]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_28
- (.I0(\s_datao_fmc1[67] [21]),
- .I1(\s_datao_fmc1[66] [21]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[65] [21]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[64] [21]),
- .O(\axi_rdata_reg[21]_3 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_29
- (.I0(\s_datao_fmc1[63] [21]),
- .I1(\s_datao_fmc1[62] [21]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[61] [21]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[60] [21]),
- .O(\axi_rdata_reg[21]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_30
- (.I0(\s_datao_fmc1[59] [21]),
- .I1(\s_datao_fmc1[58] [21]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[57] [21]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[56] [21]),
- .O(\axi_rdata_reg[21]_1 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_18
- (.I0(\s_datao_fmc1[51] [22]),
- .I1(\s_datao_fmc1[50] [22]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[49] [22]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[48] [22]),
- .O(\axi_rdata_reg[22] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_19
- (.I0(\s_datao_fmc1[55] [22]),
- .I1(\s_datao_fmc1[54] [22]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[53] [22]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[52] [22]),
- .O(\axi_rdata_reg[22]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_28
- (.I0(\s_datao_fmc1[67] [22]),
- .I1(\s_datao_fmc1[66] [22]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[65] [22]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[64] [22]),
- .O(\axi_rdata_reg[22]_3 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_29
- (.I0(\s_datao_fmc1[63] [22]),
- .I1(\s_datao_fmc1[62] [22]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[61] [22]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[60] [22]),
- .O(\axi_rdata_reg[22]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_30
- (.I0(\s_datao_fmc1[59] [22]),
- .I1(\s_datao_fmc1[58] [22]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc1[57] [22]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc1[56] [22]),
- .O(\axi_rdata_reg[22]_1 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_19
- (.I0(\s_datao_fmc1[51] [23]),
- .I1(\s_datao_fmc1[50] [23]),
- .I2(\axi_araddr_reg[4] [1]),
- .I3(\s_datao_fmc1[49] [23]),
- .I4(\axi_araddr_reg[4] [0]),
- .I5(\s_datao_fmc1[48] [23]),
- .O(\axi_rdata_reg[23] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_20
- (.I0(\s_datao_fmc1[55] [23]),
- .I1(\s_datao_fmc1[54] [23]),
- .I2(\axi_araddr_reg[4] [1]),
- .I3(\s_datao_fmc1[53] [23]),
- .I4(\axi_araddr_reg[4] [0]),
- .I5(\s_datao_fmc1[52] [23]),
- .O(\axi_rdata_reg[23]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_29
- (.I0(\s_datao_fmc1[67] [23]),
- .I1(\s_datao_fmc1[66] [23]),
- .I2(\axi_araddr_reg[4] [1]),
- .I3(\s_datao_fmc1[65] [23]),
- .I4(\axi_araddr_reg[4] [0]),
- .I5(\s_datao_fmc1[64] [23]),
- .O(\axi_rdata_reg[23]_3 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_30
- (.I0(\s_datao_fmc1[63] [23]),
- .I1(\s_datao_fmc1[62] [23]),
- .I2(\axi_araddr_reg[4] [1]),
- .I3(\s_datao_fmc1[61] [23]),
- .I4(\axi_araddr_reg[4] [0]),
- .I5(\s_datao_fmc1[60] [23]),
- .O(\axi_rdata_reg[23]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_31
- (.I0(\s_datao_fmc1[59] [23]),
- .I1(\s_datao_fmc1[58] [23]),
- .I2(\axi_araddr_reg[4] [1]),
- .I3(\s_datao_fmc1[57] [23]),
- .I4(\axi_araddr_reg[4] [0]),
- .I5(\s_datao_fmc1[56] [23]),
- .O(\axi_rdata_reg[23]_1 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_15
- (.I0(\s_datao_fmc1[51] [2]),
- .I1(\s_datao_fmc1[50] [2]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[49] [2]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[48] [2]),
- .O(\axi_rdata_reg[2]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_16
- (.I0(\s_datao_fmc1[55] [2]),
- .I1(\s_datao_fmc1[54] [2]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[53] [2]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[52] [2]),
- .O(\axi_rdata_reg[2]_1 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_40
- (.I0(\s_datao_fmc1[67] [2]),
- .I1(\s_datao_fmc1[66] [2]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[65] [2]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[64] [2]),
- .O(\axi_rdata_reg[2]_3 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_42
- (.I0(\s_datao_fmc1[59] [2]),
- .I1(\s_datao_fmc1[58] [2]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[57] [2]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[56] [2]),
- .O(\axi_rdata[2]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_43
- (.I0(\s_datao_fmc1[63] [2]),
- .I1(\s_datao_fmc1[62] [2]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc1[61] [2]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc1[60] [2]),
- .O(\axi_rdata[2]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_15
- (.I0(\s_datao_fmc1[51] [3]),
- .I1(\s_datao_fmc1[50] [3]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[49] [3]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[48] [3]),
- .O(\axi_rdata_reg[3]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_16
- (.I0(\s_datao_fmc1[55] [3]),
- .I1(\s_datao_fmc1[54] [3]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[53] [3]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[52] [3]),
- .O(\axi_rdata_reg[3]_1 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_40
- (.I0(\s_datao_fmc1[67] [3]),
- .I1(\s_datao_fmc1[66] [3]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[65] [3]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[64] [3]),
- .O(\axi_rdata_reg[3]_3 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_42
- (.I0(\s_datao_fmc1[59] [3]),
- .I1(\s_datao_fmc1[58] [3]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[57] [3]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[56] [3]),
- .O(\axi_rdata[3]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_43
- (.I0(\s_datao_fmc1[63] [3]),
- .I1(\s_datao_fmc1[62] [3]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[61] [3]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[60] [3]),
- .O(\axi_rdata[3]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_15
- (.I0(\s_datao_fmc1[51] [4]),
- .I1(\s_datao_fmc1[50] [4]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[49] [4]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[48] [4]),
- .O(\axi_rdata_reg[4]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_16
- (.I0(\s_datao_fmc1[55] [4]),
- .I1(\s_datao_fmc1[54] [4]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[53] [4]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[52] [4]),
- .O(\axi_rdata_reg[4]_1 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_40
- (.I0(\s_datao_fmc1[67] [4]),
- .I1(\s_datao_fmc1[66] [4]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[65] [4]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[64] [4]),
- .O(\axi_rdata_reg[4]_3 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_42
- (.I0(\s_datao_fmc1[59] [4]),
- .I1(\s_datao_fmc1[58] [4]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[57] [4]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[56] [4]),
- .O(\axi_rdata[4]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_43
- (.I0(\s_datao_fmc1[63] [4]),
- .I1(\s_datao_fmc1[62] [4]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[61] [4]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[60] [4]),
- .O(\axi_rdata[4]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_15
- (.I0(\s_datao_fmc1[51] [5]),
- .I1(\s_datao_fmc1[50] [5]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[49] [5]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[48] [5]),
- .O(\axi_rdata_reg[5]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_16
- (.I0(\s_datao_fmc1[55] [5]),
- .I1(\s_datao_fmc1[54] [5]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[53] [5]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[52] [5]),
- .O(\axi_rdata_reg[5]_1 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_40
- (.I0(\s_datao_fmc1[67] [5]),
- .I1(\s_datao_fmc1[66] [5]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[65] [5]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[64] [5]),
- .O(\axi_rdata_reg[5]_3 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_42
- (.I0(\s_datao_fmc1[59] [5]),
- .I1(\s_datao_fmc1[58] [5]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[57] [5]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[56] [5]),
- .O(\axi_rdata[5]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_43
- (.I0(\s_datao_fmc1[63] [5]),
- .I1(\s_datao_fmc1[62] [5]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[61] [5]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[60] [5]),
- .O(\axi_rdata[5]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_15
- (.I0(\s_datao_fmc1[51] [6]),
- .I1(\s_datao_fmc1[50] [6]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[49] [6]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[48] [6]),
- .O(\axi_rdata_reg[6]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_16
- (.I0(\s_datao_fmc1[55] [6]),
- .I1(\s_datao_fmc1[54] [6]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[53] [6]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[52] [6]),
- .O(\axi_rdata_reg[6]_1 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_40
- (.I0(\s_datao_fmc1[67] [6]),
- .I1(\s_datao_fmc1[66] [6]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[65] [6]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[64] [6]),
- .O(\axi_rdata_reg[6]_3 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_42
- (.I0(\s_datao_fmc1[59] [6]),
- .I1(\s_datao_fmc1[58] [6]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[57] [6]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[56] [6]),
- .O(\axi_rdata[6]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_43
- (.I0(\s_datao_fmc1[63] [6]),
- .I1(\s_datao_fmc1[62] [6]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[61] [6]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[60] [6]),
- .O(\axi_rdata[6]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_15
- (.I0(\s_datao_fmc1[51] [7]),
- .I1(\s_datao_fmc1[50] [7]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[49] [7]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[48] [7]),
- .O(\axi_rdata_reg[7]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_16
- (.I0(\s_datao_fmc1[55] [7]),
- .I1(\s_datao_fmc1[54] [7]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[53] [7]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[52] [7]),
- .O(\axi_rdata_reg[7]_1 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_40
- (.I0(\s_datao_fmc1[67] [7]),
- .I1(\s_datao_fmc1[66] [7]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[65] [7]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[64] [7]),
- .O(\axi_rdata_reg[7]_3 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_42
- (.I0(\s_datao_fmc1[59] [7]),
- .I1(\s_datao_fmc1[58] [7]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[57] [7]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[56] [7]),
- .O(\axi_rdata[7]_i_42_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_43
- (.I0(\s_datao_fmc1[63] [7]),
- .I1(\s_datao_fmc1[62] [7]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc1[61] [7]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc1[60] [7]),
- .O(\axi_rdata[7]_i_43_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_15
- (.I0(\s_datao_fmc1[51] [8]),
- .I1(\s_datao_fmc1[50] [8]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[49] [8]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[48] [8]),
- .O(\axi_rdata_reg[8] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_16
- (.I0(\s_datao_fmc1[55] [8]),
- .I1(\s_datao_fmc1[54] [8]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[53] [8]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[52] [8]),
- .O(\axi_rdata_reg[8]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_38
- (.I0(\s_datao_fmc1[67] [8]),
- .I1(\s_datao_fmc1[66] [8]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[65] [8]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[64] [8]),
- .O(\axi_rdata_reg[8]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_40
- (.I0(\s_datao_fmc1[59] [8]),
- .I1(\s_datao_fmc1[58] [8]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[57] [8]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[56] [8]),
- .O(\axi_rdata[8]_i_40_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_41
- (.I0(\s_datao_fmc1[63] [8]),
- .I1(\s_datao_fmc1[62] [8]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[61] [8]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[60] [8]),
- .O(\axi_rdata[8]_i_41_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_15
- (.I0(\s_datao_fmc1[51] [9]),
- .I1(\s_datao_fmc1[50] [9]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[49] [9]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[48] [9]),
- .O(\axi_rdata_reg[9] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_16
- (.I0(\s_datao_fmc1[55] [9]),
- .I1(\s_datao_fmc1[54] [9]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[53] [9]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[52] [9]),
- .O(\axi_rdata_reg[9]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_38
- (.I0(\s_datao_fmc1[67] [9]),
- .I1(\s_datao_fmc1[66] [9]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[65] [9]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[64] [9]),
- .O(\axi_rdata_reg[9]_2 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_40
- (.I0(\s_datao_fmc1[59] [9]),
- .I1(\s_datao_fmc1[58] [9]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[57] [9]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[56] [9]),
- .O(\axi_rdata[9]_i_40_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_41
- (.I0(\s_datao_fmc1[63] [9]),
- .I1(\s_datao_fmc1[62] [9]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc1[61] [9]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc1[60] [9]),
- .O(\axi_rdata[9]_i_41_n_0 ));
- MUXF7 \axi_rdata_reg[0]_i_21
- (.I0(\axi_rdata[0]_i_42_n_0 ),
- .I1(\axi_rdata[0]_i_43_n_0 ),
- .O(\axi_rdata_reg[0]_2 ),
- .S(\axi_araddr_reg[4]_rep__1 ));
- MUXF7 \axi_rdata_reg[10]_i_21
- (.I0(\axi_rdata[10]_i_40_n_0 ),
- .I1(\axi_rdata[10]_i_41_n_0 ),
- .O(\axi_rdata_reg[10]_1 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[11]_i_21
- (.I0(\axi_rdata[11]_i_40_n_0 ),
- .I1(\axi_rdata[11]_i_41_n_0 ),
- .O(\axi_rdata_reg[11]_1 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[12]_i_21
- (.I0(\axi_rdata[12]_i_40_n_0 ),
- .I1(\axi_rdata[12]_i_41_n_0 ),
- .O(\axi_rdata_reg[12]_1 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[13]_i_21
- (.I0(\axi_rdata[13]_i_40_n_0 ),
- .I1(\axi_rdata[13]_i_41_n_0 ),
- .O(\axi_rdata_reg[13]_1 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[14]_i_21
- (.I0(\axi_rdata[14]_i_40_n_0 ),
- .I1(\axi_rdata[14]_i_41_n_0 ),
- .O(\axi_rdata_reg[14]_1 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[15]_i_21
- (.I0(\axi_rdata[15]_i_40_n_0 ),
- .I1(\axi_rdata[15]_i_41_n_0 ),
- .O(\axi_rdata_reg[15]_1 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[16]_i_21
- (.I0(\axi_rdata[16]_i_40_n_0 ),
- .I1(\axi_rdata[16]_i_41_n_0 ),
- .O(\axi_rdata_reg[16]_1 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[17]_i_21
- (.I0(\axi_rdata[17]_i_40_n_0 ),
- .I1(\axi_rdata[17]_i_41_n_0 ),
- .O(\axi_rdata_reg[17]_1 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[18]_i_21
- (.I0(\axi_rdata[18]_i_40_n_0 ),
- .I1(\axi_rdata[18]_i_41_n_0 ),
- .O(\axi_rdata_reg[18]_1 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[19]_i_21
- (.I0(\axi_rdata[19]_i_40_n_0 ),
- .I1(\axi_rdata[19]_i_41_n_0 ),
- .O(\axi_rdata_reg[19]_1 ),
- .S(\axi_araddr_reg[4] [2]));
- MUXF7 \axi_rdata_reg[1]_i_21
- (.I0(\axi_rdata[1]_i_42_n_0 ),
- .I1(\axi_rdata[1]_i_43_n_0 ),
- .O(\axi_rdata_reg[1]_2 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[2]_i_21
- (.I0(\axi_rdata[2]_i_42_n_0 ),
- .I1(\axi_rdata[2]_i_43_n_0 ),
- .O(\axi_rdata_reg[2]_2 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[3]_i_21
- (.I0(\axi_rdata[3]_i_42_n_0 ),
- .I1(\axi_rdata[3]_i_43_n_0 ),
- .O(\axi_rdata_reg[3]_2 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[4]_i_21
- (.I0(\axi_rdata[4]_i_42_n_0 ),
- .I1(\axi_rdata[4]_i_43_n_0 ),
- .O(\axi_rdata_reg[4]_2 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[5]_i_21
- (.I0(\axi_rdata[5]_i_42_n_0 ),
- .I1(\axi_rdata[5]_i_43_n_0 ),
- .O(\axi_rdata_reg[5]_2 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[6]_i_21
- (.I0(\axi_rdata[6]_i_42_n_0 ),
- .I1(\axi_rdata[6]_i_43_n_0 ),
- .O(\axi_rdata_reg[6]_2 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[7]_i_21
- (.I0(\axi_rdata[7]_i_42_n_0 ),
- .I1(\axi_rdata[7]_i_43_n_0 ),
- .O(\axi_rdata_reg[7]_2 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[8]_i_21
- (.I0(\axi_rdata[8]_i_40_n_0 ),
- .I1(\axi_rdata[8]_i_41_n_0 ),
- .O(\axi_rdata_reg[8]_1 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[9]_i_21
- (.I0(\axi_rdata[9]_i_40_n_0 ),
- .I1(\axi_rdata[9]_i_41_n_0 ),
- .O(\axi_rdata_reg[9]_1 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- FDRE \data_o_reg[1][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_fbd[0]),
- .Q(\axi_rdata_reg[3]_4 [0]),
- .R(1'b0));
- FDRE \data_o_reg[1][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_fbd[1]),
- .Q(\axi_rdata_reg[3]_4 [1]),
- .R(1'b0));
- FDRE \data_o_reg[1][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_fbd[2]),
- .Q(\axi_rdata_reg[3]_4 [2]),
- .R(1'b0));
- FDRE \data_o_reg[1][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_fbd[3]),
- .Q(\axi_rdata_reg[3]_4 [3]),
- .R(1'b0));
- FDRE \data_o_reg[6][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D[0]),
- .Q(\s_datao_fmc1[6] [0]),
- .R(1'b0));
- FDRE \data_o_reg[6][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D[1]),
- .Q(\s_datao_fmc1[6] [1]),
- .R(1'b0));
- FDRE \data_o_reg[6][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D[2]),
- .Q(\s_datao_fmc1[6] [2]),
- .R(1'b0));
- FDRE \data_o_reg[6][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D[3]),
- .Q(\s_datao_fmc1[6] [3]),
- .R(1'b0));
- FDRE \data_o_reg[6][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_diffouts_o[4]),
- .Q(\s_datao_fmc1[6] [4]),
- .R(1'b0));
- FDRE \data_o_reg[6][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_diffouts_o[5]),
- .Q(\s_datao_fmc1[6] [5]),
- .R(1'b0));
- FDRE \data_o_reg[6][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_diffouts_o[6]),
- .Q(\s_datao_fmc1[6] [6]),
- .R(1'b0));
- FDRE \data_o_reg[6][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_diffouts_o[7]),
- .Q(\s_datao_fmc1[6] [7]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[0].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [0]),
- .IB(\FMC1_LA_N_b[32] [0]),
- .O(s_comparators_i_0));
- system_design_fasec_hwtest_0_0_pulseMeasure_101 \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc1[0] [0]),
- .E(\cmp_lengthCounter/RSTP ),
- .Q(v_cmpled[2:0]),
- .S(\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_3 ),
- .SR(rst_i),
- .\data_rw_o_reg[11][7] (\data_rw_o_reg[11][7] [2]),
- .\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] (\s_cmp_lengths[0]_0 ),
- .intr_o_reg(\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_4 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce ),
- .s_buff2_reg_0(\s_datao_fmc1[0] [2:1]),
- .s_comparators_i_0(s_comparators_i_0),
- .\s_datao_fmc1[4] (\s_datao_fmc1[4] [0]),
- .\s_debounce_reg[1] (s_buff2_i_1_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc1[4] [2:1]),
- .\v_cmp_reg[2] (v_cmp[2:0]),
- .\v_dout_reg[7] (\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2 ));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [0]),
- .Q(\s_datao_fmc1[48] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [10]),
- .Q(\s_datao_fmc1[48] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [11]),
- .Q(\s_datao_fmc1[48] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [12]),
- .Q(\s_datao_fmc1[48] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [13]),
- .Q(\s_datao_fmc1[48] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [14]),
- .Q(\s_datao_fmc1[48] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [15]),
- .Q(\s_datao_fmc1[48] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [16]),
- .Q(\s_datao_fmc1[48] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [17]),
- .Q(\s_datao_fmc1[48] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [18]),
- .Q(\s_datao_fmc1[48] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [19]),
- .Q(\s_datao_fmc1[48] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [1]),
- .Q(\s_datao_fmc1[48] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [20]),
- .Q(\s_datao_fmc1[48] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [21]),
- .Q(\s_datao_fmc1[48] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [22]),
- .Q(\s_datao_fmc1[48] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [23]),
- .Q(\s_datao_fmc1[48] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [2]),
- .Q(\s_datao_fmc1[48] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [3]),
- .Q(\s_datao_fmc1[48] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [4]),
- .Q(\s_datao_fmc1[48] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [5]),
- .Q(\s_datao_fmc1[48] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [6]),
- .Q(\s_datao_fmc1[48] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [7]),
- .Q(\s_datao_fmc1[48] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [8]),
- .Q(\s_datao_fmc1[48] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [9]),
- .Q(\s_datao_fmc1[48] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[10].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [10]),
- .IB(\FMC1_LA_N_b[32] [10]),
- .O(s_comparators_i_10));
- system_design_fasec_hwtest_0_0_pulseMeasure_102 \fmc_03287_channels[10].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[2]),
- .E(\cmp_lengthCounter/RSTP_1 ),
- .Q(\cmp_pulseSync/s_debounce_0 ),
- .SR(rst_i),
- .\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] (\s_cmp_lengths[10]_10 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc1[0] [10]),
- .s_comparators_i_10(s_comparators_i_10),
- .\s_debounce_reg[1] (s_buff2_i_1__9_n_0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [0]),
- .Q(\s_datao_fmc1[58] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [10]),
- .Q(\s_datao_fmc1[58] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [11]),
- .Q(\s_datao_fmc1[58] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [12]),
- .Q(\s_datao_fmc1[58] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [13]),
- .Q(\s_datao_fmc1[58] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [14]),
- .Q(\s_datao_fmc1[58] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [15]),
- .Q(\s_datao_fmc1[58] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [16]),
- .Q(\s_datao_fmc1[58] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [17]),
- .Q(\s_datao_fmc1[58] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [18]),
- .Q(\s_datao_fmc1[58] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [19]),
- .Q(\s_datao_fmc1[58] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [1]),
- .Q(\s_datao_fmc1[58] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [20]),
- .Q(\s_datao_fmc1[58] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [21]),
- .Q(\s_datao_fmc1[58] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [22]),
- .Q(\s_datao_fmc1[58] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [23]),
- .Q(\s_datao_fmc1[58] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [2]),
- .Q(\s_datao_fmc1[58] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [3]),
- .Q(\s_datao_fmc1[58] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [4]),
- .Q(\s_datao_fmc1[58] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [5]),
- .Q(\s_datao_fmc1[58] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [6]),
- .Q(\s_datao_fmc1[58] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [7]),
- .Q(\s_datao_fmc1[58] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [8]),
- .Q(\s_datao_fmc1[58] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [9]),
- .Q(\s_datao_fmc1[58] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[11].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [11]),
- .IB(\FMC1_LA_N_b[32] [11]),
- .O(s_comparators_i_11));
- system_design_fasec_hwtest_0_0_pulseMeasure_103 \fmc_03287_channels[11].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[3]),
- .E(\cmp_lengthCounter/RSTP_3 ),
- .Q(\cmp_pulseSync/s_debounce_2 ),
- .SR(rst_i),
- .\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] (\s_cmp_lengths[11]_11 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc1[0] [11]),
- .s_comparators_i_11(s_comparators_i_11),
- .\s_debounce_reg[1] (s_buff2_i_1__10_n_0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [0]),
- .Q(\s_datao_fmc1[59] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [10]),
- .Q(\s_datao_fmc1[59] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [11]),
- .Q(\s_datao_fmc1[59] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [12]),
- .Q(\s_datao_fmc1[59] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [13]),
- .Q(\s_datao_fmc1[59] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [14]),
- .Q(\s_datao_fmc1[59] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [15]),
- .Q(\s_datao_fmc1[59] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [16]),
- .Q(\s_datao_fmc1[59] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [17]),
- .Q(\s_datao_fmc1[59] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [18]),
- .Q(\s_datao_fmc1[59] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [19]),
- .Q(\s_datao_fmc1[59] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [1]),
- .Q(\s_datao_fmc1[59] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [20]),
- .Q(\s_datao_fmc1[59] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [21]),
- .Q(\s_datao_fmc1[59] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [22]),
- .Q(\s_datao_fmc1[59] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [23]),
- .Q(\s_datao_fmc1[59] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [2]),
- .Q(\s_datao_fmc1[59] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [3]),
- .Q(\s_datao_fmc1[59] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [4]),
- .Q(\s_datao_fmc1[59] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [5]),
- .Q(\s_datao_fmc1[59] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [6]),
- .Q(\s_datao_fmc1[59] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [7]),
- .Q(\s_datao_fmc1[59] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [8]),
- .Q(\s_datao_fmc1[59] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [9]),
- .Q(\s_datao_fmc1[59] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[12].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [12]),
- .IB(\FMC1_LA_N_b[32] [12]),
- .O(s_comparators_i_12));
- system_design_fasec_hwtest_0_0_pulseMeasure_104 \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[4]),
- .E(\cmp_lengthCounter/RSTP_5 ),
- .Q(v_cmpled[14:12]),
- .S(\fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_2 ),
- .SR(rst_i),
- .\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] (\s_cmp_lengths[12]_12 ),
- .intr_o_reg(\fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_3 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_4 ),
- .s_buff2_reg_0(\s_datao_fmc1[0] [14:13]),
- .s_buff3_reg(\s_datao_fmc1[0] [12]),
- .s_comparators_i_12(s_comparators_i_12),
- .\s_debounce_reg[1] (s_buff2_i_1__11_n_0),
- .s_pulseLed_reg_0(s_count_reg[6:5]),
- .\v_cmp_reg[14] (v_cmp[14:12]));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [0]),
- .Q(\s_datao_fmc1[60] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [10]),
- .Q(\s_datao_fmc1[60] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [11]),
- .Q(\s_datao_fmc1[60] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [12]),
- .Q(\s_datao_fmc1[60] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [13]),
- .Q(\s_datao_fmc1[60] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [14]),
- .Q(\s_datao_fmc1[60] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [15]),
- .Q(\s_datao_fmc1[60] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [16]),
- .Q(\s_datao_fmc1[60] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [17]),
- .Q(\s_datao_fmc1[60] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [18]),
- .Q(\s_datao_fmc1[60] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [19]),
- .Q(\s_datao_fmc1[60] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [1]),
- .Q(\s_datao_fmc1[60] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [20]),
- .Q(\s_datao_fmc1[60] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [21]),
- .Q(\s_datao_fmc1[60] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [22]),
- .Q(\s_datao_fmc1[60] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [23]),
- .Q(\s_datao_fmc1[60] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [2]),
- .Q(\s_datao_fmc1[60] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [3]),
- .Q(\s_datao_fmc1[60] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [4]),
- .Q(\s_datao_fmc1[60] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [5]),
- .Q(\s_datao_fmc1[60] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [6]),
- .Q(\s_datao_fmc1[60] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [7]),
- .Q(\s_datao_fmc1[60] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [8]),
- .Q(\s_datao_fmc1[60] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [9]),
- .Q(\s_datao_fmc1[60] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[13].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [13]),
- .IB(\FMC1_LA_N_b[32] [13]),
- .O(s_comparators_i_13));
- system_design_fasec_hwtest_0_0_pulseMeasure_105 \fmc_03287_channels[13].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[5]),
- .E(\cmp_lengthCounter/RSTP_7 ),
- .Q(\cmp_pulseSync/s_debounce_6 ),
- .SR(rst_i),
- .\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] (\s_cmp_lengths[13]_13 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc1[0] [13]),
- .s_comparators_i_13(s_comparators_i_13),
- .\s_debounce_reg[1] (s_buff2_i_1__12_n_0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [0]),
- .Q(\s_datao_fmc1[61] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [10]),
- .Q(\s_datao_fmc1[61] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [11]),
- .Q(\s_datao_fmc1[61] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [12]),
- .Q(\s_datao_fmc1[61] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [13]),
- .Q(\s_datao_fmc1[61] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [14]),
- .Q(\s_datao_fmc1[61] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [15]),
- .Q(\s_datao_fmc1[61] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [16]),
- .Q(\s_datao_fmc1[61] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [17]),
- .Q(\s_datao_fmc1[61] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [18]),
- .Q(\s_datao_fmc1[61] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [19]),
- .Q(\s_datao_fmc1[61] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [1]),
- .Q(\s_datao_fmc1[61] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [20]),
- .Q(\s_datao_fmc1[61] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [21]),
- .Q(\s_datao_fmc1[61] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [22]),
- .Q(\s_datao_fmc1[61] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [23]),
- .Q(\s_datao_fmc1[61] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [2]),
- .Q(\s_datao_fmc1[61] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [3]),
- .Q(\s_datao_fmc1[61] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [4]),
- .Q(\s_datao_fmc1[61] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [5]),
- .Q(\s_datao_fmc1[61] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [6]),
- .Q(\s_datao_fmc1[61] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [7]),
- .Q(\s_datao_fmc1[61] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [8]),
- .Q(\s_datao_fmc1[61] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [9]),
- .Q(\s_datao_fmc1[61] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[14].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [14]),
- .IB(\FMC1_LA_N_b[32] [14]),
- .O(s_comparators_i_14));
- system_design_fasec_hwtest_0_0_pulseMeasure_106 \fmc_03287_channels[14].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[6]),
- .E(\cmp_lengthCounter/RSTP_9 ),
- .Q(\cmp_pulseSync/s_debounce_8 ),
- .SR(rst_i),
- .\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] (\s_cmp_lengths[14]_14 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc1[0] [14]),
- .s_comparators_i_14(s_comparators_i_14),
- .\s_debounce_reg[1] (s_buff2_i_1__13_n_0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [0]),
- .Q(\s_datao_fmc1[62] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [10]),
- .Q(\s_datao_fmc1[62] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [11]),
- .Q(\s_datao_fmc1[62] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [12]),
- .Q(\s_datao_fmc1[62] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [13]),
- .Q(\s_datao_fmc1[62] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [14]),
- .Q(\s_datao_fmc1[62] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [15]),
- .Q(\s_datao_fmc1[62] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [16]),
- .Q(\s_datao_fmc1[62] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [17]),
- .Q(\s_datao_fmc1[62] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [18]),
- .Q(\s_datao_fmc1[62] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [19]),
- .Q(\s_datao_fmc1[62] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [1]),
- .Q(\s_datao_fmc1[62] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [20]),
- .Q(\s_datao_fmc1[62] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [21]),
- .Q(\s_datao_fmc1[62] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [22]),
- .Q(\s_datao_fmc1[62] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [23]),
- .Q(\s_datao_fmc1[62] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [2]),
- .Q(\s_datao_fmc1[62] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [3]),
- .Q(\s_datao_fmc1[62] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [4]),
- .Q(\s_datao_fmc1[62] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [5]),
- .Q(\s_datao_fmc1[62] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [6]),
- .Q(\s_datao_fmc1[62] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [7]),
- .Q(\s_datao_fmc1[62] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [8]),
- .Q(\s_datao_fmc1[62] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [9]),
- .Q(\s_datao_fmc1[62] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[15].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [15]),
- .IB(\FMC1_LA_N_b[32] [15]),
- .O(s_comparators_i_15));
- system_design_fasec_hwtest_0_0_pulseMeasure_107 \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[7]),
- .E(\cmp_lengthCounter/RSTP_11 ),
- .Q(v_cmpled[17:15]),
- .S(\fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_2 ),
- .SR(rst_i),
- .\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] (\s_cmp_lengths[15]_15 ),
- .intr_o_reg(\fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_3 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_10 ),
- .s_buff2_reg_0(\s_datao_fmc1[0] [17:16]),
- .s_buff3_reg(\s_datao_fmc1[0] [15]),
- .s_comparators_i_15(s_comparators_i_15),
- .\s_debounce_reg[1] (s_buff2_i_1__14_n_0),
- .s_pulseLed_reg_0(s_count_reg[9:8]),
- .\v_cmp_reg[17] (v_cmp[17:15]));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [0]),
- .Q(\s_datao_fmc1[63] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [10]),
- .Q(\s_datao_fmc1[63] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [11]),
- .Q(\s_datao_fmc1[63] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [12]),
- .Q(\s_datao_fmc1[63] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [13]),
- .Q(\s_datao_fmc1[63] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [14]),
- .Q(\s_datao_fmc1[63] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [15]),
- .Q(\s_datao_fmc1[63] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [16]),
- .Q(\s_datao_fmc1[63] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [17]),
- .Q(\s_datao_fmc1[63] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [18]),
- .Q(\s_datao_fmc1[63] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [19]),
- .Q(\s_datao_fmc1[63] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [1]),
- .Q(\s_datao_fmc1[63] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [20]),
- .Q(\s_datao_fmc1[63] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [21]),
- .Q(\s_datao_fmc1[63] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [22]),
- .Q(\s_datao_fmc1[63] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [23]),
- .Q(\s_datao_fmc1[63] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [2]),
- .Q(\s_datao_fmc1[63] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [3]),
- .Q(\s_datao_fmc1[63] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [4]),
- .Q(\s_datao_fmc1[63] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [5]),
- .Q(\s_datao_fmc1[63] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [6]),
- .Q(\s_datao_fmc1[63] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [7]),
- .Q(\s_datao_fmc1[63] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [8]),
- .Q(\s_datao_fmc1[63] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [9]),
- .Q(\s_datao_fmc1[63] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[16].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [16]),
- .IB(\FMC1_LA_N_b[32] [16]),
- .O(s_comparators_i_16));
- system_design_fasec_hwtest_0_0_pulseMeasure_108 \fmc_03287_channels[16].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[8]),
- .E(\cmp_lengthCounter/RSTP_13 ),
- .Q(\cmp_pulseSync/s_debounce_12 ),
- .SR(rst_i),
- .\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] (\s_cmp_lengths[16]_16 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc1[0] [16]),
- .s_comparators_i_16(s_comparators_i_16),
- .\s_debounce_reg[1] (s_buff2_i_1__15_n_0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [0]),
- .Q(\s_datao_fmc1[64] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [10]),
- .Q(\s_datao_fmc1[64] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [11]),
- .Q(\s_datao_fmc1[64] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [12]),
- .Q(\s_datao_fmc1[64] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [13]),
- .Q(\s_datao_fmc1[64] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [14]),
- .Q(\s_datao_fmc1[64] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [15]),
- .Q(\s_datao_fmc1[64] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [16]),
- .Q(\s_datao_fmc1[64] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [17]),
- .Q(\s_datao_fmc1[64] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [18]),
- .Q(\s_datao_fmc1[64] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [19]),
- .Q(\s_datao_fmc1[64] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [1]),
- .Q(\s_datao_fmc1[64] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [20]),
- .Q(\s_datao_fmc1[64] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [21]),
- .Q(\s_datao_fmc1[64] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [22]),
- .Q(\s_datao_fmc1[64] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [23]),
- .Q(\s_datao_fmc1[64] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [2]),
- .Q(\s_datao_fmc1[64] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [3]),
- .Q(\s_datao_fmc1[64] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [4]),
- .Q(\s_datao_fmc1[64] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [5]),
- .Q(\s_datao_fmc1[64] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [6]),
- .Q(\s_datao_fmc1[64] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [7]),
- .Q(\s_datao_fmc1[64] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [8]),
- .Q(\s_datao_fmc1[64] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [9]),
- .Q(\s_datao_fmc1[64] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[17].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [17]),
- .IB(\FMC1_LA_N_b[32] [17]),
- .O(s_comparators_i_17));
- system_design_fasec_hwtest_0_0_pulseMeasure_109 \fmc_03287_channels[17].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[9]),
- .E(\cmp_lengthCounter/RSTP_15 ),
- .Q(\cmp_pulseSync/s_debounce_14 ),
- .SR(rst_i),
- .\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] (\s_cmp_lengths[17]_17 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc1[0] [17]),
- .s_comparators_i_17(s_comparators_i_17),
- .\s_debounce_reg[1] (s_buff2_i_1__16_n_0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [0]),
- .Q(\s_datao_fmc1[65] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [10]),
- .Q(\s_datao_fmc1[65] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [11]),
- .Q(\s_datao_fmc1[65] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [12]),
- .Q(\s_datao_fmc1[65] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [13]),
- .Q(\s_datao_fmc1[65] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [14]),
- .Q(\s_datao_fmc1[65] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [15]),
- .Q(\s_datao_fmc1[65] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [16]),
- .Q(\s_datao_fmc1[65] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [17]),
- .Q(\s_datao_fmc1[65] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [18]),
- .Q(\s_datao_fmc1[65] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [19]),
- .Q(\s_datao_fmc1[65] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [1]),
- .Q(\s_datao_fmc1[65] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [20]),
- .Q(\s_datao_fmc1[65] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [21]),
- .Q(\s_datao_fmc1[65] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [22]),
- .Q(\s_datao_fmc1[65] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [23]),
- .Q(\s_datao_fmc1[65] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [2]),
- .Q(\s_datao_fmc1[65] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [3]),
- .Q(\s_datao_fmc1[65] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [4]),
- .Q(\s_datao_fmc1[65] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [5]),
- .Q(\s_datao_fmc1[65] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [6]),
- .Q(\s_datao_fmc1[65] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [7]),
- .Q(\s_datao_fmc1[65] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [8]),
- .Q(\s_datao_fmc1[65] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [9]),
- .Q(\s_datao_fmc1[65] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[18].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [18]),
- .IB(\FMC1_LA_N_b[32] [18]),
- .O(s_comparators_i_18));
- system_design_fasec_hwtest_0_0_pulseMeasure_110 \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[10]),
- .E(\cmp_lengthCounter/RSTP_17 ),
- .Q(v_cmpled[19:18]),
- .S(\fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_2 ),
- .SR(rst_i),
- .\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] (\s_cmp_lengths[18]_18 ),
- .intr_o_reg(\fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_3 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_16 ),
- .s_buff2_reg_0(\s_datao_fmc1[0] [19]),
- .s_buff3_reg(\s_datao_fmc1[0] [18]),
- .s_comparators_i_18(s_comparators_i_18),
- .\s_debounce_reg[1] (s_buff2_i_1__17_n_0),
- .s_pulseLed_reg_0(s_count_reg[11]),
- .\v_cmp_reg[19] (v_cmp[19:18]));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [0]),
- .Q(\s_datao_fmc1[66] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [10]),
- .Q(\s_datao_fmc1[66] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [11]),
- .Q(\s_datao_fmc1[66] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [12]),
- .Q(\s_datao_fmc1[66] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [13]),
- .Q(\s_datao_fmc1[66] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [14]),
- .Q(\s_datao_fmc1[66] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [15]),
- .Q(\s_datao_fmc1[66] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [16]),
- .Q(\s_datao_fmc1[66] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [17]),
- .Q(\s_datao_fmc1[66] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [18]),
- .Q(\s_datao_fmc1[66] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [19]),
- .Q(\s_datao_fmc1[66] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [1]),
- .Q(\s_datao_fmc1[66] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [20]),
- .Q(\s_datao_fmc1[66] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [21]),
- .Q(\s_datao_fmc1[66] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [22]),
- .Q(\s_datao_fmc1[66] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [23]),
- .Q(\s_datao_fmc1[66] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [2]),
- .Q(\s_datao_fmc1[66] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [3]),
- .Q(\s_datao_fmc1[66] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [4]),
- .Q(\s_datao_fmc1[66] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [5]),
- .Q(\s_datao_fmc1[66] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [6]),
- .Q(\s_datao_fmc1[66] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [7]),
- .Q(\s_datao_fmc1[66] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [8]),
- .Q(\s_datao_fmc1[66] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [9]),
- .Q(\s_datao_fmc1[66] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[19].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [19]),
- .IB(\FMC1_LA_N_b[32] [19]),
- .O(s_comparators_i_19));
- system_design_fasec_hwtest_0_0_pulseMeasure_111 \fmc_03287_channels[19].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[11]),
- .E(\cmp_lengthCounter/RSTP_19 ),
- .Q(\cmp_pulseSync/s_debounce_18 ),
- .SR(rst_i),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] (\s_cmp_lengths[19]_19 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc1[0] [19]),
- .s_comparators_i_19(s_comparators_i_19),
- .\s_debounce_reg[1] (s_buff2_i_1__18_n_0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [0]),
- .Q(\s_datao_fmc1[67] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [10]),
- .Q(\s_datao_fmc1[67] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [11]),
- .Q(\s_datao_fmc1[67] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [12]),
- .Q(\s_datao_fmc1[67] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [13]),
- .Q(\s_datao_fmc1[67] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [14]),
- .Q(\s_datao_fmc1[67] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [15]),
- .Q(\s_datao_fmc1[67] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [16]),
- .Q(\s_datao_fmc1[67] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [17]),
- .Q(\s_datao_fmc1[67] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [18]),
- .Q(\s_datao_fmc1[67] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [19]),
- .Q(\s_datao_fmc1[67] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [1]),
- .Q(\s_datao_fmc1[67] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [20]),
- .Q(\s_datao_fmc1[67] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [21]),
- .Q(\s_datao_fmc1[67] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [22]),
- .Q(\s_datao_fmc1[67] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [23]),
- .Q(\s_datao_fmc1[67] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [2]),
- .Q(\s_datao_fmc1[67] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [3]),
- .Q(\s_datao_fmc1[67] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [4]),
- .Q(\s_datao_fmc1[67] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [5]),
- .Q(\s_datao_fmc1[67] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [6]),
- .Q(\s_datao_fmc1[67] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [7]),
- .Q(\s_datao_fmc1[67] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [8]),
- .Q(\s_datao_fmc1[67] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [9]),
- .Q(\s_datao_fmc1[67] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[1].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [1]),
- .IB(\FMC1_LA_N_b[32] [1]),
- .O(s_comparators_i_1));
- system_design_fasec_hwtest_0_0_pulseMeasure_112 \fmc_03287_channels[1].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc1[0] [1]),
- .E(\cmp_lengthCounter/RSTP_21 ),
- .Q(\cmp_pulseSync/s_debounce_20 ),
- .SR(rst_i),
- .\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] (\s_cmp_lengths[1]_1 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_comparators_i_1(s_comparators_i_1),
- .s_count_reg(\s_datao_fmc1[4] [1]),
- .\s_debounce_reg[1] (s_buff2_i_1__0_n_0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [0]),
- .Q(\s_datao_fmc1[49] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [10]),
- .Q(\s_datao_fmc1[49] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [11]),
- .Q(\s_datao_fmc1[49] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [12]),
- .Q(\s_datao_fmc1[49] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [13]),
- .Q(\s_datao_fmc1[49] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [14]),
- .Q(\s_datao_fmc1[49] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [15]),
- .Q(\s_datao_fmc1[49] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [16]),
- .Q(\s_datao_fmc1[49] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [17]),
- .Q(\s_datao_fmc1[49] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [18]),
- .Q(\s_datao_fmc1[49] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [19]),
- .Q(\s_datao_fmc1[49] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [1]),
- .Q(\s_datao_fmc1[49] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [20]),
- .Q(\s_datao_fmc1[49] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [21]),
- .Q(\s_datao_fmc1[49] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [22]),
- .Q(\s_datao_fmc1[49] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [23]),
- .Q(\s_datao_fmc1[49] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [2]),
- .Q(\s_datao_fmc1[49] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [3]),
- .Q(\s_datao_fmc1[49] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [4]),
- .Q(\s_datao_fmc1[49] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [5]),
- .Q(\s_datao_fmc1[49] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [6]),
- .Q(\s_datao_fmc1[49] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [7]),
- .Q(\s_datao_fmc1[49] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [8]),
- .Q(\s_datao_fmc1[49] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [9]),
- .Q(\s_datao_fmc1[49] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[2].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [2]),
- .IB(\FMC1_LA_N_b[32] [2]),
- .O(s_comparators_i_2));
- system_design_fasec_hwtest_0_0_pulseMeasure_113 \fmc_03287_channels[2].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc1[0] [2]),
- .E(\cmp_lengthCounter/RSTP_23 ),
- .Q(\cmp_pulseSync/s_debounce_22 ),
- .SR(rst_i),
- .\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] (\s_cmp_lengths[2]_2 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_comparators_i_2(s_comparators_i_2),
- .s_count_reg(\s_datao_fmc1[4] [2]),
- .\s_debounce_reg[1] (s_buff2_i_1__1_n_0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [0]),
- .Q(\s_datao_fmc1[50] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [10]),
- .Q(\s_datao_fmc1[50] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [11]),
- .Q(\s_datao_fmc1[50] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [12]),
- .Q(\s_datao_fmc1[50] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [13]),
- .Q(\s_datao_fmc1[50] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [14]),
- .Q(\s_datao_fmc1[50] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [15]),
- .Q(\s_datao_fmc1[50] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [16]),
- .Q(\s_datao_fmc1[50] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [17]),
- .Q(\s_datao_fmc1[50] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [18]),
- .Q(\s_datao_fmc1[50] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [19]),
- .Q(\s_datao_fmc1[50] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [1]),
- .Q(\s_datao_fmc1[50] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [20]),
- .Q(\s_datao_fmc1[50] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [21]),
- .Q(\s_datao_fmc1[50] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [22]),
- .Q(\s_datao_fmc1[50] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [23]),
- .Q(\s_datao_fmc1[50] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [2]),
- .Q(\s_datao_fmc1[50] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [3]),
- .Q(\s_datao_fmc1[50] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [4]),
- .Q(\s_datao_fmc1[50] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [5]),
- .Q(\s_datao_fmc1[50] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [6]),
- .Q(\s_datao_fmc1[50] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [7]),
- .Q(\s_datao_fmc1[50] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [8]),
- .Q(\s_datao_fmc1[50] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [9]),
- .Q(\s_datao_fmc1[50] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[3].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [3]),
- .IB(\FMC1_LA_N_b[32] [3]),
- .O(s_comparators_i_3));
- system_design_fasec_hwtest_0_0_pulseMeasure_114 \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc1[0] [3]),
- .E(\cmp_lengthCounter/RSTP_25 ),
- .Q(v_cmpled[5:3]),
- .S(\fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_2 ),
- .SR(rst_i),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] (\s_cmp_lengths[3]_3 ),
- .intr_o_reg(\fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_3 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_24 ),
- .s_buff2_reg_0(\s_datao_fmc1[0] [5:4]),
- .s_comparators_i_3(s_comparators_i_3),
- .\s_datao_fmc1[4] (\s_datao_fmc1[4] [3]),
- .\s_debounce_reg[1] (s_buff2_i_1__2_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc1[4] [5:4]),
- .\v_cmp_reg[5] (v_cmp[5:3]));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [0]),
- .Q(\s_datao_fmc1[51] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [10]),
- .Q(\s_datao_fmc1[51] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [11]),
- .Q(\s_datao_fmc1[51] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [12]),
- .Q(\s_datao_fmc1[51] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [13]),
- .Q(\s_datao_fmc1[51] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [14]),
- .Q(\s_datao_fmc1[51] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [15]),
- .Q(\s_datao_fmc1[51] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [16]),
- .Q(\s_datao_fmc1[51] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [17]),
- .Q(\s_datao_fmc1[51] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [18]),
- .Q(\s_datao_fmc1[51] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [19]),
- .Q(\s_datao_fmc1[51] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [1]),
- .Q(\s_datao_fmc1[51] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [20]),
- .Q(\s_datao_fmc1[51] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [21]),
- .Q(\s_datao_fmc1[51] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [22]),
- .Q(\s_datao_fmc1[51] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [23]),
- .Q(\s_datao_fmc1[51] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [2]),
- .Q(\s_datao_fmc1[51] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [3]),
- .Q(\s_datao_fmc1[51] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [4]),
- .Q(\s_datao_fmc1[51] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [5]),
- .Q(\s_datao_fmc1[51] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [6]),
- .Q(\s_datao_fmc1[51] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [7]),
- .Q(\s_datao_fmc1[51] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [8]),
- .Q(\s_datao_fmc1[51] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [9]),
- .Q(\s_datao_fmc1[51] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[4].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [4]),
- .IB(\FMC1_LA_N_b[32] [4]),
- .O(s_comparators_i_4));
- system_design_fasec_hwtest_0_0_pulseMeasure_115 \fmc_03287_channels[4].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc1[0] [4]),
- .E(\cmp_lengthCounter/RSTP_27 ),
- .Q(\cmp_pulseSync/s_debounce_26 ),
- .SR(rst_i),
- .\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] (\s_cmp_lengths[4]_4 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_comparators_i_4(s_comparators_i_4),
- .s_count_reg(\s_datao_fmc1[4] [4]),
- .\s_debounce_reg[1] (s_buff2_i_1__3_n_0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [0]),
- .Q(\s_datao_fmc1[52] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [10]),
- .Q(\s_datao_fmc1[52] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [11]),
- .Q(\s_datao_fmc1[52] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [12]),
- .Q(\s_datao_fmc1[52] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [13]),
- .Q(\s_datao_fmc1[52] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [14]),
- .Q(\s_datao_fmc1[52] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [15]),
- .Q(\s_datao_fmc1[52] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [16]),
- .Q(\s_datao_fmc1[52] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [17]),
- .Q(\s_datao_fmc1[52] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [18]),
- .Q(\s_datao_fmc1[52] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [19]),
- .Q(\s_datao_fmc1[52] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [1]),
- .Q(\s_datao_fmc1[52] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [20]),
- .Q(\s_datao_fmc1[52] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [21]),
- .Q(\s_datao_fmc1[52] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [22]),
- .Q(\s_datao_fmc1[52] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [23]),
- .Q(\s_datao_fmc1[52] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [2]),
- .Q(\s_datao_fmc1[52] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [3]),
- .Q(\s_datao_fmc1[52] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [4]),
- .Q(\s_datao_fmc1[52] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [5]),
- .Q(\s_datao_fmc1[52] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [6]),
- .Q(\s_datao_fmc1[52] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [7]),
- .Q(\s_datao_fmc1[52] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [8]),
- .Q(\s_datao_fmc1[52] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [9]),
- .Q(\s_datao_fmc1[52] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[5].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [5]),
- .IB(\FMC1_LA_N_b[32] [5]),
- .O(s_comparators_i_5));
- system_design_fasec_hwtest_0_0_pulseMeasure_116 \fmc_03287_channels[5].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc1[0] [5]),
- .E(\cmp_lengthCounter/RSTP_29 ),
- .Q(\cmp_pulseSync/s_debounce_28 ),
- .SR(rst_i),
- .\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] (\s_cmp_lengths[5]_5 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_comparators_i_5(s_comparators_i_5),
- .s_count_reg(\s_datao_fmc1[4] [5]),
- .\s_debounce_reg[1] (s_buff2_i_1__4_n_0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [0]),
- .Q(\s_datao_fmc1[53] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [10]),
- .Q(\s_datao_fmc1[53] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [11]),
- .Q(\s_datao_fmc1[53] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [12]),
- .Q(\s_datao_fmc1[53] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [13]),
- .Q(\s_datao_fmc1[53] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [14]),
- .Q(\s_datao_fmc1[53] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [15]),
- .Q(\s_datao_fmc1[53] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [16]),
- .Q(\s_datao_fmc1[53] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [17]),
- .Q(\s_datao_fmc1[53] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [18]),
- .Q(\s_datao_fmc1[53] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [19]),
- .Q(\s_datao_fmc1[53] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [1]),
- .Q(\s_datao_fmc1[53] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [20]),
- .Q(\s_datao_fmc1[53] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [21]),
- .Q(\s_datao_fmc1[53] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [22]),
- .Q(\s_datao_fmc1[53] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [23]),
- .Q(\s_datao_fmc1[53] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [2]),
- .Q(\s_datao_fmc1[53] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [3]),
- .Q(\s_datao_fmc1[53] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [4]),
- .Q(\s_datao_fmc1[53] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [5]),
- .Q(\s_datao_fmc1[53] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [6]),
- .Q(\s_datao_fmc1[53] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [7]),
- .Q(\s_datao_fmc1[53] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [8]),
- .Q(\s_datao_fmc1[53] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [9]),
- .Q(\s_datao_fmc1[53] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[6].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [6]),
- .IB(\FMC1_LA_N_b[32] [6]),
- .O(s_comparators_i_6));
- system_design_fasec_hwtest_0_0_pulseMeasure_117 \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc1[0] [6]),
- .E(\cmp_lengthCounter/RSTP_31 ),
- .Q(v_cmpled[8:6]),
- .S(\fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_2 ),
- .SR(rst_i),
- .\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] (\s_cmp_lengths[6]_6 ),
- .intr_o_reg(\fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_3 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_30 ),
- .s_buff2_reg_0(\s_datao_fmc1[0] [8:7]),
- .s_comparators_i_6(s_comparators_i_6),
- .\s_datao_fmc1[4] (\s_datao_fmc1[4] [6]),
- .\s_debounce_reg[1] (s_buff2_i_1__5_n_0),
- .s_pulseLed_reg_0({s_count_reg[0],\s_datao_fmc1[4] [7]}),
- .\v_cmp_reg[8] (v_cmp[8:6]));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [0]),
- .Q(\s_datao_fmc1[54] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [10]),
- .Q(\s_datao_fmc1[54] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [11]),
- .Q(\s_datao_fmc1[54] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [12]),
- .Q(\s_datao_fmc1[54] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [13]),
- .Q(\s_datao_fmc1[54] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [14]),
- .Q(\s_datao_fmc1[54] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [15]),
- .Q(\s_datao_fmc1[54] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [16]),
- .Q(\s_datao_fmc1[54] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [17]),
- .Q(\s_datao_fmc1[54] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [18]),
- .Q(\s_datao_fmc1[54] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [19]),
- .Q(\s_datao_fmc1[54] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [1]),
- .Q(\s_datao_fmc1[54] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [20]),
- .Q(\s_datao_fmc1[54] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [21]),
- .Q(\s_datao_fmc1[54] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [22]),
- .Q(\s_datao_fmc1[54] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [23]),
- .Q(\s_datao_fmc1[54] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [2]),
- .Q(\s_datao_fmc1[54] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [3]),
- .Q(\s_datao_fmc1[54] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [4]),
- .Q(\s_datao_fmc1[54] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [5]),
- .Q(\s_datao_fmc1[54] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [6]),
- .Q(\s_datao_fmc1[54] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [7]),
- .Q(\s_datao_fmc1[54] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [8]),
- .Q(\s_datao_fmc1[54] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [9]),
- .Q(\s_datao_fmc1[54] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[7].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [7]),
- .IB(\FMC1_LA_N_b[32] [7]),
- .O(s_comparators_i_7));
- system_design_fasec_hwtest_0_0_pulseMeasure_118 \fmc_03287_channels[7].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc1[0] [7]),
- .E(\cmp_lengthCounter/RSTP_33 ),
- .Q(\cmp_pulseSync/s_debounce_32 ),
- .SR(rst_i),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] (\s_cmp_lengths[7]_7 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_comparators_i_7(s_comparators_i_7),
- .s_count_reg(\s_datao_fmc1[4] [7]),
- .\s_debounce_reg[1] (s_buff2_i_1__6_n_0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [0]),
- .Q(\s_datao_fmc1[55] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [10]),
- .Q(\s_datao_fmc1[55] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [11]),
- .Q(\s_datao_fmc1[55] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [12]),
- .Q(\s_datao_fmc1[55] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [13]),
- .Q(\s_datao_fmc1[55] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [14]),
- .Q(\s_datao_fmc1[55] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [15]),
- .Q(\s_datao_fmc1[55] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [16]),
- .Q(\s_datao_fmc1[55] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [17]),
- .Q(\s_datao_fmc1[55] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [18]),
- .Q(\s_datao_fmc1[55] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [19]),
- .Q(\s_datao_fmc1[55] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [1]),
- .Q(\s_datao_fmc1[55] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [20]),
- .Q(\s_datao_fmc1[55] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [21]),
- .Q(\s_datao_fmc1[55] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [22]),
- .Q(\s_datao_fmc1[55] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [23]),
- .Q(\s_datao_fmc1[55] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [2]),
- .Q(\s_datao_fmc1[55] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [3]),
- .Q(\s_datao_fmc1[55] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [4]),
- .Q(\s_datao_fmc1[55] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [5]),
- .Q(\s_datao_fmc1[55] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [6]),
- .Q(\s_datao_fmc1[55] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [7]),
- .Q(\s_datao_fmc1[55] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [8]),
- .Q(\s_datao_fmc1[55] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [9]),
- .Q(\s_datao_fmc1[55] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[8].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [8]),
- .IB(\FMC1_LA_N_b[32] [8]),
- .O(s_comparators_i_8));
- system_design_fasec_hwtest_0_0_pulseMeasure_119 \fmc_03287_channels[8].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[0]),
- .E(\cmp_lengthCounter/RSTP_35 ),
- .Q(\cmp_pulseSync/s_debounce_34 ),
- .SR(rst_i),
- .\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] (\s_cmp_lengths[8]_8 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc1[0] [8]),
- .s_comparators_i_8(s_comparators_i_8),
- .\s_debounce_reg[1] (s_buff2_i_1__7_n_0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [0]),
- .Q(\s_datao_fmc1[56] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [10]),
- .Q(\s_datao_fmc1[56] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [11]),
- .Q(\s_datao_fmc1[56] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [12]),
- .Q(\s_datao_fmc1[56] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [13]),
- .Q(\s_datao_fmc1[56] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [14]),
- .Q(\s_datao_fmc1[56] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [15]),
- .Q(\s_datao_fmc1[56] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [16]),
- .Q(\s_datao_fmc1[56] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [17]),
- .Q(\s_datao_fmc1[56] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [18]),
- .Q(\s_datao_fmc1[56] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [19]),
- .Q(\s_datao_fmc1[56] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [1]),
- .Q(\s_datao_fmc1[56] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [20]),
- .Q(\s_datao_fmc1[56] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [21]),
- .Q(\s_datao_fmc1[56] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [22]),
- .Q(\s_datao_fmc1[56] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [23]),
- .Q(\s_datao_fmc1[56] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [2]),
- .Q(\s_datao_fmc1[56] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [3]),
- .Q(\s_datao_fmc1[56] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [4]),
- .Q(\s_datao_fmc1[56] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [5]),
- .Q(\s_datao_fmc1[56] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [6]),
- .Q(\s_datao_fmc1[56] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [7]),
- .Q(\s_datao_fmc1[56] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [8]),
- .Q(\s_datao_fmc1[56] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [9]),
- .Q(\s_datao_fmc1[56] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[9].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC1_LA_P_b[32] [9]),
- .IB(\FMC1_LA_N_b[32] [9]),
- .O(s_comparators_i_9));
- system_design_fasec_hwtest_0_0_pulseMeasure_120 \fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure
- (.CO(intr_o0),
- .D(s_count_reg[1]),
- .E(\cmp_lengthCounter/RSTP_37 ),
- .Q(v_cmpled[11:9]),
- .S({\fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_2 ,\fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_2 ,\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_3 }),
- .SR(rst_i),
- .\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] (\s_cmp_lengths[9]_9 ),
- .intr_led_o_reg(\fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure_n_2 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_36 ),
- .s_buff2_reg_0(\s_datao_fmc1[0] [11:10]),
- .s_buff3_reg(\s_datao_fmc1[0] [9]),
- .s_comparators_i_9(s_comparators_i_9),
- .\s_debounce_reg[1] (s_buff2_i_1__8_n_0),
- .s_pulseLed_reg_0(\fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_3 ),
- .s_pulseLed_reg_1(s_count_reg[3:2]),
- .\v_cmp_reg[11] (v_cmp[11:9]),
- .\v_cmp_reg[18] ({\fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_3 ,\fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_3 ,\fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_3 }),
- .\v_cmp_reg[6] ({\fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_3 ,\fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_3 ,\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_4 }),
- .\v_cmpled_reg[18] ({\fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_2 ,\fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_2 ,\fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_2 }));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [0]),
- .Q(\s_datao_fmc1[57] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [10]),
- .Q(\s_datao_fmc1[57] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [11]),
- .Q(\s_datao_fmc1[57] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [12]),
- .Q(\s_datao_fmc1[57] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [13]),
- .Q(\s_datao_fmc1[57] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [14]),
- .Q(\s_datao_fmc1[57] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [15]),
- .Q(\s_datao_fmc1[57] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [16]),
- .Q(\s_datao_fmc1[57] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [17]),
- .Q(\s_datao_fmc1[57] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [18]),
- .Q(\s_datao_fmc1[57] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [19]),
- .Q(\s_datao_fmc1[57] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [1]),
- .Q(\s_datao_fmc1[57] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [20]),
- .Q(\s_datao_fmc1[57] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [21]),
- .Q(\s_datao_fmc1[57] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [22]),
- .Q(\s_datao_fmc1[57] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [23]),
- .Q(\s_datao_fmc1[57] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [2]),
- .Q(\s_datao_fmc1[57] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [3]),
- .Q(\s_datao_fmc1[57] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [4]),
- .Q(\s_datao_fmc1[57] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [5]),
- .Q(\s_datao_fmc1[57] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [6]),
- .Q(\s_datao_fmc1[57] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [7]),
- .Q(\s_datao_fmc1[57] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [8]),
- .Q(\s_datao_fmc1[57] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [9]),
- .Q(\s_datao_fmc1[57] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[0].gen_outs.cmp_OBUFDS_fmc
- (.I(D[0]),
- .O(\FMC1_LA_P_b[27] [0]),
- .OB(\FMC1_LA_N_b[27] [0]));
- system_design_fasec_hwtest_0_0_pulseMeasure_121 \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure
- (.D(D[0]),
- .Q(\s_datao_fmc1[6] [0]),
- .SR(rst_i),
- .\axi_araddr_reg[2]_rep__3 (\axi_araddr_reg[2]_rep__3 ),
- .\axi_araddr_reg[3]_rep__3 (\axi_araddr_reg[3]_rep__3 ),
- .\axi_rdata_reg[0] (\axi_rdata_reg[0] ),
- .intr_led_o_reg(\fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_3 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_38 ),
- .s_buff3_reg(\fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .\s_datao_fmc1[5] (\s_datao_fmc1[5] [0]),
- .\s_debounce_reg[1] (s_buff2_i_1__19_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc1[4] [0]),
- .s_pulseLed_reg_1(\s_datao_fmc1[5] [2:1]),
- .\v_outleds_reg[2] (v_outleds[2:0]));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[1].gen_outs.cmp_OBUFDS_fmc
- (.I(D[1]),
- .O(\FMC1_LA_P_b[27] [1]),
- .OB(\FMC1_LA_N_b[27] [1]));
- system_design_fasec_hwtest_0_0_pulseMeasure_122 \fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure
- (.D(D[1]),
- .Q(\s_datao_fmc1[6] [1]),
- .SR(rst_i),
- .\axi_araddr_reg[2]_rep__3 (\axi_araddr_reg[2]_rep__3 ),
- .\axi_araddr_reg[3]_rep__3 (\axi_araddr_reg[3]_rep__3 ),
- .\axi_rdata_reg[1] (\axi_rdata_reg[1] ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_39 ),
- .s_buff3_reg(\fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .s_count_reg(\s_datao_fmc1[5] [1]),
- .\s_debounce_reg[1] (s_buff2_i_1__20_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc1[4] [1]));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[2].gen_outs.cmp_OBUFDS_fmc
- (.I(D[2]),
- .O(\FMC1_LA_P_b[27] [2]),
- .OB(\FMC1_LA_N_b[27] [2]));
- system_design_fasec_hwtest_0_0_pulseMeasure_123 \fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure
- (.D(D[2]),
- .Q(\s_datao_fmc1[6] [2]),
- .SR(rst_i),
- .\axi_araddr_reg[2]_rep__3 (\axi_araddr_reg[2]_rep__3 ),
- .\axi_araddr_reg[3]_rep__3 (\axi_araddr_reg[3]_rep__3 ),
- .\axi_rdata_reg[2] (\axi_rdata_reg[2] ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_40 ),
- .s_buff3_reg(\fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .s_count_reg(\s_datao_fmc1[5] [2]),
- .\s_debounce_reg[1] (s_buff2_i_1__21_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc1[4] [2]));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[3].gen_outs.cmp_OBUFDS_fmc
- (.I(D[3]),
- .O(\FMC1_LA_P_b[27] [3]),
- .OB(\FMC1_LA_N_b[27] [3]));
- system_design_fasec_hwtest_0_0_pulseMeasure_124 \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure
- (.D(D[3]),
- .Q(\s_datao_fmc1[6] [3]),
- .SR(rst_i),
- .\axi_araddr_reg[2]_rep__2 (\axi_araddr_reg[2]_rep__2 ),
- .\axi_araddr_reg[3]_rep__2 (\axi_araddr_reg[3]_rep__2 ),
- .\axi_rdata_reg[3] (\axi_rdata_reg[3] ),
- .intr_led_o_reg(\fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_3 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_41 ),
- .s_buff3_reg(\fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .\s_datao_fmc1[5] (\s_datao_fmc1[5] [3]),
- .\s_debounce_reg[1] (s_buff2_i_1__22_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc1[4] [3]),
- .s_pulseLed_reg_1(\s_datao_fmc1[5] [5:4]),
- .\v_outleds_reg[5] (v_outleds[5:3]));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[4].gen_outs.cmp_OBUFDS_fmc
- (.I(s_diffouts_o[4]),
- .O(\FMC1_LA_P_b[27] [4]),
- .OB(\FMC1_LA_N_b[27] [4]));
- system_design_fasec_hwtest_0_0_pulseMeasure_125 \fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure
- (.D(\s_datao_fmc1[4] [4]),
- .Q(s_diffouts_o[4]),
- .SR(rst_i),
- .\axi_araddr_reg[2]_rep__2 (\axi_araddr_reg[2]_rep__2 ),
- .\axi_araddr_reg[3]_rep__2 (\axi_araddr_reg[3]_rep__2 ),
- .\axi_rdata_reg[4] (\axi_rdata_reg[4] ),
- .\data_o_reg[6][4] (\s_datao_fmc1[6] [4]),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_42 ),
- .s_buff3_reg(\fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .s_count_reg(\s_datao_fmc1[5] [4]),
- .\s_debounce_reg[1] (s_buff2_i_1__23_n_0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[5].gen_outs.cmp_OBUFDS_fmc
- (.I(s_diffouts_o[5]),
- .O(\FMC1_LA_P_b[27] [5]),
- .OB(\FMC1_LA_N_b[27] [5]));
- system_design_fasec_hwtest_0_0_pulseMeasure_126 \fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure
- (.D(\s_datao_fmc1[4] [5]),
- .Q(s_diffouts_o[5]),
- .SR(rst_i),
- .\axi_araddr_reg[2]_rep__2 (\axi_araddr_reg[2]_rep__2 ),
- .\axi_araddr_reg[3]_rep__2 (\axi_araddr_reg[3]_rep__2 ),
- .\axi_rdata_reg[5] (\axi_rdata_reg[5] ),
- .\data_o_reg[6][5] (\s_datao_fmc1[6] [5]),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_43 ),
- .s_buff3_reg(\fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .s_count_reg(\s_datao_fmc1[5] [5]),
- .\s_debounce_reg[1] (s_buff2_i_1__24_n_0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[6].gen_outs.cmp_OBUFDS_fmc
- (.I(s_diffouts_o[6]),
- .O(\FMC1_LA_P_b[27] [6]),
- .OB(\FMC1_LA_N_b[27] [6]));
- system_design_fasec_hwtest_0_0_pulseMeasure_127 \fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure
- (.D(\s_datao_fmc1[4] [6]),
- .Q(s_diffouts_o[6]),
- .SR(rst_i),
- .\axi_araddr_reg[2]_rep__2 (\axi_araddr_reg[2]_rep__2 ),
- .\axi_araddr_reg[3]_rep__2 (\axi_araddr_reg[3]_rep__2 ),
- .\axi_rdata_reg[6] (\axi_rdata_reg[6] ),
- .\data_o_reg[6][6] (\s_datao_fmc1[6] [6]),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_44 ),
- .s_buff3_reg(\fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .\s_datao_fmc1[5] (\s_datao_fmc1[5] [6]),
- .\s_debounce_reg[1] (s_buff2_i_1__25_n_0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[7].gen_outs.cmp_OBUFDS_fmc
- (.I(s_diffouts_o[7]),
- .O(\FMC1_LA_P_b[27] [7]),
- .OB(\FMC1_LA_N_b[27] [7]));
- system_design_fasec_hwtest_0_0_pulseMeasure_128 \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure
- (.D(\s_datao_fmc1[4] [7]),
- .Q(s_diffouts_o[7]),
- .SR(rst_i),
- .\axi_araddr_reg[2]_rep__2 (\axi_araddr_reg[2]_rep__2 ),
- .\axi_araddr_reg[3]_rep__2 (\axi_araddr_reg[3]_rep__2 ),
- .\axi_rdata_reg[7] (\axi_rdata_reg[7] ),
- .\data_o_reg[6][7] (\s_datao_fmc1[6] [7]),
- .intr_led_o_reg(\fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_3 ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_45 ),
- .s_buff3_reg(\fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .\s_datao_fmc1[5] (\s_datao_fmc1[5] [7]),
- .\s_debounce_reg[1] (s_buff2_i_1__26_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc1[5] [6]),
- .\v_outleds_reg[0] (\fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_3 ),
- .\v_outleds_reg[3] (\fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_3 ),
- .\v_outleds_reg[7] (v_outleds[7:6]));
- system_design_fasec_hwtest_0_0_dac7716_spi_129 \gen_spi.cmp_dac7716_spi
- (.CO(CO),
- .D(spi_sdo_i),
- .Q(Q),
- .SR(rst_i),
- .\axi_rdata_reg[31] (\axi_rdata_reg[31] ),
- .\dac_ch_o_reg[0][0]_0 (\gen_spi.cmp_dac7716_spi_n_1 ),
- .\dac_ch_o_reg[0][0]_1 (\gen_spi.cmp_dac7716_spi_n_2 ),
- .\data_rw_o_reg[11][2] (\data_rw_o_reg[11][7] [1:0]),
- .\data_rw_o_reg[16][11] (\data_rw_o_reg[16][11] ),
- .\data_rw_o_reg[16][11]_0 (\data_rw_o_reg[16][11]_0 ),
- .\data_rw_o_reg[17][11] (\data_rw_o_reg[17][11] ),
- .\data_rw_o_reg[17][11]_0 (\data_rw_o_reg[17][11]_0 ),
- .\data_rw_o_reg[18][11] (\data_rw_o_reg[18][11] ),
- .\data_rw_o_reg[18][11]_0 (\data_rw_o_reg[18][11]_0 ),
- .\data_rw_o_reg[19][11] (\data_rw_o_reg[19][11] ),
- .\data_rw_o_reg[20][11] (\data_rw_o_reg[20][11] ),
- .\data_rw_o_reg[20][11]_0 (\data_rw_o_reg[20][11]_0 ),
- .\data_rw_o_reg[21][11] (\data_rw_o_reg[21][11] ),
- .\data_rw_o_reg[21][11]_0 (\data_rw_o_reg[21][11]_0 ),
- .\data_rw_o_reg[22][11] (\data_rw_o_reg[22][11] ),
- .\data_rw_o_reg[22][11]_0 (\data_rw_o_reg[22][11]_0 ),
- .\data_rw_o_reg[23][11] (\data_rw_o_reg[23][11] ),
- .\data_rw_o_reg[23][11]_0 (\data_rw_o_reg[23][11]_0 ),
- .\data_rw_o_reg[24][11] (\data_rw_o_reg[24][11] ),
- .\data_rw_o_reg[25][11] (\data_rw_o_reg[25][11] ),
- .\data_rw_o_reg[26][11] (\data_rw_o_reg[26][11] ),
- .\data_rw_o_reg[27][11] (\data_rw_o_reg[27][11] ),
- .\data_rw_o_reg[28][11] (\data_rw_o_reg[28][11] ),
- .\data_rw_o_reg[29][11] (\data_rw_o_reg[29][11] ),
- .\data_rw_o_reg[30][11] (\data_rw_o_reg[30][11] ),
- .\data_rw_o_reg[31][11] (\data_rw_o_reg[31][11] ),
- .\data_rw_o_reg[32][11] (\data_rw_o_reg[32][11] ),
- .\data_rw_o_reg[33][11] (\data_rw_o_reg[33][11] ),
- .\data_rw_o_reg[34][11] (\data_rw_o_reg[34][11] ),
- .\data_rw_o_reg[35][11] (\data_rw_o_reg[35][11] ),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .\s_counter_reg[2] (s_spi_sclk),
- .s_spi_cs_n(s_spi_cs_n),
- .s_spi_mosi(s_spi_mosi),
- .s_start(s_start),
- .s_start_reg_0(s_start_i_1_n_0),
- .\s_tx_data_reg[111]_0 (\s_tx_data_reg[111] ),
- .\s_tx_data_reg[15]_0 (\s_tx_data_reg[15] ),
- .\s_tx_data_reg[15]_1 (\s_tx_data_reg[15]_0 ),
- .\s_tx_data_reg[39]_0 (\s_tx_data_reg[39] ),
- .\s_tx_data_reg[39]_1 (\s_tx_data_reg[39]_0 ),
- .\s_tx_data_reg[39]_2 (\s_tx_data_reg[39]_1 ),
- .\s_tx_data_reg[39]_3 (\s_tx_data_reg[39]_2 ));
- (* box_type = "PRIMITIVE" *)
- IOBUF #(
- .IOSTANDARD("DEFAULT"))
- \gen_spi.cmp_spi_cs_n_iobuf
- (.I(s_spi_cs_n),
- .IO(FMC1_LA_N_b[1]),
- .O(\NLW_gen_spi.cmp_spi_cs_n_iobuf_O_UNCONNECTED ),
- .T(1'b0));
- (* box_type = "PRIMITIVE" *)
- IOBUF #(
- .IOSTANDARD("DEFAULT"))
- \gen_spi.cmp_spi_miso_iobuf
- (.I(1'b0),
- .IO(FMC1_LA_P_b[1]),
- .O(spi_sdo_i),
- .T(1'b1));
- (* box_type = "PRIMITIVE" *)
- IOBUF #(
- .IOSTANDARD("DEFAULT"))
- \gen_spi.cmp_spi_mosi_iobuf
- (.I(s_spi_mosi),
- .IO(FMC1_LA_N_b[0]),
- .O(\NLW_gen_spi.cmp_spi_mosi_iobuf_O_UNCONNECTED ),
- .T(1'b0));
- (* box_type = "PRIMITIVE" *)
- IOBUF #(
- .IOSTANDARD("DEFAULT"))
- \gen_spi.cmp_spi_sclk_iobuf
- (.I(s_spi_sclk),
- .IO(FMC1_LA_P_b[0]),
- .O(\NLW_gen_spi.cmp_spi_sclk_iobuf_O_UNCONNECTED ),
- .T(1'b0));
- LUT2 #(
- .INIT(4'hE))
- intr_led_o_INST_0
- (.I0(fmc1_intr_led),
- .I1(fmc2_intr_led),
- .O(intr_led_o));
- FDRE intr_led_o_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure_n_2 ),
- .Q(fmc1_intr_led),
- .R(1'b0));
- LUT2 #(
- .INIT(4'hE))
- intr_o_INST_0
- (.I0(fmc1_intr),
- .I1(fmc2_intr),
- .O(intr_o));
- FDRE intr_o_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(intr_o0),
- .Q(fmc1_intr),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1
- (.I0(\cmp_pulseSync/s_debounce [1]),
- .I1(\cmp_pulseSync/s_debounce [0]),
- .I2(\cmp_pulseSync/s_debounce [4]),
- .I3(\cmp_pulseSync/s_debounce [3]),
- .I4(\cmp_pulseSync/s_debounce [2]),
- .I5(\s_datao_fmc1[0] [0]),
- .O(s_buff2_i_1_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__0
- (.I0(\cmp_pulseSync/s_debounce_20 [1]),
- .I1(\cmp_pulseSync/s_debounce_20 [0]),
- .I2(\cmp_pulseSync/s_debounce_20 [4]),
- .I3(\cmp_pulseSync/s_debounce_20 [3]),
- .I4(\cmp_pulseSync/s_debounce_20 [2]),
- .I5(\s_datao_fmc1[0] [1]),
- .O(s_buff2_i_1__0_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__1
- (.I0(\cmp_pulseSync/s_debounce_22 [1]),
- .I1(\cmp_pulseSync/s_debounce_22 [0]),
- .I2(\cmp_pulseSync/s_debounce_22 [4]),
- .I3(\cmp_pulseSync/s_debounce_22 [3]),
- .I4(\cmp_pulseSync/s_debounce_22 [2]),
- .I5(\s_datao_fmc1[0] [2]),
- .O(s_buff2_i_1__1_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__10
- (.I0(\cmp_pulseSync/s_debounce_2 [1]),
- .I1(\cmp_pulseSync/s_debounce_2 [0]),
- .I2(\cmp_pulseSync/s_debounce_2 [4]),
- .I3(\cmp_pulseSync/s_debounce_2 [3]),
- .I4(\cmp_pulseSync/s_debounce_2 [2]),
- .I5(\s_datao_fmc1[0] [11]),
- .O(s_buff2_i_1__10_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__11
- (.I0(\cmp_pulseSync/s_debounce_4 [1]),
- .I1(\cmp_pulseSync/s_debounce_4 [0]),
- .I2(\cmp_pulseSync/s_debounce_4 [4]),
- .I3(\cmp_pulseSync/s_debounce_4 [3]),
- .I4(\cmp_pulseSync/s_debounce_4 [2]),
- .I5(\s_datao_fmc1[0] [12]),
- .O(s_buff2_i_1__11_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__12
- (.I0(\cmp_pulseSync/s_debounce_6 [1]),
- .I1(\cmp_pulseSync/s_debounce_6 [0]),
- .I2(\cmp_pulseSync/s_debounce_6 [4]),
- .I3(\cmp_pulseSync/s_debounce_6 [3]),
- .I4(\cmp_pulseSync/s_debounce_6 [2]),
- .I5(\s_datao_fmc1[0] [13]),
- .O(s_buff2_i_1__12_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__13
- (.I0(\cmp_pulseSync/s_debounce_8 [1]),
- .I1(\cmp_pulseSync/s_debounce_8 [0]),
- .I2(\cmp_pulseSync/s_debounce_8 [4]),
- .I3(\cmp_pulseSync/s_debounce_8 [3]),
- .I4(\cmp_pulseSync/s_debounce_8 [2]),
- .I5(\s_datao_fmc1[0] [14]),
- .O(s_buff2_i_1__13_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__14
- (.I0(\cmp_pulseSync/s_debounce_10 [1]),
- .I1(\cmp_pulseSync/s_debounce_10 [0]),
- .I2(\cmp_pulseSync/s_debounce_10 [4]),
- .I3(\cmp_pulseSync/s_debounce_10 [3]),
- .I4(\cmp_pulseSync/s_debounce_10 [2]),
- .I5(\s_datao_fmc1[0] [15]),
- .O(s_buff2_i_1__14_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__15
- (.I0(\cmp_pulseSync/s_debounce_12 [1]),
- .I1(\cmp_pulseSync/s_debounce_12 [0]),
- .I2(\cmp_pulseSync/s_debounce_12 [4]),
- .I3(\cmp_pulseSync/s_debounce_12 [3]),
- .I4(\cmp_pulseSync/s_debounce_12 [2]),
- .I5(\s_datao_fmc1[0] [16]),
- .O(s_buff2_i_1__15_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__16
- (.I0(\cmp_pulseSync/s_debounce_14 [1]),
- .I1(\cmp_pulseSync/s_debounce_14 [0]),
- .I2(\cmp_pulseSync/s_debounce_14 [4]),
- .I3(\cmp_pulseSync/s_debounce_14 [3]),
- .I4(\cmp_pulseSync/s_debounce_14 [2]),
- .I5(\s_datao_fmc1[0] [17]),
- .O(s_buff2_i_1__16_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__17
- (.I0(\cmp_pulseSync/s_debounce_16 [1]),
- .I1(\cmp_pulseSync/s_debounce_16 [0]),
- .I2(\cmp_pulseSync/s_debounce_16 [4]),
- .I3(\cmp_pulseSync/s_debounce_16 [3]),
- .I4(\cmp_pulseSync/s_debounce_16 [2]),
- .I5(\s_datao_fmc1[0] [18]),
- .O(s_buff2_i_1__17_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__18
- (.I0(\cmp_pulseSync/s_debounce_18 [1]),
- .I1(\cmp_pulseSync/s_debounce_18 [0]),
- .I2(\cmp_pulseSync/s_debounce_18 [4]),
- .I3(\cmp_pulseSync/s_debounce_18 [3]),
- .I4(\cmp_pulseSync/s_debounce_18 [2]),
- .I5(\s_datao_fmc1[0] [19]),
- .O(s_buff2_i_1__18_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__19
- (.I0(\cmp_pulseSync/s_debounce_38 [1]),
- .I1(\cmp_pulseSync/s_debounce_38 [0]),
- .I2(\cmp_pulseSync/s_debounce_38 [4]),
- .I3(\cmp_pulseSync/s_debounce_38 [3]),
- .I4(\cmp_pulseSync/s_debounce_38 [2]),
- .I5(\fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__19_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__2
- (.I0(\cmp_pulseSync/s_debounce_24 [1]),
- .I1(\cmp_pulseSync/s_debounce_24 [0]),
- .I2(\cmp_pulseSync/s_debounce_24 [4]),
- .I3(\cmp_pulseSync/s_debounce_24 [3]),
- .I4(\cmp_pulseSync/s_debounce_24 [2]),
- .I5(\s_datao_fmc1[0] [3]),
- .O(s_buff2_i_1__2_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__20
- (.I0(\cmp_pulseSync/s_debounce_39 [1]),
- .I1(\cmp_pulseSync/s_debounce_39 [0]),
- .I2(\cmp_pulseSync/s_debounce_39 [4]),
- .I3(\cmp_pulseSync/s_debounce_39 [3]),
- .I4(\cmp_pulseSync/s_debounce_39 [2]),
- .I5(\fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__20_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__21
- (.I0(\cmp_pulseSync/s_debounce_40 [1]),
- .I1(\cmp_pulseSync/s_debounce_40 [0]),
- .I2(\cmp_pulseSync/s_debounce_40 [4]),
- .I3(\cmp_pulseSync/s_debounce_40 [3]),
- .I4(\cmp_pulseSync/s_debounce_40 [2]),
- .I5(\fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__21_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__22
- (.I0(\cmp_pulseSync/s_debounce_41 [1]),
- .I1(\cmp_pulseSync/s_debounce_41 [0]),
- .I2(\cmp_pulseSync/s_debounce_41 [4]),
- .I3(\cmp_pulseSync/s_debounce_41 [3]),
- .I4(\cmp_pulseSync/s_debounce_41 [2]),
- .I5(\fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__22_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__23
- (.I0(\cmp_pulseSync/s_debounce_42 [1]),
- .I1(\cmp_pulseSync/s_debounce_42 [0]),
- .I2(\cmp_pulseSync/s_debounce_42 [4]),
- .I3(\cmp_pulseSync/s_debounce_42 [3]),
- .I4(\cmp_pulseSync/s_debounce_42 [2]),
- .I5(\fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__23_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__24
- (.I0(\cmp_pulseSync/s_debounce_43 [1]),
- .I1(\cmp_pulseSync/s_debounce_43 [0]),
- .I2(\cmp_pulseSync/s_debounce_43 [4]),
- .I3(\cmp_pulseSync/s_debounce_43 [3]),
- .I4(\cmp_pulseSync/s_debounce_43 [2]),
- .I5(\fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__24_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__25
- (.I0(\cmp_pulseSync/s_debounce_44 [1]),
- .I1(\cmp_pulseSync/s_debounce_44 [0]),
- .I2(\cmp_pulseSync/s_debounce_44 [4]),
- .I3(\cmp_pulseSync/s_debounce_44 [3]),
- .I4(\cmp_pulseSync/s_debounce_44 [2]),
- .I5(\fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__25_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__26
- (.I0(\cmp_pulseSync/s_debounce_45 [1]),
- .I1(\cmp_pulseSync/s_debounce_45 [0]),
- .I2(\cmp_pulseSync/s_debounce_45 [4]),
- .I3(\cmp_pulseSync/s_debounce_45 [3]),
- .I4(\cmp_pulseSync/s_debounce_45 [2]),
- .I5(\fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__26_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__3
- (.I0(\cmp_pulseSync/s_debounce_26 [1]),
- .I1(\cmp_pulseSync/s_debounce_26 [0]),
- .I2(\cmp_pulseSync/s_debounce_26 [4]),
- .I3(\cmp_pulseSync/s_debounce_26 [3]),
- .I4(\cmp_pulseSync/s_debounce_26 [2]),
- .I5(\s_datao_fmc1[0] [4]),
- .O(s_buff2_i_1__3_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__4
- (.I0(\cmp_pulseSync/s_debounce_28 [1]),
- .I1(\cmp_pulseSync/s_debounce_28 [0]),
- .I2(\cmp_pulseSync/s_debounce_28 [4]),
- .I3(\cmp_pulseSync/s_debounce_28 [3]),
- .I4(\cmp_pulseSync/s_debounce_28 [2]),
- .I5(\s_datao_fmc1[0] [5]),
- .O(s_buff2_i_1__4_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__5
- (.I0(\cmp_pulseSync/s_debounce_30 [1]),
- .I1(\cmp_pulseSync/s_debounce_30 [0]),
- .I2(\cmp_pulseSync/s_debounce_30 [4]),
- .I3(\cmp_pulseSync/s_debounce_30 [3]),
- .I4(\cmp_pulseSync/s_debounce_30 [2]),
- .I5(\s_datao_fmc1[0] [6]),
- .O(s_buff2_i_1__5_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__6
- (.I0(\cmp_pulseSync/s_debounce_32 [1]),
- .I1(\cmp_pulseSync/s_debounce_32 [0]),
- .I2(\cmp_pulseSync/s_debounce_32 [4]),
- .I3(\cmp_pulseSync/s_debounce_32 [3]),
- .I4(\cmp_pulseSync/s_debounce_32 [2]),
- .I5(\s_datao_fmc1[0] [7]),
- .O(s_buff2_i_1__6_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__7
- (.I0(\cmp_pulseSync/s_debounce_34 [1]),
- .I1(\cmp_pulseSync/s_debounce_34 [0]),
- .I2(\cmp_pulseSync/s_debounce_34 [4]),
- .I3(\cmp_pulseSync/s_debounce_34 [3]),
- .I4(\cmp_pulseSync/s_debounce_34 [2]),
- .I5(\s_datao_fmc1[0] [8]),
- .O(s_buff2_i_1__7_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__8
- (.I0(\cmp_pulseSync/s_debounce_36 [1]),
- .I1(\cmp_pulseSync/s_debounce_36 [0]),
- .I2(\cmp_pulseSync/s_debounce_36 [4]),
- .I3(\cmp_pulseSync/s_debounce_36 [3]),
- .I4(\cmp_pulseSync/s_debounce_36 [2]),
- .I5(\s_datao_fmc1[0] [9]),
- .O(s_buff2_i_1__8_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__9
- (.I0(\cmp_pulseSync/s_debounce_0 [1]),
- .I1(\cmp_pulseSync/s_debounce_0 [0]),
- .I2(\cmp_pulseSync/s_debounce_0 [4]),
- .I3(\cmp_pulseSync/s_debounce_0 [3]),
- .I4(\cmp_pulseSync/s_debounce_0 [2]),
- .I5(\s_datao_fmc1[0] [10]),
- .O(s_buff2_i_1__9_n_0));
- FDRE \s_diffouts_o_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_dout[4]),
- .Q(s_diffouts_o[4]),
- .R(1'b0));
- FDRE \s_diffouts_o_reg[5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_dout[5]),
- .Q(s_diffouts_o[5]),
- .R(1'b0));
- FDRE \s_diffouts_o_reg[6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_dout[6]),
- .Q(s_diffouts_o[6]),
- .R(1'b0));
- FDRE \s_diffouts_o_reg[7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_dout[7]),
- .Q(s_diffouts_o[7]),
- .R(1'b0));
- LUT3 #(
- .INIT(8'hB8))
- s_start_i_1
- (.I0(s_start),
- .I1(\gen_spi.cmp_dac7716_spi_n_2 ),
- .I2(\gen_spi.cmp_dac7716_spi_n_1 ),
- .O(s_start_i_1_n_0));
- FDRE \v_cmp_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [0]),
- .Q(v_cmp[0]),
- .R(1'b0));
- FDRE \v_cmp_reg[10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [10]),
- .Q(v_cmp[10]),
- .R(1'b0));
- FDRE \v_cmp_reg[11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [11]),
- .Q(v_cmp[11]),
- .R(1'b0));
- FDRE \v_cmp_reg[12]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [12]),
- .Q(v_cmp[12]),
- .R(1'b0));
- FDRE \v_cmp_reg[13]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [13]),
- .Q(v_cmp[13]),
- .R(1'b0));
- FDRE \v_cmp_reg[14]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [14]),
- .Q(v_cmp[14]),
- .R(1'b0));
- FDRE \v_cmp_reg[15]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [15]),
- .Q(v_cmp[15]),
- .R(1'b0));
- FDRE \v_cmp_reg[16]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [16]),
- .Q(v_cmp[16]),
- .R(1'b0));
- FDRE \v_cmp_reg[17]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [17]),
- .Q(v_cmp[17]),
- .R(1'b0));
- FDRE \v_cmp_reg[18]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [18]),
- .Q(v_cmp[18]),
- .R(1'b0));
- FDRE \v_cmp_reg[19]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [19]),
- .Q(v_cmp[19]),
- .R(1'b0));
- FDRE \v_cmp_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [1]),
- .Q(v_cmp[1]),
- .R(1'b0));
- FDRE \v_cmp_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [2]),
- .Q(v_cmp[2]),
- .R(1'b0));
- FDRE \v_cmp_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [3]),
- .Q(v_cmp[3]),
- .R(1'b0));
- FDRE \v_cmp_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [4]),
- .Q(v_cmp[4]),
- .R(1'b0));
- FDRE \v_cmp_reg[5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [5]),
- .Q(v_cmp[5]),
- .R(1'b0));
- FDRE \v_cmp_reg[6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [6]),
- .Q(v_cmp[6]),
- .R(1'b0));
- FDRE \v_cmp_reg[7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [7]),
- .Q(v_cmp[7]),
- .R(1'b0));
- FDRE \v_cmp_reg[8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [8]),
- .Q(v_cmp[8]),
- .R(1'b0));
- FDRE \v_cmp_reg[9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[0] [9]),
- .Q(v_cmp[9]),
- .R(1'b0));
- FDRE \v_cmpled_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[4] [0]),
- .Q(v_cmpled[0]),
- .R(1'b0));
- FDRE \v_cmpled_reg[10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[2]),
- .Q(v_cmpled[10]),
- .R(1'b0));
- FDRE \v_cmpled_reg[11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[3]),
- .Q(v_cmpled[11]),
- .R(1'b0));
- FDRE \v_cmpled_reg[12]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[4]),
- .Q(v_cmpled[12]),
- .R(1'b0));
- FDRE \v_cmpled_reg[13]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[5]),
- .Q(v_cmpled[13]),
- .R(1'b0));
- FDRE \v_cmpled_reg[14]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[6]),
- .Q(v_cmpled[14]),
- .R(1'b0));
- FDRE \v_cmpled_reg[15]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[7]),
- .Q(v_cmpled[15]),
- .R(1'b0));
- FDRE \v_cmpled_reg[16]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[8]),
- .Q(v_cmpled[16]),
- .R(1'b0));
- FDRE \v_cmpled_reg[17]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[9]),
- .Q(v_cmpled[17]),
- .R(1'b0));
- FDRE \v_cmpled_reg[18]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[10]),
- .Q(v_cmpled[18]),
- .R(1'b0));
- FDRE \v_cmpled_reg[19]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[11]),
- .Q(v_cmpled[19]),
- .R(1'b0));
- FDRE \v_cmpled_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[4] [1]),
- .Q(v_cmpled[1]),
- .R(1'b0));
- FDRE \v_cmpled_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[4] [2]),
- .Q(v_cmpled[2]),
- .R(1'b0));
- FDRE \v_cmpled_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[4] [3]),
- .Q(v_cmpled[3]),
- .R(1'b0));
- FDRE \v_cmpled_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[4] [4]),
- .Q(v_cmpled[4]),
- .R(1'b0));
- FDRE \v_cmpled_reg[5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[4] [5]),
- .Q(v_cmpled[5]),
- .R(1'b0));
- FDRE \v_cmpled_reg[6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[4] [6]),
- .Q(v_cmpled[6]),
- .R(1'b0));
- FDRE \v_cmpled_reg[7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[4] [7]),
- .Q(v_cmpled[7]),
- .R(1'b0));
- FDRE \v_cmpled_reg[8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[0]),
- .Q(v_cmpled[8]),
- .R(1'b0));
- FDRE \v_cmpled_reg[9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[1]),
- .Q(v_cmpled[9]),
- .R(1'b0));
- FDSE \v_dout_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[10][4] ),
- .Q(v_dout[4]),
- .S(\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2 ));
- FDSE \v_dout_reg[5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[10][5] ),
- .Q(v_dout[5]),
- .S(\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2 ));
- FDSE \v_dout_reg[6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[10][6] ),
- .Q(v_dout[6]),
- .S(\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2 ));
- FDSE \v_dout_reg[7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[10][7] ),
- .Q(v_dout[7]),
- .S(\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2 ));
- FDRE \v_fbd_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\FMC1_LA_N_b[32] [21]),
- .Q(v_fbd[0]),
- .R(1'b0));
- FDRE \v_fbd_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\FMC1_LA_P_b[32] [21]),
- .Q(v_fbd[1]),
- .R(1'b0));
- FDRE \v_fbd_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\FMC1_LA_N_b[32] [20]),
- .Q(v_fbd[2]),
- .R(1'b0));
- FDRE \v_fbd_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\FMC1_LA_P_b[32] [20]),
- .Q(v_fbd[3]),
- .R(1'b0));
- FDRE \v_outleds_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[5] [0]),
- .Q(v_outleds[0]),
- .R(1'b0));
- FDRE \v_outleds_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[5] [1]),
- .Q(v_outleds[1]),
- .R(1'b0));
- FDRE \v_outleds_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[5] [2]),
- .Q(v_outleds[2]),
- .R(1'b0));
- FDRE \v_outleds_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[5] [3]),
- .Q(v_outleds[3]),
- .R(1'b0));
- FDRE \v_outleds_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[5] [4]),
- .Q(v_outleds[4]),
- .R(1'b0));
- FDRE \v_outleds_reg[5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[5] [5]),
- .Q(v_outleds[5]),
- .R(1'b0));
- FDRE \v_outleds_reg[6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[5] [6]),
- .Q(v_outleds[6]),
- .R(1'b0));
- FDRE \v_outleds_reg[7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc1[5] [7]),
- .Q(v_outleds[7]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "general_fmc" *)
-module system_design_fasec_hwtest_0_0_general_fmc_0
- (\FMC2_LA_P_b[27] ,
- \FMC2_LA_N_b[27] ,
- fmc2_intr,
- fmc2_intr_led,
- Q,
- \s_tx_data_reg[111] ,
- \s_tx_data_reg[15] ,
- \s_tx_data_reg[15]_0 ,
- \s_tx_data_reg[39] ,
- \s_tx_data_reg[39]_0 ,
- \s_tx_data_reg[39]_1 ,
- \s_tx_data_reg[39]_2 ,
- \axi_rdata_reg[0] ,
- s_count_reg,
- \axi_rdata_reg[0]_0 ,
- \axi_rdata_reg[0]_1 ,
- \axi_rdata_reg[1] ,
- \axi_rdata_reg[1]_0 ,
- \axi_rdata_reg[1]_1 ,
- \axi_rdata_reg[2] ,
- \axi_rdata_reg[2]_0 ,
- \axi_rdata_reg[2]_1 ,
- \axi_rdata_reg[3] ,
- \axi_rdata_reg[3]_0 ,
- \axi_rdata_reg[3]_1 ,
- \axi_rdata_reg[4] ,
- \axi_rdata_reg[4]_0 ,
- \axi_rdata_reg[4]_1 ,
- \axi_rdata_reg[5] ,
- \axi_rdata_reg[5]_0 ,
- \axi_rdata_reg[5]_1 ,
- \axi_rdata_reg[6] ,
- \axi_rdata_reg[6]_0 ,
- \axi_rdata_reg[6]_1 ,
- \axi_rdata_reg[7] ,
- \axi_rdata_reg[7]_0 ,
- \axi_rdata_reg[7]_1 ,
- \axi_rdata_reg[8] ,
- \axi_rdata_reg[8]_0 ,
- \axi_rdata_reg[9] ,
- \axi_rdata_reg[9]_0 ,
- \axi_rdata_reg[10] ,
- \axi_rdata_reg[10]_0 ,
- \axi_rdata_reg[11] ,
- \axi_rdata_reg[11]_0 ,
- \axi_rdata_reg[12] ,
- \axi_rdata_reg[12]_0 ,
- \axi_rdata_reg[13] ,
- \axi_rdata_reg[13]_0 ,
- \axi_rdata_reg[14] ,
- \axi_rdata_reg[14]_0 ,
- \axi_rdata_reg[15] ,
- \axi_rdata_reg[15]_0 ,
- \axi_rdata_reg[16] ,
- \axi_rdata_reg[16]_0 ,
- \axi_rdata_reg[17] ,
- \axi_rdata_reg[17]_0 ,
- \axi_rdata_reg[18] ,
- \axi_rdata_reg[18]_0 ,
- \axi_rdata_reg[19] ,
- \axi_rdata_reg[19]_0 ,
- \axi_rdata_reg[20] ,
- \axi_rdata_reg[20]_0 ,
- \axi_rdata_reg[20]_1 ,
- \axi_rdata_reg[21] ,
- \axi_rdata_reg[21]_0 ,
- \axi_rdata_reg[21]_1 ,
- \axi_rdata_reg[22] ,
- \axi_rdata_reg[22]_0 ,
- \axi_rdata_reg[22]_1 ,
- \axi_rdata_reg[23] ,
- \axi_rdata_reg[23]_0 ,
- \axi_rdata_reg[23]_1 ,
- \s_datao_fmc2[0] ,
- \axi_rdata_reg[31] ,
- \axi_rdata_reg[3]_2 ,
- FMC2_LA_P_b,
- FMC2_LA_N_b,
- \FMC2_LA_P_b[32] ,
- \FMC2_LA_N_b[32] ,
- D,
- rst_i,
- s00_axi_aclk,
- s00_axi_aresetn,
- \data_rw_o_reg[79][7] ,
- \axi_araddr_reg[3]_rep__3 ,
- \axi_araddr_reg[2]_rep__3 ,
- \axi_araddr_reg[5]_rep ,
- \axi_araddr_reg[4]_rep__1 ,
- \axi_araddr_reg[4]_rep__0 ,
- \axi_araddr_reg[3]_rep__2 ,
- \axi_araddr_reg[2]_rep__2 ,
- \axi_araddr_reg[3]_rep__1 ,
- \axi_araddr_reg[2]_rep__1 ,
- \axi_araddr_reg[4]_rep ,
- \axi_araddr_reg[5] ,
- \axi_araddr_reg[3]_rep__0 ,
- \axi_araddr_reg[2]_rep__0 ,
- \axi_araddr_reg[3]_rep ,
- \axi_araddr_reg[2]_rep ,
- \data_rw_o_reg[87][11] ,
- \data_rw_o_reg[87][11]_0 ,
- \data_rw_o_reg[86][11] ,
- \data_rw_o_reg[86][11]_0 ,
- \data_rw_o_reg[85][11] ,
- \data_rw_o_reg[85][11]_0 ,
- \data_rw_o_reg[84][11] ,
- \data_rw_o_reg[84][11]_0 ,
- \data_rw_o_reg[88][11] ,
- \data_rw_o_reg[88][11]_0 ,
- \data_rw_o_reg[89][11] ,
- \data_rw_o_reg[89][11]_0 ,
- \data_rw_o_reg[90][11] ,
- \data_rw_o_reg[90][11]_0 ,
- \data_rw_o_reg[91][11] ,
- \data_rw_o_reg[91][11]_0 ,
- \data_rw_o_reg[92][11] ,
- \data_rw_o_reg[93][11] ,
- \data_rw_o_reg[94][11] ,
- \data_rw_o_reg[95][11] ,
- \data_rw_o_reg[96][11] ,
- \data_rw_o_reg[97][11] ,
- \data_rw_o_reg[98][11] ,
- \data_rw_o_reg[99][11] ,
- \data_rw_o_reg[100][11] ,
- \data_rw_o_reg[101][11] ,
- \data_rw_o_reg[102][11] ,
- \data_rw_o_reg[103][11] ,
- \data_rw_o_reg[78][7] ,
- \data_rw_o_reg[78][6] ,
- \data_rw_o_reg[78][5] ,
- \data_rw_o_reg[78][4] );
- output [7:0]\FMC2_LA_P_b[27] ;
- output [7:0]\FMC2_LA_N_b[27] ;
- output fmc2_intr;
- output fmc2_intr_led;
- output [11:0]Q;
- output [11:0]\s_tx_data_reg[111] ;
- output [11:0]\s_tx_data_reg[15] ;
- output [11:0]\s_tx_data_reg[15]_0 ;
- output [11:0]\s_tx_data_reg[39] ;
- output [11:0]\s_tx_data_reg[39]_0 ;
- output [11:0]\s_tx_data_reg[39]_1 ;
- output [11:0]\s_tx_data_reg[39]_2 ;
- output \axi_rdata_reg[0] ;
- output [11:0]s_count_reg;
- output \axi_rdata_reg[0]_0 ;
- output \axi_rdata_reg[0]_1 ;
- output \axi_rdata_reg[1] ;
- output \axi_rdata_reg[1]_0 ;
- output \axi_rdata_reg[1]_1 ;
- output \axi_rdata_reg[2] ;
- output \axi_rdata_reg[2]_0 ;
- output \axi_rdata_reg[2]_1 ;
- output \axi_rdata_reg[3] ;
- output \axi_rdata_reg[3]_0 ;
- output \axi_rdata_reg[3]_1 ;
- output \axi_rdata_reg[4] ;
- output \axi_rdata_reg[4]_0 ;
- output \axi_rdata_reg[4]_1 ;
- output \axi_rdata_reg[5] ;
- output \axi_rdata_reg[5]_0 ;
- output \axi_rdata_reg[5]_1 ;
- output \axi_rdata_reg[6] ;
- output \axi_rdata_reg[6]_0 ;
- output \axi_rdata_reg[6]_1 ;
- output \axi_rdata_reg[7] ;
- output \axi_rdata_reg[7]_0 ;
- output \axi_rdata_reg[7]_1 ;
- output \axi_rdata_reg[8] ;
- output \axi_rdata_reg[8]_0 ;
- output \axi_rdata_reg[9] ;
- output \axi_rdata_reg[9]_0 ;
- output \axi_rdata_reg[10] ;
- output \axi_rdata_reg[10]_0 ;
- output \axi_rdata_reg[11] ;
- output \axi_rdata_reg[11]_0 ;
- output \axi_rdata_reg[12] ;
- output \axi_rdata_reg[12]_0 ;
- output \axi_rdata_reg[13] ;
- output \axi_rdata_reg[13]_0 ;
- output \axi_rdata_reg[14] ;
- output \axi_rdata_reg[14]_0 ;
- output \axi_rdata_reg[15] ;
- output \axi_rdata_reg[15]_0 ;
- output \axi_rdata_reg[16] ;
- output \axi_rdata_reg[16]_0 ;
- output \axi_rdata_reg[17] ;
- output \axi_rdata_reg[17]_0 ;
- output \axi_rdata_reg[18] ;
- output \axi_rdata_reg[18]_0 ;
- output \axi_rdata_reg[19] ;
- output \axi_rdata_reg[19]_0 ;
- output \axi_rdata_reg[20] ;
- output \axi_rdata_reg[20]_0 ;
- output \axi_rdata_reg[20]_1 ;
- output \axi_rdata_reg[21] ;
- output \axi_rdata_reg[21]_0 ;
- output \axi_rdata_reg[21]_1 ;
- output \axi_rdata_reg[22] ;
- output \axi_rdata_reg[22]_0 ;
- output \axi_rdata_reg[22]_1 ;
- output \axi_rdata_reg[23] ;
- output \axi_rdata_reg[23]_0 ;
- output \axi_rdata_reg[23]_1 ;
- output [19:0]\s_datao_fmc2[0] ;
- output [31:0]\axi_rdata_reg[31] ;
- output [3:0]\axi_rdata_reg[3]_2 ;
- inout [1:0]FMC2_LA_P_b;
- inout [1:0]FMC2_LA_N_b;
- input [21:0]\FMC2_LA_P_b[32] ;
- input [21:0]\FMC2_LA_N_b[32] ;
- input [3:0]D;
- input rst_i;
- input s00_axi_aclk;
- input s00_axi_aresetn;
- input [2:0]\data_rw_o_reg[79][7] ;
- input \axi_araddr_reg[3]_rep__3 ;
- input \axi_araddr_reg[2]_rep__3 ;
- input \axi_araddr_reg[5]_rep ;
- input \axi_araddr_reg[4]_rep__1 ;
- input \axi_araddr_reg[4]_rep__0 ;
- input \axi_araddr_reg[3]_rep__2 ;
- input \axi_araddr_reg[2]_rep__2 ;
- input \axi_araddr_reg[3]_rep__1 ;
- input \axi_araddr_reg[2]_rep__1 ;
- input \axi_araddr_reg[4]_rep ;
- input [3:0]\axi_araddr_reg[5] ;
- input \axi_araddr_reg[3]_rep__0 ;
- input \axi_araddr_reg[2]_rep__0 ;
- input \axi_araddr_reg[3]_rep ;
- input \axi_araddr_reg[2]_rep ;
- input [11:0]\data_rw_o_reg[87][11] ;
- input [0:0]\data_rw_o_reg[87][11]_0 ;
- input [11:0]\data_rw_o_reg[86][11] ;
- input [0:0]\data_rw_o_reg[86][11]_0 ;
- input [11:0]\data_rw_o_reg[85][11] ;
- input [0:0]\data_rw_o_reg[85][11]_0 ;
- input [11:0]\data_rw_o_reg[84][11] ;
- input [0:0]\data_rw_o_reg[84][11]_0 ;
- input [11:0]\data_rw_o_reg[88][11] ;
- input [0:0]\data_rw_o_reg[88][11]_0 ;
- input [11:0]\data_rw_o_reg[89][11] ;
- input [0:0]\data_rw_o_reg[89][11]_0 ;
- input [11:0]\data_rw_o_reg[90][11] ;
- input [0:0]\data_rw_o_reg[90][11]_0 ;
- input [11:0]\data_rw_o_reg[91][11] ;
- input [0:0]\data_rw_o_reg[91][11]_0 ;
- input [11:0]\data_rw_o_reg[92][11] ;
- input [11:0]\data_rw_o_reg[93][11] ;
- input [11:0]\data_rw_o_reg[94][11] ;
- input [11:0]\data_rw_o_reg[95][11] ;
- input [11:0]\data_rw_o_reg[96][11] ;
- input [11:0]\data_rw_o_reg[97][11] ;
- input [11:0]\data_rw_o_reg[98][11] ;
- input [11:0]\data_rw_o_reg[99][11] ;
- input [11:0]\data_rw_o_reg[100][11] ;
- input [11:0]\data_rw_o_reg[101][11] ;
- input [11:0]\data_rw_o_reg[102][11] ;
- input [11:0]\data_rw_o_reg[103][11] ;
- input \data_rw_o_reg[78][7] ;
- input \data_rw_o_reg[78][6] ;
- input \data_rw_o_reg[78][5] ;
- input \data_rw_o_reg[78][4] ;
-
- wire [3:0]D;
- wire [1:0]FMC2_LA_N_b;
- wire [7:0]\FMC2_LA_N_b[27] ;
- wire [21:0]\FMC2_LA_N_b[32] ;
- wire [1:0]FMC2_LA_P_b;
- wire [7:0]\FMC2_LA_P_b[27] ;
- wire [21:0]\FMC2_LA_P_b[32] ;
- wire [11:0]Q;
- wire \axi_araddr_reg[2]_rep ;
- wire \axi_araddr_reg[2]_rep__0 ;
- wire \axi_araddr_reg[2]_rep__1 ;
- wire \axi_araddr_reg[2]_rep__2 ;
- wire \axi_araddr_reg[2]_rep__3 ;
- wire \axi_araddr_reg[3]_rep ;
- wire \axi_araddr_reg[3]_rep__0 ;
- wire \axi_araddr_reg[3]_rep__1 ;
- wire \axi_araddr_reg[3]_rep__2 ;
- wire \axi_araddr_reg[3]_rep__3 ;
- wire \axi_araddr_reg[4]_rep ;
- wire \axi_araddr_reg[4]_rep__0 ;
- wire \axi_araddr_reg[4]_rep__1 ;
- wire [3:0]\axi_araddr_reg[5] ;
- wire \axi_araddr_reg[5]_rep ;
- wire \axi_rdata[0]_i_25_n_0 ;
- wire \axi_rdata[0]_i_26_n_0 ;
- wire \axi_rdata[0]_i_27_n_0 ;
- wire \axi_rdata[0]_i_28_n_0 ;
- wire \axi_rdata[10]_i_25_n_0 ;
- wire \axi_rdata[10]_i_26_n_0 ;
- wire \axi_rdata[10]_i_27_n_0 ;
- wire \axi_rdata[10]_i_28_n_0 ;
- wire \axi_rdata[11]_i_25_n_0 ;
- wire \axi_rdata[11]_i_26_n_0 ;
- wire \axi_rdata[11]_i_27_n_0 ;
- wire \axi_rdata[11]_i_28_n_0 ;
- wire \axi_rdata[12]_i_25_n_0 ;
- wire \axi_rdata[12]_i_26_n_0 ;
- wire \axi_rdata[12]_i_27_n_0 ;
- wire \axi_rdata[12]_i_28_n_0 ;
- wire \axi_rdata[13]_i_25_n_0 ;
- wire \axi_rdata[13]_i_26_n_0 ;
- wire \axi_rdata[13]_i_27_n_0 ;
- wire \axi_rdata[13]_i_28_n_0 ;
- wire \axi_rdata[14]_i_25_n_0 ;
- wire \axi_rdata[14]_i_26_n_0 ;
- wire \axi_rdata[14]_i_27_n_0 ;
- wire \axi_rdata[14]_i_28_n_0 ;
- wire \axi_rdata[15]_i_25_n_0 ;
- wire \axi_rdata[15]_i_26_n_0 ;
- wire \axi_rdata[15]_i_27_n_0 ;
- wire \axi_rdata[15]_i_28_n_0 ;
- wire \axi_rdata[16]_i_25_n_0 ;
- wire \axi_rdata[16]_i_26_n_0 ;
- wire \axi_rdata[16]_i_27_n_0 ;
- wire \axi_rdata[16]_i_28_n_0 ;
- wire \axi_rdata[17]_i_25_n_0 ;
- wire \axi_rdata[17]_i_26_n_0 ;
- wire \axi_rdata[17]_i_27_n_0 ;
- wire \axi_rdata[17]_i_28_n_0 ;
- wire \axi_rdata[18]_i_25_n_0 ;
- wire \axi_rdata[18]_i_26_n_0 ;
- wire \axi_rdata[18]_i_27_n_0 ;
- wire \axi_rdata[18]_i_28_n_0 ;
- wire \axi_rdata[19]_i_25_n_0 ;
- wire \axi_rdata[19]_i_26_n_0 ;
- wire \axi_rdata[19]_i_27_n_0 ;
- wire \axi_rdata[19]_i_28_n_0 ;
- wire \axi_rdata[1]_i_25_n_0 ;
- wire \axi_rdata[1]_i_26_n_0 ;
- wire \axi_rdata[1]_i_27_n_0 ;
- wire \axi_rdata[1]_i_28_n_0 ;
- wire \axi_rdata[20]_i_10_n_0 ;
- wire \axi_rdata[20]_i_11_n_0 ;
- wire \axi_rdata[20]_i_12_n_0 ;
- wire \axi_rdata[20]_i_9_n_0 ;
- wire \axi_rdata[21]_i_10_n_0 ;
- wire \axi_rdata[21]_i_11_n_0 ;
- wire \axi_rdata[21]_i_12_n_0 ;
- wire \axi_rdata[21]_i_9_n_0 ;
- wire \axi_rdata[22]_i_10_n_0 ;
- wire \axi_rdata[22]_i_11_n_0 ;
- wire \axi_rdata[22]_i_12_n_0 ;
- wire \axi_rdata[22]_i_9_n_0 ;
- wire \axi_rdata[23]_i_10_n_0 ;
- wire \axi_rdata[23]_i_11_n_0 ;
- wire \axi_rdata[23]_i_12_n_0 ;
- wire \axi_rdata[23]_i_13_n_0 ;
- wire \axi_rdata[2]_i_25_n_0 ;
- wire \axi_rdata[2]_i_26_n_0 ;
- wire \axi_rdata[2]_i_27_n_0 ;
- wire \axi_rdata[2]_i_28_n_0 ;
- wire \axi_rdata[3]_i_25_n_0 ;
- wire \axi_rdata[3]_i_26_n_0 ;
- wire \axi_rdata[3]_i_27_n_0 ;
- wire \axi_rdata[3]_i_28_n_0 ;
- wire \axi_rdata[4]_i_25_n_0 ;
- wire \axi_rdata[4]_i_26_n_0 ;
- wire \axi_rdata[4]_i_27_n_0 ;
- wire \axi_rdata[4]_i_28_n_0 ;
- wire \axi_rdata[5]_i_25_n_0 ;
- wire \axi_rdata[5]_i_26_n_0 ;
- wire \axi_rdata[5]_i_27_n_0 ;
- wire \axi_rdata[5]_i_28_n_0 ;
- wire \axi_rdata[6]_i_25_n_0 ;
- wire \axi_rdata[6]_i_26_n_0 ;
- wire \axi_rdata[6]_i_27_n_0 ;
- wire \axi_rdata[6]_i_28_n_0 ;
- wire \axi_rdata[7]_i_25_n_0 ;
- wire \axi_rdata[7]_i_26_n_0 ;
- wire \axi_rdata[7]_i_27_n_0 ;
- wire \axi_rdata[7]_i_28_n_0 ;
- wire \axi_rdata[8]_i_25_n_0 ;
- wire \axi_rdata[8]_i_26_n_0 ;
- wire \axi_rdata[8]_i_27_n_0 ;
- wire \axi_rdata[8]_i_28_n_0 ;
- wire \axi_rdata[9]_i_25_n_0 ;
- wire \axi_rdata[9]_i_26_n_0 ;
- wire \axi_rdata[9]_i_27_n_0 ;
- wire \axi_rdata[9]_i_28_n_0 ;
- wire \axi_rdata_reg[0] ;
- wire \axi_rdata_reg[0]_0 ;
- wire \axi_rdata_reg[0]_1 ;
- wire \axi_rdata_reg[0]_i_10_n_0 ;
- wire \axi_rdata_reg[0]_i_9_n_0 ;
- wire \axi_rdata_reg[10] ;
- wire \axi_rdata_reg[10]_0 ;
- wire \axi_rdata_reg[10]_i_10_n_0 ;
- wire \axi_rdata_reg[10]_i_9_n_0 ;
- wire \axi_rdata_reg[11] ;
- wire \axi_rdata_reg[11]_0 ;
- wire \axi_rdata_reg[11]_i_10_n_0 ;
- wire \axi_rdata_reg[11]_i_9_n_0 ;
- wire \axi_rdata_reg[12] ;
- wire \axi_rdata_reg[12]_0 ;
- wire \axi_rdata_reg[12]_i_10_n_0 ;
- wire \axi_rdata_reg[12]_i_9_n_0 ;
- wire \axi_rdata_reg[13] ;
- wire \axi_rdata_reg[13]_0 ;
- wire \axi_rdata_reg[13]_i_10_n_0 ;
- wire \axi_rdata_reg[13]_i_9_n_0 ;
- wire \axi_rdata_reg[14] ;
- wire \axi_rdata_reg[14]_0 ;
- wire \axi_rdata_reg[14]_i_10_n_0 ;
- wire \axi_rdata_reg[14]_i_9_n_0 ;
- wire \axi_rdata_reg[15] ;
- wire \axi_rdata_reg[15]_0 ;
- wire \axi_rdata_reg[15]_i_10_n_0 ;
- wire \axi_rdata_reg[15]_i_9_n_0 ;
- wire \axi_rdata_reg[16] ;
- wire \axi_rdata_reg[16]_0 ;
- wire \axi_rdata_reg[16]_i_10_n_0 ;
- wire \axi_rdata_reg[16]_i_9_n_0 ;
- wire \axi_rdata_reg[17] ;
- wire \axi_rdata_reg[17]_0 ;
- wire \axi_rdata_reg[17]_i_10_n_0 ;
- wire \axi_rdata_reg[17]_i_9_n_0 ;
- wire \axi_rdata_reg[18] ;
- wire \axi_rdata_reg[18]_0 ;
- wire \axi_rdata_reg[18]_i_10_n_0 ;
- wire \axi_rdata_reg[18]_i_9_n_0 ;
- wire \axi_rdata_reg[19] ;
- wire \axi_rdata_reg[19]_0 ;
- wire \axi_rdata_reg[19]_i_10_n_0 ;
- wire \axi_rdata_reg[19]_i_9_n_0 ;
- wire \axi_rdata_reg[1] ;
- wire \axi_rdata_reg[1]_0 ;
- wire \axi_rdata_reg[1]_1 ;
- wire \axi_rdata_reg[1]_i_10_n_0 ;
- wire \axi_rdata_reg[1]_i_9_n_0 ;
- wire \axi_rdata_reg[20] ;
- wire \axi_rdata_reg[20]_0 ;
- wire \axi_rdata_reg[20]_1 ;
- wire \axi_rdata_reg[21] ;
- wire \axi_rdata_reg[21]_0 ;
- wire \axi_rdata_reg[21]_1 ;
- wire \axi_rdata_reg[22] ;
- wire \axi_rdata_reg[22]_0 ;
- wire \axi_rdata_reg[22]_1 ;
- wire \axi_rdata_reg[23] ;
- wire \axi_rdata_reg[23]_0 ;
- wire \axi_rdata_reg[23]_1 ;
- wire \axi_rdata_reg[2] ;
- wire \axi_rdata_reg[2]_0 ;
- wire \axi_rdata_reg[2]_1 ;
- wire \axi_rdata_reg[2]_i_10_n_0 ;
- wire \axi_rdata_reg[2]_i_9_n_0 ;
- wire [31:0]\axi_rdata_reg[31] ;
- wire \axi_rdata_reg[3] ;
- wire \axi_rdata_reg[3]_0 ;
- wire \axi_rdata_reg[3]_1 ;
- wire [3:0]\axi_rdata_reg[3]_2 ;
- wire \axi_rdata_reg[3]_i_10_n_0 ;
- wire \axi_rdata_reg[3]_i_9_n_0 ;
- wire \axi_rdata_reg[4] ;
- wire \axi_rdata_reg[4]_0 ;
- wire \axi_rdata_reg[4]_1 ;
- wire \axi_rdata_reg[4]_i_10_n_0 ;
- wire \axi_rdata_reg[4]_i_9_n_0 ;
- wire \axi_rdata_reg[5] ;
- wire \axi_rdata_reg[5]_0 ;
- wire \axi_rdata_reg[5]_1 ;
- wire \axi_rdata_reg[5]_i_10_n_0 ;
- wire \axi_rdata_reg[5]_i_9_n_0 ;
- wire \axi_rdata_reg[6] ;
- wire \axi_rdata_reg[6]_0 ;
- wire \axi_rdata_reg[6]_1 ;
- wire \axi_rdata_reg[6]_i_10_n_0 ;
- wire \axi_rdata_reg[6]_i_9_n_0 ;
- wire \axi_rdata_reg[7] ;
- wire \axi_rdata_reg[7]_0 ;
- wire \axi_rdata_reg[7]_1 ;
- wire \axi_rdata_reg[7]_i_10_n_0 ;
- wire \axi_rdata_reg[7]_i_9_n_0 ;
- wire \axi_rdata_reg[8] ;
- wire \axi_rdata_reg[8]_0 ;
- wire \axi_rdata_reg[8]_i_10_n_0 ;
- wire \axi_rdata_reg[8]_i_9_n_0 ;
- wire \axi_rdata_reg[9] ;
- wire \axi_rdata_reg[9]_0 ;
- wire \axi_rdata_reg[9]_i_10_n_0 ;
- wire \axi_rdata_reg[9]_i_9_n_0 ;
- wire \cmp_lengthCounter/RSTP ;
- wire \cmp_lengthCounter/RSTP_1 ;
- wire \cmp_lengthCounter/RSTP_11 ;
- wire \cmp_lengthCounter/RSTP_13 ;
- wire \cmp_lengthCounter/RSTP_15 ;
- wire \cmp_lengthCounter/RSTP_17 ;
- wire \cmp_lengthCounter/RSTP_19 ;
- wire \cmp_lengthCounter/RSTP_21 ;
- wire \cmp_lengthCounter/RSTP_23 ;
- wire \cmp_lengthCounter/RSTP_25 ;
- wire \cmp_lengthCounter/RSTP_27 ;
- wire \cmp_lengthCounter/RSTP_29 ;
- wire \cmp_lengthCounter/RSTP_3 ;
- wire \cmp_lengthCounter/RSTP_31 ;
- wire \cmp_lengthCounter/RSTP_33 ;
- wire \cmp_lengthCounter/RSTP_35 ;
- wire \cmp_lengthCounter/RSTP_37 ;
- wire \cmp_lengthCounter/RSTP_5 ;
- wire \cmp_lengthCounter/RSTP_7 ;
- wire \cmp_lengthCounter/RSTP_9 ;
- wire [4:0]\cmp_pulseSync/s_debounce ;
- wire [4:0]\cmp_pulseSync/s_debounce_0 ;
- wire [4:0]\cmp_pulseSync/s_debounce_10 ;
- wire [4:0]\cmp_pulseSync/s_debounce_12 ;
- wire [4:0]\cmp_pulseSync/s_debounce_14 ;
- wire [4:0]\cmp_pulseSync/s_debounce_16 ;
- wire [4:0]\cmp_pulseSync/s_debounce_18 ;
- wire [4:0]\cmp_pulseSync/s_debounce_2 ;
- wire [4:0]\cmp_pulseSync/s_debounce_20 ;
- wire [4:0]\cmp_pulseSync/s_debounce_22 ;
- wire [4:0]\cmp_pulseSync/s_debounce_24 ;
- wire [4:0]\cmp_pulseSync/s_debounce_26 ;
- wire [4:0]\cmp_pulseSync/s_debounce_28 ;
- wire [4:0]\cmp_pulseSync/s_debounce_30 ;
- wire [4:0]\cmp_pulseSync/s_debounce_32 ;
- wire [4:0]\cmp_pulseSync/s_debounce_34 ;
- wire [4:0]\cmp_pulseSync/s_debounce_36 ;
- wire [4:0]\cmp_pulseSync/s_debounce_38 ;
- wire [4:0]\cmp_pulseSync/s_debounce_39 ;
- wire [4:0]\cmp_pulseSync/s_debounce_4 ;
- wire [4:0]\cmp_pulseSync/s_debounce_40 ;
- wire [4:0]\cmp_pulseSync/s_debounce_41 ;
- wire [4:0]\cmp_pulseSync/s_debounce_42 ;
- wire [4:0]\cmp_pulseSync/s_debounce_43 ;
- wire [4:0]\cmp_pulseSync/s_debounce_44 ;
- wire [4:0]\cmp_pulseSync/s_debounce_45 ;
- wire [4:0]\cmp_pulseSync/s_debounce_6 ;
- wire [4:0]\cmp_pulseSync/s_debounce_8 ;
- wire [11:0]\data_rw_o_reg[100][11] ;
- wire [11:0]\data_rw_o_reg[101][11] ;
- wire [11:0]\data_rw_o_reg[102][11] ;
- wire [11:0]\data_rw_o_reg[103][11] ;
- wire \data_rw_o_reg[78][4] ;
- wire \data_rw_o_reg[78][5] ;
- wire \data_rw_o_reg[78][6] ;
- wire \data_rw_o_reg[78][7] ;
- wire [2:0]\data_rw_o_reg[79][7] ;
- wire [11:0]\data_rw_o_reg[84][11] ;
- wire [0:0]\data_rw_o_reg[84][11]_0 ;
- wire [11:0]\data_rw_o_reg[85][11] ;
- wire [0:0]\data_rw_o_reg[85][11]_0 ;
- wire [11:0]\data_rw_o_reg[86][11] ;
- wire [0:0]\data_rw_o_reg[86][11]_0 ;
- wire [11:0]\data_rw_o_reg[87][11] ;
- wire [0:0]\data_rw_o_reg[87][11]_0 ;
- wire [11:0]\data_rw_o_reg[88][11] ;
- wire [0:0]\data_rw_o_reg[88][11]_0 ;
- wire [11:0]\data_rw_o_reg[89][11] ;
- wire [0:0]\data_rw_o_reg[89][11]_0 ;
- wire [11:0]\data_rw_o_reg[90][11] ;
- wire [0:0]\data_rw_o_reg[90][11]_0 ;
- wire [11:0]\data_rw_o_reg[91][11] ;
- wire [0:0]\data_rw_o_reg[91][11]_0 ;
- wire [11:0]\data_rw_o_reg[92][11] ;
- wire [11:0]\data_rw_o_reg[93][11] ;
- wire [11:0]\data_rw_o_reg[94][11] ;
- wire [11:0]\data_rw_o_reg[95][11] ;
- wire [11:0]\data_rw_o_reg[96][11] ;
- wire [11:0]\data_rw_o_reg[97][11] ;
- wire [11:0]\data_rw_o_reg[98][11] ;
- wire [11:0]\data_rw_o_reg[99][11] ;
- wire fmc2_intr;
- wire fmc2_intr_led;
- wire \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2 ;
- wire \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_3 ;
- wire \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_4 ;
- wire \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_2 ;
- wire \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_3 ;
- wire \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_2 ;
- wire \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_3 ;
- wire \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_2 ;
- wire \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_3 ;
- wire \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_2 ;
- wire \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_3 ;
- wire \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_2 ;
- wire \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_3 ;
- wire \fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure_n_2 ;
- wire \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_3 ;
- wire \fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_3 ;
- wire \fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_1 ;
- wire \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_3 ;
- wire \gen_spi.cmp_dac7716_spi_n_1 ;
- wire \gen_spi.cmp_dac7716_spi_n_2 ;
- wire intr_o0;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_buff2_i_1__0_n_0;
- wire s_buff2_i_1__10_n_0;
- wire s_buff2_i_1__11_n_0;
- wire s_buff2_i_1__12_n_0;
- wire s_buff2_i_1__13_n_0;
- wire s_buff2_i_1__14_n_0;
- wire s_buff2_i_1__15_n_0;
- wire s_buff2_i_1__16_n_0;
- wire s_buff2_i_1__17_n_0;
- wire s_buff2_i_1__18_n_0;
- wire s_buff2_i_1__19_n_0;
- wire s_buff2_i_1__1_n_0;
- wire s_buff2_i_1__20_n_0;
- wire s_buff2_i_1__21_n_0;
- wire s_buff2_i_1__22_n_0;
- wire s_buff2_i_1__23_n_0;
- wire s_buff2_i_1__24_n_0;
- wire s_buff2_i_1__25_n_0;
- wire s_buff2_i_1__26_n_0;
- wire s_buff2_i_1__2_n_0;
- wire s_buff2_i_1__3_n_0;
- wire s_buff2_i_1__4_n_0;
- wire s_buff2_i_1__5_n_0;
- wire s_buff2_i_1__6_n_0;
- wire s_buff2_i_1__7_n_0;
- wire s_buff2_i_1__8_n_0;
- wire s_buff2_i_1__9_n_0;
- wire s_buff2_i_1_n_0;
- wire [23:0]\s_cmp_lengths[0]_0 ;
- wire [23:0]\s_cmp_lengths[10]_10 ;
- wire [23:0]\s_cmp_lengths[11]_11 ;
- wire [23:0]\s_cmp_lengths[12]_12 ;
- wire [23:0]\s_cmp_lengths[13]_13 ;
- wire [23:0]\s_cmp_lengths[14]_14 ;
- wire [23:0]\s_cmp_lengths[15]_15 ;
- wire [23:0]\s_cmp_lengths[16]_16 ;
- wire [23:0]\s_cmp_lengths[17]_17 ;
- wire [23:0]\s_cmp_lengths[18]_18 ;
- wire [23:0]\s_cmp_lengths[19]_19 ;
- wire [23:0]\s_cmp_lengths[1]_1 ;
- wire [23:0]\s_cmp_lengths[2]_2 ;
- wire [23:0]\s_cmp_lengths[3]_3 ;
- wire [23:0]\s_cmp_lengths[4]_4 ;
- wire [23:0]\s_cmp_lengths[5]_5 ;
- wire [23:0]\s_cmp_lengths[6]_6 ;
- wire [23:0]\s_cmp_lengths[7]_7 ;
- wire [23:0]\s_cmp_lengths[8]_8 ;
- wire [23:0]\s_cmp_lengths[9]_9 ;
- wire s_comparators_i_0;
- wire s_comparators_i_1;
- wire s_comparators_i_10;
- wire s_comparators_i_11;
- wire s_comparators_i_12;
- wire s_comparators_i_13;
- wire s_comparators_i_14;
- wire s_comparators_i_15;
- wire s_comparators_i_16;
- wire s_comparators_i_17;
- wire s_comparators_i_18;
- wire s_comparators_i_19;
- wire s_comparators_i_2;
- wire s_comparators_i_3;
- wire s_comparators_i_4;
- wire s_comparators_i_5;
- wire s_comparators_i_6;
- wire s_comparators_i_7;
- wire s_comparators_i_8;
- wire s_comparators_i_9;
- wire [11:0]s_count_reg;
- wire [19:0]\s_datao_fmc2[0] ;
- wire [23:0]\s_datao_fmc2[48] ;
- wire [23:0]\s_datao_fmc2[49] ;
- wire [7:0]\s_datao_fmc2[4] ;
- wire [23:0]\s_datao_fmc2[50] ;
- wire [23:0]\s_datao_fmc2[51] ;
- wire [23:0]\s_datao_fmc2[52] ;
- wire [23:0]\s_datao_fmc2[53] ;
- wire [23:0]\s_datao_fmc2[54] ;
- wire [23:0]\s_datao_fmc2[55] ;
- wire [23:0]\s_datao_fmc2[56] ;
- wire [23:0]\s_datao_fmc2[57] ;
- wire [23:0]\s_datao_fmc2[58] ;
- wire [23:0]\s_datao_fmc2[59] ;
- wire [7:0]\s_datao_fmc2[5] ;
- wire [23:0]\s_datao_fmc2[60] ;
- wire [23:0]\s_datao_fmc2[61] ;
- wire [23:0]\s_datao_fmc2[62] ;
- wire [23:0]\s_datao_fmc2[63] ;
- wire [23:0]\s_datao_fmc2[64] ;
- wire [23:0]\s_datao_fmc2[65] ;
- wire [23:0]\s_datao_fmc2[66] ;
- wire [23:0]\s_datao_fmc2[67] ;
- wire [7:0]\s_datao_fmc2[6] ;
- wire [7:4]s_diffouts_o;
- wire s_spi_cs_n;
- wire s_spi_mosi;
- wire s_spi_sclk;
- wire s_start;
- wire s_start_i_1_n_0;
- wire [11:0]\s_tx_data_reg[111] ;
- wire [11:0]\s_tx_data_reg[15] ;
- wire [11:0]\s_tx_data_reg[15]_0 ;
- wire [11:0]\s_tx_data_reg[39] ;
- wire [11:0]\s_tx_data_reg[39]_0 ;
- wire [11:0]\s_tx_data_reg[39]_1 ;
- wire [11:0]\s_tx_data_reg[39]_2 ;
- wire spi_sdo_i;
- wire [19:0]v_cmp;
- wire [19:0]v_cmpled;
- wire [7:4]v_dout;
- wire [3:0]v_fbd;
- wire [7:0]v_outleds;
- wire \NLW_gen_spi.cmp_spi_cs_n_iobuf_O_UNCONNECTED ;
- wire \NLW_gen_spi.cmp_spi_mosi_iobuf_O_UNCONNECTED ;
- wire \NLW_gen_spi.cmp_spi_sclk_iobuf_O_UNCONNECTED ;
-
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_22
- (.I0(\s_datao_fmc2[51] [0]),
- .I1(\s_datao_fmc2[50] [0]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[49] [0]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[48] [0]),
- .O(\axi_rdata_reg[0]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_25
- (.I0(\s_datao_fmc2[55] [0]),
- .I1(\s_datao_fmc2[54] [0]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[53] [0]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[52] [0]),
- .O(\axi_rdata[0]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_26
- (.I0(\s_datao_fmc2[59] [0]),
- .I1(\s_datao_fmc2[58] [0]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[57] [0]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[56] [0]),
- .O(\axi_rdata[0]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_27
- (.I0(\s_datao_fmc2[63] [0]),
- .I1(\s_datao_fmc2[62] [0]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[61] [0]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[60] [0]),
- .O(\axi_rdata[0]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[0]_i_28
- (.I0(\s_datao_fmc2[67] [0]),
- .I1(\s_datao_fmc2[66] [0]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[65] [0]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[64] [0]),
- .O(\axi_rdata[0]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_22
- (.I0(\s_datao_fmc2[51] [10]),
- .I1(\s_datao_fmc2[50] [10]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[49] [10]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[48] [10]),
- .O(\axi_rdata_reg[10] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_25
- (.I0(\s_datao_fmc2[55] [10]),
- .I1(\s_datao_fmc2[54] [10]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[53] [10]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[52] [10]),
- .O(\axi_rdata[10]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_26
- (.I0(\s_datao_fmc2[59] [10]),
- .I1(\s_datao_fmc2[58] [10]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[57] [10]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[56] [10]),
- .O(\axi_rdata[10]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_27
- (.I0(\s_datao_fmc2[63] [10]),
- .I1(\s_datao_fmc2[62] [10]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[61] [10]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[60] [10]),
- .O(\axi_rdata[10]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[10]_i_28
- (.I0(\s_datao_fmc2[67] [10]),
- .I1(\s_datao_fmc2[66] [10]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[65] [10]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[64] [10]),
- .O(\axi_rdata[10]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_22
- (.I0(\s_datao_fmc2[51] [11]),
- .I1(\s_datao_fmc2[50] [11]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[49] [11]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[48] [11]),
- .O(\axi_rdata_reg[11] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_25
- (.I0(\s_datao_fmc2[55] [11]),
- .I1(\s_datao_fmc2[54] [11]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[53] [11]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[52] [11]),
- .O(\axi_rdata[11]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_26
- (.I0(\s_datao_fmc2[59] [11]),
- .I1(\s_datao_fmc2[58] [11]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[57] [11]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[56] [11]),
- .O(\axi_rdata[11]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_27
- (.I0(\s_datao_fmc2[63] [11]),
- .I1(\s_datao_fmc2[62] [11]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[61] [11]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[60] [11]),
- .O(\axi_rdata[11]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[11]_i_28
- (.I0(\s_datao_fmc2[67] [11]),
- .I1(\s_datao_fmc2[66] [11]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[65] [11]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[64] [11]),
- .O(\axi_rdata[11]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_22
- (.I0(\s_datao_fmc2[51] [12]),
- .I1(\s_datao_fmc2[50] [12]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[49] [12]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[48] [12]),
- .O(\axi_rdata_reg[12] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_25
- (.I0(\s_datao_fmc2[55] [12]),
- .I1(\s_datao_fmc2[54] [12]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[53] [12]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[52] [12]),
- .O(\axi_rdata[12]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_26
- (.I0(\s_datao_fmc2[59] [12]),
- .I1(\s_datao_fmc2[58] [12]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[57] [12]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[56] [12]),
- .O(\axi_rdata[12]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_27
- (.I0(\s_datao_fmc2[63] [12]),
- .I1(\s_datao_fmc2[62] [12]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[61] [12]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[60] [12]),
- .O(\axi_rdata[12]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[12]_i_28
- (.I0(\s_datao_fmc2[67] [12]),
- .I1(\s_datao_fmc2[66] [12]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[65] [12]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[64] [12]),
- .O(\axi_rdata[12]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_22
- (.I0(\s_datao_fmc2[51] [13]),
- .I1(\s_datao_fmc2[50] [13]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[49] [13]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[48] [13]),
- .O(\axi_rdata_reg[13] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_25
- (.I0(\s_datao_fmc2[55] [13]),
- .I1(\s_datao_fmc2[54] [13]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[53] [13]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[52] [13]),
- .O(\axi_rdata[13]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_26
- (.I0(\s_datao_fmc2[59] [13]),
- .I1(\s_datao_fmc2[58] [13]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[57] [13]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[56] [13]),
- .O(\axi_rdata[13]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_27
- (.I0(\s_datao_fmc2[63] [13]),
- .I1(\s_datao_fmc2[62] [13]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[61] [13]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[60] [13]),
- .O(\axi_rdata[13]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[13]_i_28
- (.I0(\s_datao_fmc2[67] [13]),
- .I1(\s_datao_fmc2[66] [13]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[65] [13]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[64] [13]),
- .O(\axi_rdata[13]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_22
- (.I0(\s_datao_fmc2[51] [14]),
- .I1(\s_datao_fmc2[50] [14]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[49] [14]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[48] [14]),
- .O(\axi_rdata_reg[14] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_25
- (.I0(\s_datao_fmc2[55] [14]),
- .I1(\s_datao_fmc2[54] [14]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[53] [14]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[52] [14]),
- .O(\axi_rdata[14]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_26
- (.I0(\s_datao_fmc2[59] [14]),
- .I1(\s_datao_fmc2[58] [14]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[57] [14]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[56] [14]),
- .O(\axi_rdata[14]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_27
- (.I0(\s_datao_fmc2[63] [14]),
- .I1(\s_datao_fmc2[62] [14]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[61] [14]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[60] [14]),
- .O(\axi_rdata[14]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[14]_i_28
- (.I0(\s_datao_fmc2[67] [14]),
- .I1(\s_datao_fmc2[66] [14]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[65] [14]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[64] [14]),
- .O(\axi_rdata[14]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_22
- (.I0(\s_datao_fmc2[51] [15]),
- .I1(\s_datao_fmc2[50] [15]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[49] [15]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[48] [15]),
- .O(\axi_rdata_reg[15] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_25
- (.I0(\s_datao_fmc2[55] [15]),
- .I1(\s_datao_fmc2[54] [15]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[53] [15]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[52] [15]),
- .O(\axi_rdata[15]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_26
- (.I0(\s_datao_fmc2[59] [15]),
- .I1(\s_datao_fmc2[58] [15]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[57] [15]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[56] [15]),
- .O(\axi_rdata[15]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_27
- (.I0(\s_datao_fmc2[63] [15]),
- .I1(\s_datao_fmc2[62] [15]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[61] [15]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[60] [15]),
- .O(\axi_rdata[15]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[15]_i_28
- (.I0(\s_datao_fmc2[67] [15]),
- .I1(\s_datao_fmc2[66] [15]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[65] [15]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[64] [15]),
- .O(\axi_rdata[15]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_22
- (.I0(\s_datao_fmc2[51] [16]),
- .I1(\s_datao_fmc2[50] [16]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[49] [16]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[48] [16]),
- .O(\axi_rdata_reg[16] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_25
- (.I0(\s_datao_fmc2[55] [16]),
- .I1(\s_datao_fmc2[54] [16]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[53] [16]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[52] [16]),
- .O(\axi_rdata[16]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_26
- (.I0(\s_datao_fmc2[59] [16]),
- .I1(\s_datao_fmc2[58] [16]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[57] [16]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[56] [16]),
- .O(\axi_rdata[16]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_27
- (.I0(\s_datao_fmc2[63] [16]),
- .I1(\s_datao_fmc2[62] [16]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[61] [16]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[60] [16]),
- .O(\axi_rdata[16]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[16]_i_28
- (.I0(\s_datao_fmc2[67] [16]),
- .I1(\s_datao_fmc2[66] [16]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[65] [16]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[64] [16]),
- .O(\axi_rdata[16]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_22
- (.I0(\s_datao_fmc2[51] [17]),
- .I1(\s_datao_fmc2[50] [17]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[49] [17]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[48] [17]),
- .O(\axi_rdata_reg[17] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_25
- (.I0(\s_datao_fmc2[55] [17]),
- .I1(\s_datao_fmc2[54] [17]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[53] [17]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[52] [17]),
- .O(\axi_rdata[17]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_26
- (.I0(\s_datao_fmc2[59] [17]),
- .I1(\s_datao_fmc2[58] [17]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[57] [17]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[56] [17]),
- .O(\axi_rdata[17]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_27
- (.I0(\s_datao_fmc2[63] [17]),
- .I1(\s_datao_fmc2[62] [17]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[61] [17]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[60] [17]),
- .O(\axi_rdata[17]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[17]_i_28
- (.I0(\s_datao_fmc2[67] [17]),
- .I1(\s_datao_fmc2[66] [17]),
- .I2(\axi_araddr_reg[3]_rep__0 ),
- .I3(\s_datao_fmc2[65] [17]),
- .I4(\axi_araddr_reg[2]_rep__0 ),
- .I5(\s_datao_fmc2[64] [17]),
- .O(\axi_rdata[17]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_22
- (.I0(\s_datao_fmc2[51] [18]),
- .I1(\s_datao_fmc2[50] [18]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[49] [18]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[48] [18]),
- .O(\axi_rdata_reg[18] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_25
- (.I0(\s_datao_fmc2[55] [18]),
- .I1(\s_datao_fmc2[54] [18]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[53] [18]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[52] [18]),
- .O(\axi_rdata[18]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_26
- (.I0(\s_datao_fmc2[59] [18]),
- .I1(\s_datao_fmc2[58] [18]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[57] [18]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[56] [18]),
- .O(\axi_rdata[18]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_27
- (.I0(\s_datao_fmc2[63] [18]),
- .I1(\s_datao_fmc2[62] [18]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[61] [18]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[60] [18]),
- .O(\axi_rdata[18]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[18]_i_28
- (.I0(\s_datao_fmc2[67] [18]),
- .I1(\s_datao_fmc2[66] [18]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[65] [18]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[64] [18]),
- .O(\axi_rdata[18]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_22
- (.I0(\s_datao_fmc2[51] [19]),
- .I1(\s_datao_fmc2[50] [19]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[49] [19]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[48] [19]),
- .O(\axi_rdata_reg[19] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_25
- (.I0(\s_datao_fmc2[55] [19]),
- .I1(\s_datao_fmc2[54] [19]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[53] [19]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[52] [19]),
- .O(\axi_rdata[19]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_26
- (.I0(\s_datao_fmc2[59] [19]),
- .I1(\s_datao_fmc2[58] [19]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[57] [19]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[56] [19]),
- .O(\axi_rdata[19]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_27
- (.I0(\s_datao_fmc2[63] [19]),
- .I1(\s_datao_fmc2[62] [19]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[61] [19]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[60] [19]),
- .O(\axi_rdata[19]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[19]_i_28
- (.I0(\s_datao_fmc2[67] [19]),
- .I1(\s_datao_fmc2[66] [19]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[65] [19]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[64] [19]),
- .O(\axi_rdata[19]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_22
- (.I0(\s_datao_fmc2[51] [1]),
- .I1(\s_datao_fmc2[50] [1]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[49] [1]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[48] [1]),
- .O(\axi_rdata_reg[1]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_25
- (.I0(\s_datao_fmc2[55] [1]),
- .I1(\s_datao_fmc2[54] [1]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[53] [1]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[52] [1]),
- .O(\axi_rdata[1]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_26
- (.I0(\s_datao_fmc2[59] [1]),
- .I1(\s_datao_fmc2[58] [1]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[57] [1]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[56] [1]),
- .O(\axi_rdata[1]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_27
- (.I0(\s_datao_fmc2[63] [1]),
- .I1(\s_datao_fmc2[62] [1]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[61] [1]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[60] [1]),
- .O(\axi_rdata[1]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[1]_i_28
- (.I0(\s_datao_fmc2[67] [1]),
- .I1(\s_datao_fmc2[66] [1]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[65] [1]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[64] [1]),
- .O(\axi_rdata[1]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_10
- (.I0(\s_datao_fmc2[59] [20]),
- .I1(\s_datao_fmc2[58] [20]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[57] [20]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[56] [20]),
- .O(\axi_rdata[20]_i_10_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_11
- (.I0(\s_datao_fmc2[63] [20]),
- .I1(\s_datao_fmc2[62] [20]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[61] [20]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[60] [20]),
- .O(\axi_rdata[20]_i_11_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_12
- (.I0(\s_datao_fmc2[67] [20]),
- .I1(\s_datao_fmc2[66] [20]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[65] [20]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[64] [20]),
- .O(\axi_rdata[20]_i_12_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_13
- (.I0(\s_datao_fmc2[51] [20]),
- .I1(\s_datao_fmc2[50] [20]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[49] [20]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[48] [20]),
- .O(\axi_rdata_reg[20] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[20]_i_9
- (.I0(\s_datao_fmc2[55] [20]),
- .I1(\s_datao_fmc2[54] [20]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[53] [20]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[52] [20]),
- .O(\axi_rdata[20]_i_9_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_10
- (.I0(\s_datao_fmc2[59] [21]),
- .I1(\s_datao_fmc2[58] [21]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[57] [21]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[56] [21]),
- .O(\axi_rdata[21]_i_10_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_11
- (.I0(\s_datao_fmc2[63] [21]),
- .I1(\s_datao_fmc2[62] [21]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[61] [21]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[60] [21]),
- .O(\axi_rdata[21]_i_11_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_12
- (.I0(\s_datao_fmc2[67] [21]),
- .I1(\s_datao_fmc2[66] [21]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[65] [21]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[64] [21]),
- .O(\axi_rdata[21]_i_12_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_13
- (.I0(\s_datao_fmc2[51] [21]),
- .I1(\s_datao_fmc2[50] [21]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[49] [21]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[48] [21]),
- .O(\axi_rdata_reg[21] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[21]_i_9
- (.I0(\s_datao_fmc2[55] [21]),
- .I1(\s_datao_fmc2[54] [21]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[53] [21]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[52] [21]),
- .O(\axi_rdata[21]_i_9_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_10
- (.I0(\s_datao_fmc2[59] [22]),
- .I1(\s_datao_fmc2[58] [22]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[57] [22]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[56] [22]),
- .O(\axi_rdata[22]_i_10_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_11
- (.I0(\s_datao_fmc2[63] [22]),
- .I1(\s_datao_fmc2[62] [22]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[61] [22]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[60] [22]),
- .O(\axi_rdata[22]_i_11_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_12
- (.I0(\s_datao_fmc2[67] [22]),
- .I1(\s_datao_fmc2[66] [22]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[65] [22]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[64] [22]),
- .O(\axi_rdata[22]_i_12_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_13
- (.I0(\s_datao_fmc2[51] [22]),
- .I1(\s_datao_fmc2[50] [22]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[49] [22]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[48] [22]),
- .O(\axi_rdata_reg[22] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[22]_i_9
- (.I0(\s_datao_fmc2[55] [22]),
- .I1(\s_datao_fmc2[54] [22]),
- .I2(\axi_araddr_reg[3]_rep ),
- .I3(\s_datao_fmc2[53] [22]),
- .I4(\axi_araddr_reg[2]_rep ),
- .I5(\s_datao_fmc2[52] [22]),
- .O(\axi_rdata[22]_i_9_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_10
- (.I0(\s_datao_fmc2[55] [23]),
- .I1(\s_datao_fmc2[54] [23]),
- .I2(\axi_araddr_reg[5] [1]),
- .I3(\s_datao_fmc2[53] [23]),
- .I4(\axi_araddr_reg[5] [0]),
- .I5(\s_datao_fmc2[52] [23]),
- .O(\axi_rdata[23]_i_10_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_11
- (.I0(\s_datao_fmc2[59] [23]),
- .I1(\s_datao_fmc2[58] [23]),
- .I2(\axi_araddr_reg[5] [1]),
- .I3(\s_datao_fmc2[57] [23]),
- .I4(\axi_araddr_reg[5] [0]),
- .I5(\s_datao_fmc2[56] [23]),
- .O(\axi_rdata[23]_i_11_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_12
- (.I0(\s_datao_fmc2[63] [23]),
- .I1(\s_datao_fmc2[62] [23]),
- .I2(\axi_araddr_reg[5] [1]),
- .I3(\s_datao_fmc2[61] [23]),
- .I4(\axi_araddr_reg[5] [0]),
- .I5(\s_datao_fmc2[60] [23]),
- .O(\axi_rdata[23]_i_12_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_13
- (.I0(\s_datao_fmc2[67] [23]),
- .I1(\s_datao_fmc2[66] [23]),
- .I2(\axi_araddr_reg[5] [1]),
- .I3(\s_datao_fmc2[65] [23]),
- .I4(\axi_araddr_reg[5] [0]),
- .I5(\s_datao_fmc2[64] [23]),
- .O(\axi_rdata[23]_i_13_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[23]_i_14
- (.I0(\s_datao_fmc2[51] [23]),
- .I1(\s_datao_fmc2[50] [23]),
- .I2(\axi_araddr_reg[5] [1]),
- .I3(\s_datao_fmc2[49] [23]),
- .I4(\axi_araddr_reg[5] [0]),
- .I5(\s_datao_fmc2[48] [23]),
- .O(\axi_rdata_reg[23] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_22
- (.I0(\s_datao_fmc2[51] [2]),
- .I1(\s_datao_fmc2[50] [2]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[49] [2]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[48] [2]),
- .O(\axi_rdata_reg[2]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_25
- (.I0(\s_datao_fmc2[55] [2]),
- .I1(\s_datao_fmc2[54] [2]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[53] [2]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[52] [2]),
- .O(\axi_rdata[2]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_26
- (.I0(\s_datao_fmc2[59] [2]),
- .I1(\s_datao_fmc2[58] [2]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[57] [2]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[56] [2]),
- .O(\axi_rdata[2]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_27
- (.I0(\s_datao_fmc2[63] [2]),
- .I1(\s_datao_fmc2[62] [2]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[61] [2]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[60] [2]),
- .O(\axi_rdata[2]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[2]_i_28
- (.I0(\s_datao_fmc2[67] [2]),
- .I1(\s_datao_fmc2[66] [2]),
- .I2(\axi_araddr_reg[3]_rep__3 ),
- .I3(\s_datao_fmc2[65] [2]),
- .I4(\axi_araddr_reg[2]_rep__3 ),
- .I5(\s_datao_fmc2[64] [2]),
- .O(\axi_rdata[2]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_22
- (.I0(\s_datao_fmc2[51] [3]),
- .I1(\s_datao_fmc2[50] [3]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[49] [3]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[48] [3]),
- .O(\axi_rdata_reg[3]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_25
- (.I0(\s_datao_fmc2[55] [3]),
- .I1(\s_datao_fmc2[54] [3]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[53] [3]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[52] [3]),
- .O(\axi_rdata[3]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_26
- (.I0(\s_datao_fmc2[59] [3]),
- .I1(\s_datao_fmc2[58] [3]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[57] [3]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[56] [3]),
- .O(\axi_rdata[3]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_27
- (.I0(\s_datao_fmc2[63] [3]),
- .I1(\s_datao_fmc2[62] [3]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[61] [3]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[60] [3]),
- .O(\axi_rdata[3]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[3]_i_28
- (.I0(\s_datao_fmc2[67] [3]),
- .I1(\s_datao_fmc2[66] [3]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[65] [3]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[64] [3]),
- .O(\axi_rdata[3]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_22
- (.I0(\s_datao_fmc2[51] [4]),
- .I1(\s_datao_fmc2[50] [4]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[49] [4]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[48] [4]),
- .O(\axi_rdata_reg[4]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_25
- (.I0(\s_datao_fmc2[55] [4]),
- .I1(\s_datao_fmc2[54] [4]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[53] [4]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[52] [4]),
- .O(\axi_rdata[4]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_26
- (.I0(\s_datao_fmc2[59] [4]),
- .I1(\s_datao_fmc2[58] [4]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[57] [4]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[56] [4]),
- .O(\axi_rdata[4]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_27
- (.I0(\s_datao_fmc2[63] [4]),
- .I1(\s_datao_fmc2[62] [4]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[61] [4]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[60] [4]),
- .O(\axi_rdata[4]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[4]_i_28
- (.I0(\s_datao_fmc2[67] [4]),
- .I1(\s_datao_fmc2[66] [4]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[65] [4]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[64] [4]),
- .O(\axi_rdata[4]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_22
- (.I0(\s_datao_fmc2[51] [5]),
- .I1(\s_datao_fmc2[50] [5]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[49] [5]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[48] [5]),
- .O(\axi_rdata_reg[5]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_25
- (.I0(\s_datao_fmc2[55] [5]),
- .I1(\s_datao_fmc2[54] [5]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[53] [5]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[52] [5]),
- .O(\axi_rdata[5]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_26
- (.I0(\s_datao_fmc2[59] [5]),
- .I1(\s_datao_fmc2[58] [5]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[57] [5]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[56] [5]),
- .O(\axi_rdata[5]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_27
- (.I0(\s_datao_fmc2[63] [5]),
- .I1(\s_datao_fmc2[62] [5]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[61] [5]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[60] [5]),
- .O(\axi_rdata[5]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[5]_i_28
- (.I0(\s_datao_fmc2[67] [5]),
- .I1(\s_datao_fmc2[66] [5]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[65] [5]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[64] [5]),
- .O(\axi_rdata[5]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_22
- (.I0(\s_datao_fmc2[51] [6]),
- .I1(\s_datao_fmc2[50] [6]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[49] [6]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[48] [6]),
- .O(\axi_rdata_reg[6]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_25
- (.I0(\s_datao_fmc2[55] [6]),
- .I1(\s_datao_fmc2[54] [6]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[53] [6]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[52] [6]),
- .O(\axi_rdata[6]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_26
- (.I0(\s_datao_fmc2[59] [6]),
- .I1(\s_datao_fmc2[58] [6]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[57] [6]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[56] [6]),
- .O(\axi_rdata[6]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_27
- (.I0(\s_datao_fmc2[63] [6]),
- .I1(\s_datao_fmc2[62] [6]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[61] [6]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[60] [6]),
- .O(\axi_rdata[6]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[6]_i_28
- (.I0(\s_datao_fmc2[67] [6]),
- .I1(\s_datao_fmc2[66] [6]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[65] [6]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[64] [6]),
- .O(\axi_rdata[6]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_22
- (.I0(\s_datao_fmc2[51] [7]),
- .I1(\s_datao_fmc2[50] [7]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[49] [7]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[48] [7]),
- .O(\axi_rdata_reg[7]_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_25
- (.I0(\s_datao_fmc2[55] [7]),
- .I1(\s_datao_fmc2[54] [7]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[53] [7]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[52] [7]),
- .O(\axi_rdata[7]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_26
- (.I0(\s_datao_fmc2[59] [7]),
- .I1(\s_datao_fmc2[58] [7]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[57] [7]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[56] [7]),
- .O(\axi_rdata[7]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_27
- (.I0(\s_datao_fmc2[63] [7]),
- .I1(\s_datao_fmc2[62] [7]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[61] [7]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[60] [7]),
- .O(\axi_rdata[7]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[7]_i_28
- (.I0(\s_datao_fmc2[67] [7]),
- .I1(\s_datao_fmc2[66] [7]),
- .I2(\axi_araddr_reg[3]_rep__2 ),
- .I3(\s_datao_fmc2[65] [7]),
- .I4(\axi_araddr_reg[2]_rep__2 ),
- .I5(\s_datao_fmc2[64] [7]),
- .O(\axi_rdata[7]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_22
- (.I0(\s_datao_fmc2[51] [8]),
- .I1(\s_datao_fmc2[50] [8]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[49] [8]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[48] [8]),
- .O(\axi_rdata_reg[8] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_25
- (.I0(\s_datao_fmc2[55] [8]),
- .I1(\s_datao_fmc2[54] [8]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[53] [8]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[52] [8]),
- .O(\axi_rdata[8]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_26
- (.I0(\s_datao_fmc2[59] [8]),
- .I1(\s_datao_fmc2[58] [8]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[57] [8]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[56] [8]),
- .O(\axi_rdata[8]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_27
- (.I0(\s_datao_fmc2[63] [8]),
- .I1(\s_datao_fmc2[62] [8]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[61] [8]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[60] [8]),
- .O(\axi_rdata[8]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[8]_i_28
- (.I0(\s_datao_fmc2[67] [8]),
- .I1(\s_datao_fmc2[66] [8]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[65] [8]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[64] [8]),
- .O(\axi_rdata[8]_i_28_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_22
- (.I0(\s_datao_fmc2[51] [9]),
- .I1(\s_datao_fmc2[50] [9]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[49] [9]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[48] [9]),
- .O(\axi_rdata_reg[9] ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_25
- (.I0(\s_datao_fmc2[55] [9]),
- .I1(\s_datao_fmc2[54] [9]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[53] [9]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[52] [9]),
- .O(\axi_rdata[9]_i_25_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_26
- (.I0(\s_datao_fmc2[59] [9]),
- .I1(\s_datao_fmc2[58] [9]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[57] [9]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[56] [9]),
- .O(\axi_rdata[9]_i_26_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_27
- (.I0(\s_datao_fmc2[63] [9]),
- .I1(\s_datao_fmc2[62] [9]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[61] [9]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[60] [9]),
- .O(\axi_rdata[9]_i_27_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \axi_rdata[9]_i_28
- (.I0(\s_datao_fmc2[67] [9]),
- .I1(\s_datao_fmc2[66] [9]),
- .I2(\axi_araddr_reg[3]_rep__1 ),
- .I3(\s_datao_fmc2[65] [9]),
- .I4(\axi_araddr_reg[2]_rep__1 ),
- .I5(\s_datao_fmc2[64] [9]),
- .O(\axi_rdata[9]_i_28_n_0 ));
- MUXF7 \axi_rdata_reg[0]_i_10
- (.I0(\axi_rdata[0]_i_27_n_0 ),
- .I1(\axi_rdata[0]_i_28_n_0 ),
- .O(\axi_rdata_reg[0]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep__1 ));
- MUXF8 \axi_rdata_reg[0]_i_4
- (.I0(\axi_rdata_reg[0]_i_9_n_0 ),
- .I1(\axi_rdata_reg[0]_i_10_n_0 ),
- .O(\axi_rdata_reg[0]_1 ),
- .S(\axi_araddr_reg[5]_rep ));
- MUXF7 \axi_rdata_reg[0]_i_9
- (.I0(\axi_rdata[0]_i_25_n_0 ),
- .I1(\axi_rdata[0]_i_26_n_0 ),
- .O(\axi_rdata_reg[0]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep__1 ));
- MUXF7 \axi_rdata_reg[10]_i_10
- (.I0(\axi_rdata[10]_i_27_n_0 ),
- .I1(\axi_rdata[10]_i_28_n_0 ),
- .O(\axi_rdata_reg[10]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF8 \axi_rdata_reg[10]_i_4
- (.I0(\axi_rdata_reg[10]_i_9_n_0 ),
- .I1(\axi_rdata_reg[10]_i_10_n_0 ),
- .O(\axi_rdata_reg[10]_0 ),
- .S(\axi_araddr_reg[5]_rep ));
- MUXF7 \axi_rdata_reg[10]_i_9
- (.I0(\axi_rdata[10]_i_25_n_0 ),
- .I1(\axi_rdata[10]_i_26_n_0 ),
- .O(\axi_rdata_reg[10]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[11]_i_10
- (.I0(\axi_rdata[11]_i_27_n_0 ),
- .I1(\axi_rdata[11]_i_28_n_0 ),
- .O(\axi_rdata_reg[11]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF8 \axi_rdata_reg[11]_i_4
- (.I0(\axi_rdata_reg[11]_i_9_n_0 ),
- .I1(\axi_rdata_reg[11]_i_10_n_0 ),
- .O(\axi_rdata_reg[11]_0 ),
- .S(\axi_araddr_reg[5] [3]));
- MUXF7 \axi_rdata_reg[11]_i_9
- (.I0(\axi_rdata[11]_i_25_n_0 ),
- .I1(\axi_rdata[11]_i_26_n_0 ),
- .O(\axi_rdata_reg[11]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[12]_i_10
- (.I0(\axi_rdata[12]_i_27_n_0 ),
- .I1(\axi_rdata[12]_i_28_n_0 ),
- .O(\axi_rdata_reg[12]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF8 \axi_rdata_reg[12]_i_4
- (.I0(\axi_rdata_reg[12]_i_9_n_0 ),
- .I1(\axi_rdata_reg[12]_i_10_n_0 ),
- .O(\axi_rdata_reg[12]_0 ),
- .S(\axi_araddr_reg[5] [3]));
- MUXF7 \axi_rdata_reg[12]_i_9
- (.I0(\axi_rdata[12]_i_25_n_0 ),
- .I1(\axi_rdata[12]_i_26_n_0 ),
- .O(\axi_rdata_reg[12]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[13]_i_10
- (.I0(\axi_rdata[13]_i_27_n_0 ),
- .I1(\axi_rdata[13]_i_28_n_0 ),
- .O(\axi_rdata_reg[13]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF8 \axi_rdata_reg[13]_i_4
- (.I0(\axi_rdata_reg[13]_i_9_n_0 ),
- .I1(\axi_rdata_reg[13]_i_10_n_0 ),
- .O(\axi_rdata_reg[13]_0 ),
- .S(\axi_araddr_reg[5] [3]));
- MUXF7 \axi_rdata_reg[13]_i_9
- (.I0(\axi_rdata[13]_i_25_n_0 ),
- .I1(\axi_rdata[13]_i_26_n_0 ),
- .O(\axi_rdata_reg[13]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[14]_i_10
- (.I0(\axi_rdata[14]_i_27_n_0 ),
- .I1(\axi_rdata[14]_i_28_n_0 ),
- .O(\axi_rdata_reg[14]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF8 \axi_rdata_reg[14]_i_4
- (.I0(\axi_rdata_reg[14]_i_9_n_0 ),
- .I1(\axi_rdata_reg[14]_i_10_n_0 ),
- .O(\axi_rdata_reg[14]_0 ),
- .S(\axi_araddr_reg[5] [3]));
- MUXF7 \axi_rdata_reg[14]_i_9
- (.I0(\axi_rdata[14]_i_25_n_0 ),
- .I1(\axi_rdata[14]_i_26_n_0 ),
- .O(\axi_rdata_reg[14]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[15]_i_10
- (.I0(\axi_rdata[15]_i_27_n_0 ),
- .I1(\axi_rdata[15]_i_28_n_0 ),
- .O(\axi_rdata_reg[15]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF8 \axi_rdata_reg[15]_i_4
- (.I0(\axi_rdata_reg[15]_i_9_n_0 ),
- .I1(\axi_rdata_reg[15]_i_10_n_0 ),
- .O(\axi_rdata_reg[15]_0 ),
- .S(\axi_araddr_reg[5] [3]));
- MUXF7 \axi_rdata_reg[15]_i_9
- (.I0(\axi_rdata[15]_i_25_n_0 ),
- .I1(\axi_rdata[15]_i_26_n_0 ),
- .O(\axi_rdata_reg[15]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[16]_i_10
- (.I0(\axi_rdata[16]_i_27_n_0 ),
- .I1(\axi_rdata[16]_i_28_n_0 ),
- .O(\axi_rdata_reg[16]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF8 \axi_rdata_reg[16]_i_4
- (.I0(\axi_rdata_reg[16]_i_9_n_0 ),
- .I1(\axi_rdata_reg[16]_i_10_n_0 ),
- .O(\axi_rdata_reg[16]_0 ),
- .S(\axi_araddr_reg[5] [3]));
- MUXF7 \axi_rdata_reg[16]_i_9
- (.I0(\axi_rdata[16]_i_25_n_0 ),
- .I1(\axi_rdata[16]_i_26_n_0 ),
- .O(\axi_rdata_reg[16]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[17]_i_10
- (.I0(\axi_rdata[17]_i_27_n_0 ),
- .I1(\axi_rdata[17]_i_28_n_0 ),
- .O(\axi_rdata_reg[17]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF8 \axi_rdata_reg[17]_i_4
- (.I0(\axi_rdata_reg[17]_i_9_n_0 ),
- .I1(\axi_rdata_reg[17]_i_10_n_0 ),
- .O(\axi_rdata_reg[17]_0 ),
- .S(\axi_araddr_reg[5] [3]));
- MUXF7 \axi_rdata_reg[17]_i_9
- (.I0(\axi_rdata[17]_i_25_n_0 ),
- .I1(\axi_rdata[17]_i_26_n_0 ),
- .O(\axi_rdata_reg[17]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[18]_i_10
- (.I0(\axi_rdata[18]_i_27_n_0 ),
- .I1(\axi_rdata[18]_i_28_n_0 ),
- .O(\axi_rdata_reg[18]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF8 \axi_rdata_reg[18]_i_4
- (.I0(\axi_rdata_reg[18]_i_9_n_0 ),
- .I1(\axi_rdata_reg[18]_i_10_n_0 ),
- .O(\axi_rdata_reg[18]_0 ),
- .S(\axi_araddr_reg[5] [3]));
- MUXF7 \axi_rdata_reg[18]_i_9
- (.I0(\axi_rdata[18]_i_25_n_0 ),
- .I1(\axi_rdata[18]_i_26_n_0 ),
- .O(\axi_rdata_reg[18]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep ));
- MUXF7 \axi_rdata_reg[19]_i_10
- (.I0(\axi_rdata[19]_i_27_n_0 ),
- .I1(\axi_rdata[19]_i_28_n_0 ),
- .O(\axi_rdata_reg[19]_i_10_n_0 ),
- .S(\axi_araddr_reg[5] [2]));
- MUXF8 \axi_rdata_reg[19]_i_4
- (.I0(\axi_rdata_reg[19]_i_9_n_0 ),
- .I1(\axi_rdata_reg[19]_i_10_n_0 ),
- .O(\axi_rdata_reg[19]_0 ),
- .S(\axi_araddr_reg[5] [3]));
- MUXF7 \axi_rdata_reg[19]_i_9
- (.I0(\axi_rdata[19]_i_25_n_0 ),
- .I1(\axi_rdata[19]_i_26_n_0 ),
- .O(\axi_rdata_reg[19]_i_9_n_0 ),
- .S(\axi_araddr_reg[5] [2]));
- MUXF7 \axi_rdata_reg[1]_i_10
- (.I0(\axi_rdata[1]_i_27_n_0 ),
- .I1(\axi_rdata[1]_i_28_n_0 ),
- .O(\axi_rdata_reg[1]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF8 \axi_rdata_reg[1]_i_4
- (.I0(\axi_rdata_reg[1]_i_9_n_0 ),
- .I1(\axi_rdata_reg[1]_i_10_n_0 ),
- .O(\axi_rdata_reg[1]_1 ),
- .S(\axi_araddr_reg[5]_rep ));
- MUXF7 \axi_rdata_reg[1]_i_9
- (.I0(\axi_rdata[1]_i_25_n_0 ),
- .I1(\axi_rdata[1]_i_26_n_0 ),
- .O(\axi_rdata_reg[1]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[20]_i_3
- (.I0(\axi_rdata[20]_i_9_n_0 ),
- .I1(\axi_rdata[20]_i_10_n_0 ),
- .O(\axi_rdata_reg[20]_0 ),
- .S(\axi_araddr_reg[5] [2]));
- MUXF7 \axi_rdata_reg[20]_i_4
- (.I0(\axi_rdata[20]_i_11_n_0 ),
- .I1(\axi_rdata[20]_i_12_n_0 ),
- .O(\axi_rdata_reg[20]_1 ),
- .S(\axi_araddr_reg[5] [2]));
- MUXF7 \axi_rdata_reg[21]_i_3
- (.I0(\axi_rdata[21]_i_9_n_0 ),
- .I1(\axi_rdata[21]_i_10_n_0 ),
- .O(\axi_rdata_reg[21]_0 ),
- .S(\axi_araddr_reg[5] [2]));
- MUXF7 \axi_rdata_reg[21]_i_4
- (.I0(\axi_rdata[21]_i_11_n_0 ),
- .I1(\axi_rdata[21]_i_12_n_0 ),
- .O(\axi_rdata_reg[21]_1 ),
- .S(\axi_araddr_reg[5] [2]));
- MUXF7 \axi_rdata_reg[22]_i_3
- (.I0(\axi_rdata[22]_i_9_n_0 ),
- .I1(\axi_rdata[22]_i_10_n_0 ),
- .O(\axi_rdata_reg[22]_0 ),
- .S(\axi_araddr_reg[5] [2]));
- MUXF7 \axi_rdata_reg[22]_i_4
- (.I0(\axi_rdata[22]_i_11_n_0 ),
- .I1(\axi_rdata[22]_i_12_n_0 ),
- .O(\axi_rdata_reg[22]_1 ),
- .S(\axi_araddr_reg[5] [2]));
- MUXF7 \axi_rdata_reg[23]_i_4
- (.I0(\axi_rdata[23]_i_10_n_0 ),
- .I1(\axi_rdata[23]_i_11_n_0 ),
- .O(\axi_rdata_reg[23]_0 ),
- .S(\axi_araddr_reg[5] [2]));
- MUXF7 \axi_rdata_reg[23]_i_5
- (.I0(\axi_rdata[23]_i_12_n_0 ),
- .I1(\axi_rdata[23]_i_13_n_0 ),
- .O(\axi_rdata_reg[23]_1 ),
- .S(\axi_araddr_reg[5] [2]));
- MUXF7 \axi_rdata_reg[2]_i_10
- (.I0(\axi_rdata[2]_i_27_n_0 ),
- .I1(\axi_rdata[2]_i_28_n_0 ),
- .O(\axi_rdata_reg[2]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF8 \axi_rdata_reg[2]_i_4
- (.I0(\axi_rdata_reg[2]_i_9_n_0 ),
- .I1(\axi_rdata_reg[2]_i_10_n_0 ),
- .O(\axi_rdata_reg[2]_1 ),
- .S(\axi_araddr_reg[5]_rep ));
- MUXF7 \axi_rdata_reg[2]_i_9
- (.I0(\axi_rdata[2]_i_25_n_0 ),
- .I1(\axi_rdata[2]_i_26_n_0 ),
- .O(\axi_rdata_reg[2]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[3]_i_10
- (.I0(\axi_rdata[3]_i_27_n_0 ),
- .I1(\axi_rdata[3]_i_28_n_0 ),
- .O(\axi_rdata_reg[3]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF8 \axi_rdata_reg[3]_i_4
- (.I0(\axi_rdata_reg[3]_i_9_n_0 ),
- .I1(\axi_rdata_reg[3]_i_10_n_0 ),
- .O(\axi_rdata_reg[3]_1 ),
- .S(\axi_araddr_reg[5]_rep ));
- MUXF7 \axi_rdata_reg[3]_i_9
- (.I0(\axi_rdata[3]_i_25_n_0 ),
- .I1(\axi_rdata[3]_i_26_n_0 ),
- .O(\axi_rdata_reg[3]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[4]_i_10
- (.I0(\axi_rdata[4]_i_27_n_0 ),
- .I1(\axi_rdata[4]_i_28_n_0 ),
- .O(\axi_rdata_reg[4]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF8 \axi_rdata_reg[4]_i_4
- (.I0(\axi_rdata_reg[4]_i_9_n_0 ),
- .I1(\axi_rdata_reg[4]_i_10_n_0 ),
- .O(\axi_rdata_reg[4]_1 ),
- .S(\axi_araddr_reg[5]_rep ));
- MUXF7 \axi_rdata_reg[4]_i_9
- (.I0(\axi_rdata[4]_i_25_n_0 ),
- .I1(\axi_rdata[4]_i_26_n_0 ),
- .O(\axi_rdata_reg[4]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[5]_i_10
- (.I0(\axi_rdata[5]_i_27_n_0 ),
- .I1(\axi_rdata[5]_i_28_n_0 ),
- .O(\axi_rdata_reg[5]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF8 \axi_rdata_reg[5]_i_4
- (.I0(\axi_rdata_reg[5]_i_9_n_0 ),
- .I1(\axi_rdata_reg[5]_i_10_n_0 ),
- .O(\axi_rdata_reg[5]_1 ),
- .S(\axi_araddr_reg[5]_rep ));
- MUXF7 \axi_rdata_reg[5]_i_9
- (.I0(\axi_rdata[5]_i_25_n_0 ),
- .I1(\axi_rdata[5]_i_26_n_0 ),
- .O(\axi_rdata_reg[5]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[6]_i_10
- (.I0(\axi_rdata[6]_i_27_n_0 ),
- .I1(\axi_rdata[6]_i_28_n_0 ),
- .O(\axi_rdata_reg[6]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF8 \axi_rdata_reg[6]_i_4
- (.I0(\axi_rdata_reg[6]_i_9_n_0 ),
- .I1(\axi_rdata_reg[6]_i_10_n_0 ),
- .O(\axi_rdata_reg[6]_1 ),
- .S(\axi_araddr_reg[5]_rep ));
- MUXF7 \axi_rdata_reg[6]_i_9
- (.I0(\axi_rdata[6]_i_25_n_0 ),
- .I1(\axi_rdata[6]_i_26_n_0 ),
- .O(\axi_rdata_reg[6]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[7]_i_10
- (.I0(\axi_rdata[7]_i_27_n_0 ),
- .I1(\axi_rdata[7]_i_28_n_0 ),
- .O(\axi_rdata_reg[7]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF8 \axi_rdata_reg[7]_i_4
- (.I0(\axi_rdata_reg[7]_i_9_n_0 ),
- .I1(\axi_rdata_reg[7]_i_10_n_0 ),
- .O(\axi_rdata_reg[7]_1 ),
- .S(\axi_araddr_reg[5]_rep ));
- MUXF7 \axi_rdata_reg[7]_i_9
- (.I0(\axi_rdata[7]_i_25_n_0 ),
- .I1(\axi_rdata[7]_i_26_n_0 ),
- .O(\axi_rdata_reg[7]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[8]_i_10
- (.I0(\axi_rdata[8]_i_27_n_0 ),
- .I1(\axi_rdata[8]_i_28_n_0 ),
- .O(\axi_rdata_reg[8]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF8 \axi_rdata_reg[8]_i_4
- (.I0(\axi_rdata_reg[8]_i_9_n_0 ),
- .I1(\axi_rdata_reg[8]_i_10_n_0 ),
- .O(\axi_rdata_reg[8]_0 ),
- .S(\axi_araddr_reg[5]_rep ));
- MUXF7 \axi_rdata_reg[8]_i_9
- (.I0(\axi_rdata[8]_i_25_n_0 ),
- .I1(\axi_rdata[8]_i_26_n_0 ),
- .O(\axi_rdata_reg[8]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF7 \axi_rdata_reg[9]_i_10
- (.I0(\axi_rdata[9]_i_27_n_0 ),
- .I1(\axi_rdata[9]_i_28_n_0 ),
- .O(\axi_rdata_reg[9]_i_10_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- MUXF8 \axi_rdata_reg[9]_i_4
- (.I0(\axi_rdata_reg[9]_i_9_n_0 ),
- .I1(\axi_rdata_reg[9]_i_10_n_0 ),
- .O(\axi_rdata_reg[9]_0 ),
- .S(\axi_araddr_reg[5]_rep ));
- MUXF7 \axi_rdata_reg[9]_i_9
- (.I0(\axi_rdata[9]_i_25_n_0 ),
- .I1(\axi_rdata[9]_i_26_n_0 ),
- .O(\axi_rdata_reg[9]_i_9_n_0 ),
- .S(\axi_araddr_reg[4]_rep__0 ));
- FDRE \data_o_reg[1][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_fbd[0]),
- .Q(\axi_rdata_reg[3]_2 [0]),
- .R(1'b0));
- FDRE \data_o_reg[1][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_fbd[1]),
- .Q(\axi_rdata_reg[3]_2 [1]),
- .R(1'b0));
- FDRE \data_o_reg[1][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_fbd[2]),
- .Q(\axi_rdata_reg[3]_2 [2]),
- .R(1'b0));
- FDRE \data_o_reg[1][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_fbd[3]),
- .Q(\axi_rdata_reg[3]_2 [3]),
- .R(1'b0));
- FDRE \data_o_reg[6][0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D[0]),
- .Q(\s_datao_fmc2[6] [0]),
- .R(1'b0));
- FDRE \data_o_reg[6][1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D[1]),
- .Q(\s_datao_fmc2[6] [1]),
- .R(1'b0));
- FDRE \data_o_reg[6][2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D[2]),
- .Q(\s_datao_fmc2[6] [2]),
- .R(1'b0));
- FDRE \data_o_reg[6][3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(D[3]),
- .Q(\s_datao_fmc2[6] [3]),
- .R(1'b0));
- FDRE \data_o_reg[6][4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_diffouts_o[4]),
- .Q(\s_datao_fmc2[6] [4]),
- .R(1'b0));
- FDRE \data_o_reg[6][5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_diffouts_o[5]),
- .Q(\s_datao_fmc2[6] [5]),
- .R(1'b0));
- FDRE \data_o_reg[6][6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_diffouts_o[6]),
- .Q(\s_datao_fmc2[6] [6]),
- .R(1'b0));
- FDRE \data_o_reg[6][7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_diffouts_o[7]),
- .Q(\s_datao_fmc2[6] [7]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[0].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [0]),
- .IB(\FMC2_LA_N_b[32] [0]),
- .O(s_comparators_i_0));
- system_design_fasec_hwtest_0_0_pulseMeasure \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc2[0] [0]),
- .E(\cmp_lengthCounter/RSTP ),
- .Q(v_cmpled[2:0]),
- .S(\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_3 ),
- .\data_rw_o_reg[79][7] (\data_rw_o_reg[79][7] [2]),
- .\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] (\s_cmp_lengths[0]_0 ),
- .intr_o_reg(\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_4 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce ),
- .s_buff2_reg_0(\s_datao_fmc2[0] [2:1]),
- .s_comparators_i_0(s_comparators_i_0),
- .\s_datao_fmc2[4] (\s_datao_fmc2[4] [0]),
- .\s_debounce_reg[1] (s_buff2_i_1_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc2[4] [2:1]),
- .\v_cmp_reg[2] (v_cmp[2:0]),
- .\v_dout_reg[7] (\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2 ));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [0]),
- .Q(\s_datao_fmc2[48] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [10]),
- .Q(\s_datao_fmc2[48] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [11]),
- .Q(\s_datao_fmc2[48] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [12]),
- .Q(\s_datao_fmc2[48] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [13]),
- .Q(\s_datao_fmc2[48] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [14]),
- .Q(\s_datao_fmc2[48] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [15]),
- .Q(\s_datao_fmc2[48] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [16]),
- .Q(\s_datao_fmc2[48] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [17]),
- .Q(\s_datao_fmc2[48] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [18]),
- .Q(\s_datao_fmc2[48] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [19]),
- .Q(\s_datao_fmc2[48] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [1]),
- .Q(\s_datao_fmc2[48] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [20]),
- .Q(\s_datao_fmc2[48] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [21]),
- .Q(\s_datao_fmc2[48] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [22]),
- .Q(\s_datao_fmc2[48] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [23]),
- .Q(\s_datao_fmc2[48] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [2]),
- .Q(\s_datao_fmc2[48] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [3]),
- .Q(\s_datao_fmc2[48] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [4]),
- .Q(\s_datao_fmc2[48] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [5]),
- .Q(\s_datao_fmc2[48] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [6]),
- .Q(\s_datao_fmc2[48] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [7]),
- .Q(\s_datao_fmc2[48] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [8]),
- .Q(\s_datao_fmc2[48] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[0].gen_chs.data_o_reg[48][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP ),
- .D(\s_cmp_lengths[0]_0 [9]),
- .Q(\s_datao_fmc2[48] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[10].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [10]),
- .IB(\FMC2_LA_N_b[32] [10]),
- .O(s_comparators_i_10));
- system_design_fasec_hwtest_0_0_pulseMeasure_1 \fmc_03287_channels[10].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[2]),
- .E(\cmp_lengthCounter/RSTP_1 ),
- .Q(\cmp_pulseSync/s_debounce_0 ),
- .\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] (\s_cmp_lengths[10]_10 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc2[0] [10]),
- .s_comparators_i_10(s_comparators_i_10),
- .\s_debounce_reg[1] (s_buff2_i_1__9_n_0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [0]),
- .Q(\s_datao_fmc2[58] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [10]),
- .Q(\s_datao_fmc2[58] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [11]),
- .Q(\s_datao_fmc2[58] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [12]),
- .Q(\s_datao_fmc2[58] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [13]),
- .Q(\s_datao_fmc2[58] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [14]),
- .Q(\s_datao_fmc2[58] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [15]),
- .Q(\s_datao_fmc2[58] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [16]),
- .Q(\s_datao_fmc2[58] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [17]),
- .Q(\s_datao_fmc2[58] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [18]),
- .Q(\s_datao_fmc2[58] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [19]),
- .Q(\s_datao_fmc2[58] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [1]),
- .Q(\s_datao_fmc2[58] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [20]),
- .Q(\s_datao_fmc2[58] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [21]),
- .Q(\s_datao_fmc2[58] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [22]),
- .Q(\s_datao_fmc2[58] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [23]),
- .Q(\s_datao_fmc2[58] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [2]),
- .Q(\s_datao_fmc2[58] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [3]),
- .Q(\s_datao_fmc2[58] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [4]),
- .Q(\s_datao_fmc2[58] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [5]),
- .Q(\s_datao_fmc2[58] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [6]),
- .Q(\s_datao_fmc2[58] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [7]),
- .Q(\s_datao_fmc2[58] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [8]),
- .Q(\s_datao_fmc2[58] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[10].gen_chs.data_o_reg[58][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_1 ),
- .D(\s_cmp_lengths[10]_10 [9]),
- .Q(\s_datao_fmc2[58] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[11].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [11]),
- .IB(\FMC2_LA_N_b[32] [11]),
- .O(s_comparators_i_11));
- system_design_fasec_hwtest_0_0_pulseMeasure_2 \fmc_03287_channels[11].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[3]),
- .E(\cmp_lengthCounter/RSTP_3 ),
- .Q(\cmp_pulseSync/s_debounce_2 ),
- .\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] (\s_cmp_lengths[11]_11 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc2[0] [11]),
- .s_comparators_i_11(s_comparators_i_11),
- .\s_debounce_reg[1] (s_buff2_i_1__10_n_0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [0]),
- .Q(\s_datao_fmc2[59] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [10]),
- .Q(\s_datao_fmc2[59] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [11]),
- .Q(\s_datao_fmc2[59] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [12]),
- .Q(\s_datao_fmc2[59] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [13]),
- .Q(\s_datao_fmc2[59] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [14]),
- .Q(\s_datao_fmc2[59] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [15]),
- .Q(\s_datao_fmc2[59] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [16]),
- .Q(\s_datao_fmc2[59] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [17]),
- .Q(\s_datao_fmc2[59] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [18]),
- .Q(\s_datao_fmc2[59] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [19]),
- .Q(\s_datao_fmc2[59] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [1]),
- .Q(\s_datao_fmc2[59] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [20]),
- .Q(\s_datao_fmc2[59] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [21]),
- .Q(\s_datao_fmc2[59] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [22]),
- .Q(\s_datao_fmc2[59] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [23]),
- .Q(\s_datao_fmc2[59] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [2]),
- .Q(\s_datao_fmc2[59] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [3]),
- .Q(\s_datao_fmc2[59] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [4]),
- .Q(\s_datao_fmc2[59] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [5]),
- .Q(\s_datao_fmc2[59] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [6]),
- .Q(\s_datao_fmc2[59] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [7]),
- .Q(\s_datao_fmc2[59] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [8]),
- .Q(\s_datao_fmc2[59] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[11].gen_chs.data_o_reg[59][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_3 ),
- .D(\s_cmp_lengths[11]_11 [9]),
- .Q(\s_datao_fmc2[59] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[12].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [12]),
- .IB(\FMC2_LA_N_b[32] [12]),
- .O(s_comparators_i_12));
- system_design_fasec_hwtest_0_0_pulseMeasure_3 \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[4]),
- .E(\cmp_lengthCounter/RSTP_5 ),
- .Q(v_cmpled[14:12]),
- .S(\fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_2 ),
- .\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] (\s_cmp_lengths[12]_12 ),
- .intr_o_reg(\fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_3 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_4 ),
- .s_buff2_reg_0(\s_datao_fmc2[0] [14:13]),
- .s_buff3_reg(\s_datao_fmc2[0] [12]),
- .s_comparators_i_12(s_comparators_i_12),
- .\s_debounce_reg[1] (s_buff2_i_1__11_n_0),
- .s_pulseLed_reg_0(s_count_reg[6:5]),
- .\v_cmp_reg[14] (v_cmp[14:12]));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [0]),
- .Q(\s_datao_fmc2[60] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [10]),
- .Q(\s_datao_fmc2[60] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [11]),
- .Q(\s_datao_fmc2[60] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [12]),
- .Q(\s_datao_fmc2[60] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [13]),
- .Q(\s_datao_fmc2[60] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [14]),
- .Q(\s_datao_fmc2[60] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [15]),
- .Q(\s_datao_fmc2[60] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [16]),
- .Q(\s_datao_fmc2[60] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [17]),
- .Q(\s_datao_fmc2[60] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [18]),
- .Q(\s_datao_fmc2[60] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [19]),
- .Q(\s_datao_fmc2[60] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [1]),
- .Q(\s_datao_fmc2[60] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [20]),
- .Q(\s_datao_fmc2[60] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [21]),
- .Q(\s_datao_fmc2[60] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [22]),
- .Q(\s_datao_fmc2[60] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [23]),
- .Q(\s_datao_fmc2[60] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [2]),
- .Q(\s_datao_fmc2[60] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [3]),
- .Q(\s_datao_fmc2[60] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [4]),
- .Q(\s_datao_fmc2[60] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [5]),
- .Q(\s_datao_fmc2[60] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [6]),
- .Q(\s_datao_fmc2[60] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [7]),
- .Q(\s_datao_fmc2[60] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [8]),
- .Q(\s_datao_fmc2[60] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[12].gen_chs.data_o_reg[60][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_5 ),
- .D(\s_cmp_lengths[12]_12 [9]),
- .Q(\s_datao_fmc2[60] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[13].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [13]),
- .IB(\FMC2_LA_N_b[32] [13]),
- .O(s_comparators_i_13));
- system_design_fasec_hwtest_0_0_pulseMeasure_4 \fmc_03287_channels[13].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[5]),
- .E(\cmp_lengthCounter/RSTP_7 ),
- .Q(\cmp_pulseSync/s_debounce_6 ),
- .\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] (\s_cmp_lengths[13]_13 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc2[0] [13]),
- .s_comparators_i_13(s_comparators_i_13),
- .\s_debounce_reg[1] (s_buff2_i_1__12_n_0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [0]),
- .Q(\s_datao_fmc2[61] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [10]),
- .Q(\s_datao_fmc2[61] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [11]),
- .Q(\s_datao_fmc2[61] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [12]),
- .Q(\s_datao_fmc2[61] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [13]),
- .Q(\s_datao_fmc2[61] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [14]),
- .Q(\s_datao_fmc2[61] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [15]),
- .Q(\s_datao_fmc2[61] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [16]),
- .Q(\s_datao_fmc2[61] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [17]),
- .Q(\s_datao_fmc2[61] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [18]),
- .Q(\s_datao_fmc2[61] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [19]),
- .Q(\s_datao_fmc2[61] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [1]),
- .Q(\s_datao_fmc2[61] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [20]),
- .Q(\s_datao_fmc2[61] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [21]),
- .Q(\s_datao_fmc2[61] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [22]),
- .Q(\s_datao_fmc2[61] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [23]),
- .Q(\s_datao_fmc2[61] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [2]),
- .Q(\s_datao_fmc2[61] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [3]),
- .Q(\s_datao_fmc2[61] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [4]),
- .Q(\s_datao_fmc2[61] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [5]),
- .Q(\s_datao_fmc2[61] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [6]),
- .Q(\s_datao_fmc2[61] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [7]),
- .Q(\s_datao_fmc2[61] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [8]),
- .Q(\s_datao_fmc2[61] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[13].gen_chs.data_o_reg[61][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_7 ),
- .D(\s_cmp_lengths[13]_13 [9]),
- .Q(\s_datao_fmc2[61] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[14].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [14]),
- .IB(\FMC2_LA_N_b[32] [14]),
- .O(s_comparators_i_14));
- system_design_fasec_hwtest_0_0_pulseMeasure_5 \fmc_03287_channels[14].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[6]),
- .E(\cmp_lengthCounter/RSTP_9 ),
- .Q(\cmp_pulseSync/s_debounce_8 ),
- .\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] (\s_cmp_lengths[14]_14 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc2[0] [14]),
- .s_comparators_i_14(s_comparators_i_14),
- .\s_debounce_reg[1] (s_buff2_i_1__13_n_0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [0]),
- .Q(\s_datao_fmc2[62] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [10]),
- .Q(\s_datao_fmc2[62] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [11]),
- .Q(\s_datao_fmc2[62] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [12]),
- .Q(\s_datao_fmc2[62] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [13]),
- .Q(\s_datao_fmc2[62] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [14]),
- .Q(\s_datao_fmc2[62] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [15]),
- .Q(\s_datao_fmc2[62] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [16]),
- .Q(\s_datao_fmc2[62] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [17]),
- .Q(\s_datao_fmc2[62] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [18]),
- .Q(\s_datao_fmc2[62] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [19]),
- .Q(\s_datao_fmc2[62] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [1]),
- .Q(\s_datao_fmc2[62] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [20]),
- .Q(\s_datao_fmc2[62] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [21]),
- .Q(\s_datao_fmc2[62] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [22]),
- .Q(\s_datao_fmc2[62] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [23]),
- .Q(\s_datao_fmc2[62] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [2]),
- .Q(\s_datao_fmc2[62] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [3]),
- .Q(\s_datao_fmc2[62] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [4]),
- .Q(\s_datao_fmc2[62] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [5]),
- .Q(\s_datao_fmc2[62] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [6]),
- .Q(\s_datao_fmc2[62] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [7]),
- .Q(\s_datao_fmc2[62] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [8]),
- .Q(\s_datao_fmc2[62] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[14].gen_chs.data_o_reg[62][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_9 ),
- .D(\s_cmp_lengths[14]_14 [9]),
- .Q(\s_datao_fmc2[62] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[15].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [15]),
- .IB(\FMC2_LA_N_b[32] [15]),
- .O(s_comparators_i_15));
- system_design_fasec_hwtest_0_0_pulseMeasure_6 \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[7]),
- .E(\cmp_lengthCounter/RSTP_11 ),
- .Q(v_cmpled[17:15]),
- .S(\fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_2 ),
- .\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] (\s_cmp_lengths[15]_15 ),
- .intr_o_reg(\fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_3 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_10 ),
- .s_buff2_reg_0(\s_datao_fmc2[0] [17:16]),
- .s_buff3_reg(\s_datao_fmc2[0] [15]),
- .s_comparators_i_15(s_comparators_i_15),
- .\s_debounce_reg[1] (s_buff2_i_1__14_n_0),
- .s_pulseLed_reg_0(s_count_reg[9:8]),
- .\v_cmp_reg[17] (v_cmp[17:15]));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [0]),
- .Q(\s_datao_fmc2[63] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [10]),
- .Q(\s_datao_fmc2[63] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [11]),
- .Q(\s_datao_fmc2[63] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [12]),
- .Q(\s_datao_fmc2[63] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [13]),
- .Q(\s_datao_fmc2[63] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [14]),
- .Q(\s_datao_fmc2[63] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [15]),
- .Q(\s_datao_fmc2[63] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [16]),
- .Q(\s_datao_fmc2[63] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [17]),
- .Q(\s_datao_fmc2[63] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [18]),
- .Q(\s_datao_fmc2[63] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [19]),
- .Q(\s_datao_fmc2[63] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [1]),
- .Q(\s_datao_fmc2[63] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [20]),
- .Q(\s_datao_fmc2[63] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [21]),
- .Q(\s_datao_fmc2[63] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [22]),
- .Q(\s_datao_fmc2[63] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [23]),
- .Q(\s_datao_fmc2[63] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [2]),
- .Q(\s_datao_fmc2[63] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [3]),
- .Q(\s_datao_fmc2[63] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [4]),
- .Q(\s_datao_fmc2[63] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [5]),
- .Q(\s_datao_fmc2[63] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [6]),
- .Q(\s_datao_fmc2[63] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [7]),
- .Q(\s_datao_fmc2[63] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [8]),
- .Q(\s_datao_fmc2[63] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[15].gen_chs.data_o_reg[63][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_11 ),
- .D(\s_cmp_lengths[15]_15 [9]),
- .Q(\s_datao_fmc2[63] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[16].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [16]),
- .IB(\FMC2_LA_N_b[32] [16]),
- .O(s_comparators_i_16));
- system_design_fasec_hwtest_0_0_pulseMeasure_7 \fmc_03287_channels[16].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[8]),
- .E(\cmp_lengthCounter/RSTP_13 ),
- .Q(\cmp_pulseSync/s_debounce_12 ),
- .\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] (\s_cmp_lengths[16]_16 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc2[0] [16]),
- .s_comparators_i_16(s_comparators_i_16),
- .\s_debounce_reg[1] (s_buff2_i_1__15_n_0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [0]),
- .Q(\s_datao_fmc2[64] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [10]),
- .Q(\s_datao_fmc2[64] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [11]),
- .Q(\s_datao_fmc2[64] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [12]),
- .Q(\s_datao_fmc2[64] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [13]),
- .Q(\s_datao_fmc2[64] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [14]),
- .Q(\s_datao_fmc2[64] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [15]),
- .Q(\s_datao_fmc2[64] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [16]),
- .Q(\s_datao_fmc2[64] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [17]),
- .Q(\s_datao_fmc2[64] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [18]),
- .Q(\s_datao_fmc2[64] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [19]),
- .Q(\s_datao_fmc2[64] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [1]),
- .Q(\s_datao_fmc2[64] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [20]),
- .Q(\s_datao_fmc2[64] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [21]),
- .Q(\s_datao_fmc2[64] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [22]),
- .Q(\s_datao_fmc2[64] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [23]),
- .Q(\s_datao_fmc2[64] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [2]),
- .Q(\s_datao_fmc2[64] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [3]),
- .Q(\s_datao_fmc2[64] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [4]),
- .Q(\s_datao_fmc2[64] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [5]),
- .Q(\s_datao_fmc2[64] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [6]),
- .Q(\s_datao_fmc2[64] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [7]),
- .Q(\s_datao_fmc2[64] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [8]),
- .Q(\s_datao_fmc2[64] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[16].gen_chs.data_o_reg[64][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_13 ),
- .D(\s_cmp_lengths[16]_16 [9]),
- .Q(\s_datao_fmc2[64] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[17].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [17]),
- .IB(\FMC2_LA_N_b[32] [17]),
- .O(s_comparators_i_17));
- system_design_fasec_hwtest_0_0_pulseMeasure_8 \fmc_03287_channels[17].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[9]),
- .E(\cmp_lengthCounter/RSTP_15 ),
- .Q(\cmp_pulseSync/s_debounce_14 ),
- .\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] (\s_cmp_lengths[17]_17 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc2[0] [17]),
- .s_comparators_i_17(s_comparators_i_17),
- .\s_debounce_reg[1] (s_buff2_i_1__16_n_0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [0]),
- .Q(\s_datao_fmc2[65] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [10]),
- .Q(\s_datao_fmc2[65] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [11]),
- .Q(\s_datao_fmc2[65] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [12]),
- .Q(\s_datao_fmc2[65] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [13]),
- .Q(\s_datao_fmc2[65] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [14]),
- .Q(\s_datao_fmc2[65] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [15]),
- .Q(\s_datao_fmc2[65] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [16]),
- .Q(\s_datao_fmc2[65] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [17]),
- .Q(\s_datao_fmc2[65] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [18]),
- .Q(\s_datao_fmc2[65] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [19]),
- .Q(\s_datao_fmc2[65] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [1]),
- .Q(\s_datao_fmc2[65] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [20]),
- .Q(\s_datao_fmc2[65] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [21]),
- .Q(\s_datao_fmc2[65] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [22]),
- .Q(\s_datao_fmc2[65] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [23]),
- .Q(\s_datao_fmc2[65] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [2]),
- .Q(\s_datao_fmc2[65] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [3]),
- .Q(\s_datao_fmc2[65] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [4]),
- .Q(\s_datao_fmc2[65] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [5]),
- .Q(\s_datao_fmc2[65] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [6]),
- .Q(\s_datao_fmc2[65] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [7]),
- .Q(\s_datao_fmc2[65] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [8]),
- .Q(\s_datao_fmc2[65] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[17].gen_chs.data_o_reg[65][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_15 ),
- .D(\s_cmp_lengths[17]_17 [9]),
- .Q(\s_datao_fmc2[65] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[18].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [18]),
- .IB(\FMC2_LA_N_b[32] [18]),
- .O(s_comparators_i_18));
- system_design_fasec_hwtest_0_0_pulseMeasure_9 \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[10]),
- .E(\cmp_lengthCounter/RSTP_17 ),
- .Q(v_cmpled[19:18]),
- .S(\fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_2 ),
- .\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] (\s_cmp_lengths[18]_18 ),
- .intr_o_reg(\fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_3 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_16 ),
- .s_buff2_reg_0(\s_datao_fmc2[0] [19]),
- .s_buff3_reg(\s_datao_fmc2[0] [18]),
- .s_comparators_i_18(s_comparators_i_18),
- .\s_debounce_reg[1] (s_buff2_i_1__17_n_0),
- .s_pulseLed_reg_0(s_count_reg[11]),
- .\v_cmp_reg[19] (v_cmp[19:18]));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [0]),
- .Q(\s_datao_fmc2[66] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [10]),
- .Q(\s_datao_fmc2[66] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [11]),
- .Q(\s_datao_fmc2[66] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [12]),
- .Q(\s_datao_fmc2[66] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [13]),
- .Q(\s_datao_fmc2[66] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [14]),
- .Q(\s_datao_fmc2[66] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [15]),
- .Q(\s_datao_fmc2[66] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [16]),
- .Q(\s_datao_fmc2[66] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [17]),
- .Q(\s_datao_fmc2[66] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [18]),
- .Q(\s_datao_fmc2[66] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [19]),
- .Q(\s_datao_fmc2[66] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [1]),
- .Q(\s_datao_fmc2[66] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [20]),
- .Q(\s_datao_fmc2[66] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [21]),
- .Q(\s_datao_fmc2[66] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [22]),
- .Q(\s_datao_fmc2[66] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [23]),
- .Q(\s_datao_fmc2[66] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [2]),
- .Q(\s_datao_fmc2[66] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [3]),
- .Q(\s_datao_fmc2[66] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [4]),
- .Q(\s_datao_fmc2[66] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [5]),
- .Q(\s_datao_fmc2[66] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [6]),
- .Q(\s_datao_fmc2[66] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [7]),
- .Q(\s_datao_fmc2[66] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [8]),
- .Q(\s_datao_fmc2[66] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[18].gen_chs.data_o_reg[66][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_17 ),
- .D(\s_cmp_lengths[18]_18 [9]),
- .Q(\s_datao_fmc2[66] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[19].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [19]),
- .IB(\FMC2_LA_N_b[32] [19]),
- .O(s_comparators_i_19));
- system_design_fasec_hwtest_0_0_pulseMeasure_10 \fmc_03287_channels[19].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[11]),
- .E(\cmp_lengthCounter/RSTP_19 ),
- .Q(\cmp_pulseSync/s_debounce_18 ),
- .\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] (\s_cmp_lengths[19]_19 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc2[0] [19]),
- .s_comparators_i_19(s_comparators_i_19),
- .\s_debounce_reg[1] (s_buff2_i_1__18_n_0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [0]),
- .Q(\s_datao_fmc2[67] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [10]),
- .Q(\s_datao_fmc2[67] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [11]),
- .Q(\s_datao_fmc2[67] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [12]),
- .Q(\s_datao_fmc2[67] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [13]),
- .Q(\s_datao_fmc2[67] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [14]),
- .Q(\s_datao_fmc2[67] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [15]),
- .Q(\s_datao_fmc2[67] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [16]),
- .Q(\s_datao_fmc2[67] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [17]),
- .Q(\s_datao_fmc2[67] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [18]),
- .Q(\s_datao_fmc2[67] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [19]),
- .Q(\s_datao_fmc2[67] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [1]),
- .Q(\s_datao_fmc2[67] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [20]),
- .Q(\s_datao_fmc2[67] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [21]),
- .Q(\s_datao_fmc2[67] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [22]),
- .Q(\s_datao_fmc2[67] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [23]),
- .Q(\s_datao_fmc2[67] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [2]),
- .Q(\s_datao_fmc2[67] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [3]),
- .Q(\s_datao_fmc2[67] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [4]),
- .Q(\s_datao_fmc2[67] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [5]),
- .Q(\s_datao_fmc2[67] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [6]),
- .Q(\s_datao_fmc2[67] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [7]),
- .Q(\s_datao_fmc2[67] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [8]),
- .Q(\s_datao_fmc2[67] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[19].gen_chs.data_o_reg[67][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_19 ),
- .D(\s_cmp_lengths[19]_19 [9]),
- .Q(\s_datao_fmc2[67] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[1].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [1]),
- .IB(\FMC2_LA_N_b[32] [1]),
- .O(s_comparators_i_1));
- system_design_fasec_hwtest_0_0_pulseMeasure_11 \fmc_03287_channels[1].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc2[0] [1]),
- .E(\cmp_lengthCounter/RSTP_21 ),
- .Q(\cmp_pulseSync/s_debounce_20 ),
- .\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] (\s_cmp_lengths[1]_1 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_comparators_i_1(s_comparators_i_1),
- .s_count_reg(\s_datao_fmc2[4] [1]),
- .\s_debounce_reg[1] (s_buff2_i_1__0_n_0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [0]),
- .Q(\s_datao_fmc2[49] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [10]),
- .Q(\s_datao_fmc2[49] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [11]),
- .Q(\s_datao_fmc2[49] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [12]),
- .Q(\s_datao_fmc2[49] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [13]),
- .Q(\s_datao_fmc2[49] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [14]),
- .Q(\s_datao_fmc2[49] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [15]),
- .Q(\s_datao_fmc2[49] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [16]),
- .Q(\s_datao_fmc2[49] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [17]),
- .Q(\s_datao_fmc2[49] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [18]),
- .Q(\s_datao_fmc2[49] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [19]),
- .Q(\s_datao_fmc2[49] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [1]),
- .Q(\s_datao_fmc2[49] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [20]),
- .Q(\s_datao_fmc2[49] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [21]),
- .Q(\s_datao_fmc2[49] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [22]),
- .Q(\s_datao_fmc2[49] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [23]),
- .Q(\s_datao_fmc2[49] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [2]),
- .Q(\s_datao_fmc2[49] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [3]),
- .Q(\s_datao_fmc2[49] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [4]),
- .Q(\s_datao_fmc2[49] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [5]),
- .Q(\s_datao_fmc2[49] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [6]),
- .Q(\s_datao_fmc2[49] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [7]),
- .Q(\s_datao_fmc2[49] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [8]),
- .Q(\s_datao_fmc2[49] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[1].gen_chs.data_o_reg[49][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_21 ),
- .D(\s_cmp_lengths[1]_1 [9]),
- .Q(\s_datao_fmc2[49] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[2].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [2]),
- .IB(\FMC2_LA_N_b[32] [2]),
- .O(s_comparators_i_2));
- system_design_fasec_hwtest_0_0_pulseMeasure_12 \fmc_03287_channels[2].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc2[0] [2]),
- .E(\cmp_lengthCounter/RSTP_23 ),
- .Q(\cmp_pulseSync/s_debounce_22 ),
- .\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] (\s_cmp_lengths[2]_2 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_comparators_i_2(s_comparators_i_2),
- .s_count_reg(\s_datao_fmc2[4] [2]),
- .\s_debounce_reg[1] (s_buff2_i_1__1_n_0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [0]),
- .Q(\s_datao_fmc2[50] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [10]),
- .Q(\s_datao_fmc2[50] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [11]),
- .Q(\s_datao_fmc2[50] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [12]),
- .Q(\s_datao_fmc2[50] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [13]),
- .Q(\s_datao_fmc2[50] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [14]),
- .Q(\s_datao_fmc2[50] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [15]),
- .Q(\s_datao_fmc2[50] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [16]),
- .Q(\s_datao_fmc2[50] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [17]),
- .Q(\s_datao_fmc2[50] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [18]),
- .Q(\s_datao_fmc2[50] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [19]),
- .Q(\s_datao_fmc2[50] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [1]),
- .Q(\s_datao_fmc2[50] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [20]),
- .Q(\s_datao_fmc2[50] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [21]),
- .Q(\s_datao_fmc2[50] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [22]),
- .Q(\s_datao_fmc2[50] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [23]),
- .Q(\s_datao_fmc2[50] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [2]),
- .Q(\s_datao_fmc2[50] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [3]),
- .Q(\s_datao_fmc2[50] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [4]),
- .Q(\s_datao_fmc2[50] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [5]),
- .Q(\s_datao_fmc2[50] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [6]),
- .Q(\s_datao_fmc2[50] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [7]),
- .Q(\s_datao_fmc2[50] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [8]),
- .Q(\s_datao_fmc2[50] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[2].gen_chs.data_o_reg[50][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_23 ),
- .D(\s_cmp_lengths[2]_2 [9]),
- .Q(\s_datao_fmc2[50] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[3].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [3]),
- .IB(\FMC2_LA_N_b[32] [3]),
- .O(s_comparators_i_3));
- system_design_fasec_hwtest_0_0_pulseMeasure_13 \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc2[0] [3]),
- .E(\cmp_lengthCounter/RSTP_25 ),
- .Q(v_cmpled[5:3]),
- .S(\fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_2 ),
- .\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] (\s_cmp_lengths[3]_3 ),
- .intr_o_reg(\fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_3 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_24 ),
- .s_buff2_reg_0(\s_datao_fmc2[0] [5:4]),
- .s_comparators_i_3(s_comparators_i_3),
- .\s_datao_fmc2[4] (\s_datao_fmc2[4] [3]),
- .\s_debounce_reg[1] (s_buff2_i_1__2_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc2[4] [5:4]),
- .\v_cmp_reg[5] (v_cmp[5:3]));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [0]),
- .Q(\s_datao_fmc2[51] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [10]),
- .Q(\s_datao_fmc2[51] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [11]),
- .Q(\s_datao_fmc2[51] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [12]),
- .Q(\s_datao_fmc2[51] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [13]),
- .Q(\s_datao_fmc2[51] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [14]),
- .Q(\s_datao_fmc2[51] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [15]),
- .Q(\s_datao_fmc2[51] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [16]),
- .Q(\s_datao_fmc2[51] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [17]),
- .Q(\s_datao_fmc2[51] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [18]),
- .Q(\s_datao_fmc2[51] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [19]),
- .Q(\s_datao_fmc2[51] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [1]),
- .Q(\s_datao_fmc2[51] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [20]),
- .Q(\s_datao_fmc2[51] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [21]),
- .Q(\s_datao_fmc2[51] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [22]),
- .Q(\s_datao_fmc2[51] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [23]),
- .Q(\s_datao_fmc2[51] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [2]),
- .Q(\s_datao_fmc2[51] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [3]),
- .Q(\s_datao_fmc2[51] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [4]),
- .Q(\s_datao_fmc2[51] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [5]),
- .Q(\s_datao_fmc2[51] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [6]),
- .Q(\s_datao_fmc2[51] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [7]),
- .Q(\s_datao_fmc2[51] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [8]),
- .Q(\s_datao_fmc2[51] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[3].gen_chs.data_o_reg[51][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_25 ),
- .D(\s_cmp_lengths[3]_3 [9]),
- .Q(\s_datao_fmc2[51] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[4].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [4]),
- .IB(\FMC2_LA_N_b[32] [4]),
- .O(s_comparators_i_4));
- system_design_fasec_hwtest_0_0_pulseMeasure_14 \fmc_03287_channels[4].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc2[0] [4]),
- .E(\cmp_lengthCounter/RSTP_27 ),
- .Q(\cmp_pulseSync/s_debounce_26 ),
- .\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] (\s_cmp_lengths[4]_4 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_comparators_i_4(s_comparators_i_4),
- .s_count_reg(\s_datao_fmc2[4] [4]),
- .\s_debounce_reg[1] (s_buff2_i_1__3_n_0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [0]),
- .Q(\s_datao_fmc2[52] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [10]),
- .Q(\s_datao_fmc2[52] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [11]),
- .Q(\s_datao_fmc2[52] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [12]),
- .Q(\s_datao_fmc2[52] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [13]),
- .Q(\s_datao_fmc2[52] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [14]),
- .Q(\s_datao_fmc2[52] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [15]),
- .Q(\s_datao_fmc2[52] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [16]),
- .Q(\s_datao_fmc2[52] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [17]),
- .Q(\s_datao_fmc2[52] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [18]),
- .Q(\s_datao_fmc2[52] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [19]),
- .Q(\s_datao_fmc2[52] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [1]),
- .Q(\s_datao_fmc2[52] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [20]),
- .Q(\s_datao_fmc2[52] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [21]),
- .Q(\s_datao_fmc2[52] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [22]),
- .Q(\s_datao_fmc2[52] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [23]),
- .Q(\s_datao_fmc2[52] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [2]),
- .Q(\s_datao_fmc2[52] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [3]),
- .Q(\s_datao_fmc2[52] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [4]),
- .Q(\s_datao_fmc2[52] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [5]),
- .Q(\s_datao_fmc2[52] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [6]),
- .Q(\s_datao_fmc2[52] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [7]),
- .Q(\s_datao_fmc2[52] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [8]),
- .Q(\s_datao_fmc2[52] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[4].gen_chs.data_o_reg[52][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_27 ),
- .D(\s_cmp_lengths[4]_4 [9]),
- .Q(\s_datao_fmc2[52] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[5].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [5]),
- .IB(\FMC2_LA_N_b[32] [5]),
- .O(s_comparators_i_5));
- system_design_fasec_hwtest_0_0_pulseMeasure_15 \fmc_03287_channels[5].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc2[0] [5]),
- .E(\cmp_lengthCounter/RSTP_29 ),
- .Q(\cmp_pulseSync/s_debounce_28 ),
- .\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] (\s_cmp_lengths[5]_5 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_comparators_i_5(s_comparators_i_5),
- .s_count_reg(\s_datao_fmc2[4] [5]),
- .\s_debounce_reg[1] (s_buff2_i_1__4_n_0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [0]),
- .Q(\s_datao_fmc2[53] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [10]),
- .Q(\s_datao_fmc2[53] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [11]),
- .Q(\s_datao_fmc2[53] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [12]),
- .Q(\s_datao_fmc2[53] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [13]),
- .Q(\s_datao_fmc2[53] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [14]),
- .Q(\s_datao_fmc2[53] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [15]),
- .Q(\s_datao_fmc2[53] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [16]),
- .Q(\s_datao_fmc2[53] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [17]),
- .Q(\s_datao_fmc2[53] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [18]),
- .Q(\s_datao_fmc2[53] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [19]),
- .Q(\s_datao_fmc2[53] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [1]),
- .Q(\s_datao_fmc2[53] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [20]),
- .Q(\s_datao_fmc2[53] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [21]),
- .Q(\s_datao_fmc2[53] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [22]),
- .Q(\s_datao_fmc2[53] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [23]),
- .Q(\s_datao_fmc2[53] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [2]),
- .Q(\s_datao_fmc2[53] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [3]),
- .Q(\s_datao_fmc2[53] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [4]),
- .Q(\s_datao_fmc2[53] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [5]),
- .Q(\s_datao_fmc2[53] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [6]),
- .Q(\s_datao_fmc2[53] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [7]),
- .Q(\s_datao_fmc2[53] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [8]),
- .Q(\s_datao_fmc2[53] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[5].gen_chs.data_o_reg[53][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_29 ),
- .D(\s_cmp_lengths[5]_5 [9]),
- .Q(\s_datao_fmc2[53] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[6].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [6]),
- .IB(\FMC2_LA_N_b[32] [6]),
- .O(s_comparators_i_6));
- system_design_fasec_hwtest_0_0_pulseMeasure_16 \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc2[0] [6]),
- .E(\cmp_lengthCounter/RSTP_31 ),
- .Q(v_cmpled[8:6]),
- .S(\fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_2 ),
- .\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] (\s_cmp_lengths[6]_6 ),
- .intr_o_reg(\fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_3 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_30 ),
- .s_buff2_reg_0(\s_datao_fmc2[0] [8:7]),
- .s_comparators_i_6(s_comparators_i_6),
- .\s_datao_fmc2[4] (\s_datao_fmc2[4] [6]),
- .\s_debounce_reg[1] (s_buff2_i_1__5_n_0),
- .s_pulseLed_reg_0({s_count_reg[0],\s_datao_fmc2[4] [7]}),
- .\v_cmp_reg[8] (v_cmp[8:6]));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [0]),
- .Q(\s_datao_fmc2[54] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [10]),
- .Q(\s_datao_fmc2[54] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [11]),
- .Q(\s_datao_fmc2[54] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [12]),
- .Q(\s_datao_fmc2[54] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [13]),
- .Q(\s_datao_fmc2[54] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [14]),
- .Q(\s_datao_fmc2[54] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [15]),
- .Q(\s_datao_fmc2[54] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [16]),
- .Q(\s_datao_fmc2[54] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [17]),
- .Q(\s_datao_fmc2[54] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [18]),
- .Q(\s_datao_fmc2[54] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [19]),
- .Q(\s_datao_fmc2[54] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [1]),
- .Q(\s_datao_fmc2[54] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [20]),
- .Q(\s_datao_fmc2[54] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [21]),
- .Q(\s_datao_fmc2[54] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [22]),
- .Q(\s_datao_fmc2[54] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [23]),
- .Q(\s_datao_fmc2[54] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [2]),
- .Q(\s_datao_fmc2[54] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [3]),
- .Q(\s_datao_fmc2[54] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [4]),
- .Q(\s_datao_fmc2[54] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [5]),
- .Q(\s_datao_fmc2[54] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [6]),
- .Q(\s_datao_fmc2[54] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [7]),
- .Q(\s_datao_fmc2[54] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [8]),
- .Q(\s_datao_fmc2[54] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[6].gen_chs.data_o_reg[54][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_31 ),
- .D(\s_cmp_lengths[6]_6 [9]),
- .Q(\s_datao_fmc2[54] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[7].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [7]),
- .IB(\FMC2_LA_N_b[32] [7]),
- .O(s_comparators_i_7));
- system_design_fasec_hwtest_0_0_pulseMeasure_17 \fmc_03287_channels[7].gen_chs.cmp_ch_pulseMeasure
- (.D(\s_datao_fmc2[0] [7]),
- .E(\cmp_lengthCounter/RSTP_33 ),
- .Q(\cmp_pulseSync/s_debounce_32 ),
- .\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] (\s_cmp_lengths[7]_7 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_comparators_i_7(s_comparators_i_7),
- .s_count_reg(\s_datao_fmc2[4] [7]),
- .\s_debounce_reg[1] (s_buff2_i_1__6_n_0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [0]),
- .Q(\s_datao_fmc2[55] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [10]),
- .Q(\s_datao_fmc2[55] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [11]),
- .Q(\s_datao_fmc2[55] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [12]),
- .Q(\s_datao_fmc2[55] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [13]),
- .Q(\s_datao_fmc2[55] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [14]),
- .Q(\s_datao_fmc2[55] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [15]),
- .Q(\s_datao_fmc2[55] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [16]),
- .Q(\s_datao_fmc2[55] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [17]),
- .Q(\s_datao_fmc2[55] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [18]),
- .Q(\s_datao_fmc2[55] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [19]),
- .Q(\s_datao_fmc2[55] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [1]),
- .Q(\s_datao_fmc2[55] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [20]),
- .Q(\s_datao_fmc2[55] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [21]),
- .Q(\s_datao_fmc2[55] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [22]),
- .Q(\s_datao_fmc2[55] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [23]),
- .Q(\s_datao_fmc2[55] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [2]),
- .Q(\s_datao_fmc2[55] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [3]),
- .Q(\s_datao_fmc2[55] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [4]),
- .Q(\s_datao_fmc2[55] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [5]),
- .Q(\s_datao_fmc2[55] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [6]),
- .Q(\s_datao_fmc2[55] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [7]),
- .Q(\s_datao_fmc2[55] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [8]),
- .Q(\s_datao_fmc2[55] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[7].gen_chs.data_o_reg[55][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_33 ),
- .D(\s_cmp_lengths[7]_7 [9]),
- .Q(\s_datao_fmc2[55] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[8].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [8]),
- .IB(\FMC2_LA_N_b[32] [8]),
- .O(s_comparators_i_8));
- system_design_fasec_hwtest_0_0_pulseMeasure_18 \fmc_03287_channels[8].gen_chs.cmp_ch_pulseMeasure
- (.D(s_count_reg[0]),
- .E(\cmp_lengthCounter/RSTP_35 ),
- .Q(\cmp_pulseSync/s_debounce_34 ),
- .\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] (\s_cmp_lengths[8]_8 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg(\s_datao_fmc2[0] [8]),
- .s_comparators_i_8(s_comparators_i_8),
- .\s_debounce_reg[1] (s_buff2_i_1__7_n_0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [0]),
- .Q(\s_datao_fmc2[56] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [10]),
- .Q(\s_datao_fmc2[56] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [11]),
- .Q(\s_datao_fmc2[56] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [12]),
- .Q(\s_datao_fmc2[56] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [13]),
- .Q(\s_datao_fmc2[56] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [14]),
- .Q(\s_datao_fmc2[56] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [15]),
- .Q(\s_datao_fmc2[56] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [16]),
- .Q(\s_datao_fmc2[56] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [17]),
- .Q(\s_datao_fmc2[56] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [18]),
- .Q(\s_datao_fmc2[56] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [19]),
- .Q(\s_datao_fmc2[56] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [1]),
- .Q(\s_datao_fmc2[56] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [20]),
- .Q(\s_datao_fmc2[56] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [21]),
- .Q(\s_datao_fmc2[56] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [22]),
- .Q(\s_datao_fmc2[56] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [23]),
- .Q(\s_datao_fmc2[56] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [2]),
- .Q(\s_datao_fmc2[56] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [3]),
- .Q(\s_datao_fmc2[56] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [4]),
- .Q(\s_datao_fmc2[56] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [5]),
- .Q(\s_datao_fmc2[56] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [6]),
- .Q(\s_datao_fmc2[56] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [7]),
- .Q(\s_datao_fmc2[56] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [8]),
- .Q(\s_datao_fmc2[56] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[8].gen_chs.data_o_reg[56][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_35 ),
- .D(\s_cmp_lengths[8]_8 [9]),
- .Q(\s_datao_fmc2[56] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* IBUF_DELAY_VALUE = "0" *)
- (* IFD_DELAY_VALUE = "AUTO" *)
- (* box_type = "PRIMITIVE" *)
- IBUFDS #(
- .DQS_BIAS("FALSE"),
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_channels[9].gen_chs.cmp_IBUFDS_fmc
- (.I(\FMC2_LA_P_b[32] [9]),
- .IB(\FMC2_LA_N_b[32] [9]),
- .O(s_comparators_i_9));
- system_design_fasec_hwtest_0_0_pulseMeasure_19 \fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure
- (.CO(intr_o0),
- .D(s_count_reg[1]),
- .E(\cmp_lengthCounter/RSTP_37 ),
- .Q(v_cmpled[11:9]),
- .S({\fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_2 ,\fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_2 ,\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_3 }),
- .\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] (\s_cmp_lengths[9]_9 ),
- .intr_led_o_reg(\fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure_n_2 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_36 ),
- .s_buff2_reg_0(\s_datao_fmc2[0] [11:10]),
- .s_buff3_reg(\s_datao_fmc2[0] [9]),
- .s_comparators_i_9(s_comparators_i_9),
- .\s_debounce_reg[1] (s_buff2_i_1__8_n_0),
- .s_pulseLed_reg_0(\fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_3 ),
- .s_pulseLed_reg_1(s_count_reg[3:2]),
- .\v_cmp_reg[11] (v_cmp[11:9]),
- .\v_cmp_reg[18] ({\fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_3 ,\fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_3 ,\fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_3 }),
- .\v_cmp_reg[6] ({\fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_3 ,\fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_3 ,\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_4 }),
- .\v_cmpled_reg[18] ({\fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_2 ,\fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_2 ,\fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_2 }));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][0]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [0]),
- .Q(\s_datao_fmc2[57] [0]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][10]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [10]),
- .Q(\s_datao_fmc2[57] [10]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][11]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [11]),
- .Q(\s_datao_fmc2[57] [11]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][12]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [12]),
- .Q(\s_datao_fmc2[57] [12]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][13]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [13]),
- .Q(\s_datao_fmc2[57] [13]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][14]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [14]),
- .Q(\s_datao_fmc2[57] [14]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][15]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [15]),
- .Q(\s_datao_fmc2[57] [15]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][16]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [16]),
- .Q(\s_datao_fmc2[57] [16]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][17]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [17]),
- .Q(\s_datao_fmc2[57] [17]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][18]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [18]),
- .Q(\s_datao_fmc2[57] [18]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][19]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [19]),
- .Q(\s_datao_fmc2[57] [19]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][1]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [1]),
- .Q(\s_datao_fmc2[57] [1]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][20]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [20]),
- .Q(\s_datao_fmc2[57] [20]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][21]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [21]),
- .Q(\s_datao_fmc2[57] [21]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][22]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [22]),
- .Q(\s_datao_fmc2[57] [22]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [23]),
- .Q(\s_datao_fmc2[57] [23]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][2]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [2]),
- .Q(\s_datao_fmc2[57] [2]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][3]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [3]),
- .Q(\s_datao_fmc2[57] [3]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][4]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [4]),
- .Q(\s_datao_fmc2[57] [4]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][5]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [5]),
- .Q(\s_datao_fmc2[57] [5]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][6]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [6]),
- .Q(\s_datao_fmc2[57] [6]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][7]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [7]),
- .Q(\s_datao_fmc2[57] [7]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][8]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [8]),
- .Q(\s_datao_fmc2[57] [8]),
- .R(1'b0));
- FDRE \fmc_03287_channels[9].gen_chs.data_o_reg[57][9]
- (.C(s00_axi_aclk),
- .CE(\cmp_lengthCounter/RSTP_37 ),
- .D(\s_cmp_lengths[9]_9 [9]),
- .Q(\s_datao_fmc2[57] [9]),
- .R(1'b0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[0].gen_outs.cmp_OBUFDS_fmc
- (.I(D[0]),
- .O(\FMC2_LA_P_b[27] [0]),
- .OB(\FMC2_LA_N_b[27] [0]));
- system_design_fasec_hwtest_0_0_pulseMeasure_20 \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure
- (.D(D[0]),
- .Q(\s_datao_fmc2[6] [0]),
- .\axi_araddr_reg[2]_rep__3 (\axi_araddr_reg[2]_rep__3 ),
- .\axi_araddr_reg[3]_rep__3 (\axi_araddr_reg[3]_rep__3 ),
- .\axi_rdata_reg[0] (\axi_rdata_reg[0] ),
- .intr_led_o_reg(\fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_3 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_38 ),
- .s_buff3_reg(\fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .\s_datao_fmc2[5] (\s_datao_fmc2[5] [0]),
- .\s_debounce_reg[1] (s_buff2_i_1__19_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc2[4] [0]),
- .s_pulseLed_reg_1(\s_datao_fmc2[5] [2:1]),
- .\v_outleds_reg[2] (v_outleds[2:0]));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[1].gen_outs.cmp_OBUFDS_fmc
- (.I(D[1]),
- .O(\FMC2_LA_P_b[27] [1]),
- .OB(\FMC2_LA_N_b[27] [1]));
- system_design_fasec_hwtest_0_0_pulseMeasure_21 \fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure
- (.D(D[1]),
- .Q(\s_datao_fmc2[6] [1]),
- .\axi_araddr_reg[2]_rep__3 (\axi_araddr_reg[2]_rep__3 ),
- .\axi_araddr_reg[3]_rep__3 (\axi_araddr_reg[3]_rep__3 ),
- .\axi_rdata_reg[1] (\axi_rdata_reg[1] ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_39 ),
- .s_buff3_reg(\fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .s_count_reg(\s_datao_fmc2[5] [1]),
- .\s_debounce_reg[1] (s_buff2_i_1__20_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc2[4] [1]));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[2].gen_outs.cmp_OBUFDS_fmc
- (.I(D[2]),
- .O(\FMC2_LA_P_b[27] [2]),
- .OB(\FMC2_LA_N_b[27] [2]));
- system_design_fasec_hwtest_0_0_pulseMeasure_22 \fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure
- (.D(D[2]),
- .Q(\s_datao_fmc2[6] [2]),
- .\axi_araddr_reg[2]_rep__3 (\axi_araddr_reg[2]_rep__3 ),
- .\axi_araddr_reg[3]_rep__3 (\axi_araddr_reg[3]_rep__3 ),
- .\axi_rdata_reg[2] (\axi_rdata_reg[2] ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_40 ),
- .s_buff3_reg(\fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .s_count_reg(\s_datao_fmc2[5] [2]),
- .\s_debounce_reg[1] (s_buff2_i_1__21_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc2[4] [2]));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[3].gen_outs.cmp_OBUFDS_fmc
- (.I(D[3]),
- .O(\FMC2_LA_P_b[27] [3]),
- .OB(\FMC2_LA_N_b[27] [3]));
- system_design_fasec_hwtest_0_0_pulseMeasure_23 \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure
- (.D(D[3]),
- .Q(\s_datao_fmc2[6] [3]),
- .\axi_araddr_reg[2]_rep__2 (\axi_araddr_reg[2]_rep__2 ),
- .\axi_araddr_reg[3]_rep__2 (\axi_araddr_reg[3]_rep__2 ),
- .\axi_rdata_reg[3] (\axi_rdata_reg[3] ),
- .intr_led_o_reg(\fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_3 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_41 ),
- .s_buff3_reg(\fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .\s_datao_fmc2[5] (\s_datao_fmc2[5] [3]),
- .\s_debounce_reg[1] (s_buff2_i_1__22_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc2[4] [3]),
- .s_pulseLed_reg_1(\s_datao_fmc2[5] [5:4]),
- .\v_outleds_reg[5] (v_outleds[5:3]));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[4].gen_outs.cmp_OBUFDS_fmc
- (.I(s_diffouts_o[4]),
- .O(\FMC2_LA_P_b[27] [4]),
- .OB(\FMC2_LA_N_b[27] [4]));
- system_design_fasec_hwtest_0_0_pulseMeasure_24 \fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure
- (.D(\s_datao_fmc2[4] [4]),
- .Q(s_diffouts_o[4]),
- .\axi_araddr_reg[2]_rep__2 (\axi_araddr_reg[2]_rep__2 ),
- .\axi_araddr_reg[3]_rep__2 (\axi_araddr_reg[3]_rep__2 ),
- .\axi_rdata_reg[4] (\axi_rdata_reg[4] ),
- .\data_o_reg[6][4] (\s_datao_fmc2[6] [4]),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_42 ),
- .s_buff3_reg(\fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .s_count_reg(\s_datao_fmc2[5] [4]),
- .\s_debounce_reg[1] (s_buff2_i_1__23_n_0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[5].gen_outs.cmp_OBUFDS_fmc
- (.I(s_diffouts_o[5]),
- .O(\FMC2_LA_P_b[27] [5]),
- .OB(\FMC2_LA_N_b[27] [5]));
- system_design_fasec_hwtest_0_0_pulseMeasure_25 \fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure
- (.D(\s_datao_fmc2[4] [5]),
- .Q(s_diffouts_o[5]),
- .\axi_araddr_reg[2]_rep__2 (\axi_araddr_reg[2]_rep__2 ),
- .\axi_araddr_reg[3]_rep__2 (\axi_araddr_reg[3]_rep__2 ),
- .\axi_rdata_reg[5] (\axi_rdata_reg[5] ),
- .\data_o_reg[6][5] (\s_datao_fmc2[6] [5]),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_43 ),
- .s_buff3_reg(\fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .s_count_reg(\s_datao_fmc2[5] [5]),
- .\s_debounce_reg[1] (s_buff2_i_1__24_n_0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[6].gen_outs.cmp_OBUFDS_fmc
- (.I(s_diffouts_o[6]),
- .O(\FMC2_LA_P_b[27] [6]),
- .OB(\FMC2_LA_N_b[27] [6]));
- system_design_fasec_hwtest_0_0_pulseMeasure_26 \fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure
- (.D(\s_datao_fmc2[4] [6]),
- .Q(s_diffouts_o[6]),
- .\axi_araddr_reg[2]_rep__2 (\axi_araddr_reg[2]_rep__2 ),
- .\axi_araddr_reg[3]_rep__2 (\axi_araddr_reg[3]_rep__2 ),
- .\axi_rdata_reg[6] (\axi_rdata_reg[6] ),
- .\data_o_reg[6][6] (\s_datao_fmc2[6] [6]),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_44 ),
- .s_buff3_reg(\fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .\s_datao_fmc2[5] (\s_datao_fmc2[5] [6]),
- .\s_debounce_reg[1] (s_buff2_i_1__25_n_0));
- (* CAPACITANCE = "DONT_CARE" *)
- (* XILINX_LEGACY_PRIM = "OBUFDS" *)
- (* box_type = "PRIMITIVE" *)
- OBUFDS #(
- .IOSTANDARD("DEFAULT"))
- \fmc_03287_obufds[7].gen_outs.cmp_OBUFDS_fmc
- (.I(s_diffouts_o[7]),
- .O(\FMC2_LA_P_b[27] [7]),
- .OB(\FMC2_LA_N_b[27] [7]));
- system_design_fasec_hwtest_0_0_pulseMeasure_27 \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure
- (.D(\s_datao_fmc2[4] [7]),
- .Q(s_diffouts_o[7]),
- .\axi_araddr_reg[2]_rep__2 (\axi_araddr_reg[2]_rep__2 ),
- .\axi_araddr_reg[3]_rep__2 (\axi_araddr_reg[3]_rep__2 ),
- .\axi_rdata_reg[7] (\axi_rdata_reg[7] ),
- .\data_o_reg[6][7] (\s_datao_fmc2[6] [7]),
- .intr_led_o_reg(\fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_3 ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg(\cmp_pulseSync/s_debounce_45 ),
- .s_buff3_reg(\fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .\s_datao_fmc2[5] (\s_datao_fmc2[5] [7]),
- .\s_debounce_reg[1] (s_buff2_i_1__26_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc2[5] [6]),
- .\v_outleds_reg[0] (\fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_3 ),
- .\v_outleds_reg[3] (\fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_3 ),
- .\v_outleds_reg[7] (v_outleds[7:6]));
- system_design_fasec_hwtest_0_0_dac7716_spi \gen_spi.cmp_dac7716_spi
- (.D(spi_sdo_i),
- .Q(Q),
- .\axi_rdata_reg[31] (\axi_rdata_reg[31] ),
- .\dac_ch_o_reg[0][0]_0 (\gen_spi.cmp_dac7716_spi_n_1 ),
- .\dac_ch_o_reg[0][0]_1 (\gen_spi.cmp_dac7716_spi_n_2 ),
- .\data_rw_o_reg[100][11] (\data_rw_o_reg[100][11] ),
- .\data_rw_o_reg[101][11] (\data_rw_o_reg[101][11] ),
- .\data_rw_o_reg[102][11] (\data_rw_o_reg[102][11] ),
- .\data_rw_o_reg[103][11] (\data_rw_o_reg[103][11] ),
- .\data_rw_o_reg[79][2] (\data_rw_o_reg[79][7] [1:0]),
- .\data_rw_o_reg[84][11] (\data_rw_o_reg[84][11] ),
- .\data_rw_o_reg[84][11]_0 (\data_rw_o_reg[84][11]_0 ),
- .\data_rw_o_reg[85][11] (\data_rw_o_reg[85][11] ),
- .\data_rw_o_reg[85][11]_0 (\data_rw_o_reg[85][11]_0 ),
- .\data_rw_o_reg[86][11] (\data_rw_o_reg[86][11] ),
- .\data_rw_o_reg[86][11]_0 (\data_rw_o_reg[86][11]_0 ),
- .\data_rw_o_reg[87][11] (\data_rw_o_reg[87][11] ),
- .\data_rw_o_reg[87][11]_0 (\data_rw_o_reg[87][11]_0 ),
- .\data_rw_o_reg[88][11] (\data_rw_o_reg[88][11] ),
- .\data_rw_o_reg[88][11]_0 (\data_rw_o_reg[88][11]_0 ),
- .\data_rw_o_reg[89][11] (\data_rw_o_reg[89][11] ),
- .\data_rw_o_reg[89][11]_0 (\data_rw_o_reg[89][11]_0 ),
- .\data_rw_o_reg[90][11] (\data_rw_o_reg[90][11] ),
- .\data_rw_o_reg[90][11]_0 (\data_rw_o_reg[90][11]_0 ),
- .\data_rw_o_reg[91][11] (\data_rw_o_reg[91][11] ),
- .\data_rw_o_reg[91][11]_0 (\data_rw_o_reg[91][11]_0 ),
- .\data_rw_o_reg[92][11] (\data_rw_o_reg[92][11] ),
- .\data_rw_o_reg[93][11] (\data_rw_o_reg[93][11] ),
- .\data_rw_o_reg[94][11] (\data_rw_o_reg[94][11] ),
- .\data_rw_o_reg[95][11] (\data_rw_o_reg[95][11] ),
- .\data_rw_o_reg[96][11] (\data_rw_o_reg[96][11] ),
- .\data_rw_o_reg[97][11] (\data_rw_o_reg[97][11] ),
- .\data_rw_o_reg[98][11] (\data_rw_o_reg[98][11] ),
- .\data_rw_o_reg[99][11] (\data_rw_o_reg[99][11] ),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .\s_counter_reg[2] (s_spi_sclk),
- .s_spi_cs_n(s_spi_cs_n),
- .s_spi_mosi(s_spi_mosi),
- .s_start(s_start),
- .s_start_reg_0(s_start_i_1_n_0),
- .\s_tx_data_reg[111]_0 (\s_tx_data_reg[111] ),
- .\s_tx_data_reg[15]_0 (\s_tx_data_reg[15] ),
- .\s_tx_data_reg[15]_1 (\s_tx_data_reg[15]_0 ),
- .\s_tx_data_reg[39]_0 (\s_tx_data_reg[39] ),
- .\s_tx_data_reg[39]_1 (\s_tx_data_reg[39]_0 ),
- .\s_tx_data_reg[39]_2 (\s_tx_data_reg[39]_1 ),
- .\s_tx_data_reg[39]_3 (\s_tx_data_reg[39]_2 ));
- (* box_type = "PRIMITIVE" *)
- IOBUF #(
- .IOSTANDARD("DEFAULT"))
- \gen_spi.cmp_spi_cs_n_iobuf
- (.I(s_spi_cs_n),
- .IO(FMC2_LA_N_b[1]),
- .O(\NLW_gen_spi.cmp_spi_cs_n_iobuf_O_UNCONNECTED ),
- .T(1'b0));
- (* box_type = "PRIMITIVE" *)
- IOBUF #(
- .IOSTANDARD("DEFAULT"))
- \gen_spi.cmp_spi_miso_iobuf
- (.I(1'b0),
- .IO(FMC2_LA_P_b[1]),
- .O(spi_sdo_i),
- .T(1'b1));
- (* box_type = "PRIMITIVE" *)
- IOBUF #(
- .IOSTANDARD("DEFAULT"))
- \gen_spi.cmp_spi_mosi_iobuf
- (.I(s_spi_mosi),
- .IO(FMC2_LA_N_b[0]),
- .O(\NLW_gen_spi.cmp_spi_mosi_iobuf_O_UNCONNECTED ),
- .T(1'b0));
- (* box_type = "PRIMITIVE" *)
- IOBUF #(
- .IOSTANDARD("DEFAULT"))
- \gen_spi.cmp_spi_sclk_iobuf
- (.I(s_spi_sclk),
- .IO(FMC2_LA_P_b[0]),
- .O(\NLW_gen_spi.cmp_spi_sclk_iobuf_O_UNCONNECTED ),
- .T(1'b0));
- FDRE intr_led_o_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure_n_2 ),
- .Q(fmc2_intr_led),
- .R(1'b0));
- FDRE intr_o_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(intr_o0),
- .Q(fmc2_intr),
- .R(1'b0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1
- (.I0(\cmp_pulseSync/s_debounce [1]),
- .I1(\cmp_pulseSync/s_debounce [0]),
- .I2(\cmp_pulseSync/s_debounce [4]),
- .I3(\cmp_pulseSync/s_debounce [3]),
- .I4(\cmp_pulseSync/s_debounce [2]),
- .I5(\s_datao_fmc2[0] [0]),
- .O(s_buff2_i_1_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__0
- (.I0(\cmp_pulseSync/s_debounce_20 [1]),
- .I1(\cmp_pulseSync/s_debounce_20 [0]),
- .I2(\cmp_pulseSync/s_debounce_20 [4]),
- .I3(\cmp_pulseSync/s_debounce_20 [3]),
- .I4(\cmp_pulseSync/s_debounce_20 [2]),
- .I5(\s_datao_fmc2[0] [1]),
- .O(s_buff2_i_1__0_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__1
- (.I0(\cmp_pulseSync/s_debounce_22 [1]),
- .I1(\cmp_pulseSync/s_debounce_22 [0]),
- .I2(\cmp_pulseSync/s_debounce_22 [4]),
- .I3(\cmp_pulseSync/s_debounce_22 [3]),
- .I4(\cmp_pulseSync/s_debounce_22 [2]),
- .I5(\s_datao_fmc2[0] [2]),
- .O(s_buff2_i_1__1_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__10
- (.I0(\cmp_pulseSync/s_debounce_2 [1]),
- .I1(\cmp_pulseSync/s_debounce_2 [0]),
- .I2(\cmp_pulseSync/s_debounce_2 [4]),
- .I3(\cmp_pulseSync/s_debounce_2 [3]),
- .I4(\cmp_pulseSync/s_debounce_2 [2]),
- .I5(\s_datao_fmc2[0] [11]),
- .O(s_buff2_i_1__10_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__11
- (.I0(\cmp_pulseSync/s_debounce_4 [1]),
- .I1(\cmp_pulseSync/s_debounce_4 [0]),
- .I2(\cmp_pulseSync/s_debounce_4 [4]),
- .I3(\cmp_pulseSync/s_debounce_4 [3]),
- .I4(\cmp_pulseSync/s_debounce_4 [2]),
- .I5(\s_datao_fmc2[0] [12]),
- .O(s_buff2_i_1__11_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__12
- (.I0(\cmp_pulseSync/s_debounce_6 [1]),
- .I1(\cmp_pulseSync/s_debounce_6 [0]),
- .I2(\cmp_pulseSync/s_debounce_6 [4]),
- .I3(\cmp_pulseSync/s_debounce_6 [3]),
- .I4(\cmp_pulseSync/s_debounce_6 [2]),
- .I5(\s_datao_fmc2[0] [13]),
- .O(s_buff2_i_1__12_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__13
- (.I0(\cmp_pulseSync/s_debounce_8 [1]),
- .I1(\cmp_pulseSync/s_debounce_8 [0]),
- .I2(\cmp_pulseSync/s_debounce_8 [4]),
- .I3(\cmp_pulseSync/s_debounce_8 [3]),
- .I4(\cmp_pulseSync/s_debounce_8 [2]),
- .I5(\s_datao_fmc2[0] [14]),
- .O(s_buff2_i_1__13_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__14
- (.I0(\cmp_pulseSync/s_debounce_10 [1]),
- .I1(\cmp_pulseSync/s_debounce_10 [0]),
- .I2(\cmp_pulseSync/s_debounce_10 [4]),
- .I3(\cmp_pulseSync/s_debounce_10 [3]),
- .I4(\cmp_pulseSync/s_debounce_10 [2]),
- .I5(\s_datao_fmc2[0] [15]),
- .O(s_buff2_i_1__14_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__15
- (.I0(\cmp_pulseSync/s_debounce_12 [1]),
- .I1(\cmp_pulseSync/s_debounce_12 [0]),
- .I2(\cmp_pulseSync/s_debounce_12 [4]),
- .I3(\cmp_pulseSync/s_debounce_12 [3]),
- .I4(\cmp_pulseSync/s_debounce_12 [2]),
- .I5(\s_datao_fmc2[0] [16]),
- .O(s_buff2_i_1__15_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__16
- (.I0(\cmp_pulseSync/s_debounce_14 [1]),
- .I1(\cmp_pulseSync/s_debounce_14 [0]),
- .I2(\cmp_pulseSync/s_debounce_14 [4]),
- .I3(\cmp_pulseSync/s_debounce_14 [3]),
- .I4(\cmp_pulseSync/s_debounce_14 [2]),
- .I5(\s_datao_fmc2[0] [17]),
- .O(s_buff2_i_1__16_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__17
- (.I0(\cmp_pulseSync/s_debounce_16 [1]),
- .I1(\cmp_pulseSync/s_debounce_16 [0]),
- .I2(\cmp_pulseSync/s_debounce_16 [4]),
- .I3(\cmp_pulseSync/s_debounce_16 [3]),
- .I4(\cmp_pulseSync/s_debounce_16 [2]),
- .I5(\s_datao_fmc2[0] [18]),
- .O(s_buff2_i_1__17_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__18
- (.I0(\cmp_pulseSync/s_debounce_18 [1]),
- .I1(\cmp_pulseSync/s_debounce_18 [0]),
- .I2(\cmp_pulseSync/s_debounce_18 [4]),
- .I3(\cmp_pulseSync/s_debounce_18 [3]),
- .I4(\cmp_pulseSync/s_debounce_18 [2]),
- .I5(\s_datao_fmc2[0] [19]),
- .O(s_buff2_i_1__18_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__19
- (.I0(\cmp_pulseSync/s_debounce_38 [1]),
- .I1(\cmp_pulseSync/s_debounce_38 [0]),
- .I2(\cmp_pulseSync/s_debounce_38 [4]),
- .I3(\cmp_pulseSync/s_debounce_38 [3]),
- .I4(\cmp_pulseSync/s_debounce_38 [2]),
- .I5(\fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__19_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__2
- (.I0(\cmp_pulseSync/s_debounce_24 [1]),
- .I1(\cmp_pulseSync/s_debounce_24 [0]),
- .I2(\cmp_pulseSync/s_debounce_24 [4]),
- .I3(\cmp_pulseSync/s_debounce_24 [3]),
- .I4(\cmp_pulseSync/s_debounce_24 [2]),
- .I5(\s_datao_fmc2[0] [3]),
- .O(s_buff2_i_1__2_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__20
- (.I0(\cmp_pulseSync/s_debounce_39 [1]),
- .I1(\cmp_pulseSync/s_debounce_39 [0]),
- .I2(\cmp_pulseSync/s_debounce_39 [4]),
- .I3(\cmp_pulseSync/s_debounce_39 [3]),
- .I4(\cmp_pulseSync/s_debounce_39 [2]),
- .I5(\fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__20_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__21
- (.I0(\cmp_pulseSync/s_debounce_40 [1]),
- .I1(\cmp_pulseSync/s_debounce_40 [0]),
- .I2(\cmp_pulseSync/s_debounce_40 [4]),
- .I3(\cmp_pulseSync/s_debounce_40 [3]),
- .I4(\cmp_pulseSync/s_debounce_40 [2]),
- .I5(\fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__21_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__22
- (.I0(\cmp_pulseSync/s_debounce_41 [1]),
- .I1(\cmp_pulseSync/s_debounce_41 [0]),
- .I2(\cmp_pulseSync/s_debounce_41 [4]),
- .I3(\cmp_pulseSync/s_debounce_41 [3]),
- .I4(\cmp_pulseSync/s_debounce_41 [2]),
- .I5(\fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__22_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__23
- (.I0(\cmp_pulseSync/s_debounce_42 [1]),
- .I1(\cmp_pulseSync/s_debounce_42 [0]),
- .I2(\cmp_pulseSync/s_debounce_42 [4]),
- .I3(\cmp_pulseSync/s_debounce_42 [3]),
- .I4(\cmp_pulseSync/s_debounce_42 [2]),
- .I5(\fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__23_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__24
- (.I0(\cmp_pulseSync/s_debounce_43 [1]),
- .I1(\cmp_pulseSync/s_debounce_43 [0]),
- .I2(\cmp_pulseSync/s_debounce_43 [4]),
- .I3(\cmp_pulseSync/s_debounce_43 [3]),
- .I4(\cmp_pulseSync/s_debounce_43 [2]),
- .I5(\fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__24_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__25
- (.I0(\cmp_pulseSync/s_debounce_44 [1]),
- .I1(\cmp_pulseSync/s_debounce_44 [0]),
- .I2(\cmp_pulseSync/s_debounce_44 [4]),
- .I3(\cmp_pulseSync/s_debounce_44 [3]),
- .I4(\cmp_pulseSync/s_debounce_44 [2]),
- .I5(\fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__25_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__26
- (.I0(\cmp_pulseSync/s_debounce_45 [1]),
- .I1(\cmp_pulseSync/s_debounce_45 [0]),
- .I2(\cmp_pulseSync/s_debounce_45 [4]),
- .I3(\cmp_pulseSync/s_debounce_45 [3]),
- .I4(\cmp_pulseSync/s_debounce_45 [2]),
- .I5(\fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_1 ),
- .O(s_buff2_i_1__26_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__3
- (.I0(\cmp_pulseSync/s_debounce_26 [1]),
- .I1(\cmp_pulseSync/s_debounce_26 [0]),
- .I2(\cmp_pulseSync/s_debounce_26 [4]),
- .I3(\cmp_pulseSync/s_debounce_26 [3]),
- .I4(\cmp_pulseSync/s_debounce_26 [2]),
- .I5(\s_datao_fmc2[0] [4]),
- .O(s_buff2_i_1__3_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__4
- (.I0(\cmp_pulseSync/s_debounce_28 [1]),
- .I1(\cmp_pulseSync/s_debounce_28 [0]),
- .I2(\cmp_pulseSync/s_debounce_28 [4]),
- .I3(\cmp_pulseSync/s_debounce_28 [3]),
- .I4(\cmp_pulseSync/s_debounce_28 [2]),
- .I5(\s_datao_fmc2[0] [5]),
- .O(s_buff2_i_1__4_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__5
- (.I0(\cmp_pulseSync/s_debounce_30 [1]),
- .I1(\cmp_pulseSync/s_debounce_30 [0]),
- .I2(\cmp_pulseSync/s_debounce_30 [4]),
- .I3(\cmp_pulseSync/s_debounce_30 [3]),
- .I4(\cmp_pulseSync/s_debounce_30 [2]),
- .I5(\s_datao_fmc2[0] [6]),
- .O(s_buff2_i_1__5_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__6
- (.I0(\cmp_pulseSync/s_debounce_32 [1]),
- .I1(\cmp_pulseSync/s_debounce_32 [0]),
- .I2(\cmp_pulseSync/s_debounce_32 [4]),
- .I3(\cmp_pulseSync/s_debounce_32 [3]),
- .I4(\cmp_pulseSync/s_debounce_32 [2]),
- .I5(\s_datao_fmc2[0] [7]),
- .O(s_buff2_i_1__6_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__7
- (.I0(\cmp_pulseSync/s_debounce_34 [1]),
- .I1(\cmp_pulseSync/s_debounce_34 [0]),
- .I2(\cmp_pulseSync/s_debounce_34 [4]),
- .I3(\cmp_pulseSync/s_debounce_34 [3]),
- .I4(\cmp_pulseSync/s_debounce_34 [2]),
- .I5(\s_datao_fmc2[0] [8]),
- .O(s_buff2_i_1__7_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__8
- (.I0(\cmp_pulseSync/s_debounce_36 [1]),
- .I1(\cmp_pulseSync/s_debounce_36 [0]),
- .I2(\cmp_pulseSync/s_debounce_36 [4]),
- .I3(\cmp_pulseSync/s_debounce_36 [3]),
- .I4(\cmp_pulseSync/s_debounce_36 [2]),
- .I5(\s_datao_fmc2[0] [9]),
- .O(s_buff2_i_1__8_n_0));
- LUT6 #(
- .INIT(64'hFFFFFFFE80000000))
- s_buff2_i_1__9
- (.I0(\cmp_pulseSync/s_debounce_0 [1]),
- .I1(\cmp_pulseSync/s_debounce_0 [0]),
- .I2(\cmp_pulseSync/s_debounce_0 [4]),
- .I3(\cmp_pulseSync/s_debounce_0 [3]),
- .I4(\cmp_pulseSync/s_debounce_0 [2]),
- .I5(\s_datao_fmc2[0] [10]),
- .O(s_buff2_i_1__9_n_0));
- FDRE \s_diffouts_o_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_dout[4]),
- .Q(s_diffouts_o[4]),
- .R(1'b0));
- FDRE \s_diffouts_o_reg[5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_dout[5]),
- .Q(s_diffouts_o[5]),
- .R(1'b0));
- FDRE \s_diffouts_o_reg[6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_dout[6]),
- .Q(s_diffouts_o[6]),
- .R(1'b0));
- FDRE \s_diffouts_o_reg[7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(v_dout[7]),
- .Q(s_diffouts_o[7]),
- .R(1'b0));
- LUT3 #(
- .INIT(8'hB8))
- s_start_i_1
- (.I0(s_start),
- .I1(\gen_spi.cmp_dac7716_spi_n_2 ),
- .I2(\gen_spi.cmp_dac7716_spi_n_1 ),
- .O(s_start_i_1_n_0));
- FDRE \v_cmp_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [0]),
- .Q(v_cmp[0]),
- .R(1'b0));
- FDRE \v_cmp_reg[10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [10]),
- .Q(v_cmp[10]),
- .R(1'b0));
- FDRE \v_cmp_reg[11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [11]),
- .Q(v_cmp[11]),
- .R(1'b0));
- FDRE \v_cmp_reg[12]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [12]),
- .Q(v_cmp[12]),
- .R(1'b0));
- FDRE \v_cmp_reg[13]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [13]),
- .Q(v_cmp[13]),
- .R(1'b0));
- FDRE \v_cmp_reg[14]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [14]),
- .Q(v_cmp[14]),
- .R(1'b0));
- FDRE \v_cmp_reg[15]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [15]),
- .Q(v_cmp[15]),
- .R(1'b0));
- FDRE \v_cmp_reg[16]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [16]),
- .Q(v_cmp[16]),
- .R(1'b0));
- FDRE \v_cmp_reg[17]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [17]),
- .Q(v_cmp[17]),
- .R(1'b0));
- FDRE \v_cmp_reg[18]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [18]),
- .Q(v_cmp[18]),
- .R(1'b0));
- FDRE \v_cmp_reg[19]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [19]),
- .Q(v_cmp[19]),
- .R(1'b0));
- FDRE \v_cmp_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [1]),
- .Q(v_cmp[1]),
- .R(1'b0));
- FDRE \v_cmp_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [2]),
- .Q(v_cmp[2]),
- .R(1'b0));
- FDRE \v_cmp_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [3]),
- .Q(v_cmp[3]),
- .R(1'b0));
- FDRE \v_cmp_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [4]),
- .Q(v_cmp[4]),
- .R(1'b0));
- FDRE \v_cmp_reg[5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [5]),
- .Q(v_cmp[5]),
- .R(1'b0));
- FDRE \v_cmp_reg[6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [6]),
- .Q(v_cmp[6]),
- .R(1'b0));
- FDRE \v_cmp_reg[7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [7]),
- .Q(v_cmp[7]),
- .R(1'b0));
- FDRE \v_cmp_reg[8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [8]),
- .Q(v_cmp[8]),
- .R(1'b0));
- FDRE \v_cmp_reg[9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[0] [9]),
- .Q(v_cmp[9]),
- .R(1'b0));
- FDRE \v_cmpled_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[4] [0]),
- .Q(v_cmpled[0]),
- .R(1'b0));
- FDRE \v_cmpled_reg[10]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[2]),
- .Q(v_cmpled[10]),
- .R(1'b0));
- FDRE \v_cmpled_reg[11]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[3]),
- .Q(v_cmpled[11]),
- .R(1'b0));
- FDRE \v_cmpled_reg[12]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[4]),
- .Q(v_cmpled[12]),
- .R(1'b0));
- FDRE \v_cmpled_reg[13]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[5]),
- .Q(v_cmpled[13]),
- .R(1'b0));
- FDRE \v_cmpled_reg[14]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[6]),
- .Q(v_cmpled[14]),
- .R(1'b0));
- FDRE \v_cmpled_reg[15]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[7]),
- .Q(v_cmpled[15]),
- .R(1'b0));
- FDRE \v_cmpled_reg[16]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[8]),
- .Q(v_cmpled[16]),
- .R(1'b0));
- FDRE \v_cmpled_reg[17]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[9]),
- .Q(v_cmpled[17]),
- .R(1'b0));
- FDRE \v_cmpled_reg[18]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[10]),
- .Q(v_cmpled[18]),
- .R(1'b0));
- FDRE \v_cmpled_reg[19]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[11]),
- .Q(v_cmpled[19]),
- .R(1'b0));
- FDRE \v_cmpled_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[4] [1]),
- .Q(v_cmpled[1]),
- .R(1'b0));
- FDRE \v_cmpled_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[4] [2]),
- .Q(v_cmpled[2]),
- .R(1'b0));
- FDRE \v_cmpled_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[4] [3]),
- .Q(v_cmpled[3]),
- .R(1'b0));
- FDRE \v_cmpled_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[4] [4]),
- .Q(v_cmpled[4]),
- .R(1'b0));
- FDRE \v_cmpled_reg[5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[4] [5]),
- .Q(v_cmpled[5]),
- .R(1'b0));
- FDRE \v_cmpled_reg[6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[4] [6]),
- .Q(v_cmpled[6]),
- .R(1'b0));
- FDRE \v_cmpled_reg[7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[4] [7]),
- .Q(v_cmpled[7]),
- .R(1'b0));
- FDRE \v_cmpled_reg[8]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[0]),
- .Q(v_cmpled[8]),
- .R(1'b0));
- FDRE \v_cmpled_reg[9]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(s_count_reg[1]),
- .Q(v_cmpled[9]),
- .R(1'b0));
- FDSE \v_dout_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[78][4] ),
- .Q(v_dout[4]),
- .S(\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2 ));
- FDSE \v_dout_reg[5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[78][5] ),
- .Q(v_dout[5]),
- .S(\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2 ));
- FDSE \v_dout_reg[6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[78][6] ),
- .Q(v_dout[6]),
- .S(\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2 ));
- FDSE \v_dout_reg[7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\data_rw_o_reg[78][7] ),
- .Q(v_dout[7]),
- .S(\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2 ));
- FDRE \v_fbd_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\FMC2_LA_N_b[32] [21]),
- .Q(v_fbd[0]),
- .R(1'b0));
- FDRE \v_fbd_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\FMC2_LA_P_b[32] [21]),
- .Q(v_fbd[1]),
- .R(1'b0));
- FDRE \v_fbd_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\FMC2_LA_N_b[32] [20]),
- .Q(v_fbd[2]),
- .R(1'b0));
- FDRE \v_fbd_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\FMC2_LA_P_b[32] [20]),
- .Q(v_fbd[3]),
- .R(1'b0));
- FDRE \v_outleds_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[5] [0]),
- .Q(v_outleds[0]),
- .R(1'b0));
- FDRE \v_outleds_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[5] [1]),
- .Q(v_outleds[1]),
- .R(1'b0));
- FDRE \v_outleds_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[5] [2]),
- .Q(v_outleds[2]),
- .R(1'b0));
- FDRE \v_outleds_reg[3]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[5] [3]),
- .Q(v_outleds[3]),
- .R(1'b0));
- FDRE \v_outleds_reg[4]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[5] [4]),
- .Q(v_outleds[4]),
- .R(1'b0));
- FDRE \v_outleds_reg[5]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[5] [5]),
- .Q(v_outleds[5]),
- .R(1'b0));
- FDRE \v_outleds_reg[6]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[5] [6]),
- .Q(v_outleds[6]),
- .R(1'b0));
- FDRE \v_outleds_reg[7]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_datao_fmc2[5] [7]),
- .Q(v_outleds[7]),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure
- (\s_datao_fmc2[4] ,
- D,
- \v_dout_reg[7] ,
- S,
- intr_o_reg,
- E,
- s_buff2_reg,
- \fmc_03287_channels[0].gen_chs.data_o_reg[48][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_0,
- \data_rw_o_reg[79][7] ,
- Q,
- s_pulseLed_reg_0,
- \v_cmp_reg[2] ,
- s_buff2_reg_0,
- s00_axi_aresetn);
- output [0:0]\s_datao_fmc2[4] ;
- output [0:0]D;
- output \v_dout_reg[7] ;
- output [0:0]S;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output [4:0]s_buff2_reg;
- output [23:0]\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_0;
- input [0:0]\data_rw_o_reg[79][7] ;
- input [2:0]Q;
- input [1:0]s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[2] ;
- input [1:0]s_buff2_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [2:0]Q;
- wire [0:0]S;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_5;
- wire [0:0]\data_rw_o_reg[79][7] ;
- wire [23:0]\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] ;
- wire [0:0]intr_o_reg;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire [1:0]s_buff2_reg_0;
- wire s_comparators_i_0;
- wire [0:0]\s_datao_fmc2[4] ;
- wire \s_debounce_reg[1] ;
- wire [1:0]s_pulseLed_reg_0;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
- wire [2:0]\v_cmp_reg[2] ;
- wire \v_dout_reg[7] ;
-
- system_design_fasec_hwtest_0_0_counterUpDown_98 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_99 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_5),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc2[4] ));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_100 cmp_pulseSync
- (.E(E),
- .\data_rw_o_reg[79][7] (\data_rw_o_reg[79][7] ),
- .intr_o_reg(intr_o_reg),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff2_reg_1(s_buff2_reg_0),
- .s_buff3_reg_0(D),
- .s_comparators_i_0(s_comparators_i_0),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_5),
- .s_pulseLed_reg_0(\s_datao_fmc2[4] ),
- .\v_cmp_reg[2] (\v_cmp_reg[2] ),
- .\v_dout_reg[7] (\v_dout_reg[7] ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_led_o_i_13__0
- (.I0(Q[0]),
- .I1(\s_datao_fmc2[4] ),
- .I2(s_pulseLed_reg_0[1]),
- .I3(Q[2]),
- .I4(s_pulseLed_reg_0[0]),
- .I5(Q[1]),
- .O(S));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(\s_datao_fmc2[4] ));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_1
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[10].gen_chs.data_o_reg[58][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_10,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_10;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_10;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_95 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_96 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_97 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_10(s_comparators_i_10),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_10
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_19,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_19;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_19;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_68 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_69 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_70 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_19(s_comparators_i_19),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_101
- (\s_datao_fmc1[4] ,
- D,
- \v_dout_reg[7] ,
- S,
- intr_o_reg,
- E,
- s_buff2_reg,
- \fmc_03287_channels[0].gen_chs.data_o_reg[48][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_0,
- \data_rw_o_reg[11][7] ,
- Q,
- s_pulseLed_reg_0,
- \v_cmp_reg[2] ,
- s_buff2_reg_0,
- s00_axi_aresetn);
- output [0:0]\s_datao_fmc1[4] ;
- output [0:0]D;
- output \v_dout_reg[7] ;
- output [0:0]S;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output [4:0]s_buff2_reg;
- output [23:0]\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_0;
- input [0:0]\data_rw_o_reg[11][7] ;
- input [2:0]Q;
- input [1:0]s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[2] ;
- input [1:0]s_buff2_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [2:0]Q;
- wire [0:0]S;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_5;
- wire [0:0]\data_rw_o_reg[11][7] ;
- wire [23:0]\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] ;
- wire [0:0]intr_o_reg;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire [1:0]s_buff2_reg_0;
- wire s_comparators_i_0;
- wire [0:0]\s_datao_fmc1[4] ;
- wire \s_debounce_reg[1] ;
- wire [1:0]s_pulseLed_reg_0;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
- wire [2:0]\v_cmp_reg[2] ;
- wire \v_dout_reg[7] ;
-
- system_design_fasec_hwtest_0_0_counterUpDown_204 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_205 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_5),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc1[4] ));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_206 cmp_pulseSync
- (.E(E),
- .SR(SR),
- .\data_rw_o_reg[11][7] (\data_rw_o_reg[11][7] ),
- .intr_o_reg(intr_o_reg),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff2_reg_1(s_buff2_reg_0),
- .s_buff3_reg_0(D),
- .s_comparators_i_0(s_comparators_i_0),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_5),
- .s_pulseLed_reg_0(\s_datao_fmc1[4] ),
- .\v_cmp_reg[2] (\v_cmp_reg[2] ),
- .\v_dout_reg[7] (\v_dout_reg[7] ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_led_o_i_13
- (.I0(Q[0]),
- .I1(\s_datao_fmc1[4] ),
- .I2(s_pulseLed_reg_0[1]),
- .I3(Q[2]),
- .I4(s_pulseLed_reg_0[0]),
- .I5(Q[1]),
- .O(S));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(\s_datao_fmc1[4] ));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[0].gen_chs.data_o_reg[48][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_102
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[10].gen_chs.data_o_reg[58][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_10,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_10;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_10;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_201 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_202 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_203 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_10(s_comparators_i_10),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[10].gen_chs.data_o_reg[58][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_103
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_11,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_11;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_11;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_198 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_199 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_200 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_11(s_comparators_i_11),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_104
- (D,
- s_buff3_reg,
- S,
- intr_o_reg,
- E,
- s_buff2_reg,
- \fmc_03287_channels[12].gen_chs.data_o_reg[60][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_12,
- Q,
- s_pulseLed_reg_0,
- \v_cmp_reg[14] ,
- s_buff2_reg_0,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]S;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output [4:0]s_buff2_reg;
- output [23:0]\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_12;
- input [2:0]Q;
- input [1:0]s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[14] ;
- input [1:0]s_buff2_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [2:0]Q;
- wire [0:0]S;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_4;
- wire [23:0]\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] ;
- wire [0:0]intr_o_reg;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire [1:0]s_buff2_reg_0;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_12;
- wire \s_debounce_reg[1] ;
- wire [1:0]s_pulseLed_reg_0;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
- wire [2:0]\v_cmp_reg[14] ;
-
- system_design_fasec_hwtest_0_0_counterUpDown_195 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_196 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_197 cmp_pulseSync
- (.E(E),
- .SR(SR),
- .intr_o_reg(intr_o_reg),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff2_reg_1(s_buff2_reg_0),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_12(s_comparators_i_12),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg_0(D),
- .\v_cmp_reg[14] (\v_cmp_reg[14] ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_led_o_i_7
- (.I0(Q[0]),
- .I1(D),
- .I2(s_pulseLed_reg_0[1]),
- .I3(Q[2]),
- .I4(s_pulseLed_reg_0[0]),
- .I5(Q[1]),
- .O(S));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_105
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[13].gen_chs.data_o_reg[61][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_13,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_13;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_13;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_192 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_193 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_194 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_13(s_comparators_i_13),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_106
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[14].gen_chs.data_o_reg[62][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_14,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_14;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_14;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_189 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_190 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_191 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_14(s_comparators_i_14),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_107
- (D,
- s_buff3_reg,
- S,
- intr_o_reg,
- E,
- s_buff2_reg,
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_15,
- Q,
- s_pulseLed_reg_0,
- \v_cmp_reg[17] ,
- s_buff2_reg_0,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]S;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output [4:0]s_buff2_reg;
- output [23:0]\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_15;
- input [2:0]Q;
- input [1:0]s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[17] ;
- input [1:0]s_buff2_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [2:0]Q;
- wire [0:0]S;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_4;
- wire [23:0]\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] ;
- wire [0:0]intr_o_reg;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire [1:0]s_buff2_reg_0;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_15;
- wire \s_debounce_reg[1] ;
- wire [1:0]s_pulseLed_reg_0;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
- wire [2:0]\v_cmp_reg[17] ;
-
- system_design_fasec_hwtest_0_0_counterUpDown_186 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_187 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_188 cmp_pulseSync
- (.E(E),
- .SR(SR),
- .intr_o_reg(intr_o_reg),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff2_reg_1(s_buff2_reg_0),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_15(s_comparators_i_15),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg_0(D),
- .\v_cmp_reg[17] (\v_cmp_reg[17] ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_led_o_i_6
- (.I0(Q[0]),
- .I1(D),
- .I2(s_pulseLed_reg_0[1]),
- .I3(Q[2]),
- .I4(s_pulseLed_reg_0[0]),
- .I5(Q[1]),
- .O(S));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_108
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[16].gen_chs.data_o_reg[64][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_16,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_16;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_16;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_183 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_184 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_185 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_16(s_comparators_i_16),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_109
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[17].gen_chs.data_o_reg[65][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_17,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_17;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_17;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_180 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_181 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_182 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_17(s_comparators_i_17),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_11
- (s_count_reg,
- D,
- E,
- Q,
- \fmc_03287_channels[1].gen_chs.data_o_reg[49][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_1,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output [0:0]D;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_1;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_comparators_i_1;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_65 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_66 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_67 cmp_pulseSync
- (.E(E),
- .Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(D),
- .s_comparators_i_1(s_comparators_i_1),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_110
- (D,
- s_buff3_reg,
- S,
- intr_o_reg,
- E,
- s_buff2_reg,
- \fmc_03287_channels[18].gen_chs.data_o_reg[66][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_18,
- Q,
- s_pulseLed_reg_0,
- \v_cmp_reg[19] ,
- s_buff2_reg_0,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]S;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output [4:0]s_buff2_reg;
- output [23:0]\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_18;
- input [1:0]Q;
- input [0:0]s_pulseLed_reg_0;
- input [1:0]\v_cmp_reg[19] ;
- input [0:0]s_buff2_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [1:0]Q;
- wire [0:0]S;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_4;
- wire [23:0]\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] ;
- wire [0:0]intr_o_reg;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire [0:0]s_buff2_reg_0;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_18;
- wire \s_debounce_reg[1] ;
- wire [0:0]s_pulseLed_reg_0;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
- wire [1:0]\v_cmp_reg[19] ;
-
- system_design_fasec_hwtest_0_0_counterUpDown_177 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_178 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_179 cmp_pulseSync
- (.E(E),
- .SR(SR),
- .intr_o_reg(intr_o_reg),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff2_reg_1(s_buff2_reg_0),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_18(s_comparators_i_18),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg_0(D),
- .\v_cmp_reg[19] (\v_cmp_reg[19] ));
- LUT4 #(
- .INIT(16'h9009))
- intr_led_o_i_5
- (.I0(Q[0]),
- .I1(D),
- .I2(Q[1]),
- .I3(s_pulseLed_reg_0),
- .O(S));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_111
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_19,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_19;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_19;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_174 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_175 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_176 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_19(s_comparators_i_19),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[19].gen_chs.data_o_reg[67][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_112
- (s_count_reg,
- D,
- E,
- Q,
- \fmc_03287_channels[1].gen_chs.data_o_reg[49][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_1,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output [0:0]D;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_1;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_comparators_i_1;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_171 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_172 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_173 cmp_pulseSync
- (.E(E),
- .Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(D),
- .s_comparators_i_1(s_comparators_i_1),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[1].gen_chs.data_o_reg[49][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_113
- (s_count_reg,
- D,
- E,
- Q,
- \fmc_03287_channels[2].gen_chs.data_o_reg[50][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_2,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output [0:0]D;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_2;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_comparators_i_2;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_168 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_169 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_170 cmp_pulseSync
- (.E(E),
- .Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(D),
- .s_comparators_i_2(s_comparators_i_2),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_114
- (\s_datao_fmc1[4] ,
- D,
- S,
- intr_o_reg,
- E,
- s_buff2_reg,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_3,
- Q,
- s_pulseLed_reg_0,
- \v_cmp_reg[5] ,
- s_buff2_reg_0,
- s00_axi_aresetn);
- output [0:0]\s_datao_fmc1[4] ;
- output [0:0]D;
- output [0:0]S;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output [4:0]s_buff2_reg;
- output [23:0]\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_3;
- input [2:0]Q;
- input [1:0]s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[5] ;
- input [1:0]s_buff2_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [2:0]Q;
- wire [0:0]S;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_4;
- wire [23:0]\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] ;
- wire [0:0]intr_o_reg;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire [1:0]s_buff2_reg_0;
- wire s_comparators_i_3;
- wire [0:0]\s_datao_fmc1[4] ;
- wire \s_debounce_reg[1] ;
- wire [1:0]s_pulseLed_reg_0;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
- wire [2:0]\v_cmp_reg[5] ;
-
- system_design_fasec_hwtest_0_0_counterUpDown_165 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_166 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc1[4] ));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_167 cmp_pulseSync
- (.E(E),
- .SR(SR),
- .intr_o_reg(intr_o_reg),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff2_reg_1(s_buff2_reg_0),
- .s_buff3_reg_0(D),
- .s_comparators_i_3(s_comparators_i_3),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg_0(\s_datao_fmc1[4] ),
- .\v_cmp_reg[5] (\v_cmp_reg[5] ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_led_o_i_12
- (.I0(Q[0]),
- .I1(\s_datao_fmc1[4] ),
- .I2(s_pulseLed_reg_0[1]),
- .I3(Q[2]),
- .I4(s_pulseLed_reg_0[0]),
- .I5(Q[1]),
- .O(S));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(\s_datao_fmc1[4] ));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_115
- (s_count_reg,
- D,
- E,
- Q,
- \fmc_03287_channels[4].gen_chs.data_o_reg[52][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_4,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output [0:0]D;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_4;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_comparators_i_4;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_162 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_163 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_164 cmp_pulseSync
- (.E(E),
- .Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(D),
- .s_comparators_i_4(s_comparators_i_4),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_116
- (s_count_reg,
- D,
- E,
- Q,
- \fmc_03287_channels[5].gen_chs.data_o_reg[53][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_5,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output [0:0]D;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_5;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_comparators_i_5;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_159 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_160 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_161 cmp_pulseSync
- (.E(E),
- .Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(D),
- .s_comparators_i_5(s_comparators_i_5),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_117
- (\s_datao_fmc1[4] ,
- D,
- S,
- intr_o_reg,
- E,
- s_buff2_reg,
- \fmc_03287_channels[6].gen_chs.data_o_reg[54][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_6,
- Q,
- s_pulseLed_reg_0,
- \v_cmp_reg[8] ,
- s_buff2_reg_0,
- s00_axi_aresetn);
- output [0:0]\s_datao_fmc1[4] ;
- output [0:0]D;
- output [0:0]S;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output [4:0]s_buff2_reg;
- output [23:0]\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_6;
- input [2:0]Q;
- input [1:0]s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[8] ;
- input [1:0]s_buff2_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [2:0]Q;
- wire [0:0]S;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_4;
- wire [23:0]\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] ;
- wire [0:0]intr_o_reg;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire [1:0]s_buff2_reg_0;
- wire s_comparators_i_6;
- wire [0:0]\s_datao_fmc1[4] ;
- wire \s_debounce_reg[1] ;
- wire [1:0]s_pulseLed_reg_0;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
- wire [2:0]\v_cmp_reg[8] ;
-
- system_design_fasec_hwtest_0_0_counterUpDown_156 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_157 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc1[4] ));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_158 cmp_pulseSync
- (.E(E),
- .SR(SR),
- .intr_o_reg(intr_o_reg),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff2_reg_1(s_buff2_reg_0),
- .s_buff3_reg_0(D),
- .s_comparators_i_6(s_comparators_i_6),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg_0(\s_datao_fmc1[4] ),
- .\v_cmp_reg[8] (\v_cmp_reg[8] ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_led_o_i_11
- (.I0(Q[0]),
- .I1(\s_datao_fmc1[4] ),
- .I2(s_pulseLed_reg_0[1]),
- .I3(Q[2]),
- .I4(s_pulseLed_reg_0[0]),
- .I5(Q[1]),
- .O(S));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(\s_datao_fmc1[4] ));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_118
- (s_count_reg,
- D,
- E,
- Q,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_7,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output [0:0]D;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_7;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_comparators_i_7;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_153 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_154 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_155 cmp_pulseSync
- (.E(E),
- .Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(D),
- .s_comparators_i_7(s_comparators_i_7),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_119
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[8].gen_chs.data_o_reg[56][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_8,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_8;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_8;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_150 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_151 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_152 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_8(s_comparators_i_8),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_12
- (s_count_reg,
- D,
- E,
- Q,
- \fmc_03287_channels[2].gen_chs.data_o_reg[50][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_2,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output [0:0]D;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_2;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_comparators_i_2;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_62 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_63 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_64 cmp_pulseSync
- (.E(E),
- .Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(D),
- .s_comparators_i_2(s_comparators_i_2),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[2].gen_chs.data_o_reg[50][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_120
- (D,
- s_buff3_reg,
- intr_led_o_reg,
- CO,
- E,
- s_buff2_reg,
- \fmc_03287_channels[9].gen_chs.data_o_reg[57][23] ,
- s00_axi_aclk,
- SR,
- \s_debounce_reg[1] ,
- s_comparators_i_9,
- s_pulseLed_reg_0,
- Q,
- s_pulseLed_reg_1,
- S,
- \v_cmpled_reg[18] ,
- \v_cmp_reg[6] ,
- \v_cmp_reg[18] ,
- \v_cmp_reg[11] ,
- s_buff2_reg_0,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output intr_led_o_reg;
- output [0:0]CO;
- output [0:0]E;
- output [4:0]s_buff2_reg;
- output [23:0]\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] ;
- input s00_axi_aclk;
- input [0:0]SR;
- input \s_debounce_reg[1] ;
- input s_comparators_i_9;
- input s_pulseLed_reg_0;
- input [2:0]Q;
- input [1:0]s_pulseLed_reg_1;
- input [2:0]S;
- input [2:0]\v_cmpled_reg[18] ;
- input [2:0]\v_cmp_reg[6] ;
- input [2:0]\v_cmp_reg[18] ;
- input [2:0]\v_cmp_reg[11] ;
- input [1:0]s_buff2_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]CO;
- wire [0:0]D;
- wire [0:0]E;
- wire [2:0]Q;
- wire [2:0]S;
- wire [0:0]SR;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_4;
- wire [23:0]\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] ;
- wire intr_led_o1;
- wire intr_led_o_i_10_n_0;
- wire intr_led_o_reg;
- wire intr_led_o_reg_i_2_n_2;
- wire intr_led_o_reg_i_2_n_3;
- wire intr_led_o_reg_i_4_n_0;
- wire intr_led_o_reg_i_4_n_1;
- wire intr_led_o_reg_i_4_n_2;
- wire intr_led_o_reg_i_4_n_3;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire [1:0]s_buff2_reg_0;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_9;
- wire \s_debounce_reg[1] ;
- wire s_pulseLed_reg_0;
- wire [1:0]s_pulseLed_reg_1;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
- wire [2:0]\v_cmp_reg[11] ;
- wire [2:0]\v_cmp_reg[18] ;
- wire [2:0]\v_cmp_reg[6] ;
- wire [2:0]\v_cmpled_reg[18] ;
- wire [3:3]NLW_intr_led_o_reg_i_2_CO_UNCONNECTED;
- wire [3:0]NLW_intr_led_o_reg_i_2_O_UNCONNECTED;
- wire [3:0]NLW_intr_led_o_reg_i_4_O_UNCONNECTED;
-
- system_design_fasec_hwtest_0_0_counterUpDown_147 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_148 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_149 cmp_pulseSync
- (.CO(CO),
- .E(E),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff2_reg_1(s_buff2_reg_0),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_9(s_comparators_i_9),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg_0(D),
- .\v_cmp_reg[11] (\v_cmp_reg[11] ),
- .\v_cmp_reg[18] (\v_cmp_reg[18] ),
- .\v_cmp_reg[6] (\v_cmp_reg[6] ));
- LUT2 #(
- .INIT(4'hE))
- intr_led_o_i_1
- (.I0(intr_led_o1),
- .I1(s_pulseLed_reg_0),
- .O(intr_led_o_reg));
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_led_o_i_10
- (.I0(Q[0]),
- .I1(D),
- .I2(s_pulseLed_reg_1[1]),
- .I3(Q[2]),
- .I4(s_pulseLed_reg_1[0]),
- .I5(Q[1]),
- .O(intr_led_o_i_10_n_0));
- CARRY4 intr_led_o_reg_i_2
- (.CI(intr_led_o_reg_i_4_n_0),
- .CO({NLW_intr_led_o_reg_i_2_CO_UNCONNECTED[3],intr_led_o1,intr_led_o_reg_i_2_n_2,intr_led_o_reg_i_2_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b1,1'b1,1'b1}),
- .O(NLW_intr_led_o_reg_i_2_O_UNCONNECTED[3:0]),
- .S({1'b0,\v_cmpled_reg[18] }));
- CARRY4 intr_led_o_reg_i_4
- (.CI(1'b0),
- .CO({intr_led_o_reg_i_4_n_0,intr_led_o_reg_i_4_n_1,intr_led_o_reg_i_4_n_2,intr_led_o_reg_i_4_n_3}),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(NLW_intr_led_o_reg_i_4_O_UNCONNECTED[3:0]),
- .S({intr_led_o_i_10_n_0,S}));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(SR),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_121
- (\s_datao_fmc1[5] ,
- s_buff3_reg,
- \axi_rdata_reg[0] ,
- intr_led_o_reg,
- s_buff2_reg,
- s00_axi_aclk,
- SR,
- D,
- \s_debounce_reg[1] ,
- Q,
- \axi_araddr_reg[3]_rep__3 ,
- \axi_araddr_reg[2]_rep__3 ,
- s_pulseLed_reg_0,
- \v_outleds_reg[2] ,
- s_pulseLed_reg_1,
- s00_axi_aresetn);
- output [0:0]\s_datao_fmc1[5] ;
- output s_buff3_reg;
- output \axi_rdata_reg[0] ;
- output intr_led_o_reg;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]SR;
- input [0:0]D;
- input \s_debounce_reg[1] ;
- input [0:0]Q;
- input \axi_araddr_reg[3]_rep__3 ;
- input \axi_araddr_reg[2]_rep__3 ;
- input [0:0]s_pulseLed_reg_0;
- input [2:0]\v_outleds_reg[2] ;
- input [1:0]s_pulseLed_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire [0:0]SR;
- wire \axi_araddr_reg[2]_rep__3 ;
- wire \axi_araddr_reg[3]_rep__3 ;
- wire \axi_rdata_reg[0] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire intr_led_o_reg;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]\s_datao_fmc1[5] ;
- wire \s_debounce_reg[1] ;
- wire [0:0]s_pulseLed_reg_0;
- wire [1:0]s_pulseLed_reg_1;
- wire [2:0]\v_outleds_reg[2] ;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[0]_i_34
- (.I0(Q),
- .I1(\axi_araddr_reg[3]_rep__3 ),
- .I2(\s_datao_fmc1[5] ),
- .I3(\axi_araddr_reg[2]_rep__3 ),
- .I4(s_pulseLed_reg_0),
- .O(\axi_rdata_reg[0] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_145 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc1[5] ));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_146 cmp_pulseSync
- (.D(D),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(\s_datao_fmc1[5] ));
- LUT6 #(
- .INIT(64'h6FF6FFFFFFFF6FF6))
- intr_led_o_i_9
- (.I0(\v_outleds_reg[2] [0]),
- .I1(\s_datao_fmc1[5] ),
- .I2(s_pulseLed_reg_1[1]),
- .I3(\v_outleds_reg[2] [2]),
- .I4(s_pulseLed_reg_1[0]),
- .I5(\v_outleds_reg[2] [1]),
- .O(intr_led_o_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(\s_datao_fmc1[5] ));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_122
- (s_count_reg,
- s_buff3_reg,
- \axi_rdata_reg[1] ,
- s_buff2_reg,
- s00_axi_aclk,
- SR,
- D,
- \s_debounce_reg[1] ,
- Q,
- \axi_araddr_reg[3]_rep__3 ,
- \axi_araddr_reg[2]_rep__3 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output s_buff3_reg;
- output \axi_rdata_reg[1] ;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]SR;
- input [0:0]D;
- input \s_debounce_reg[1] ;
- input [0:0]Q;
- input \axi_araddr_reg[3]_rep__3 ;
- input \axi_araddr_reg[2]_rep__3 ;
- input [0:0]s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire [0:0]SR;
- wire \axi_araddr_reg[2]_rep__3 ;
- wire \axi_araddr_reg[3]_rep__3 ;
- wire \axi_rdata_reg[1] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
- wire [0:0]s_pulseLed_reg_0;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[1]_i_34
- (.I0(Q),
- .I1(\axi_araddr_reg[3]_rep__3 ),
- .I2(s_count_reg),
- .I3(\axi_araddr_reg[2]_rep__3 ),
- .I4(s_pulseLed_reg_0),
- .O(\axi_rdata_reg[1] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_143 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_144 cmp_pulseSync
- (.D(D),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_123
- (s_count_reg,
- s_buff3_reg,
- \axi_rdata_reg[2] ,
- s_buff2_reg,
- s00_axi_aclk,
- SR,
- D,
- \s_debounce_reg[1] ,
- Q,
- \axi_araddr_reg[3]_rep__3 ,
- \axi_araddr_reg[2]_rep__3 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output s_buff3_reg;
- output \axi_rdata_reg[2] ;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]SR;
- input [0:0]D;
- input \s_debounce_reg[1] ;
- input [0:0]Q;
- input \axi_araddr_reg[3]_rep__3 ;
- input \axi_araddr_reg[2]_rep__3 ;
- input [0:0]s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire [0:0]SR;
- wire \axi_araddr_reg[2]_rep__3 ;
- wire \axi_araddr_reg[3]_rep__3 ;
- wire \axi_rdata_reg[2] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
- wire [0:0]s_pulseLed_reg_0;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[2]_i_34
- (.I0(Q),
- .I1(\axi_araddr_reg[3]_rep__3 ),
- .I2(s_count_reg),
- .I3(\axi_araddr_reg[2]_rep__3 ),
- .I4(s_pulseLed_reg_0),
- .O(\axi_rdata_reg[2] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_141 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_142 cmp_pulseSync
- (.D(D),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_124
- (\s_datao_fmc1[5] ,
- s_buff3_reg,
- \axi_rdata_reg[3] ,
- intr_led_o_reg,
- s_buff2_reg,
- s00_axi_aclk,
- SR,
- D,
- \s_debounce_reg[1] ,
- Q,
- \axi_araddr_reg[3]_rep__2 ,
- \axi_araddr_reg[2]_rep__2 ,
- s_pulseLed_reg_0,
- \v_outleds_reg[5] ,
- s_pulseLed_reg_1,
- s00_axi_aresetn);
- output [0:0]\s_datao_fmc1[5] ;
- output s_buff3_reg;
- output \axi_rdata_reg[3] ;
- output intr_led_o_reg;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]SR;
- input [0:0]D;
- input \s_debounce_reg[1] ;
- input [0:0]Q;
- input \axi_araddr_reg[3]_rep__2 ;
- input \axi_araddr_reg[2]_rep__2 ;
- input [0:0]s_pulseLed_reg_0;
- input [2:0]\v_outleds_reg[5] ;
- input [1:0]s_pulseLed_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire [0:0]SR;
- wire \axi_araddr_reg[2]_rep__2 ;
- wire \axi_araddr_reg[3]_rep__2 ;
- wire \axi_rdata_reg[3] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire intr_led_o_reg;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]\s_datao_fmc1[5] ;
- wire \s_debounce_reg[1] ;
- wire [0:0]s_pulseLed_reg_0;
- wire [1:0]s_pulseLed_reg_1;
- wire [2:0]\v_outleds_reg[5] ;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[3]_i_34
- (.I0(Q),
- .I1(\axi_araddr_reg[3]_rep__2 ),
- .I2(\s_datao_fmc1[5] ),
- .I3(\axi_araddr_reg[2]_rep__2 ),
- .I4(s_pulseLed_reg_0),
- .O(\axi_rdata_reg[3] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_139 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc1[5] ));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_140 cmp_pulseSync
- (.D(D),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(\s_datao_fmc1[5] ));
- LUT6 #(
- .INIT(64'h6FF6FFFFFFFF6FF6))
- intr_led_o_i_8
- (.I0(\v_outleds_reg[5] [0]),
- .I1(\s_datao_fmc1[5] ),
- .I2(s_pulseLed_reg_1[1]),
- .I3(\v_outleds_reg[5] [2]),
- .I4(s_pulseLed_reg_1[0]),
- .I5(\v_outleds_reg[5] [1]),
- .O(intr_led_o_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(\s_datao_fmc1[5] ));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_125
- (s_count_reg,
- s_buff3_reg,
- \axi_rdata_reg[4] ,
- s_buff2_reg,
- s00_axi_aclk,
- SR,
- Q,
- \s_debounce_reg[1] ,
- \data_o_reg[6][4] ,
- \axi_araddr_reg[3]_rep__2 ,
- \axi_araddr_reg[2]_rep__2 ,
- D,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output s_buff3_reg;
- output \axi_rdata_reg[4] ;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]SR;
- input [0:0]Q;
- input \s_debounce_reg[1] ;
- input [0:0]\data_o_reg[6][4] ;
- input \axi_araddr_reg[3]_rep__2 ;
- input \axi_araddr_reg[2]_rep__2 ;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire [0:0]SR;
- wire \axi_araddr_reg[2]_rep__2 ;
- wire \axi_araddr_reg[3]_rep__2 ;
- wire \axi_rdata_reg[4] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire [0:0]\data_o_reg[6][4] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[4]_i_34
- (.I0(\data_o_reg[6][4] ),
- .I1(\axi_araddr_reg[3]_rep__2 ),
- .I2(s_count_reg),
- .I3(\axi_araddr_reg[2]_rep__2 ),
- .I4(D),
- .O(\axi_rdata_reg[4] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_137 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_138 cmp_pulseSync
- (.Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_126
- (s_count_reg,
- s_buff3_reg,
- \axi_rdata_reg[5] ,
- s_buff2_reg,
- s00_axi_aclk,
- SR,
- Q,
- \s_debounce_reg[1] ,
- \data_o_reg[6][5] ,
- \axi_araddr_reg[3]_rep__2 ,
- \axi_araddr_reg[2]_rep__2 ,
- D,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output s_buff3_reg;
- output \axi_rdata_reg[5] ;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]SR;
- input [0:0]Q;
- input \s_debounce_reg[1] ;
- input [0:0]\data_o_reg[6][5] ;
- input \axi_araddr_reg[3]_rep__2 ;
- input \axi_araddr_reg[2]_rep__2 ;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire [0:0]SR;
- wire \axi_araddr_reg[2]_rep__2 ;
- wire \axi_araddr_reg[3]_rep__2 ;
- wire \axi_rdata_reg[5] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire [0:0]\data_o_reg[6][5] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[5]_i_34
- (.I0(\data_o_reg[6][5] ),
- .I1(\axi_araddr_reg[3]_rep__2 ),
- .I2(s_count_reg),
- .I3(\axi_araddr_reg[2]_rep__2 ),
- .I4(D),
- .O(\axi_rdata_reg[5] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_135 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_136 cmp_pulseSync
- (.Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_127
- (\s_datao_fmc1[5] ,
- s_buff3_reg,
- \axi_rdata_reg[6] ,
- s_buff2_reg,
- s00_axi_aclk,
- SR,
- Q,
- \s_debounce_reg[1] ,
- \data_o_reg[6][6] ,
- \axi_araddr_reg[3]_rep__2 ,
- \axi_araddr_reg[2]_rep__2 ,
- D,
- s00_axi_aresetn);
- output [0:0]\s_datao_fmc1[5] ;
- output s_buff3_reg;
- output \axi_rdata_reg[6] ;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]SR;
- input [0:0]Q;
- input \s_debounce_reg[1] ;
- input [0:0]\data_o_reg[6][6] ;
- input \axi_araddr_reg[3]_rep__2 ;
- input \axi_araddr_reg[2]_rep__2 ;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire [0:0]SR;
- wire \axi_araddr_reg[2]_rep__2 ;
- wire \axi_araddr_reg[3]_rep__2 ;
- wire \axi_rdata_reg[6] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire [0:0]\data_o_reg[6][6] ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]\s_datao_fmc1[5] ;
- wire \s_debounce_reg[1] ;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[6]_i_34
- (.I0(\data_o_reg[6][6] ),
- .I1(\axi_araddr_reg[3]_rep__2 ),
- .I2(\s_datao_fmc1[5] ),
- .I3(\axi_araddr_reg[2]_rep__2 ),
- .I4(D),
- .O(\axi_rdata_reg[6] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_133 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc1[5] ));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_134 cmp_pulseSync
- (.Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(\s_datao_fmc1[5] ));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(\s_datao_fmc1[5] ));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_128
- (\s_datao_fmc1[5] ,
- s_buff3_reg,
- \axi_rdata_reg[7] ,
- intr_led_o_reg,
- s_buff2_reg,
- s00_axi_aclk,
- SR,
- Q,
- \s_debounce_reg[1] ,
- \data_o_reg[6][7] ,
- \axi_araddr_reg[3]_rep__2 ,
- \axi_araddr_reg[2]_rep__2 ,
- D,
- \v_outleds_reg[7] ,
- s_pulseLed_reg_0,
- \v_outleds_reg[3] ,
- \v_outleds_reg[0] ,
- s00_axi_aresetn);
- output [0:0]\s_datao_fmc1[5] ;
- output s_buff3_reg;
- output \axi_rdata_reg[7] ;
- output intr_led_o_reg;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input [0:0]SR;
- input [0:0]Q;
- input \s_debounce_reg[1] ;
- input [0:0]\data_o_reg[6][7] ;
- input \axi_araddr_reg[3]_rep__2 ;
- input \axi_araddr_reg[2]_rep__2 ;
- input [0:0]D;
- input [1:0]\v_outleds_reg[7] ;
- input [0:0]s_pulseLed_reg_0;
- input \v_outleds_reg[3] ;
- input \v_outleds_reg[0] ;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire [0:0]SR;
- wire \axi_araddr_reg[2]_rep__2 ;
- wire \axi_araddr_reg[3]_rep__2 ;
- wire \axi_rdata_reg[7] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire [0:0]\data_o_reg[6][7] ;
- wire intr_led_o_reg;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]\s_datao_fmc1[5] ;
- wire \s_debounce_reg[1] ;
- wire [0:0]s_pulseLed_reg_0;
- wire \v_outleds_reg[0] ;
- wire \v_outleds_reg[3] ;
- wire [1:0]\v_outleds_reg[7] ;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[7]_i_34
- (.I0(\data_o_reg[6][7] ),
- .I1(\axi_araddr_reg[3]_rep__2 ),
- .I2(\s_datao_fmc1[5] ),
- .I3(\axi_araddr_reg[2]_rep__2 ),
- .I4(D),
- .O(\axi_rdata_reg[7] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_131 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc1[5] ));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_132 cmp_pulseSync
- (.Q(Q),
- .SR(SR),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(\s_datao_fmc1[5] ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF6FF6))
- intr_led_o_i_3
- (.I0(\s_datao_fmc1[5] ),
- .I1(\v_outleds_reg[7] [1]),
- .I2(s_pulseLed_reg_0),
- .I3(\v_outleds_reg[7] [0]),
- .I4(\v_outleds_reg[3] ),
- .I5(\v_outleds_reg[0] ),
- .O(intr_led_o_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(SR),
- .D(cmp_pulseCounterLED_n_0),
- .Q(\s_datao_fmc1[5] ));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_13
- (\s_datao_fmc2[4] ,
- D,
- S,
- intr_o_reg,
- E,
- s_buff2_reg,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_3,
- Q,
- s_pulseLed_reg_0,
- \v_cmp_reg[5] ,
- s_buff2_reg_0,
- s00_axi_aresetn);
- output [0:0]\s_datao_fmc2[4] ;
- output [0:0]D;
- output [0:0]S;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output [4:0]s_buff2_reg;
- output [23:0]\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_3;
- input [2:0]Q;
- input [1:0]s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[5] ;
- input [1:0]s_buff2_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [2:0]Q;
- wire [0:0]S;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_4;
- wire [23:0]\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] ;
- wire [0:0]intr_o_reg;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire [1:0]s_buff2_reg_0;
- wire s_comparators_i_3;
- wire [0:0]\s_datao_fmc2[4] ;
- wire \s_debounce_reg[1] ;
- wire [1:0]s_pulseLed_reg_0;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
- wire [2:0]\v_cmp_reg[5] ;
-
- system_design_fasec_hwtest_0_0_counterUpDown_59 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_60 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc2[4] ));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_61 cmp_pulseSync
- (.E(E),
- .intr_o_reg(intr_o_reg),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff2_reg_1(s_buff2_reg_0),
- .s_buff3_reg_0(D),
- .s_comparators_i_3(s_comparators_i_3),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg_0(\s_datao_fmc2[4] ),
- .\v_cmp_reg[5] (\v_cmp_reg[5] ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_led_o_i_12__0
- (.I0(Q[0]),
- .I1(\s_datao_fmc2[4] ),
- .I2(s_pulseLed_reg_0[1]),
- .I3(Q[2]),
- .I4(s_pulseLed_reg_0[0]),
- .I5(Q[1]),
- .O(S));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(\s_datao_fmc2[4] ));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[3].gen_chs.data_o_reg[51][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_14
- (s_count_reg,
- D,
- E,
- Q,
- \fmc_03287_channels[4].gen_chs.data_o_reg[52][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_4,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output [0:0]D;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_4;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_comparators_i_4;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_56 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_57 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_58 cmp_pulseSync
- (.E(E),
- .Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(D),
- .s_comparators_i_4(s_comparators_i_4),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[4].gen_chs.data_o_reg[52][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_15
- (s_count_reg,
- D,
- E,
- Q,
- \fmc_03287_channels[5].gen_chs.data_o_reg[53][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_5,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output [0:0]D;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_5;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_comparators_i_5;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_53 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_54 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_55 cmp_pulseSync
- (.E(E),
- .Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(D),
- .s_comparators_i_5(s_comparators_i_5),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[5].gen_chs.data_o_reg[53][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_16
- (\s_datao_fmc2[4] ,
- D,
- S,
- intr_o_reg,
- E,
- s_buff2_reg,
- \fmc_03287_channels[6].gen_chs.data_o_reg[54][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_6,
- Q,
- s_pulseLed_reg_0,
- \v_cmp_reg[8] ,
- s_buff2_reg_0,
- s00_axi_aresetn);
- output [0:0]\s_datao_fmc2[4] ;
- output [0:0]D;
- output [0:0]S;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output [4:0]s_buff2_reg;
- output [23:0]\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_6;
- input [2:0]Q;
- input [1:0]s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[8] ;
- input [1:0]s_buff2_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [2:0]Q;
- wire [0:0]S;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_4;
- wire [23:0]\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] ;
- wire [0:0]intr_o_reg;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire [1:0]s_buff2_reg_0;
- wire s_comparators_i_6;
- wire [0:0]\s_datao_fmc2[4] ;
- wire \s_debounce_reg[1] ;
- wire [1:0]s_pulseLed_reg_0;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
- wire [2:0]\v_cmp_reg[8] ;
-
- system_design_fasec_hwtest_0_0_counterUpDown_50 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_51 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc2[4] ));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_52 cmp_pulseSync
- (.E(E),
- .intr_o_reg(intr_o_reg),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff2_reg_1(s_buff2_reg_0),
- .s_buff3_reg_0(D),
- .s_comparators_i_6(s_comparators_i_6),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg_0(\s_datao_fmc2[4] ),
- .\v_cmp_reg[8] (\v_cmp_reg[8] ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_led_o_i_11__0
- (.I0(Q[0]),
- .I1(\s_datao_fmc2[4] ),
- .I2(s_pulseLed_reg_0[1]),
- .I3(Q[2]),
- .I4(s_pulseLed_reg_0[0]),
- .I5(Q[1]),
- .O(S));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(\s_datao_fmc2[4] ));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[6].gen_chs.data_o_reg[54][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_17
- (s_count_reg,
- D,
- E,
- Q,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_7,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output [0:0]D;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_7;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire s_comparators_i_7;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_47 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(D));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_48 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_49 cmp_pulseSync
- (.E(E),
- .Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(D),
- .s_comparators_i_7(s_comparators_i_7),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[7].gen_chs.data_o_reg[55][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(D),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_18
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[8].gen_chs.data_o_reg[56][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_8,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_8;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_8;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_44 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_45 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_46 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_8(s_comparators_i_8),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[8].gen_chs.data_o_reg[56][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_19
- (D,
- s_buff3_reg,
- intr_led_o_reg,
- CO,
- E,
- s_buff2_reg,
- \fmc_03287_channels[9].gen_chs.data_o_reg[57][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_9,
- s_pulseLed_reg_0,
- Q,
- s_pulseLed_reg_1,
- S,
- \v_cmpled_reg[18] ,
- \v_cmp_reg[6] ,
- \v_cmp_reg[18] ,
- \v_cmp_reg[11] ,
- s_buff2_reg_0,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output intr_led_o_reg;
- output [0:0]CO;
- output [0:0]E;
- output [4:0]s_buff2_reg;
- output [23:0]\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_9;
- input s_pulseLed_reg_0;
- input [2:0]Q;
- input [1:0]s_pulseLed_reg_1;
- input [2:0]S;
- input [2:0]\v_cmpled_reg[18] ;
- input [2:0]\v_cmp_reg[6] ;
- input [2:0]\v_cmp_reg[18] ;
- input [2:0]\v_cmp_reg[11] ;
- input [1:0]s_buff2_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]CO;
- wire [0:0]D;
- wire [0:0]E;
- wire [2:0]Q;
- wire [2:0]S;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_4;
- wire [23:0]\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] ;
- wire intr_led_o1;
- wire intr_led_o_i_10__0_n_0;
- wire intr_led_o_reg;
- wire intr_led_o_reg_i_2__0_n_2;
- wire intr_led_o_reg_i_2__0_n_3;
- wire intr_led_o_reg_i_4__0_n_0;
- wire intr_led_o_reg_i_4__0_n_1;
- wire intr_led_o_reg_i_4__0_n_2;
- wire intr_led_o_reg_i_4__0_n_3;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire [1:0]s_buff2_reg_0;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_9;
- wire \s_debounce_reg[1] ;
- wire s_pulseLed_reg_0;
- wire [1:0]s_pulseLed_reg_1;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
- wire [2:0]\v_cmp_reg[11] ;
- wire [2:0]\v_cmp_reg[18] ;
- wire [2:0]\v_cmp_reg[6] ;
- wire [2:0]\v_cmpled_reg[18] ;
- wire [3:3]NLW_intr_led_o_reg_i_2__0_CO_UNCONNECTED;
- wire [3:0]NLW_intr_led_o_reg_i_2__0_O_UNCONNECTED;
- wire [3:0]NLW_intr_led_o_reg_i_4__0_O_UNCONNECTED;
-
- system_design_fasec_hwtest_0_0_counterUpDown cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_42 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_43 cmp_pulseSync
- (.CO(CO),
- .E(E),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff2_reg_1(s_buff2_reg_0),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_9(s_comparators_i_9),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg_0(D),
- .\v_cmp_reg[11] (\v_cmp_reg[11] ),
- .\v_cmp_reg[18] (\v_cmp_reg[18] ),
- .\v_cmp_reg[6] (\v_cmp_reg[6] ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_led_o_i_10__0
- (.I0(Q[0]),
- .I1(D),
- .I2(s_pulseLed_reg_1[1]),
- .I3(Q[2]),
- .I4(s_pulseLed_reg_1[0]),
- .I5(Q[1]),
- .O(intr_led_o_i_10__0_n_0));
- LUT2 #(
- .INIT(4'hE))
- intr_led_o_i_1__0
- (.I0(intr_led_o1),
- .I1(s_pulseLed_reg_0),
- .O(intr_led_o_reg));
- CARRY4 intr_led_o_reg_i_2__0
- (.CI(intr_led_o_reg_i_4__0_n_0),
- .CO({NLW_intr_led_o_reg_i_2__0_CO_UNCONNECTED[3],intr_led_o1,intr_led_o_reg_i_2__0_n_2,intr_led_o_reg_i_2__0_n_3}),
- .CYINIT(1'b0),
- .DI({1'b0,1'b1,1'b1,1'b1}),
- .O(NLW_intr_led_o_reg_i_2__0_O_UNCONNECTED[3:0]),
- .S({1'b0,\v_cmpled_reg[18] }));
- CARRY4 intr_led_o_reg_i_4__0
- (.CI(1'b0),
- .CO({intr_led_o_reg_i_4__0_n_0,intr_led_o_reg_i_4__0_n_1,intr_led_o_reg_i_4__0_n_2,intr_led_o_reg_i_4__0_n_3}),
- .CYINIT(1'b0),
- .DI({1'b1,1'b1,1'b1,1'b1}),
- .O(NLW_intr_led_o_reg_i_4__0_O_UNCONNECTED[3:0]),
- .S({intr_led_o_i_10__0_n_0,S}));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[9].gen_chs.data_o_reg[57][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_2
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_11,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_11;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_11;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_92 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_93 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_94 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_11(s_comparators_i_11),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[11].gen_chs.data_o_reg[59][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_20
- (\s_datao_fmc2[5] ,
- s_buff3_reg,
- \axi_rdata_reg[0] ,
- intr_led_o_reg,
- s_buff2_reg,
- s00_axi_aclk,
- rst_i,
- D,
- \s_debounce_reg[1] ,
- Q,
- \axi_araddr_reg[3]_rep__3 ,
- \axi_araddr_reg[2]_rep__3 ,
- s_pulseLed_reg_0,
- \v_outleds_reg[2] ,
- s_pulseLed_reg_1,
- s00_axi_aresetn);
- output [0:0]\s_datao_fmc2[5] ;
- output s_buff3_reg;
- output \axi_rdata_reg[0] ;
- output intr_led_o_reg;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input rst_i;
- input [0:0]D;
- input \s_debounce_reg[1] ;
- input [0:0]Q;
- input \axi_araddr_reg[3]_rep__3 ;
- input \axi_araddr_reg[2]_rep__3 ;
- input [0:0]s_pulseLed_reg_0;
- input [2:0]\v_outleds_reg[2] ;
- input [1:0]s_pulseLed_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire \axi_araddr_reg[2]_rep__3 ;
- wire \axi_araddr_reg[3]_rep__3 ;
- wire \axi_rdata_reg[0] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire intr_led_o_reg;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]\s_datao_fmc2[5] ;
- wire \s_debounce_reg[1] ;
- wire [0:0]s_pulseLed_reg_0;
- wire [1:0]s_pulseLed_reg_1;
- wire [2:0]\v_outleds_reg[2] ;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[0]_i_38
- (.I0(Q),
- .I1(\axi_araddr_reg[3]_rep__3 ),
- .I2(\s_datao_fmc2[5] ),
- .I3(\axi_araddr_reg[2]_rep__3 ),
- .I4(s_pulseLed_reg_0),
- .O(\axi_rdata_reg[0] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_40 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc2[5] ));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_41 cmp_pulseSync
- (.D(D),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(\s_datao_fmc2[5] ));
- LUT6 #(
- .INIT(64'h6FF6FFFFFFFF6FF6))
- intr_led_o_i_9__0
- (.I0(\v_outleds_reg[2] [0]),
- .I1(\s_datao_fmc2[5] ),
- .I2(s_pulseLed_reg_1[1]),
- .I3(\v_outleds_reg[2] [2]),
- .I4(s_pulseLed_reg_1[0]),
- .I5(\v_outleds_reg[2] [1]),
- .O(intr_led_o_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(\s_datao_fmc2[5] ));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_21
- (s_count_reg,
- s_buff3_reg,
- \axi_rdata_reg[1] ,
- s_buff2_reg,
- s00_axi_aclk,
- rst_i,
- D,
- \s_debounce_reg[1] ,
- Q,
- \axi_araddr_reg[3]_rep__3 ,
- \axi_araddr_reg[2]_rep__3 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output s_buff3_reg;
- output \axi_rdata_reg[1] ;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input rst_i;
- input [0:0]D;
- input \s_debounce_reg[1] ;
- input [0:0]Q;
- input \axi_araddr_reg[3]_rep__3 ;
- input \axi_araddr_reg[2]_rep__3 ;
- input [0:0]s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire \axi_araddr_reg[2]_rep__3 ;
- wire \axi_araddr_reg[3]_rep__3 ;
- wire \axi_rdata_reg[1] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
- wire [0:0]s_pulseLed_reg_0;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[1]_i_38
- (.I0(Q),
- .I1(\axi_araddr_reg[3]_rep__3 ),
- .I2(s_count_reg),
- .I3(\axi_araddr_reg[2]_rep__3 ),
- .I4(s_pulseLed_reg_0),
- .O(\axi_rdata_reg[1] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_38 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_39 cmp_pulseSync
- (.D(D),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_22
- (s_count_reg,
- s_buff3_reg,
- \axi_rdata_reg[2] ,
- s_buff2_reg,
- s00_axi_aclk,
- rst_i,
- D,
- \s_debounce_reg[1] ,
- Q,
- \axi_araddr_reg[3]_rep__3 ,
- \axi_araddr_reg[2]_rep__3 ,
- s_pulseLed_reg_0,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output s_buff3_reg;
- output \axi_rdata_reg[2] ;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input rst_i;
- input [0:0]D;
- input \s_debounce_reg[1] ;
- input [0:0]Q;
- input \axi_araddr_reg[3]_rep__3 ;
- input \axi_araddr_reg[2]_rep__3 ;
- input [0:0]s_pulseLed_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire \axi_araddr_reg[2]_rep__3 ;
- wire \axi_araddr_reg[3]_rep__3 ;
- wire \axi_rdata_reg[2] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
- wire [0:0]s_pulseLed_reg_0;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[2]_i_38
- (.I0(Q),
- .I1(\axi_araddr_reg[3]_rep__3 ),
- .I2(s_count_reg),
- .I3(\axi_araddr_reg[2]_rep__3 ),
- .I4(s_pulseLed_reg_0),
- .O(\axi_rdata_reg[2] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_36 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_37 cmp_pulseSync
- (.D(D),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_23
- (\s_datao_fmc2[5] ,
- s_buff3_reg,
- \axi_rdata_reg[3] ,
- intr_led_o_reg,
- s_buff2_reg,
- s00_axi_aclk,
- rst_i,
- D,
- \s_debounce_reg[1] ,
- Q,
- \axi_araddr_reg[3]_rep__2 ,
- \axi_araddr_reg[2]_rep__2 ,
- s_pulseLed_reg_0,
- \v_outleds_reg[5] ,
- s_pulseLed_reg_1,
- s00_axi_aresetn);
- output [0:0]\s_datao_fmc2[5] ;
- output s_buff3_reg;
- output \axi_rdata_reg[3] ;
- output intr_led_o_reg;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input rst_i;
- input [0:0]D;
- input \s_debounce_reg[1] ;
- input [0:0]Q;
- input \axi_araddr_reg[3]_rep__2 ;
- input \axi_araddr_reg[2]_rep__2 ;
- input [0:0]s_pulseLed_reg_0;
- input [2:0]\v_outleds_reg[5] ;
- input [1:0]s_pulseLed_reg_1;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire \axi_araddr_reg[2]_rep__2 ;
- wire \axi_araddr_reg[3]_rep__2 ;
- wire \axi_rdata_reg[3] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire intr_led_o_reg;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]\s_datao_fmc2[5] ;
- wire \s_debounce_reg[1] ;
- wire [0:0]s_pulseLed_reg_0;
- wire [1:0]s_pulseLed_reg_1;
- wire [2:0]\v_outleds_reg[5] ;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[3]_i_38
- (.I0(Q),
- .I1(\axi_araddr_reg[3]_rep__2 ),
- .I2(\s_datao_fmc2[5] ),
- .I3(\axi_araddr_reg[2]_rep__2 ),
- .I4(s_pulseLed_reg_0),
- .O(\axi_rdata_reg[3] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_34 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc2[5] ));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_35 cmp_pulseSync
- (.D(D),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(\s_datao_fmc2[5] ));
- LUT6 #(
- .INIT(64'h6FF6FFFFFFFF6FF6))
- intr_led_o_i_8__0
- (.I0(\v_outleds_reg[5] [0]),
- .I1(\s_datao_fmc2[5] ),
- .I2(s_pulseLed_reg_1[1]),
- .I3(\v_outleds_reg[5] [2]),
- .I4(s_pulseLed_reg_1[0]),
- .I5(\v_outleds_reg[5] [1]),
- .O(intr_led_o_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(\s_datao_fmc2[5] ));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_24
- (s_count_reg,
- s_buff3_reg,
- \axi_rdata_reg[4] ,
- s_buff2_reg,
- s00_axi_aclk,
- rst_i,
- Q,
- \s_debounce_reg[1] ,
- \data_o_reg[6][4] ,
- \axi_araddr_reg[3]_rep__2 ,
- \axi_araddr_reg[2]_rep__2 ,
- D,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output s_buff3_reg;
- output \axi_rdata_reg[4] ;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input rst_i;
- input [0:0]Q;
- input \s_debounce_reg[1] ;
- input [0:0]\data_o_reg[6][4] ;
- input \axi_araddr_reg[3]_rep__2 ;
- input \axi_araddr_reg[2]_rep__2 ;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire \axi_araddr_reg[2]_rep__2 ;
- wire \axi_araddr_reg[3]_rep__2 ;
- wire \axi_rdata_reg[4] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire [0:0]\data_o_reg[6][4] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[4]_i_38
- (.I0(\data_o_reg[6][4] ),
- .I1(\axi_araddr_reg[3]_rep__2 ),
- .I2(s_count_reg),
- .I3(\axi_araddr_reg[2]_rep__2 ),
- .I4(D),
- .O(\axi_rdata_reg[4] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_32 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_33 cmp_pulseSync
- (.Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_25
- (s_count_reg,
- s_buff3_reg,
- \axi_rdata_reg[5] ,
- s_buff2_reg,
- s00_axi_aclk,
- rst_i,
- Q,
- \s_debounce_reg[1] ,
- \data_o_reg[6][5] ,
- \axi_araddr_reg[3]_rep__2 ,
- \axi_araddr_reg[2]_rep__2 ,
- D,
- s00_axi_aresetn);
- output [0:0]s_count_reg;
- output s_buff3_reg;
- output \axi_rdata_reg[5] ;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input rst_i;
- input [0:0]Q;
- input \s_debounce_reg[1] ;
- input [0:0]\data_o_reg[6][5] ;
- input \axi_araddr_reg[3]_rep__2 ;
- input \axi_araddr_reg[2]_rep__2 ;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire \axi_araddr_reg[2]_rep__2 ;
- wire \axi_araddr_reg[3]_rep__2 ;
- wire \axi_rdata_reg[5] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire [0:0]\data_o_reg[6][5] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]s_count_reg;
- wire \s_debounce_reg[1] ;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[5]_i_38
- (.I0(\data_o_reg[6][5] ),
- .I1(\axi_araddr_reg[3]_rep__2 ),
- .I2(s_count_reg),
- .I3(\axi_araddr_reg[2]_rep__2 ),
- .I4(D),
- .O(\axi_rdata_reg[5] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_30 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(s_count_reg));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_31 cmp_pulseSync
- (.Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(s_count_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(s_count_reg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_26
- (\s_datao_fmc2[5] ,
- s_buff3_reg,
- \axi_rdata_reg[6] ,
- s_buff2_reg,
- s00_axi_aclk,
- rst_i,
- Q,
- \s_debounce_reg[1] ,
- \data_o_reg[6][6] ,
- \axi_araddr_reg[3]_rep__2 ,
- \axi_araddr_reg[2]_rep__2 ,
- D,
- s00_axi_aresetn);
- output [0:0]\s_datao_fmc2[5] ;
- output s_buff3_reg;
- output \axi_rdata_reg[6] ;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input rst_i;
- input [0:0]Q;
- input \s_debounce_reg[1] ;
- input [0:0]\data_o_reg[6][6] ;
- input \axi_araddr_reg[3]_rep__2 ;
- input \axi_araddr_reg[2]_rep__2 ;
- input [0:0]D;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire \axi_araddr_reg[2]_rep__2 ;
- wire \axi_araddr_reg[3]_rep__2 ;
- wire \axi_rdata_reg[6] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire [0:0]\data_o_reg[6][6] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]\s_datao_fmc2[5] ;
- wire \s_debounce_reg[1] ;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[6]_i_38
- (.I0(\data_o_reg[6][6] ),
- .I1(\axi_araddr_reg[3]_rep__2 ),
- .I2(\s_datao_fmc2[5] ),
- .I3(\axi_araddr_reg[2]_rep__2 ),
- .I4(D),
- .O(\axi_rdata_reg[6] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_28 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc2[5] ));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_29 cmp_pulseSync
- (.Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(\s_datao_fmc2[5] ));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(\s_datao_fmc2[5] ));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_27
- (\s_datao_fmc2[5] ,
- s_buff3_reg,
- \axi_rdata_reg[7] ,
- intr_led_o_reg,
- s_buff2_reg,
- s00_axi_aclk,
- rst_i,
- Q,
- \s_debounce_reg[1] ,
- \data_o_reg[6][7] ,
- \axi_araddr_reg[3]_rep__2 ,
- \axi_araddr_reg[2]_rep__2 ,
- D,
- \v_outleds_reg[7] ,
- s_pulseLed_reg_0,
- \v_outleds_reg[3] ,
- \v_outleds_reg[0] ,
- s00_axi_aresetn);
- output [0:0]\s_datao_fmc2[5] ;
- output s_buff3_reg;
- output \axi_rdata_reg[7] ;
- output intr_led_o_reg;
- output [4:0]s_buff2_reg;
- input s00_axi_aclk;
- input rst_i;
- input [0:0]Q;
- input \s_debounce_reg[1] ;
- input [0:0]\data_o_reg[6][7] ;
- input \axi_araddr_reg[3]_rep__2 ;
- input \axi_araddr_reg[2]_rep__2 ;
- input [0:0]D;
- input [1:0]\v_outleds_reg[7] ;
- input [0:0]s_pulseLed_reg_0;
- input \v_outleds_reg[3] ;
- input \v_outleds_reg[0] ;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]Q;
- wire \axi_araddr_reg[2]_rep__2 ;
- wire \axi_araddr_reg[3]_rep__2 ;
- wire \axi_rdata_reg[7] ;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_2;
- wire [0:0]\data_o_reg[6][7] ;
- wire intr_led_o_reg;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire s_buff3_reg;
- wire [0:0]\s_datao_fmc2[5] ;
- wire \s_debounce_reg[1] ;
- wire [0:0]s_pulseLed_reg_0;
- wire \v_outleds_reg[0] ;
- wire \v_outleds_reg[3] ;
- wire [1:0]\v_outleds_reg[7] ;
-
- LUT5 #(
- .INIT(32'h30BB3088))
- \axi_rdata[7]_i_38
- (.I0(\data_o_reg[6][7] ),
- .I1(\axi_araddr_reg[3]_rep__2 ),
- .I2(\s_datao_fmc2[5] ),
- .I3(\axi_araddr_reg[2]_rep__2 ),
- .I4(D),
- .O(\axi_rdata_reg[7] ));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(\s_datao_fmc2[5] ));
- system_design_fasec_hwtest_0_0_doubleBufferEdge cmp_pulseSync
- (.Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff3_reg_0(s_buff3_reg),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_2),
- .s_pulseLed_reg_0(\s_datao_fmc2[5] ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFF6FF6))
- intr_led_o_i_3__0
- (.I0(\s_datao_fmc2[5] ),
- .I1(\v_outleds_reg[7] [1]),
- .I2(s_pulseLed_reg_0),
- .I3(\v_outleds_reg[7] [0]),
- .I4(\v_outleds_reg[3] ),
- .I5(\v_outleds_reg[0] ),
- .O(intr_led_o_reg));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(\s_datao_fmc2[5] ));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_3
- (D,
- s_buff3_reg,
- S,
- intr_o_reg,
- E,
- s_buff2_reg,
- \fmc_03287_channels[12].gen_chs.data_o_reg[60][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_12,
- Q,
- s_pulseLed_reg_0,
- \v_cmp_reg[14] ,
- s_buff2_reg_0,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]S;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output [4:0]s_buff2_reg;
- output [23:0]\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_12;
- input [2:0]Q;
- input [1:0]s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[14] ;
- input [1:0]s_buff2_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [2:0]Q;
- wire [0:0]S;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_4;
- wire [23:0]\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] ;
- wire [0:0]intr_o_reg;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire [1:0]s_buff2_reg_0;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_12;
- wire \s_debounce_reg[1] ;
- wire [1:0]s_pulseLed_reg_0;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
- wire [2:0]\v_cmp_reg[14] ;
-
- system_design_fasec_hwtest_0_0_counterUpDown_89 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_90 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_91 cmp_pulseSync
- (.E(E),
- .intr_o_reg(intr_o_reg),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff2_reg_1(s_buff2_reg_0),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_12(s_comparators_i_12),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg_0(D),
- .\v_cmp_reg[14] (\v_cmp_reg[14] ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_led_o_i_7__0
- (.I0(Q[0]),
- .I1(D),
- .I2(s_pulseLed_reg_0[1]),
- .I3(Q[2]),
- .I4(s_pulseLed_reg_0[0]),
- .I5(Q[1]),
- .O(S));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[12].gen_chs.data_o_reg[60][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_4
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[13].gen_chs.data_o_reg[61][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_13,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_13;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_13;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_86 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_87 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_88 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_13(s_comparators_i_13),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[13].gen_chs.data_o_reg[61][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_5
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[14].gen_chs.data_o_reg[62][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_14,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_14;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_14;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_83 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_84 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_85 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_14(s_comparators_i_14),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[14].gen_chs.data_o_reg[62][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_6
- (D,
- s_buff3_reg,
- S,
- intr_o_reg,
- E,
- s_buff2_reg,
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_15,
- Q,
- s_pulseLed_reg_0,
- \v_cmp_reg[17] ,
- s_buff2_reg_0,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]S;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output [4:0]s_buff2_reg;
- output [23:0]\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_15;
- input [2:0]Q;
- input [1:0]s_pulseLed_reg_0;
- input [2:0]\v_cmp_reg[17] ;
- input [1:0]s_buff2_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [2:0]Q;
- wire [0:0]S;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_4;
- wire [23:0]\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] ;
- wire [0:0]intr_o_reg;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire [1:0]s_buff2_reg_0;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_15;
- wire \s_debounce_reg[1] ;
- wire [1:0]s_pulseLed_reg_0;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
- wire [2:0]\v_cmp_reg[17] ;
-
- system_design_fasec_hwtest_0_0_counterUpDown_80 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_81 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_82 cmp_pulseSync
- (.E(E),
- .intr_o_reg(intr_o_reg),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff2_reg_1(s_buff2_reg_0),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_15(s_comparators_i_15),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg_0(D),
- .\v_cmp_reg[17] (\v_cmp_reg[17] ));
- LUT6 #(
- .INIT(64'h9009000000009009))
- intr_led_o_i_6__0
- (.I0(Q[0]),
- .I1(D),
- .I2(s_pulseLed_reg_0[1]),
- .I3(Q[2]),
- .I4(s_pulseLed_reg_0[0]),
- .I5(Q[1]),
- .O(S));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[15].gen_chs.data_o_reg[63][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_7
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[16].gen_chs.data_o_reg[64][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_16,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_16;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_16;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_77 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_78 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_79 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_16(s_comparators_i_16),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[16].gen_chs.data_o_reg[64][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_8
- (D,
- s_buff3_reg,
- E,
- Q,
- \fmc_03287_channels[17].gen_chs.data_o_reg[65][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_17,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]E;
- output [4:0]Q;
- output [23:0]\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_17;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [4:0]Q;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_3;
- wire [23:0]\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] ;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_17;
- wire \s_debounce_reg[1] ;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
-
- system_design_fasec_hwtest_0_0_counterUpDown_74 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_75 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_3),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_76 cmp_pulseSync
- (.D(D),
- .E(E),
- .Q(Q),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_17(s_comparators_i_17),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_3));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[17].gen_chs.data_o_reg[65][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "pulseMeasure" *)
-module system_design_fasec_hwtest_0_0_pulseMeasure_9
- (D,
- s_buff3_reg,
- S,
- intr_o_reg,
- E,
- s_buff2_reg,
- \fmc_03287_channels[18].gen_chs.data_o_reg[66][23] ,
- s00_axi_aclk,
- rst_i,
- \s_debounce_reg[1] ,
- s_comparators_i_18,
- Q,
- s_pulseLed_reg_0,
- \v_cmp_reg[19] ,
- s_buff2_reg_0,
- s00_axi_aresetn);
- output [0:0]D;
- output [0:0]s_buff3_reg;
- output [0:0]S;
- output [0:0]intr_o_reg;
- output [0:0]E;
- output [4:0]s_buff2_reg;
- output [23:0]\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] ;
- input s00_axi_aclk;
- input rst_i;
- input \s_debounce_reg[1] ;
- input s_comparators_i_18;
- input [1:0]Q;
- input [0:0]s_pulseLed_reg_0;
- input [1:0]\v_cmp_reg[19] ;
- input [0:0]s_buff2_reg_0;
- input s00_axi_aresetn;
-
- wire [0:0]D;
- wire [0:0]E;
- wire [1:0]Q;
- wire [0:0]S;
- wire cmp_pulseCounterLED_n_0;
- wire cmp_pulseSync_n_1;
- wire cmp_pulseSync_n_4;
- wire [23:0]\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] ;
- wire [0:0]intr_o_reg;
- wire rst_i;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [4:0]s_buff2_reg;
- wire [0:0]s_buff2_reg_0;
- wire [0:0]s_buff3_reg;
- wire s_comparators_i_18;
- wire \s_debounce_reg[1] ;
- wire [0:0]s_pulseLed_reg_0;
- wire [23:0]s_pulseLength;
- wire s_pulseReg;
- wire [1:0]\v_cmp_reg[19] ;
-
- system_design_fasec_hwtest_0_0_counterUpDown_71 cmp_lengthCounter
- (.E(E),
- .count_o(s_pulseLength),
- .s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(s_buff3_reg));
- system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_72 cmp_pulseCounterLED
- (.s00_axi_aclk(s00_axi_aclk),
- .s_buff2_reg(cmp_pulseSync_n_1),
- .s_buff3_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg(cmp_pulseCounterLED_n_0),
- .s_pulseLed_reg_0(D));
- system_design_fasec_hwtest_0_0_doubleBufferEdge_73 cmp_pulseSync
- (.E(E),
- .intr_o_reg(intr_o_reg),
- .rst_i(rst_i),
- .s00_axi_aclk(s00_axi_aclk),
- .s00_axi_aresetn(s00_axi_aresetn),
- .s_buff2_reg_0(s_buff2_reg),
- .s_buff2_reg_1(s_buff2_reg_0),
- .s_buff3_reg_0(s_buff3_reg),
- .s_comparators_i_18(s_comparators_i_18),
- .s_count_reg(cmp_pulseSync_n_1),
- .\s_debounce_reg[1]_0 (\s_debounce_reg[1] ),
- .s_pulseLed_reg(cmp_pulseSync_n_4),
- .s_pulseLed_reg_0(D),
- .\v_cmp_reg[19] (\v_cmp_reg[19] ));
- LUT4 #(
- .INIT(16'h9009))
- intr_led_o_i_5__0
- (.I0(Q[0]),
- .I1(D),
- .I2(Q[1]),
- .I3(s_pulseLed_reg_0),
- .O(S));
- FDCE s_pulseLed_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(cmp_pulseCounterLED_n_0),
- .Q(D));
- FDCE \s_pulseLengthLatch_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[0]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [0]));
- FDCE \s_pulseLengthLatch_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[10]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [10]));
- FDCE \s_pulseLengthLatch_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[11]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [11]));
- FDCE \s_pulseLengthLatch_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[12]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [12]));
- FDCE \s_pulseLengthLatch_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[13]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [13]));
- FDCE \s_pulseLengthLatch_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[14]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [14]));
- FDCE \s_pulseLengthLatch_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[15]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [15]));
- FDCE \s_pulseLengthLatch_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[16]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [16]));
- FDCE \s_pulseLengthLatch_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[17]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [17]));
- FDCE \s_pulseLengthLatch_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[18]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [18]));
- FDCE \s_pulseLengthLatch_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[19]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [19]));
- FDCE \s_pulseLengthLatch_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[1]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [1]));
- FDCE \s_pulseLengthLatch_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[20]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [20]));
- FDCE \s_pulseLengthLatch_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[21]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [21]));
- FDCE \s_pulseLengthLatch_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[22]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [22]));
- FDCE \s_pulseLengthLatch_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[23]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [23]));
- FDCE \s_pulseLengthLatch_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[2]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [2]));
- FDCE \s_pulseLengthLatch_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[3]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [3]));
- FDCE \s_pulseLengthLatch_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[4]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [4]));
- FDCE \s_pulseLengthLatch_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[5]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [5]));
- FDCE \s_pulseLengthLatch_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[6]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [6]));
- FDCE \s_pulseLengthLatch_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[7]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [7]));
- FDCE \s_pulseLengthLatch_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[8]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [8]));
- FDCE \s_pulseLengthLatch_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_pulseReg),
- .CLR(rst_i),
- .D(s_pulseLength[9]),
- .Q(\fmc_03287_channels[18].gen_chs.data_o_reg[66][23] [9]));
- FDCE s_pulseReg_reg
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .CLR(rst_i),
- .D(s_buff3_reg),
- .Q(s_pulseReg));
-endmodule
-
-(* ORIG_REF_NAME = "spi_transceiver" *)
-module system_design_fasec_hwtest_0_0_spi_transceiver
- (E,
- \v_ch_address_reg[0] ,
- \v_ch_address_reg[1] ,
- \s_state_reg[0] ,
- \s_state_reg[1] ,
- Q,
- \dac_ch_o_reg[0][31] ,
- s_spi_mosi,
- s_spi_cs_n,
- \data_rw_o_reg[79][1] ,
- \v_ch_address_reg[0]_0 ,
- \s_state_reg[1]_0 ,
- s00_axi_aresetn,
- \s_state_reg[0]_0 ,
- \[0].[3].s_reqs_reg[3][changed] ,
- \[0].[2].s_reqs_reg[2][changed] ,
- ch_address,
- \[0].[2].s_reqs_reg[2][changed]_0 ,
- rst_i,
- s00_axi_aclk,
- D,
- s_start_reg,
- \s_tx_data_reg[113] );
- output [0:0]E;
- output \v_ch_address_reg[0] ;
- output \v_ch_address_reg[1] ;
- output \s_state_reg[0] ;
- output \s_state_reg[1] ;
- output [0:0]Q;
- output [31:0]\dac_ch_o_reg[0][31] ;
- output s_spi_mosi;
- output s_spi_cs_n;
- input \data_rw_o_reg[79][1] ;
- input \v_ch_address_reg[0]_0 ;
- input \s_state_reg[1]_0 ;
- input s00_axi_aresetn;
- input \s_state_reg[0]_0 ;
- input \[0].[3].s_reqs_reg[3][changed] ;
- input \[0].[2].s_reqs_reg[2][changed] ;
- input [1:0]ch_address;
- input \[0].[2].s_reqs_reg[2][changed]_0 ;
- input rst_i;
- input s00_axi_aclk;
- input [0:0]D;
- input s_start_reg;
- input [61:0]\s_tx_data_reg[113] ;
-
- wire [0:0]D;
- wire [0:0]E;
- wire \FSM_sequential_s_state[0]_i_1__0_n_0 ;
- wire \FSM_sequential_s_state[0]_i_2__0_n_0 ;
- wire \FSM_sequential_s_state[0]_i_3__0_n_0 ;
- wire \FSM_sequential_s_state[1]_i_1__0_n_0 ;
- wire \FSM_sequential_s_state[2]_i_1__0_n_0 ;
- wire \FSM_sequential_s_state[2]_i_2__0_n_0 ;
- wire \FSM_sequential_s_state[2]_i_3__0_n_0 ;
- wire \FSM_sequential_s_state[2]_i_4__0_n_0 ;
- wire [0:0]Q;
- wire \[0].[2].s_reqs_reg[2][changed] ;
- wire \[0].[2].s_reqs_reg[2][changed]_0 ;
- wire \[0].[3].s_reqs_reg[3][changed] ;
- wire [1:0]ch_address;
- wire [31:0]\dac_ch_o_reg[0][31] ;
- wire \data_rw_o_reg[79][1] ;
- wire p_0_in;
- wire rst_i;
- wire \rx_data_o[31]_i_1__0_n_0 ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [1:0]s_counter;
- wire \s_counter[0]_i_1__0_n_0 ;
- wire \s_counter[1]_i_1__0_n_0 ;
- wire \s_counter[2]_i_1__0_n_0 ;
- wire s_done;
- wire [31:0]s_rxdat;
- wire s_rxdat_0;
- wire s_spi_cs_n;
- wire s_spi_mosi;
- wire s_start_reg;
- (* RTL_KEEP = "yes" *) wire [2:0]s_state;
- wire \s_state[0]_i_2__0_n_0 ;
- wire \s_state[1]_i_4__0_n_0 ;
- wire \s_state_reg[0] ;
- wire \s_state_reg[0]_0 ;
- wire \s_state_reg[1] ;
- wire \s_state_reg[1]_0 ;
- wire [61:0]\s_tx_data_reg[113] ;
- wire s_txdat;
- wire \s_txdat[100]_i_1__0_n_0 ;
- wire \s_txdat[101]_i_1__0_n_0 ;
- wire \s_txdat[102]_i_1__0_n_0 ;
- wire \s_txdat[103]_i_1__0_n_0 ;
- wire \s_txdat[104]_i_1__0_n_0 ;
- wire \s_txdat[105]_i_1__0_n_0 ;
- wire \s_txdat[106]_i_1__0_n_0 ;
- wire \s_txdat[107]_i_1__0_n_0 ;
- wire \s_txdat[108]_i_1__0_n_0 ;
- wire \s_txdat[109]_i_1__0_n_0 ;
- wire \s_txdat[10]_i_1__0_n_0 ;
- wire \s_txdat[110]_i_1__0_n_0 ;
- wire \s_txdat[111]_i_1__0_n_0 ;
- wire \s_txdat[112]_i_1__0_n_0 ;
- wire \s_txdat[113]_i_1__0_n_0 ;
- wire \s_txdat[114]_i_1__0_n_0 ;
- wire \s_txdat[115]_i_1__0_n_0 ;
- wire \s_txdat[116]_i_1__0_n_0 ;
- wire \s_txdat[117]_i_1__0_n_0 ;
- wire \s_txdat[118]_i_1__0_n_0 ;
- wire \s_txdat[119]_i_2__0_n_0 ;
- wire \s_txdat[119]_i_3__0_n_0 ;
- wire \s_txdat[119]_i_4__0_n_0 ;
- wire \s_txdat[119]_i_5__0_n_0 ;
- wire \s_txdat[11]_i_1__0_n_0 ;
- wire \s_txdat[12]_i_1__0_n_0 ;
- wire \s_txdat[13]_i_1__0_n_0 ;
- wire \s_txdat[14]_i_1__0_n_0 ;
- wire \s_txdat[15]_i_1__0_n_0 ;
- wire \s_txdat[16]_i_1__0_n_0 ;
- wire \s_txdat[17]_i_1__0_n_0 ;
- wire \s_txdat[18]_i_1__0_n_0 ;
- wire \s_txdat[19]_i_1__0_n_0 ;
- wire \s_txdat[20]_i_1__0_n_0 ;
- wire \s_txdat[21]_i_1__0_n_0 ;
- wire \s_txdat[22]_i_1__0_n_0 ;
- wire \s_txdat[23]_i_1__0_n_0 ;
- wire \s_txdat[24]_i_1__0_n_0 ;
- wire \s_txdat[25]_i_1__0_n_0 ;
- wire \s_txdat[26]_i_1__0_n_0 ;
- wire \s_txdat[27]_i_1__0_n_0 ;
- wire \s_txdat[28]_i_1__0_n_0 ;
- wire \s_txdat[29]_i_1__0_n_0 ;
- wire \s_txdat[30]_i_1__0_n_0 ;
- wire \s_txdat[31]_i_1__0_n_0 ;
- wire \s_txdat[32]_i_1__0_n_0 ;
- wire \s_txdat[33]_i_1__0_n_0 ;
- wire \s_txdat[34]_i_1__0_n_0 ;
- wire \s_txdat[35]_i_1__0_n_0 ;
- wire \s_txdat[36]_i_1__0_n_0 ;
- wire \s_txdat[37]_i_1__0_n_0 ;
- wire \s_txdat[38]_i_1__0_n_0 ;
- wire \s_txdat[39]_i_1__0_n_0 ;
- wire \s_txdat[40]_i_1__0_n_0 ;
- wire \s_txdat[41]_i_1__0_n_0 ;
- wire \s_txdat[42]_i_1__0_n_0 ;
- wire \s_txdat[43]_i_1__0_n_0 ;
- wire \s_txdat[44]_i_1__0_n_0 ;
- wire \s_txdat[45]_i_1__0_n_0 ;
- wire \s_txdat[46]_i_1__0_n_0 ;
- wire \s_txdat[47]_i_1__0_n_0 ;
- wire \s_txdat[48]_i_1__0_n_0 ;
- wire \s_txdat[49]_i_1__0_n_0 ;
- wire \s_txdat[4]_i_1__0_n_0 ;
- wire \s_txdat[50]_i_1__0_n_0 ;
- wire \s_txdat[51]_i_1__0_n_0 ;
- wire \s_txdat[52]_i_1__0_n_0 ;
- wire \s_txdat[53]_i_1__0_n_0 ;
- wire \s_txdat[54]_i_1__0_n_0 ;
- wire \s_txdat[55]_i_1__0_n_0 ;
- wire \s_txdat[56]_i_1__0_n_0 ;
- wire \s_txdat[57]_i_1__0_n_0 ;
- wire \s_txdat[58]_i_1__0_n_0 ;
- wire \s_txdat[59]_i_1__0_n_0 ;
- wire \s_txdat[5]_i_1__0_n_0 ;
- wire \s_txdat[60]_i_1__0_n_0 ;
- wire \s_txdat[61]_i_1__0_n_0 ;
- wire \s_txdat[62]_i_1__0_n_0 ;
- wire \s_txdat[63]_i_1__0_n_0 ;
- wire \s_txdat[64]_i_1__0_n_0 ;
- wire \s_txdat[65]_i_1__0_n_0 ;
- wire \s_txdat[66]_i_1__0_n_0 ;
- wire \s_txdat[67]_i_1__0_n_0 ;
- wire \s_txdat[68]_i_1__0_n_0 ;
- wire \s_txdat[69]_i_1__0_n_0 ;
- wire \s_txdat[6]_i_1__0_n_0 ;
- wire \s_txdat[70]_i_1__0_n_0 ;
- wire \s_txdat[71]_i_1__0_n_0 ;
- wire \s_txdat[72]_i_1__0_n_0 ;
- wire \s_txdat[73]_i_1__0_n_0 ;
- wire \s_txdat[74]_i_1__0_n_0 ;
- wire \s_txdat[75]_i_1__0_n_0 ;
- wire \s_txdat[76]_i_1__0_n_0 ;
- wire \s_txdat[77]_i_1__0_n_0 ;
- wire \s_txdat[78]_i_1__0_n_0 ;
- wire \s_txdat[79]_i_1__0_n_0 ;
- wire \s_txdat[7]_i_1__0_n_0 ;
- wire \s_txdat[80]_i_1__0_n_0 ;
- wire \s_txdat[81]_i_1__0_n_0 ;
- wire \s_txdat[82]_i_1__0_n_0 ;
- wire \s_txdat[83]_i_1__0_n_0 ;
- wire \s_txdat[84]_i_1__0_n_0 ;
- wire \s_txdat[85]_i_1__0_n_0 ;
- wire \s_txdat[86]_i_1__0_n_0 ;
- wire \s_txdat[87]_i_1__0_n_0 ;
- wire \s_txdat[88]_i_1__0_n_0 ;
- wire \s_txdat[89]_i_1__0_n_0 ;
- wire \s_txdat[8]_i_1__0_n_0 ;
- wire \s_txdat[90]_i_1__0_n_0 ;
- wire \s_txdat[91]_i_1__0_n_0 ;
- wire \s_txdat[92]_i_1__0_n_0 ;
- wire \s_txdat[93]_i_1__0_n_0 ;
- wire \s_txdat[94]_i_1__0_n_0 ;
- wire \s_txdat[95]_i_1__0_n_0 ;
- wire \s_txdat[96]_i_1__0_n_0 ;
- wire \s_txdat[97]_i_1__0_n_0 ;
- wire \s_txdat[98]_i_1__0_n_0 ;
- wire \s_txdat[99]_i_1__0_n_0 ;
- wire \s_txdat[9]_i_1__0_n_0 ;
- wire \s_txdat_reg_n_0_[100] ;
- wire \s_txdat_reg_n_0_[101] ;
- wire \s_txdat_reg_n_0_[102] ;
- wire \s_txdat_reg_n_0_[103] ;
- wire \s_txdat_reg_n_0_[104] ;
- wire \s_txdat_reg_n_0_[105] ;
- wire \s_txdat_reg_n_0_[106] ;
- wire \s_txdat_reg_n_0_[107] ;
- wire \s_txdat_reg_n_0_[108] ;
- wire \s_txdat_reg_n_0_[109] ;
- wire \s_txdat_reg_n_0_[10] ;
- wire \s_txdat_reg_n_0_[110] ;
- wire \s_txdat_reg_n_0_[111] ;
- wire \s_txdat_reg_n_0_[112] ;
- wire \s_txdat_reg_n_0_[113] ;
- wire \s_txdat_reg_n_0_[114] ;
- wire \s_txdat_reg_n_0_[115] ;
- wire \s_txdat_reg_n_0_[116] ;
- wire \s_txdat_reg_n_0_[117] ;
- wire \s_txdat_reg_n_0_[118] ;
- wire \s_txdat_reg_n_0_[11] ;
- wire \s_txdat_reg_n_0_[12] ;
- wire \s_txdat_reg_n_0_[13] ;
- wire \s_txdat_reg_n_0_[14] ;
- wire \s_txdat_reg_n_0_[15] ;
- wire \s_txdat_reg_n_0_[16] ;
- wire \s_txdat_reg_n_0_[17] ;
- wire \s_txdat_reg_n_0_[18] ;
- wire \s_txdat_reg_n_0_[19] ;
- wire \s_txdat_reg_n_0_[20] ;
- wire \s_txdat_reg_n_0_[21] ;
- wire \s_txdat_reg_n_0_[22] ;
- wire \s_txdat_reg_n_0_[23] ;
- wire \s_txdat_reg_n_0_[24] ;
- wire \s_txdat_reg_n_0_[25] ;
- wire \s_txdat_reg_n_0_[26] ;
- wire \s_txdat_reg_n_0_[27] ;
- wire \s_txdat_reg_n_0_[28] ;
- wire \s_txdat_reg_n_0_[29] ;
- wire \s_txdat_reg_n_0_[30] ;
- wire \s_txdat_reg_n_0_[31] ;
- wire \s_txdat_reg_n_0_[32] ;
- wire \s_txdat_reg_n_0_[33] ;
- wire \s_txdat_reg_n_0_[34] ;
- wire \s_txdat_reg_n_0_[35] ;
- wire \s_txdat_reg_n_0_[36] ;
- wire \s_txdat_reg_n_0_[37] ;
- wire \s_txdat_reg_n_0_[38] ;
- wire \s_txdat_reg_n_0_[39] ;
- wire \s_txdat_reg_n_0_[40] ;
- wire \s_txdat_reg_n_0_[41] ;
- wire \s_txdat_reg_n_0_[42] ;
- wire \s_txdat_reg_n_0_[43] ;
- wire \s_txdat_reg_n_0_[44] ;
- wire \s_txdat_reg_n_0_[45] ;
- wire \s_txdat_reg_n_0_[46] ;
- wire \s_txdat_reg_n_0_[47] ;
- wire \s_txdat_reg_n_0_[48] ;
- wire \s_txdat_reg_n_0_[49] ;
- wire \s_txdat_reg_n_0_[4] ;
- wire \s_txdat_reg_n_0_[50] ;
- wire \s_txdat_reg_n_0_[51] ;
- wire \s_txdat_reg_n_0_[52] ;
- wire \s_txdat_reg_n_0_[53] ;
- wire \s_txdat_reg_n_0_[54] ;
- wire \s_txdat_reg_n_0_[55] ;
- wire \s_txdat_reg_n_0_[56] ;
- wire \s_txdat_reg_n_0_[57] ;
- wire \s_txdat_reg_n_0_[58] ;
- wire \s_txdat_reg_n_0_[59] ;
- wire \s_txdat_reg_n_0_[5] ;
- wire \s_txdat_reg_n_0_[60] ;
- wire \s_txdat_reg_n_0_[61] ;
- wire \s_txdat_reg_n_0_[62] ;
- wire \s_txdat_reg_n_0_[63] ;
- wire \s_txdat_reg_n_0_[64] ;
- wire \s_txdat_reg_n_0_[65] ;
- wire \s_txdat_reg_n_0_[66] ;
- wire \s_txdat_reg_n_0_[67] ;
- wire \s_txdat_reg_n_0_[68] ;
- wire \s_txdat_reg_n_0_[69] ;
- wire \s_txdat_reg_n_0_[6] ;
- wire \s_txdat_reg_n_0_[70] ;
- wire \s_txdat_reg_n_0_[71] ;
- wire \s_txdat_reg_n_0_[72] ;
- wire \s_txdat_reg_n_0_[73] ;
- wire \s_txdat_reg_n_0_[74] ;
- wire \s_txdat_reg_n_0_[75] ;
- wire \s_txdat_reg_n_0_[76] ;
- wire \s_txdat_reg_n_0_[77] ;
- wire \s_txdat_reg_n_0_[78] ;
- wire \s_txdat_reg_n_0_[79] ;
- wire \s_txdat_reg_n_0_[7] ;
- wire \s_txdat_reg_n_0_[80] ;
- wire \s_txdat_reg_n_0_[81] ;
- wire \s_txdat_reg_n_0_[82] ;
- wire \s_txdat_reg_n_0_[83] ;
- wire \s_txdat_reg_n_0_[84] ;
- wire \s_txdat_reg_n_0_[85] ;
- wire \s_txdat_reg_n_0_[86] ;
- wire \s_txdat_reg_n_0_[87] ;
- wire \s_txdat_reg_n_0_[88] ;
- wire \s_txdat_reg_n_0_[89] ;
- wire \s_txdat_reg_n_0_[8] ;
- wire \s_txdat_reg_n_0_[90] ;
- wire \s_txdat_reg_n_0_[91] ;
- wire \s_txdat_reg_n_0_[92] ;
- wire \s_txdat_reg_n_0_[93] ;
- wire \s_txdat_reg_n_0_[94] ;
- wire \s_txdat_reg_n_0_[95] ;
- wire \s_txdat_reg_n_0_[96] ;
- wire \s_txdat_reg_n_0_[97] ;
- wire \s_txdat_reg_n_0_[98] ;
- wire \s_txdat_reg_n_0_[99] ;
- wire \s_txdat_reg_n_0_[9] ;
- wire v_ch_address;
- wire \v_ch_address_reg[0] ;
- wire \v_ch_address_reg[0]_0 ;
- wire \v_ch_address_reg[1] ;
- wire v_cnt;
- wire \v_cnt[0]_i_1__0_n_0 ;
- wire \v_cnt[1]_i_1__0_n_0 ;
- wire \v_cnt[2]_i_1__0_n_0 ;
- wire \v_cnt[3]_i_1__0_n_0 ;
- wire \v_cnt[4]_i_1__0_n_0 ;
- wire \v_cnt[5]_i_1__0_n_0 ;
- wire \v_cnt[6]_i_2__0_n_0 ;
- wire \v_cnt[6]_i_3__0_n_0 ;
- wire \v_cnt[6]_i_4__0_n_0 ;
- wire \v_cnt[6]_i_5__0_n_0 ;
- wire \v_cnt_reg_n_0_[0] ;
- wire \v_cnt_reg_n_0_[1] ;
- wire \v_cnt_reg_n_0_[2] ;
- wire \v_cnt_reg_n_0_[3] ;
- wire \v_cnt_reg_n_0_[4] ;
- wire \v_cnt_reg_n_0_[5] ;
- wire \v_cnt_reg_n_0_[6] ;
-
- LUT3 #(
- .INIT(8'hB8))
- \FSM_sequential_s_state[0]_i_1__0
- (.I0(\FSM_sequential_s_state[0]_i_2__0_n_0 ),
- .I1(\FSM_sequential_s_state[2]_i_2__0_n_0 ),
- .I2(s_state[0]),
- .O(\FSM_sequential_s_state[0]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'hFFFEFF00FFFFFF00))
- \FSM_sequential_s_state[0]_i_2__0
- (.I0(\v_cnt_reg_n_0_[0] ),
- .I1(\v_cnt_reg_n_0_[1] ),
- .I2(\v_cnt_reg_n_0_[2] ),
- .I3(\FSM_sequential_s_state[0]_i_3__0_n_0 ),
- .I4(s_state[1]),
- .I5(\v_cnt_reg_n_0_[3] ),
- .O(\FSM_sequential_s_state[0]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'h77C3FFC3FFC3FFC3))
- \FSM_sequential_s_state[0]_i_3__0
- (.I0(\v_cnt_reg_n_0_[4] ),
- .I1(s_state[0]),
- .I2(s_state[2]),
- .I3(s_state[1]),
- .I4(\v_cnt_reg_n_0_[6] ),
- .I5(\v_cnt_reg_n_0_[5] ),
- .O(\FSM_sequential_s_state[0]_i_3__0_n_0 ));
- LUT4 #(
- .INIT(16'h6F60))
- \FSM_sequential_s_state[1]_i_1__0
- (.I0(s_state[0]),
- .I1(s_state[1]),
- .I2(\FSM_sequential_s_state[2]_i_2__0_n_0 ),
- .I3(s_state[1]),
- .O(\FSM_sequential_s_state[1]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h8F80))
- \FSM_sequential_s_state[2]_i_1__0
- (.I0(s_state[1]),
- .I1(s_state[0]),
- .I2(\FSM_sequential_s_state[2]_i_2__0_n_0 ),
- .I3(s_state[2]),
- .O(\FSM_sequential_s_state[2]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'hABEEAAAAAAEEAAAA))
- \FSM_sequential_s_state[2]_i_2__0
- (.I0(\FSM_sequential_s_state[2]_i_3__0_n_0 ),
- .I1(s_state[0]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .I4(\s_txdat[119]_i_3__0_n_0 ),
- .I5(\FSM_sequential_s_state[2]_i_4__0_n_0 ),
- .O(\FSM_sequential_s_state[2]_i_2__0_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF0010))
- \FSM_sequential_s_state[2]_i_3__0
- (.I0(s_state[1]),
- .I1(s_state[2]),
- .I2(s_start_reg),
- .I3(s_state[0]),
- .I4(s_rxdat_0),
- .O(\FSM_sequential_s_state[2]_i_3__0_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair48" *)
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \FSM_sequential_s_state[2]_i_4__0
- (.I0(\v_cnt_reg_n_0_[2] ),
- .I1(\v_cnt_reg_n_0_[5] ),
- .I2(\v_cnt_reg_n_0_[6] ),
- .I3(\v_cnt_reg_n_0_[4] ),
- .I4(\v_cnt_reg_n_0_[3] ),
- .O(\FSM_sequential_s_state[2]_i_4__0_n_0 ));
- (* KEEP = "yes" *)
- FDRE \FSM_sequential_s_state_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\FSM_sequential_s_state[0]_i_1__0_n_0 ),
- .Q(s_state[0]),
- .R(rst_i));
- (* KEEP = "yes" *)
- FDRE \FSM_sequential_s_state_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\FSM_sequential_s_state[1]_i_1__0_n_0 ),
- .Q(s_state[1]),
- .R(rst_i));
- (* KEEP = "yes" *)
- FDRE \FSM_sequential_s_state_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\FSM_sequential_s_state[2]_i_1__0_n_0 ),
- .Q(s_state[2]),
- .R(rst_i));
- LUT6 #(
- .INIT(64'h0000000002000000))
- \dac_ch_o[0][31]_i_1__0
- (.I0(\s_state_reg[1]_0 ),
- .I1(s_state[1]),
- .I2(s_state[0]),
- .I3(s00_axi_aresetn),
- .I4(\s_state_reg[0]_0 ),
- .I5(\v_ch_address_reg[0]_0 ),
- .O(E));
- LUT3 #(
- .INIT(8'h07))
- \gen_spi.cmp_spi_cs_n_iobuf_i_1__0
- (.I0(s_state[0]),
- .I1(s_state[2]),
- .I2(s_state[1]),
- .O(s_spi_cs_n));
- LUT4 #(
- .INIT(16'h2B3B))
- \gen_spi.cmp_spi_mosi_iobuf_i_1__0
- (.I0(p_0_in),
- .I1(s_state[1]),
- .I2(s_state[2]),
- .I3(s_state[0]),
- .O(s_spi_mosi));
- LUT4 #(
- .INIT(16'h0002))
- \rx_data_o[31]_i_1__0
- (.I0(s00_axi_aresetn),
- .I1(s_state[0]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\rx_data_o[31]_i_1__0_n_0 ));
- FDRE \rx_data_o_reg[0]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[0]),
- .Q(\dac_ch_o_reg[0][31] [0]),
- .R(1'b0));
- FDRE \rx_data_o_reg[10]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[10]),
- .Q(\dac_ch_o_reg[0][31] [10]),
- .R(1'b0));
- FDRE \rx_data_o_reg[11]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[11]),
- .Q(\dac_ch_o_reg[0][31] [11]),
- .R(1'b0));
- FDRE \rx_data_o_reg[12]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[12]),
- .Q(\dac_ch_o_reg[0][31] [12]),
- .R(1'b0));
- FDRE \rx_data_o_reg[13]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[13]),
- .Q(\dac_ch_o_reg[0][31] [13]),
- .R(1'b0));
- FDRE \rx_data_o_reg[14]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[14]),
- .Q(\dac_ch_o_reg[0][31] [14]),
- .R(1'b0));
- FDRE \rx_data_o_reg[15]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[15]),
- .Q(\dac_ch_o_reg[0][31] [15]),
- .R(1'b0));
- FDRE \rx_data_o_reg[16]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[16]),
- .Q(\dac_ch_o_reg[0][31] [16]),
- .R(1'b0));
- FDRE \rx_data_o_reg[17]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[17]),
- .Q(\dac_ch_o_reg[0][31] [17]),
- .R(1'b0));
- FDRE \rx_data_o_reg[18]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[18]),
- .Q(\dac_ch_o_reg[0][31] [18]),
- .R(1'b0));
- FDRE \rx_data_o_reg[19]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[19]),
- .Q(\dac_ch_o_reg[0][31] [19]),
- .R(1'b0));
- FDRE \rx_data_o_reg[1]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[1]),
- .Q(\dac_ch_o_reg[0][31] [1]),
- .R(1'b0));
- FDRE \rx_data_o_reg[20]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[20]),
- .Q(\dac_ch_o_reg[0][31] [20]),
- .R(1'b0));
- FDRE \rx_data_o_reg[21]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[21]),
- .Q(\dac_ch_o_reg[0][31] [21]),
- .R(1'b0));
- FDRE \rx_data_o_reg[22]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[22]),
- .Q(\dac_ch_o_reg[0][31] [22]),
- .R(1'b0));
- FDRE \rx_data_o_reg[23]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[23]),
- .Q(\dac_ch_o_reg[0][31] [23]),
- .R(1'b0));
- FDRE \rx_data_o_reg[24]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[24]),
- .Q(\dac_ch_o_reg[0][31] [24]),
- .R(1'b0));
- FDRE \rx_data_o_reg[25]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[25]),
- .Q(\dac_ch_o_reg[0][31] [25]),
- .R(1'b0));
- FDRE \rx_data_o_reg[26]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[26]),
- .Q(\dac_ch_o_reg[0][31] [26]),
- .R(1'b0));
- FDRE \rx_data_o_reg[27]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[27]),
- .Q(\dac_ch_o_reg[0][31] [27]),
- .R(1'b0));
- FDRE \rx_data_o_reg[28]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[28]),
- .Q(\dac_ch_o_reg[0][31] [28]),
- .R(1'b0));
- FDRE \rx_data_o_reg[29]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[29]),
- .Q(\dac_ch_o_reg[0][31] [29]),
- .R(1'b0));
- FDRE \rx_data_o_reg[2]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[2]),
- .Q(\dac_ch_o_reg[0][31] [2]),
- .R(1'b0));
- FDRE \rx_data_o_reg[30]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[30]),
- .Q(\dac_ch_o_reg[0][31] [30]),
- .R(1'b0));
- FDRE \rx_data_o_reg[31]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[31]),
- .Q(\dac_ch_o_reg[0][31] [31]),
- .R(1'b0));
- FDRE \rx_data_o_reg[3]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[3]),
- .Q(\dac_ch_o_reg[0][31] [3]),
- .R(1'b0));
- FDRE \rx_data_o_reg[4]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[4]),
- .Q(\dac_ch_o_reg[0][31] [4]),
- .R(1'b0));
- FDRE \rx_data_o_reg[5]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[5]),
- .Q(\dac_ch_o_reg[0][31] [5]),
- .R(1'b0));
- FDRE \rx_data_o_reg[6]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[6]),
- .Q(\dac_ch_o_reg[0][31] [6]),
- .R(1'b0));
- FDRE \rx_data_o_reg[7]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[7]),
- .Q(\dac_ch_o_reg[0][31] [7]),
- .R(1'b0));
- FDRE \rx_data_o_reg[8]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[8]),
- .Q(\dac_ch_o_reg[0][31] [8]),
- .R(1'b0));
- FDRE \rx_data_o_reg[9]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1__0_n_0 ),
- .D(s_rxdat[9]),
- .Q(\dac_ch_o_reg[0][31] [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair52" *)
- LUT1 #(
- .INIT(2'h1))
- \s_counter[0]_i_1__0
- (.I0(s_counter[0]),
- .O(\s_counter[0]_i_1__0_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair52" *)
- LUT2 #(
- .INIT(4'h6))
- \s_counter[1]_i_1__0
- (.I0(s_counter[0]),
- .I1(s_counter[1]),
- .O(\s_counter[1]_i_1__0_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair51" *)
- LUT3 #(
- .INIT(8'h6A))
- \s_counter[2]_i_1__0
- (.I0(Q),
- .I1(s_counter[0]),
- .I2(s_counter[1]),
- .O(\s_counter[2]_i_1__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \s_counter_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_counter[0]_i_1__0_n_0 ),
- .Q(s_counter[0]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_counter_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_counter[1]_i_1__0_n_0 ),
- .Q(s_counter[1]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_counter_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_counter[2]_i_1__0_n_0 ),
- .Q(Q),
- .R(rst_i));
- LUT6 #(
- .INIT(64'h2400000000000000))
- \s_rxdat[31]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(s_state[0]),
- .I3(s_counter[0]),
- .I4(s_counter[1]),
- .I5(Q),
- .O(s_rxdat_0));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(D),
- .Q(s_rxdat[0]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[9]),
- .Q(s_rxdat[10]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[10]),
- .Q(s_rxdat[11]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[11]),
- .Q(s_rxdat[12]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[12]),
- .Q(s_rxdat[13]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[13]),
- .Q(s_rxdat[14]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[14]),
- .Q(s_rxdat[15]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[15]),
- .Q(s_rxdat[16]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[16]),
- .Q(s_rxdat[17]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[17]),
- .Q(s_rxdat[18]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[18]),
- .Q(s_rxdat[19]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[0]),
- .Q(s_rxdat[1]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[19]),
- .Q(s_rxdat[20]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[20]),
- .Q(s_rxdat[21]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[21]),
- .Q(s_rxdat[22]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[22]),
- .Q(s_rxdat[23]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[24]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[23]),
- .Q(s_rxdat[24]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[25]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[24]),
- .Q(s_rxdat[25]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[26]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[25]),
- .Q(s_rxdat[26]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[27]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[26]),
- .Q(s_rxdat[27]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[28]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[27]),
- .Q(s_rxdat[28]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[29]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[28]),
- .Q(s_rxdat[29]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[1]),
- .Q(s_rxdat[2]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[30]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[29]),
- .Q(s_rxdat[30]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[31]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[30]),
- .Q(s_rxdat[31]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[2]),
- .Q(s_rxdat[3]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[3]),
- .Q(s_rxdat[4]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[4]),
- .Q(s_rxdat[5]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[5]),
- .Q(s_rxdat[6]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[6]),
- .Q(s_rxdat[7]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[7]),
- .Q(s_rxdat[8]),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[8]),
- .Q(s_rxdat[9]),
- .R(rst_i));
- LUT5 #(
- .INIT(32'h2AFFFF00))
- \s_state[0]_i_1__0
- (.I0(\s_state_reg[1]_0 ),
- .I1(ch_address[0]),
- .I2(ch_address[1]),
- .I3(\s_state[0]_i_2__0_n_0 ),
- .I4(\s_state_reg[0]_0 ),
- .O(\s_state_reg[0] ));
- LUT6 #(
- .INIT(64'hFAFFAFFAFABFAFBA))
- \s_state[0]_i_2__0
- (.I0(\[0].[3].s_reqs_reg[3][changed] ),
- .I1(\v_ch_address_reg[0]_0 ),
- .I2(\s_state_reg[0]_0 ),
- .I3(\s_state_reg[1]_0 ),
- .I4(s_done),
- .I5(\[0].[2].s_reqs_reg[2][changed] ),
- .O(\s_state[0]_i_2__0_n_0 ));
- LUT5 #(
- .INIT(32'hFDFFFCF0))
- \s_state[1]_i_1__0
- (.I0(\s_state_reg[0]_0 ),
- .I1(\[0].[2].s_reqs_reg[2][changed]_0 ),
- .I2(\[0].[3].s_reqs_reg[3][changed] ),
- .I3(\s_state[1]_i_4__0_n_0 ),
- .I4(\s_state_reg[1]_0 ),
- .O(\s_state_reg[1] ));
- LUT6 #(
- .INIT(64'hCF3CCA3CCA3CCA3C))
- \s_state[1]_i_4__0
- (.I0(\[0].[2].s_reqs_reg[2][changed] ),
- .I1(s_done),
- .I2(\s_state_reg[1]_0 ),
- .I3(\s_state_reg[0]_0 ),
- .I4(ch_address[1]),
- .I5(ch_address[0]),
- .O(\s_state[1]_i_4__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[100]_i_1__0
- (.I0(\s_txdat_reg_n_0_[99] ),
- .I1(\s_tx_data_reg[113] [48]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[100]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[101]_i_1__0
- (.I0(\s_txdat_reg_n_0_[100] ),
- .I1(\s_tx_data_reg[113] [49]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[101]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[102]_i_1__0
- (.I0(\s_txdat_reg_n_0_[101] ),
- .I1(\s_tx_data_reg[113] [50]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[102]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[103]_i_1__0
- (.I0(\s_txdat_reg_n_0_[102] ),
- .I1(\s_tx_data_reg[113] [51]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[103]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[104]_i_1__0
- (.I0(\s_txdat_reg_n_0_[103] ),
- .I1(\s_tx_data_reg[113] [52]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[104]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[105]_i_1__0
- (.I0(\s_txdat_reg_n_0_[104] ),
- .I1(\s_tx_data_reg[113] [53]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[105]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[106]_i_1__0
- (.I0(\s_txdat_reg_n_0_[105] ),
- .I1(\s_tx_data_reg[113] [54]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[106]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[107]_i_1__0
- (.I0(\s_txdat_reg_n_0_[106] ),
- .I1(\s_tx_data_reg[113] [55]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[107]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[108]_i_1__0
- (.I0(\s_txdat_reg_n_0_[107] ),
- .I1(\s_tx_data_reg[113] [56]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[108]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[109]_i_1__0
- (.I0(\s_txdat_reg_n_0_[108] ),
- .I1(\s_tx_data_reg[113] [57]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[109]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[10]_i_1__0
- (.I0(\s_txdat_reg_n_0_[9] ),
- .I1(\s_tx_data_reg[113] [6]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[10]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[110]_i_1__0
- (.I0(\s_txdat_reg_n_0_[109] ),
- .I1(\s_tx_data_reg[113] [58]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[110]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[111]_i_1__0
- (.I0(\s_txdat_reg_n_0_[110] ),
- .I1(\s_tx_data_reg[113] [59]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[111]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[112]_i_1__0
- (.I0(\s_txdat_reg_n_0_[111] ),
- .I1(\s_tx_data_reg[113] [60]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[112]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[113]_i_1__0
- (.I0(\s_txdat_reg_n_0_[112] ),
- .I1(\s_tx_data_reg[113] [61]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[113]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h23))
- \s_txdat[114]_i_1__0
- (.I0(\s_txdat_reg_n_0_[113] ),
- .I1(s_state[2]),
- .I2(s_state[1]),
- .O(\s_txdat[114]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[115]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[114] ),
- .O(\s_txdat[115]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[116]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[115] ),
- .O(\s_txdat[116]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[117]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[116] ),
- .O(\s_txdat[117]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[118]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[117] ),
- .O(\s_txdat[118]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h00800080000F0000))
- \s_txdat[119]_i_1__0
- (.I0(\s_txdat[119]_i_3__0_n_0 ),
- .I1(\s_txdat[119]_i_4__0_n_0 ),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .I4(s_start_reg),
- .I5(s_state[0]),
- .O(s_txdat));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[119]_i_2__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[118] ),
- .O(\s_txdat[119]_i_2__0_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair51" *)
- LUT3 #(
- .INIT(8'h08))
- \s_txdat[119]_i_3__0
- (.I0(s_counter[1]),
- .I1(s_counter[0]),
- .I2(Q),
- .O(\s_txdat[119]_i_3__0_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair49" *)
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- \s_txdat[119]_i_4__0
- (.I0(\v_cnt_reg_n_0_[2] ),
- .I1(\v_cnt_reg_n_0_[6] ),
- .I2(\v_cnt_reg_n_0_[0] ),
- .I3(\v_cnt_reg_n_0_[1] ),
- .I4(\s_txdat[119]_i_5__0_n_0 ),
- .O(\s_txdat[119]_i_4__0_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair48" *)
- LUT3 #(
- .INIT(8'h7F))
- \s_txdat[119]_i_5__0
- (.I0(\v_cnt_reg_n_0_[4] ),
- .I1(\v_cnt_reg_n_0_[3] ),
- .I2(\v_cnt_reg_n_0_[5] ),
- .O(\s_txdat[119]_i_5__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[11]_i_1__0
- (.I0(\s_txdat_reg_n_0_[10] ),
- .I1(\s_tx_data_reg[113] [7]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[11]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[12]_i_1__0
- (.I0(\s_txdat_reg_n_0_[11] ),
- .I1(\s_tx_data_reg[113] [8]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[12]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[13]_i_1__0
- (.I0(\s_txdat_reg_n_0_[12] ),
- .I1(\s_tx_data_reg[113] [9]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[13]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[14]_i_1__0
- (.I0(\s_txdat_reg_n_0_[13] ),
- .I1(\s_tx_data_reg[113] [10]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[14]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[15]_i_1__0
- (.I0(\s_txdat_reg_n_0_[14] ),
- .I1(\s_tx_data_reg[113] [11]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[15]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[16]_i_1__0
- (.I0(\s_txdat_reg_n_0_[15] ),
- .I1(\s_tx_data_reg[113] [60]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[16]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[17]_i_1__0
- (.I0(\s_txdat_reg_n_0_[16] ),
- .I1(\s_tx_data_reg[113] [61]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[17]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h23))
- \s_txdat[18]_i_1__0
- (.I0(\s_txdat_reg_n_0_[17] ),
- .I1(s_state[2]),
- .I2(s_state[1]),
- .O(\s_txdat[18]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[19]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[18] ),
- .O(\s_txdat[19]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[20]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[19] ),
- .O(\s_txdat[20]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[21]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[20] ),
- .O(\s_txdat[21]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[22]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[21] ),
- .O(\s_txdat[22]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[23]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[22] ),
- .O(\s_txdat[23]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[24]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[23] ),
- .O(\s_txdat[24]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[25]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[24] ),
- .O(\s_txdat[25]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[26]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[25] ),
- .O(\s_txdat[26]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[27]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[26] ),
- .O(\s_txdat[27]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[28]_i_1__0
- (.I0(\s_txdat_reg_n_0_[27] ),
- .I1(\s_tx_data_reg[113] [12]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[28]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[29]_i_1__0
- (.I0(\s_txdat_reg_n_0_[28] ),
- .I1(\s_tx_data_reg[113] [13]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[29]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[30]_i_1__0
- (.I0(\s_txdat_reg_n_0_[29] ),
- .I1(\s_tx_data_reg[113] [14]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[30]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[31]_i_1__0
- (.I0(\s_txdat_reg_n_0_[30] ),
- .I1(\s_tx_data_reg[113] [15]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[31]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[32]_i_1__0
- (.I0(\s_txdat_reg_n_0_[31] ),
- .I1(\s_tx_data_reg[113] [16]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[32]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[33]_i_1__0
- (.I0(\s_txdat_reg_n_0_[32] ),
- .I1(\s_tx_data_reg[113] [17]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[33]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[34]_i_1__0
- (.I0(\s_txdat_reg_n_0_[33] ),
- .I1(\s_tx_data_reg[113] [18]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[34]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[35]_i_1__0
- (.I0(\s_txdat_reg_n_0_[34] ),
- .I1(\s_tx_data_reg[113] [19]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[35]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[36]_i_1__0
- (.I0(\s_txdat_reg_n_0_[35] ),
- .I1(\s_tx_data_reg[113] [20]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[36]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[37]_i_1__0
- (.I0(\s_txdat_reg_n_0_[36] ),
- .I1(\s_tx_data_reg[113] [21]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[37]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[38]_i_1__0
- (.I0(\s_txdat_reg_n_0_[37] ),
- .I1(\s_tx_data_reg[113] [22]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[38]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[39]_i_1__0
- (.I0(\s_txdat_reg_n_0_[38] ),
- .I1(\s_tx_data_reg[113] [23]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[39]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[40]_i_1__0
- (.I0(\s_txdat_reg_n_0_[39] ),
- .I1(\s_tx_data_reg[113] [60]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[40]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[41]_i_1__0
- (.I0(\s_txdat_reg_n_0_[40] ),
- .I1(\s_tx_data_reg[113] [61]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[41]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h23))
- \s_txdat[42]_i_1__0
- (.I0(\s_txdat_reg_n_0_[41] ),
- .I1(s_state[2]),
- .I2(s_state[1]),
- .O(\s_txdat[42]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[43]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[42] ),
- .O(\s_txdat[43]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[44]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[43] ),
- .O(\s_txdat[44]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[45]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[44] ),
- .O(\s_txdat[45]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[46]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[45] ),
- .O(\s_txdat[46]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[47]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[46] ),
- .O(\s_txdat[47]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[48]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[47] ),
- .O(\s_txdat[48]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[49]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[48] ),
- .O(\s_txdat[49]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h10))
- \s_txdat[4]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_tx_data_reg[113] [0]),
- .O(\s_txdat[4]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[50]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[49] ),
- .O(\s_txdat[50]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[51]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[50] ),
- .O(\s_txdat[51]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[52]_i_1__0
- (.I0(\s_txdat_reg_n_0_[51] ),
- .I1(\s_tx_data_reg[113] [24]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[52]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[53]_i_1__0
- (.I0(\s_txdat_reg_n_0_[52] ),
- .I1(\s_tx_data_reg[113] [25]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[53]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[54]_i_1__0
- (.I0(\s_txdat_reg_n_0_[53] ),
- .I1(\s_tx_data_reg[113] [26]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[54]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[55]_i_1__0
- (.I0(\s_txdat_reg_n_0_[54] ),
- .I1(\s_tx_data_reg[113] [27]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[55]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[56]_i_1__0
- (.I0(\s_txdat_reg_n_0_[55] ),
- .I1(\s_tx_data_reg[113] [28]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[56]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[57]_i_1__0
- (.I0(\s_txdat_reg_n_0_[56] ),
- .I1(\s_tx_data_reg[113] [29]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[57]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[58]_i_1__0
- (.I0(\s_txdat_reg_n_0_[57] ),
- .I1(\s_tx_data_reg[113] [30]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[58]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[59]_i_1__0
- (.I0(\s_txdat_reg_n_0_[58] ),
- .I1(\s_tx_data_reg[113] [31]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[59]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[5]_i_1__0
- (.I0(\s_txdat_reg_n_0_[4] ),
- .I1(\s_tx_data_reg[113] [1]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[5]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[60]_i_1__0
- (.I0(\s_txdat_reg_n_0_[59] ),
- .I1(\s_tx_data_reg[113] [32]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[60]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[61]_i_1__0
- (.I0(\s_txdat_reg_n_0_[60] ),
- .I1(\s_tx_data_reg[113] [33]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[61]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[62]_i_1__0
- (.I0(\s_txdat_reg_n_0_[61] ),
- .I1(\s_tx_data_reg[113] [34]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[62]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[63]_i_1__0
- (.I0(\s_txdat_reg_n_0_[62] ),
- .I1(\s_tx_data_reg[113] [35]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[63]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[64]_i_1__0
- (.I0(\s_txdat_reg_n_0_[63] ),
- .I1(\s_tx_data_reg[113] [60]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[64]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[65]_i_1__0
- (.I0(\s_txdat_reg_n_0_[64] ),
- .I1(\s_tx_data_reg[113] [61]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[65]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h23))
- \s_txdat[66]_i_1__0
- (.I0(\s_txdat_reg_n_0_[65] ),
- .I1(s_state[2]),
- .I2(s_state[1]),
- .O(\s_txdat[66]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[67]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[66] ),
- .O(\s_txdat[67]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[68]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[67] ),
- .O(\s_txdat[68]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[69]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[68] ),
- .O(\s_txdat[69]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[6]_i_1__0
- (.I0(\s_txdat_reg_n_0_[5] ),
- .I1(\s_tx_data_reg[113] [2]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[6]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[70]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[69] ),
- .O(\s_txdat[70]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[71]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[70] ),
- .O(\s_txdat[71]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[72]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[71] ),
- .O(\s_txdat[72]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[73]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[72] ),
- .O(\s_txdat[73]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[74]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[73] ),
- .O(\s_txdat[74]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[75]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[74] ),
- .O(\s_txdat[75]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[76]_i_1__0
- (.I0(\s_txdat_reg_n_0_[75] ),
- .I1(\s_tx_data_reg[113] [36]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[76]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[77]_i_1__0
- (.I0(\s_txdat_reg_n_0_[76] ),
- .I1(\s_tx_data_reg[113] [37]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[77]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[78]_i_1__0
- (.I0(\s_txdat_reg_n_0_[77] ),
- .I1(\s_tx_data_reg[113] [38]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[78]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[79]_i_1__0
- (.I0(\s_txdat_reg_n_0_[78] ),
- .I1(\s_tx_data_reg[113] [39]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[79]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[7]_i_1__0
- (.I0(\s_txdat_reg_n_0_[6] ),
- .I1(\s_tx_data_reg[113] [3]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[7]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[80]_i_1__0
- (.I0(\s_txdat_reg_n_0_[79] ),
- .I1(\s_tx_data_reg[113] [40]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[80]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[81]_i_1__0
- (.I0(\s_txdat_reg_n_0_[80] ),
- .I1(\s_tx_data_reg[113] [41]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[81]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[82]_i_1__0
- (.I0(\s_txdat_reg_n_0_[81] ),
- .I1(\s_tx_data_reg[113] [42]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[82]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[83]_i_1__0
- (.I0(\s_txdat_reg_n_0_[82] ),
- .I1(\s_tx_data_reg[113] [43]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[83]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[84]_i_1__0
- (.I0(\s_txdat_reg_n_0_[83] ),
- .I1(\s_tx_data_reg[113] [44]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[84]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[85]_i_1__0
- (.I0(\s_txdat_reg_n_0_[84] ),
- .I1(\s_tx_data_reg[113] [45]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[85]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[86]_i_1__0
- (.I0(\s_txdat_reg_n_0_[85] ),
- .I1(\s_tx_data_reg[113] [46]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[86]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[87]_i_1__0
- (.I0(\s_txdat_reg_n_0_[86] ),
- .I1(\s_tx_data_reg[113] [47]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[87]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[88]_i_1__0
- (.I0(\s_txdat_reg_n_0_[87] ),
- .I1(\s_tx_data_reg[113] [60]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[88]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[89]_i_1__0
- (.I0(\s_txdat_reg_n_0_[88] ),
- .I1(\s_tx_data_reg[113] [61]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[89]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[8]_i_1__0
- (.I0(\s_txdat_reg_n_0_[7] ),
- .I1(\s_tx_data_reg[113] [4]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[8]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h23))
- \s_txdat[90]_i_1__0
- (.I0(\s_txdat_reg_n_0_[89] ),
- .I1(s_state[2]),
- .I2(s_state[1]),
- .O(\s_txdat[90]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[91]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[90] ),
- .O(\s_txdat[91]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[92]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[91] ),
- .O(\s_txdat[92]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[93]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[92] ),
- .O(\s_txdat[93]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[94]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[93] ),
- .O(\s_txdat[94]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[95]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[94] ),
- .O(\s_txdat[95]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[96]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[95] ),
- .O(\s_txdat[96]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[97]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[96] ),
- .O(\s_txdat[97]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[98]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[97] ),
- .O(\s_txdat[98]_i_1__0_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[99]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[98] ),
- .O(\s_txdat[99]_i_1__0_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[9]_i_1__0
- (.I0(\s_txdat_reg_n_0_[8] ),
- .I1(\s_tx_data_reg[113] [5]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[9]_i_1__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[100]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[100]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[100] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[101]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[101]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[101] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[102]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[102]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[102] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[103]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[103]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[103] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[104]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[104]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[104] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[105]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[105]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[105] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[106]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[106]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[106] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[107]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[107]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[107] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[108]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[108]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[108] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[109]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[109]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[109] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[10]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[10] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[110]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[110]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[110] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[111]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[111]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[111] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[112]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[112]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[112] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[113]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[113]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[113] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[114]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[114]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[114] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[115]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[115]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[115] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[116]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[116]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[116] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[117]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[117]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[117] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[118]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[118]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[118] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[119]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[119]_i_2__0_n_0 ),
- .Q(p_0_in),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[11]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[11] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[12]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[12] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[13]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[13] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[14]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[14] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[15]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[15] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[16]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[16] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[17]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[17] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[18]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[18] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[19]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[19] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[20]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[20] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[21]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[21] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[22]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[22] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[23]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[23] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[24]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[24]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[24] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[25]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[25]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[25] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[26]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[26]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[26] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[27]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[27]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[27] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[28]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[28]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[28] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[29]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[29]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[29] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[30]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[30]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[30] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[31]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[31]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[31] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[32]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[32]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[32] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[33]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[33]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[33] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[34]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[34]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[34] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[35]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[35]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[35] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[36]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[36]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[36] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[37]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[37]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[37] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[38]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[38]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[38] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[39]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[39]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[39] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[40]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[40]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[40] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[41]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[41]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[41] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[42]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[42]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[42] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[43]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[43]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[43] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[44]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[44]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[44] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[45]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[45]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[45] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[46]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[46]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[46] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[47]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[47]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[47] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[48]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[48]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[48] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[49]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[49]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[49] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[4]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[4] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[50]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[50]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[50] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[51]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[51]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[51] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[52]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[52]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[52] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[53]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[53]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[53] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[54]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[54]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[54] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[55]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[55]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[55] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[56]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[56]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[56] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[57]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[57]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[57] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[58]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[58]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[58] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[59]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[59]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[59] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[5]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[5] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[60]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[60]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[60] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[61]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[61]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[61] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[62]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[62]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[62] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[63]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[63]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[63] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[64]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[64]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[64] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[65]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[65]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[65] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[66]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[66]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[66] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[67]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[67]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[67] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[68]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[68]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[68] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[69]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[69]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[69] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[6]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[6] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[70]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[70]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[70] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[71]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[71]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[71] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[72]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[72]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[72] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[73]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[73]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[73] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[74]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[74]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[74] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[75]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[75]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[75] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[76]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[76]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[76] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[77]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[77]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[77] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[78]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[78]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[78] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[79]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[79]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[79] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[7]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[7] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[80]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[80]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[80] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[81]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[81]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[81] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[82]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[82]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[82] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[83]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[83]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[83] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[84]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[84]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[84] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[85]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[85]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[85] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[86]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[86]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[86] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[87]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[87]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[87] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[88]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[88]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[88] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[89]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[89]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[89] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[8]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[8] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[90]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[90]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[90] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[91]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[91]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[91] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[92]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[92]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[92] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[93]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[93]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[93] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[94]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[94]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[94] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[95]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[95]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[95] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[96]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[96]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[96] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[97]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[97]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[97] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[98]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[98]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[98] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[99]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[99]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[99] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[9]_i_1__0_n_0 ),
- .Q(\s_txdat_reg_n_0_[9] ),
- .R(rst_i));
- (* SOFT_HLUTNM = "soft_lutpair50" *)
- LUT3 #(
- .INIT(8'h38))
- \v_ch_address[0]_i_1__0
- (.I0(\s_state_reg[0]_0 ),
- .I1(v_ch_address),
- .I2(ch_address[0]),
- .O(\v_ch_address_reg[0] ));
- (* SOFT_HLUTNM = "soft_lutpair50" *)
- LUT4 #(
- .INIT(16'h4F80))
- \v_ch_address[1]_i_1__0
- (.I0(ch_address[0]),
- .I1(\s_state_reg[0]_0 ),
- .I2(v_ch_address),
- .I3(ch_address[1]),
- .O(\v_ch_address_reg[1] ));
- LUT6 #(
- .INIT(64'hCA000A000A000A00))
- \v_ch_address[1]_i_2__0
- (.I0(\data_rw_o_reg[79][1] ),
- .I1(\v_ch_address_reg[0]_0 ),
- .I2(\s_state_reg[1]_0 ),
- .I3(s00_axi_aresetn),
- .I4(s_done),
- .I5(\s_state_reg[0]_0 ),
- .O(v_ch_address));
- LUT2 #(
- .INIT(4'h1))
- \v_ch_address[1]_i_4__0
- (.I0(s_state[0]),
- .I1(s_state[1]),
- .O(s_done));
- LUT4 #(
- .INIT(16'h0026))
- \v_cnt[0]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(s_state[0]),
- .I3(\v_cnt_reg_n_0_[0] ),
- .O(\v_cnt[0]_i_1__0_n_0 ));
- LUT5 #(
- .INIT(32'h00262600))
- \v_cnt[1]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(s_state[0]),
- .I3(\v_cnt_reg_n_0_[1] ),
- .I4(\v_cnt_reg_n_0_[0] ),
- .O(\v_cnt[1]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h0026260026002600))
- \v_cnt[2]_i_1__0
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(s_state[0]),
- .I3(\v_cnt_reg_n_0_[2] ),
- .I4(\v_cnt_reg_n_0_[0] ),
- .I5(\v_cnt_reg_n_0_[1] ),
- .O(\v_cnt[2]_i_1__0_n_0 ));
- LUT5 #(
- .INIT(32'h28888888))
- \v_cnt[3]_i_1__0
- (.I0(\v_cnt[6]_i_4__0_n_0 ),
- .I1(\v_cnt_reg_n_0_[3] ),
- .I2(\v_cnt_reg_n_0_[1] ),
- .I3(\v_cnt_reg_n_0_[0] ),
- .I4(\v_cnt_reg_n_0_[2] ),
- .O(\v_cnt[3]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'h2888888888888888))
- \v_cnt[4]_i_1__0
- (.I0(\v_cnt[6]_i_4__0_n_0 ),
- .I1(\v_cnt_reg_n_0_[4] ),
- .I2(\v_cnt_reg_n_0_[2] ),
- .I3(\v_cnt_reg_n_0_[0] ),
- .I4(\v_cnt_reg_n_0_[1] ),
- .I5(\v_cnt_reg_n_0_[3] ),
- .O(\v_cnt[4]_i_1__0_n_0 ));
- LUT5 #(
- .INIT(32'h88882888))
- \v_cnt[5]_i_1__0
- (.I0(\v_cnt[6]_i_4__0_n_0 ),
- .I1(\v_cnt_reg_n_0_[5] ),
- .I2(\v_cnt_reg_n_0_[4] ),
- .I3(\v_cnt_reg_n_0_[3] ),
- .I4(\v_cnt[6]_i_5__0_n_0 ),
- .O(\v_cnt[5]_i_1__0_n_0 ));
- LUT6 #(
- .INIT(64'hEEEEEEEEEEEEEFEE))
- \v_cnt[6]_i_1__0
- (.I0(\v_cnt[6]_i_3__0_n_0 ),
- .I1(s_rxdat_0),
- .I2(s_state[0]),
- .I3(s_start_reg),
- .I4(s_state[2]),
- .I5(s_state[1]),
- .O(v_cnt));
- LUT6 #(
- .INIT(64'h8888888828888888))
- \v_cnt[6]_i_2__0
- (.I0(\v_cnt[6]_i_4__0_n_0 ),
- .I1(\v_cnt_reg_n_0_[6] ),
- .I2(\v_cnt_reg_n_0_[5] ),
- .I3(\v_cnt_reg_n_0_[3] ),
- .I4(\v_cnt_reg_n_0_[4] ),
- .I5(\v_cnt[6]_i_5__0_n_0 ),
- .O(\v_cnt[6]_i_2__0_n_0 ));
- LUT6 #(
- .INIT(64'h000C000010101010))
- \v_cnt[6]_i_3__0
- (.I0(\FSM_sequential_s_state[2]_i_4__0_n_0 ),
- .I1(s_state[1]),
- .I2(s_state[2]),
- .I3(\s_txdat[119]_i_4__0_n_0 ),
- .I4(\s_txdat[119]_i_3__0_n_0 ),
- .I5(s_state[0]),
- .O(\v_cnt[6]_i_3__0_n_0 ));
- LUT3 #(
- .INIT(8'h34))
- \v_cnt[6]_i_4__0
- (.I0(s_state[0]),
- .I1(s_state[1]),
- .I2(s_state[2]),
- .O(\v_cnt[6]_i_4__0_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair49" *)
- LUT3 #(
- .INIT(8'h7F))
- \v_cnt[6]_i_5__0
- (.I0(\v_cnt_reg_n_0_[1] ),
- .I1(\v_cnt_reg_n_0_[0] ),
- .I2(\v_cnt_reg_n_0_[2] ),
- .O(\v_cnt[6]_i_5__0_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \v_cnt_reg[0]
- (.C(s00_axi_aclk),
- .CE(v_cnt),
- .D(\v_cnt[0]_i_1__0_n_0 ),
- .Q(\v_cnt_reg_n_0_[0] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \v_cnt_reg[1]
- (.C(s00_axi_aclk),
- .CE(v_cnt),
- .D(\v_cnt[1]_i_1__0_n_0 ),
- .Q(\v_cnt_reg_n_0_[1] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \v_cnt_reg[2]
- (.C(s00_axi_aclk),
- .CE(v_cnt),
- .D(\v_cnt[2]_i_1__0_n_0 ),
- .Q(\v_cnt_reg_n_0_[2] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \v_cnt_reg[3]
- (.C(s00_axi_aclk),
- .CE(v_cnt),
- .D(\v_cnt[3]_i_1__0_n_0 ),
- .Q(\v_cnt_reg_n_0_[3] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \v_cnt_reg[4]
- (.C(s00_axi_aclk),
- .CE(v_cnt),
- .D(\v_cnt[4]_i_1__0_n_0 ),
- .Q(\v_cnt_reg_n_0_[4] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \v_cnt_reg[5]
- (.C(s00_axi_aclk),
- .CE(v_cnt),
- .D(\v_cnt[5]_i_1__0_n_0 ),
- .Q(\v_cnt_reg_n_0_[5] ),
- .R(rst_i));
- FDRE #(
- .INIT(1'b0))
- \v_cnt_reg[6]
- (.C(s00_axi_aclk),
- .CE(v_cnt),
- .D(\v_cnt[6]_i_2__0_n_0 ),
- .Q(\v_cnt_reg_n_0_[6] ),
- .R(rst_i));
-endmodule
-
-(* ORIG_REF_NAME = "spi_transceiver" *)
-module system_design_fasec_hwtest_0_0_spi_transceiver_130
- (E,
- \v_ch_address_reg[0] ,
- \v_ch_address_reg[1] ,
- \s_state_reg[0] ,
- \s_state_reg[1] ,
- Q,
- \dac_ch_o_reg[0][31] ,
- s_spi_mosi,
- s_spi_cs_n,
- \data_rw_o_reg[11][1] ,
- \v_ch_address_reg[0]_0 ,
- \s_state_reg[1]_0 ,
- s00_axi_aresetn,
- \s_state_reg[0]_0 ,
- \[0].[3].s_reqs_reg[3][changed] ,
- \[0].[2].s_reqs_reg[2][changed] ,
- ch_address,
- \[0].[2].s_reqs_reg[2][changed]_0 ,
- SR,
- s00_axi_aclk,
- D,
- s_start_reg,
- \s_tx_data_reg[113] );
- output [0:0]E;
- output \v_ch_address_reg[0] ;
- output \v_ch_address_reg[1] ;
- output \s_state_reg[0] ;
- output \s_state_reg[1] ;
- output [0:0]Q;
- output [31:0]\dac_ch_o_reg[0][31] ;
- output s_spi_mosi;
- output s_spi_cs_n;
- input \data_rw_o_reg[11][1] ;
- input \v_ch_address_reg[0]_0 ;
- input \s_state_reg[1]_0 ;
- input s00_axi_aresetn;
- input \s_state_reg[0]_0 ;
- input \[0].[3].s_reqs_reg[3][changed] ;
- input \[0].[2].s_reqs_reg[2][changed] ;
- input [1:0]ch_address;
- input \[0].[2].s_reqs_reg[2][changed]_0 ;
- input [0:0]SR;
- input s00_axi_aclk;
- input [0:0]D;
- input s_start_reg;
- input [61:0]\s_tx_data_reg[113] ;
-
- wire [0:0]D;
- wire [0:0]E;
- wire \FSM_sequential_s_state[0]_i_1_n_0 ;
- wire \FSM_sequential_s_state[0]_i_2_n_0 ;
- wire \FSM_sequential_s_state[0]_i_3_n_0 ;
- wire \FSM_sequential_s_state[1]_i_1_n_0 ;
- wire \FSM_sequential_s_state[2]_i_1_n_0 ;
- wire \FSM_sequential_s_state[2]_i_2_n_0 ;
- wire \FSM_sequential_s_state[2]_i_3_n_0 ;
- wire \FSM_sequential_s_state[2]_i_4_n_0 ;
- wire [0:0]Q;
- wire [0:0]SR;
- wire \[0].[2].s_reqs_reg[2][changed] ;
- wire \[0].[2].s_reqs_reg[2][changed]_0 ;
- wire \[0].[3].s_reqs_reg[3][changed] ;
- wire [1:0]ch_address;
- wire [31:0]\dac_ch_o_reg[0][31] ;
- wire \data_rw_o_reg[11][1] ;
- wire p_0_in;
- wire \rx_data_o[31]_i_1_n_0 ;
- wire s00_axi_aclk;
- wire s00_axi_aresetn;
- wire [1:0]s_counter;
- wire \s_counter[0]_i_1_n_0 ;
- wire \s_counter[1]_i_1_n_0 ;
- wire \s_counter[2]_i_1_n_0 ;
- wire s_done;
- wire [31:0]s_rxdat;
- wire s_rxdat_0;
- wire s_spi_cs_n;
- wire s_spi_mosi;
- wire s_start_reg;
- (* RTL_KEEP = "yes" *) wire [2:0]s_state;
- wire \s_state[0]_i_2_n_0 ;
- wire \s_state[1]_i_4_n_0 ;
- wire \s_state_reg[0] ;
- wire \s_state_reg[0]_0 ;
- wire \s_state_reg[1] ;
- wire \s_state_reg[1]_0 ;
- wire [61:0]\s_tx_data_reg[113] ;
- wire s_txdat;
- wire \s_txdat[100]_i_1_n_0 ;
- wire \s_txdat[101]_i_1_n_0 ;
- wire \s_txdat[102]_i_1_n_0 ;
- wire \s_txdat[103]_i_1_n_0 ;
- wire \s_txdat[104]_i_1_n_0 ;
- wire \s_txdat[105]_i_1_n_0 ;
- wire \s_txdat[106]_i_1_n_0 ;
- wire \s_txdat[107]_i_1_n_0 ;
- wire \s_txdat[108]_i_1_n_0 ;
- wire \s_txdat[109]_i_1_n_0 ;
- wire \s_txdat[10]_i_1_n_0 ;
- wire \s_txdat[110]_i_1_n_0 ;
- wire \s_txdat[111]_i_1_n_0 ;
- wire \s_txdat[112]_i_1_n_0 ;
- wire \s_txdat[113]_i_1_n_0 ;
- wire \s_txdat[114]_i_1_n_0 ;
- wire \s_txdat[115]_i_1_n_0 ;
- wire \s_txdat[116]_i_1_n_0 ;
- wire \s_txdat[117]_i_1_n_0 ;
- wire \s_txdat[118]_i_1_n_0 ;
- wire \s_txdat[119]_i_2_n_0 ;
- wire \s_txdat[119]_i_3_n_0 ;
- wire \s_txdat[119]_i_4_n_0 ;
- wire \s_txdat[119]_i_5_n_0 ;
- wire \s_txdat[11]_i_1_n_0 ;
- wire \s_txdat[12]_i_1_n_0 ;
- wire \s_txdat[13]_i_1_n_0 ;
- wire \s_txdat[14]_i_1_n_0 ;
- wire \s_txdat[15]_i_1_n_0 ;
- wire \s_txdat[16]_i_1_n_0 ;
- wire \s_txdat[17]_i_1_n_0 ;
- wire \s_txdat[18]_i_1_n_0 ;
- wire \s_txdat[19]_i_1_n_0 ;
- wire \s_txdat[20]_i_1_n_0 ;
- wire \s_txdat[21]_i_1_n_0 ;
- wire \s_txdat[22]_i_1_n_0 ;
- wire \s_txdat[23]_i_1_n_0 ;
- wire \s_txdat[24]_i_1_n_0 ;
- wire \s_txdat[25]_i_1_n_0 ;
- wire \s_txdat[26]_i_1_n_0 ;
- wire \s_txdat[27]_i_1_n_0 ;
- wire \s_txdat[28]_i_1_n_0 ;
- wire \s_txdat[29]_i_1_n_0 ;
- wire \s_txdat[30]_i_1_n_0 ;
- wire \s_txdat[31]_i_1_n_0 ;
- wire \s_txdat[32]_i_1_n_0 ;
- wire \s_txdat[33]_i_1_n_0 ;
- wire \s_txdat[34]_i_1_n_0 ;
- wire \s_txdat[35]_i_1_n_0 ;
- wire \s_txdat[36]_i_1_n_0 ;
- wire \s_txdat[37]_i_1_n_0 ;
- wire \s_txdat[38]_i_1_n_0 ;
- wire \s_txdat[39]_i_1_n_0 ;
- wire \s_txdat[40]_i_1_n_0 ;
- wire \s_txdat[41]_i_1_n_0 ;
- wire \s_txdat[42]_i_1_n_0 ;
- wire \s_txdat[43]_i_1_n_0 ;
- wire \s_txdat[44]_i_1_n_0 ;
- wire \s_txdat[45]_i_1_n_0 ;
- wire \s_txdat[46]_i_1_n_0 ;
- wire \s_txdat[47]_i_1_n_0 ;
- wire \s_txdat[48]_i_1_n_0 ;
- wire \s_txdat[49]_i_1_n_0 ;
- wire \s_txdat[4]_i_1_n_0 ;
- wire \s_txdat[50]_i_1_n_0 ;
- wire \s_txdat[51]_i_1_n_0 ;
- wire \s_txdat[52]_i_1_n_0 ;
- wire \s_txdat[53]_i_1_n_0 ;
- wire \s_txdat[54]_i_1_n_0 ;
- wire \s_txdat[55]_i_1_n_0 ;
- wire \s_txdat[56]_i_1_n_0 ;
- wire \s_txdat[57]_i_1_n_0 ;
- wire \s_txdat[58]_i_1_n_0 ;
- wire \s_txdat[59]_i_1_n_0 ;
- wire \s_txdat[5]_i_1_n_0 ;
- wire \s_txdat[60]_i_1_n_0 ;
- wire \s_txdat[61]_i_1_n_0 ;
- wire \s_txdat[62]_i_1_n_0 ;
- wire \s_txdat[63]_i_1_n_0 ;
- wire \s_txdat[64]_i_1_n_0 ;
- wire \s_txdat[65]_i_1_n_0 ;
- wire \s_txdat[66]_i_1_n_0 ;
- wire \s_txdat[67]_i_1_n_0 ;
- wire \s_txdat[68]_i_1_n_0 ;
- wire \s_txdat[69]_i_1_n_0 ;
- wire \s_txdat[6]_i_1_n_0 ;
- wire \s_txdat[70]_i_1_n_0 ;
- wire \s_txdat[71]_i_1_n_0 ;
- wire \s_txdat[72]_i_1_n_0 ;
- wire \s_txdat[73]_i_1_n_0 ;
- wire \s_txdat[74]_i_1_n_0 ;
- wire \s_txdat[75]_i_1_n_0 ;
- wire \s_txdat[76]_i_1_n_0 ;
- wire \s_txdat[77]_i_1_n_0 ;
- wire \s_txdat[78]_i_1_n_0 ;
- wire \s_txdat[79]_i_1_n_0 ;
- wire \s_txdat[7]_i_1_n_0 ;
- wire \s_txdat[80]_i_1_n_0 ;
- wire \s_txdat[81]_i_1_n_0 ;
- wire \s_txdat[82]_i_1_n_0 ;
- wire \s_txdat[83]_i_1_n_0 ;
- wire \s_txdat[84]_i_1_n_0 ;
- wire \s_txdat[85]_i_1_n_0 ;
- wire \s_txdat[86]_i_1_n_0 ;
- wire \s_txdat[87]_i_1_n_0 ;
- wire \s_txdat[88]_i_1_n_0 ;
- wire \s_txdat[89]_i_1_n_0 ;
- wire \s_txdat[8]_i_1_n_0 ;
- wire \s_txdat[90]_i_1_n_0 ;
- wire \s_txdat[91]_i_1_n_0 ;
- wire \s_txdat[92]_i_1_n_0 ;
- wire \s_txdat[93]_i_1_n_0 ;
- wire \s_txdat[94]_i_1_n_0 ;
- wire \s_txdat[95]_i_1_n_0 ;
- wire \s_txdat[96]_i_1_n_0 ;
- wire \s_txdat[97]_i_1_n_0 ;
- wire \s_txdat[98]_i_1_n_0 ;
- wire \s_txdat[99]_i_1_n_0 ;
- wire \s_txdat[9]_i_1_n_0 ;
- wire \s_txdat_reg_n_0_[100] ;
- wire \s_txdat_reg_n_0_[101] ;
- wire \s_txdat_reg_n_0_[102] ;
- wire \s_txdat_reg_n_0_[103] ;
- wire \s_txdat_reg_n_0_[104] ;
- wire \s_txdat_reg_n_0_[105] ;
- wire \s_txdat_reg_n_0_[106] ;
- wire \s_txdat_reg_n_0_[107] ;
- wire \s_txdat_reg_n_0_[108] ;
- wire \s_txdat_reg_n_0_[109] ;
- wire \s_txdat_reg_n_0_[10] ;
- wire \s_txdat_reg_n_0_[110] ;
- wire \s_txdat_reg_n_0_[111] ;
- wire \s_txdat_reg_n_0_[112] ;
- wire \s_txdat_reg_n_0_[113] ;
- wire \s_txdat_reg_n_0_[114] ;
- wire \s_txdat_reg_n_0_[115] ;
- wire \s_txdat_reg_n_0_[116] ;
- wire \s_txdat_reg_n_0_[117] ;
- wire \s_txdat_reg_n_0_[118] ;
- wire \s_txdat_reg_n_0_[11] ;
- wire \s_txdat_reg_n_0_[12] ;
- wire \s_txdat_reg_n_0_[13] ;
- wire \s_txdat_reg_n_0_[14] ;
- wire \s_txdat_reg_n_0_[15] ;
- wire \s_txdat_reg_n_0_[16] ;
- wire \s_txdat_reg_n_0_[17] ;
- wire \s_txdat_reg_n_0_[18] ;
- wire \s_txdat_reg_n_0_[19] ;
- wire \s_txdat_reg_n_0_[20] ;
- wire \s_txdat_reg_n_0_[21] ;
- wire \s_txdat_reg_n_0_[22] ;
- wire \s_txdat_reg_n_0_[23] ;
- wire \s_txdat_reg_n_0_[24] ;
- wire \s_txdat_reg_n_0_[25] ;
- wire \s_txdat_reg_n_0_[26] ;
- wire \s_txdat_reg_n_0_[27] ;
- wire \s_txdat_reg_n_0_[28] ;
- wire \s_txdat_reg_n_0_[29] ;
- wire \s_txdat_reg_n_0_[30] ;
- wire \s_txdat_reg_n_0_[31] ;
- wire \s_txdat_reg_n_0_[32] ;
- wire \s_txdat_reg_n_0_[33] ;
- wire \s_txdat_reg_n_0_[34] ;
- wire \s_txdat_reg_n_0_[35] ;
- wire \s_txdat_reg_n_0_[36] ;
- wire \s_txdat_reg_n_0_[37] ;
- wire \s_txdat_reg_n_0_[38] ;
- wire \s_txdat_reg_n_0_[39] ;
- wire \s_txdat_reg_n_0_[40] ;
- wire \s_txdat_reg_n_0_[41] ;
- wire \s_txdat_reg_n_0_[42] ;
- wire \s_txdat_reg_n_0_[43] ;
- wire \s_txdat_reg_n_0_[44] ;
- wire \s_txdat_reg_n_0_[45] ;
- wire \s_txdat_reg_n_0_[46] ;
- wire \s_txdat_reg_n_0_[47] ;
- wire \s_txdat_reg_n_0_[48] ;
- wire \s_txdat_reg_n_0_[49] ;
- wire \s_txdat_reg_n_0_[4] ;
- wire \s_txdat_reg_n_0_[50] ;
- wire \s_txdat_reg_n_0_[51] ;
- wire \s_txdat_reg_n_0_[52] ;
- wire \s_txdat_reg_n_0_[53] ;
- wire \s_txdat_reg_n_0_[54] ;
- wire \s_txdat_reg_n_0_[55] ;
- wire \s_txdat_reg_n_0_[56] ;
- wire \s_txdat_reg_n_0_[57] ;
- wire \s_txdat_reg_n_0_[58] ;
- wire \s_txdat_reg_n_0_[59] ;
- wire \s_txdat_reg_n_0_[5] ;
- wire \s_txdat_reg_n_0_[60] ;
- wire \s_txdat_reg_n_0_[61] ;
- wire \s_txdat_reg_n_0_[62] ;
- wire \s_txdat_reg_n_0_[63] ;
- wire \s_txdat_reg_n_0_[64] ;
- wire \s_txdat_reg_n_0_[65] ;
- wire \s_txdat_reg_n_0_[66] ;
- wire \s_txdat_reg_n_0_[67] ;
- wire \s_txdat_reg_n_0_[68] ;
- wire \s_txdat_reg_n_0_[69] ;
- wire \s_txdat_reg_n_0_[6] ;
- wire \s_txdat_reg_n_0_[70] ;
- wire \s_txdat_reg_n_0_[71] ;
- wire \s_txdat_reg_n_0_[72] ;
- wire \s_txdat_reg_n_0_[73] ;
- wire \s_txdat_reg_n_0_[74] ;
- wire \s_txdat_reg_n_0_[75] ;
- wire \s_txdat_reg_n_0_[76] ;
- wire \s_txdat_reg_n_0_[77] ;
- wire \s_txdat_reg_n_0_[78] ;
- wire \s_txdat_reg_n_0_[79] ;
- wire \s_txdat_reg_n_0_[7] ;
- wire \s_txdat_reg_n_0_[80] ;
- wire \s_txdat_reg_n_0_[81] ;
- wire \s_txdat_reg_n_0_[82] ;
- wire \s_txdat_reg_n_0_[83] ;
- wire \s_txdat_reg_n_0_[84] ;
- wire \s_txdat_reg_n_0_[85] ;
- wire \s_txdat_reg_n_0_[86] ;
- wire \s_txdat_reg_n_0_[87] ;
- wire \s_txdat_reg_n_0_[88] ;
- wire \s_txdat_reg_n_0_[89] ;
- wire \s_txdat_reg_n_0_[8] ;
- wire \s_txdat_reg_n_0_[90] ;
- wire \s_txdat_reg_n_0_[91] ;
- wire \s_txdat_reg_n_0_[92] ;
- wire \s_txdat_reg_n_0_[93] ;
- wire \s_txdat_reg_n_0_[94] ;
- wire \s_txdat_reg_n_0_[95] ;
- wire \s_txdat_reg_n_0_[96] ;
- wire \s_txdat_reg_n_0_[97] ;
- wire \s_txdat_reg_n_0_[98] ;
- wire \s_txdat_reg_n_0_[99] ;
- wire \s_txdat_reg_n_0_[9] ;
- wire v_ch_address;
- wire \v_ch_address_reg[0] ;
- wire \v_ch_address_reg[0]_0 ;
- wire \v_ch_address_reg[1] ;
- wire v_cnt;
- wire \v_cnt[0]_i_1_n_0 ;
- wire \v_cnt[1]_i_1_n_0 ;
- wire \v_cnt[2]_i_1_n_0 ;
- wire \v_cnt[3]_i_1_n_0 ;
- wire \v_cnt[4]_i_1_n_0 ;
- wire \v_cnt[5]_i_1_n_0 ;
- wire \v_cnt[6]_i_2_n_0 ;
- wire \v_cnt[6]_i_3_n_0 ;
- wire \v_cnt[6]_i_4_n_0 ;
- wire \v_cnt[6]_i_5_n_0 ;
- wire \v_cnt_reg_n_0_[0] ;
- wire \v_cnt_reg_n_0_[1] ;
- wire \v_cnt_reg_n_0_[2] ;
- wire \v_cnt_reg_n_0_[3] ;
- wire \v_cnt_reg_n_0_[4] ;
- wire \v_cnt_reg_n_0_[5] ;
- wire \v_cnt_reg_n_0_[6] ;
-
- LUT3 #(
- .INIT(8'hB8))
- \FSM_sequential_s_state[0]_i_1
- (.I0(\FSM_sequential_s_state[0]_i_2_n_0 ),
- .I1(\FSM_sequential_s_state[2]_i_2_n_0 ),
- .I2(s_state[0]),
- .O(\FSM_sequential_s_state[0]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hFFFEFF00FFFFFF00))
- \FSM_sequential_s_state[0]_i_2
- (.I0(\v_cnt_reg_n_0_[0] ),
- .I1(\v_cnt_reg_n_0_[1] ),
- .I2(\v_cnt_reg_n_0_[2] ),
- .I3(\FSM_sequential_s_state[0]_i_3_n_0 ),
- .I4(s_state[1]),
- .I5(\v_cnt_reg_n_0_[3] ),
- .O(\FSM_sequential_s_state[0]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h77C3FFC3FFC3FFC3))
- \FSM_sequential_s_state[0]_i_3
- (.I0(\v_cnt_reg_n_0_[4] ),
- .I1(s_state[0]),
- .I2(s_state[2]),
- .I3(s_state[1]),
- .I4(\v_cnt_reg_n_0_[6] ),
- .I5(\v_cnt_reg_n_0_[5] ),
- .O(\FSM_sequential_s_state[0]_i_3_n_0 ));
- LUT4 #(
- .INIT(16'h6F60))
- \FSM_sequential_s_state[1]_i_1
- (.I0(s_state[0]),
- .I1(s_state[1]),
- .I2(\FSM_sequential_s_state[2]_i_2_n_0 ),
- .I3(s_state[1]),
- .O(\FSM_sequential_s_state[1]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h8F80))
- \FSM_sequential_s_state[2]_i_1
- (.I0(s_state[1]),
- .I1(s_state[0]),
- .I2(\FSM_sequential_s_state[2]_i_2_n_0 ),
- .I3(s_state[2]),
- .O(\FSM_sequential_s_state[2]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hABEEAAAAAAEEAAAA))
- \FSM_sequential_s_state[2]_i_2
- (.I0(\FSM_sequential_s_state[2]_i_3_n_0 ),
- .I1(s_state[0]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .I4(\s_txdat[119]_i_3_n_0 ),
- .I5(\FSM_sequential_s_state[2]_i_4_n_0 ),
- .O(\FSM_sequential_s_state[2]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF0010))
- \FSM_sequential_s_state[2]_i_3
- (.I0(s_state[1]),
- .I1(s_state[2]),
- .I2(s_start_reg),
- .I3(s_state[0]),
- .I4(s_rxdat_0),
- .O(\FSM_sequential_s_state[2]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair37" *)
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \FSM_sequential_s_state[2]_i_4
- (.I0(\v_cnt_reg_n_0_[2] ),
- .I1(\v_cnt_reg_n_0_[5] ),
- .I2(\v_cnt_reg_n_0_[6] ),
- .I3(\v_cnt_reg_n_0_[4] ),
- .I4(\v_cnt_reg_n_0_[3] ),
- .O(\FSM_sequential_s_state[2]_i_4_n_0 ));
- (* KEEP = "yes" *)
- FDRE \FSM_sequential_s_state_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\FSM_sequential_s_state[0]_i_1_n_0 ),
- .Q(s_state[0]),
- .R(SR));
- (* KEEP = "yes" *)
- FDRE \FSM_sequential_s_state_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\FSM_sequential_s_state[1]_i_1_n_0 ),
- .Q(s_state[1]),
- .R(SR));
- (* KEEP = "yes" *)
- FDRE \FSM_sequential_s_state_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\FSM_sequential_s_state[2]_i_1_n_0 ),
- .Q(s_state[2]),
- .R(SR));
- LUT6 #(
- .INIT(64'h0000000002000000))
- \dac_ch_o[0][31]_i_1
- (.I0(\s_state_reg[1]_0 ),
- .I1(s_state[1]),
- .I2(s_state[0]),
- .I3(s00_axi_aresetn),
- .I4(\s_state_reg[0]_0 ),
- .I5(\v_ch_address_reg[0]_0 ),
- .O(E));
- LUT3 #(
- .INIT(8'h07))
- \gen_spi.cmp_spi_cs_n_iobuf_i_1
- (.I0(s_state[0]),
- .I1(s_state[2]),
- .I2(s_state[1]),
- .O(s_spi_cs_n));
- LUT4 #(
- .INIT(16'h2B3B))
- \gen_spi.cmp_spi_mosi_iobuf_i_1
- (.I0(p_0_in),
- .I1(s_state[1]),
- .I2(s_state[2]),
- .I3(s_state[0]),
- .O(s_spi_mosi));
- LUT4 #(
- .INIT(16'h0002))
- \rx_data_o[31]_i_1
- (.I0(s00_axi_aresetn),
- .I1(s_state[0]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\rx_data_o[31]_i_1_n_0 ));
- FDRE \rx_data_o_reg[0]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[0]),
- .Q(\dac_ch_o_reg[0][31] [0]),
- .R(1'b0));
- FDRE \rx_data_o_reg[10]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[10]),
- .Q(\dac_ch_o_reg[0][31] [10]),
- .R(1'b0));
- FDRE \rx_data_o_reg[11]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[11]),
- .Q(\dac_ch_o_reg[0][31] [11]),
- .R(1'b0));
- FDRE \rx_data_o_reg[12]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[12]),
- .Q(\dac_ch_o_reg[0][31] [12]),
- .R(1'b0));
- FDRE \rx_data_o_reg[13]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[13]),
- .Q(\dac_ch_o_reg[0][31] [13]),
- .R(1'b0));
- FDRE \rx_data_o_reg[14]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[14]),
- .Q(\dac_ch_o_reg[0][31] [14]),
- .R(1'b0));
- FDRE \rx_data_o_reg[15]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[15]),
- .Q(\dac_ch_o_reg[0][31] [15]),
- .R(1'b0));
- FDRE \rx_data_o_reg[16]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[16]),
- .Q(\dac_ch_o_reg[0][31] [16]),
- .R(1'b0));
- FDRE \rx_data_o_reg[17]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[17]),
- .Q(\dac_ch_o_reg[0][31] [17]),
- .R(1'b0));
- FDRE \rx_data_o_reg[18]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[18]),
- .Q(\dac_ch_o_reg[0][31] [18]),
- .R(1'b0));
- FDRE \rx_data_o_reg[19]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[19]),
- .Q(\dac_ch_o_reg[0][31] [19]),
- .R(1'b0));
- FDRE \rx_data_o_reg[1]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[1]),
- .Q(\dac_ch_o_reg[0][31] [1]),
- .R(1'b0));
- FDRE \rx_data_o_reg[20]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[20]),
- .Q(\dac_ch_o_reg[0][31] [20]),
- .R(1'b0));
- FDRE \rx_data_o_reg[21]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[21]),
- .Q(\dac_ch_o_reg[0][31] [21]),
- .R(1'b0));
- FDRE \rx_data_o_reg[22]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[22]),
- .Q(\dac_ch_o_reg[0][31] [22]),
- .R(1'b0));
- FDRE \rx_data_o_reg[23]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[23]),
- .Q(\dac_ch_o_reg[0][31] [23]),
- .R(1'b0));
- FDRE \rx_data_o_reg[24]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[24]),
- .Q(\dac_ch_o_reg[0][31] [24]),
- .R(1'b0));
- FDRE \rx_data_o_reg[25]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[25]),
- .Q(\dac_ch_o_reg[0][31] [25]),
- .R(1'b0));
- FDRE \rx_data_o_reg[26]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[26]),
- .Q(\dac_ch_o_reg[0][31] [26]),
- .R(1'b0));
- FDRE \rx_data_o_reg[27]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[27]),
- .Q(\dac_ch_o_reg[0][31] [27]),
- .R(1'b0));
- FDRE \rx_data_o_reg[28]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[28]),
- .Q(\dac_ch_o_reg[0][31] [28]),
- .R(1'b0));
- FDRE \rx_data_o_reg[29]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[29]),
- .Q(\dac_ch_o_reg[0][31] [29]),
- .R(1'b0));
- FDRE \rx_data_o_reg[2]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[2]),
- .Q(\dac_ch_o_reg[0][31] [2]),
- .R(1'b0));
- FDRE \rx_data_o_reg[30]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[30]),
- .Q(\dac_ch_o_reg[0][31] [30]),
- .R(1'b0));
- FDRE \rx_data_o_reg[31]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[31]),
- .Q(\dac_ch_o_reg[0][31] [31]),
- .R(1'b0));
- FDRE \rx_data_o_reg[3]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[3]),
- .Q(\dac_ch_o_reg[0][31] [3]),
- .R(1'b0));
- FDRE \rx_data_o_reg[4]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[4]),
- .Q(\dac_ch_o_reg[0][31] [4]),
- .R(1'b0));
- FDRE \rx_data_o_reg[5]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[5]),
- .Q(\dac_ch_o_reg[0][31] [5]),
- .R(1'b0));
- FDRE \rx_data_o_reg[6]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[6]),
- .Q(\dac_ch_o_reg[0][31] [6]),
- .R(1'b0));
- FDRE \rx_data_o_reg[7]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[7]),
- .Q(\dac_ch_o_reg[0][31] [7]),
- .R(1'b0));
- FDRE \rx_data_o_reg[8]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[8]),
- .Q(\dac_ch_o_reg[0][31] [8]),
- .R(1'b0));
- FDRE \rx_data_o_reg[9]
- (.C(s00_axi_aclk),
- .CE(\rx_data_o[31]_i_1_n_0 ),
- .D(s_rxdat[9]),
- .Q(\dac_ch_o_reg[0][31] [9]),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair41" *)
- LUT1 #(
- .INIT(2'h1))
- \s_counter[0]_i_1
- (.I0(s_counter[0]),
- .O(\s_counter[0]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair41" *)
- LUT2 #(
- .INIT(4'h6))
- \s_counter[1]_i_1
- (.I0(s_counter[0]),
- .I1(s_counter[1]),
- .O(\s_counter[1]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair40" *)
- LUT3 #(
- .INIT(8'h6A))
- \s_counter[2]_i_1
- (.I0(Q),
- .I1(s_counter[0]),
- .I2(s_counter[1]),
- .O(\s_counter[2]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \s_counter_reg[0]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_counter[0]_i_1_n_0 ),
- .Q(s_counter[0]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_counter_reg[1]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_counter[1]_i_1_n_0 ),
- .Q(s_counter[1]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_counter_reg[2]
- (.C(s00_axi_aclk),
- .CE(1'b1),
- .D(\s_counter[2]_i_1_n_0 ),
- .Q(Q),
- .R(SR));
- LUT6 #(
- .INIT(64'h2400000000000000))
- \s_rxdat[31]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(s_state[0]),
- .I3(s_counter[0]),
- .I4(s_counter[1]),
- .I5(Q),
- .O(s_rxdat_0));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[0]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(D),
- .Q(s_rxdat[0]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[9]),
- .Q(s_rxdat[10]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[10]),
- .Q(s_rxdat[11]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[11]),
- .Q(s_rxdat[12]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[12]),
- .Q(s_rxdat[13]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[13]),
- .Q(s_rxdat[14]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[14]),
- .Q(s_rxdat[15]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[15]),
- .Q(s_rxdat[16]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[16]),
- .Q(s_rxdat[17]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[17]),
- .Q(s_rxdat[18]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[18]),
- .Q(s_rxdat[19]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[1]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[0]),
- .Q(s_rxdat[1]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[19]),
- .Q(s_rxdat[20]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[20]),
- .Q(s_rxdat[21]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[21]),
- .Q(s_rxdat[22]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[22]),
- .Q(s_rxdat[23]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[24]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[23]),
- .Q(s_rxdat[24]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[25]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[24]),
- .Q(s_rxdat[25]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[26]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[25]),
- .Q(s_rxdat[26]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[27]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[26]),
- .Q(s_rxdat[27]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[28]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[27]),
- .Q(s_rxdat[28]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[29]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[28]),
- .Q(s_rxdat[29]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[2]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[1]),
- .Q(s_rxdat[2]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[30]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[29]),
- .Q(s_rxdat[30]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[31]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[30]),
- .Q(s_rxdat[31]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[3]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[2]),
- .Q(s_rxdat[3]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[3]),
- .Q(s_rxdat[4]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[4]),
- .Q(s_rxdat[5]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[5]),
- .Q(s_rxdat[6]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[6]),
- .Q(s_rxdat[7]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[7]),
- .Q(s_rxdat[8]),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_rxdat_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_rxdat_0),
- .D(s_rxdat[8]),
- .Q(s_rxdat[9]),
- .R(SR));
- LUT5 #(
- .INIT(32'h2AFFFF00))
- \s_state[0]_i_1
- (.I0(\s_state_reg[1]_0 ),
- .I1(ch_address[0]),
- .I2(ch_address[1]),
- .I3(\s_state[0]_i_2_n_0 ),
- .I4(\s_state_reg[0]_0 ),
- .O(\s_state_reg[0] ));
- LUT6 #(
- .INIT(64'hFAFFAFFAFABFAFBA))
- \s_state[0]_i_2
- (.I0(\[0].[3].s_reqs_reg[3][changed] ),
- .I1(\v_ch_address_reg[0]_0 ),
- .I2(\s_state_reg[0]_0 ),
- .I3(\s_state_reg[1]_0 ),
- .I4(s_done),
- .I5(\[0].[2].s_reqs_reg[2][changed] ),
- .O(\s_state[0]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFDFFFCF0))
- \s_state[1]_i_1
- (.I0(\s_state_reg[0]_0 ),
- .I1(\[0].[2].s_reqs_reg[2][changed]_0 ),
- .I2(\[0].[3].s_reqs_reg[3][changed] ),
- .I3(\s_state[1]_i_4_n_0 ),
- .I4(\s_state_reg[1]_0 ),
- .O(\s_state_reg[1] ));
- LUT6 #(
- .INIT(64'hCF3CCA3CCA3CCA3C))
- \s_state[1]_i_4
- (.I0(\[0].[2].s_reqs_reg[2][changed] ),
- .I1(s_done),
- .I2(\s_state_reg[1]_0 ),
- .I3(\s_state_reg[0]_0 ),
- .I4(ch_address[1]),
- .I5(ch_address[0]),
- .O(\s_state[1]_i_4_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[100]_i_1
- (.I0(\s_txdat_reg_n_0_[99] ),
- .I1(\s_tx_data_reg[113] [48]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[100]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[101]_i_1
- (.I0(\s_txdat_reg_n_0_[100] ),
- .I1(\s_tx_data_reg[113] [49]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[101]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[102]_i_1
- (.I0(\s_txdat_reg_n_0_[101] ),
- .I1(\s_tx_data_reg[113] [50]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[102]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[103]_i_1
- (.I0(\s_txdat_reg_n_0_[102] ),
- .I1(\s_tx_data_reg[113] [51]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[103]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[104]_i_1
- (.I0(\s_txdat_reg_n_0_[103] ),
- .I1(\s_tx_data_reg[113] [52]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[104]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[105]_i_1
- (.I0(\s_txdat_reg_n_0_[104] ),
- .I1(\s_tx_data_reg[113] [53]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[105]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[106]_i_1
- (.I0(\s_txdat_reg_n_0_[105] ),
- .I1(\s_tx_data_reg[113] [54]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[106]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[107]_i_1
- (.I0(\s_txdat_reg_n_0_[106] ),
- .I1(\s_tx_data_reg[113] [55]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[107]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[108]_i_1
- (.I0(\s_txdat_reg_n_0_[107] ),
- .I1(\s_tx_data_reg[113] [56]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[108]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[109]_i_1
- (.I0(\s_txdat_reg_n_0_[108] ),
- .I1(\s_tx_data_reg[113] [57]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[109]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[10]_i_1
- (.I0(\s_txdat_reg_n_0_[9] ),
- .I1(\s_tx_data_reg[113] [6]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[10]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[110]_i_1
- (.I0(\s_txdat_reg_n_0_[109] ),
- .I1(\s_tx_data_reg[113] [58]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[110]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[111]_i_1
- (.I0(\s_txdat_reg_n_0_[110] ),
- .I1(\s_tx_data_reg[113] [59]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[111]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[112]_i_1
- (.I0(\s_txdat_reg_n_0_[111] ),
- .I1(\s_tx_data_reg[113] [60]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[112]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[113]_i_1
- (.I0(\s_txdat_reg_n_0_[112] ),
- .I1(\s_tx_data_reg[113] [61]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[113]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h23))
- \s_txdat[114]_i_1
- (.I0(\s_txdat_reg_n_0_[113] ),
- .I1(s_state[2]),
- .I2(s_state[1]),
- .O(\s_txdat[114]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[115]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[114] ),
- .O(\s_txdat[115]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[116]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[115] ),
- .O(\s_txdat[116]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[117]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[116] ),
- .O(\s_txdat[117]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[118]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[117] ),
- .O(\s_txdat[118]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h00800080000F0000))
- \s_txdat[119]_i_1
- (.I0(\s_txdat[119]_i_3_n_0 ),
- .I1(\s_txdat[119]_i_4_n_0 ),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .I4(s_start_reg),
- .I5(s_state[0]),
- .O(s_txdat));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[119]_i_2
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[118] ),
- .O(\s_txdat[119]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair40" *)
- LUT3 #(
- .INIT(8'h08))
- \s_txdat[119]_i_3
- (.I0(s_counter[1]),
- .I1(s_counter[0]),
- .I2(Q),
- .O(\s_txdat[119]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair38" *)
- LUT5 #(
- .INIT(32'hFFFFFFFB))
- \s_txdat[119]_i_4
- (.I0(\v_cnt_reg_n_0_[2] ),
- .I1(\v_cnt_reg_n_0_[6] ),
- .I2(\v_cnt_reg_n_0_[0] ),
- .I3(\v_cnt_reg_n_0_[1] ),
- .I4(\s_txdat[119]_i_5_n_0 ),
- .O(\s_txdat[119]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair37" *)
- LUT3 #(
- .INIT(8'h7F))
- \s_txdat[119]_i_5
- (.I0(\v_cnt_reg_n_0_[4] ),
- .I1(\v_cnt_reg_n_0_[3] ),
- .I2(\v_cnt_reg_n_0_[5] ),
- .O(\s_txdat[119]_i_5_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[11]_i_1
- (.I0(\s_txdat_reg_n_0_[10] ),
- .I1(\s_tx_data_reg[113] [7]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[11]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[12]_i_1
- (.I0(\s_txdat_reg_n_0_[11] ),
- .I1(\s_tx_data_reg[113] [8]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[12]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[13]_i_1
- (.I0(\s_txdat_reg_n_0_[12] ),
- .I1(\s_tx_data_reg[113] [9]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[13]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[14]_i_1
- (.I0(\s_txdat_reg_n_0_[13] ),
- .I1(\s_tx_data_reg[113] [10]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[14]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[15]_i_1
- (.I0(\s_txdat_reg_n_0_[14] ),
- .I1(\s_tx_data_reg[113] [11]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[15]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[16]_i_1
- (.I0(\s_txdat_reg_n_0_[15] ),
- .I1(\s_tx_data_reg[113] [60]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[16]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[17]_i_1
- (.I0(\s_txdat_reg_n_0_[16] ),
- .I1(\s_tx_data_reg[113] [61]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[17]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h23))
- \s_txdat[18]_i_1
- (.I0(\s_txdat_reg_n_0_[17] ),
- .I1(s_state[2]),
- .I2(s_state[1]),
- .O(\s_txdat[18]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[19]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[18] ),
- .O(\s_txdat[19]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[20]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[19] ),
- .O(\s_txdat[20]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[21]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[20] ),
- .O(\s_txdat[21]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[22]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[21] ),
- .O(\s_txdat[22]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[23]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[22] ),
- .O(\s_txdat[23]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[24]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[23] ),
- .O(\s_txdat[24]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[25]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[24] ),
- .O(\s_txdat[25]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[26]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[25] ),
- .O(\s_txdat[26]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[27]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[26] ),
- .O(\s_txdat[27]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[28]_i_1
- (.I0(\s_txdat_reg_n_0_[27] ),
- .I1(\s_tx_data_reg[113] [12]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[28]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[29]_i_1
- (.I0(\s_txdat_reg_n_0_[28] ),
- .I1(\s_tx_data_reg[113] [13]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[29]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[30]_i_1
- (.I0(\s_txdat_reg_n_0_[29] ),
- .I1(\s_tx_data_reg[113] [14]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[30]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[31]_i_1
- (.I0(\s_txdat_reg_n_0_[30] ),
- .I1(\s_tx_data_reg[113] [15]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[31]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[32]_i_1
- (.I0(\s_txdat_reg_n_0_[31] ),
- .I1(\s_tx_data_reg[113] [16]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[32]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[33]_i_1
- (.I0(\s_txdat_reg_n_0_[32] ),
- .I1(\s_tx_data_reg[113] [17]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[33]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[34]_i_1
- (.I0(\s_txdat_reg_n_0_[33] ),
- .I1(\s_tx_data_reg[113] [18]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[34]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[35]_i_1
- (.I0(\s_txdat_reg_n_0_[34] ),
- .I1(\s_tx_data_reg[113] [19]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[35]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[36]_i_1
- (.I0(\s_txdat_reg_n_0_[35] ),
- .I1(\s_tx_data_reg[113] [20]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[36]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[37]_i_1
- (.I0(\s_txdat_reg_n_0_[36] ),
- .I1(\s_tx_data_reg[113] [21]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[37]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[38]_i_1
- (.I0(\s_txdat_reg_n_0_[37] ),
- .I1(\s_tx_data_reg[113] [22]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[38]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[39]_i_1
- (.I0(\s_txdat_reg_n_0_[38] ),
- .I1(\s_tx_data_reg[113] [23]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[39]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[40]_i_1
- (.I0(\s_txdat_reg_n_0_[39] ),
- .I1(\s_tx_data_reg[113] [60]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[40]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[41]_i_1
- (.I0(\s_txdat_reg_n_0_[40] ),
- .I1(\s_tx_data_reg[113] [61]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[41]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h23))
- \s_txdat[42]_i_1
- (.I0(\s_txdat_reg_n_0_[41] ),
- .I1(s_state[2]),
- .I2(s_state[1]),
- .O(\s_txdat[42]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[43]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[42] ),
- .O(\s_txdat[43]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[44]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[43] ),
- .O(\s_txdat[44]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[45]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[44] ),
- .O(\s_txdat[45]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[46]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[45] ),
- .O(\s_txdat[46]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[47]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[46] ),
- .O(\s_txdat[47]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[48]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[47] ),
- .O(\s_txdat[48]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[49]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[48] ),
- .O(\s_txdat[49]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h10))
- \s_txdat[4]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_tx_data_reg[113] [0]),
- .O(\s_txdat[4]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[50]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[49] ),
- .O(\s_txdat[50]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[51]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[50] ),
- .O(\s_txdat[51]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[52]_i_1
- (.I0(\s_txdat_reg_n_0_[51] ),
- .I1(\s_tx_data_reg[113] [24]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[52]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[53]_i_1
- (.I0(\s_txdat_reg_n_0_[52] ),
- .I1(\s_tx_data_reg[113] [25]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[53]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[54]_i_1
- (.I0(\s_txdat_reg_n_0_[53] ),
- .I1(\s_tx_data_reg[113] [26]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[54]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[55]_i_1
- (.I0(\s_txdat_reg_n_0_[54] ),
- .I1(\s_tx_data_reg[113] [27]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[55]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[56]_i_1
- (.I0(\s_txdat_reg_n_0_[55] ),
- .I1(\s_tx_data_reg[113] [28]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[56]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[57]_i_1
- (.I0(\s_txdat_reg_n_0_[56] ),
- .I1(\s_tx_data_reg[113] [29]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[57]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[58]_i_1
- (.I0(\s_txdat_reg_n_0_[57] ),
- .I1(\s_tx_data_reg[113] [30]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[58]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[59]_i_1
- (.I0(\s_txdat_reg_n_0_[58] ),
- .I1(\s_tx_data_reg[113] [31]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[59]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[5]_i_1
- (.I0(\s_txdat_reg_n_0_[4] ),
- .I1(\s_tx_data_reg[113] [1]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[5]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[60]_i_1
- (.I0(\s_txdat_reg_n_0_[59] ),
- .I1(\s_tx_data_reg[113] [32]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[60]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[61]_i_1
- (.I0(\s_txdat_reg_n_0_[60] ),
- .I1(\s_tx_data_reg[113] [33]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[61]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[62]_i_1
- (.I0(\s_txdat_reg_n_0_[61] ),
- .I1(\s_tx_data_reg[113] [34]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[62]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[63]_i_1
- (.I0(\s_txdat_reg_n_0_[62] ),
- .I1(\s_tx_data_reg[113] [35]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[63]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[64]_i_1
- (.I0(\s_txdat_reg_n_0_[63] ),
- .I1(\s_tx_data_reg[113] [60]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[64]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[65]_i_1
- (.I0(\s_txdat_reg_n_0_[64] ),
- .I1(\s_tx_data_reg[113] [61]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[65]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h23))
- \s_txdat[66]_i_1
- (.I0(\s_txdat_reg_n_0_[65] ),
- .I1(s_state[2]),
- .I2(s_state[1]),
- .O(\s_txdat[66]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[67]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[66] ),
- .O(\s_txdat[67]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[68]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[67] ),
- .O(\s_txdat[68]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[69]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[68] ),
- .O(\s_txdat[69]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[6]_i_1
- (.I0(\s_txdat_reg_n_0_[5] ),
- .I1(\s_tx_data_reg[113] [2]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[6]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[70]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[69] ),
- .O(\s_txdat[70]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[71]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[70] ),
- .O(\s_txdat[71]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[72]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[71] ),
- .O(\s_txdat[72]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[73]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[72] ),
- .O(\s_txdat[73]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[74]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[73] ),
- .O(\s_txdat[74]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[75]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[74] ),
- .O(\s_txdat[75]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[76]_i_1
- (.I0(\s_txdat_reg_n_0_[75] ),
- .I1(\s_tx_data_reg[113] [36]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[76]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[77]_i_1
- (.I0(\s_txdat_reg_n_0_[76] ),
- .I1(\s_tx_data_reg[113] [37]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[77]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[78]_i_1
- (.I0(\s_txdat_reg_n_0_[77] ),
- .I1(\s_tx_data_reg[113] [38]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[78]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[79]_i_1
- (.I0(\s_txdat_reg_n_0_[78] ),
- .I1(\s_tx_data_reg[113] [39]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[79]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[7]_i_1
- (.I0(\s_txdat_reg_n_0_[6] ),
- .I1(\s_tx_data_reg[113] [3]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[7]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[80]_i_1
- (.I0(\s_txdat_reg_n_0_[79] ),
- .I1(\s_tx_data_reg[113] [40]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[80]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[81]_i_1
- (.I0(\s_txdat_reg_n_0_[80] ),
- .I1(\s_tx_data_reg[113] [41]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[81]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[82]_i_1
- (.I0(\s_txdat_reg_n_0_[81] ),
- .I1(\s_tx_data_reg[113] [42]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[82]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[83]_i_1
- (.I0(\s_txdat_reg_n_0_[82] ),
- .I1(\s_tx_data_reg[113] [43]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[83]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[84]_i_1
- (.I0(\s_txdat_reg_n_0_[83] ),
- .I1(\s_tx_data_reg[113] [44]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[84]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[85]_i_1
- (.I0(\s_txdat_reg_n_0_[84] ),
- .I1(\s_tx_data_reg[113] [45]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[85]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[86]_i_1
- (.I0(\s_txdat_reg_n_0_[85] ),
- .I1(\s_tx_data_reg[113] [46]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[86]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[87]_i_1
- (.I0(\s_txdat_reg_n_0_[86] ),
- .I1(\s_tx_data_reg[113] [47]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[87]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[88]_i_1
- (.I0(\s_txdat_reg_n_0_[87] ),
- .I1(\s_tx_data_reg[113] [60]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[88]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[89]_i_1
- (.I0(\s_txdat_reg_n_0_[88] ),
- .I1(\s_tx_data_reg[113] [61]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[89]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[8]_i_1
- (.I0(\s_txdat_reg_n_0_[7] ),
- .I1(\s_tx_data_reg[113] [4]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[8]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h23))
- \s_txdat[90]_i_1
- (.I0(\s_txdat_reg_n_0_[89] ),
- .I1(s_state[2]),
- .I2(s_state[1]),
- .O(\s_txdat[90]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[91]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[90] ),
- .O(\s_txdat[91]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[92]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[91] ),
- .O(\s_txdat[92]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[93]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[92] ),
- .O(\s_txdat[93]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[94]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[93] ),
- .O(\s_txdat[94]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[95]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[94] ),
- .O(\s_txdat[95]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[96]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[95] ),
- .O(\s_txdat[96]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[97]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[96] ),
- .O(\s_txdat[97]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[98]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[97] ),
- .O(\s_txdat[98]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
- \s_txdat[99]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(\s_txdat_reg_n_0_[98] ),
- .O(\s_txdat[99]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'h00AC))
- \s_txdat[9]_i_1
- (.I0(\s_txdat_reg_n_0_[8] ),
- .I1(\s_tx_data_reg[113] [5]),
- .I2(s_state[1]),
- .I3(s_state[2]),
- .O(\s_txdat[9]_i_1_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[100]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[100]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[100] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[101]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[101]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[101] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[102]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[102]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[102] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[103]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[103]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[103] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[104]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[104]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[104] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[105]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[105]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[105] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[106]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[106]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[106] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[107]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[107]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[107] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[108]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[108]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[108] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[109]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[109]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[109] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[10]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[10]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[10] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[110]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[110]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[110] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[111]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[111]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[111] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[112]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[112]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[112] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[113]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[113]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[113] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[114]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[114]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[114] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[115]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[115]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[115] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[116]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[116]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[116] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[117]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[117]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[117] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[118]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[118]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[118] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[119]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[119]_i_2_n_0 ),
- .Q(p_0_in),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[11]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[11]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[11] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[12]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[12]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[12] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[13]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[13]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[13] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[14]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[14]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[14] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[15]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[15]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[15] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[16]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[16]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[16] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[17]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[17]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[17] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[18]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[18]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[18] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[19]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[19]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[19] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[20]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[20]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[20] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[21]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[21]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[21] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[22]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[22]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[22] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[23]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[23]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[23] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[24]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[24]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[24] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[25]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[25]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[25] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[26]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[26]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[26] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[27]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[27]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[27] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[28]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[28]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[28] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[29]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[29]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[29] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[30]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[30]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[30] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[31]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[31]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[31] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[32]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[32]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[32] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[33]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[33]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[33] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[34]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[34]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[34] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[35]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[35]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[35] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[36]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[36]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[36] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[37]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[37]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[37] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[38]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[38]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[38] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[39]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[39]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[39] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[40]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[40]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[40] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[41]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[41]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[41] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[42]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[42]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[42] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[43]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[43]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[43] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[44]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[44]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[44] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[45]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[45]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[45] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[46]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[46]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[46] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[47]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[47]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[47] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[48]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[48]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[48] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[49]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[49]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[49] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[4]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[4]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[4] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[50]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[50]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[50] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[51]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[51]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[51] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[52]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[52]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[52] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[53]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[53]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[53] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[54]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[54]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[54] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[55]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[55]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[55] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[56]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[56]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[56] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[57]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[57]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[57] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[58]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[58]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[58] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[59]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[59]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[59] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[5]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[5]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[5] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[60]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[60]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[60] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[61]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[61]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[61] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[62]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[62]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[62] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[63]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[63]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[63] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[64]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[64]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[64] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[65]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[65]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[65] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[66]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[66]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[66] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[67]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[67]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[67] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[68]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[68]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[68] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[69]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[69]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[69] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[6]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[6]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[6] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[70]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[70]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[70] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[71]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[71]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[71] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[72]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[72]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[72] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[73]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[73]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[73] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[74]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[74]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[74] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[75]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[75]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[75] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[76]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[76]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[76] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[77]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[77]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[77] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[78]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[78]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[78] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[79]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[79]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[79] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[7]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[7]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[7] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[80]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[80]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[80] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[81]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[81]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[81] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[82]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[82]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[82] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[83]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[83]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[83] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[84]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[84]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[84] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[85]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[85]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[85] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[86]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[86]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[86] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[87]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[87]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[87] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[88]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[88]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[88] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[89]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[89]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[89] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[8]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[8]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[8] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[90]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[90]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[90] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[91]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[91]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[91] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[92]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[92]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[92] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[93]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[93]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[93] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[94]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[94]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[94] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[95]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[95]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[95] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[96]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[96]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[96] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[97]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[97]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[97] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[98]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[98]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[98] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[99]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[99]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[99] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \s_txdat_reg[9]
- (.C(s00_axi_aclk),
- .CE(s_txdat),
- .D(\s_txdat[9]_i_1_n_0 ),
- .Q(\s_txdat_reg_n_0_[9] ),
- .R(SR));
- (* SOFT_HLUTNM = "soft_lutpair39" *)
- LUT3 #(
- .INIT(8'h38))
- \v_ch_address[0]_i_1
- (.I0(\s_state_reg[0]_0 ),
- .I1(v_ch_address),
- .I2(ch_address[0]),
- .O(\v_ch_address_reg[0] ));
- (* SOFT_HLUTNM = "soft_lutpair39" *)
- LUT4 #(
- .INIT(16'h4F80))
- \v_ch_address[1]_i_1
- (.I0(ch_address[0]),
- .I1(\s_state_reg[0]_0 ),
- .I2(v_ch_address),
- .I3(ch_address[1]),
- .O(\v_ch_address_reg[1] ));
- LUT6 #(
- .INIT(64'hCA000A000A000A00))
- \v_ch_address[1]_i_2
- (.I0(\data_rw_o_reg[11][1] ),
- .I1(\v_ch_address_reg[0]_0 ),
- .I2(\s_state_reg[1]_0 ),
- .I3(s00_axi_aresetn),
- .I4(s_done),
- .I5(\s_state_reg[0]_0 ),
- .O(v_ch_address));
- LUT2 #(
- .INIT(4'h1))
- \v_ch_address[1]_i_4
- (.I0(s_state[0]),
- .I1(s_state[1]),
- .O(s_done));
- LUT4 #(
- .INIT(16'h0026))
- \v_cnt[0]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(s_state[0]),
- .I3(\v_cnt_reg_n_0_[0] ),
- .O(\v_cnt[0]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h00262600))
- \v_cnt[1]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(s_state[0]),
- .I3(\v_cnt_reg_n_0_[1] ),
- .I4(\v_cnt_reg_n_0_[0] ),
- .O(\v_cnt[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h0026260026002600))
- \v_cnt[2]_i_1
- (.I0(s_state[2]),
- .I1(s_state[1]),
- .I2(s_state[0]),
- .I3(\v_cnt_reg_n_0_[2] ),
- .I4(\v_cnt_reg_n_0_[0] ),
- .I5(\v_cnt_reg_n_0_[1] ),
- .O(\v_cnt[2]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h28888888))
- \v_cnt[3]_i_1
- (.I0(\v_cnt[6]_i_4_n_0 ),
- .I1(\v_cnt_reg_n_0_[3] ),
- .I2(\v_cnt_reg_n_0_[1] ),
- .I3(\v_cnt_reg_n_0_[0] ),
- .I4(\v_cnt_reg_n_0_[2] ),
- .O(\v_cnt[3]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h2888888888888888))
- \v_cnt[4]_i_1
- (.I0(\v_cnt[6]_i_4_n_0 ),
- .I1(\v_cnt_reg_n_0_[4] ),
- .I2(\v_cnt_reg_n_0_[2] ),
- .I3(\v_cnt_reg_n_0_[0] ),
- .I4(\v_cnt_reg_n_0_[1] ),
- .I5(\v_cnt_reg_n_0_[3] ),
- .O(\v_cnt[4]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h88882888))
- \v_cnt[5]_i_1
- (.I0(\v_cnt[6]_i_4_n_0 ),
- .I1(\v_cnt_reg_n_0_[5] ),
- .I2(\v_cnt_reg_n_0_[4] ),
- .I3(\v_cnt_reg_n_0_[3] ),
- .I4(\v_cnt[6]_i_5_n_0 ),
- .O(\v_cnt[5]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'hEEEEEEEEEEEEEFEE))
- \v_cnt[6]_i_1
- (.I0(\v_cnt[6]_i_3_n_0 ),
- .I1(s_rxdat_0),
- .I2(s_state[0]),
- .I3(s_start_reg),
- .I4(s_state[2]),
- .I5(s_state[1]),
- .O(v_cnt));
- LUT6 #(
- .INIT(64'h8888888828888888))
- \v_cnt[6]_i_2
- (.I0(\v_cnt[6]_i_4_n_0 ),
- .I1(\v_cnt_reg_n_0_[6] ),
- .I2(\v_cnt_reg_n_0_[5] ),
- .I3(\v_cnt_reg_n_0_[3] ),
- .I4(\v_cnt_reg_n_0_[4] ),
- .I5(\v_cnt[6]_i_5_n_0 ),
- .O(\v_cnt[6]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h000C000010101010))
- \v_cnt[6]_i_3
- (.I0(\FSM_sequential_s_state[2]_i_4_n_0 ),
- .I1(s_state[1]),
- .I2(s_state[2]),
- .I3(\s_txdat[119]_i_4_n_0 ),
- .I4(\s_txdat[119]_i_3_n_0 ),
- .I5(s_state[0]),
- .O(\v_cnt[6]_i_3_n_0 ));
- LUT3 #(
- .INIT(8'h34))
- \v_cnt[6]_i_4
- (.I0(s_state[0]),
- .I1(s_state[1]),
- .I2(s_state[2]),
- .O(\v_cnt[6]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair38" *)
- LUT3 #(
- .INIT(8'h7F))
- \v_cnt[6]_i_5
- (.I0(\v_cnt_reg_n_0_[1] ),
- .I1(\v_cnt_reg_n_0_[0] ),
- .I2(\v_cnt_reg_n_0_[2] ),
- .O(\v_cnt[6]_i_5_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \v_cnt_reg[0]
- (.C(s00_axi_aclk),
- .CE(v_cnt),
- .D(\v_cnt[0]_i_1_n_0 ),
- .Q(\v_cnt_reg_n_0_[0] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \v_cnt_reg[1]
- (.C(s00_axi_aclk),
- .CE(v_cnt),
- .D(\v_cnt[1]_i_1_n_0 ),
- .Q(\v_cnt_reg_n_0_[1] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \v_cnt_reg[2]
- (.C(s00_axi_aclk),
- .CE(v_cnt),
- .D(\v_cnt[2]_i_1_n_0 ),
- .Q(\v_cnt_reg_n_0_[2] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \v_cnt_reg[3]
- (.C(s00_axi_aclk),
- .CE(v_cnt),
- .D(\v_cnt[3]_i_1_n_0 ),
- .Q(\v_cnt_reg_n_0_[3] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \v_cnt_reg[4]
- (.C(s00_axi_aclk),
- .CE(v_cnt),
- .D(\v_cnt[4]_i_1_n_0 ),
- .Q(\v_cnt_reg_n_0_[4] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \v_cnt_reg[5]
- (.C(s00_axi_aclk),
- .CE(v_cnt),
- .D(\v_cnt[5]_i_1_n_0 ),
- .Q(\v_cnt_reg_n_0_[5] ),
- .R(SR));
- FDRE #(
- .INIT(1'b0))
- \v_cnt_reg[6]
- (.C(s00_axi_aclk),
- .CE(v_cnt),
- .D(\v_cnt[6]_i_2_n_0 ),
- .Q(\v_cnt_reg_n_0_[6] ),
- .R(SR));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (weak1, weak0) GSR = GSR_int;
- assign (weak1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.vhdl b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.vhdl
deleted file mode 100644
index 6e484c94..00000000
--- a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.vhdl
+++ /dev/null
@@ -1,108803 +0,0 @@
--- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
--- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Oct 11 12:21:17 2017
--- Host : lapte24154 running 64-bit openSUSE Leap 42.2
--- Command : write_vhdl -force -mode funcsim
--- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_sim_netlist.vhdl
--- Design : system_design_fasec_hwtest_0_0
--- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--- synthesized. This netlist cannot be used for SDF annotated simulation.
--- Device : xc7z030ffg676-2
--- --------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_axi4lite_slave is
- port (
- s00_axi_awready : out STD_LOGIC;
- s00_axi_wready : out STD_LOGIC;
- s00_axi_arready : out STD_LOGIC;
- s00_axi_bvalid : out STD_LOGIC;
- s00_axi_rvalid : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[0].[2].s_reqs_reg[2][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[0].[1].s_reqs_reg[1][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[0].[0].s_reqs_reg[0][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[0].s_reqs_reg[4][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[1].s_reqs_reg[5][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[2].s_reqs_reg[6][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[3].s_reqs_reg[7][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- CO : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[0].[2].s_reqs_reg[2][changed]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[0].[1].s_reqs_reg[1][changed]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[0].[0].s_reqs_reg[0][changed]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[1].[0].s_reqs_reg[4][changed]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[1].[1].s_reqs_reg[5][changed]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[1].[2].s_reqs_reg[6][changed]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[1].[3].s_reqs_reg[7][changed]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[0].[3].s_reqs_reg[3][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[0].[2].s_reqs_reg[2][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[0].[1].s_reqs_reg[1][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[0].[0].s_reqs_reg[0][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[0].s_reqs_reg[4][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[1].s_reqs_reg[5][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[2].s_reqs_reg[6][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[3].s_reqs_reg[7][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[0].[3].s_reqs_reg[3][changed]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[0].[2].s_reqs_reg[2][changed]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[0].[1].s_reqs_reg[1][changed]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[0].[0].s_reqs_reg[0][changed]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[1].[0].s_reqs_reg[4][changed]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[1].[1].s_reqs_reg[5][changed]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[1].[2].s_reqs_reg[6][changed]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \[1].[3].s_reqs_reg[7][changed]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_rdata_reg[23]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
- \axi_rdata_reg[10]_0\ : out STD_LOGIC;
- \axi_rdata_reg[0]_0\ : out STD_LOGIC;
- \axi_rdata_reg[2]_0\ : out STD_LOGIC;
- \axi_rdata_reg[2]_1\ : out STD_LOGIC;
- \[2].[3].s_reqs_reg[11][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[2].[2].s_reqs_reg[10][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[2].[1].s_reqs_reg[9][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[2].[0].s_reqs_reg[8][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[3].[3].s_reqs_reg[15][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[3].[2].s_reqs_reg[14][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[3].[1].s_reqs_reg[13][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[3].[0].s_reqs_reg[12][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[4].[3].s_reqs_reg[19][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[4].[2].s_reqs_reg[18][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[4].[1].s_reqs_reg[17][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[4].[0].s_reqs_reg[16][value][11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[2].[3].s_reqs_reg[11][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[2].[2].s_reqs_reg[10][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[2].[1].s_reqs_reg[9][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[2].[0].s_reqs_reg[8][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[3].[3].s_reqs_reg[15][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[3].[2].s_reqs_reg[14][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[3].[1].s_reqs_reg[13][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[3].[0].s_reqs_reg[12][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[4].[3].s_reqs_reg[19][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[4].[2].s_reqs_reg[18][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[4].[1].s_reqs_reg[17][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \[4].[0].s_reqs_reg[16][value][11]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \axi_rdata_reg[9]_0\ : out STD_LOGIC;
- \v_dout_reg[7]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
- \v_dout_reg[7]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
- \axi_rdata_reg[7]_0\ : out STD_LOGIC;
- \axi_rdata_reg[7]_1\ : out STD_LOGIC;
- \axi_rdata_reg[12]_0\ : out STD_LOGIC;
- \axi_rdata_reg[12]_1\ : out STD_LOGIC;
- \axi_rdata_reg[18]_0\ : out STD_LOGIC;
- \axi_rdata_reg[17]_0\ : out STD_LOGIC;
- \axi_rdata_reg[17]_1\ : out STD_LOGIC;
- \axi_rdata_reg[22]_0\ : out STD_LOGIC;
- \axi_rdata_reg[22]_1\ : out STD_LOGIC;
- dig_outs_i : out STD_LOGIC_VECTOR ( 0 to 0 );
- dig_out6_n : out STD_LOGIC;
- \v_dout_reg[7]_1\ : out STD_LOGIC;
- \v_dout_reg[6]\ : out STD_LOGIC;
- \v_dout_reg[5]\ : out STD_LOGIC;
- \v_dout_reg[4]\ : out STD_LOGIC;
- \v_dout_reg[7]_2\ : out STD_LOGIC;
- \v_dout_reg[6]_0\ : out STD_LOGIC;
- \v_dout_reg[5]_0\ : out STD_LOGIC;
- \v_dout_reg[4]_0\ : out STD_LOGIC;
- s00_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \[0].[3].s_reqs_reg[3][value][11]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[0].[2].s_reqs_reg[2][value][11]_1\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[0].[1].s_reqs_reg[1][value][11]_1\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[0].[0].s_reqs_reg[0][value][11]_1\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[0].s_reqs_reg[4][value][11]_1\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[1].s_reqs_reg[5][value][11]_1\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[2].s_reqs_reg[6][value][11]_1\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[3].s_reqs_reg[7][value][11]_1\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[0].[3].s_reqs_reg[3][value][11]_1\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[0].[2].s_reqs_reg[2][value][11]_2\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[0].[1].s_reqs_reg[1][value][11]_2\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[0].[0].s_reqs_reg[0][value][11]_2\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[0].s_reqs_reg[4][value][11]_2\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[1].s_reqs_reg[5][value][11]_2\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[2].s_reqs_reg[6][value][11]_2\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \[1].[3].s_reqs_reg[7][value][11]_2\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- s00_axi_wvalid : in STD_LOGIC;
- s00_axi_awvalid : in STD_LOGIC;
- s00_axi_rready : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][0]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][0]\ : in STD_LOGIC;
- gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
- \s_ins_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
- \data_o_reg[6][0]\ : in STD_LOGIC;
- \data_o_reg[1][3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
- \s_datao_fmc1[0]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
- \axi_araddr_reg[4]_rep__1_0\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][0]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][0]\ : in STD_LOGIC;
- \data_o_reg[1][3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
- \s_datao_fmc2[0]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
- \data_o_reg[6][0]_0\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][1]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][1]\ : in STD_LOGIC;
- \data_o_reg[6][1]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep__0_0\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][1]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][1]\ : in STD_LOGIC;
- \data_o_reg[6][1]_0\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][2]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][2]\ : in STD_LOGIC;
- \data_o_reg[6][2]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep__0_1\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][2]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][2]\ : in STD_LOGIC;
- \data_o_reg[6][2]_0\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][3]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][3]\ : in STD_LOGIC;
- \data_o_reg[6][3]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep__0_2\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][3]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][3]\ : in STD_LOGIC;
- \data_o_reg[6][3]_0\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][4]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][4]\ : in STD_LOGIC;
- \data_o_reg[6][4]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep__0_3\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][4]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][4]\ : in STD_LOGIC;
- \data_o_reg[6][4]_0\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][5]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][5]\ : in STD_LOGIC;
- \data_o_reg[6][5]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep__0_4\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][5]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][5]\ : in STD_LOGIC;
- \data_o_reg[6][5]_0\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][6]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][6]\ : in STD_LOGIC;
- \data_o_reg[6][6]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep__0_5\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][6]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][6]\ : in STD_LOGIC;
- \data_o_reg[6][6]_0\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][7]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][7]\ : in STD_LOGIC;
- \data_o_reg[6][7]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep__0_6\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][7]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][7]\ : in STD_LOGIC;
- \data_o_reg[6][7]_0\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][8]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][8]\ : in STD_LOGIC;
- \s_datao_fmc1[4]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \axi_araddr_reg[4]_rep__0_7\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][8]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][8]\ : in STD_LOGIC;
- \s_datao_fmc2[4]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][9]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][9]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep__0_8\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][9]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][9]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][10]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][10]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep_0\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][10]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][10]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][11]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][11]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep_1\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][11]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][11]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][12]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][12]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep_2\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][12]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][12]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][13]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][13]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep_3\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][13]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][13]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][14]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][14]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep_4\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][14]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][14]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][15]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][15]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep_5\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][15]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][15]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][16]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][16]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep_6\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][16]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][16]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][17]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][17]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep_7\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][17]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][17]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][18]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][18]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep_8\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][18]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][18]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][19]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][19]\ : in STD_LOGIC;
- \axi_araddr_reg[4]_0\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][19]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][19]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][20]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][20]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][20]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][20]\ : in STD_LOGIC;
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][20]\ : in STD_LOGIC;
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][20]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][21]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][21]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][21]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][21]\ : in STD_LOGIC;
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][21]\ : in STD_LOGIC;
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][21]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][22]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][22]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][22]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][22]\ : in STD_LOGIC;
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][22]\ : in STD_LOGIC;
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][22]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\ : in STD_LOGIC;
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\ : in STD_LOGIC;
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]_0\ : in STD_LOGIC;
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\ : in STD_LOGIC;
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\ : in STD_LOGIC;
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\ : in STD_LOGIC;
- \dac_ch_o_reg[0][31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_bready : in STD_LOGIC;
- s00_axi_arvalid : in STD_LOGIC;
- s_tick : in STD_LOGIC;
- \axi_araddr_reg[4]_1\ : in STD_LOGIC;
- \axi_araddr_reg[4]_2\ : in STD_LOGIC;
- \axi_araddr_reg[4]_3\ : in STD_LOGIC;
- \axi_araddr_reg[4]_4\ : in STD_LOGIC;
- \axi_araddr_reg[4]_5\ : in STD_LOGIC;
- \axi_araddr_reg[4]_6\ : in STD_LOGIC;
- \axi_araddr_reg[4]_7\ : in STD_LOGIC;
- \axi_araddr_reg[4]_8\ : in STD_LOGIC;
- \axi_araddr_reg[5]_0\ : in STD_LOGIC;
- \axi_araddr_reg[5]_1\ : in STD_LOGIC;
- \axi_araddr_reg[5]_2\ : in STD_LOGIC;
- \axi_araddr_reg[5]_3\ : in STD_LOGIC;
- \axi_araddr_reg[5]_4\ : in STD_LOGIC;
- \axi_araddr_reg[5]_5\ : in STD_LOGIC;
- \axi_araddr_reg[5]_6\ : in STD_LOGIC;
- \axi_araddr_reg[5]_7\ : in STD_LOGIC;
- \axi_araddr_reg[5]_8\ : in STD_LOGIC;
- \axi_araddr_reg[5]_rep_0\ : in STD_LOGIC;
- \axi_araddr_reg[5]_rep_1\ : in STD_LOGIC;
- \axi_araddr_reg[5]_rep_2\ : in STD_LOGIC;
- \axi_araddr_reg[5]_rep_3\ : in STD_LOGIC;
- \axi_araddr_reg[5]_rep_4\ : in STD_LOGIC;
- \axi_araddr_reg[5]_rep_5\ : in STD_LOGIC;
- \axi_araddr_reg[5]_rep_6\ : in STD_LOGIC;
- \axi_araddr_reg[5]_rep_7\ : in STD_LOGIC;
- \axi_araddr_reg[5]_rep_8\ : in STD_LOGIC;
- \axi_araddr_reg[5]_rep_9\ : in STD_LOGIC;
- \axi_araddr_reg[5]_rep_10\ : in STD_LOGIC;
- \dac_ch_o_reg[0][31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s00_axi_awaddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
- s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_aresetn : in STD_LOGIC;
- s00_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_axi4lite_slave : entity is "axi4lite_slave";
-end system_design_fasec_hwtest_0_0_axi4lite_slave;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_axi4lite_slave is
- signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[0].[0].s_reqs[0][changed]_i_3__0_n_0\ : STD_LOGIC;
- signal \[0].[0].s_reqs[0][changed]_i_3_n_0\ : STD_LOGIC;
- signal \[0].[0].s_reqs[0][changed]_i_4__0_n_0\ : STD_LOGIC;
- signal \[0].[0].s_reqs[0][changed]_i_4_n_0\ : STD_LOGIC;
- signal \[0].[0].s_reqs[0][changed]_i_5__0_n_0\ : STD_LOGIC;
- signal \[0].[0].s_reqs[0][changed]_i_5_n_0\ : STD_LOGIC;
- signal \[0].[0].s_reqs[0][changed]_i_6__0_n_0\ : STD_LOGIC;
- signal \[0].[0].s_reqs[0][changed]_i_6_n_0\ : STD_LOGIC;
- signal \[0].[0].s_reqs_reg[0][changed]_i_2__0_n_1\ : STD_LOGIC;
- signal \[0].[0].s_reqs_reg[0][changed]_i_2__0_n_2\ : STD_LOGIC;
- signal \[0].[0].s_reqs_reg[0][changed]_i_2__0_n_3\ : STD_LOGIC;
- signal \[0].[0].s_reqs_reg[0][changed]_i_2_n_1\ : STD_LOGIC;
- signal \[0].[0].s_reqs_reg[0][changed]_i_2_n_2\ : STD_LOGIC;
- signal \[0].[0].s_reqs_reg[0][changed]_i_2_n_3\ : STD_LOGIC;
- signal \^[0].[0].s_reqs_reg[0][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[0].[0].s_reqs_reg[0][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[0].[1].s_reqs[1][changed]_i_3__0_n_0\ : STD_LOGIC;
- signal \[0].[1].s_reqs[1][changed]_i_3_n_0\ : STD_LOGIC;
- signal \[0].[1].s_reqs[1][changed]_i_4__0_n_0\ : STD_LOGIC;
- signal \[0].[1].s_reqs[1][changed]_i_4_n_0\ : STD_LOGIC;
- signal \[0].[1].s_reqs[1][changed]_i_5__0_n_0\ : STD_LOGIC;
- signal \[0].[1].s_reqs[1][changed]_i_5_n_0\ : STD_LOGIC;
- signal \[0].[1].s_reqs[1][changed]_i_6__0_n_0\ : STD_LOGIC;
- signal \[0].[1].s_reqs[1][changed]_i_6_n_0\ : STD_LOGIC;
- signal \[0].[1].s_reqs_reg[1][changed]_i_2__0_n_1\ : STD_LOGIC;
- signal \[0].[1].s_reqs_reg[1][changed]_i_2__0_n_2\ : STD_LOGIC;
- signal \[0].[1].s_reqs_reg[1][changed]_i_2__0_n_3\ : STD_LOGIC;
- signal \[0].[1].s_reqs_reg[1][changed]_i_2_n_1\ : STD_LOGIC;
- signal \[0].[1].s_reqs_reg[1][changed]_i_2_n_2\ : STD_LOGIC;
- signal \[0].[1].s_reqs_reg[1][changed]_i_2_n_3\ : STD_LOGIC;
- signal \^[0].[1].s_reqs_reg[1][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[0].[1].s_reqs_reg[1][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[0].[2].s_reqs[2][changed]_i_3__0_n_0\ : STD_LOGIC;
- signal \[0].[2].s_reqs[2][changed]_i_3_n_0\ : STD_LOGIC;
- signal \[0].[2].s_reqs[2][changed]_i_4__0_n_0\ : STD_LOGIC;
- signal \[0].[2].s_reqs[2][changed]_i_4_n_0\ : STD_LOGIC;
- signal \[0].[2].s_reqs[2][changed]_i_5__0_n_0\ : STD_LOGIC;
- signal \[0].[2].s_reqs[2][changed]_i_5_n_0\ : STD_LOGIC;
- signal \[0].[2].s_reqs[2][changed]_i_6__0_n_0\ : STD_LOGIC;
- signal \[0].[2].s_reqs[2][changed]_i_6_n_0\ : STD_LOGIC;
- signal \[0].[2].s_reqs_reg[2][changed]_i_2__0_n_1\ : STD_LOGIC;
- signal \[0].[2].s_reqs_reg[2][changed]_i_2__0_n_2\ : STD_LOGIC;
- signal \[0].[2].s_reqs_reg[2][changed]_i_2__0_n_3\ : STD_LOGIC;
- signal \[0].[2].s_reqs_reg[2][changed]_i_2_n_1\ : STD_LOGIC;
- signal \[0].[2].s_reqs_reg[2][changed]_i_2_n_2\ : STD_LOGIC;
- signal \[0].[2].s_reqs_reg[2][changed]_i_2_n_3\ : STD_LOGIC;
- signal \^[0].[2].s_reqs_reg[2][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[0].[2].s_reqs_reg[2][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[0].[3].s_reqs[3][changed]_i_3__0_n_0\ : STD_LOGIC;
- signal \[0].[3].s_reqs[3][changed]_i_3_n_0\ : STD_LOGIC;
- signal \[0].[3].s_reqs[3][changed]_i_4__0_n_0\ : STD_LOGIC;
- signal \[0].[3].s_reqs[3][changed]_i_4_n_0\ : STD_LOGIC;
- signal \[0].[3].s_reqs[3][changed]_i_5__0_n_0\ : STD_LOGIC;
- signal \[0].[3].s_reqs[3][changed]_i_5_n_0\ : STD_LOGIC;
- signal \[0].[3].s_reqs[3][changed]_i_6__0_n_0\ : STD_LOGIC;
- signal \[0].[3].s_reqs[3][changed]_i_6_n_0\ : STD_LOGIC;
- signal \[0].[3].s_reqs_reg[3][changed]_i_2__0_n_1\ : STD_LOGIC;
- signal \[0].[3].s_reqs_reg[3][changed]_i_2__0_n_2\ : STD_LOGIC;
- signal \[0].[3].s_reqs_reg[3][changed]_i_2__0_n_3\ : STD_LOGIC;
- signal \[0].[3].s_reqs_reg[3][changed]_i_2_n_1\ : STD_LOGIC;
- signal \[0].[3].s_reqs_reg[3][changed]_i_2_n_2\ : STD_LOGIC;
- signal \[0].[3].s_reqs_reg[3][changed]_i_2_n_3\ : STD_LOGIC;
- signal \^[0].[3].s_reqs_reg[3][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[1].[0].s_reqs[4][changed]_i_3__0_n_0\ : STD_LOGIC;
- signal \[1].[0].s_reqs[4][changed]_i_3_n_0\ : STD_LOGIC;
- signal \[1].[0].s_reqs[4][changed]_i_4__0_n_0\ : STD_LOGIC;
- signal \[1].[0].s_reqs[4][changed]_i_4_n_0\ : STD_LOGIC;
- signal \[1].[0].s_reqs[4][changed]_i_5__0_n_0\ : STD_LOGIC;
- signal \[1].[0].s_reqs[4][changed]_i_5_n_0\ : STD_LOGIC;
- signal \[1].[0].s_reqs[4][changed]_i_6__0_n_0\ : STD_LOGIC;
- signal \[1].[0].s_reqs[4][changed]_i_6_n_0\ : STD_LOGIC;
- signal \[1].[0].s_reqs_reg[4][changed]_i_2__0_n_1\ : STD_LOGIC;
- signal \[1].[0].s_reqs_reg[4][changed]_i_2__0_n_2\ : STD_LOGIC;
- signal \[1].[0].s_reqs_reg[4][changed]_i_2__0_n_3\ : STD_LOGIC;
- signal \[1].[0].s_reqs_reg[4][changed]_i_2_n_1\ : STD_LOGIC;
- signal \[1].[0].s_reqs_reg[4][changed]_i_2_n_2\ : STD_LOGIC;
- signal \[1].[0].s_reqs_reg[4][changed]_i_2_n_3\ : STD_LOGIC;
- signal \^[1].[0].s_reqs_reg[4][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[1].[0].s_reqs_reg[4][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[1].[1].s_reqs[5][changed]_i_3__0_n_0\ : STD_LOGIC;
- signal \[1].[1].s_reqs[5][changed]_i_3_n_0\ : STD_LOGIC;
- signal \[1].[1].s_reqs[5][changed]_i_4__0_n_0\ : STD_LOGIC;
- signal \[1].[1].s_reqs[5][changed]_i_4_n_0\ : STD_LOGIC;
- signal \[1].[1].s_reqs[5][changed]_i_5__0_n_0\ : STD_LOGIC;
- signal \[1].[1].s_reqs[5][changed]_i_5_n_0\ : STD_LOGIC;
- signal \[1].[1].s_reqs[5][changed]_i_6__0_n_0\ : STD_LOGIC;
- signal \[1].[1].s_reqs[5][changed]_i_6_n_0\ : STD_LOGIC;
- signal \[1].[1].s_reqs_reg[5][changed]_i_2__0_n_1\ : STD_LOGIC;
- signal \[1].[1].s_reqs_reg[5][changed]_i_2__0_n_2\ : STD_LOGIC;
- signal \[1].[1].s_reqs_reg[5][changed]_i_2__0_n_3\ : STD_LOGIC;
- signal \[1].[1].s_reqs_reg[5][changed]_i_2_n_1\ : STD_LOGIC;
- signal \[1].[1].s_reqs_reg[5][changed]_i_2_n_2\ : STD_LOGIC;
- signal \[1].[1].s_reqs_reg[5][changed]_i_2_n_3\ : STD_LOGIC;
- signal \^[1].[1].s_reqs_reg[5][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[1].[1].s_reqs_reg[5][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[1].[2].s_reqs[6][changed]_i_3__0_n_0\ : STD_LOGIC;
- signal \[1].[2].s_reqs[6][changed]_i_3_n_0\ : STD_LOGIC;
- signal \[1].[2].s_reqs[6][changed]_i_4__0_n_0\ : STD_LOGIC;
- signal \[1].[2].s_reqs[6][changed]_i_4_n_0\ : STD_LOGIC;
- signal \[1].[2].s_reqs[6][changed]_i_5__0_n_0\ : STD_LOGIC;
- signal \[1].[2].s_reqs[6][changed]_i_5_n_0\ : STD_LOGIC;
- signal \[1].[2].s_reqs[6][changed]_i_6__0_n_0\ : STD_LOGIC;
- signal \[1].[2].s_reqs[6][changed]_i_6_n_0\ : STD_LOGIC;
- signal \[1].[2].s_reqs_reg[6][changed]_i_2__0_n_1\ : STD_LOGIC;
- signal \[1].[2].s_reqs_reg[6][changed]_i_2__0_n_2\ : STD_LOGIC;
- signal \[1].[2].s_reqs_reg[6][changed]_i_2__0_n_3\ : STD_LOGIC;
- signal \[1].[2].s_reqs_reg[6][changed]_i_2_n_1\ : STD_LOGIC;
- signal \[1].[2].s_reqs_reg[6][changed]_i_2_n_2\ : STD_LOGIC;
- signal \[1].[2].s_reqs_reg[6][changed]_i_2_n_3\ : STD_LOGIC;
- signal \^[1].[2].s_reqs_reg[6][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[1].[2].s_reqs_reg[6][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[1].[3].s_reqs[7][changed]_i_3__0_n_0\ : STD_LOGIC;
- signal \[1].[3].s_reqs[7][changed]_i_3_n_0\ : STD_LOGIC;
- signal \[1].[3].s_reqs[7][changed]_i_4__0_n_0\ : STD_LOGIC;
- signal \[1].[3].s_reqs[7][changed]_i_4_n_0\ : STD_LOGIC;
- signal \[1].[3].s_reqs[7][changed]_i_5__0_n_0\ : STD_LOGIC;
- signal \[1].[3].s_reqs[7][changed]_i_5_n_0\ : STD_LOGIC;
- signal \[1].[3].s_reqs[7][changed]_i_6__0_n_0\ : STD_LOGIC;
- signal \[1].[3].s_reqs[7][changed]_i_6_n_0\ : STD_LOGIC;
- signal \[1].[3].s_reqs_reg[7][changed]_i_2__0_n_1\ : STD_LOGIC;
- signal \[1].[3].s_reqs_reg[7][changed]_i_2__0_n_2\ : STD_LOGIC;
- signal \[1].[3].s_reqs_reg[7][changed]_i_2__0_n_3\ : STD_LOGIC;
- signal \[1].[3].s_reqs_reg[7][changed]_i_2_n_1\ : STD_LOGIC;
- signal \[1].[3].s_reqs_reg[7][changed]_i_2_n_2\ : STD_LOGIC;
- signal \[1].[3].s_reqs_reg[7][changed]_i_2_n_3\ : STD_LOGIC;
- signal \^[1].[3].s_reqs_reg[7][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[1].[3].s_reqs_reg[7][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[2].[0].s_reqs_reg[8][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[2].[0].s_reqs_reg[8][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[2].[1].s_reqs_reg[9][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[2].[1].s_reqs_reg[9][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[2].[2].s_reqs_reg[10][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[2].[2].s_reqs_reg[10][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[2].[3].s_reqs_reg[11][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[2].[3].s_reqs_reg[11][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[3].[0].s_reqs_reg[12][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[3].[0].s_reqs_reg[12][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[3].[1].s_reqs_reg[13][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[3].[1].s_reqs_reg[13][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[3].[2].s_reqs_reg[14][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[3].[2].s_reqs_reg[14][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[3].[3].s_reqs_reg[15][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[3].[3].s_reqs_reg[15][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[4].[0].s_reqs_reg[16][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[4].[0].s_reqs_reg[16][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[4].[1].s_reqs_reg[17][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[4].[1].s_reqs_reg[17][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[4].[2].s_reqs_reg[18][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[4].[2].s_reqs_reg[18][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[4].[3].s_reqs_reg[19][value][11]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^[4].[3].s_reqs_reg[19][value][11]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal axi_araddr : STD_LOGIC_VECTOR ( 10 downto 6 );
- signal axi_arready_i_1_n_0 : STD_LOGIC;
- signal axi_awready_i_2_n_0 : STD_LOGIC;
- signal \axi_bresp[1]_i_1_n_0\ : STD_LOGIC;
- signal \axi_bresp[1]_i_3_n_0\ : STD_LOGIC;
- signal axi_bvalid04_out : STD_LOGIC;
- signal axi_bvalid_i_1_n_0 : STD_LOGIC;
- signal \axi_rdata[0]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_44_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_45_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_44_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_45_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_16_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_38_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_16_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_38_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_16_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_38_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_15_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_21_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_38_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_21_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_22_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_4_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[24]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_21_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_22_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_4_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[25]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_21_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_22_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_4_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[26]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_21_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_22_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_4_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[27]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_21_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_22_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_4_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[28]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_21_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_22_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_4_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[29]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_44_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_45_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_21_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_22_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_4_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[30]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_15_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_21_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_22_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_4_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[31]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_44_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_45_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_44_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_45_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_44_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_45_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_44_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_45_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_44_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_45_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_14_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_1_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_29_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_30_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_31_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_32_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_33_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_34_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_35_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_36_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_37_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_39_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_5_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_8_n_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[0]_0\ : STD_LOGIC;
- signal \axi_rdata_reg[0]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[0]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[0]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[0]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[0]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[0]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[0]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[0]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[0]_i_3_n_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[10]_0\ : STD_LOGIC;
- signal \axi_rdata_reg[10]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[10]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[10]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[10]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[10]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[10]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[10]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[11]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[11]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[11]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[11]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[11]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[11]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[11]_i_3_n_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[12]_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[12]_1\ : STD_LOGIC;
- signal \axi_rdata_reg[12]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[12]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[12]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[12]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[12]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[12]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[12]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[13]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[13]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[13]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[13]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[13]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[13]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[13]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[14]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[14]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[14]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[14]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[14]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[14]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[14]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[15]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[15]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[15]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[15]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[15]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[15]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[15]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[16]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[16]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[16]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[16]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[16]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[16]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[16]_i_3_n_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[17]_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[17]_1\ : STD_LOGIC;
- signal \axi_rdata_reg[17]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[17]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[17]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[17]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[17]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[17]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[17]_i_3_n_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[18]_0\ : STD_LOGIC;
- signal \axi_rdata_reg[18]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[18]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[18]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[18]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[18]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[18]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[18]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[19]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[19]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[19]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[19]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[19]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[19]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[19]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[1]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[1]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[1]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[1]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[1]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[1]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[1]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[1]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[1]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[20]_i_15_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[20]_i_21_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[20]_i_22_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[20]_i_6_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[21]_i_15_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[21]_i_21_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[21]_i_22_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[21]_i_6_n_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[22]_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[22]_1\ : STD_LOGIC;
- signal \axi_rdata_reg[22]_i_15_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[22]_i_21_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[22]_i_22_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[22]_i_6_n_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[23]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \axi_rdata_reg[23]_i_16_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[23]_i_22_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[23]_i_23_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[23]_i_7_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[24]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[24]_i_15_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[24]_i_16_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[24]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[25]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[25]_i_15_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[25]_i_16_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[25]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[26]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[26]_i_15_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[26]_i_16_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[26]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[27]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[27]_i_15_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[27]_i_16_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[27]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[28]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[28]_i_15_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[28]_i_16_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[28]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[29]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[29]_i_15_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[29]_i_16_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[29]_i_8_n_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[2]_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[2]_1\ : STD_LOGIC;
- signal \axi_rdata_reg[2]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[2]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[2]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[2]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[2]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[2]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[2]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[2]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[2]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[30]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[30]_i_15_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[30]_i_16_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[30]_i_8_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[31]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[31]_i_16_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[31]_i_17_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[31]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[3]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[3]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[3]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[3]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[3]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[3]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[3]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[3]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[3]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[4]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[4]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[4]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[4]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[4]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[4]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[4]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[4]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[4]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[5]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[5]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[5]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[5]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[5]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[5]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[5]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[5]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[5]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[6]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[6]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[6]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[6]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[6]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[6]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[6]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[6]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[6]_i_3_n_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[7]_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[7]_1\ : STD_LOGIC;
- signal \axi_rdata_reg[7]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[7]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[7]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[7]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[7]_i_19_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[7]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[7]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[7]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[7]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[8]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[8]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[8]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[8]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[8]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[8]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[8]_i_3_n_0\ : STD_LOGIC;
- signal \^axi_rdata_reg[9]_0\ : STD_LOGIC;
- signal \axi_rdata_reg[9]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[9]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[9]_i_18_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[9]_i_20_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[9]_i_24_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[9]_i_2_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[9]_i_3_n_0\ : STD_LOGIC;
- signal \axi_rresp[1]_i_1_n_0\ : STD_LOGIC;
- signal axi_rvalid0 : STD_LOGIC;
- signal axi_rvalid_i_1_n_0 : STD_LOGIC;
- signal axi_wready_i_1_n_0 : STD_LOGIC;
- signal \data_rw_o[0]1\ : STD_LOGIC;
- signal \data_rw_o[100][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[100][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[100][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[100][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[100][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[101][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[101][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[101][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[101][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[101][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[102][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[102][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[102][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[102][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[102][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[103][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[103][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[103][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[103][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[103][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[103][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[10]\ : STD_LOGIC_VECTOR ( 7 downto 4 );
- signal \data_rw_o[10][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[10][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[10][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[10][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[10][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[11][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[11][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[11][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[11][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[11][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[16][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[16][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[16][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[16][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[16][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[16][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[17][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[17][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[17][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[17][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[17][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[17][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[18][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[18][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[18][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[18][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[18][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[19][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[19][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[19][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[19][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[19][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[19][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[20][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[20][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[20][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[20][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[20][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[21][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[21][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[21][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[21][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[21][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[22][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[22][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[22][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[22][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[22][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[23][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[23][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[23][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[23][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[23][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[23][31]_i_4_n_0\ : STD_LOGIC;
- signal \data_rw_o[23][31]_i_5_n_0\ : STD_LOGIC;
- signal \data_rw_o[23][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[24][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[24][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[24][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[24][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[24][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[25][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[25][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[25][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[25][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[25][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[26][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[26][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[26][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[26][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[26][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[27][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[27][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[27][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[27][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[27][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[28][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[28][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[28][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[28][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[28][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[29][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[29][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[29][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[29][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[29][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[30][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[30][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[30][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[30][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[30][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[31][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[31][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[31][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[31][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[31][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[31][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[32][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[32][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[32][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[32][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[32][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[32][31]_i_4_n_0\ : STD_LOGIC;
- signal \data_rw_o[32][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[33][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[33][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[33][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[33][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[33][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[33][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[34][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[34][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[34][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[34][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[34][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[35][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[35][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[35][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[35][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[35][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[35][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal \data_rw_o[3][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[3][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[3][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[3][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[3][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[3][31]_i_4_n_0\ : STD_LOGIC;
- signal \data_rw_o[3][31]_i_5_n_0\ : STD_LOGIC;
- signal \data_rw_o[3][31]_i_7_n_0\ : STD_LOGIC;
- signal \data_rw_o[3][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[78]\ : STD_LOGIC_VECTOR ( 7 downto 4 );
- signal \data_rw_o[78][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[78][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[78][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[78][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[78][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[78][31]_i_4_n_0\ : STD_LOGIC;
- signal \data_rw_o[78][31]_i_5_n_0\ : STD_LOGIC;
- signal \data_rw_o[78][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[79][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[79][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[79][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[79][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[79][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[84][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[84][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[84][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[84][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[84][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[84][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[85][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[85][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[85][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[85][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[85][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[85][31]_i_4_n_0\ : STD_LOGIC;
- signal \data_rw_o[85][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[86][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[86][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[86][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[86][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[86][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[86][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[87][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[87][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[87][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[87][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[87][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[87][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[88][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[88][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[88][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[88][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[88][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[88][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[89][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[89][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[89][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[89][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[89][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[89][31]_i_4_n_0\ : STD_LOGIC;
- signal \data_rw_o[89][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[90][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[90][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[90][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[90][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[90][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[91][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[91][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[91][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[91][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[91][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[92][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[92][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[92][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[92][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[92][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[93][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[93][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[93][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[93][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[93][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[93][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[94][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[94][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[94][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[94][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[94][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[94][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[95][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[95][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[95][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[95][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[95][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[96][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[96][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[96][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[96][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[96][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[96][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[97][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[97][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[97][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[97][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[97][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[97][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[98][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[98][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[98][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[98][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[98][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[99][15]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[99][23]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[99][31]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o[99][31]_i_2_n_0\ : STD_LOGIC;
- signal \data_rw_o[99][31]_i_3_n_0\ : STD_LOGIC;
- signal \data_rw_o[99][7]_i_1_n_0\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[100][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[101][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[102][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[103][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][0]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][10]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][11]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][1]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][2]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][3]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][8]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[10][9]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][0]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][10]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][11]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][3]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][4]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][5]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][6]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][8]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[11][9]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[16][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[17][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[18][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[19][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[20][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[21][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[22][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[23][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[24][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[25][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[26][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[27][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[28][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[29][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[30][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[31][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[32][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[33][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[34][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[35][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][10]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][11]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][2]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][3]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][4]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][5]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][6]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][7]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][8]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[3][9]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][0]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][10]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][11]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][1]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][2]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][3]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][8]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[78][9]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][0]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][10]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][11]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][3]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][4]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][5]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][6]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][8]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[79][9]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[84][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[85][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[86][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[87][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[88][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[89][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[90][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[91][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[92][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[93][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[94][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[95][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[96][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[97][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[98][31]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][12]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][13]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][14]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][15]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][16]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][17]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][18]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][19]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][20]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][21]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][22]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][23]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][24]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][25]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][26]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][27]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][28]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][29]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][30]\ : STD_LOGIC;
- signal \data_rw_o_reg_n_0_[99][31]\ : STD_LOGIC;
- signal \^s00_axi_arready\ : STD_LOGIC;
- signal \^s00_axi_awready\ : STD_LOGIC;
- signal \^s00_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s00_axi_bvalid\ : STD_LOGIC;
- signal \^s00_axi_rresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s00_axi_rvalid\ : STD_LOGIC;
- signal \^s00_axi_wready\ : STD_LOGIC;
- signal sel0 : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal \^v_dout_reg[7]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal \^v_dout_reg[7]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal \NLW_[0].[0].s_reqs_reg[0][changed]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[0].[0].s_reqs_reg[0][changed]_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[0].[1].s_reqs_reg[1][changed]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[0].[1].s_reqs_reg[1][changed]_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[0].[2].s_reqs_reg[2][changed]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[0].[2].s_reqs_reg[2][changed]_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[0].[3].s_reqs_reg[3][changed]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[0].[3].s_reqs_reg[3][changed]_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[1].[0].s_reqs_reg[4][changed]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[1].[0].s_reqs_reg[4][changed]_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[1].[1].s_reqs_reg[5][changed]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[1].[1].s_reqs_reg[5][changed]_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[1].[2].s_reqs_reg[6][changed]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[1].[2].s_reqs_reg[6][changed]_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[1].[3].s_reqs_reg[7][changed]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_[1].[3].s_reqs_reg[7][changed]_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- attribute ORIG_CELL_NAME : string;
- attribute ORIG_CELL_NAME of \axi_araddr_reg[2]\ : label is "axi_araddr_reg[2]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[2]_rep\ : label is "axi_araddr_reg[2]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[2]_rep__0\ : label is "axi_araddr_reg[2]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[2]_rep__1\ : label is "axi_araddr_reg[2]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[2]_rep__2\ : label is "axi_araddr_reg[2]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[2]_rep__3\ : label is "axi_araddr_reg[2]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[3]\ : label is "axi_araddr_reg[3]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[3]_rep\ : label is "axi_araddr_reg[3]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[3]_rep__0\ : label is "axi_araddr_reg[3]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[3]_rep__1\ : label is "axi_araddr_reg[3]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[3]_rep__2\ : label is "axi_araddr_reg[3]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[3]_rep__3\ : label is "axi_araddr_reg[3]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[4]\ : label is "axi_araddr_reg[4]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[4]_rep\ : label is "axi_araddr_reg[4]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[4]_rep__0\ : label is "axi_araddr_reg[4]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[4]_rep__1\ : label is "axi_araddr_reg[4]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[5]\ : label is "axi_araddr_reg[5]";
- attribute ORIG_CELL_NAME of \axi_araddr_reg[5]_rep\ : label is "axi_araddr_reg[5]";
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \axi_bresp[1]_i_2\ : label is "soft_lutpair1";
- attribute SOFT_HLUTNM of \axi_bresp[1]_i_3\ : label is "soft_lutpair18";
- attribute SOFT_HLUTNM of \axi_rdata[10]_i_23\ : label is "soft_lutpair2";
- attribute SOFT_HLUTNM of \axi_rdata[11]_i_23\ : label is "soft_lutpair2";
- attribute SOFT_HLUTNM of \axi_rdata[13]_i_23\ : label is "soft_lutpair7";
- attribute SOFT_HLUTNM of \axi_rdata[14]_i_23\ : label is "soft_lutpair7";
- attribute SOFT_HLUTNM of \axi_rdata[15]_i_23\ : label is "soft_lutpair8";
- attribute SOFT_HLUTNM of \axi_rdata[16]_i_14\ : label is "soft_lutpair12";
- attribute SOFT_HLUTNM of \axi_rdata[16]_i_23\ : label is "soft_lutpair8";
- attribute SOFT_HLUTNM of \axi_rdata[17]_i_23\ : label is "soft_lutpair12";
- attribute SOFT_HLUTNM of \axi_rdata[18]_i_14\ : label is "soft_lutpair13";
- attribute SOFT_HLUTNM of \axi_rdata[18]_i_23\ : label is "soft_lutpair13";
- attribute SOFT_HLUTNM of \axi_rdata[19]_i_14\ : label is "soft_lutpair11";
- attribute SOFT_HLUTNM of \axi_rdata[19]_i_23\ : label is "soft_lutpair10";
- attribute SOFT_HLUTNM of \axi_rdata[1]_i_23\ : label is "soft_lutpair6";
- attribute SOFT_HLUTNM of \axi_rdata[20]_i_14\ : label is "soft_lutpair15";
- attribute SOFT_HLUTNM of \axi_rdata[20]_i_24\ : label is "soft_lutpair11";
- attribute SOFT_HLUTNM of \axi_rdata[21]_i_14\ : label is "soft_lutpair16";
- attribute SOFT_HLUTNM of \axi_rdata[21]_i_24\ : label is "soft_lutpair15";
- attribute SOFT_HLUTNM of \axi_rdata[22]_i_14\ : label is "soft_lutpair16";
- attribute SOFT_HLUTNM of \axi_rdata[22]_i_24\ : label is "soft_lutpair10";
- attribute SOFT_HLUTNM of \axi_rdata[23]_i_15\ : label is "soft_lutpair9";
- attribute SOFT_HLUTNM of \axi_rdata[23]_i_25\ : label is "soft_lutpair9";
- attribute SOFT_HLUTNM of \axi_rdata[2]_i_23\ : label is "soft_lutpair6";
- attribute SOFT_HLUTNM of \axi_rdata[3]_i_23\ : label is "soft_lutpair4";
- attribute SOFT_HLUTNM of \axi_rdata[4]_i_23\ : label is "soft_lutpair5";
- attribute SOFT_HLUTNM of \axi_rdata[5]_i_23\ : label is "soft_lutpair5";
- attribute SOFT_HLUTNM of \axi_rdata[7]_i_23\ : label is "soft_lutpair4";
- attribute SOFT_HLUTNM of \axi_rdata[8]_i_23\ : label is "soft_lutpair3";
- attribute SOFT_HLUTNM of \axi_rdata[9]_i_23\ : label is "soft_lutpair3";
- attribute SOFT_HLUTNM of \axi_rresp[1]_i_2\ : label is "soft_lutpair17";
- attribute SOFT_HLUTNM of axi_rvalid_i_1 : label is "soft_lutpair17";
- attribute SOFT_HLUTNM of axi_wready_i_1 : label is "soft_lutpair1";
- attribute SOFT_HLUTNM of \data_rw_o[103][31]_i_3\ : label is "soft_lutpair31";
- attribute SOFT_HLUTNM of \data_rw_o[16][31]_i_3\ : label is "soft_lutpair19";
- attribute SOFT_HLUTNM of \data_rw_o[17][31]_i_3\ : label is "soft_lutpair23";
- attribute SOFT_HLUTNM of \data_rw_o[19][31]_i_3\ : label is "soft_lutpair19";
- attribute SOFT_HLUTNM of \data_rw_o[23][31]_i_3\ : label is "soft_lutpair27";
- attribute SOFT_HLUTNM of \data_rw_o[23][31]_i_4\ : label is "soft_lutpair30";
- attribute SOFT_HLUTNM of \data_rw_o[23][31]_i_5\ : label is "soft_lutpair23";
- attribute SOFT_HLUTNM of \data_rw_o[31][31]_i_3\ : label is "soft_lutpair20";
- attribute SOFT_HLUTNM of \data_rw_o[32][31]_i_3\ : label is "soft_lutpair0";
- attribute SOFT_HLUTNM of \data_rw_o[32][31]_i_4\ : label is "soft_lutpair24";
- attribute SOFT_HLUTNM of \data_rw_o[33][31]_i_3\ : label is "soft_lutpair30";
- attribute SOFT_HLUTNM of \data_rw_o[35][31]_i_3\ : label is "soft_lutpair27";
- attribute SOFT_HLUTNM of \data_rw_o[3][31]_i_4\ : label is "soft_lutpair0";
- attribute SOFT_HLUTNM of \data_rw_o[3][31]_i_7\ : label is "soft_lutpair18";
- attribute SOFT_HLUTNM of \data_rw_o[78][31]_i_3\ : label is "soft_lutpair28";
- attribute SOFT_HLUTNM of \data_rw_o[78][31]_i_4\ : label is "soft_lutpair29";
- attribute SOFT_HLUTNM of \data_rw_o[78][31]_i_5\ : label is "soft_lutpair25";
- attribute SOFT_HLUTNM of \data_rw_o[84][31]_i_3\ : label is "soft_lutpair21";
- attribute SOFT_HLUTNM of \data_rw_o[85][31]_i_3\ : label is "soft_lutpair24";
- attribute SOFT_HLUTNM of \data_rw_o[85][31]_i_4\ : label is "soft_lutpair31";
- attribute SOFT_HLUTNM of \data_rw_o[87][31]_i_3\ : label is "soft_lutpair26";
- attribute SOFT_HLUTNM of \data_rw_o[88][31]_i_3\ : label is "soft_lutpair22";
- attribute SOFT_HLUTNM of \data_rw_o[89][31]_i_3\ : label is "soft_lutpair22";
- attribute SOFT_HLUTNM of \data_rw_o[89][31]_i_4\ : label is "soft_lutpair25";
- attribute SOFT_HLUTNM of \data_rw_o[93][31]_i_3\ : label is "soft_lutpair20";
- attribute SOFT_HLUTNM of \data_rw_o[94][31]_i_3\ : label is "soft_lutpair29";
- attribute SOFT_HLUTNM of \data_rw_o[96][31]_i_3\ : label is "soft_lutpair21";
- attribute SOFT_HLUTNM of \data_rw_o[97][31]_i_3\ : label is "soft_lutpair28";
- attribute SOFT_HLUTNM of \data_rw_o[99][31]_i_3\ : label is "soft_lutpair26";
- attribute SOFT_HLUTNM of dig_out6_n_INST_0 : label is "soft_lutpair14";
- attribute SOFT_HLUTNM of \dig_outs_i[0]_INST_0\ : label is "soft_lutpair14";
- attribute SOFT_HLUTNM of \v_dout[4]_i_1\ : label is "soft_lutpair33";
- attribute SOFT_HLUTNM of \v_dout[4]_i_1__0\ : label is "soft_lutpair35";
- attribute SOFT_HLUTNM of \v_dout[5]_i_1\ : label is "soft_lutpair33";
- attribute SOFT_HLUTNM of \v_dout[5]_i_1__0\ : label is "soft_lutpair35";
- attribute SOFT_HLUTNM of \v_dout[6]_i_1\ : label is "soft_lutpair32";
- attribute SOFT_HLUTNM of \v_dout[6]_i_1__0\ : label is "soft_lutpair34";
- attribute SOFT_HLUTNM of \v_dout[7]_i_2\ : label is "soft_lutpair32";
- attribute SOFT_HLUTNM of \v_dout[7]_i_2__0\ : label is "soft_lutpair34";
-begin
- Q(11 downto 0) <= \^q\(11 downto 0);
- \[0].[0].s_reqs_reg[0][value][11]\(11 downto 0) <= \^[0].[0].s_reqs_reg[0][value][11]\(11 downto 0);
- \[0].[0].s_reqs_reg[0][value][11]_0\(11 downto 0) <= \^[0].[0].s_reqs_reg[0][value][11]_0\(11 downto 0);
- \[0].[1].s_reqs_reg[1][value][11]\(11 downto 0) <= \^[0].[1].s_reqs_reg[1][value][11]\(11 downto 0);
- \[0].[1].s_reqs_reg[1][value][11]_0\(11 downto 0) <= \^[0].[1].s_reqs_reg[1][value][11]_0\(11 downto 0);
- \[0].[2].s_reqs_reg[2][value][11]\(11 downto 0) <= \^[0].[2].s_reqs_reg[2][value][11]\(11 downto 0);
- \[0].[2].s_reqs_reg[2][value][11]_0\(11 downto 0) <= \^[0].[2].s_reqs_reg[2][value][11]_0\(11 downto 0);
- \[0].[3].s_reqs_reg[3][value][11]\(11 downto 0) <= \^[0].[3].s_reqs_reg[3][value][11]\(11 downto 0);
- \[1].[0].s_reqs_reg[4][value][11]\(11 downto 0) <= \^[1].[0].s_reqs_reg[4][value][11]\(11 downto 0);
- \[1].[0].s_reqs_reg[4][value][11]_0\(11 downto 0) <= \^[1].[0].s_reqs_reg[4][value][11]_0\(11 downto 0);
- \[1].[1].s_reqs_reg[5][value][11]\(11 downto 0) <= \^[1].[1].s_reqs_reg[5][value][11]\(11 downto 0);
- \[1].[1].s_reqs_reg[5][value][11]_0\(11 downto 0) <= \^[1].[1].s_reqs_reg[5][value][11]_0\(11 downto 0);
- \[1].[2].s_reqs_reg[6][value][11]\(11 downto 0) <= \^[1].[2].s_reqs_reg[6][value][11]\(11 downto 0);
- \[1].[2].s_reqs_reg[6][value][11]_0\(11 downto 0) <= \^[1].[2].s_reqs_reg[6][value][11]_0\(11 downto 0);
- \[1].[3].s_reqs_reg[7][value][11]\(11 downto 0) <= \^[1].[3].s_reqs_reg[7][value][11]\(11 downto 0);
- \[1].[3].s_reqs_reg[7][value][11]_0\(11 downto 0) <= \^[1].[3].s_reqs_reg[7][value][11]_0\(11 downto 0);
- \[2].[0].s_reqs_reg[8][value][11]\(11 downto 0) <= \^[2].[0].s_reqs_reg[8][value][11]\(11 downto 0);
- \[2].[0].s_reqs_reg[8][value][11]_0\(11 downto 0) <= \^[2].[0].s_reqs_reg[8][value][11]_0\(11 downto 0);
- \[2].[1].s_reqs_reg[9][value][11]\(11 downto 0) <= \^[2].[1].s_reqs_reg[9][value][11]\(11 downto 0);
- \[2].[1].s_reqs_reg[9][value][11]_0\(11 downto 0) <= \^[2].[1].s_reqs_reg[9][value][11]_0\(11 downto 0);
- \[2].[2].s_reqs_reg[10][value][11]\(11 downto 0) <= \^[2].[2].s_reqs_reg[10][value][11]\(11 downto 0);
- \[2].[2].s_reqs_reg[10][value][11]_0\(11 downto 0) <= \^[2].[2].s_reqs_reg[10][value][11]_0\(11 downto 0);
- \[2].[3].s_reqs_reg[11][value][11]\(11 downto 0) <= \^[2].[3].s_reqs_reg[11][value][11]\(11 downto 0);
- \[2].[3].s_reqs_reg[11][value][11]_0\(11 downto 0) <= \^[2].[3].s_reqs_reg[11][value][11]_0\(11 downto 0);
- \[3].[0].s_reqs_reg[12][value][11]\(11 downto 0) <= \^[3].[0].s_reqs_reg[12][value][11]\(11 downto 0);
- \[3].[0].s_reqs_reg[12][value][11]_0\(11 downto 0) <= \^[3].[0].s_reqs_reg[12][value][11]_0\(11 downto 0);
- \[3].[1].s_reqs_reg[13][value][11]\(11 downto 0) <= \^[3].[1].s_reqs_reg[13][value][11]\(11 downto 0);
- \[3].[1].s_reqs_reg[13][value][11]_0\(11 downto 0) <= \^[3].[1].s_reqs_reg[13][value][11]_0\(11 downto 0);
- \[3].[2].s_reqs_reg[14][value][11]\(11 downto 0) <= \^[3].[2].s_reqs_reg[14][value][11]\(11 downto 0);
- \[3].[2].s_reqs_reg[14][value][11]_0\(11 downto 0) <= \^[3].[2].s_reqs_reg[14][value][11]_0\(11 downto 0);
- \[3].[3].s_reqs_reg[15][value][11]\(11 downto 0) <= \^[3].[3].s_reqs_reg[15][value][11]\(11 downto 0);
- \[3].[3].s_reqs_reg[15][value][11]_0\(11 downto 0) <= \^[3].[3].s_reqs_reg[15][value][11]_0\(11 downto 0);
- \[4].[0].s_reqs_reg[16][value][11]\(11 downto 0) <= \^[4].[0].s_reqs_reg[16][value][11]\(11 downto 0);
- \[4].[0].s_reqs_reg[16][value][11]_0\(11 downto 0) <= \^[4].[0].s_reqs_reg[16][value][11]_0\(11 downto 0);
- \[4].[1].s_reqs_reg[17][value][11]\(11 downto 0) <= \^[4].[1].s_reqs_reg[17][value][11]\(11 downto 0);
- \[4].[1].s_reqs_reg[17][value][11]_0\(11 downto 0) <= \^[4].[1].s_reqs_reg[17][value][11]_0\(11 downto 0);
- \[4].[2].s_reqs_reg[18][value][11]\(11 downto 0) <= \^[4].[2].s_reqs_reg[18][value][11]\(11 downto 0);
- \[4].[2].s_reqs_reg[18][value][11]_0\(11 downto 0) <= \^[4].[2].s_reqs_reg[18][value][11]_0\(11 downto 0);
- \[4].[3].s_reqs_reg[19][value][11]\(11 downto 0) <= \^[4].[3].s_reqs_reg[19][value][11]\(11 downto 0);
- \[4].[3].s_reqs_reg[19][value][11]_0\(11 downto 0) <= \^[4].[3].s_reqs_reg[19][value][11]_0\(11 downto 0);
- \axi_rdata_reg[0]_0\ <= \^axi_rdata_reg[0]_0\;
- \axi_rdata_reg[10]_0\ <= \^axi_rdata_reg[10]_0\;
- \axi_rdata_reg[12]_0\ <= \^axi_rdata_reg[12]_0\;
- \axi_rdata_reg[12]_1\ <= \^axi_rdata_reg[12]_1\;
- \axi_rdata_reg[17]_0\ <= \^axi_rdata_reg[17]_0\;
- \axi_rdata_reg[17]_1\ <= \^axi_rdata_reg[17]_1\;
- \axi_rdata_reg[18]_0\ <= \^axi_rdata_reg[18]_0\;
- \axi_rdata_reg[22]_0\ <= \^axi_rdata_reg[22]_0\;
- \axi_rdata_reg[22]_1\ <= \^axi_rdata_reg[22]_1\;
- \axi_rdata_reg[23]_0\(3 downto 0) <= \^axi_rdata_reg[23]_0\(3 downto 0);
- \axi_rdata_reg[2]_0\ <= \^axi_rdata_reg[2]_0\;
- \axi_rdata_reg[2]_1\ <= \^axi_rdata_reg[2]_1\;
- \axi_rdata_reg[7]_0\ <= \^axi_rdata_reg[7]_0\;
- \axi_rdata_reg[7]_1\ <= \^axi_rdata_reg[7]_1\;
- \axi_rdata_reg[9]_0\ <= \^axi_rdata_reg[9]_0\;
- s00_axi_arready <= \^s00_axi_arready\;
- s00_axi_awready <= \^s00_axi_awready\;
- s00_axi_bresp(0) <= \^s00_axi_bresp\(0);
- s00_axi_bvalid <= \^s00_axi_bvalid\;
- s00_axi_rresp(0) <= \^s00_axi_rresp\(0);
- s00_axi_rvalid <= \^s00_axi_rvalid\;
- s00_axi_wready <= \^s00_axi_wready\;
- \v_dout_reg[7]\(2 downto 0) <= \^v_dout_reg[7]\(2 downto 0);
- \v_dout_reg[7]_0\(2 downto 0) <= \^v_dout_reg[7]_0\(2 downto 0);
-\[0].[0].s_reqs[0][changed]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[0].s_reqs_reg[0][value][11]\(11),
- I1 => \[0].[0].s_reqs_reg[0][value][11]_1\(11),
- I2 => \^[0].[0].s_reqs_reg[0][value][11]\(10),
- I3 => \[0].[0].s_reqs_reg[0][value][11]_1\(10),
- I4 => \[0].[0].s_reqs_reg[0][value][11]_1\(9),
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(9),
- O => \[0].[0].s_reqs[0][changed]_i_3_n_0\
- );
-\[0].[0].s_reqs[0][changed]_i_3__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[0].s_reqs_reg[0][value][11]_0\(11),
- I1 => \[0].[0].s_reqs_reg[0][value][11]_2\(11),
- I2 => \^[0].[0].s_reqs_reg[0][value][11]_0\(10),
- I3 => \[0].[0].s_reqs_reg[0][value][11]_2\(10),
- I4 => \[0].[0].s_reqs_reg[0][value][11]_2\(9),
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(9),
- O => \[0].[0].s_reqs[0][changed]_i_3__0_n_0\
- );
-\[0].[0].s_reqs[0][changed]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[0].s_reqs_reg[0][value][11]\(8),
- I1 => \[0].[0].s_reqs_reg[0][value][11]_1\(8),
- I2 => \^[0].[0].s_reqs_reg[0][value][11]\(7),
- I3 => \[0].[0].s_reqs_reg[0][value][11]_1\(7),
- I4 => \[0].[0].s_reqs_reg[0][value][11]_1\(6),
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(6),
- O => \[0].[0].s_reqs[0][changed]_i_4_n_0\
- );
-\[0].[0].s_reqs[0][changed]_i_4__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[0].s_reqs_reg[0][value][11]_0\(8),
- I1 => \[0].[0].s_reqs_reg[0][value][11]_2\(8),
- I2 => \^[0].[0].s_reqs_reg[0][value][11]_0\(7),
- I3 => \[0].[0].s_reqs_reg[0][value][11]_2\(7),
- I4 => \[0].[0].s_reqs_reg[0][value][11]_2\(6),
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(6),
- O => \[0].[0].s_reqs[0][changed]_i_4__0_n_0\
- );
-\[0].[0].s_reqs[0][changed]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[0].s_reqs_reg[0][value][11]\(5),
- I1 => \[0].[0].s_reqs_reg[0][value][11]_1\(5),
- I2 => \^[0].[0].s_reqs_reg[0][value][11]\(4),
- I3 => \[0].[0].s_reqs_reg[0][value][11]_1\(4),
- I4 => \[0].[0].s_reqs_reg[0][value][11]_1\(3),
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(3),
- O => \[0].[0].s_reqs[0][changed]_i_5_n_0\
- );
-\[0].[0].s_reqs[0][changed]_i_5__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[0].s_reqs_reg[0][value][11]_0\(5),
- I1 => \[0].[0].s_reqs_reg[0][value][11]_2\(5),
- I2 => \^[0].[0].s_reqs_reg[0][value][11]_0\(4),
- I3 => \[0].[0].s_reqs_reg[0][value][11]_2\(4),
- I4 => \[0].[0].s_reqs_reg[0][value][11]_2\(3),
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(3),
- O => \[0].[0].s_reqs[0][changed]_i_5__0_n_0\
- );
-\[0].[0].s_reqs[0][changed]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[0].s_reqs_reg[0][value][11]\(2),
- I1 => \[0].[0].s_reqs_reg[0][value][11]_1\(2),
- I2 => \^[0].[0].s_reqs_reg[0][value][11]\(1),
- I3 => \[0].[0].s_reqs_reg[0][value][11]_1\(1),
- I4 => \[0].[0].s_reqs_reg[0][value][11]_1\(0),
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(0),
- O => \[0].[0].s_reqs[0][changed]_i_6_n_0\
- );
-\[0].[0].s_reqs[0][changed]_i_6__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[0].s_reqs_reg[0][value][11]_0\(2),
- I1 => \[0].[0].s_reqs_reg[0][value][11]_2\(2),
- I2 => \^[0].[0].s_reqs_reg[0][value][11]_0\(1),
- I3 => \[0].[0].s_reqs_reg[0][value][11]_2\(1),
- I4 => \[0].[0].s_reqs_reg[0][value][11]_2\(0),
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(0),
- O => \[0].[0].s_reqs[0][changed]_i_6__0_n_0\
- );
-\[0].[0].s_reqs_reg[0][changed]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[0].[0].s_reqs_reg[0][changed]\(0),
- CO(2) => \[0].[0].s_reqs_reg[0][changed]_i_2_n_1\,
- CO(1) => \[0].[0].s_reqs_reg[0][changed]_i_2_n_2\,
- CO(0) => \[0].[0].s_reqs_reg[0][changed]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[0].[0].s_reqs_reg[0][changed]_i_2_O_UNCONNECTED\(3 downto 0),
- S(3) => \[0].[0].s_reqs[0][changed]_i_3_n_0\,
- S(2) => \[0].[0].s_reqs[0][changed]_i_4_n_0\,
- S(1) => \[0].[0].s_reqs[0][changed]_i_5_n_0\,
- S(0) => \[0].[0].s_reqs[0][changed]_i_6_n_0\
- );
-\[0].[0].s_reqs_reg[0][changed]_i_2__0\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[0].[0].s_reqs_reg[0][changed]_0\(0),
- CO(2) => \[0].[0].s_reqs_reg[0][changed]_i_2__0_n_1\,
- CO(1) => \[0].[0].s_reqs_reg[0][changed]_i_2__0_n_2\,
- CO(0) => \[0].[0].s_reqs_reg[0][changed]_i_2__0_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[0].[0].s_reqs_reg[0][changed]_i_2__0_O_UNCONNECTED\(3 downto 0),
- S(3) => \[0].[0].s_reqs[0][changed]_i_3__0_n_0\,
- S(2) => \[0].[0].s_reqs[0][changed]_i_4__0_n_0\,
- S(1) => \[0].[0].s_reqs[0][changed]_i_5__0_n_0\,
- S(0) => \[0].[0].s_reqs[0][changed]_i_6__0_n_0\
- );
-\[0].[1].s_reqs[1][changed]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[1].s_reqs_reg[1][value][11]\(11),
- I1 => \[0].[1].s_reqs_reg[1][value][11]_1\(11),
- I2 => \^[0].[1].s_reqs_reg[1][value][11]\(10),
- I3 => \[0].[1].s_reqs_reg[1][value][11]_1\(10),
- I4 => \[0].[1].s_reqs_reg[1][value][11]_1\(9),
- I5 => \^[0].[1].s_reqs_reg[1][value][11]\(9),
- O => \[0].[1].s_reqs[1][changed]_i_3_n_0\
- );
-\[0].[1].s_reqs[1][changed]_i_3__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[1].s_reqs_reg[1][value][11]_0\(11),
- I1 => \[0].[1].s_reqs_reg[1][value][11]_2\(11),
- I2 => \^[0].[1].s_reqs_reg[1][value][11]_0\(10),
- I3 => \[0].[1].s_reqs_reg[1][value][11]_2\(10),
- I4 => \[0].[1].s_reqs_reg[1][value][11]_2\(9),
- I5 => \^[0].[1].s_reqs_reg[1][value][11]_0\(9),
- O => \[0].[1].s_reqs[1][changed]_i_3__0_n_0\
- );
-\[0].[1].s_reqs[1][changed]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[1].s_reqs_reg[1][value][11]\(8),
- I1 => \[0].[1].s_reqs_reg[1][value][11]_1\(8),
- I2 => \^[0].[1].s_reqs_reg[1][value][11]\(7),
- I3 => \[0].[1].s_reqs_reg[1][value][11]_1\(7),
- I4 => \[0].[1].s_reqs_reg[1][value][11]_1\(6),
- I5 => \^[0].[1].s_reqs_reg[1][value][11]\(6),
- O => \[0].[1].s_reqs[1][changed]_i_4_n_0\
- );
-\[0].[1].s_reqs[1][changed]_i_4__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[1].s_reqs_reg[1][value][11]_0\(8),
- I1 => \[0].[1].s_reqs_reg[1][value][11]_2\(8),
- I2 => \^[0].[1].s_reqs_reg[1][value][11]_0\(7),
- I3 => \[0].[1].s_reqs_reg[1][value][11]_2\(7),
- I4 => \[0].[1].s_reqs_reg[1][value][11]_2\(6),
- I5 => \^[0].[1].s_reqs_reg[1][value][11]_0\(6),
- O => \[0].[1].s_reqs[1][changed]_i_4__0_n_0\
- );
-\[0].[1].s_reqs[1][changed]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[1].s_reqs_reg[1][value][11]\(5),
- I1 => \[0].[1].s_reqs_reg[1][value][11]_1\(5),
- I2 => \^[0].[1].s_reqs_reg[1][value][11]\(4),
- I3 => \[0].[1].s_reqs_reg[1][value][11]_1\(4),
- I4 => \[0].[1].s_reqs_reg[1][value][11]_1\(3),
- I5 => \^[0].[1].s_reqs_reg[1][value][11]\(3),
- O => \[0].[1].s_reqs[1][changed]_i_5_n_0\
- );
-\[0].[1].s_reqs[1][changed]_i_5__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[1].s_reqs_reg[1][value][11]_0\(5),
- I1 => \[0].[1].s_reqs_reg[1][value][11]_2\(5),
- I2 => \^[0].[1].s_reqs_reg[1][value][11]_0\(4),
- I3 => \[0].[1].s_reqs_reg[1][value][11]_2\(4),
- I4 => \[0].[1].s_reqs_reg[1][value][11]_2\(3),
- I5 => \^[0].[1].s_reqs_reg[1][value][11]_0\(3),
- O => \[0].[1].s_reqs[1][changed]_i_5__0_n_0\
- );
-\[0].[1].s_reqs[1][changed]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[1].s_reqs_reg[1][value][11]\(2),
- I1 => \[0].[1].s_reqs_reg[1][value][11]_1\(2),
- I2 => \^[0].[1].s_reqs_reg[1][value][11]\(1),
- I3 => \[0].[1].s_reqs_reg[1][value][11]_1\(1),
- I4 => \[0].[1].s_reqs_reg[1][value][11]_1\(0),
- I5 => \^[0].[1].s_reqs_reg[1][value][11]\(0),
- O => \[0].[1].s_reqs[1][changed]_i_6_n_0\
- );
-\[0].[1].s_reqs[1][changed]_i_6__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[1].s_reqs_reg[1][value][11]_0\(2),
- I1 => \[0].[1].s_reqs_reg[1][value][11]_2\(2),
- I2 => \^[0].[1].s_reqs_reg[1][value][11]_0\(1),
- I3 => \[0].[1].s_reqs_reg[1][value][11]_2\(1),
- I4 => \[0].[1].s_reqs_reg[1][value][11]_2\(0),
- I5 => \^[0].[1].s_reqs_reg[1][value][11]_0\(0),
- O => \[0].[1].s_reqs[1][changed]_i_6__0_n_0\
- );
-\[0].[1].s_reqs_reg[1][changed]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[0].[1].s_reqs_reg[1][changed]\(0),
- CO(2) => \[0].[1].s_reqs_reg[1][changed]_i_2_n_1\,
- CO(1) => \[0].[1].s_reqs_reg[1][changed]_i_2_n_2\,
- CO(0) => \[0].[1].s_reqs_reg[1][changed]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[0].[1].s_reqs_reg[1][changed]_i_2_O_UNCONNECTED\(3 downto 0),
- S(3) => \[0].[1].s_reqs[1][changed]_i_3_n_0\,
- S(2) => \[0].[1].s_reqs[1][changed]_i_4_n_0\,
- S(1) => \[0].[1].s_reqs[1][changed]_i_5_n_0\,
- S(0) => \[0].[1].s_reqs[1][changed]_i_6_n_0\
- );
-\[0].[1].s_reqs_reg[1][changed]_i_2__0\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[0].[1].s_reqs_reg[1][changed]_0\(0),
- CO(2) => \[0].[1].s_reqs_reg[1][changed]_i_2__0_n_1\,
- CO(1) => \[0].[1].s_reqs_reg[1][changed]_i_2__0_n_2\,
- CO(0) => \[0].[1].s_reqs_reg[1][changed]_i_2__0_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[0].[1].s_reqs_reg[1][changed]_i_2__0_O_UNCONNECTED\(3 downto 0),
- S(3) => \[0].[1].s_reqs[1][changed]_i_3__0_n_0\,
- S(2) => \[0].[1].s_reqs[1][changed]_i_4__0_n_0\,
- S(1) => \[0].[1].s_reqs[1][changed]_i_5__0_n_0\,
- S(0) => \[0].[1].s_reqs[1][changed]_i_6__0_n_0\
- );
-\[0].[2].s_reqs[2][changed]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[2].s_reqs_reg[2][value][11]\(11),
- I1 => \[0].[2].s_reqs_reg[2][value][11]_1\(11),
- I2 => \^[0].[2].s_reqs_reg[2][value][11]\(10),
- I3 => \[0].[2].s_reqs_reg[2][value][11]_1\(10),
- I4 => \[0].[2].s_reqs_reg[2][value][11]_1\(9),
- I5 => \^[0].[2].s_reqs_reg[2][value][11]\(9),
- O => \[0].[2].s_reqs[2][changed]_i_3_n_0\
- );
-\[0].[2].s_reqs[2][changed]_i_3__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[2].s_reqs_reg[2][value][11]_0\(11),
- I1 => \[0].[2].s_reqs_reg[2][value][11]_2\(11),
- I2 => \^[0].[2].s_reqs_reg[2][value][11]_0\(10),
- I3 => \[0].[2].s_reqs_reg[2][value][11]_2\(10),
- I4 => \[0].[2].s_reqs_reg[2][value][11]_2\(9),
- I5 => \^[0].[2].s_reqs_reg[2][value][11]_0\(9),
- O => \[0].[2].s_reqs[2][changed]_i_3__0_n_0\
- );
-\[0].[2].s_reqs[2][changed]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[2].s_reqs_reg[2][value][11]\(8),
- I1 => \[0].[2].s_reqs_reg[2][value][11]_1\(8),
- I2 => \^[0].[2].s_reqs_reg[2][value][11]\(7),
- I3 => \[0].[2].s_reqs_reg[2][value][11]_1\(7),
- I4 => \[0].[2].s_reqs_reg[2][value][11]_1\(6),
- I5 => \^[0].[2].s_reqs_reg[2][value][11]\(6),
- O => \[0].[2].s_reqs[2][changed]_i_4_n_0\
- );
-\[0].[2].s_reqs[2][changed]_i_4__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[2].s_reqs_reg[2][value][11]_0\(8),
- I1 => \[0].[2].s_reqs_reg[2][value][11]_2\(8),
- I2 => \^[0].[2].s_reqs_reg[2][value][11]_0\(7),
- I3 => \[0].[2].s_reqs_reg[2][value][11]_2\(7),
- I4 => \[0].[2].s_reqs_reg[2][value][11]_2\(6),
- I5 => \^[0].[2].s_reqs_reg[2][value][11]_0\(6),
- O => \[0].[2].s_reqs[2][changed]_i_4__0_n_0\
- );
-\[0].[2].s_reqs[2][changed]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[2].s_reqs_reg[2][value][11]\(5),
- I1 => \[0].[2].s_reqs_reg[2][value][11]_1\(5),
- I2 => \^[0].[2].s_reqs_reg[2][value][11]\(4),
- I3 => \[0].[2].s_reqs_reg[2][value][11]_1\(4),
- I4 => \[0].[2].s_reqs_reg[2][value][11]_1\(3),
- I5 => \^[0].[2].s_reqs_reg[2][value][11]\(3),
- O => \[0].[2].s_reqs[2][changed]_i_5_n_0\
- );
-\[0].[2].s_reqs[2][changed]_i_5__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[2].s_reqs_reg[2][value][11]_0\(5),
- I1 => \[0].[2].s_reqs_reg[2][value][11]_2\(5),
- I2 => \^[0].[2].s_reqs_reg[2][value][11]_0\(4),
- I3 => \[0].[2].s_reqs_reg[2][value][11]_2\(4),
- I4 => \[0].[2].s_reqs_reg[2][value][11]_2\(3),
- I5 => \^[0].[2].s_reqs_reg[2][value][11]_0\(3),
- O => \[0].[2].s_reqs[2][changed]_i_5__0_n_0\
- );
-\[0].[2].s_reqs[2][changed]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[2].s_reqs_reg[2][value][11]\(2),
- I1 => \[0].[2].s_reqs_reg[2][value][11]_1\(2),
- I2 => \^[0].[2].s_reqs_reg[2][value][11]\(1),
- I3 => \[0].[2].s_reqs_reg[2][value][11]_1\(1),
- I4 => \[0].[2].s_reqs_reg[2][value][11]_1\(0),
- I5 => \^[0].[2].s_reqs_reg[2][value][11]\(0),
- O => \[0].[2].s_reqs[2][changed]_i_6_n_0\
- );
-\[0].[2].s_reqs[2][changed]_i_6__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[2].s_reqs_reg[2][value][11]_0\(2),
- I1 => \[0].[2].s_reqs_reg[2][value][11]_2\(2),
- I2 => \^[0].[2].s_reqs_reg[2][value][11]_0\(1),
- I3 => \[0].[2].s_reqs_reg[2][value][11]_2\(1),
- I4 => \[0].[2].s_reqs_reg[2][value][11]_2\(0),
- I5 => \^[0].[2].s_reqs_reg[2][value][11]_0\(0),
- O => \[0].[2].s_reqs[2][changed]_i_6__0_n_0\
- );
-\[0].[2].s_reqs_reg[2][changed]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[0].[2].s_reqs_reg[2][changed]\(0),
- CO(2) => \[0].[2].s_reqs_reg[2][changed]_i_2_n_1\,
- CO(1) => \[0].[2].s_reqs_reg[2][changed]_i_2_n_2\,
- CO(0) => \[0].[2].s_reqs_reg[2][changed]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[0].[2].s_reqs_reg[2][changed]_i_2_O_UNCONNECTED\(3 downto 0),
- S(3) => \[0].[2].s_reqs[2][changed]_i_3_n_0\,
- S(2) => \[0].[2].s_reqs[2][changed]_i_4_n_0\,
- S(1) => \[0].[2].s_reqs[2][changed]_i_5_n_0\,
- S(0) => \[0].[2].s_reqs[2][changed]_i_6_n_0\
- );
-\[0].[2].s_reqs_reg[2][changed]_i_2__0\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[0].[2].s_reqs_reg[2][changed]_0\(0),
- CO(2) => \[0].[2].s_reqs_reg[2][changed]_i_2__0_n_1\,
- CO(1) => \[0].[2].s_reqs_reg[2][changed]_i_2__0_n_2\,
- CO(0) => \[0].[2].s_reqs_reg[2][changed]_i_2__0_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[0].[2].s_reqs_reg[2][changed]_i_2__0_O_UNCONNECTED\(3 downto 0),
- S(3) => \[0].[2].s_reqs[2][changed]_i_3__0_n_0\,
- S(2) => \[0].[2].s_reqs[2][changed]_i_4__0_n_0\,
- S(1) => \[0].[2].s_reqs[2][changed]_i_5__0_n_0\,
- S(0) => \[0].[2].s_reqs[2][changed]_i_6__0_n_0\
- );
-\[0].[3].s_reqs[3][changed]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^q\(11),
- I1 => \[0].[3].s_reqs_reg[3][value][11]_0\(11),
- I2 => \^q\(10),
- I3 => \[0].[3].s_reqs_reg[3][value][11]_0\(10),
- I4 => \[0].[3].s_reqs_reg[3][value][11]_0\(9),
- I5 => \^q\(9),
- O => \[0].[3].s_reqs[3][changed]_i_3_n_0\
- );
-\[0].[3].s_reqs[3][changed]_i_3__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(11),
- I1 => \[0].[3].s_reqs_reg[3][value][11]_1\(11),
- I2 => \^[0].[3].s_reqs_reg[3][value][11]\(10),
- I3 => \[0].[3].s_reqs_reg[3][value][11]_1\(10),
- I4 => \[0].[3].s_reqs_reg[3][value][11]_1\(9),
- I5 => \^[0].[3].s_reqs_reg[3][value][11]\(9),
- O => \[0].[3].s_reqs[3][changed]_i_3__0_n_0\
- );
-\[0].[3].s_reqs[3][changed]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^q\(8),
- I1 => \[0].[3].s_reqs_reg[3][value][11]_0\(8),
- I2 => \^q\(7),
- I3 => \[0].[3].s_reqs_reg[3][value][11]_0\(7),
- I4 => \[0].[3].s_reqs_reg[3][value][11]_0\(6),
- I5 => \^q\(6),
- O => \[0].[3].s_reqs[3][changed]_i_4_n_0\
- );
-\[0].[3].s_reqs[3][changed]_i_4__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(8),
- I1 => \[0].[3].s_reqs_reg[3][value][11]_1\(8),
- I2 => \^[0].[3].s_reqs_reg[3][value][11]\(7),
- I3 => \[0].[3].s_reqs_reg[3][value][11]_1\(7),
- I4 => \[0].[3].s_reqs_reg[3][value][11]_1\(6),
- I5 => \^[0].[3].s_reqs_reg[3][value][11]\(6),
- O => \[0].[3].s_reqs[3][changed]_i_4__0_n_0\
- );
-\[0].[3].s_reqs[3][changed]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^q\(5),
- I1 => \[0].[3].s_reqs_reg[3][value][11]_0\(5),
- I2 => \^q\(4),
- I3 => \[0].[3].s_reqs_reg[3][value][11]_0\(4),
- I4 => \[0].[3].s_reqs_reg[3][value][11]_0\(3),
- I5 => \^q\(3),
- O => \[0].[3].s_reqs[3][changed]_i_5_n_0\
- );
-\[0].[3].s_reqs[3][changed]_i_5__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(5),
- I1 => \[0].[3].s_reqs_reg[3][value][11]_1\(5),
- I2 => \^[0].[3].s_reqs_reg[3][value][11]\(4),
- I3 => \[0].[3].s_reqs_reg[3][value][11]_1\(4),
- I4 => \[0].[3].s_reqs_reg[3][value][11]_1\(3),
- I5 => \^[0].[3].s_reqs_reg[3][value][11]\(3),
- O => \[0].[3].s_reqs[3][changed]_i_5__0_n_0\
- );
-\[0].[3].s_reqs[3][changed]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^q\(2),
- I1 => \[0].[3].s_reqs_reg[3][value][11]_0\(2),
- I2 => \^q\(1),
- I3 => \[0].[3].s_reqs_reg[3][value][11]_0\(1),
- I4 => \[0].[3].s_reqs_reg[3][value][11]_0\(0),
- I5 => \^q\(0),
- O => \[0].[3].s_reqs[3][changed]_i_6_n_0\
- );
-\[0].[3].s_reqs[3][changed]_i_6__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(2),
- I1 => \[0].[3].s_reqs_reg[3][value][11]_1\(2),
- I2 => \^[0].[3].s_reqs_reg[3][value][11]\(1),
- I3 => \[0].[3].s_reqs_reg[3][value][11]_1\(1),
- I4 => \[0].[3].s_reqs_reg[3][value][11]_1\(0),
- I5 => \^[0].[3].s_reqs_reg[3][value][11]\(0),
- O => \[0].[3].s_reqs[3][changed]_i_6__0_n_0\
- );
-\[0].[3].s_reqs_reg[3][changed]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => CO(0),
- CO(2) => \[0].[3].s_reqs_reg[3][changed]_i_2_n_1\,
- CO(1) => \[0].[3].s_reqs_reg[3][changed]_i_2_n_2\,
- CO(0) => \[0].[3].s_reqs_reg[3][changed]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[0].[3].s_reqs_reg[3][changed]_i_2_O_UNCONNECTED\(3 downto 0),
- S(3) => \[0].[3].s_reqs[3][changed]_i_3_n_0\,
- S(2) => \[0].[3].s_reqs[3][changed]_i_4_n_0\,
- S(1) => \[0].[3].s_reqs[3][changed]_i_5_n_0\,
- S(0) => \[0].[3].s_reqs[3][changed]_i_6_n_0\
- );
-\[0].[3].s_reqs_reg[3][changed]_i_2__0\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[0].[3].s_reqs_reg[3][changed]\(0),
- CO(2) => \[0].[3].s_reqs_reg[3][changed]_i_2__0_n_1\,
- CO(1) => \[0].[3].s_reqs_reg[3][changed]_i_2__0_n_2\,
- CO(0) => \[0].[3].s_reqs_reg[3][changed]_i_2__0_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[0].[3].s_reqs_reg[3][changed]_i_2__0_O_UNCONNECTED\(3 downto 0),
- S(3) => \[0].[3].s_reqs[3][changed]_i_3__0_n_0\,
- S(2) => \[0].[3].s_reqs[3][changed]_i_4__0_n_0\,
- S(1) => \[0].[3].s_reqs[3][changed]_i_5__0_n_0\,
- S(0) => \[0].[3].s_reqs[3][changed]_i_6__0_n_0\
- );
-\[1].[0].s_reqs[4][changed]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[0].s_reqs_reg[4][value][11]\(11),
- I1 => \[1].[0].s_reqs_reg[4][value][11]_1\(11),
- I2 => \^[1].[0].s_reqs_reg[4][value][11]\(10),
- I3 => \[1].[0].s_reqs_reg[4][value][11]_1\(10),
- I4 => \[1].[0].s_reqs_reg[4][value][11]_1\(9),
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(9),
- O => \[1].[0].s_reqs[4][changed]_i_3_n_0\
- );
-\[1].[0].s_reqs[4][changed]_i_3__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[0].s_reqs_reg[4][value][11]_0\(11),
- I1 => \[1].[0].s_reqs_reg[4][value][11]_2\(11),
- I2 => \^[1].[0].s_reqs_reg[4][value][11]_0\(10),
- I3 => \[1].[0].s_reqs_reg[4][value][11]_2\(10),
- I4 => \[1].[0].s_reqs_reg[4][value][11]_2\(9),
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(9),
- O => \[1].[0].s_reqs[4][changed]_i_3__0_n_0\
- );
-\[1].[0].s_reqs[4][changed]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[0].s_reqs_reg[4][value][11]\(8),
- I1 => \[1].[0].s_reqs_reg[4][value][11]_1\(8),
- I2 => \^[1].[0].s_reqs_reg[4][value][11]\(7),
- I3 => \[1].[0].s_reqs_reg[4][value][11]_1\(7),
- I4 => \[1].[0].s_reqs_reg[4][value][11]_1\(6),
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(6),
- O => \[1].[0].s_reqs[4][changed]_i_4_n_0\
- );
-\[1].[0].s_reqs[4][changed]_i_4__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[0].s_reqs_reg[4][value][11]_0\(8),
- I1 => \[1].[0].s_reqs_reg[4][value][11]_2\(8),
- I2 => \^[1].[0].s_reqs_reg[4][value][11]_0\(7),
- I3 => \[1].[0].s_reqs_reg[4][value][11]_2\(7),
- I4 => \[1].[0].s_reqs_reg[4][value][11]_2\(6),
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(6),
- O => \[1].[0].s_reqs[4][changed]_i_4__0_n_0\
- );
-\[1].[0].s_reqs[4][changed]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[0].s_reqs_reg[4][value][11]\(5),
- I1 => \[1].[0].s_reqs_reg[4][value][11]_1\(5),
- I2 => \^[1].[0].s_reqs_reg[4][value][11]\(4),
- I3 => \[1].[0].s_reqs_reg[4][value][11]_1\(4),
- I4 => \[1].[0].s_reqs_reg[4][value][11]_1\(3),
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(3),
- O => \[1].[0].s_reqs[4][changed]_i_5_n_0\
- );
-\[1].[0].s_reqs[4][changed]_i_5__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[0].s_reqs_reg[4][value][11]_0\(5),
- I1 => \[1].[0].s_reqs_reg[4][value][11]_2\(5),
- I2 => \^[1].[0].s_reqs_reg[4][value][11]_0\(4),
- I3 => \[1].[0].s_reqs_reg[4][value][11]_2\(4),
- I4 => \[1].[0].s_reqs_reg[4][value][11]_2\(3),
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(3),
- O => \[1].[0].s_reqs[4][changed]_i_5__0_n_0\
- );
-\[1].[0].s_reqs[4][changed]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[0].s_reqs_reg[4][value][11]\(2),
- I1 => \[1].[0].s_reqs_reg[4][value][11]_1\(2),
- I2 => \^[1].[0].s_reqs_reg[4][value][11]\(1),
- I3 => \[1].[0].s_reqs_reg[4][value][11]_1\(1),
- I4 => \[1].[0].s_reqs_reg[4][value][11]_1\(0),
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(0),
- O => \[1].[0].s_reqs[4][changed]_i_6_n_0\
- );
-\[1].[0].s_reqs[4][changed]_i_6__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[0].s_reqs_reg[4][value][11]_0\(2),
- I1 => \[1].[0].s_reqs_reg[4][value][11]_2\(2),
- I2 => \^[1].[0].s_reqs_reg[4][value][11]_0\(1),
- I3 => \[1].[0].s_reqs_reg[4][value][11]_2\(1),
- I4 => \[1].[0].s_reqs_reg[4][value][11]_2\(0),
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(0),
- O => \[1].[0].s_reqs[4][changed]_i_6__0_n_0\
- );
-\[1].[0].s_reqs_reg[4][changed]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[1].[0].s_reqs_reg[4][changed]\(0),
- CO(2) => \[1].[0].s_reqs_reg[4][changed]_i_2_n_1\,
- CO(1) => \[1].[0].s_reqs_reg[4][changed]_i_2_n_2\,
- CO(0) => \[1].[0].s_reqs_reg[4][changed]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[1].[0].s_reqs_reg[4][changed]_i_2_O_UNCONNECTED\(3 downto 0),
- S(3) => \[1].[0].s_reqs[4][changed]_i_3_n_0\,
- S(2) => \[1].[0].s_reqs[4][changed]_i_4_n_0\,
- S(1) => \[1].[0].s_reqs[4][changed]_i_5_n_0\,
- S(0) => \[1].[0].s_reqs[4][changed]_i_6_n_0\
- );
-\[1].[0].s_reqs_reg[4][changed]_i_2__0\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[1].[0].s_reqs_reg[4][changed]_0\(0),
- CO(2) => \[1].[0].s_reqs_reg[4][changed]_i_2__0_n_1\,
- CO(1) => \[1].[0].s_reqs_reg[4][changed]_i_2__0_n_2\,
- CO(0) => \[1].[0].s_reqs_reg[4][changed]_i_2__0_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[1].[0].s_reqs_reg[4][changed]_i_2__0_O_UNCONNECTED\(3 downto 0),
- S(3) => \[1].[0].s_reqs[4][changed]_i_3__0_n_0\,
- S(2) => \[1].[0].s_reqs[4][changed]_i_4__0_n_0\,
- S(1) => \[1].[0].s_reqs[4][changed]_i_5__0_n_0\,
- S(0) => \[1].[0].s_reqs[4][changed]_i_6__0_n_0\
- );
-\[1].[1].s_reqs[5][changed]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[1].s_reqs_reg[5][value][11]\(11),
- I1 => \[1].[1].s_reqs_reg[5][value][11]_1\(11),
- I2 => \^[1].[1].s_reqs_reg[5][value][11]\(10),
- I3 => \[1].[1].s_reqs_reg[5][value][11]_1\(10),
- I4 => \[1].[1].s_reqs_reg[5][value][11]_1\(9),
- I5 => \^[1].[1].s_reqs_reg[5][value][11]\(9),
- O => \[1].[1].s_reqs[5][changed]_i_3_n_0\
- );
-\[1].[1].s_reqs[5][changed]_i_3__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[1].s_reqs_reg[5][value][11]_0\(11),
- I1 => \[1].[1].s_reqs_reg[5][value][11]_2\(11),
- I2 => \^[1].[1].s_reqs_reg[5][value][11]_0\(10),
- I3 => \[1].[1].s_reqs_reg[5][value][11]_2\(10),
- I4 => \[1].[1].s_reqs_reg[5][value][11]_2\(9),
- I5 => \^[1].[1].s_reqs_reg[5][value][11]_0\(9),
- O => \[1].[1].s_reqs[5][changed]_i_3__0_n_0\
- );
-\[1].[1].s_reqs[5][changed]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[1].s_reqs_reg[5][value][11]\(8),
- I1 => \[1].[1].s_reqs_reg[5][value][11]_1\(8),
- I2 => \^[1].[1].s_reqs_reg[5][value][11]\(7),
- I3 => \[1].[1].s_reqs_reg[5][value][11]_1\(7),
- I4 => \[1].[1].s_reqs_reg[5][value][11]_1\(6),
- I5 => \^[1].[1].s_reqs_reg[5][value][11]\(6),
- O => \[1].[1].s_reqs[5][changed]_i_4_n_0\
- );
-\[1].[1].s_reqs[5][changed]_i_4__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[1].s_reqs_reg[5][value][11]_0\(8),
- I1 => \[1].[1].s_reqs_reg[5][value][11]_2\(8),
- I2 => \^[1].[1].s_reqs_reg[5][value][11]_0\(7),
- I3 => \[1].[1].s_reqs_reg[5][value][11]_2\(7),
- I4 => \[1].[1].s_reqs_reg[5][value][11]_2\(6),
- I5 => \^[1].[1].s_reqs_reg[5][value][11]_0\(6),
- O => \[1].[1].s_reqs[5][changed]_i_4__0_n_0\
- );
-\[1].[1].s_reqs[5][changed]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[1].s_reqs_reg[5][value][11]\(5),
- I1 => \[1].[1].s_reqs_reg[5][value][11]_1\(5),
- I2 => \^[1].[1].s_reqs_reg[5][value][11]\(4),
- I3 => \[1].[1].s_reqs_reg[5][value][11]_1\(4),
- I4 => \[1].[1].s_reqs_reg[5][value][11]_1\(3),
- I5 => \^[1].[1].s_reqs_reg[5][value][11]\(3),
- O => \[1].[1].s_reqs[5][changed]_i_5_n_0\
- );
-\[1].[1].s_reqs[5][changed]_i_5__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[1].s_reqs_reg[5][value][11]_0\(5),
- I1 => \[1].[1].s_reqs_reg[5][value][11]_2\(5),
- I2 => \^[1].[1].s_reqs_reg[5][value][11]_0\(4),
- I3 => \[1].[1].s_reqs_reg[5][value][11]_2\(4),
- I4 => \[1].[1].s_reqs_reg[5][value][11]_2\(3),
- I5 => \^[1].[1].s_reqs_reg[5][value][11]_0\(3),
- O => \[1].[1].s_reqs[5][changed]_i_5__0_n_0\
- );
-\[1].[1].s_reqs[5][changed]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[1].s_reqs_reg[5][value][11]\(2),
- I1 => \[1].[1].s_reqs_reg[5][value][11]_1\(2),
- I2 => \^[1].[1].s_reqs_reg[5][value][11]\(1),
- I3 => \[1].[1].s_reqs_reg[5][value][11]_1\(1),
- I4 => \[1].[1].s_reqs_reg[5][value][11]_1\(0),
- I5 => \^[1].[1].s_reqs_reg[5][value][11]\(0),
- O => \[1].[1].s_reqs[5][changed]_i_6_n_0\
- );
-\[1].[1].s_reqs[5][changed]_i_6__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[1].s_reqs_reg[5][value][11]_0\(2),
- I1 => \[1].[1].s_reqs_reg[5][value][11]_2\(2),
- I2 => \^[1].[1].s_reqs_reg[5][value][11]_0\(1),
- I3 => \[1].[1].s_reqs_reg[5][value][11]_2\(1),
- I4 => \[1].[1].s_reqs_reg[5][value][11]_2\(0),
- I5 => \^[1].[1].s_reqs_reg[5][value][11]_0\(0),
- O => \[1].[1].s_reqs[5][changed]_i_6__0_n_0\
- );
-\[1].[1].s_reqs_reg[5][changed]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[1].[1].s_reqs_reg[5][changed]\(0),
- CO(2) => \[1].[1].s_reqs_reg[5][changed]_i_2_n_1\,
- CO(1) => \[1].[1].s_reqs_reg[5][changed]_i_2_n_2\,
- CO(0) => \[1].[1].s_reqs_reg[5][changed]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[1].[1].s_reqs_reg[5][changed]_i_2_O_UNCONNECTED\(3 downto 0),
- S(3) => \[1].[1].s_reqs[5][changed]_i_3_n_0\,
- S(2) => \[1].[1].s_reqs[5][changed]_i_4_n_0\,
- S(1) => \[1].[1].s_reqs[5][changed]_i_5_n_0\,
- S(0) => \[1].[1].s_reqs[5][changed]_i_6_n_0\
- );
-\[1].[1].s_reqs_reg[5][changed]_i_2__0\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[1].[1].s_reqs_reg[5][changed]_0\(0),
- CO(2) => \[1].[1].s_reqs_reg[5][changed]_i_2__0_n_1\,
- CO(1) => \[1].[1].s_reqs_reg[5][changed]_i_2__0_n_2\,
- CO(0) => \[1].[1].s_reqs_reg[5][changed]_i_2__0_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[1].[1].s_reqs_reg[5][changed]_i_2__0_O_UNCONNECTED\(3 downto 0),
- S(3) => \[1].[1].s_reqs[5][changed]_i_3__0_n_0\,
- S(2) => \[1].[1].s_reqs[5][changed]_i_4__0_n_0\,
- S(1) => \[1].[1].s_reqs[5][changed]_i_5__0_n_0\,
- S(0) => \[1].[1].s_reqs[5][changed]_i_6__0_n_0\
- );
-\[1].[2].s_reqs[6][changed]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[2].s_reqs_reg[6][value][11]\(11),
- I1 => \[1].[2].s_reqs_reg[6][value][11]_1\(11),
- I2 => \^[1].[2].s_reqs_reg[6][value][11]\(10),
- I3 => \[1].[2].s_reqs_reg[6][value][11]_1\(10),
- I4 => \[1].[2].s_reqs_reg[6][value][11]_1\(9),
- I5 => \^[1].[2].s_reqs_reg[6][value][11]\(9),
- O => \[1].[2].s_reqs[6][changed]_i_3_n_0\
- );
-\[1].[2].s_reqs[6][changed]_i_3__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[2].s_reqs_reg[6][value][11]_0\(11),
- I1 => \[1].[2].s_reqs_reg[6][value][11]_2\(11),
- I2 => \^[1].[2].s_reqs_reg[6][value][11]_0\(10),
- I3 => \[1].[2].s_reqs_reg[6][value][11]_2\(10),
- I4 => \[1].[2].s_reqs_reg[6][value][11]_2\(9),
- I5 => \^[1].[2].s_reqs_reg[6][value][11]_0\(9),
- O => \[1].[2].s_reqs[6][changed]_i_3__0_n_0\
- );
-\[1].[2].s_reqs[6][changed]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[2].s_reqs_reg[6][value][11]\(8),
- I1 => \[1].[2].s_reqs_reg[6][value][11]_1\(8),
- I2 => \^[1].[2].s_reqs_reg[6][value][11]\(7),
- I3 => \[1].[2].s_reqs_reg[6][value][11]_1\(7),
- I4 => \[1].[2].s_reqs_reg[6][value][11]_1\(6),
- I5 => \^[1].[2].s_reqs_reg[6][value][11]\(6),
- O => \[1].[2].s_reqs[6][changed]_i_4_n_0\
- );
-\[1].[2].s_reqs[6][changed]_i_4__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[2].s_reqs_reg[6][value][11]_0\(8),
- I1 => \[1].[2].s_reqs_reg[6][value][11]_2\(8),
- I2 => \^[1].[2].s_reqs_reg[6][value][11]_0\(7),
- I3 => \[1].[2].s_reqs_reg[6][value][11]_2\(7),
- I4 => \[1].[2].s_reqs_reg[6][value][11]_2\(6),
- I5 => \^[1].[2].s_reqs_reg[6][value][11]_0\(6),
- O => \[1].[2].s_reqs[6][changed]_i_4__0_n_0\
- );
-\[1].[2].s_reqs[6][changed]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[2].s_reqs_reg[6][value][11]\(5),
- I1 => \[1].[2].s_reqs_reg[6][value][11]_1\(5),
- I2 => \^[1].[2].s_reqs_reg[6][value][11]\(4),
- I3 => \[1].[2].s_reqs_reg[6][value][11]_1\(4),
- I4 => \[1].[2].s_reqs_reg[6][value][11]_1\(3),
- I5 => \^[1].[2].s_reqs_reg[6][value][11]\(3),
- O => \[1].[2].s_reqs[6][changed]_i_5_n_0\
- );
-\[1].[2].s_reqs[6][changed]_i_5__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[2].s_reqs_reg[6][value][11]_0\(5),
- I1 => \[1].[2].s_reqs_reg[6][value][11]_2\(5),
- I2 => \^[1].[2].s_reqs_reg[6][value][11]_0\(4),
- I3 => \[1].[2].s_reqs_reg[6][value][11]_2\(4),
- I4 => \[1].[2].s_reqs_reg[6][value][11]_2\(3),
- I5 => \^[1].[2].s_reqs_reg[6][value][11]_0\(3),
- O => \[1].[2].s_reqs[6][changed]_i_5__0_n_0\
- );
-\[1].[2].s_reqs[6][changed]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[2].s_reqs_reg[6][value][11]\(2),
- I1 => \[1].[2].s_reqs_reg[6][value][11]_1\(2),
- I2 => \^[1].[2].s_reqs_reg[6][value][11]\(1),
- I3 => \[1].[2].s_reqs_reg[6][value][11]_1\(1),
- I4 => \[1].[2].s_reqs_reg[6][value][11]_1\(0),
- I5 => \^[1].[2].s_reqs_reg[6][value][11]\(0),
- O => \[1].[2].s_reqs[6][changed]_i_6_n_0\
- );
-\[1].[2].s_reqs[6][changed]_i_6__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[2].s_reqs_reg[6][value][11]_0\(2),
- I1 => \[1].[2].s_reqs_reg[6][value][11]_2\(2),
- I2 => \^[1].[2].s_reqs_reg[6][value][11]_0\(1),
- I3 => \[1].[2].s_reqs_reg[6][value][11]_2\(1),
- I4 => \[1].[2].s_reqs_reg[6][value][11]_2\(0),
- I5 => \^[1].[2].s_reqs_reg[6][value][11]_0\(0),
- O => \[1].[2].s_reqs[6][changed]_i_6__0_n_0\
- );
-\[1].[2].s_reqs_reg[6][changed]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[1].[2].s_reqs_reg[6][changed]\(0),
- CO(2) => \[1].[2].s_reqs_reg[6][changed]_i_2_n_1\,
- CO(1) => \[1].[2].s_reqs_reg[6][changed]_i_2_n_2\,
- CO(0) => \[1].[2].s_reqs_reg[6][changed]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[1].[2].s_reqs_reg[6][changed]_i_2_O_UNCONNECTED\(3 downto 0),
- S(3) => \[1].[2].s_reqs[6][changed]_i_3_n_0\,
- S(2) => \[1].[2].s_reqs[6][changed]_i_4_n_0\,
- S(1) => \[1].[2].s_reqs[6][changed]_i_5_n_0\,
- S(0) => \[1].[2].s_reqs[6][changed]_i_6_n_0\
- );
-\[1].[2].s_reqs_reg[6][changed]_i_2__0\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[1].[2].s_reqs_reg[6][changed]_0\(0),
- CO(2) => \[1].[2].s_reqs_reg[6][changed]_i_2__0_n_1\,
- CO(1) => \[1].[2].s_reqs_reg[6][changed]_i_2__0_n_2\,
- CO(0) => \[1].[2].s_reqs_reg[6][changed]_i_2__0_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[1].[2].s_reqs_reg[6][changed]_i_2__0_O_UNCONNECTED\(3 downto 0),
- S(3) => \[1].[2].s_reqs[6][changed]_i_3__0_n_0\,
- S(2) => \[1].[2].s_reqs[6][changed]_i_4__0_n_0\,
- S(1) => \[1].[2].s_reqs[6][changed]_i_5__0_n_0\,
- S(0) => \[1].[2].s_reqs[6][changed]_i_6__0_n_0\
- );
-\[1].[3].s_reqs[7][changed]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(11),
- I1 => \[1].[3].s_reqs_reg[7][value][11]_1\(11),
- I2 => \^[1].[3].s_reqs_reg[7][value][11]\(10),
- I3 => \[1].[3].s_reqs_reg[7][value][11]_1\(10),
- I4 => \[1].[3].s_reqs_reg[7][value][11]_1\(9),
- I5 => \^[1].[3].s_reqs_reg[7][value][11]\(9),
- O => \[1].[3].s_reqs[7][changed]_i_3_n_0\
- );
-\[1].[3].s_reqs[7][changed]_i_3__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(11),
- I1 => \[1].[3].s_reqs_reg[7][value][11]_2\(11),
- I2 => \^[1].[3].s_reqs_reg[7][value][11]_0\(10),
- I3 => \[1].[3].s_reqs_reg[7][value][11]_2\(10),
- I4 => \[1].[3].s_reqs_reg[7][value][11]_2\(9),
- I5 => \^[1].[3].s_reqs_reg[7][value][11]_0\(9),
- O => \[1].[3].s_reqs[7][changed]_i_3__0_n_0\
- );
-\[1].[3].s_reqs[7][changed]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(8),
- I1 => \[1].[3].s_reqs_reg[7][value][11]_1\(8),
- I2 => \^[1].[3].s_reqs_reg[7][value][11]\(7),
- I3 => \[1].[3].s_reqs_reg[7][value][11]_1\(7),
- I4 => \[1].[3].s_reqs_reg[7][value][11]_1\(6),
- I5 => \^[1].[3].s_reqs_reg[7][value][11]\(6),
- O => \[1].[3].s_reqs[7][changed]_i_4_n_0\
- );
-\[1].[3].s_reqs[7][changed]_i_4__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(8),
- I1 => \[1].[3].s_reqs_reg[7][value][11]_2\(8),
- I2 => \^[1].[3].s_reqs_reg[7][value][11]_0\(7),
- I3 => \[1].[3].s_reqs_reg[7][value][11]_2\(7),
- I4 => \[1].[3].s_reqs_reg[7][value][11]_2\(6),
- I5 => \^[1].[3].s_reqs_reg[7][value][11]_0\(6),
- O => \[1].[3].s_reqs[7][changed]_i_4__0_n_0\
- );
-\[1].[3].s_reqs[7][changed]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(5),
- I1 => \[1].[3].s_reqs_reg[7][value][11]_1\(5),
- I2 => \^[1].[3].s_reqs_reg[7][value][11]\(4),
- I3 => \[1].[3].s_reqs_reg[7][value][11]_1\(4),
- I4 => \[1].[3].s_reqs_reg[7][value][11]_1\(3),
- I5 => \^[1].[3].s_reqs_reg[7][value][11]\(3),
- O => \[1].[3].s_reqs[7][changed]_i_5_n_0\
- );
-\[1].[3].s_reqs[7][changed]_i_5__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(5),
- I1 => \[1].[3].s_reqs_reg[7][value][11]_2\(5),
- I2 => \^[1].[3].s_reqs_reg[7][value][11]_0\(4),
- I3 => \[1].[3].s_reqs_reg[7][value][11]_2\(4),
- I4 => \[1].[3].s_reqs_reg[7][value][11]_2\(3),
- I5 => \^[1].[3].s_reqs_reg[7][value][11]_0\(3),
- O => \[1].[3].s_reqs[7][changed]_i_5__0_n_0\
- );
-\[1].[3].s_reqs[7][changed]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(2),
- I1 => \[1].[3].s_reqs_reg[7][value][11]_1\(2),
- I2 => \^[1].[3].s_reqs_reg[7][value][11]\(1),
- I3 => \[1].[3].s_reqs_reg[7][value][11]_1\(1),
- I4 => \[1].[3].s_reqs_reg[7][value][11]_1\(0),
- I5 => \^[1].[3].s_reqs_reg[7][value][11]\(0),
- O => \[1].[3].s_reqs[7][changed]_i_6_n_0\
- );
-\[1].[3].s_reqs[7][changed]_i_6__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(2),
- I1 => \[1].[3].s_reqs_reg[7][value][11]_2\(2),
- I2 => \^[1].[3].s_reqs_reg[7][value][11]_0\(1),
- I3 => \[1].[3].s_reqs_reg[7][value][11]_2\(1),
- I4 => \[1].[3].s_reqs_reg[7][value][11]_2\(0),
- I5 => \^[1].[3].s_reqs_reg[7][value][11]_0\(0),
- O => \[1].[3].s_reqs[7][changed]_i_6__0_n_0\
- );
-\[1].[3].s_reqs_reg[7][changed]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[1].[3].s_reqs_reg[7][changed]\(0),
- CO(2) => \[1].[3].s_reqs_reg[7][changed]_i_2_n_1\,
- CO(1) => \[1].[3].s_reqs_reg[7][changed]_i_2_n_2\,
- CO(0) => \[1].[3].s_reqs_reg[7][changed]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[1].[3].s_reqs_reg[7][changed]_i_2_O_UNCONNECTED\(3 downto 0),
- S(3) => \[1].[3].s_reqs[7][changed]_i_3_n_0\,
- S(2) => \[1].[3].s_reqs[7][changed]_i_4_n_0\,
- S(1) => \[1].[3].s_reqs[7][changed]_i_5_n_0\,
- S(0) => \[1].[3].s_reqs[7][changed]_i_6_n_0\
- );
-\[1].[3].s_reqs_reg[7][changed]_i_2__0\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \[1].[3].s_reqs_reg[7][changed]_0\(0),
- CO(2) => \[1].[3].s_reqs_reg[7][changed]_i_2__0_n_1\,
- CO(1) => \[1].[3].s_reqs_reg[7][changed]_i_2__0_n_2\,
- CO(0) => \[1].[3].s_reqs_reg[7][changed]_i_2__0_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_[1].[3].s_reqs_reg[7][changed]_i_2__0_O_UNCONNECTED\(3 downto 0),
- S(3) => \[1].[3].s_reqs[7][changed]_i_3__0_n_0\,
- S(2) => \[1].[3].s_reqs[7][changed]_i_4__0_n_0\,
- S(1) => \[1].[3].s_reqs[7][changed]_i_5__0_n_0\,
- S(0) => \[1].[3].s_reqs[7][changed]_i_6__0_n_0\
- );
-\axi_araddr_reg[10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(8),
- Q => axi_araddr(10),
- R => rst_i
- );
-\axi_araddr_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(0),
- Q => \^axi_rdata_reg[23]_0\(0),
- R => rst_i
- );
-\axi_araddr_reg[2]_rep\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(0),
- Q => \^axi_rdata_reg[22]_1\,
- R => rst_i
- );
-\axi_araddr_reg[2]_rep__0\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(0),
- Q => \^axi_rdata_reg[17]_1\,
- R => rst_i
- );
-\axi_araddr_reg[2]_rep__1\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(0),
- Q => \^axi_rdata_reg[12]_0\,
- R => rst_i
- );
-\axi_araddr_reg[2]_rep__2\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(0),
- Q => \^axi_rdata_reg[7]_1\,
- R => rst_i
- );
-\axi_araddr_reg[2]_rep__3\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(0),
- Q => \^axi_rdata_reg[2]_1\,
- R => rst_i
- );
-\axi_araddr_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(1),
- Q => \^axi_rdata_reg[23]_0\(1),
- R => rst_i
- );
-\axi_araddr_reg[3]_rep\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(1),
- Q => \^axi_rdata_reg[22]_0\,
- R => rst_i
- );
-\axi_araddr_reg[3]_rep__0\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(1),
- Q => \^axi_rdata_reg[17]_0\,
- R => rst_i
- );
-\axi_araddr_reg[3]_rep__1\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(1),
- Q => \^axi_rdata_reg[12]_1\,
- R => rst_i
- );
-\axi_araddr_reg[3]_rep__2\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(1),
- Q => \^axi_rdata_reg[7]_0\,
- R => rst_i
- );
-\axi_araddr_reg[3]_rep__3\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(1),
- Q => \^axi_rdata_reg[2]_0\,
- R => rst_i
- );
-\axi_araddr_reg[4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(2),
- Q => \^axi_rdata_reg[23]_0\(2),
- R => rst_i
- );
-\axi_araddr_reg[4]_rep\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(2),
- Q => \^axi_rdata_reg[18]_0\,
- R => rst_i
- );
-\axi_araddr_reg[4]_rep__0\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(2),
- Q => \^axi_rdata_reg[9]_0\,
- R => rst_i
- );
-\axi_araddr_reg[4]_rep__1\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(2),
- Q => \^axi_rdata_reg[0]_0\,
- R => rst_i
- );
-\axi_araddr_reg[5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(3),
- Q => \^axi_rdata_reg[23]_0\(3),
- R => rst_i
- );
-\axi_araddr_reg[5]_rep\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(3),
- Q => \^axi_rdata_reg[10]_0\,
- R => rst_i
- );
-\axi_araddr_reg[6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(4),
- Q => axi_araddr(6),
- R => rst_i
- );
-\axi_araddr_reg[7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(5),
- Q => axi_araddr(7),
- R => rst_i
- );
-\axi_araddr_reg[8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(6),
- Q => axi_araddr(8),
- R => rst_i
- );
-\axi_araddr_reg[9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_arready_i_1_n_0,
- D => s00_axi_araddr(7),
- Q => axi_araddr(9),
- R => rst_i
- );
-axi_arready_i_1: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => s00_axi_arvalid,
- I1 => \^s00_axi_arready\,
- O => axi_arready_i_1_n_0
- );
-axi_arready_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => axi_arready_i_1_n_0,
- Q => \^s00_axi_arready\,
- R => rst_i
- );
-\axi_awaddr_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_awready_i_2_n_0,
- D => s00_axi_awaddr(0),
- Q => sel0(0),
- R => rst_i
- );
-\axi_awaddr_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_awready_i_2_n_0,
- D => s00_axi_awaddr(1),
- Q => sel0(1),
- R => rst_i
- );
-\axi_awaddr_reg[4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_awready_i_2_n_0,
- D => s00_axi_awaddr(2),
- Q => sel0(2),
- R => rst_i
- );
-\axi_awaddr_reg[5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_awready_i_2_n_0,
- D => s00_axi_awaddr(3),
- Q => sel0(3),
- R => rst_i
- );
-\axi_awaddr_reg[6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_awready_i_2_n_0,
- D => s00_axi_awaddr(4),
- Q => sel0(4),
- R => rst_i
- );
-\axi_awaddr_reg[7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_awready_i_2_n_0,
- D => s00_axi_awaddr(5),
- Q => sel0(5),
- R => rst_i
- );
-\axi_awaddr_reg[8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_awready_i_2_n_0,
- D => s00_axi_awaddr(6),
- Q => sel0(6),
- R => rst_i
- );
-\axi_awaddr_reg[9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => axi_awready_i_2_n_0,
- D => s00_axi_awaddr(7),
- Q => sel0(7),
- R => rst_i
- );
-axi_awready_i_2: unisim.vcomponents.LUT3
- generic map(
- INIT => X"08"
- )
- port map (
- I0 => s00_axi_awvalid,
- I1 => s00_axi_wvalid,
- I2 => \^s00_axi_awready\,
- O => axi_awready_i_2_n_0
- );
-axi_awready_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => axi_awready_i_2_n_0,
- Q => \^s00_axi_awready\,
- R => rst_i
- );
-\axi_bresp[1]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"002AFF2A00000000"
- )
- port map (
- I0 => \^s00_axi_bresp\(0),
- I1 => \^s00_axi_bvalid\,
- I2 => s00_axi_bready,
- I3 => axi_bvalid04_out,
- I4 => \axi_bresp[1]_i_3_n_0\,
- I5 => s00_axi_aresetn,
- O => \axi_bresp[1]_i_1_n_0\
- );
-\axi_bresp[1]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"20000000"
- )
- port map (
- I0 => \^s00_axi_awready\,
- I1 => \^s00_axi_bvalid\,
- I2 => \^s00_axi_wready\,
- I3 => s00_axi_wvalid,
- I4 => s00_axi_awvalid,
- O => axi_bvalid04_out
- );
-\axi_bresp[1]_i_3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"01FF"
- )
- port map (
- I0 => sel0(5),
- I1 => sel0(4),
- I2 => sel0(6),
- I3 => sel0(7),
- O => \axi_bresp[1]_i_3_n_0\
- );
-\axi_bresp_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \axi_bresp[1]_i_1_n_0\,
- Q => \^s00_axi_bresp\(0),
- R => '0'
- );
-axi_bvalid_i_1: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000FFFF80008000"
- )
- port map (
- I0 => s00_axi_awvalid,
- I1 => s00_axi_wvalid,
- I2 => \^s00_axi_wready\,
- I3 => \^s00_axi_awready\,
- I4 => s00_axi_bready,
- I5 => \^s00_axi_bvalid\,
- O => axi_bvalid_i_1_n_0
- );
-axi_bvalid_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => axi_bvalid_i_1_n_0,
- Q => \^s00_axi_bvalid\,
- R => rst_i
- );
-\axi_rdata[0]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[0]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[0]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_rep_10\,
- O => \axi_rdata[0]_i_1_n_0\
- );
-\axi_rdata[0]_i_14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"EE55FA00EE00FA00"
- )
- port map (
- I0 => \^axi_rdata_reg[0]_0\,
- I1 => \data_rw_o[3]\(0),
- I2 => gem_status_vector_i(0),
- I3 => \^axi_rdata_reg[2]_0\,
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \s_ins_reg[3]\(0),
- O => \axi_rdata[0]_i_14_n_0\
- );
-\axi_rdata[0]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[0]_i_35_n_0\,
- I1 => \^axi_rdata_reg[0]_0\,
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(0),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^axi_rdata_reg[10]_0\,
- O => \axi_rdata[0]_i_17_n_0\
- );
-\axi_rdata[0]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[2]_0\,
- I1 => \dac_ch_o_reg[0][31]\(0),
- I2 => \^axi_rdata_reg[2]_1\,
- I3 => \^axi_rdata_reg[0]_0\,
- O => \axi_rdata[0]_i_23_n_0\
- );
-\axi_rdata[0]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]\(0),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]\(0),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]\(0),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]\(0),
- O => \axi_rdata[0]_i_29_n_0\
- );
-\axi_rdata[0]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]\(0),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]\(0),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]\(0),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]\(0),
- O => \axi_rdata[0]_i_30_n_0\
- );
-\axi_rdata[0]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^q\(0),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]\(0),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]\(0),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(0),
- O => \axi_rdata[0]_i_31_n_0\
- );
-\axi_rdata[0]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(0),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]\(0),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]\(0),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(0),
- O => \axi_rdata[0]_i_32_n_0\
- );
-\axi_rdata[0]_i_33\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][0]\,
- I1 => \data_rw_o_reg_n_0_[10][0]\,
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \data_o_reg[1][3]\(0),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \s_datao_fmc1[0]\(0),
- O => \axi_rdata[0]_i_33_n_0\
- );
-\axi_rdata[0]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]\(0),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]\(0),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]\(0),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]\(0),
- O => \axi_rdata[0]_i_35_n_0\
- );
-\axi_rdata[0]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(0),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(0),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(0),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(0),
- O => \axi_rdata[0]_i_36_n_0\
- );
-\axi_rdata[0]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(0),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(0),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(0),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(0),
- O => \axi_rdata[0]_i_37_n_0\
- );
-\axi_rdata[0]_i_39\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(0),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(0),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(0),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(0),
- O => \axi_rdata[0]_i_39_n_0\
- );
-\axi_rdata[0]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][0]\,
- I1 => \data_rw_o_reg_n_0_[78][0]\,
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \data_o_reg[1][3]_0\(0),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \s_datao_fmc2[0]\(0),
- O => \axi_rdata[0]_i_41_n_0\
- );
-\axi_rdata[0]_i_44\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(0),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(0),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(0),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(0),
- O => \axi_rdata[0]_i_44_n_0\
- );
-\axi_rdata[0]_i_45\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(0),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(0),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(0),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(0),
- O => \axi_rdata[0]_i_45_n_0\
- );
-\axi_rdata[0]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[0]_i_11_n_0\,
- I1 => \axi_rdata_reg[0]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[0]_i_13_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata[0]_i_14_n_0\,
- O => \axi_rdata[0]_i_5_n_0\
- );
-\axi_rdata[0]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[10]_0\,
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][0]\,
- I2 => \^axi_rdata_reg[0]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][0]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[0]_i_17_n_0\,
- O => \axi_rdata[0]_i_6_n_0\
- );
-\axi_rdata[0]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[0]_i_18_n_0\,
- I1 => \axi_rdata_reg[0]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[0]_i_20_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_araddr_reg[4]_rep__1_0\,
- O => \axi_rdata[0]_i_7_n_0\
- );
-\axi_rdata[0]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][0]_0\,
- I1 => \^axi_rdata_reg[0]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[0]_i_23_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata_reg[0]_i_24_n_0\,
- O => \axi_rdata[0]_i_8_n_0\
- );
-\axi_rdata[10]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[10]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[10]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_rep_0\,
- O => \axi_rdata[10]_i_1_n_0\
- );
-\axi_rdata[10]_i_13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"04FF0400"
- )
- port map (
- I0 => \^axi_rdata_reg[12]_0\,
- I1 => \s_datao_fmc1[4]\(2),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^axi_rdata_reg[18]_0\,
- I4 => \axi_rdata[10]_i_33_n_0\,
- O => \axi_rdata[10]_i_13_n_0\
- );
-\axi_rdata[10]_i_14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"CC408840"
- )
- port map (
- I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[12]_1\,
- I2 => gem_status_vector_i(10),
- I3 => \^axi_rdata_reg[12]_0\,
- I4 => \data_rw_o_reg_n_0_[3][10]\,
- O => \axi_rdata[10]_i_14_n_0\
- );
-\axi_rdata[10]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[10]_i_34_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \dac_ch_o_reg[0][31]_0\(10),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^axi_rdata_reg[10]_0\,
- O => \axi_rdata[10]_i_17_n_0\
- );
-\axi_rdata[10]_i_19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88888B88"
- )
- port map (
- I0 => \axi_rdata[10]_i_37_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[12]_0\,
- I3 => \s_datao_fmc2[4]\(2),
- I4 => \^axi_rdata_reg[12]_1\,
- O => \axi_rdata[10]_i_19_n_0\
- );
-\axi_rdata[10]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[12]_1\,
- I1 => \dac_ch_o_reg[0][31]\(10),
- I2 => \^axi_rdata_reg[12]_0\,
- I3 => \^axi_rdata_reg[18]_0\,
- O => \axi_rdata[10]_i_23_n_0\
- );
-\axi_rdata[10]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]\(10),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]\(10),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]\(10),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]\(10),
- O => \axi_rdata[10]_i_29_n_0\
- );
-\axi_rdata[10]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]\(10),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]\(10),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]\(10),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]\(10),
- O => \axi_rdata[10]_i_30_n_0\
- );
-\axi_rdata[10]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^q\(10),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]\(10),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]\(10),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(10),
- O => \axi_rdata[10]_i_31_n_0\
- );
-\axi_rdata[10]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(10),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]\(10),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]\(10),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(10),
- O => \axi_rdata[10]_i_32_n_0\
- );
-\axi_rdata[10]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][10]\,
- I1 => \data_rw_o_reg_n_0_[10][10]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \s_datao_fmc1[0]\(10),
- I4 => \^axi_rdata_reg[12]_0\,
- O => \axi_rdata[10]_i_33_n_0\
- );
-\axi_rdata[10]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]\(10),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]\(10),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]\(10),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]\(10),
- O => \axi_rdata[10]_i_34_n_0\
- );
-\axi_rdata[10]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(10),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(10),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(10),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(10),
- O => \axi_rdata[10]_i_35_n_0\
- );
-\axi_rdata[10]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(10),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(10),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(10),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(10),
- O => \axi_rdata[10]_i_36_n_0\
- );
-\axi_rdata[10]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(10),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(10),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(10),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(10),
- O => \axi_rdata[10]_i_37_n_0\
- );
-\axi_rdata[10]_i_39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][10]\,
- I1 => \data_rw_o_reg_n_0_[78][10]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \s_datao_fmc2[0]\(10),
- I4 => \^axi_rdata_reg[12]_0\,
- O => \axi_rdata[10]_i_39_n_0\
- );
-\axi_rdata[10]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(10),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(10),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(10),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(10),
- O => \axi_rdata[10]_i_42_n_0\
- );
-\axi_rdata[10]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(10),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(10),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(10),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(10),
- O => \axi_rdata[10]_i_43_n_0\
- );
-\axi_rdata[10]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[10]_i_11_n_0\,
- I1 => \axi_rdata_reg[10]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[10]_i_13_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata[10]_i_14_n_0\,
- O => \axi_rdata[10]_i_5_n_0\
- );
-\axi_rdata[10]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[10]_0\,
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][10]\,
- I2 => \^axi_rdata_reg[18]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][10]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[10]_i_17_n_0\,
- O => \axi_rdata[10]_i_6_n_0\
- );
-\axi_rdata[10]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[10]_i_18_n_0\,
- I1 => \axi_rdata[10]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[10]_i_20_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_araddr_reg[4]_rep_0\,
- O => \axi_rdata[10]_i_7_n_0\
- );
-\axi_rdata[10]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][10]_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[10]_i_23_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata_reg[10]_i_24_n_0\,
- O => \axi_rdata[10]_i_8_n_0\
- );
-\axi_rdata[11]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[11]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[11]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_8\,
- O => \axi_rdata[11]_i_1_n_0\
- );
-\axi_rdata[11]_i_13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"04FF0400"
- )
- port map (
- I0 => \^axi_rdata_reg[12]_0\,
- I1 => \s_datao_fmc1[4]\(3),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^axi_rdata_reg[18]_0\,
- I4 => \axi_rdata[11]_i_33_n_0\,
- O => \axi_rdata[11]_i_13_n_0\
- );
-\axi_rdata[11]_i_14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"CC408840"
- )
- port map (
- I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[12]_1\,
- I2 => gem_status_vector_i(11),
- I3 => \^axi_rdata_reg[12]_0\,
- I4 => \data_rw_o_reg_n_0_[3][11]\,
- O => \axi_rdata[11]_i_14_n_0\
- );
-\axi_rdata[11]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[11]_i_34_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \dac_ch_o_reg[0][31]_0\(11),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[11]_i_17_n_0\
- );
-\axi_rdata[11]_i_19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88888B88"
- )
- port map (
- I0 => \axi_rdata[11]_i_37_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[12]_0\,
- I3 => \s_datao_fmc2[4]\(3),
- I4 => \^axi_rdata_reg[12]_1\,
- O => \axi_rdata[11]_i_19_n_0\
- );
-\axi_rdata[11]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[12]_1\,
- I1 => \dac_ch_o_reg[0][31]\(11),
- I2 => \^axi_rdata_reg[12]_0\,
- I3 => \^axi_rdata_reg[18]_0\,
- O => \axi_rdata[11]_i_23_n_0\
- );
-\axi_rdata[11]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]\(11),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]\(11),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]\(11),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]\(11),
- O => \axi_rdata[11]_i_29_n_0\
- );
-\axi_rdata[11]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]\(11),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]\(11),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]\(11),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]\(11),
- O => \axi_rdata[11]_i_30_n_0\
- );
-\axi_rdata[11]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^q\(11),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]\(11),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]\(11),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(11),
- O => \axi_rdata[11]_i_31_n_0\
- );
-\axi_rdata[11]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(11),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]\(11),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]\(11),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(11),
- O => \axi_rdata[11]_i_32_n_0\
- );
-\axi_rdata[11]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][11]\,
- I1 => \data_rw_o_reg_n_0_[10][11]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \s_datao_fmc1[0]\(11),
- I4 => \^axi_rdata_reg[12]_0\,
- O => \axi_rdata[11]_i_33_n_0\
- );
-\axi_rdata[11]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]\(11),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]\(11),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]\(11),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]\(11),
- O => \axi_rdata[11]_i_34_n_0\
- );
-\axi_rdata[11]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(11),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(11),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(11),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(11),
- O => \axi_rdata[11]_i_35_n_0\
- );
-\axi_rdata[11]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(11),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(11),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(11),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(11),
- O => \axi_rdata[11]_i_36_n_0\
- );
-\axi_rdata[11]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(11),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(11),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(11),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(11),
- O => \axi_rdata[11]_i_37_n_0\
- );
-\axi_rdata[11]_i_39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][11]\,
- I1 => \data_rw_o_reg_n_0_[78][11]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \s_datao_fmc2[0]\(11),
- I4 => \^axi_rdata_reg[12]_0\,
- O => \axi_rdata[11]_i_39_n_0\
- );
-\axi_rdata[11]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(11),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(11),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(11),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(11),
- O => \axi_rdata[11]_i_42_n_0\
- );
-\axi_rdata[11]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(11),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(11),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(11),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(11),
- O => \axi_rdata[11]_i_43_n_0\
- );
-\axi_rdata[11]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[11]_i_11_n_0\,
- I1 => \axi_rdata_reg[11]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[11]_i_13_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata[11]_i_14_n_0\,
- O => \axi_rdata[11]_i_5_n_0\
- );
-\axi_rdata[11]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][11]\,
- I2 => \^axi_rdata_reg[18]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][11]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[11]_i_17_n_0\,
- O => \axi_rdata[11]_i_6_n_0\
- );
-\axi_rdata[11]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[11]_i_18_n_0\,
- I1 => \axi_rdata[11]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[11]_i_20_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_araddr_reg[4]_rep_1\,
- O => \axi_rdata[11]_i_7_n_0\
- );
-\axi_rdata[11]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][11]_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[11]_i_23_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[11]_i_24_n_0\,
- O => \axi_rdata[11]_i_8_n_0\
- );
-\axi_rdata[12]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[12]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[12]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_7\,
- O => \axi_rdata[12]_i_1_n_0\
- );
-\axi_rdata[12]_i_13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"04FF0400"
- )
- port map (
- I0 => \^axi_rdata_reg[12]_0\,
- I1 => \s_datao_fmc1[4]\(4),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^axi_rdata_reg[18]_0\,
- I4 => \axi_rdata[12]_i_33_n_0\,
- O => \axi_rdata[12]_i_13_n_0\
- );
-\axi_rdata[12]_i_14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"CCC888C8"
- )
- port map (
- I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[12]_1\,
- I2 => gem_status_vector_i(12),
- I3 => \^axi_rdata_reg[12]_0\,
- I4 => \data_rw_o_reg_n_0_[3][12]\,
- O => \axi_rdata[12]_i_14_n_0\
- );
-\axi_rdata[12]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[12]_i_34_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \dac_ch_o_reg[0][31]_0\(12),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[12]_i_17_n_0\
- );
-\axi_rdata[12]_i_19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88888B88"
- )
- port map (
- I0 => \axi_rdata[12]_i_37_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[12]_0\,
- I3 => \s_datao_fmc2[4]\(4),
- I4 => \^axi_rdata_reg[12]_1\,
- O => \axi_rdata[12]_i_19_n_0\
- );
-\axi_rdata[12]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[12]_1\,
- I1 => \dac_ch_o_reg[0][31]\(12),
- I2 => \^axi_rdata_reg[12]_0\,
- I3 => \^axi_rdata_reg[18]_0\,
- O => \axi_rdata[12]_i_23_n_0\
- );
-\axi_rdata[12]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][12]\,
- I1 => \data_rw_o_reg_n_0_[26][12]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \data_rw_o_reg_n_0_[25][12]\,
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \data_rw_o_reg_n_0_[24][12]\,
- O => \axi_rdata[12]_i_29_n_0\
- );
-\axi_rdata[12]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][12]\,
- I1 => \data_rw_o_reg_n_0_[30][12]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \data_rw_o_reg_n_0_[29][12]\,
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \data_rw_o_reg_n_0_[28][12]\,
- O => \axi_rdata[12]_i_30_n_0\
- );
-\axi_rdata[12]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][12]\,
- I1 => \data_rw_o_reg_n_0_[18][12]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \data_rw_o_reg_n_0_[17][12]\,
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \data_rw_o_reg_n_0_[16][12]\,
- O => \axi_rdata[12]_i_31_n_0\
- );
-\axi_rdata[12]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][12]\,
- I1 => \data_rw_o_reg_n_0_[22][12]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \data_rw_o_reg_n_0_[21][12]\,
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \data_rw_o_reg_n_0_[20][12]\,
- O => \axi_rdata[12]_i_32_n_0\
- );
-\axi_rdata[12]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][12]\,
- I1 => \data_rw_o_reg_n_0_[10][12]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \s_datao_fmc1[0]\(12),
- I4 => \^axi_rdata_reg[12]_0\,
- O => \axi_rdata[12]_i_33_n_0\
- );
-\axi_rdata[12]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][12]\,
- I1 => \data_rw_o_reg_n_0_[34][12]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \data_rw_o_reg_n_0_[33][12]\,
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \data_rw_o_reg_n_0_[32][12]\,
- O => \axi_rdata[12]_i_34_n_0\
- );
-\axi_rdata[12]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][12]\,
- I1 => \data_rw_o_reg_n_0_[90][12]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \data_rw_o_reg_n_0_[89][12]\,
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \data_rw_o_reg_n_0_[88][12]\,
- O => \axi_rdata[12]_i_35_n_0\
- );
-\axi_rdata[12]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][12]\,
- I1 => \data_rw_o_reg_n_0_[94][12]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \data_rw_o_reg_n_0_[93][12]\,
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \data_rw_o_reg_n_0_[92][12]\,
- O => \axi_rdata[12]_i_36_n_0\
- );
-\axi_rdata[12]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][12]\,
- I1 => \data_rw_o_reg_n_0_[86][12]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \data_rw_o_reg_n_0_[85][12]\,
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \data_rw_o_reg_n_0_[84][12]\,
- O => \axi_rdata[12]_i_37_n_0\
- );
-\axi_rdata[12]_i_39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][12]\,
- I1 => \data_rw_o_reg_n_0_[78][12]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \s_datao_fmc2[0]\(12),
- I4 => \^axi_rdata_reg[12]_0\,
- O => \axi_rdata[12]_i_39_n_0\
- );
-\axi_rdata[12]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][12]\,
- I1 => \data_rw_o_reg_n_0_[98][12]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \data_rw_o_reg_n_0_[97][12]\,
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \data_rw_o_reg_n_0_[96][12]\,
- O => \axi_rdata[12]_i_42_n_0\
- );
-\axi_rdata[12]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][12]\,
- I1 => \data_rw_o_reg_n_0_[102][12]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \data_rw_o_reg_n_0_[101][12]\,
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \data_rw_o_reg_n_0_[100][12]\,
- O => \axi_rdata[12]_i_43_n_0\
- );
-\axi_rdata[12]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[12]_i_11_n_0\,
- I1 => \axi_rdata_reg[12]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[12]_i_13_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata[12]_i_14_n_0\,
- O => \axi_rdata[12]_i_5_n_0\
- );
-\axi_rdata[12]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][12]\,
- I2 => \^axi_rdata_reg[18]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][12]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[12]_i_17_n_0\,
- O => \axi_rdata[12]_i_6_n_0\
- );
-\axi_rdata[12]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[12]_i_18_n_0\,
- I1 => \axi_rdata[12]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[12]_i_20_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_araddr_reg[4]_rep_2\,
- O => \axi_rdata[12]_i_7_n_0\
- );
-\axi_rdata[12]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][12]_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[12]_i_23_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[12]_i_24_n_0\,
- O => \axi_rdata[12]_i_8_n_0\
- );
-\axi_rdata[13]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[13]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[13]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_6\,
- O => \axi_rdata[13]_i_1_n_0\
- );
-\axi_rdata[13]_i_13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"04FF0400"
- )
- port map (
- I0 => \^axi_rdata_reg[17]_1\,
- I1 => \s_datao_fmc1[4]\(5),
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \^axi_rdata_reg[18]_0\,
- I4 => \axi_rdata[13]_i_33_n_0\,
- O => \axi_rdata[13]_i_13_n_0\
- );
-\axi_rdata[13]_i_14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"44C800C8"
- )
- port map (
- I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[17]_0\,
- I2 => gem_status_vector_i(13),
- I3 => \^axi_rdata_reg[17]_1\,
- I4 => \data_rw_o_reg_n_0_[3][13]\,
- O => \axi_rdata[13]_i_14_n_0\
- );
-\axi_rdata[13]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[13]_i_34_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(13),
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[13]_i_17_n_0\
- );
-\axi_rdata[13]_i_19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88888B88"
- )
- port map (
- I0 => \axi_rdata[13]_i_37_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_1\,
- I3 => \s_datao_fmc2[4]\(5),
- I4 => \^axi_rdata_reg[17]_0\,
- O => \axi_rdata[13]_i_19_n_0\
- );
-\axi_rdata[13]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[17]_0\,
- I1 => \dac_ch_o_reg[0][31]\(13),
- I2 => \^axi_rdata_reg[17]_1\,
- I3 => \^axi_rdata_reg[18]_0\,
- O => \axi_rdata[13]_i_23_n_0\
- );
-\axi_rdata[13]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][13]\,
- I1 => \data_rw_o_reg_n_0_[26][13]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[25][13]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[24][13]\,
- O => \axi_rdata[13]_i_29_n_0\
- );
-\axi_rdata[13]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][13]\,
- I1 => \data_rw_o_reg_n_0_[30][13]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[29][13]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[28][13]\,
- O => \axi_rdata[13]_i_30_n_0\
- );
-\axi_rdata[13]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][13]\,
- I1 => \data_rw_o_reg_n_0_[18][13]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[17][13]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[16][13]\,
- O => \axi_rdata[13]_i_31_n_0\
- );
-\axi_rdata[13]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][13]\,
- I1 => \data_rw_o_reg_n_0_[22][13]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[21][13]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[20][13]\,
- O => \axi_rdata[13]_i_32_n_0\
- );
-\axi_rdata[13]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][13]\,
- I1 => \data_rw_o_reg_n_0_[10][13]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \s_datao_fmc1[0]\(13),
- I4 => \^axi_rdata_reg[17]_1\,
- O => \axi_rdata[13]_i_33_n_0\
- );
-\axi_rdata[13]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][13]\,
- I1 => \data_rw_o_reg_n_0_[34][13]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[33][13]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[32][13]\,
- O => \axi_rdata[13]_i_34_n_0\
- );
-\axi_rdata[13]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][13]\,
- I1 => \data_rw_o_reg_n_0_[90][13]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[89][13]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[88][13]\,
- O => \axi_rdata[13]_i_35_n_0\
- );
-\axi_rdata[13]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][13]\,
- I1 => \data_rw_o_reg_n_0_[94][13]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[93][13]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[92][13]\,
- O => \axi_rdata[13]_i_36_n_0\
- );
-\axi_rdata[13]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][13]\,
- I1 => \data_rw_o_reg_n_0_[86][13]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[85][13]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[84][13]\,
- O => \axi_rdata[13]_i_37_n_0\
- );
-\axi_rdata[13]_i_39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][13]\,
- I1 => \data_rw_o_reg_n_0_[78][13]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \s_datao_fmc2[0]\(13),
- I4 => \^axi_rdata_reg[17]_1\,
- O => \axi_rdata[13]_i_39_n_0\
- );
-\axi_rdata[13]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][13]\,
- I1 => \data_rw_o_reg_n_0_[98][13]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[97][13]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[96][13]\,
- O => \axi_rdata[13]_i_42_n_0\
- );
-\axi_rdata[13]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][13]\,
- I1 => \data_rw_o_reg_n_0_[102][13]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[101][13]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[100][13]\,
- O => \axi_rdata[13]_i_43_n_0\
- );
-\axi_rdata[13]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[13]_i_11_n_0\,
- I1 => \axi_rdata_reg[13]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[13]_i_13_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata[13]_i_14_n_0\,
- O => \axi_rdata[13]_i_5_n_0\
- );
-\axi_rdata[13]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][13]\,
- I2 => \^axi_rdata_reg[18]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][13]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[13]_i_17_n_0\,
- O => \axi_rdata[13]_i_6_n_0\
- );
-\axi_rdata[13]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[13]_i_18_n_0\,
- I1 => \axi_rdata[13]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[13]_i_20_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_araddr_reg[4]_rep_3\,
- O => \axi_rdata[13]_i_7_n_0\
- );
-\axi_rdata[13]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][13]_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[13]_i_23_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[13]_i_24_n_0\,
- O => \axi_rdata[13]_i_8_n_0\
- );
-\axi_rdata[14]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[14]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[14]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_5\,
- O => \axi_rdata[14]_i_1_n_0\
- );
-\axi_rdata[14]_i_13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"04FF0400"
- )
- port map (
- I0 => \^axi_rdata_reg[17]_1\,
- I1 => \s_datao_fmc1[4]\(6),
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \^axi_rdata_reg[18]_0\,
- I4 => \axi_rdata[14]_i_33_n_0\,
- O => \axi_rdata[14]_i_13_n_0\
- );
-\axi_rdata[14]_i_14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"CCC888C8"
- )
- port map (
- I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[17]_0\,
- I2 => gem_status_vector_i(14),
- I3 => \^axi_rdata_reg[17]_1\,
- I4 => \data_rw_o_reg_n_0_[3][14]\,
- O => \axi_rdata[14]_i_14_n_0\
- );
-\axi_rdata[14]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[14]_i_34_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(14),
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[14]_i_17_n_0\
- );
-\axi_rdata[14]_i_19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88888B88"
- )
- port map (
- I0 => \axi_rdata[14]_i_37_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_1\,
- I3 => \s_datao_fmc2[4]\(6),
- I4 => \^axi_rdata_reg[17]_0\,
- O => \axi_rdata[14]_i_19_n_0\
- );
-\axi_rdata[14]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[17]_0\,
- I1 => \dac_ch_o_reg[0][31]\(14),
- I2 => \^axi_rdata_reg[17]_1\,
- I3 => \^axi_rdata_reg[18]_0\,
- O => \axi_rdata[14]_i_23_n_0\
- );
-\axi_rdata[14]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][14]\,
- I1 => \data_rw_o_reg_n_0_[26][14]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[25][14]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[24][14]\,
- O => \axi_rdata[14]_i_29_n_0\
- );
-\axi_rdata[14]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][14]\,
- I1 => \data_rw_o_reg_n_0_[30][14]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[29][14]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[28][14]\,
- O => \axi_rdata[14]_i_30_n_0\
- );
-\axi_rdata[14]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][14]\,
- I1 => \data_rw_o_reg_n_0_[18][14]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[17][14]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[16][14]\,
- O => \axi_rdata[14]_i_31_n_0\
- );
-\axi_rdata[14]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][14]\,
- I1 => \data_rw_o_reg_n_0_[22][14]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[21][14]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[20][14]\,
- O => \axi_rdata[14]_i_32_n_0\
- );
-\axi_rdata[14]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][14]\,
- I1 => \data_rw_o_reg_n_0_[10][14]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \s_datao_fmc1[0]\(14),
- I4 => \^axi_rdata_reg[17]_1\,
- O => \axi_rdata[14]_i_33_n_0\
- );
-\axi_rdata[14]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][14]\,
- I1 => \data_rw_o_reg_n_0_[34][14]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[33][14]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[32][14]\,
- O => \axi_rdata[14]_i_34_n_0\
- );
-\axi_rdata[14]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][14]\,
- I1 => \data_rw_o_reg_n_0_[90][14]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[89][14]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[88][14]\,
- O => \axi_rdata[14]_i_35_n_0\
- );
-\axi_rdata[14]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][14]\,
- I1 => \data_rw_o_reg_n_0_[94][14]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[93][14]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[92][14]\,
- O => \axi_rdata[14]_i_36_n_0\
- );
-\axi_rdata[14]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][14]\,
- I1 => \data_rw_o_reg_n_0_[86][14]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[85][14]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[84][14]\,
- O => \axi_rdata[14]_i_37_n_0\
- );
-\axi_rdata[14]_i_39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][14]\,
- I1 => \data_rw_o_reg_n_0_[78][14]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \s_datao_fmc2[0]\(14),
- I4 => \^axi_rdata_reg[17]_1\,
- O => \axi_rdata[14]_i_39_n_0\
- );
-\axi_rdata[14]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][14]\,
- I1 => \data_rw_o_reg_n_0_[98][14]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[97][14]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[96][14]\,
- O => \axi_rdata[14]_i_42_n_0\
- );
-\axi_rdata[14]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][14]\,
- I1 => \data_rw_o_reg_n_0_[102][14]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[101][14]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[100][14]\,
- O => \axi_rdata[14]_i_43_n_0\
- );
-\axi_rdata[14]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[14]_i_11_n_0\,
- I1 => \axi_rdata_reg[14]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[14]_i_13_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata[14]_i_14_n_0\,
- O => \axi_rdata[14]_i_5_n_0\
- );
-\axi_rdata[14]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][14]\,
- I2 => \^axi_rdata_reg[18]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][14]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[14]_i_17_n_0\,
- O => \axi_rdata[14]_i_6_n_0\
- );
-\axi_rdata[14]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[14]_i_18_n_0\,
- I1 => \axi_rdata[14]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[14]_i_20_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_araddr_reg[4]_rep_4\,
- O => \axi_rdata[14]_i_7_n_0\
- );
-\axi_rdata[14]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][14]_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[14]_i_23_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[14]_i_24_n_0\,
- O => \axi_rdata[14]_i_8_n_0\
- );
-\axi_rdata[15]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[15]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[15]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_4\,
- O => \axi_rdata[15]_i_1_n_0\
- );
-\axi_rdata[15]_i_13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"04FF0400"
- )
- port map (
- I0 => \^axi_rdata_reg[17]_1\,
- I1 => \s_datao_fmc1[4]\(7),
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \^axi_rdata_reg[18]_0\,
- I4 => \axi_rdata[15]_i_33_n_0\,
- O => \axi_rdata[15]_i_13_n_0\
- );
-\axi_rdata[15]_i_14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"CCC888C8"
- )
- port map (
- I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[17]_0\,
- I2 => gem_status_vector_i(15),
- I3 => \^axi_rdata_reg[17]_1\,
- I4 => \data_rw_o_reg_n_0_[3][15]\,
- O => \axi_rdata[15]_i_14_n_0\
- );
-\axi_rdata[15]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[15]_i_34_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(15),
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[15]_i_17_n_0\
- );
-\axi_rdata[15]_i_19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88888B88"
- )
- port map (
- I0 => \axi_rdata[15]_i_37_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_1\,
- I3 => \s_datao_fmc2[4]\(7),
- I4 => \^axi_rdata_reg[17]_0\,
- O => \axi_rdata[15]_i_19_n_0\
- );
-\axi_rdata[15]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[17]_0\,
- I1 => \dac_ch_o_reg[0][31]\(15),
- I2 => \^axi_rdata_reg[17]_1\,
- I3 => \^axi_rdata_reg[18]_0\,
- O => \axi_rdata[15]_i_23_n_0\
- );
-\axi_rdata[15]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][15]\,
- I1 => \data_rw_o_reg_n_0_[26][15]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[25][15]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[24][15]\,
- O => \axi_rdata[15]_i_29_n_0\
- );
-\axi_rdata[15]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][15]\,
- I1 => \data_rw_o_reg_n_0_[30][15]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[29][15]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[28][15]\,
- O => \axi_rdata[15]_i_30_n_0\
- );
-\axi_rdata[15]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][15]\,
- I1 => \data_rw_o_reg_n_0_[18][15]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[17][15]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[16][15]\,
- O => \axi_rdata[15]_i_31_n_0\
- );
-\axi_rdata[15]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][15]\,
- I1 => \data_rw_o_reg_n_0_[22][15]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[21][15]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[20][15]\,
- O => \axi_rdata[15]_i_32_n_0\
- );
-\axi_rdata[15]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][15]\,
- I1 => \data_rw_o_reg_n_0_[10][15]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \s_datao_fmc1[0]\(15),
- I4 => \^axi_rdata_reg[17]_1\,
- O => \axi_rdata[15]_i_33_n_0\
- );
-\axi_rdata[15]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][15]\,
- I1 => \data_rw_o_reg_n_0_[34][15]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[33][15]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[32][15]\,
- O => \axi_rdata[15]_i_34_n_0\
- );
-\axi_rdata[15]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][15]\,
- I1 => \data_rw_o_reg_n_0_[90][15]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[89][15]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[88][15]\,
- O => \axi_rdata[15]_i_35_n_0\
- );
-\axi_rdata[15]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][15]\,
- I1 => \data_rw_o_reg_n_0_[94][15]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[93][15]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[92][15]\,
- O => \axi_rdata[15]_i_36_n_0\
- );
-\axi_rdata[15]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][15]\,
- I1 => \data_rw_o_reg_n_0_[86][15]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[85][15]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[84][15]\,
- O => \axi_rdata[15]_i_37_n_0\
- );
-\axi_rdata[15]_i_39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][15]\,
- I1 => \data_rw_o_reg_n_0_[78][15]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \s_datao_fmc2[0]\(15),
- I4 => \^axi_rdata_reg[17]_1\,
- O => \axi_rdata[15]_i_39_n_0\
- );
-\axi_rdata[15]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][15]\,
- I1 => \data_rw_o_reg_n_0_[98][15]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[97][15]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[96][15]\,
- O => \axi_rdata[15]_i_42_n_0\
- );
-\axi_rdata[15]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][15]\,
- I1 => \data_rw_o_reg_n_0_[102][15]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[101][15]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[100][15]\,
- O => \axi_rdata[15]_i_43_n_0\
- );
-\axi_rdata[15]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[15]_i_11_n_0\,
- I1 => \axi_rdata_reg[15]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[15]_i_13_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata[15]_i_14_n_0\,
- O => \axi_rdata[15]_i_5_n_0\
- );
-\axi_rdata[15]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][15]\,
- I2 => \^axi_rdata_reg[18]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][15]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[15]_i_17_n_0\,
- O => \axi_rdata[15]_i_6_n_0\
- );
-\axi_rdata[15]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[15]_i_18_n_0\,
- I1 => \axi_rdata[15]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[15]_i_20_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_araddr_reg[4]_rep_5\,
- O => \axi_rdata[15]_i_7_n_0\
- );
-\axi_rdata[15]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][15]_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[15]_i_23_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[15]_i_24_n_0\,
- O => \axi_rdata[15]_i_8_n_0\
- );
-\axi_rdata[16]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[16]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[16]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_3\,
- O => \axi_rdata[16]_i_1_n_0\
- );
-\axi_rdata[16]_i_13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"04FF0400"
- )
- port map (
- I0 => \^axi_rdata_reg[17]_1\,
- I1 => \s_datao_fmc1[4]\(8),
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \^axi_rdata_reg[18]_0\,
- I4 => \axi_rdata[16]_i_33_n_0\,
- O => \axi_rdata[16]_i_13_n_0\
- );
-\axi_rdata[16]_i_14\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"C888"
- )
- port map (
- I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[17]_0\,
- I2 => \data_rw_o_reg_n_0_[3][16]\,
- I3 => \^axi_rdata_reg[17]_1\,
- O => \axi_rdata[16]_i_14_n_0\
- );
-\axi_rdata[16]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[16]_i_34_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(16),
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[16]_i_17_n_0\
- );
-\axi_rdata[16]_i_19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88888B88"
- )
- port map (
- I0 => \axi_rdata[16]_i_37_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_1\,
- I3 => \s_datao_fmc2[4]\(8),
- I4 => \^axi_rdata_reg[17]_0\,
- O => \axi_rdata[16]_i_19_n_0\
- );
-\axi_rdata[16]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[17]_0\,
- I1 => \dac_ch_o_reg[0][31]\(16),
- I2 => \^axi_rdata_reg[17]_1\,
- I3 => \^axi_rdata_reg[18]_0\,
- O => \axi_rdata[16]_i_23_n_0\
- );
-\axi_rdata[16]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][16]\,
- I1 => \data_rw_o_reg_n_0_[26][16]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[25][16]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[24][16]\,
- O => \axi_rdata[16]_i_29_n_0\
- );
-\axi_rdata[16]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][16]\,
- I1 => \data_rw_o_reg_n_0_[30][16]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[29][16]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[28][16]\,
- O => \axi_rdata[16]_i_30_n_0\
- );
-\axi_rdata[16]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][16]\,
- I1 => \data_rw_o_reg_n_0_[18][16]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[17][16]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[16][16]\,
- O => \axi_rdata[16]_i_31_n_0\
- );
-\axi_rdata[16]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][16]\,
- I1 => \data_rw_o_reg_n_0_[22][16]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[21][16]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[20][16]\,
- O => \axi_rdata[16]_i_32_n_0\
- );
-\axi_rdata[16]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][16]\,
- I1 => \data_rw_o_reg_n_0_[10][16]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \s_datao_fmc1[0]\(16),
- I4 => \^axi_rdata_reg[17]_1\,
- O => \axi_rdata[16]_i_33_n_0\
- );
-\axi_rdata[16]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][16]\,
- I1 => \data_rw_o_reg_n_0_[34][16]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[33][16]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[32][16]\,
- O => \axi_rdata[16]_i_34_n_0\
- );
-\axi_rdata[16]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][16]\,
- I1 => \data_rw_o_reg_n_0_[90][16]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[89][16]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[88][16]\,
- O => \axi_rdata[16]_i_35_n_0\
- );
-\axi_rdata[16]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][16]\,
- I1 => \data_rw_o_reg_n_0_[94][16]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[93][16]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[92][16]\,
- O => \axi_rdata[16]_i_36_n_0\
- );
-\axi_rdata[16]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][16]\,
- I1 => \data_rw_o_reg_n_0_[86][16]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[85][16]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[84][16]\,
- O => \axi_rdata[16]_i_37_n_0\
- );
-\axi_rdata[16]_i_39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][16]\,
- I1 => \data_rw_o_reg_n_0_[78][16]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \s_datao_fmc2[0]\(16),
- I4 => \^axi_rdata_reg[17]_1\,
- O => \axi_rdata[16]_i_39_n_0\
- );
-\axi_rdata[16]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][16]\,
- I1 => \data_rw_o_reg_n_0_[98][16]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[97][16]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[96][16]\,
- O => \axi_rdata[16]_i_42_n_0\
- );
-\axi_rdata[16]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][16]\,
- I1 => \data_rw_o_reg_n_0_[102][16]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[101][16]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[100][16]\,
- O => \axi_rdata[16]_i_43_n_0\
- );
-\axi_rdata[16]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[16]_i_11_n_0\,
- I1 => \axi_rdata_reg[16]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[16]_i_13_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata[16]_i_14_n_0\,
- O => \axi_rdata[16]_i_5_n_0\
- );
-\axi_rdata[16]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][16]\,
- I2 => \^axi_rdata_reg[18]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][16]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[16]_i_17_n_0\,
- O => \axi_rdata[16]_i_6_n_0\
- );
-\axi_rdata[16]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[16]_i_18_n_0\,
- I1 => \axi_rdata[16]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[16]_i_20_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_araddr_reg[4]_rep_6\,
- O => \axi_rdata[16]_i_7_n_0\
- );
-\axi_rdata[16]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][16]_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[16]_i_23_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[16]_i_24_n_0\,
- O => \axi_rdata[16]_i_8_n_0\
- );
-\axi_rdata[17]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[17]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[17]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_2\,
- O => \axi_rdata[17]_i_1_n_0\
- );
-\axi_rdata[17]_i_13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"04FF0400"
- )
- port map (
- I0 => \^axi_rdata_reg[17]_1\,
- I1 => \s_datao_fmc1[4]\(9),
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \^axi_rdata_reg[18]_0\,
- I4 => \axi_rdata[17]_i_33_n_0\,
- O => \axi_rdata[17]_i_13_n_0\
- );
-\axi_rdata[17]_i_14\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"C800"
- )
- port map (
- I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[17]_0\,
- I2 => \data_rw_o_reg_n_0_[3][17]\,
- I3 => \^axi_rdata_reg[17]_1\,
- O => \axi_rdata[17]_i_14_n_0\
- );
-\axi_rdata[17]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[17]_i_34_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(17),
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[17]_i_17_n_0\
- );
-\axi_rdata[17]_i_19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88888B88"
- )
- port map (
- I0 => \axi_rdata[17]_i_37_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[17]_1\,
- I3 => \s_datao_fmc2[4]\(9),
- I4 => \^axi_rdata_reg[17]_0\,
- O => \axi_rdata[17]_i_19_n_0\
- );
-\axi_rdata[17]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[17]_0\,
- I1 => \dac_ch_o_reg[0][31]\(17),
- I2 => \^axi_rdata_reg[17]_1\,
- I3 => \^axi_rdata_reg[18]_0\,
- O => \axi_rdata[17]_i_23_n_0\
- );
-\axi_rdata[17]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][17]\,
- I1 => \data_rw_o_reg_n_0_[26][17]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[25][17]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[24][17]\,
- O => \axi_rdata[17]_i_29_n_0\
- );
-\axi_rdata[17]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][17]\,
- I1 => \data_rw_o_reg_n_0_[30][17]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[29][17]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[28][17]\,
- O => \axi_rdata[17]_i_30_n_0\
- );
-\axi_rdata[17]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][17]\,
- I1 => \data_rw_o_reg_n_0_[18][17]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[17][17]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[16][17]\,
- O => \axi_rdata[17]_i_31_n_0\
- );
-\axi_rdata[17]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][17]\,
- I1 => \data_rw_o_reg_n_0_[22][17]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[21][17]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[20][17]\,
- O => \axi_rdata[17]_i_32_n_0\
- );
-\axi_rdata[17]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][17]\,
- I1 => \data_rw_o_reg_n_0_[10][17]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \s_datao_fmc1[0]\(17),
- I4 => \^axi_rdata_reg[17]_1\,
- O => \axi_rdata[17]_i_33_n_0\
- );
-\axi_rdata[17]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][17]\,
- I1 => \data_rw_o_reg_n_0_[34][17]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[33][17]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[32][17]\,
- O => \axi_rdata[17]_i_34_n_0\
- );
-\axi_rdata[17]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][17]\,
- I1 => \data_rw_o_reg_n_0_[90][17]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[89][17]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[88][17]\,
- O => \axi_rdata[17]_i_35_n_0\
- );
-\axi_rdata[17]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][17]\,
- I1 => \data_rw_o_reg_n_0_[94][17]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[93][17]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[92][17]\,
- O => \axi_rdata[17]_i_36_n_0\
- );
-\axi_rdata[17]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][17]\,
- I1 => \data_rw_o_reg_n_0_[86][17]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[85][17]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[84][17]\,
- O => \axi_rdata[17]_i_37_n_0\
- );
-\axi_rdata[17]_i_39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][17]\,
- I1 => \data_rw_o_reg_n_0_[78][17]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \s_datao_fmc2[0]\(17),
- I4 => \^axi_rdata_reg[17]_1\,
- O => \axi_rdata[17]_i_39_n_0\
- );
-\axi_rdata[17]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][17]\,
- I1 => \data_rw_o_reg_n_0_[98][17]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[97][17]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[96][17]\,
- O => \axi_rdata[17]_i_42_n_0\
- );
-\axi_rdata[17]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][17]\,
- I1 => \data_rw_o_reg_n_0_[102][17]\,
- I2 => \^axi_rdata_reg[17]_0\,
- I3 => \data_rw_o_reg_n_0_[101][17]\,
- I4 => \^axi_rdata_reg[17]_1\,
- I5 => \data_rw_o_reg_n_0_[100][17]\,
- O => \axi_rdata[17]_i_43_n_0\
- );
-\axi_rdata[17]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[17]_i_11_n_0\,
- I1 => \axi_rdata_reg[17]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[17]_i_13_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata[17]_i_14_n_0\,
- O => \axi_rdata[17]_i_5_n_0\
- );
-\axi_rdata[17]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][17]\,
- I2 => \^axi_rdata_reg[18]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][17]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[17]_i_17_n_0\,
- O => \axi_rdata[17]_i_6_n_0\
- );
-\axi_rdata[17]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[17]_i_18_n_0\,
- I1 => \axi_rdata[17]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[17]_i_20_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_araddr_reg[4]_rep_7\,
- O => \axi_rdata[17]_i_7_n_0\
- );
-\axi_rdata[17]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][17]_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[17]_i_23_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[17]_i_24_n_0\,
- O => \axi_rdata[17]_i_8_n_0\
- );
-\axi_rdata[18]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[18]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[18]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_1\,
- O => \axi_rdata[18]_i_1_n_0\
- );
-\axi_rdata[18]_i_13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"04FF0400"
- )
- port map (
- I0 => \^axi_rdata_reg[22]_1\,
- I1 => \s_datao_fmc1[4]\(10),
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \^axi_rdata_reg[18]_0\,
- I4 => \axi_rdata[18]_i_33_n_0\,
- O => \axi_rdata[18]_i_13_n_0\
- );
-\axi_rdata[18]_i_14\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4088"
- )
- port map (
- I0 => \^axi_rdata_reg[18]_0\,
- I1 => \^axi_rdata_reg[22]_0\,
- I2 => \data_rw_o_reg_n_0_[3][18]\,
- I3 => \^axi_rdata_reg[22]_1\,
- O => \axi_rdata[18]_i_14_n_0\
- );
-\axi_rdata[18]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[18]_i_34_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(18),
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[18]_i_17_n_0\
- );
-\axi_rdata[18]_i_19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88888B88"
- )
- port map (
- I0 => \axi_rdata[18]_i_37_n_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => \^axi_rdata_reg[22]_1\,
- I3 => \s_datao_fmc2[4]\(10),
- I4 => \^axi_rdata_reg[22]_0\,
- O => \axi_rdata[18]_i_19_n_0\
- );
-\axi_rdata[18]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[22]_0\,
- I1 => \dac_ch_o_reg[0][31]\(18),
- I2 => \^axi_rdata_reg[22]_1\,
- I3 => \^axi_rdata_reg[18]_0\,
- O => \axi_rdata[18]_i_23_n_0\
- );
-\axi_rdata[18]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][18]\,
- I1 => \data_rw_o_reg_n_0_[26][18]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[25][18]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[24][18]\,
- O => \axi_rdata[18]_i_29_n_0\
- );
-\axi_rdata[18]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][18]\,
- I1 => \data_rw_o_reg_n_0_[30][18]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[29][18]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[28][18]\,
- O => \axi_rdata[18]_i_30_n_0\
- );
-\axi_rdata[18]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][18]\,
- I1 => \data_rw_o_reg_n_0_[18][18]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[17][18]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[16][18]\,
- O => \axi_rdata[18]_i_31_n_0\
- );
-\axi_rdata[18]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][18]\,
- I1 => \data_rw_o_reg_n_0_[22][18]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[21][18]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[20][18]\,
- O => \axi_rdata[18]_i_32_n_0\
- );
-\axi_rdata[18]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][18]\,
- I1 => \data_rw_o_reg_n_0_[10][18]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \s_datao_fmc1[0]\(18),
- I4 => \^axi_rdata_reg[22]_1\,
- O => \axi_rdata[18]_i_33_n_0\
- );
-\axi_rdata[18]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][18]\,
- I1 => \data_rw_o_reg_n_0_[34][18]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[33][18]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[32][18]\,
- O => \axi_rdata[18]_i_34_n_0\
- );
-\axi_rdata[18]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][18]\,
- I1 => \data_rw_o_reg_n_0_[90][18]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[89][18]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[88][18]\,
- O => \axi_rdata[18]_i_35_n_0\
- );
-\axi_rdata[18]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][18]\,
- I1 => \data_rw_o_reg_n_0_[94][18]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[93][18]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[92][18]\,
- O => \axi_rdata[18]_i_36_n_0\
- );
-\axi_rdata[18]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][18]\,
- I1 => \data_rw_o_reg_n_0_[86][18]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[85][18]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[84][18]\,
- O => \axi_rdata[18]_i_37_n_0\
- );
-\axi_rdata[18]_i_39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][18]\,
- I1 => \data_rw_o_reg_n_0_[78][18]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \s_datao_fmc2[0]\(18),
- I4 => \^axi_rdata_reg[22]_1\,
- O => \axi_rdata[18]_i_39_n_0\
- );
-\axi_rdata[18]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][18]\,
- I1 => \data_rw_o_reg_n_0_[98][18]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[97][18]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[96][18]\,
- O => \axi_rdata[18]_i_42_n_0\
- );
-\axi_rdata[18]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][18]\,
- I1 => \data_rw_o_reg_n_0_[102][18]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[101][18]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[100][18]\,
- O => \axi_rdata[18]_i_43_n_0\
- );
-\axi_rdata[18]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[18]_i_11_n_0\,
- I1 => \axi_rdata_reg[18]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[18]_i_13_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata[18]_i_14_n_0\,
- O => \axi_rdata[18]_i_5_n_0\
- );
-\axi_rdata[18]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][18]\,
- I2 => \^axi_rdata_reg[18]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][18]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[18]_i_17_n_0\,
- O => \axi_rdata[18]_i_6_n_0\
- );
-\axi_rdata[18]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[18]_i_18_n_0\,
- I1 => \axi_rdata[18]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[18]_i_20_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_araddr_reg[4]_rep_8\,
- O => \axi_rdata[18]_i_7_n_0\
- );
-\axi_rdata[18]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][18]_0\,
- I1 => \^axi_rdata_reg[18]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[18]_i_23_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[18]_i_24_n_0\,
- O => \axi_rdata[18]_i_8_n_0\
- );
-\axi_rdata[19]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[19]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[19]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_0\,
- O => \axi_rdata[19]_i_1_n_0\
- );
-\axi_rdata[19]_i_13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"04FF0400"
- )
- port map (
- I0 => \^axi_rdata_reg[22]_1\,
- I1 => \s_datao_fmc1[4]\(11),
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \axi_rdata[19]_i_33_n_0\,
- O => \axi_rdata[19]_i_13_n_0\
- );
-\axi_rdata[19]_i_14\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"C888"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(2),
- I1 => \^axi_rdata_reg[22]_0\,
- I2 => \data_rw_o_reg_n_0_[3][19]\,
- I3 => \^axi_rdata_reg[22]_1\,
- O => \axi_rdata[19]_i_14_n_0\
- );
-\axi_rdata[19]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[19]_i_34_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(19),
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[19]_i_17_n_0\
- );
-\axi_rdata[19]_i_19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88888B88"
- )
- port map (
- I0 => \axi_rdata[19]_i_37_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[22]_1\,
- I3 => \s_datao_fmc2[4]\(11),
- I4 => \^axi_rdata_reg[22]_0\,
- O => \axi_rdata[19]_i_19_n_0\
- );
-\axi_rdata[19]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[22]_0\,
- I1 => \dac_ch_o_reg[0][31]\(19),
- I2 => \^axi_rdata_reg[22]_1\,
- I3 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[19]_i_23_n_0\
- );
-\axi_rdata[19]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][19]\,
- I1 => \data_rw_o_reg_n_0_[26][19]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[25][19]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[24][19]\,
- O => \axi_rdata[19]_i_29_n_0\
- );
-\axi_rdata[19]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][19]\,
- I1 => \data_rw_o_reg_n_0_[30][19]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[29][19]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[28][19]\,
- O => \axi_rdata[19]_i_30_n_0\
- );
-\axi_rdata[19]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][19]\,
- I1 => \data_rw_o_reg_n_0_[18][19]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[17][19]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[16][19]\,
- O => \axi_rdata[19]_i_31_n_0\
- );
-\axi_rdata[19]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][19]\,
- I1 => \data_rw_o_reg_n_0_[22][19]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[21][19]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[20][19]\,
- O => \axi_rdata[19]_i_32_n_0\
- );
-\axi_rdata[19]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][19]\,
- I1 => \data_rw_o_reg_n_0_[10][19]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \s_datao_fmc1[0]\(19),
- I4 => \^axi_rdata_reg[22]_1\,
- O => \axi_rdata[19]_i_33_n_0\
- );
-\axi_rdata[19]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][19]\,
- I1 => \data_rw_o_reg_n_0_[34][19]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[33][19]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[32][19]\,
- O => \axi_rdata[19]_i_34_n_0\
- );
-\axi_rdata[19]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][19]\,
- I1 => \data_rw_o_reg_n_0_[90][19]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[89][19]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[88][19]\,
- O => \axi_rdata[19]_i_35_n_0\
- );
-\axi_rdata[19]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][19]\,
- I1 => \data_rw_o_reg_n_0_[94][19]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[93][19]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[92][19]\,
- O => \axi_rdata[19]_i_36_n_0\
- );
-\axi_rdata[19]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][19]\,
- I1 => \data_rw_o_reg_n_0_[86][19]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[85][19]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[84][19]\,
- O => \axi_rdata[19]_i_37_n_0\
- );
-\axi_rdata[19]_i_39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][19]\,
- I1 => \data_rw_o_reg_n_0_[78][19]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \s_datao_fmc2[0]\(19),
- I4 => \^axi_rdata_reg[22]_1\,
- O => \axi_rdata[19]_i_39_n_0\
- );
-\axi_rdata[19]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][19]\,
- I1 => \data_rw_o_reg_n_0_[98][19]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[97][19]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[96][19]\,
- O => \axi_rdata[19]_i_42_n_0\
- );
-\axi_rdata[19]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][19]\,
- I1 => \data_rw_o_reg_n_0_[102][19]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[101][19]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[100][19]\,
- O => \axi_rdata[19]_i_43_n_0\
- );
-\axi_rdata[19]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[19]_i_11_n_0\,
- I1 => \axi_rdata_reg[19]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[19]_i_13_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata[19]_i_14_n_0\,
- O => \axi_rdata[19]_i_5_n_0\
- );
-\axi_rdata[19]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][19]\,
- I2 => \^axi_rdata_reg[23]_0\(2),
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][19]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[19]_i_17_n_0\,
- O => \axi_rdata[19]_i_6_n_0\
- );
-\axi_rdata[19]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[19]_i_18_n_0\,
- I1 => \axi_rdata[19]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[19]_i_20_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_araddr_reg[4]_0\,
- O => \axi_rdata[19]_i_7_n_0\
- );
-\axi_rdata[19]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][19]_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => axi_araddr(6),
- I3 => \axi_rdata[19]_i_23_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[19]_i_24_n_0\,
- O => \axi_rdata[19]_i_8_n_0\
- );
-\axi_rdata[1]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[1]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[1]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_rep_9\,
- O => \axi_rdata[1]_i_1_n_0\
- );
-\axi_rdata[1]_i_14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"4455FA004400FA00"
- )
- port map (
- I0 => \^axi_rdata_reg[9]_0\,
- I1 => \data_rw_o[3]\(1),
- I2 => gem_status_vector_i(1),
- I3 => \^axi_rdata_reg[2]_0\,
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \s_ins_reg[3]\(1),
- O => \axi_rdata[1]_i_14_n_0\
- );
-\axi_rdata[1]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[1]_i_35_n_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(1),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^axi_rdata_reg[10]_0\,
- O => \axi_rdata[1]_i_17_n_0\
- );
-\axi_rdata[1]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[2]_0\,
- I1 => \dac_ch_o_reg[0][31]\(1),
- I2 => \^axi_rdata_reg[2]_1\,
- I3 => \^axi_rdata_reg[9]_0\,
- O => \axi_rdata[1]_i_23_n_0\
- );
-\axi_rdata[1]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]\(1),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]\(1),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]\(1),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]\(1),
- O => \axi_rdata[1]_i_29_n_0\
- );
-\axi_rdata[1]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]\(1),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]\(1),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]\(1),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]\(1),
- O => \axi_rdata[1]_i_30_n_0\
- );
-\axi_rdata[1]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^q\(1),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]\(1),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]\(1),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(1),
- O => \axi_rdata[1]_i_31_n_0\
- );
-\axi_rdata[1]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(1),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]\(1),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]\(1),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(1),
- O => \axi_rdata[1]_i_32_n_0\
- );
-\axi_rdata[1]_i_33\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^v_dout_reg[7]\(0),
- I1 => \data_rw_o_reg_n_0_[10][1]\,
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \data_o_reg[1][3]\(1),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \s_datao_fmc1[0]\(1),
- O => \axi_rdata[1]_i_33_n_0\
- );
-\axi_rdata[1]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]\(1),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]\(1),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]\(1),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]\(1),
- O => \axi_rdata[1]_i_35_n_0\
- );
-\axi_rdata[1]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(1),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(1),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(1),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(1),
- O => \axi_rdata[1]_i_36_n_0\
- );
-\axi_rdata[1]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(1),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(1),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(1),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(1),
- O => \axi_rdata[1]_i_37_n_0\
- );
-\axi_rdata[1]_i_39\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(1),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(1),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(1),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(1),
- O => \axi_rdata[1]_i_39_n_0\
- );
-\axi_rdata[1]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^v_dout_reg[7]_0\(0),
- I1 => \data_rw_o_reg_n_0_[78][1]\,
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \data_o_reg[1][3]_0\(1),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \s_datao_fmc2[0]\(1),
- O => \axi_rdata[1]_i_41_n_0\
- );
-\axi_rdata[1]_i_44\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(1),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(1),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(1),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(1),
- O => \axi_rdata[1]_i_44_n_0\
- );
-\axi_rdata[1]_i_45\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(1),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(1),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(1),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(1),
- O => \axi_rdata[1]_i_45_n_0\
- );
-\axi_rdata[1]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[1]_i_11_n_0\,
- I1 => \axi_rdata_reg[1]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[1]_i_13_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata[1]_i_14_n_0\,
- O => \axi_rdata[1]_i_5_n_0\
- );
-\axi_rdata[1]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[10]_0\,
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][1]\,
- I2 => \^axi_rdata_reg[9]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][1]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[1]_i_17_n_0\,
- O => \axi_rdata[1]_i_6_n_0\
- );
-\axi_rdata[1]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[1]_i_18_n_0\,
- I1 => \axi_rdata_reg[1]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[1]_i_20_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_araddr_reg[4]_rep__0_0\,
- O => \axi_rdata[1]_i_7_n_0\
- );
-\axi_rdata[1]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][1]_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[1]_i_23_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata_reg[1]_i_24_n_0\,
- O => \axi_rdata[1]_i_8_n_0\
- );
-\axi_rdata[20]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A8A8A8080808A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata[20]_i_2_n_0\,
- I2 => axi_araddr(9),
- I3 => \axi_araddr_reg[4]_7\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_araddr_reg[4]_8\,
- O => \axi_rdata[20]_i_1_n_0\
- );
-\axi_rdata[20]_i_14\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[22]_0\,
- I1 => \dac_ch_o_reg[0][31]\(20),
- I2 => \^axi_rdata_reg[22]_1\,
- I3 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[20]_i_14_n_0\
- );
-\axi_rdata[20]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata[20]_i_27_n_0\,
- I1 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][20]\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \fmc_03287_channels[15].gen_chs.data_o_reg[63][20]\,
- I4 => \^axi_rdata_reg[23]_0\(2),
- I5 => \fmc_03287_channels[11].gen_chs.data_o_reg[59][20]\,
- O => \axi_rdata[20]_i_16_n_0\
- );
-\axi_rdata[20]_i_17\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AFC0A0C0"
- )
- port map (
- I0 => \axi_rdata[20]_i_31_n_0\,
- I1 => \axi_rdata[20]_i_32_n_0\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \axi_rdata[20]_i_33_n_0\,
- O => \axi_rdata[20]_i_17_n_0\
- );
-\axi_rdata[20]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata[20]_i_5_n_0\,
- I1 => \axi_rdata_reg[20]_i_6_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata[20]_i_7_n_0\,
- I4 => axi_araddr(7),
- I5 => \axi_rdata[20]_i_8_n_0\,
- O => \axi_rdata[20]_i_2_n_0\
- );
-\axi_rdata[20]_i_20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[20]_i_34_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(20),
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[20]_i_20_n_0\
- );
-\axi_rdata[20]_i_23\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0000B800"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][20]\,
- I1 => \^axi_rdata_reg[22]_1\,
- I2 => \data_rw_o_reg_n_0_[10][20]\,
- I3 => \^axi_rdata_reg[22]_0\,
- I4 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[20]_i_23_n_0\
- );
-\axi_rdata[20]_i_24\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4088"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(2),
- I1 => \^axi_rdata_reg[22]_0\,
- I2 => \data_rw_o_reg_n_0_[3][20]\,
- I3 => \^axi_rdata_reg[22]_1\,
- O => \axi_rdata[20]_i_24_n_0\
- );
-\axi_rdata[20]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][20]\,
- I1 => \data_rw_o_reg_n_0_[98][20]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[97][20]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[96][20]\,
- O => \axi_rdata[20]_i_25_n_0\
- );
-\axi_rdata[20]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][20]\,
- I1 => \data_rw_o_reg_n_0_[102][20]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[101][20]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[100][20]\,
- O => \axi_rdata[20]_i_26_n_0\
- );
-\axi_rdata[20]_i_27\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"A808"
- )
- port map (
- I0 => \^axi_rdata_reg[22]_0\,
- I1 => \data_rw_o_reg_n_0_[78][20]\,
- I2 => \^axi_rdata_reg[22]_1\,
- I3 => \data_rw_o_reg_n_0_[79][20]\,
- O => \axi_rdata[20]_i_27_n_0\
- );
-\axi_rdata[20]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][20]\,
- I1 => \data_rw_o_reg_n_0_[94][20]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[93][20]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[92][20]\,
- O => \axi_rdata[20]_i_31_n_0\
- );
-\axi_rdata[20]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][20]\,
- I1 => \data_rw_o_reg_n_0_[90][20]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[89][20]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[88][20]\,
- O => \axi_rdata[20]_i_32_n_0\
- );
-\axi_rdata[20]_i_33\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][20]\,
- I1 => \data_rw_o_reg_n_0_[86][20]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[85][20]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[84][20]\,
- O => \axi_rdata[20]_i_33_n_0\
- );
-\axi_rdata[20]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][20]\,
- I1 => \data_rw_o_reg_n_0_[34][20]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[33][20]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[32][20]\,
- O => \axi_rdata[20]_i_34_n_0\
- );
-\axi_rdata[20]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][20]\,
- I1 => \data_rw_o_reg_n_0_[26][20]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[25][20]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[24][20]\,
- O => \axi_rdata[20]_i_35_n_0\
- );
-\axi_rdata[20]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][20]\,
- I1 => \data_rw_o_reg_n_0_[30][20]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[29][20]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[28][20]\,
- O => \axi_rdata[20]_i_36_n_0\
- );
-\axi_rdata[20]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][20]\,
- I1 => \data_rw_o_reg_n_0_[18][20]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[17][20]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[16][20]\,
- O => \axi_rdata[20]_i_37_n_0\
- );
-\axi_rdata[20]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][20]\,
- I1 => \data_rw_o_reg_n_0_[22][20]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[21][20]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[20][20]\,
- O => \axi_rdata[20]_i_38_n_0\
- );
-\axi_rdata[20]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][20]_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => axi_araddr(6),
- I3 => \axi_rdata[20]_i_14_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[20]_i_15_n_0\,
- O => \axi_rdata[20]_i_5_n_0\
- );
-\axi_rdata[20]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][20]\,
- I2 => \^axi_rdata_reg[23]_0\(2),
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][20]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[20]_i_20_n_0\,
- O => \axi_rdata[20]_i_7_n_0\
- );
-\axi_rdata[20]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[20]_i_21_n_0\,
- I1 => \axi_rdata_reg[20]_i_22_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[20]_i_23_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata[20]_i_24_n_0\,
- O => \axi_rdata[20]_i_8_n_0\
- );
-\axi_rdata[21]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A8A8A8080808A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata[21]_i_2_n_0\,
- I2 => axi_araddr(9),
- I3 => \axi_araddr_reg[4]_5\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_araddr_reg[4]_6\,
- O => \axi_rdata[21]_i_1_n_0\
- );
-\axi_rdata[21]_i_14\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[22]_0\,
- I1 => \dac_ch_o_reg[0][31]\(21),
- I2 => \^axi_rdata_reg[22]_1\,
- I3 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[21]_i_14_n_0\
- );
-\axi_rdata[21]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata[21]_i_27_n_0\,
- I1 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][21]\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \fmc_03287_channels[15].gen_chs.data_o_reg[63][21]\,
- I4 => \^axi_rdata_reg[23]_0\(2),
- I5 => \fmc_03287_channels[11].gen_chs.data_o_reg[59][21]\,
- O => \axi_rdata[21]_i_16_n_0\
- );
-\axi_rdata[21]_i_17\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AFC0A0C0"
- )
- port map (
- I0 => \axi_rdata[21]_i_31_n_0\,
- I1 => \axi_rdata[21]_i_32_n_0\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \axi_rdata[21]_i_33_n_0\,
- O => \axi_rdata[21]_i_17_n_0\
- );
-\axi_rdata[21]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata[21]_i_5_n_0\,
- I1 => \axi_rdata_reg[21]_i_6_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata[21]_i_7_n_0\,
- I4 => axi_araddr(7),
- I5 => \axi_rdata[21]_i_8_n_0\,
- O => \axi_rdata[21]_i_2_n_0\
- );
-\axi_rdata[21]_i_20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[21]_i_34_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(21),
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[21]_i_20_n_0\
- );
-\axi_rdata[21]_i_23\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0000B800"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][21]\,
- I1 => \^axi_rdata_reg[22]_1\,
- I2 => \data_rw_o_reg_n_0_[10][21]\,
- I3 => \^axi_rdata_reg[22]_0\,
- I4 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[21]_i_23_n_0\
- );
-\axi_rdata[21]_i_24\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0080"
- )
- port map (
- I0 => \^axi_rdata_reg[22]_1\,
- I1 => \data_rw_o_reg_n_0_[3][21]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[21]_i_24_n_0\
- );
-\axi_rdata[21]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][21]\,
- I1 => \data_rw_o_reg_n_0_[98][21]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[97][21]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[96][21]\,
- O => \axi_rdata[21]_i_25_n_0\
- );
-\axi_rdata[21]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][21]\,
- I1 => \data_rw_o_reg_n_0_[102][21]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[101][21]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[100][21]\,
- O => \axi_rdata[21]_i_26_n_0\
- );
-\axi_rdata[21]_i_27\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"A808"
- )
- port map (
- I0 => \^axi_rdata_reg[22]_0\,
- I1 => \data_rw_o_reg_n_0_[78][21]\,
- I2 => \^axi_rdata_reg[22]_1\,
- I3 => \data_rw_o_reg_n_0_[79][21]\,
- O => \axi_rdata[21]_i_27_n_0\
- );
-\axi_rdata[21]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][21]\,
- I1 => \data_rw_o_reg_n_0_[94][21]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[93][21]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[92][21]\,
- O => \axi_rdata[21]_i_31_n_0\
- );
-\axi_rdata[21]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][21]\,
- I1 => \data_rw_o_reg_n_0_[90][21]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[89][21]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[88][21]\,
- O => \axi_rdata[21]_i_32_n_0\
- );
-\axi_rdata[21]_i_33\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][21]\,
- I1 => \data_rw_o_reg_n_0_[86][21]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[85][21]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[84][21]\,
- O => \axi_rdata[21]_i_33_n_0\
- );
-\axi_rdata[21]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][21]\,
- I1 => \data_rw_o_reg_n_0_[34][21]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[33][21]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[32][21]\,
- O => \axi_rdata[21]_i_34_n_0\
- );
-\axi_rdata[21]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][21]\,
- I1 => \data_rw_o_reg_n_0_[26][21]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[25][21]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[24][21]\,
- O => \axi_rdata[21]_i_35_n_0\
- );
-\axi_rdata[21]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][21]\,
- I1 => \data_rw_o_reg_n_0_[30][21]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[29][21]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[28][21]\,
- O => \axi_rdata[21]_i_36_n_0\
- );
-\axi_rdata[21]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][21]\,
- I1 => \data_rw_o_reg_n_0_[18][21]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[17][21]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[16][21]\,
- O => \axi_rdata[21]_i_37_n_0\
- );
-\axi_rdata[21]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][21]\,
- I1 => \data_rw_o_reg_n_0_[22][21]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[21][21]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[20][21]\,
- O => \axi_rdata[21]_i_38_n_0\
- );
-\axi_rdata[21]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][21]_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => axi_araddr(6),
- I3 => \axi_rdata[21]_i_14_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[21]_i_15_n_0\,
- O => \axi_rdata[21]_i_5_n_0\
- );
-\axi_rdata[21]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][21]\,
- I2 => \^axi_rdata_reg[23]_0\(2),
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][21]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[21]_i_20_n_0\,
- O => \axi_rdata[21]_i_7_n_0\
- );
-\axi_rdata[21]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[21]_i_21_n_0\,
- I1 => \axi_rdata_reg[21]_i_22_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[21]_i_23_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata[21]_i_24_n_0\,
- O => \axi_rdata[21]_i_8_n_0\
- );
-\axi_rdata[22]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A8A8A8080808A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata[22]_i_2_n_0\,
- I2 => axi_araddr(9),
- I3 => \axi_araddr_reg[4]_3\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_araddr_reg[4]_4\,
- O => \axi_rdata[22]_i_1_n_0\
- );
-\axi_rdata[22]_i_14\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[22]_0\,
- I1 => \dac_ch_o_reg[0][31]\(22),
- I2 => \^axi_rdata_reg[22]_1\,
- I3 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[22]_i_14_n_0\
- );
-\axi_rdata[22]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata[22]_i_27_n_0\,
- I1 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][22]\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \fmc_03287_channels[15].gen_chs.data_o_reg[63][22]\,
- I4 => \^axi_rdata_reg[23]_0\(2),
- I5 => \fmc_03287_channels[11].gen_chs.data_o_reg[59][22]\,
- O => \axi_rdata[22]_i_16_n_0\
- );
-\axi_rdata[22]_i_17\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AFC0A0C0"
- )
- port map (
- I0 => \axi_rdata[22]_i_31_n_0\,
- I1 => \axi_rdata[22]_i_32_n_0\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \axi_rdata[22]_i_33_n_0\,
- O => \axi_rdata[22]_i_17_n_0\
- );
-\axi_rdata[22]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata[22]_i_5_n_0\,
- I1 => \axi_rdata_reg[22]_i_6_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata[22]_i_7_n_0\,
- I4 => axi_araddr(7),
- I5 => \axi_rdata[22]_i_8_n_0\,
- O => \axi_rdata[22]_i_2_n_0\
- );
-\axi_rdata[22]_i_20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[22]_i_34_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(22),
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[22]_i_20_n_0\
- );
-\axi_rdata[22]_i_23\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0000B800"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][22]\,
- I1 => \^axi_rdata_reg[22]_1\,
- I2 => \data_rw_o_reg_n_0_[10][22]\,
- I3 => \^axi_rdata_reg[22]_0\,
- I4 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[22]_i_23_n_0\
- );
-\axi_rdata[22]_i_24\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4088"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(2),
- I1 => \^axi_rdata_reg[22]_0\,
- I2 => \data_rw_o_reg_n_0_[3][22]\,
- I3 => \^axi_rdata_reg[22]_1\,
- O => \axi_rdata[22]_i_24_n_0\
- );
-\axi_rdata[22]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][22]\,
- I1 => \data_rw_o_reg_n_0_[98][22]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[97][22]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[96][22]\,
- O => \axi_rdata[22]_i_25_n_0\
- );
-\axi_rdata[22]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][22]\,
- I1 => \data_rw_o_reg_n_0_[102][22]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[101][22]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[100][22]\,
- O => \axi_rdata[22]_i_26_n_0\
- );
-\axi_rdata[22]_i_27\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"A808"
- )
- port map (
- I0 => \^axi_rdata_reg[22]_0\,
- I1 => \data_rw_o_reg_n_0_[78][22]\,
- I2 => \^axi_rdata_reg[22]_1\,
- I3 => \data_rw_o_reg_n_0_[79][22]\,
- O => \axi_rdata[22]_i_27_n_0\
- );
-\axi_rdata[22]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][22]\,
- I1 => \data_rw_o_reg_n_0_[94][22]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[93][22]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[92][22]\,
- O => \axi_rdata[22]_i_31_n_0\
- );
-\axi_rdata[22]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][22]\,
- I1 => \data_rw_o_reg_n_0_[90][22]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[89][22]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[88][22]\,
- O => \axi_rdata[22]_i_32_n_0\
- );
-\axi_rdata[22]_i_33\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][22]\,
- I1 => \data_rw_o_reg_n_0_[86][22]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[85][22]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[84][22]\,
- O => \axi_rdata[22]_i_33_n_0\
- );
-\axi_rdata[22]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][22]\,
- I1 => \data_rw_o_reg_n_0_[34][22]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[33][22]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[32][22]\,
- O => \axi_rdata[22]_i_34_n_0\
- );
-\axi_rdata[22]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][22]\,
- I1 => \data_rw_o_reg_n_0_[26][22]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[25][22]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[24][22]\,
- O => \axi_rdata[22]_i_35_n_0\
- );
-\axi_rdata[22]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][22]\,
- I1 => \data_rw_o_reg_n_0_[30][22]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[29][22]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[28][22]\,
- O => \axi_rdata[22]_i_36_n_0\
- );
-\axi_rdata[22]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][22]\,
- I1 => \data_rw_o_reg_n_0_[18][22]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[17][22]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[16][22]\,
- O => \axi_rdata[22]_i_37_n_0\
- );
-\axi_rdata[22]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][22]\,
- I1 => \data_rw_o_reg_n_0_[22][22]\,
- I2 => \^axi_rdata_reg[22]_0\,
- I3 => \data_rw_o_reg_n_0_[21][22]\,
- I4 => \^axi_rdata_reg[22]_1\,
- I5 => \data_rw_o_reg_n_0_[20][22]\,
- O => \axi_rdata[22]_i_38_n_0\
- );
-\axi_rdata[22]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][22]_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => axi_araddr(6),
- I3 => \axi_rdata[22]_i_14_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[22]_i_15_n_0\,
- O => \axi_rdata[22]_i_5_n_0\
- );
-\axi_rdata[22]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][22]\,
- I2 => \^axi_rdata_reg[23]_0\(2),
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][22]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[22]_i_20_n_0\,
- O => \axi_rdata[22]_i_7_n_0\
- );
-\axi_rdata[22]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[22]_i_21_n_0\,
- I1 => \axi_rdata_reg[22]_i_22_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[22]_i_23_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata[22]_i_24_n_0\,
- O => \axi_rdata[22]_i_8_n_0\
- );
-\axi_rdata[23]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A8A8A8080808A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata[23]_i_3_n_0\,
- I2 => axi_araddr(9),
- I3 => \axi_araddr_reg[4]_1\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_araddr_reg[4]_2\,
- O => \axi_rdata[23]_i_1_n_0\
- );
-\axi_rdata[23]_i_15\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(1),
- I1 => \dac_ch_o_reg[0][31]\(23),
- I2 => \^axi_rdata_reg[23]_0\(0),
- I3 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[23]_i_15_n_0\
- );
-\axi_rdata[23]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata[23]_i_28_n_0\,
- I1 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\,
- I4 => \^axi_rdata_reg[23]_0\(2),
- I5 => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\,
- O => \axi_rdata[23]_i_17_n_0\
- );
-\axi_rdata[23]_i_18\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AFC0A0C0"
- )
- port map (
- I0 => \axi_rdata[23]_i_32_n_0\,
- I1 => \axi_rdata[23]_i_33_n_0\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \axi_rdata[23]_i_34_n_0\,
- O => \axi_rdata[23]_i_18_n_0\
- );
-\axi_rdata[23]_i_2\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"01FF"
- )
- port map (
- I0 => axi_araddr(7),
- I1 => axi_araddr(6),
- I2 => axi_araddr(8),
- I3 => axi_araddr(9),
- O => \axi_rdata[23]_i_2_n_0\
- );
-\axi_rdata[23]_i_21\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[23]_i_35_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \dac_ch_o_reg[0][31]_0\(23),
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[23]_i_21_n_0\
- );
-\axi_rdata[23]_i_24\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0000B800"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][23]\,
- I1 => \^axi_rdata_reg[23]_0\(0),
- I2 => \data_rw_o_reg_n_0_[10][23]\,
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[23]_i_24_n_0\
- );
-\axi_rdata[23]_i_25\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"C888"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(2),
- I1 => \^axi_rdata_reg[23]_0\(1),
- I2 => \data_rw_o_reg_n_0_[3][23]\,
- I3 => \^axi_rdata_reg[23]_0\(0),
- O => \axi_rdata[23]_i_25_n_0\
- );
-\axi_rdata[23]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][23]\,
- I1 => \data_rw_o_reg_n_0_[98][23]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[97][23]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[96][23]\,
- O => \axi_rdata[23]_i_26_n_0\
- );
-\axi_rdata[23]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][23]\,
- I1 => \data_rw_o_reg_n_0_[102][23]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[101][23]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[100][23]\,
- O => \axi_rdata[23]_i_27_n_0\
- );
-\axi_rdata[23]_i_28\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"A808"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(1),
- I1 => \data_rw_o_reg_n_0_[78][23]\,
- I2 => \^axi_rdata_reg[23]_0\(0),
- I3 => \data_rw_o_reg_n_0_[79][23]\,
- O => \axi_rdata[23]_i_28_n_0\
- );
-\axi_rdata[23]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata[23]_i_6_n_0\,
- I1 => \axi_rdata_reg[23]_i_7_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata[23]_i_8_n_0\,
- I4 => axi_araddr(7),
- I5 => \axi_rdata[23]_i_9_n_0\,
- O => \axi_rdata[23]_i_3_n_0\
- );
-\axi_rdata[23]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][23]\,
- I1 => \data_rw_o_reg_n_0_[94][23]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[93][23]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[92][23]\,
- O => \axi_rdata[23]_i_32_n_0\
- );
-\axi_rdata[23]_i_33\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][23]\,
- I1 => \data_rw_o_reg_n_0_[90][23]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[89][23]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[88][23]\,
- O => \axi_rdata[23]_i_33_n_0\
- );
-\axi_rdata[23]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][23]\,
- I1 => \data_rw_o_reg_n_0_[86][23]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[85][23]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[84][23]\,
- O => \axi_rdata[23]_i_34_n_0\
- );
-\axi_rdata[23]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][23]\,
- I1 => \data_rw_o_reg_n_0_[34][23]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[33][23]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[32][23]\,
- O => \axi_rdata[23]_i_35_n_0\
- );
-\axi_rdata[23]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][23]\,
- I1 => \data_rw_o_reg_n_0_[26][23]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[25][23]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[24][23]\,
- O => \axi_rdata[23]_i_36_n_0\
- );
-\axi_rdata[23]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][23]\,
- I1 => \data_rw_o_reg_n_0_[30][23]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[29][23]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[28][23]\,
- O => \axi_rdata[23]_i_37_n_0\
- );
-\axi_rdata[23]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][23]\,
- I1 => \data_rw_o_reg_n_0_[18][23]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[17][23]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[16][23]\,
- O => \axi_rdata[23]_i_38_n_0\
- );
-\axi_rdata[23]_i_39\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][23]\,
- I1 => \data_rw_o_reg_n_0_[22][23]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[21][23]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[20][23]\,
- O => \axi_rdata[23]_i_39_n_0\
- );
-\axi_rdata[23]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => axi_araddr(6),
- I3 => \axi_rdata[23]_i_15_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[23]_i_16_n_0\,
- O => \axi_rdata[23]_i_6_n_0\
- );
-\axi_rdata[23]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\,
- I2 => \^axi_rdata_reg[23]_0\(2),
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[23]_i_21_n_0\,
- O => \axi_rdata[23]_i_8_n_0\
- );
-\axi_rdata[23]_i_9\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[23]_i_22_n_0\,
- I1 => \axi_rdata_reg[23]_i_23_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[23]_i_24_n_0\,
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata[23]_i_25_n_0\,
- O => \axi_rdata[23]_i_9_n_0\
- );
-\axi_rdata[24]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4540"
- )
- port map (
- I0 => axi_araddr(9),
- I1 => \axi_rdata[24]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata[24]_i_3_n_0\,
- O => \axi_rdata[24]_i_1_n_0\
- );
-\axi_rdata[24]_i_11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][24]\,
- I1 => \data_rw_o_reg_n_0_[94][24]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[93][24]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[92][24]\,
- O => \axi_rdata[24]_i_11_n_0\
- );
-\axi_rdata[24]_i_12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][24]\,
- I1 => \data_rw_o_reg_n_0_[90][24]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[89][24]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[88][24]\,
- O => \axi_rdata[24]_i_12_n_0\
- );
-\axi_rdata[24]_i_13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][24]\,
- I1 => \data_rw_o_reg_n_0_[86][24]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[85][24]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[84][24]\,
- O => \axi_rdata[24]_i_13_n_0\
- );
-\axi_rdata[24]_i_14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][24]\,
- I1 => \data_rw_o_reg_n_0_[34][24]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[33][24]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[32][24]\,
- O => \axi_rdata[24]_i_14_n_0\
- );
-\axi_rdata[24]_i_17\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0000B800"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][24]\,
- I1 => \^axi_rdata_reg[23]_0\(0),
- I2 => \data_rw_o_reg_n_0_[10][24]\,
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[24]_i_17_n_0\
- );
-\axi_rdata[24]_i_18\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][24]\,
- I1 => \data_rw_o_reg_n_0_[98][24]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[97][24]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[96][24]\,
- O => \axi_rdata[24]_i_18_n_0\
- );
-\axi_rdata[24]_i_19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][24]\,
- I1 => \data_rw_o_reg_n_0_[102][24]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[101][24]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[100][24]\,
- O => \axi_rdata[24]_i_19_n_0\
- );
-\axi_rdata[24]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[24]_i_4_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata[24]_i_5_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[24]_i_6_n_0\,
- O => \axi_rdata[24]_i_2_n_0\
- );
-\axi_rdata[24]_i_20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][24]\,
- I1 => \data_rw_o_reg_n_0_[18][24]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[17][24]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[16][24]\,
- O => \axi_rdata[24]_i_20_n_0\
- );
-\axi_rdata[24]_i_21\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][24]\,
- I1 => \data_rw_o_reg_n_0_[22][24]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[21][24]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[20][24]\,
- O => \axi_rdata[24]_i_21_n_0\
- );
-\axi_rdata[24]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][24]\,
- I1 => \data_rw_o_reg_n_0_[26][24]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[25][24]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[24][24]\,
- O => \axi_rdata[24]_i_22_n_0\
- );
-\axi_rdata[24]_i_23\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][24]\,
- I1 => \data_rw_o_reg_n_0_[30][24]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[29][24]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[28][24]\,
- O => \axi_rdata[24]_i_23_n_0\
- );
-\axi_rdata[24]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[24]_i_7_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata_reg[24]_i_8_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[24]_i_9_n_0\,
- O => \axi_rdata[24]_i_3_n_0\
- );
-\axi_rdata[24]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0004FFFF00040000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(1),
- I1 => \dac_ch_o_reg[0][31]\(24),
- I2 => \^axi_rdata_reg[23]_0\(0),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[24]_i_10_n_0\,
- O => \axi_rdata[24]_i_4_n_0\
- );
-\axi_rdata[24]_i_5\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AFC0A0C0"
- )
- port map (
- I0 => \axi_rdata[24]_i_11_n_0\,
- I1 => \axi_rdata[24]_i_12_n_0\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \axi_rdata[24]_i_13_n_0\,
- O => \axi_rdata[24]_i_5_n_0\
- );
-\axi_rdata[24]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8880008000000000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \^axi_rdata_reg[23]_0\(1),
- I2 => \data_rw_o_reg_n_0_[78][24]\,
- I3 => \^axi_rdata_reg[23]_0\(0),
- I4 => \data_rw_o_reg_n_0_[79][24]\,
- I5 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[24]_i_6_n_0\
- );
-\axi_rdata[24]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[24]_i_14_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \dac_ch_o_reg[0][31]_0\(24),
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[24]_i_7_n_0\
- );
-\axi_rdata[24]_i_9\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8B888888B888B888"
- )
- port map (
- I0 => \axi_rdata[24]_i_17_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(3),
- I2 => \^axi_rdata_reg[23]_0\(2),
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \data_rw_o_reg_n_0_[3][24]\,
- I5 => \^axi_rdata_reg[23]_0\(0),
- O => \axi_rdata[24]_i_9_n_0\
- );
-\axi_rdata[25]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4540"
- )
- port map (
- I0 => axi_araddr(9),
- I1 => \axi_rdata[25]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata[25]_i_3_n_0\,
- O => \axi_rdata[25]_i_1_n_0\
- );
-\axi_rdata[25]_i_11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][25]\,
- I1 => \data_rw_o_reg_n_0_[94][25]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[93][25]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[92][25]\,
- O => \axi_rdata[25]_i_11_n_0\
- );
-\axi_rdata[25]_i_12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][25]\,
- I1 => \data_rw_o_reg_n_0_[90][25]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[89][25]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[88][25]\,
- O => \axi_rdata[25]_i_12_n_0\
- );
-\axi_rdata[25]_i_13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][25]\,
- I1 => \data_rw_o_reg_n_0_[86][25]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[85][25]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[84][25]\,
- O => \axi_rdata[25]_i_13_n_0\
- );
-\axi_rdata[25]_i_14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][25]\,
- I1 => \data_rw_o_reg_n_0_[34][25]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[33][25]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[32][25]\,
- O => \axi_rdata[25]_i_14_n_0\
- );
-\axi_rdata[25]_i_17\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0000B800"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][25]\,
- I1 => \^axi_rdata_reg[23]_0\(0),
- I2 => \data_rw_o_reg_n_0_[10][25]\,
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[25]_i_17_n_0\
- );
-\axi_rdata[25]_i_18\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][25]\,
- I1 => \data_rw_o_reg_n_0_[98][25]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[97][25]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[96][25]\,
- O => \axi_rdata[25]_i_18_n_0\
- );
-\axi_rdata[25]_i_19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][25]\,
- I1 => \data_rw_o_reg_n_0_[102][25]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[101][25]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[100][25]\,
- O => \axi_rdata[25]_i_19_n_0\
- );
-\axi_rdata[25]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[25]_i_4_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata[25]_i_5_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[25]_i_6_n_0\,
- O => \axi_rdata[25]_i_2_n_0\
- );
-\axi_rdata[25]_i_20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][25]\,
- I1 => \data_rw_o_reg_n_0_[18][25]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[17][25]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[16][25]\,
- O => \axi_rdata[25]_i_20_n_0\
- );
-\axi_rdata[25]_i_21\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][25]\,
- I1 => \data_rw_o_reg_n_0_[22][25]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[21][25]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[20][25]\,
- O => \axi_rdata[25]_i_21_n_0\
- );
-\axi_rdata[25]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][25]\,
- I1 => \data_rw_o_reg_n_0_[26][25]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[25][25]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[24][25]\,
- O => \axi_rdata[25]_i_22_n_0\
- );
-\axi_rdata[25]_i_23\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][25]\,
- I1 => \data_rw_o_reg_n_0_[30][25]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[29][25]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[28][25]\,
- O => \axi_rdata[25]_i_23_n_0\
- );
-\axi_rdata[25]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[25]_i_7_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata_reg[25]_i_8_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[25]_i_9_n_0\,
- O => \axi_rdata[25]_i_3_n_0\
- );
-\axi_rdata[25]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0004FFFF00040000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(1),
- I1 => \dac_ch_o_reg[0][31]\(25),
- I2 => \^axi_rdata_reg[23]_0\(0),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[25]_i_10_n_0\,
- O => \axi_rdata[25]_i_4_n_0\
- );
-\axi_rdata[25]_i_5\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AFC0A0C0"
- )
- port map (
- I0 => \axi_rdata[25]_i_11_n_0\,
- I1 => \axi_rdata[25]_i_12_n_0\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \axi_rdata[25]_i_13_n_0\,
- O => \axi_rdata[25]_i_5_n_0\
- );
-\axi_rdata[25]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8880008000000000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \^axi_rdata_reg[23]_0\(1),
- I2 => \data_rw_o_reg_n_0_[78][25]\,
- I3 => \^axi_rdata_reg[23]_0\(0),
- I4 => \data_rw_o_reg_n_0_[79][25]\,
- I5 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[25]_i_6_n_0\
- );
-\axi_rdata[25]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[25]_i_14_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \dac_ch_o_reg[0][31]_0\(25),
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[25]_i_7_n_0\
- );
-\axi_rdata[25]_i_9\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"88888888B8888888"
- )
- port map (
- I0 => \axi_rdata[25]_i_17_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(3),
- I2 => \^axi_rdata_reg[23]_0\(0),
- I3 => \data_rw_o_reg_n_0_[3][25]\,
- I4 => \^axi_rdata_reg[23]_0\(1),
- I5 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[25]_i_9_n_0\
- );
-\axi_rdata[26]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4540"
- )
- port map (
- I0 => axi_araddr(9),
- I1 => \axi_rdata[26]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata[26]_i_3_n_0\,
- O => \axi_rdata[26]_i_1_n_0\
- );
-\axi_rdata[26]_i_11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][26]\,
- I1 => \data_rw_o_reg_n_0_[94][26]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[93][26]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[92][26]\,
- O => \axi_rdata[26]_i_11_n_0\
- );
-\axi_rdata[26]_i_12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][26]\,
- I1 => \data_rw_o_reg_n_0_[90][26]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[89][26]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[88][26]\,
- O => \axi_rdata[26]_i_12_n_0\
- );
-\axi_rdata[26]_i_13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][26]\,
- I1 => \data_rw_o_reg_n_0_[86][26]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[85][26]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[84][26]\,
- O => \axi_rdata[26]_i_13_n_0\
- );
-\axi_rdata[26]_i_14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][26]\,
- I1 => \data_rw_o_reg_n_0_[34][26]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[33][26]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[32][26]\,
- O => \axi_rdata[26]_i_14_n_0\
- );
-\axi_rdata[26]_i_17\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0000B800"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][26]\,
- I1 => \^axi_rdata_reg[23]_0\(0),
- I2 => \data_rw_o_reg_n_0_[10][26]\,
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[26]_i_17_n_0\
- );
-\axi_rdata[26]_i_18\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][26]\,
- I1 => \data_rw_o_reg_n_0_[98][26]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[97][26]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[96][26]\,
- O => \axi_rdata[26]_i_18_n_0\
- );
-\axi_rdata[26]_i_19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][26]\,
- I1 => \data_rw_o_reg_n_0_[102][26]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[101][26]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[100][26]\,
- O => \axi_rdata[26]_i_19_n_0\
- );
-\axi_rdata[26]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[26]_i_4_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata[26]_i_5_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[26]_i_6_n_0\,
- O => \axi_rdata[26]_i_2_n_0\
- );
-\axi_rdata[26]_i_20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][26]\,
- I1 => \data_rw_o_reg_n_0_[18][26]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[17][26]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[16][26]\,
- O => \axi_rdata[26]_i_20_n_0\
- );
-\axi_rdata[26]_i_21\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][26]\,
- I1 => \data_rw_o_reg_n_0_[22][26]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[21][26]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[20][26]\,
- O => \axi_rdata[26]_i_21_n_0\
- );
-\axi_rdata[26]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][26]\,
- I1 => \data_rw_o_reg_n_0_[26][26]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[25][26]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[24][26]\,
- O => \axi_rdata[26]_i_22_n_0\
- );
-\axi_rdata[26]_i_23\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][26]\,
- I1 => \data_rw_o_reg_n_0_[30][26]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[29][26]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[28][26]\,
- O => \axi_rdata[26]_i_23_n_0\
- );
-\axi_rdata[26]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[26]_i_7_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata_reg[26]_i_8_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[26]_i_9_n_0\,
- O => \axi_rdata[26]_i_3_n_0\
- );
-\axi_rdata[26]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0004FFFF00040000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(1),
- I1 => \dac_ch_o_reg[0][31]\(26),
- I2 => \^axi_rdata_reg[23]_0\(0),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[26]_i_10_n_0\,
- O => \axi_rdata[26]_i_4_n_0\
- );
-\axi_rdata[26]_i_5\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AFC0A0C0"
- )
- port map (
- I0 => \axi_rdata[26]_i_11_n_0\,
- I1 => \axi_rdata[26]_i_12_n_0\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \axi_rdata[26]_i_13_n_0\,
- O => \axi_rdata[26]_i_5_n_0\
- );
-\axi_rdata[26]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8880008000000000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \^axi_rdata_reg[23]_0\(1),
- I2 => \data_rw_o_reg_n_0_[78][26]\,
- I3 => \^axi_rdata_reg[23]_0\(0),
- I4 => \data_rw_o_reg_n_0_[79][26]\,
- I5 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[26]_i_6_n_0\
- );
-\axi_rdata[26]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[26]_i_14_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \dac_ch_o_reg[0][31]_0\(26),
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[26]_i_7_n_0\
- );
-\axi_rdata[26]_i_9\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"88888888B8888888"
- )
- port map (
- I0 => \axi_rdata[26]_i_17_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(3),
- I2 => \^axi_rdata_reg[23]_0\(0),
- I3 => \data_rw_o_reg_n_0_[3][26]\,
- I4 => \^axi_rdata_reg[23]_0\(1),
- I5 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[26]_i_9_n_0\
- );
-\axi_rdata[27]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4540"
- )
- port map (
- I0 => axi_araddr(9),
- I1 => \axi_rdata[27]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata[27]_i_3_n_0\,
- O => \axi_rdata[27]_i_1_n_0\
- );
-\axi_rdata[27]_i_11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][27]\,
- I1 => \data_rw_o_reg_n_0_[94][27]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[93][27]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[92][27]\,
- O => \axi_rdata[27]_i_11_n_0\
- );
-\axi_rdata[27]_i_12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][27]\,
- I1 => \data_rw_o_reg_n_0_[90][27]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[89][27]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[88][27]\,
- O => \axi_rdata[27]_i_12_n_0\
- );
-\axi_rdata[27]_i_13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][27]\,
- I1 => \data_rw_o_reg_n_0_[86][27]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[85][27]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[84][27]\,
- O => \axi_rdata[27]_i_13_n_0\
- );
-\axi_rdata[27]_i_14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][27]\,
- I1 => \data_rw_o_reg_n_0_[34][27]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[33][27]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[32][27]\,
- O => \axi_rdata[27]_i_14_n_0\
- );
-\axi_rdata[27]_i_17\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0000B800"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][27]\,
- I1 => \^axi_rdata_reg[23]_0\(0),
- I2 => \data_rw_o_reg_n_0_[10][27]\,
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[27]_i_17_n_0\
- );
-\axi_rdata[27]_i_18\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][27]\,
- I1 => \data_rw_o_reg_n_0_[98][27]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[97][27]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[96][27]\,
- O => \axi_rdata[27]_i_18_n_0\
- );
-\axi_rdata[27]_i_19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][27]\,
- I1 => \data_rw_o_reg_n_0_[102][27]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[101][27]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[100][27]\,
- O => \axi_rdata[27]_i_19_n_0\
- );
-\axi_rdata[27]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[27]_i_4_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata[27]_i_5_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[27]_i_6_n_0\,
- O => \axi_rdata[27]_i_2_n_0\
- );
-\axi_rdata[27]_i_20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][27]\,
- I1 => \data_rw_o_reg_n_0_[18][27]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[17][27]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[16][27]\,
- O => \axi_rdata[27]_i_20_n_0\
- );
-\axi_rdata[27]_i_21\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][27]\,
- I1 => \data_rw_o_reg_n_0_[22][27]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[21][27]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[20][27]\,
- O => \axi_rdata[27]_i_21_n_0\
- );
-\axi_rdata[27]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][27]\,
- I1 => \data_rw_o_reg_n_0_[26][27]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[25][27]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[24][27]\,
- O => \axi_rdata[27]_i_22_n_0\
- );
-\axi_rdata[27]_i_23\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][27]\,
- I1 => \data_rw_o_reg_n_0_[30][27]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[29][27]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[28][27]\,
- O => \axi_rdata[27]_i_23_n_0\
- );
-\axi_rdata[27]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[27]_i_7_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata_reg[27]_i_8_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[27]_i_9_n_0\,
- O => \axi_rdata[27]_i_3_n_0\
- );
-\axi_rdata[27]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0004FFFF00040000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(1),
- I1 => \dac_ch_o_reg[0][31]\(27),
- I2 => \^axi_rdata_reg[23]_0\(0),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[27]_i_10_n_0\,
- O => \axi_rdata[27]_i_4_n_0\
- );
-\axi_rdata[27]_i_5\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AFC0A0C0"
- )
- port map (
- I0 => \axi_rdata[27]_i_11_n_0\,
- I1 => \axi_rdata[27]_i_12_n_0\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \axi_rdata[27]_i_13_n_0\,
- O => \axi_rdata[27]_i_5_n_0\
- );
-\axi_rdata[27]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8880008000000000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \^axi_rdata_reg[23]_0\(1),
- I2 => \data_rw_o_reg_n_0_[78][27]\,
- I3 => \^axi_rdata_reg[23]_0\(0),
- I4 => \data_rw_o_reg_n_0_[79][27]\,
- I5 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[27]_i_6_n_0\
- );
-\axi_rdata[27]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[27]_i_14_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \dac_ch_o_reg[0][31]_0\(27),
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[27]_i_7_n_0\
- );
-\axi_rdata[27]_i_9\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8B888888B888B888"
- )
- port map (
- I0 => \axi_rdata[27]_i_17_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(3),
- I2 => \^axi_rdata_reg[23]_0\(2),
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \data_rw_o_reg_n_0_[3][27]\,
- I5 => \^axi_rdata_reg[23]_0\(0),
- O => \axi_rdata[27]_i_9_n_0\
- );
-\axi_rdata[28]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4540"
- )
- port map (
- I0 => axi_araddr(9),
- I1 => \axi_rdata[28]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata[28]_i_3_n_0\,
- O => \axi_rdata[28]_i_1_n_0\
- );
-\axi_rdata[28]_i_11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][28]\,
- I1 => \data_rw_o_reg_n_0_[94][28]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[93][28]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[92][28]\,
- O => \axi_rdata[28]_i_11_n_0\
- );
-\axi_rdata[28]_i_12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][28]\,
- I1 => \data_rw_o_reg_n_0_[90][28]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[89][28]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[88][28]\,
- O => \axi_rdata[28]_i_12_n_0\
- );
-\axi_rdata[28]_i_13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][28]\,
- I1 => \data_rw_o_reg_n_0_[86][28]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[85][28]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[84][28]\,
- O => \axi_rdata[28]_i_13_n_0\
- );
-\axi_rdata[28]_i_14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][28]\,
- I1 => \data_rw_o_reg_n_0_[34][28]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[33][28]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[32][28]\,
- O => \axi_rdata[28]_i_14_n_0\
- );
-\axi_rdata[28]_i_17\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0000B800"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][28]\,
- I1 => \^axi_rdata_reg[23]_0\(0),
- I2 => \data_rw_o_reg_n_0_[10][28]\,
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[28]_i_17_n_0\
- );
-\axi_rdata[28]_i_18\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][28]\,
- I1 => \data_rw_o_reg_n_0_[98][28]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[97][28]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[96][28]\,
- O => \axi_rdata[28]_i_18_n_0\
- );
-\axi_rdata[28]_i_19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][28]\,
- I1 => \data_rw_o_reg_n_0_[102][28]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[101][28]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[100][28]\,
- O => \axi_rdata[28]_i_19_n_0\
- );
-\axi_rdata[28]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[28]_i_4_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata[28]_i_5_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[28]_i_6_n_0\,
- O => \axi_rdata[28]_i_2_n_0\
- );
-\axi_rdata[28]_i_20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][28]\,
- I1 => \data_rw_o_reg_n_0_[18][28]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[17][28]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[16][28]\,
- O => \axi_rdata[28]_i_20_n_0\
- );
-\axi_rdata[28]_i_21\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][28]\,
- I1 => \data_rw_o_reg_n_0_[22][28]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[21][28]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[20][28]\,
- O => \axi_rdata[28]_i_21_n_0\
- );
-\axi_rdata[28]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][28]\,
- I1 => \data_rw_o_reg_n_0_[26][28]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[25][28]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[24][28]\,
- O => \axi_rdata[28]_i_22_n_0\
- );
-\axi_rdata[28]_i_23\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][28]\,
- I1 => \data_rw_o_reg_n_0_[30][28]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[29][28]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[28][28]\,
- O => \axi_rdata[28]_i_23_n_0\
- );
-\axi_rdata[28]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[28]_i_7_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata_reg[28]_i_8_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[28]_i_9_n_0\,
- O => \axi_rdata[28]_i_3_n_0\
- );
-\axi_rdata[28]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0004FFFF00040000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(1),
- I1 => \dac_ch_o_reg[0][31]\(28),
- I2 => \^axi_rdata_reg[23]_0\(0),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[28]_i_10_n_0\,
- O => \axi_rdata[28]_i_4_n_0\
- );
-\axi_rdata[28]_i_5\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AFC0A0C0"
- )
- port map (
- I0 => \axi_rdata[28]_i_11_n_0\,
- I1 => \axi_rdata[28]_i_12_n_0\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \axi_rdata[28]_i_13_n_0\,
- O => \axi_rdata[28]_i_5_n_0\
- );
-\axi_rdata[28]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8880008000000000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \^axi_rdata_reg[23]_0\(1),
- I2 => \data_rw_o_reg_n_0_[78][28]\,
- I3 => \^axi_rdata_reg[23]_0\(0),
- I4 => \data_rw_o_reg_n_0_[79][28]\,
- I5 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[28]_i_6_n_0\
- );
-\axi_rdata[28]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[28]_i_14_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \dac_ch_o_reg[0][31]_0\(28),
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[28]_i_7_n_0\
- );
-\axi_rdata[28]_i_9\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"BB88B888B888B888"
- )
- port map (
- I0 => \axi_rdata[28]_i_17_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(3),
- I2 => \^axi_rdata_reg[23]_0\(2),
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \data_rw_o_reg_n_0_[3][28]\,
- I5 => \^axi_rdata_reg[23]_0\(0),
- O => \axi_rdata[28]_i_9_n_0\
- );
-\axi_rdata[29]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4540"
- )
- port map (
- I0 => axi_araddr(9),
- I1 => \axi_rdata[29]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata[29]_i_3_n_0\,
- O => \axi_rdata[29]_i_1_n_0\
- );
-\axi_rdata[29]_i_11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][29]\,
- I1 => \data_rw_o_reg_n_0_[94][29]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[93][29]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[92][29]\,
- O => \axi_rdata[29]_i_11_n_0\
- );
-\axi_rdata[29]_i_12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][29]\,
- I1 => \data_rw_o_reg_n_0_[90][29]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[89][29]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[88][29]\,
- O => \axi_rdata[29]_i_12_n_0\
- );
-\axi_rdata[29]_i_13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][29]\,
- I1 => \data_rw_o_reg_n_0_[86][29]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[85][29]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[84][29]\,
- O => \axi_rdata[29]_i_13_n_0\
- );
-\axi_rdata[29]_i_14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][29]\,
- I1 => \data_rw_o_reg_n_0_[34][29]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[33][29]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[32][29]\,
- O => \axi_rdata[29]_i_14_n_0\
- );
-\axi_rdata[29]_i_17\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0000B800"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][29]\,
- I1 => \^axi_rdata_reg[23]_0\(0),
- I2 => \data_rw_o_reg_n_0_[10][29]\,
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[29]_i_17_n_0\
- );
-\axi_rdata[29]_i_18\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][29]\,
- I1 => \data_rw_o_reg_n_0_[98][29]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[97][29]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[96][29]\,
- O => \axi_rdata[29]_i_18_n_0\
- );
-\axi_rdata[29]_i_19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][29]\,
- I1 => \data_rw_o_reg_n_0_[102][29]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[101][29]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[100][29]\,
- O => \axi_rdata[29]_i_19_n_0\
- );
-\axi_rdata[29]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[29]_i_4_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata[29]_i_5_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[29]_i_6_n_0\,
- O => \axi_rdata[29]_i_2_n_0\
- );
-\axi_rdata[29]_i_20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][29]\,
- I1 => \data_rw_o_reg_n_0_[18][29]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[17][29]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[16][29]\,
- O => \axi_rdata[29]_i_20_n_0\
- );
-\axi_rdata[29]_i_21\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][29]\,
- I1 => \data_rw_o_reg_n_0_[22][29]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[21][29]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[20][29]\,
- O => \axi_rdata[29]_i_21_n_0\
- );
-\axi_rdata[29]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][29]\,
- I1 => \data_rw_o_reg_n_0_[26][29]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[25][29]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[24][29]\,
- O => \axi_rdata[29]_i_22_n_0\
- );
-\axi_rdata[29]_i_23\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][29]\,
- I1 => \data_rw_o_reg_n_0_[30][29]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[29][29]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[28][29]\,
- O => \axi_rdata[29]_i_23_n_0\
- );
-\axi_rdata[29]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[29]_i_7_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata_reg[29]_i_8_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[29]_i_9_n_0\,
- O => \axi_rdata[29]_i_3_n_0\
- );
-\axi_rdata[29]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0004FFFF00040000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(1),
- I1 => \dac_ch_o_reg[0][31]\(29),
- I2 => \^axi_rdata_reg[23]_0\(0),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[29]_i_10_n_0\,
- O => \axi_rdata[29]_i_4_n_0\
- );
-\axi_rdata[29]_i_5\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AFC0A0C0"
- )
- port map (
- I0 => \axi_rdata[29]_i_11_n_0\,
- I1 => \axi_rdata[29]_i_12_n_0\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \axi_rdata[29]_i_13_n_0\,
- O => \axi_rdata[29]_i_5_n_0\
- );
-\axi_rdata[29]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8880008000000000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \^axi_rdata_reg[23]_0\(1),
- I2 => \data_rw_o_reg_n_0_[78][29]\,
- I3 => \^axi_rdata_reg[23]_0\(0),
- I4 => \data_rw_o_reg_n_0_[79][29]\,
- I5 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[29]_i_6_n_0\
- );
-\axi_rdata[29]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[29]_i_14_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \dac_ch_o_reg[0][31]_0\(29),
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[29]_i_7_n_0\
- );
-\axi_rdata[29]_i_9\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"BB88B88888888888"
- )
- port map (
- I0 => \axi_rdata[29]_i_17_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(3),
- I2 => \^axi_rdata_reg[23]_0\(2),
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \data_rw_o_reg_n_0_[3][29]\,
- I5 => \^axi_rdata_reg[23]_0\(0),
- O => \axi_rdata[29]_i_9_n_0\
- );
-\axi_rdata[2]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[2]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[2]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_rep_8\,
- O => \axi_rdata[2]_i_1_n_0\
- );
-\axi_rdata[2]_i_14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"EE555000EE005000"
- )
- port map (
- I0 => \^axi_rdata_reg[9]_0\,
- I1 => \data_rw_o_reg_n_0_[3][2]\,
- I2 => gem_status_vector_i(2),
- I3 => \^axi_rdata_reg[2]_0\,
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \s_ins_reg[3]\(2),
- O => \axi_rdata[2]_i_14_n_0\
- );
-\axi_rdata[2]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[2]_i_35_n_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(2),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^axi_rdata_reg[10]_0\,
- O => \axi_rdata[2]_i_17_n_0\
- );
-\axi_rdata[2]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[2]_0\,
- I1 => \dac_ch_o_reg[0][31]\(2),
- I2 => \^axi_rdata_reg[2]_1\,
- I3 => \^axi_rdata_reg[9]_0\,
- O => \axi_rdata[2]_i_23_n_0\
- );
-\axi_rdata[2]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]\(2),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]\(2),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]\(2),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]\(2),
- O => \axi_rdata[2]_i_29_n_0\
- );
-\axi_rdata[2]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]\(2),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]\(2),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]\(2),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]\(2),
- O => \axi_rdata[2]_i_30_n_0\
- );
-\axi_rdata[2]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^q\(2),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]\(2),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]\(2),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(2),
- O => \axi_rdata[2]_i_31_n_0\
- );
-\axi_rdata[2]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(2),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]\(2),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]\(2),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(2),
- O => \axi_rdata[2]_i_32_n_0\
- );
-\axi_rdata[2]_i_33\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^v_dout_reg[7]\(1),
- I1 => \data_rw_o_reg_n_0_[10][2]\,
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \data_o_reg[1][3]\(2),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \s_datao_fmc1[0]\(2),
- O => \axi_rdata[2]_i_33_n_0\
- );
-\axi_rdata[2]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]\(2),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]\(2),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]\(2),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]\(2),
- O => \axi_rdata[2]_i_35_n_0\
- );
-\axi_rdata[2]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(2),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(2),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(2),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(2),
- O => \axi_rdata[2]_i_36_n_0\
- );
-\axi_rdata[2]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(2),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(2),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(2),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(2),
- O => \axi_rdata[2]_i_37_n_0\
- );
-\axi_rdata[2]_i_39\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(2),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(2),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(2),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(2),
- O => \axi_rdata[2]_i_39_n_0\
- );
-\axi_rdata[2]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^v_dout_reg[7]_0\(1),
- I1 => \data_rw_o_reg_n_0_[78][2]\,
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \data_o_reg[1][3]_0\(2),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \s_datao_fmc2[0]\(2),
- O => \axi_rdata[2]_i_41_n_0\
- );
-\axi_rdata[2]_i_44\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(2),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(2),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(2),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(2),
- O => \axi_rdata[2]_i_44_n_0\
- );
-\axi_rdata[2]_i_45\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(2),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(2),
- I2 => \^axi_rdata_reg[2]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(2),
- I4 => \^axi_rdata_reg[2]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(2),
- O => \axi_rdata[2]_i_45_n_0\
- );
-\axi_rdata[2]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[2]_i_11_n_0\,
- I1 => \axi_rdata_reg[2]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[2]_i_13_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata[2]_i_14_n_0\,
- O => \axi_rdata[2]_i_5_n_0\
- );
-\axi_rdata[2]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[10]_0\,
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][2]\,
- I2 => \^axi_rdata_reg[9]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][2]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[2]_i_17_n_0\,
- O => \axi_rdata[2]_i_6_n_0\
- );
-\axi_rdata[2]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[2]_i_18_n_0\,
- I1 => \axi_rdata_reg[2]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[2]_i_20_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_araddr_reg[4]_rep__0_1\,
- O => \axi_rdata[2]_i_7_n_0\
- );
-\axi_rdata[2]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][2]_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[2]_i_23_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata_reg[2]_i_24_n_0\,
- O => \axi_rdata[2]_i_8_n_0\
- );
-\axi_rdata[30]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4540"
- )
- port map (
- I0 => axi_araddr(9),
- I1 => \axi_rdata[30]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata[30]_i_3_n_0\,
- O => \axi_rdata[30]_i_1_n_0\
- );
-\axi_rdata[30]_i_11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][30]\,
- I1 => \data_rw_o_reg_n_0_[94][30]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[93][30]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[92][30]\,
- O => \axi_rdata[30]_i_11_n_0\
- );
-\axi_rdata[30]_i_12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][30]\,
- I1 => \data_rw_o_reg_n_0_[90][30]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[89][30]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[88][30]\,
- O => \axi_rdata[30]_i_12_n_0\
- );
-\axi_rdata[30]_i_13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][30]\,
- I1 => \data_rw_o_reg_n_0_[86][30]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[85][30]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[84][30]\,
- O => \axi_rdata[30]_i_13_n_0\
- );
-\axi_rdata[30]_i_14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][30]\,
- I1 => \data_rw_o_reg_n_0_[34][30]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[33][30]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[32][30]\,
- O => \axi_rdata[30]_i_14_n_0\
- );
-\axi_rdata[30]_i_17\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0000B800"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][30]\,
- I1 => \^axi_rdata_reg[23]_0\(0),
- I2 => \data_rw_o_reg_n_0_[10][30]\,
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[30]_i_17_n_0\
- );
-\axi_rdata[30]_i_18\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][30]\,
- I1 => \data_rw_o_reg_n_0_[98][30]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[97][30]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[96][30]\,
- O => \axi_rdata[30]_i_18_n_0\
- );
-\axi_rdata[30]_i_19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][30]\,
- I1 => \data_rw_o_reg_n_0_[102][30]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[101][30]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[100][30]\,
- O => \axi_rdata[30]_i_19_n_0\
- );
-\axi_rdata[30]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[30]_i_4_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata[30]_i_5_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[30]_i_6_n_0\,
- O => \axi_rdata[30]_i_2_n_0\
- );
-\axi_rdata[30]_i_20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][30]\,
- I1 => \data_rw_o_reg_n_0_[18][30]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[17][30]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[16][30]\,
- O => \axi_rdata[30]_i_20_n_0\
- );
-\axi_rdata[30]_i_21\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][30]\,
- I1 => \data_rw_o_reg_n_0_[22][30]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[21][30]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[20][30]\,
- O => \axi_rdata[30]_i_21_n_0\
- );
-\axi_rdata[30]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][30]\,
- I1 => \data_rw_o_reg_n_0_[26][30]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[25][30]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[24][30]\,
- O => \axi_rdata[30]_i_22_n_0\
- );
-\axi_rdata[30]_i_23\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][30]\,
- I1 => \data_rw_o_reg_n_0_[30][30]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[29][30]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[28][30]\,
- O => \axi_rdata[30]_i_23_n_0\
- );
-\axi_rdata[30]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[30]_i_7_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata_reg[30]_i_8_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[30]_i_9_n_0\,
- O => \axi_rdata[30]_i_3_n_0\
- );
-\axi_rdata[30]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0004FFFF00040000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(1),
- I1 => \dac_ch_o_reg[0][31]\(30),
- I2 => \^axi_rdata_reg[23]_0\(0),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[30]_i_10_n_0\,
- O => \axi_rdata[30]_i_4_n_0\
- );
-\axi_rdata[30]_i_5\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AFC0A0C0"
- )
- port map (
- I0 => \axi_rdata[30]_i_11_n_0\,
- I1 => \axi_rdata[30]_i_12_n_0\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \axi_rdata[30]_i_13_n_0\,
- O => \axi_rdata[30]_i_5_n_0\
- );
-\axi_rdata[30]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8880008000000000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \^axi_rdata_reg[23]_0\(1),
- I2 => \data_rw_o_reg_n_0_[78][30]\,
- I3 => \^axi_rdata_reg[23]_0\(0),
- I4 => \data_rw_o_reg_n_0_[79][30]\,
- I5 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[30]_i_6_n_0\
- );
-\axi_rdata[30]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[30]_i_14_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \dac_ch_o_reg[0][31]_0\(30),
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[30]_i_7_n_0\
- );
-\axi_rdata[30]_i_9\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"BB88B888B888B888"
- )
- port map (
- I0 => \axi_rdata[30]_i_17_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(3),
- I2 => \^axi_rdata_reg[23]_0\(2),
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \data_rw_o_reg_n_0_[3][30]\,
- I5 => \^axi_rdata_reg[23]_0\(0),
- O => \axi_rdata[30]_i_9_n_0\
- );
-\axi_rdata[31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"08"
- )
- port map (
- I0 => \^s00_axi_arready\,
- I1 => s00_axi_arvalid,
- I2 => \^s00_axi_rvalid\,
- O => \axi_rdata[31]_i_1_n_0\
- );
-\axi_rdata[31]_i_10\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"BB88B88888888888"
- )
- port map (
- I0 => \axi_rdata[31]_i_18_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(3),
- I2 => \^axi_rdata_reg[23]_0\(2),
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \data_rw_o_reg_n_0_[3][31]\,
- I5 => \^axi_rdata_reg[23]_0\(0),
- O => \axi_rdata[31]_i_10_n_0\
- );
-\axi_rdata[31]_i_12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[95][31]\,
- I1 => \data_rw_o_reg_n_0_[94][31]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[93][31]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[92][31]\,
- O => \axi_rdata[31]_i_12_n_0\
- );
-\axi_rdata[31]_i_13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[91][31]\,
- I1 => \data_rw_o_reg_n_0_[90][31]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[89][31]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[88][31]\,
- O => \axi_rdata[31]_i_13_n_0\
- );
-\axi_rdata[31]_i_14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[87][31]\,
- I1 => \data_rw_o_reg_n_0_[86][31]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[85][31]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[84][31]\,
- O => \axi_rdata[31]_i_14_n_0\
- );
-\axi_rdata[31]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[35][31]\,
- I1 => \data_rw_o_reg_n_0_[34][31]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[33][31]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[32][31]\,
- O => \axi_rdata[31]_i_15_n_0\
- );
-\axi_rdata[31]_i_18\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0000B800"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][31]\,
- I1 => \^axi_rdata_reg[23]_0\(0),
- I2 => \data_rw_o_reg_n_0_[10][31]\,
- I3 => \^axi_rdata_reg[23]_0\(1),
- I4 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[31]_i_18_n_0\
- );
-\axi_rdata[31]_i_19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[99][31]\,
- I1 => \data_rw_o_reg_n_0_[98][31]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[97][31]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[96][31]\,
- O => \axi_rdata[31]_i_19_n_0\
- );
-\axi_rdata[31]_i_2\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4540"
- )
- port map (
- I0 => axi_araddr(9),
- I1 => \axi_rdata[31]_i_3_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata[31]_i_4_n_0\,
- O => \axi_rdata[31]_i_2_n_0\
- );
-\axi_rdata[31]_i_20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[103][31]\,
- I1 => \data_rw_o_reg_n_0_[102][31]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[101][31]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[100][31]\,
- O => \axi_rdata[31]_i_20_n_0\
- );
-\axi_rdata[31]_i_21\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[19][31]\,
- I1 => \data_rw_o_reg_n_0_[18][31]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[17][31]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[16][31]\,
- O => \axi_rdata[31]_i_21_n_0\
- );
-\axi_rdata[31]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[23][31]\,
- I1 => \data_rw_o_reg_n_0_[22][31]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[21][31]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[20][31]\,
- O => \axi_rdata[31]_i_22_n_0\
- );
-\axi_rdata[31]_i_23\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[27][31]\,
- I1 => \data_rw_o_reg_n_0_[26][31]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[25][31]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[24][31]\,
- O => \axi_rdata[31]_i_23_n_0\
- );
-\axi_rdata[31]_i_24\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[31][31]\,
- I1 => \data_rw_o_reg_n_0_[30][31]\,
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \data_rw_o_reg_n_0_[29][31]\,
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \data_rw_o_reg_n_0_[28][31]\,
- O => \axi_rdata[31]_i_24_n_0\
- );
-\axi_rdata[31]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[31]_i_5_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata[31]_i_6_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[31]_i_7_n_0\,
- O => \axi_rdata[31]_i_3_n_0\
- );
-\axi_rdata[31]_i_4\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \axi_rdata[31]_i_8_n_0\,
- I1 => axi_araddr(7),
- I2 => \axi_rdata_reg[31]_i_9_n_0\,
- I3 => axi_araddr(6),
- I4 => \axi_rdata[31]_i_10_n_0\,
- O => \axi_rdata[31]_i_4_n_0\
- );
-\axi_rdata[31]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0004FFFF00040000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(1),
- I1 => \dac_ch_o_reg[0][31]\(31),
- I2 => \^axi_rdata_reg[23]_0\(0),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \^axi_rdata_reg[23]_0\(3),
- I5 => \axi_rdata_reg[31]_i_11_n_0\,
- O => \axi_rdata[31]_i_5_n_0\
- );
-\axi_rdata[31]_i_6\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"AFC0A0C0"
- )
- port map (
- I0 => \axi_rdata[31]_i_12_n_0\,
- I1 => \axi_rdata[31]_i_13_n_0\,
- I2 => \^axi_rdata_reg[23]_0\(3),
- I3 => \^axi_rdata_reg[23]_0\(2),
- I4 => \axi_rdata[31]_i_14_n_0\,
- O => \axi_rdata[31]_i_6_n_0\
- );
-\axi_rdata[31]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8880008000000000"
- )
- port map (
- I0 => \^axi_rdata_reg[23]_0\(3),
- I1 => \^axi_rdata_reg[23]_0\(1),
- I2 => \data_rw_o_reg_n_0_[78][31]\,
- I3 => \^axi_rdata_reg[23]_0\(0),
- I4 => \data_rw_o_reg_n_0_[79][31]\,
- I5 => \^axi_rdata_reg[23]_0\(2),
- O => \axi_rdata[31]_i_7_n_0\
- );
-\axi_rdata[31]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[31]_i_15_n_0\,
- I1 => \^axi_rdata_reg[23]_0\(2),
- I2 => \^axi_rdata_reg[23]_0\(1),
- I3 => \dac_ch_o_reg[0][31]_0\(31),
- I4 => \^axi_rdata_reg[23]_0\(0),
- I5 => \^axi_rdata_reg[23]_0\(3),
- O => \axi_rdata[31]_i_8_n_0\
- );
-\axi_rdata[3]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[3]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[3]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_rep_7\,
- O => \axi_rdata[3]_i_1_n_0\
- );
-\axi_rdata[3]_i_14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"00000000F8C83808"
- )
- port map (
- I0 => \s_ins_reg[3]\(3),
- I1 => \^axi_rdata_reg[7]_1\,
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => gem_status_vector_i(3),
- I4 => \data_rw_o_reg_n_0_[3][3]\,
- I5 => \^axi_rdata_reg[9]_0\,
- O => \axi_rdata[3]_i_14_n_0\
- );
-\axi_rdata[3]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[3]_i_35_n_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(3),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^axi_rdata_reg[10]_0\,
- O => \axi_rdata[3]_i_17_n_0\
- );
-\axi_rdata[3]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[7]_0\,
- I1 => \dac_ch_o_reg[0][31]\(3),
- I2 => \^axi_rdata_reg[7]_1\,
- I3 => \^axi_rdata_reg[9]_0\,
- O => \axi_rdata[3]_i_23_n_0\
- );
-\axi_rdata[3]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]\(3),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]\(3),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]\(3),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]\(3),
- O => \axi_rdata[3]_i_29_n_0\
- );
-\axi_rdata[3]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]\(3),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]\(3),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]\(3),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]\(3),
- O => \axi_rdata[3]_i_30_n_0\
- );
-\axi_rdata[3]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^q\(3),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]\(3),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]\(3),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(3),
- O => \axi_rdata[3]_i_31_n_0\
- );
-\axi_rdata[3]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(3),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]\(3),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]\(3),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(3),
- O => \axi_rdata[3]_i_32_n_0\
- );
-\axi_rdata[3]_i_33\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][3]\,
- I1 => \data_rw_o_reg_n_0_[10][3]\,
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \data_o_reg[1][3]\(3),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \s_datao_fmc1[0]\(3),
- O => \axi_rdata[3]_i_33_n_0\
- );
-\axi_rdata[3]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]\(3),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]\(3),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]\(3),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]\(3),
- O => \axi_rdata[3]_i_35_n_0\
- );
-\axi_rdata[3]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(3),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(3),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(3),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(3),
- O => \axi_rdata[3]_i_36_n_0\
- );
-\axi_rdata[3]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(3),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(3),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(3),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(3),
- O => \axi_rdata[3]_i_37_n_0\
- );
-\axi_rdata[3]_i_39\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(3),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(3),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(3),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(3),
- O => \axi_rdata[3]_i_39_n_0\
- );
-\axi_rdata[3]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][3]\,
- I1 => \data_rw_o_reg_n_0_[78][3]\,
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \data_o_reg[1][3]_0\(3),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \s_datao_fmc2[0]\(3),
- O => \axi_rdata[3]_i_41_n_0\
- );
-\axi_rdata[3]_i_44\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(3),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(3),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(3),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(3),
- O => \axi_rdata[3]_i_44_n_0\
- );
-\axi_rdata[3]_i_45\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(3),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(3),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(3),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(3),
- O => \axi_rdata[3]_i_45_n_0\
- );
-\axi_rdata[3]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[3]_i_11_n_0\,
- I1 => \axi_rdata_reg[3]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[3]_i_13_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata[3]_i_14_n_0\,
- O => \axi_rdata[3]_i_5_n_0\
- );
-\axi_rdata[3]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[10]_0\,
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][3]\,
- I2 => \^axi_rdata_reg[9]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][3]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[3]_i_17_n_0\,
- O => \axi_rdata[3]_i_6_n_0\
- );
-\axi_rdata[3]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[3]_i_18_n_0\,
- I1 => \axi_rdata_reg[3]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[3]_i_20_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_araddr_reg[4]_rep__0_2\,
- O => \axi_rdata[3]_i_7_n_0\
- );
-\axi_rdata[3]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][3]_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[3]_i_23_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata_reg[3]_i_24_n_0\,
- O => \axi_rdata[3]_i_8_n_0\
- );
-\axi_rdata[4]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[4]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[4]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_rep_6\,
- O => \axi_rdata[4]_i_1_n_0\
- );
-\axi_rdata[4]_i_14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"CC408840"
- )
- port map (
- I0 => \^axi_rdata_reg[9]_0\,
- I1 => \^axi_rdata_reg[7]_0\,
- I2 => gem_status_vector_i(4),
- I3 => \^axi_rdata_reg[7]_1\,
- I4 => \data_rw_o_reg_n_0_[3][4]\,
- O => \axi_rdata[4]_i_14_n_0\
- );
-\axi_rdata[4]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[4]_i_35_n_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(4),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^axi_rdata_reg[10]_0\,
- O => \axi_rdata[4]_i_17_n_0\
- );
-\axi_rdata[4]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[7]_0\,
- I1 => \dac_ch_o_reg[0][31]\(4),
- I2 => \^axi_rdata_reg[7]_1\,
- I3 => \^axi_rdata_reg[9]_0\,
- O => \axi_rdata[4]_i_23_n_0\
- );
-\axi_rdata[4]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]\(4),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]\(4),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]\(4),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]\(4),
- O => \axi_rdata[4]_i_29_n_0\
- );
-\axi_rdata[4]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]\(4),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]\(4),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]\(4),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]\(4),
- O => \axi_rdata[4]_i_30_n_0\
- );
-\axi_rdata[4]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^q\(4),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]\(4),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]\(4),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(4),
- O => \axi_rdata[4]_i_31_n_0\
- );
-\axi_rdata[4]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(4),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]\(4),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]\(4),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(4),
- O => \axi_rdata[4]_i_32_n_0\
- );
-\axi_rdata[4]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][4]\,
- I1 => \data_rw_o[10]\(4),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \s_datao_fmc1[0]\(4),
- I4 => \^axi_rdata_reg[7]_1\,
- O => \axi_rdata[4]_i_33_n_0\
- );
-\axi_rdata[4]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]\(4),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]\(4),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]\(4),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]\(4),
- O => \axi_rdata[4]_i_35_n_0\
- );
-\axi_rdata[4]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(4),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(4),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(4),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(4),
- O => \axi_rdata[4]_i_36_n_0\
- );
-\axi_rdata[4]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(4),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(4),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(4),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(4),
- O => \axi_rdata[4]_i_37_n_0\
- );
-\axi_rdata[4]_i_39\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(4),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(4),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(4),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(4),
- O => \axi_rdata[4]_i_39_n_0\
- );
-\axi_rdata[4]_i_41\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][4]\,
- I1 => \data_rw_o[78]\(4),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \s_datao_fmc2[0]\(4),
- I4 => \^axi_rdata_reg[7]_1\,
- O => \axi_rdata[4]_i_41_n_0\
- );
-\axi_rdata[4]_i_44\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(4),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(4),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(4),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(4),
- O => \axi_rdata[4]_i_44_n_0\
- );
-\axi_rdata[4]_i_45\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(4),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(4),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(4),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(4),
- O => \axi_rdata[4]_i_45_n_0\
- );
-\axi_rdata[4]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[4]_i_11_n_0\,
- I1 => \axi_rdata_reg[4]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[4]_i_13_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata[4]_i_14_n_0\,
- O => \axi_rdata[4]_i_5_n_0\
- );
-\axi_rdata[4]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[10]_0\,
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][4]\,
- I2 => \^axi_rdata_reg[9]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][4]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[4]_i_17_n_0\,
- O => \axi_rdata[4]_i_6_n_0\
- );
-\axi_rdata[4]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[4]_i_18_n_0\,
- I1 => \axi_rdata_reg[4]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[4]_i_20_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_araddr_reg[4]_rep__0_3\,
- O => \axi_rdata[4]_i_7_n_0\
- );
-\axi_rdata[4]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][4]_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[4]_i_23_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata_reg[4]_i_24_n_0\,
- O => \axi_rdata[4]_i_8_n_0\
- );
-\axi_rdata[5]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[5]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[5]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_rep_5\,
- O => \axi_rdata[5]_i_1_n_0\
- );
-\axi_rdata[5]_i_14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0000B800"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[3][5]\,
- I1 => \^axi_rdata_reg[7]_1\,
- I2 => gem_status_vector_i(5),
- I3 => \^axi_rdata_reg[7]_0\,
- I4 => \^axi_rdata_reg[9]_0\,
- O => \axi_rdata[5]_i_14_n_0\
- );
-\axi_rdata[5]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[5]_i_35_n_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(5),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^axi_rdata_reg[10]_0\,
- O => \axi_rdata[5]_i_17_n_0\
- );
-\axi_rdata[5]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[7]_0\,
- I1 => \dac_ch_o_reg[0][31]\(5),
- I2 => \^axi_rdata_reg[7]_1\,
- I3 => \^axi_rdata_reg[9]_0\,
- O => \axi_rdata[5]_i_23_n_0\
- );
-\axi_rdata[5]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]\(5),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]\(5),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]\(5),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]\(5),
- O => \axi_rdata[5]_i_29_n_0\
- );
-\axi_rdata[5]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]\(5),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]\(5),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]\(5),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]\(5),
- O => \axi_rdata[5]_i_30_n_0\
- );
-\axi_rdata[5]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^q\(5),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]\(5),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]\(5),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(5),
- O => \axi_rdata[5]_i_31_n_0\
- );
-\axi_rdata[5]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(5),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]\(5),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]\(5),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(5),
- O => \axi_rdata[5]_i_32_n_0\
- );
-\axi_rdata[5]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][5]\,
- I1 => \data_rw_o[10]\(5),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \s_datao_fmc1[0]\(5),
- I4 => \^axi_rdata_reg[7]_1\,
- O => \axi_rdata[5]_i_33_n_0\
- );
-\axi_rdata[5]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]\(5),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]\(5),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]\(5),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]\(5),
- O => \axi_rdata[5]_i_35_n_0\
- );
-\axi_rdata[5]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(5),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(5),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(5),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(5),
- O => \axi_rdata[5]_i_36_n_0\
- );
-\axi_rdata[5]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(5),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(5),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(5),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(5),
- O => \axi_rdata[5]_i_37_n_0\
- );
-\axi_rdata[5]_i_39\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(5),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(5),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(5),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(5),
- O => \axi_rdata[5]_i_39_n_0\
- );
-\axi_rdata[5]_i_41\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][5]\,
- I1 => \data_rw_o[78]\(5),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \s_datao_fmc2[0]\(5),
- I4 => \^axi_rdata_reg[7]_1\,
- O => \axi_rdata[5]_i_41_n_0\
- );
-\axi_rdata[5]_i_44\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(5),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(5),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(5),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(5),
- O => \axi_rdata[5]_i_44_n_0\
- );
-\axi_rdata[5]_i_45\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(5),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(5),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(5),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(5),
- O => \axi_rdata[5]_i_45_n_0\
- );
-\axi_rdata[5]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[5]_i_11_n_0\,
- I1 => \axi_rdata_reg[5]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[5]_i_13_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata[5]_i_14_n_0\,
- O => \axi_rdata[5]_i_5_n_0\
- );
-\axi_rdata[5]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[10]_0\,
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][5]\,
- I2 => \^axi_rdata_reg[9]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][5]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[5]_i_17_n_0\,
- O => \axi_rdata[5]_i_6_n_0\
- );
-\axi_rdata[5]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[5]_i_18_n_0\,
- I1 => \axi_rdata_reg[5]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[5]_i_20_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_araddr_reg[4]_rep__0_4\,
- O => \axi_rdata[5]_i_7_n_0\
- );
-\axi_rdata[5]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][5]_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[5]_i_23_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata_reg[5]_i_24_n_0\,
- O => \axi_rdata[5]_i_8_n_0\
- );
-\axi_rdata[6]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[6]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[6]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_rep_4\,
- O => \axi_rdata[6]_i_1_n_0\
- );
-\axi_rdata[6]_i_14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"44C800C8"
- )
- port map (
- I0 => \^axi_rdata_reg[9]_0\,
- I1 => \^axi_rdata_reg[7]_0\,
- I2 => gem_status_vector_i(6),
- I3 => \^axi_rdata_reg[7]_1\,
- I4 => \data_rw_o_reg_n_0_[3][6]\,
- O => \axi_rdata[6]_i_14_n_0\
- );
-\axi_rdata[6]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[6]_i_35_n_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(6),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^axi_rdata_reg[10]_0\,
- O => \axi_rdata[6]_i_17_n_0\
- );
-\axi_rdata[6]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[7]_0\,
- I1 => \dac_ch_o_reg[0][31]\(6),
- I2 => \^axi_rdata_reg[7]_1\,
- I3 => \^axi_rdata_reg[9]_0\,
- O => \axi_rdata[6]_i_23_n_0\
- );
-\axi_rdata[6]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]\(6),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]\(6),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]\(6),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]\(6),
- O => \axi_rdata[6]_i_29_n_0\
- );
-\axi_rdata[6]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]\(6),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]\(6),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]\(6),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]\(6),
- O => \axi_rdata[6]_i_30_n_0\
- );
-\axi_rdata[6]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^q\(6),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]\(6),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]\(6),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(6),
- O => \axi_rdata[6]_i_31_n_0\
- );
-\axi_rdata[6]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(6),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]\(6),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]\(6),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(6),
- O => \axi_rdata[6]_i_32_n_0\
- );
-\axi_rdata[6]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][6]\,
- I1 => \data_rw_o[10]\(6),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \s_datao_fmc1[0]\(6),
- I4 => \^axi_rdata_reg[7]_1\,
- O => \axi_rdata[6]_i_33_n_0\
- );
-\axi_rdata[6]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]\(6),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]\(6),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]\(6),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]\(6),
- O => \axi_rdata[6]_i_35_n_0\
- );
-\axi_rdata[6]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(6),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(6),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(6),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(6),
- O => \axi_rdata[6]_i_36_n_0\
- );
-\axi_rdata[6]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(6),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(6),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(6),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(6),
- O => \axi_rdata[6]_i_37_n_0\
- );
-\axi_rdata[6]_i_39\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(6),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(6),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(6),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(6),
- O => \axi_rdata[6]_i_39_n_0\
- );
-\axi_rdata[6]_i_41\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][6]\,
- I1 => \data_rw_o[78]\(6),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \s_datao_fmc2[0]\(6),
- I4 => \^axi_rdata_reg[7]_1\,
- O => \axi_rdata[6]_i_41_n_0\
- );
-\axi_rdata[6]_i_44\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(6),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(6),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(6),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(6),
- O => \axi_rdata[6]_i_44_n_0\
- );
-\axi_rdata[6]_i_45\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(6),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(6),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(6),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(6),
- O => \axi_rdata[6]_i_45_n_0\
- );
-\axi_rdata[6]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[6]_i_11_n_0\,
- I1 => \axi_rdata_reg[6]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[6]_i_13_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata[6]_i_14_n_0\,
- O => \axi_rdata[6]_i_5_n_0\
- );
-\axi_rdata[6]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[10]_0\,
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][6]\,
- I2 => \^axi_rdata_reg[9]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][6]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[6]_i_17_n_0\,
- O => \axi_rdata[6]_i_6_n_0\
- );
-\axi_rdata[6]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[6]_i_18_n_0\,
- I1 => \axi_rdata_reg[6]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[6]_i_20_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_araddr_reg[4]_rep__0_5\,
- O => \axi_rdata[6]_i_7_n_0\
- );
-\axi_rdata[6]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][6]_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[6]_i_23_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata_reg[6]_i_24_n_0\,
- O => \axi_rdata[6]_i_8_n_0\
- );
-\axi_rdata[7]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[7]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[7]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_rep_3\,
- O => \axi_rdata[7]_i_1_n_0\
- );
-\axi_rdata[7]_i_14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"CC408840"
- )
- port map (
- I0 => \^axi_rdata_reg[9]_0\,
- I1 => \^axi_rdata_reg[7]_0\,
- I2 => gem_status_vector_i(7),
- I3 => \^axi_rdata_reg[7]_1\,
- I4 => \data_rw_o_reg_n_0_[3][7]\,
- O => \axi_rdata[7]_i_14_n_0\
- );
-\axi_rdata[7]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[7]_i_35_n_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \dac_ch_o_reg[0][31]_0\(7),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^axi_rdata_reg[10]_0\,
- O => \axi_rdata[7]_i_17_n_0\
- );
-\axi_rdata[7]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[7]_0\,
- I1 => \dac_ch_o_reg[0][31]\(7),
- I2 => \^axi_rdata_reg[7]_1\,
- I3 => \^axi_rdata_reg[9]_0\,
- O => \axi_rdata[7]_i_23_n_0\
- );
-\axi_rdata[7]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]\(7),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]\(7),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]\(7),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]\(7),
- O => \axi_rdata[7]_i_29_n_0\
- );
-\axi_rdata[7]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]\(7),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]\(7),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]\(7),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]\(7),
- O => \axi_rdata[7]_i_30_n_0\
- );
-\axi_rdata[7]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^q\(7),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]\(7),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]\(7),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(7),
- O => \axi_rdata[7]_i_31_n_0\
- );
-\axi_rdata[7]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(7),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]\(7),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]\(7),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(7),
- O => \axi_rdata[7]_i_32_n_0\
- );
-\axi_rdata[7]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \^v_dout_reg[7]\(2),
- I1 => \data_rw_o[10]\(7),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \s_datao_fmc1[0]\(7),
- I4 => \^axi_rdata_reg[7]_1\,
- O => \axi_rdata[7]_i_33_n_0\
- );
-\axi_rdata[7]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]\(7),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]\(7),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]\(7),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]\(7),
- O => \axi_rdata[7]_i_35_n_0\
- );
-\axi_rdata[7]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(7),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(7),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(7),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(7),
- O => \axi_rdata[7]_i_36_n_0\
- );
-\axi_rdata[7]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(7),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(7),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(7),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(7),
- O => \axi_rdata[7]_i_37_n_0\
- );
-\axi_rdata[7]_i_39\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(7),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(7),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(7),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(7),
- O => \axi_rdata[7]_i_39_n_0\
- );
-\axi_rdata[7]_i_41\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \^v_dout_reg[7]_0\(2),
- I1 => \data_rw_o[78]\(7),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \s_datao_fmc2[0]\(7),
- I4 => \^axi_rdata_reg[7]_1\,
- O => \axi_rdata[7]_i_41_n_0\
- );
-\axi_rdata[7]_i_44\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(7),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(7),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(7),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(7),
- O => \axi_rdata[7]_i_44_n_0\
- );
-\axi_rdata[7]_i_45\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(7),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(7),
- I2 => \^axi_rdata_reg[7]_0\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(7),
- I4 => \^axi_rdata_reg[7]_1\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(7),
- O => \axi_rdata[7]_i_45_n_0\
- );
-\axi_rdata[7]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[7]_i_11_n_0\,
- I1 => \axi_rdata_reg[7]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[7]_i_13_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata[7]_i_14_n_0\,
- O => \axi_rdata[7]_i_5_n_0\
- );
-\axi_rdata[7]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[10]_0\,
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][7]\,
- I2 => \^axi_rdata_reg[9]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][7]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[7]_i_17_n_0\,
- O => \axi_rdata[7]_i_6_n_0\
- );
-\axi_rdata[7]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[7]_i_18_n_0\,
- I1 => \axi_rdata_reg[7]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[7]_i_20_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_araddr_reg[4]_rep__0_6\,
- O => \axi_rdata[7]_i_7_n_0\
- );
-\axi_rdata[7]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][7]_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[7]_i_23_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata_reg[7]_i_24_n_0\,
- O => \axi_rdata[7]_i_8_n_0\
- );
-\axi_rdata[8]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[8]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[8]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_rep_2\,
- O => \axi_rdata[8]_i_1_n_0\
- );
-\axi_rdata[8]_i_13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"04FF0400"
- )
- port map (
- I0 => \^axi_rdata_reg[12]_0\,
- I1 => \s_datao_fmc1[4]\(0),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^axi_rdata_reg[9]_0\,
- I4 => \axi_rdata[8]_i_33_n_0\,
- O => \axi_rdata[8]_i_13_n_0\
- );
-\axi_rdata[8]_i_14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"0000B800"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[3][8]\,
- I1 => \^axi_rdata_reg[12]_0\,
- I2 => gem_status_vector_i(8),
- I3 => \^axi_rdata_reg[12]_1\,
- I4 => \^axi_rdata_reg[9]_0\,
- O => \axi_rdata[8]_i_14_n_0\
- );
-\axi_rdata[8]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[8]_i_34_n_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \dac_ch_o_reg[0][31]_0\(8),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^axi_rdata_reg[10]_0\,
- O => \axi_rdata[8]_i_17_n_0\
- );
-\axi_rdata[8]_i_19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88888B88"
- )
- port map (
- I0 => \axi_rdata[8]_i_37_n_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[12]_0\,
- I3 => \s_datao_fmc2[4]\(0),
- I4 => \^axi_rdata_reg[12]_1\,
- O => \axi_rdata[8]_i_19_n_0\
- );
-\axi_rdata[8]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[12]_1\,
- I1 => \dac_ch_o_reg[0][31]\(8),
- I2 => \^axi_rdata_reg[12]_0\,
- I3 => \^axi_rdata_reg[9]_0\,
- O => \axi_rdata[8]_i_23_n_0\
- );
-\axi_rdata[8]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]\(8),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]\(8),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]\(8),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]\(8),
- O => \axi_rdata[8]_i_29_n_0\
- );
-\axi_rdata[8]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]\(8),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]\(8),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]\(8),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]\(8),
- O => \axi_rdata[8]_i_30_n_0\
- );
-\axi_rdata[8]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^q\(8),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]\(8),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]\(8),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(8),
- O => \axi_rdata[8]_i_31_n_0\
- );
-\axi_rdata[8]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(8),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]\(8),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]\(8),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(8),
- O => \axi_rdata[8]_i_32_n_0\
- );
-\axi_rdata[8]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][8]\,
- I1 => \data_rw_o_reg_n_0_[10][8]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \s_datao_fmc1[0]\(8),
- I4 => \^axi_rdata_reg[12]_0\,
- O => \axi_rdata[8]_i_33_n_0\
- );
-\axi_rdata[8]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]\(8),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]\(8),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]\(8),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]\(8),
- O => \axi_rdata[8]_i_34_n_0\
- );
-\axi_rdata[8]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(8),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(8),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(8),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(8),
- O => \axi_rdata[8]_i_35_n_0\
- );
-\axi_rdata[8]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(8),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(8),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(8),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(8),
- O => \axi_rdata[8]_i_36_n_0\
- );
-\axi_rdata[8]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(8),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(8),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(8),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(8),
- O => \axi_rdata[8]_i_37_n_0\
- );
-\axi_rdata[8]_i_39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][8]\,
- I1 => \data_rw_o_reg_n_0_[78][8]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \s_datao_fmc2[0]\(8),
- I4 => \^axi_rdata_reg[12]_0\,
- O => \axi_rdata[8]_i_39_n_0\
- );
-\axi_rdata[8]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(8),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(8),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(8),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(8),
- O => \axi_rdata[8]_i_42_n_0\
- );
-\axi_rdata[8]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(8),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(8),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(8),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(8),
- O => \axi_rdata[8]_i_43_n_0\
- );
-\axi_rdata[8]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[8]_i_11_n_0\,
- I1 => \axi_rdata_reg[8]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[8]_i_13_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata[8]_i_14_n_0\,
- O => \axi_rdata[8]_i_5_n_0\
- );
-\axi_rdata[8]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[10]_0\,
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][8]\,
- I2 => \^axi_rdata_reg[9]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][8]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[8]_i_17_n_0\,
- O => \axi_rdata[8]_i_6_n_0\
- );
-\axi_rdata[8]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[8]_i_18_n_0\,
- I1 => \axi_rdata[8]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[8]_i_20_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_araddr_reg[4]_rep__0_7\,
- O => \axi_rdata[8]_i_7_n_0\
- );
-\axi_rdata[8]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][8]_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[8]_i_23_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata_reg[8]_i_24_n_0\,
- O => \axi_rdata[8]_i_8_n_0\
- );
-\axi_rdata[9]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAAA8080000A808"
- )
- port map (
- I0 => \axi_rdata[23]_i_2_n_0\,
- I1 => \axi_rdata_reg[9]_i_2_n_0\,
- I2 => axi_araddr(8),
- I3 => \axi_rdata_reg[9]_i_3_n_0\,
- I4 => axi_araddr(9),
- I5 => \axi_araddr_reg[5]_rep_1\,
- O => \axi_rdata[9]_i_1_n_0\
- );
-\axi_rdata[9]_i_13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"04FF0400"
- )
- port map (
- I0 => \^axi_rdata_reg[12]_0\,
- I1 => \s_datao_fmc1[4]\(1),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^axi_rdata_reg[9]_0\,
- I4 => \axi_rdata[9]_i_33_n_0\,
- O => \axi_rdata[9]_i_13_n_0\
- );
-\axi_rdata[9]_i_14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"CC408840"
- )
- port map (
- I0 => \^axi_rdata_reg[9]_0\,
- I1 => \^axi_rdata_reg[12]_1\,
- I2 => gem_status_vector_i(9),
- I3 => \^axi_rdata_reg[12]_0\,
- I4 => \data_rw_o_reg_n_0_[3][9]\,
- O => \axi_rdata[9]_i_14_n_0\
- );
-\axi_rdata[9]_i_17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000022222E22"
- )
- port map (
- I0 => \axi_rdata[9]_i_34_n_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \dac_ch_o_reg[0][31]_0\(9),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^axi_rdata_reg[10]_0\,
- O => \axi_rdata[9]_i_17_n_0\
- );
-\axi_rdata[9]_i_19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88888B88"
- )
- port map (
- I0 => \axi_rdata[9]_i_37_n_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => \^axi_rdata_reg[12]_0\,
- I3 => \s_datao_fmc2[4]\(1),
- I4 => \^axi_rdata_reg[12]_1\,
- O => \axi_rdata[9]_i_19_n_0\
- );
-\axi_rdata[9]_i_23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0004"
- )
- port map (
- I0 => \^axi_rdata_reg[12]_1\,
- I1 => \dac_ch_o_reg[0][31]\(9),
- I2 => \^axi_rdata_reg[12]_0\,
- I3 => \^axi_rdata_reg[9]_0\,
- O => \axi_rdata[9]_i_23_n_0\
- );
-\axi_rdata[9]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]\(9),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]\(9),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]\(9),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]\(9),
- O => \axi_rdata[9]_i_29_n_0\
- );
-\axi_rdata[9]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]\(9),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]\(9),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]\(9),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]\(9),
- O => \axi_rdata[9]_i_30_n_0\
- );
-\axi_rdata[9]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^q\(9),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]\(9),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]\(9),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]\(9),
- O => \axi_rdata[9]_i_31_n_0\
- );
-\axi_rdata[9]_i_32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]\(9),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]\(9),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]\(9),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]\(9),
- O => \axi_rdata[9]_i_32_n_0\
- );
-\axi_rdata[9]_i_33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[11][9]\,
- I1 => \data_rw_o_reg_n_0_[10][9]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \s_datao_fmc1[0]\(9),
- I4 => \^axi_rdata_reg[12]_0\,
- O => \axi_rdata[9]_i_33_n_0\
- );
-\axi_rdata[9]_i_34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]\(9),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]\(9),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]\(9),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]\(9),
- O => \axi_rdata[9]_i_34_n_0\
- );
-\axi_rdata[9]_i_35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[1].[3].s_reqs_reg[7][value][11]_0\(9),
- I1 => \^[1].[2].s_reqs_reg[6][value][11]_0\(9),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[1].[1].s_reqs_reg[5][value][11]_0\(9),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[1].[0].s_reqs_reg[4][value][11]_0\(9),
- O => \axi_rdata[9]_i_35_n_0\
- );
-\axi_rdata[9]_i_36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[2].[3].s_reqs_reg[11][value][11]_0\(9),
- I1 => \^[2].[2].s_reqs_reg[10][value][11]_0\(9),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[2].[1].s_reqs_reg[9][value][11]_0\(9),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[2].[0].s_reqs_reg[8][value][11]_0\(9),
- O => \axi_rdata[9]_i_36_n_0\
- );
-\axi_rdata[9]_i_37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[0].[3].s_reqs_reg[3][value][11]\(9),
- I1 => \^[0].[2].s_reqs_reg[2][value][11]_0\(9),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[0].[1].s_reqs_reg[1][value][11]_0\(9),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[0].[0].s_reqs_reg[0][value][11]_0\(9),
- O => \axi_rdata[9]_i_37_n_0\
- );
-\axi_rdata[9]_i_39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"A0A0CFC0"
- )
- port map (
- I0 => \data_rw_o_reg_n_0_[79][9]\,
- I1 => \data_rw_o_reg_n_0_[78][9]\,
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \s_datao_fmc2[0]\(9),
- I4 => \^axi_rdata_reg[12]_0\,
- O => \axi_rdata[9]_i_39_n_0\
- );
-\axi_rdata[9]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[3].[3].s_reqs_reg[15][value][11]_0\(9),
- I1 => \^[3].[2].s_reqs_reg[14][value][11]_0\(9),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[3].[1].s_reqs_reg[13][value][11]_0\(9),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[3].[0].s_reqs_reg[12][value][11]_0\(9),
- O => \axi_rdata[9]_i_42_n_0\
- );
-\axi_rdata[9]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \^[4].[3].s_reqs_reg[19][value][11]_0\(9),
- I1 => \^[4].[2].s_reqs_reg[18][value][11]_0\(9),
- I2 => \^axi_rdata_reg[12]_1\,
- I3 => \^[4].[1].s_reqs_reg[17][value][11]_0\(9),
- I4 => \^axi_rdata_reg[12]_0\,
- I5 => \^[4].[0].s_reqs_reg[16][value][11]_0\(9),
- O => \axi_rdata[9]_i_43_n_0\
- );
-\axi_rdata[9]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[9]_i_11_n_0\,
- I1 => \axi_rdata_reg[9]_i_12_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[9]_i_13_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata[9]_i_14_n_0\,
- O => \axi_rdata[9]_i_5_n_0\
- );
-\axi_rdata[9]_i_6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"A808FFFFA8080000"
- )
- port map (
- I0 => \^axi_rdata_reg[10]_0\,
- I1 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][9]\,
- I2 => \^axi_rdata_reg[9]_0\,
- I3 => \fmc_03287_channels[7].gen_chs.data_o_reg[55][9]\,
- I4 => axi_araddr(6),
- I5 => \axi_rdata[9]_i_17_n_0\,
- O => \axi_rdata[9]_i_6_n_0\
- );
-\axi_rdata[9]_i_7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \axi_rdata_reg[9]_i_18_n_0\,
- I1 => \axi_rdata[9]_i_19_n_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata_reg[9]_i_20_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_araddr_reg[4]_rep__0_8\,
- O => \axi_rdata[9]_i_7_n_0\
- );
-\axi_rdata[9]_i_8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8F800F0F8F800000"
- )
- port map (
- I0 => \fmc_03287_channels[3].gen_chs.data_o_reg[51][9]_0\,
- I1 => \^axi_rdata_reg[9]_0\,
- I2 => axi_araddr(6),
- I3 => \axi_rdata[9]_i_23_n_0\,
- I4 => \^axi_rdata_reg[10]_0\,
- I5 => \axi_rdata_reg[9]_i_24_n_0\,
- O => \axi_rdata[9]_i_8_n_0\
- );
-\axi_rdata_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[0]_i_1_n_0\,
- Q => s00_axi_rdata(0),
- R => rst_i
- );
-\axi_rdata_reg[0]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[0]_i_29_n_0\,
- I1 => \axi_rdata[0]_i_30_n_0\,
- O => \axi_rdata_reg[0]_i_11_n_0\,
- S => \^axi_rdata_reg[0]_0\
- );
-\axi_rdata_reg[0]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[0]_i_31_n_0\,
- I1 => \axi_rdata[0]_i_32_n_0\,
- O => \axi_rdata_reg[0]_i_12_n_0\,
- S => \^axi_rdata_reg[0]_0\
- );
-\axi_rdata_reg[0]_i_13\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[0]_i_33_n_0\,
- I1 => \data_o_reg[6][0]\,
- O => \axi_rdata_reg[0]_i_13_n_0\,
- S => \^axi_rdata_reg[0]_0\
- );
-\axi_rdata_reg[0]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[0]_i_36_n_0\,
- I1 => \axi_rdata[0]_i_37_n_0\,
- O => \axi_rdata_reg[0]_i_18_n_0\,
- S => \^axi_rdata_reg[0]_0\
- );
-\axi_rdata_reg[0]_i_19\: unisim.vcomponents.MUXF7
- port map (
- I0 => \data_o_reg[6][0]_0\,
- I1 => \axi_rdata[0]_i_39_n_0\,
- O => \axi_rdata_reg[0]_i_19_n_0\,
- S => \^axi_rdata_reg[0]_0\
- );
-\axi_rdata_reg[0]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[0]_i_5_n_0\,
- I1 => \axi_rdata[0]_i_6_n_0\,
- O => \axi_rdata_reg[0]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[0]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][0]\,
- I1 => \axi_rdata[0]_i_41_n_0\,
- O => \axi_rdata_reg[0]_i_20_n_0\,
- S => \^axi_rdata_reg[0]_0\
- );
-\axi_rdata_reg[0]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[0]_i_44_n_0\,
- I1 => \axi_rdata[0]_i_45_n_0\,
- O => \axi_rdata_reg[0]_i_24_n_0\,
- S => \^axi_rdata_reg[0]_0\
- );
-\axi_rdata_reg[0]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[0]_i_7_n_0\,
- I1 => \axi_rdata[0]_i_8_n_0\,
- O => \axi_rdata_reg[0]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[10]_i_1_n_0\,
- Q => s00_axi_rdata(10),
- R => rst_i
- );
-\axi_rdata_reg[10]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[10]_i_29_n_0\,
- I1 => \axi_rdata[10]_i_30_n_0\,
- O => \axi_rdata_reg[10]_i_11_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[10]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[10]_i_31_n_0\,
- I1 => \axi_rdata[10]_i_32_n_0\,
- O => \axi_rdata_reg[10]_i_12_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[10]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[10]_i_35_n_0\,
- I1 => \axi_rdata[10]_i_36_n_0\,
- O => \axi_rdata_reg[10]_i_18_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[10]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[10]_i_5_n_0\,
- I1 => \axi_rdata[10]_i_6_n_0\,
- O => \axi_rdata_reg[10]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[10]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][10]\,
- I1 => \axi_rdata[10]_i_39_n_0\,
- O => \axi_rdata_reg[10]_i_20_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[10]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[10]_i_42_n_0\,
- I1 => \axi_rdata[10]_i_43_n_0\,
- O => \axi_rdata_reg[10]_i_24_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[10]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[10]_i_7_n_0\,
- I1 => \axi_rdata[10]_i_8_n_0\,
- O => \axi_rdata_reg[10]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[11]_i_1_n_0\,
- Q => s00_axi_rdata(11),
- R => rst_i
- );
-\axi_rdata_reg[11]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[11]_i_29_n_0\,
- I1 => \axi_rdata[11]_i_30_n_0\,
- O => \axi_rdata_reg[11]_i_11_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[11]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[11]_i_31_n_0\,
- I1 => \axi_rdata[11]_i_32_n_0\,
- O => \axi_rdata_reg[11]_i_12_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[11]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[11]_i_35_n_0\,
- I1 => \axi_rdata[11]_i_36_n_0\,
- O => \axi_rdata_reg[11]_i_18_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[11]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[11]_i_5_n_0\,
- I1 => \axi_rdata[11]_i_6_n_0\,
- O => \axi_rdata_reg[11]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[11]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][11]\,
- I1 => \axi_rdata[11]_i_39_n_0\,
- O => \axi_rdata_reg[11]_i_20_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[11]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[11]_i_42_n_0\,
- I1 => \axi_rdata[11]_i_43_n_0\,
- O => \axi_rdata_reg[11]_i_24_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[11]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[11]_i_7_n_0\,
- I1 => \axi_rdata[11]_i_8_n_0\,
- O => \axi_rdata_reg[11]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[12]_i_1_n_0\,
- Q => s00_axi_rdata(12),
- R => rst_i
- );
-\axi_rdata_reg[12]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[12]_i_29_n_0\,
- I1 => \axi_rdata[12]_i_30_n_0\,
- O => \axi_rdata_reg[12]_i_11_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[12]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[12]_i_31_n_0\,
- I1 => \axi_rdata[12]_i_32_n_0\,
- O => \axi_rdata_reg[12]_i_12_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[12]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[12]_i_35_n_0\,
- I1 => \axi_rdata[12]_i_36_n_0\,
- O => \axi_rdata_reg[12]_i_18_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[12]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[12]_i_5_n_0\,
- I1 => \axi_rdata[12]_i_6_n_0\,
- O => \axi_rdata_reg[12]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[12]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][12]\,
- I1 => \axi_rdata[12]_i_39_n_0\,
- O => \axi_rdata_reg[12]_i_20_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[12]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[12]_i_42_n_0\,
- I1 => \axi_rdata[12]_i_43_n_0\,
- O => \axi_rdata_reg[12]_i_24_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[12]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[12]_i_7_n_0\,
- I1 => \axi_rdata[12]_i_8_n_0\,
- O => \axi_rdata_reg[12]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[13]_i_1_n_0\,
- Q => s00_axi_rdata(13),
- R => rst_i
- );
-\axi_rdata_reg[13]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[13]_i_29_n_0\,
- I1 => \axi_rdata[13]_i_30_n_0\,
- O => \axi_rdata_reg[13]_i_11_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[13]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[13]_i_31_n_0\,
- I1 => \axi_rdata[13]_i_32_n_0\,
- O => \axi_rdata_reg[13]_i_12_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[13]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[13]_i_35_n_0\,
- I1 => \axi_rdata[13]_i_36_n_0\,
- O => \axi_rdata_reg[13]_i_18_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[13]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[13]_i_5_n_0\,
- I1 => \axi_rdata[13]_i_6_n_0\,
- O => \axi_rdata_reg[13]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[13]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][13]\,
- I1 => \axi_rdata[13]_i_39_n_0\,
- O => \axi_rdata_reg[13]_i_20_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[13]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[13]_i_42_n_0\,
- I1 => \axi_rdata[13]_i_43_n_0\,
- O => \axi_rdata_reg[13]_i_24_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[13]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[13]_i_7_n_0\,
- I1 => \axi_rdata[13]_i_8_n_0\,
- O => \axi_rdata_reg[13]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[14]_i_1_n_0\,
- Q => s00_axi_rdata(14),
- R => rst_i
- );
-\axi_rdata_reg[14]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[14]_i_29_n_0\,
- I1 => \axi_rdata[14]_i_30_n_0\,
- O => \axi_rdata_reg[14]_i_11_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[14]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[14]_i_31_n_0\,
- I1 => \axi_rdata[14]_i_32_n_0\,
- O => \axi_rdata_reg[14]_i_12_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[14]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[14]_i_35_n_0\,
- I1 => \axi_rdata[14]_i_36_n_0\,
- O => \axi_rdata_reg[14]_i_18_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[14]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[14]_i_5_n_0\,
- I1 => \axi_rdata[14]_i_6_n_0\,
- O => \axi_rdata_reg[14]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[14]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][14]\,
- I1 => \axi_rdata[14]_i_39_n_0\,
- O => \axi_rdata_reg[14]_i_20_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[14]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[14]_i_42_n_0\,
- I1 => \axi_rdata[14]_i_43_n_0\,
- O => \axi_rdata_reg[14]_i_24_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[14]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[14]_i_7_n_0\,
- I1 => \axi_rdata[14]_i_8_n_0\,
- O => \axi_rdata_reg[14]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[15]_i_1_n_0\,
- Q => s00_axi_rdata(15),
- R => rst_i
- );
-\axi_rdata_reg[15]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[15]_i_29_n_0\,
- I1 => \axi_rdata[15]_i_30_n_0\,
- O => \axi_rdata_reg[15]_i_11_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[15]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[15]_i_31_n_0\,
- I1 => \axi_rdata[15]_i_32_n_0\,
- O => \axi_rdata_reg[15]_i_12_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[15]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[15]_i_35_n_0\,
- I1 => \axi_rdata[15]_i_36_n_0\,
- O => \axi_rdata_reg[15]_i_18_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[15]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[15]_i_5_n_0\,
- I1 => \axi_rdata[15]_i_6_n_0\,
- O => \axi_rdata_reg[15]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[15]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][15]\,
- I1 => \axi_rdata[15]_i_39_n_0\,
- O => \axi_rdata_reg[15]_i_20_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[15]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[15]_i_42_n_0\,
- I1 => \axi_rdata[15]_i_43_n_0\,
- O => \axi_rdata_reg[15]_i_24_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[15]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[15]_i_7_n_0\,
- I1 => \axi_rdata[15]_i_8_n_0\,
- O => \axi_rdata_reg[15]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[16]_i_1_n_0\,
- Q => s00_axi_rdata(16),
- R => rst_i
- );
-\axi_rdata_reg[16]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[16]_i_29_n_0\,
- I1 => \axi_rdata[16]_i_30_n_0\,
- O => \axi_rdata_reg[16]_i_11_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[16]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[16]_i_31_n_0\,
- I1 => \axi_rdata[16]_i_32_n_0\,
- O => \axi_rdata_reg[16]_i_12_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[16]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[16]_i_35_n_0\,
- I1 => \axi_rdata[16]_i_36_n_0\,
- O => \axi_rdata_reg[16]_i_18_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[16]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[16]_i_5_n_0\,
- I1 => \axi_rdata[16]_i_6_n_0\,
- O => \axi_rdata_reg[16]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[16]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][16]\,
- I1 => \axi_rdata[16]_i_39_n_0\,
- O => \axi_rdata_reg[16]_i_20_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[16]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[16]_i_42_n_0\,
- I1 => \axi_rdata[16]_i_43_n_0\,
- O => \axi_rdata_reg[16]_i_24_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[16]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[16]_i_7_n_0\,
- I1 => \axi_rdata[16]_i_8_n_0\,
- O => \axi_rdata_reg[16]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[17]_i_1_n_0\,
- Q => s00_axi_rdata(17),
- R => rst_i
- );
-\axi_rdata_reg[17]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[17]_i_29_n_0\,
- I1 => \axi_rdata[17]_i_30_n_0\,
- O => \axi_rdata_reg[17]_i_11_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[17]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[17]_i_31_n_0\,
- I1 => \axi_rdata[17]_i_32_n_0\,
- O => \axi_rdata_reg[17]_i_12_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[17]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[17]_i_35_n_0\,
- I1 => \axi_rdata[17]_i_36_n_0\,
- O => \axi_rdata_reg[17]_i_18_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[17]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[17]_i_5_n_0\,
- I1 => \axi_rdata[17]_i_6_n_0\,
- O => \axi_rdata_reg[17]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[17]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][17]\,
- I1 => \axi_rdata[17]_i_39_n_0\,
- O => \axi_rdata_reg[17]_i_20_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[17]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[17]_i_42_n_0\,
- I1 => \axi_rdata[17]_i_43_n_0\,
- O => \axi_rdata_reg[17]_i_24_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[17]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[17]_i_7_n_0\,
- I1 => \axi_rdata[17]_i_8_n_0\,
- O => \axi_rdata_reg[17]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[18]_i_1_n_0\,
- Q => s00_axi_rdata(18),
- R => rst_i
- );
-\axi_rdata_reg[18]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[18]_i_29_n_0\,
- I1 => \axi_rdata[18]_i_30_n_0\,
- O => \axi_rdata_reg[18]_i_11_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[18]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[18]_i_31_n_0\,
- I1 => \axi_rdata[18]_i_32_n_0\,
- O => \axi_rdata_reg[18]_i_12_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[18]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[18]_i_35_n_0\,
- I1 => \axi_rdata[18]_i_36_n_0\,
- O => \axi_rdata_reg[18]_i_18_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[18]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[18]_i_5_n_0\,
- I1 => \axi_rdata[18]_i_6_n_0\,
- O => \axi_rdata_reg[18]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[18]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][18]\,
- I1 => \axi_rdata[18]_i_39_n_0\,
- O => \axi_rdata_reg[18]_i_20_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[18]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[18]_i_42_n_0\,
- I1 => \axi_rdata[18]_i_43_n_0\,
- O => \axi_rdata_reg[18]_i_24_n_0\,
- S => \^axi_rdata_reg[18]_0\
- );
-\axi_rdata_reg[18]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[18]_i_7_n_0\,
- I1 => \axi_rdata[18]_i_8_n_0\,
- O => \axi_rdata_reg[18]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[19]_i_1_n_0\,
- Q => s00_axi_rdata(19),
- R => rst_i
- );
-\axi_rdata_reg[19]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[19]_i_29_n_0\,
- I1 => \axi_rdata[19]_i_30_n_0\,
- O => \axi_rdata_reg[19]_i_11_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[19]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[19]_i_31_n_0\,
- I1 => \axi_rdata[19]_i_32_n_0\,
- O => \axi_rdata_reg[19]_i_12_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[19]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[19]_i_35_n_0\,
- I1 => \axi_rdata[19]_i_36_n_0\,
- O => \axi_rdata_reg[19]_i_18_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[19]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[19]_i_5_n_0\,
- I1 => \axi_rdata[19]_i_6_n_0\,
- O => \axi_rdata_reg[19]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[19]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][19]\,
- I1 => \axi_rdata[19]_i_39_n_0\,
- O => \axi_rdata_reg[19]_i_20_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[19]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[19]_i_42_n_0\,
- I1 => \axi_rdata[19]_i_43_n_0\,
- O => \axi_rdata_reg[19]_i_24_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[19]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[19]_i_7_n_0\,
- I1 => \axi_rdata[19]_i_8_n_0\,
- O => \axi_rdata_reg[19]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[1]_i_1_n_0\,
- Q => s00_axi_rdata(1),
- R => rst_i
- );
-\axi_rdata_reg[1]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[1]_i_29_n_0\,
- I1 => \axi_rdata[1]_i_30_n_0\,
- O => \axi_rdata_reg[1]_i_11_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[1]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[1]_i_31_n_0\,
- I1 => \axi_rdata[1]_i_32_n_0\,
- O => \axi_rdata_reg[1]_i_12_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[1]_i_13\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[1]_i_33_n_0\,
- I1 => \data_o_reg[6][1]\,
- O => \axi_rdata_reg[1]_i_13_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[1]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[1]_i_36_n_0\,
- I1 => \axi_rdata[1]_i_37_n_0\,
- O => \axi_rdata_reg[1]_i_18_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[1]_i_19\: unisim.vcomponents.MUXF7
- port map (
- I0 => \data_o_reg[6][1]_0\,
- I1 => \axi_rdata[1]_i_39_n_0\,
- O => \axi_rdata_reg[1]_i_19_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[1]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[1]_i_5_n_0\,
- I1 => \axi_rdata[1]_i_6_n_0\,
- O => \axi_rdata_reg[1]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[1]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][1]\,
- I1 => \axi_rdata[1]_i_41_n_0\,
- O => \axi_rdata_reg[1]_i_20_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[1]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[1]_i_44_n_0\,
- I1 => \axi_rdata[1]_i_45_n_0\,
- O => \axi_rdata_reg[1]_i_24_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[1]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[1]_i_7_n_0\,
- I1 => \axi_rdata[1]_i_8_n_0\,
- O => \axi_rdata_reg[1]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[20]_i_1_n_0\,
- Q => s00_axi_rdata(20),
- R => rst_i
- );
-\axi_rdata_reg[20]_i_15\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[20]_i_25_n_0\,
- I1 => \axi_rdata[20]_i_26_n_0\,
- O => \axi_rdata_reg[20]_i_15_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[20]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[20]_i_35_n_0\,
- I1 => \axi_rdata[20]_i_36_n_0\,
- O => \axi_rdata_reg[20]_i_21_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[20]_i_22\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[20]_i_37_n_0\,
- I1 => \axi_rdata[20]_i_38_n_0\,
- O => \axi_rdata_reg[20]_i_22_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[20]_i_6\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[20]_i_16_n_0\,
- I1 => \axi_rdata[20]_i_17_n_0\,
- O => \axi_rdata_reg[20]_i_6_n_0\,
- S => axi_araddr(6)
- );
-\axi_rdata_reg[21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[21]_i_1_n_0\,
- Q => s00_axi_rdata(21),
- R => rst_i
- );
-\axi_rdata_reg[21]_i_15\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[21]_i_25_n_0\,
- I1 => \axi_rdata[21]_i_26_n_0\,
- O => \axi_rdata_reg[21]_i_15_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[21]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[21]_i_35_n_0\,
- I1 => \axi_rdata[21]_i_36_n_0\,
- O => \axi_rdata_reg[21]_i_21_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[21]_i_22\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[21]_i_37_n_0\,
- I1 => \axi_rdata[21]_i_38_n_0\,
- O => \axi_rdata_reg[21]_i_22_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[21]_i_6\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[21]_i_16_n_0\,
- I1 => \axi_rdata[21]_i_17_n_0\,
- O => \axi_rdata_reg[21]_i_6_n_0\,
- S => axi_araddr(6)
- );
-\axi_rdata_reg[22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[22]_i_1_n_0\,
- Q => s00_axi_rdata(22),
- R => rst_i
- );
-\axi_rdata_reg[22]_i_15\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[22]_i_25_n_0\,
- I1 => \axi_rdata[22]_i_26_n_0\,
- O => \axi_rdata_reg[22]_i_15_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[22]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[22]_i_35_n_0\,
- I1 => \axi_rdata[22]_i_36_n_0\,
- O => \axi_rdata_reg[22]_i_21_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[22]_i_22\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[22]_i_37_n_0\,
- I1 => \axi_rdata[22]_i_38_n_0\,
- O => \axi_rdata_reg[22]_i_22_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[22]_i_6\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[22]_i_16_n_0\,
- I1 => \axi_rdata[22]_i_17_n_0\,
- O => \axi_rdata_reg[22]_i_6_n_0\,
- S => axi_araddr(6)
- );
-\axi_rdata_reg[23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[23]_i_1_n_0\,
- Q => s00_axi_rdata(23),
- R => rst_i
- );
-\axi_rdata_reg[23]_i_16\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[23]_i_26_n_0\,
- I1 => \axi_rdata[23]_i_27_n_0\,
- O => \axi_rdata_reg[23]_i_16_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[23]_i_22\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[23]_i_36_n_0\,
- I1 => \axi_rdata[23]_i_37_n_0\,
- O => \axi_rdata_reg[23]_i_22_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[23]_i_23\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[23]_i_38_n_0\,
- I1 => \axi_rdata[23]_i_39_n_0\,
- O => \axi_rdata_reg[23]_i_23_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[23]_i_7\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[23]_i_17_n_0\,
- I1 => \axi_rdata[23]_i_18_n_0\,
- O => \axi_rdata_reg[23]_i_7_n_0\,
- S => axi_araddr(6)
- );
-\axi_rdata_reg[24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[24]_i_1_n_0\,
- Q => s00_axi_rdata(24),
- R => rst_i
- );
-\axi_rdata_reg[24]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[24]_i_18_n_0\,
- I1 => \axi_rdata[24]_i_19_n_0\,
- O => \axi_rdata_reg[24]_i_10_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[24]_i_15\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[24]_i_20_n_0\,
- I1 => \axi_rdata[24]_i_21_n_0\,
- O => \axi_rdata_reg[24]_i_15_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[24]_i_16\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[24]_i_22_n_0\,
- I1 => \axi_rdata[24]_i_23_n_0\,
- O => \axi_rdata_reg[24]_i_16_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[24]_i_8\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[24]_i_15_n_0\,
- I1 => \axi_rdata_reg[24]_i_16_n_0\,
- O => \axi_rdata_reg[24]_i_8_n_0\,
- S => \^axi_rdata_reg[23]_0\(3)
- );
-\axi_rdata_reg[25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[25]_i_1_n_0\,
- Q => s00_axi_rdata(25),
- R => rst_i
- );
-\axi_rdata_reg[25]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[25]_i_18_n_0\,
- I1 => \axi_rdata[25]_i_19_n_0\,
- O => \axi_rdata_reg[25]_i_10_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[25]_i_15\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[25]_i_20_n_0\,
- I1 => \axi_rdata[25]_i_21_n_0\,
- O => \axi_rdata_reg[25]_i_15_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[25]_i_16\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[25]_i_22_n_0\,
- I1 => \axi_rdata[25]_i_23_n_0\,
- O => \axi_rdata_reg[25]_i_16_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[25]_i_8\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[25]_i_15_n_0\,
- I1 => \axi_rdata_reg[25]_i_16_n_0\,
- O => \axi_rdata_reg[25]_i_8_n_0\,
- S => \^axi_rdata_reg[23]_0\(3)
- );
-\axi_rdata_reg[26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[26]_i_1_n_0\,
- Q => s00_axi_rdata(26),
- R => rst_i
- );
-\axi_rdata_reg[26]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[26]_i_18_n_0\,
- I1 => \axi_rdata[26]_i_19_n_0\,
- O => \axi_rdata_reg[26]_i_10_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[26]_i_15\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[26]_i_20_n_0\,
- I1 => \axi_rdata[26]_i_21_n_0\,
- O => \axi_rdata_reg[26]_i_15_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[26]_i_16\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[26]_i_22_n_0\,
- I1 => \axi_rdata[26]_i_23_n_0\,
- O => \axi_rdata_reg[26]_i_16_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[26]_i_8\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[26]_i_15_n_0\,
- I1 => \axi_rdata_reg[26]_i_16_n_0\,
- O => \axi_rdata_reg[26]_i_8_n_0\,
- S => \^axi_rdata_reg[23]_0\(3)
- );
-\axi_rdata_reg[27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[27]_i_1_n_0\,
- Q => s00_axi_rdata(27),
- R => rst_i
- );
-\axi_rdata_reg[27]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[27]_i_18_n_0\,
- I1 => \axi_rdata[27]_i_19_n_0\,
- O => \axi_rdata_reg[27]_i_10_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[27]_i_15\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[27]_i_20_n_0\,
- I1 => \axi_rdata[27]_i_21_n_0\,
- O => \axi_rdata_reg[27]_i_15_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[27]_i_16\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[27]_i_22_n_0\,
- I1 => \axi_rdata[27]_i_23_n_0\,
- O => \axi_rdata_reg[27]_i_16_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[27]_i_8\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[27]_i_15_n_0\,
- I1 => \axi_rdata_reg[27]_i_16_n_0\,
- O => \axi_rdata_reg[27]_i_8_n_0\,
- S => \^axi_rdata_reg[23]_0\(3)
- );
-\axi_rdata_reg[28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[28]_i_1_n_0\,
- Q => s00_axi_rdata(28),
- R => rst_i
- );
-\axi_rdata_reg[28]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[28]_i_18_n_0\,
- I1 => \axi_rdata[28]_i_19_n_0\,
- O => \axi_rdata_reg[28]_i_10_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[28]_i_15\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[28]_i_20_n_0\,
- I1 => \axi_rdata[28]_i_21_n_0\,
- O => \axi_rdata_reg[28]_i_15_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[28]_i_16\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[28]_i_22_n_0\,
- I1 => \axi_rdata[28]_i_23_n_0\,
- O => \axi_rdata_reg[28]_i_16_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[28]_i_8\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[28]_i_15_n_0\,
- I1 => \axi_rdata_reg[28]_i_16_n_0\,
- O => \axi_rdata_reg[28]_i_8_n_0\,
- S => \^axi_rdata_reg[23]_0\(3)
- );
-\axi_rdata_reg[29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[29]_i_1_n_0\,
- Q => s00_axi_rdata(29),
- R => rst_i
- );
-\axi_rdata_reg[29]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[29]_i_18_n_0\,
- I1 => \axi_rdata[29]_i_19_n_0\,
- O => \axi_rdata_reg[29]_i_10_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[29]_i_15\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[29]_i_20_n_0\,
- I1 => \axi_rdata[29]_i_21_n_0\,
- O => \axi_rdata_reg[29]_i_15_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[29]_i_16\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[29]_i_22_n_0\,
- I1 => \axi_rdata[29]_i_23_n_0\,
- O => \axi_rdata_reg[29]_i_16_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[29]_i_8\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[29]_i_15_n_0\,
- I1 => \axi_rdata_reg[29]_i_16_n_0\,
- O => \axi_rdata_reg[29]_i_8_n_0\,
- S => \^axi_rdata_reg[23]_0\(3)
- );
-\axi_rdata_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[2]_i_1_n_0\,
- Q => s00_axi_rdata(2),
- R => rst_i
- );
-\axi_rdata_reg[2]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[2]_i_29_n_0\,
- I1 => \axi_rdata[2]_i_30_n_0\,
- O => \axi_rdata_reg[2]_i_11_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[2]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[2]_i_31_n_0\,
- I1 => \axi_rdata[2]_i_32_n_0\,
- O => \axi_rdata_reg[2]_i_12_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[2]_i_13\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[2]_i_33_n_0\,
- I1 => \data_o_reg[6][2]\,
- O => \axi_rdata_reg[2]_i_13_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[2]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[2]_i_36_n_0\,
- I1 => \axi_rdata[2]_i_37_n_0\,
- O => \axi_rdata_reg[2]_i_18_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[2]_i_19\: unisim.vcomponents.MUXF7
- port map (
- I0 => \data_o_reg[6][2]_0\,
- I1 => \axi_rdata[2]_i_39_n_0\,
- O => \axi_rdata_reg[2]_i_19_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[2]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[2]_i_5_n_0\,
- I1 => \axi_rdata[2]_i_6_n_0\,
- O => \axi_rdata_reg[2]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[2]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][2]\,
- I1 => \axi_rdata[2]_i_41_n_0\,
- O => \axi_rdata_reg[2]_i_20_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[2]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[2]_i_44_n_0\,
- I1 => \axi_rdata[2]_i_45_n_0\,
- O => \axi_rdata_reg[2]_i_24_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[2]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[2]_i_7_n_0\,
- I1 => \axi_rdata[2]_i_8_n_0\,
- O => \axi_rdata_reg[2]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[30]_i_1_n_0\,
- Q => s00_axi_rdata(30),
- R => rst_i
- );
-\axi_rdata_reg[30]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[30]_i_18_n_0\,
- I1 => \axi_rdata[30]_i_19_n_0\,
- O => \axi_rdata_reg[30]_i_10_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[30]_i_15\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[30]_i_20_n_0\,
- I1 => \axi_rdata[30]_i_21_n_0\,
- O => \axi_rdata_reg[30]_i_15_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[30]_i_16\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[30]_i_22_n_0\,
- I1 => \axi_rdata[30]_i_23_n_0\,
- O => \axi_rdata_reg[30]_i_16_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[30]_i_8\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[30]_i_15_n_0\,
- I1 => \axi_rdata_reg[30]_i_16_n_0\,
- O => \axi_rdata_reg[30]_i_8_n_0\,
- S => \^axi_rdata_reg[23]_0\(3)
- );
-\axi_rdata_reg[31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[31]_i_2_n_0\,
- Q => s00_axi_rdata(31),
- R => rst_i
- );
-\axi_rdata_reg[31]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[31]_i_19_n_0\,
- I1 => \axi_rdata[31]_i_20_n_0\,
- O => \axi_rdata_reg[31]_i_11_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[31]_i_16\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[31]_i_21_n_0\,
- I1 => \axi_rdata[31]_i_22_n_0\,
- O => \axi_rdata_reg[31]_i_16_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[31]_i_17\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[31]_i_23_n_0\,
- I1 => \axi_rdata[31]_i_24_n_0\,
- O => \axi_rdata_reg[31]_i_17_n_0\,
- S => \^axi_rdata_reg[23]_0\(2)
- );
-\axi_rdata_reg[31]_i_9\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[31]_i_16_n_0\,
- I1 => \axi_rdata_reg[31]_i_17_n_0\,
- O => \axi_rdata_reg[31]_i_9_n_0\,
- S => \^axi_rdata_reg[23]_0\(3)
- );
-\axi_rdata_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[3]_i_1_n_0\,
- Q => s00_axi_rdata(3),
- R => rst_i
- );
-\axi_rdata_reg[3]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[3]_i_29_n_0\,
- I1 => \axi_rdata[3]_i_30_n_0\,
- O => \axi_rdata_reg[3]_i_11_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[3]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[3]_i_31_n_0\,
- I1 => \axi_rdata[3]_i_32_n_0\,
- O => \axi_rdata_reg[3]_i_12_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[3]_i_13\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[3]_i_33_n_0\,
- I1 => \data_o_reg[6][3]\,
- O => \axi_rdata_reg[3]_i_13_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[3]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[3]_i_36_n_0\,
- I1 => \axi_rdata[3]_i_37_n_0\,
- O => \axi_rdata_reg[3]_i_18_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[3]_i_19\: unisim.vcomponents.MUXF7
- port map (
- I0 => \data_o_reg[6][3]_0\,
- I1 => \axi_rdata[3]_i_39_n_0\,
- O => \axi_rdata_reg[3]_i_19_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[3]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[3]_i_5_n_0\,
- I1 => \axi_rdata[3]_i_6_n_0\,
- O => \axi_rdata_reg[3]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[3]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][3]\,
- I1 => \axi_rdata[3]_i_41_n_0\,
- O => \axi_rdata_reg[3]_i_20_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[3]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[3]_i_44_n_0\,
- I1 => \axi_rdata[3]_i_45_n_0\,
- O => \axi_rdata_reg[3]_i_24_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[3]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[3]_i_7_n_0\,
- I1 => \axi_rdata[3]_i_8_n_0\,
- O => \axi_rdata_reg[3]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[4]_i_1_n_0\,
- Q => s00_axi_rdata(4),
- R => rst_i
- );
-\axi_rdata_reg[4]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[4]_i_29_n_0\,
- I1 => \axi_rdata[4]_i_30_n_0\,
- O => \axi_rdata_reg[4]_i_11_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[4]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[4]_i_31_n_0\,
- I1 => \axi_rdata[4]_i_32_n_0\,
- O => \axi_rdata_reg[4]_i_12_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[4]_i_13\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[4]_i_33_n_0\,
- I1 => \data_o_reg[6][4]\,
- O => \axi_rdata_reg[4]_i_13_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[4]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[4]_i_36_n_0\,
- I1 => \axi_rdata[4]_i_37_n_0\,
- O => \axi_rdata_reg[4]_i_18_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[4]_i_19\: unisim.vcomponents.MUXF7
- port map (
- I0 => \data_o_reg[6][4]_0\,
- I1 => \axi_rdata[4]_i_39_n_0\,
- O => \axi_rdata_reg[4]_i_19_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[4]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[4]_i_5_n_0\,
- I1 => \axi_rdata[4]_i_6_n_0\,
- O => \axi_rdata_reg[4]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[4]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][4]\,
- I1 => \axi_rdata[4]_i_41_n_0\,
- O => \axi_rdata_reg[4]_i_20_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[4]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[4]_i_44_n_0\,
- I1 => \axi_rdata[4]_i_45_n_0\,
- O => \axi_rdata_reg[4]_i_24_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[4]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[4]_i_7_n_0\,
- I1 => \axi_rdata[4]_i_8_n_0\,
- O => \axi_rdata_reg[4]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[5]_i_1_n_0\,
- Q => s00_axi_rdata(5),
- R => rst_i
- );
-\axi_rdata_reg[5]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[5]_i_29_n_0\,
- I1 => \axi_rdata[5]_i_30_n_0\,
- O => \axi_rdata_reg[5]_i_11_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[5]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[5]_i_31_n_0\,
- I1 => \axi_rdata[5]_i_32_n_0\,
- O => \axi_rdata_reg[5]_i_12_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[5]_i_13\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[5]_i_33_n_0\,
- I1 => \data_o_reg[6][5]\,
- O => \axi_rdata_reg[5]_i_13_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[5]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[5]_i_36_n_0\,
- I1 => \axi_rdata[5]_i_37_n_0\,
- O => \axi_rdata_reg[5]_i_18_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[5]_i_19\: unisim.vcomponents.MUXF7
- port map (
- I0 => \data_o_reg[6][5]_0\,
- I1 => \axi_rdata[5]_i_39_n_0\,
- O => \axi_rdata_reg[5]_i_19_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[5]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[5]_i_5_n_0\,
- I1 => \axi_rdata[5]_i_6_n_0\,
- O => \axi_rdata_reg[5]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[5]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][5]\,
- I1 => \axi_rdata[5]_i_41_n_0\,
- O => \axi_rdata_reg[5]_i_20_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[5]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[5]_i_44_n_0\,
- I1 => \axi_rdata[5]_i_45_n_0\,
- O => \axi_rdata_reg[5]_i_24_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[5]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[5]_i_7_n_0\,
- I1 => \axi_rdata[5]_i_8_n_0\,
- O => \axi_rdata_reg[5]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[6]_i_1_n_0\,
- Q => s00_axi_rdata(6),
- R => rst_i
- );
-\axi_rdata_reg[6]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[6]_i_29_n_0\,
- I1 => \axi_rdata[6]_i_30_n_0\,
- O => \axi_rdata_reg[6]_i_11_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[6]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[6]_i_31_n_0\,
- I1 => \axi_rdata[6]_i_32_n_0\,
- O => \axi_rdata_reg[6]_i_12_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[6]_i_13\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[6]_i_33_n_0\,
- I1 => \data_o_reg[6][6]\,
- O => \axi_rdata_reg[6]_i_13_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[6]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[6]_i_36_n_0\,
- I1 => \axi_rdata[6]_i_37_n_0\,
- O => \axi_rdata_reg[6]_i_18_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[6]_i_19\: unisim.vcomponents.MUXF7
- port map (
- I0 => \data_o_reg[6][6]_0\,
- I1 => \axi_rdata[6]_i_39_n_0\,
- O => \axi_rdata_reg[6]_i_19_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[6]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[6]_i_5_n_0\,
- I1 => \axi_rdata[6]_i_6_n_0\,
- O => \axi_rdata_reg[6]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[6]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][6]\,
- I1 => \axi_rdata[6]_i_41_n_0\,
- O => \axi_rdata_reg[6]_i_20_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[6]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[6]_i_44_n_0\,
- I1 => \axi_rdata[6]_i_45_n_0\,
- O => \axi_rdata_reg[6]_i_24_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[6]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[6]_i_7_n_0\,
- I1 => \axi_rdata[6]_i_8_n_0\,
- O => \axi_rdata_reg[6]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[7]_i_1_n_0\,
- Q => s00_axi_rdata(7),
- R => rst_i
- );
-\axi_rdata_reg[7]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[7]_i_29_n_0\,
- I1 => \axi_rdata[7]_i_30_n_0\,
- O => \axi_rdata_reg[7]_i_11_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[7]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[7]_i_31_n_0\,
- I1 => \axi_rdata[7]_i_32_n_0\,
- O => \axi_rdata_reg[7]_i_12_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[7]_i_13\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[7]_i_33_n_0\,
- I1 => \data_o_reg[6][7]\,
- O => \axi_rdata_reg[7]_i_13_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[7]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[7]_i_36_n_0\,
- I1 => \axi_rdata[7]_i_37_n_0\,
- O => \axi_rdata_reg[7]_i_18_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[7]_i_19\: unisim.vcomponents.MUXF7
- port map (
- I0 => \data_o_reg[6][7]_0\,
- I1 => \axi_rdata[7]_i_39_n_0\,
- O => \axi_rdata_reg[7]_i_19_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[7]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[7]_i_5_n_0\,
- I1 => \axi_rdata[7]_i_6_n_0\,
- O => \axi_rdata_reg[7]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[7]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][7]\,
- I1 => \axi_rdata[7]_i_41_n_0\,
- O => \axi_rdata_reg[7]_i_20_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[7]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[7]_i_44_n_0\,
- I1 => \axi_rdata[7]_i_45_n_0\,
- O => \axi_rdata_reg[7]_i_24_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[7]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[7]_i_7_n_0\,
- I1 => \axi_rdata[7]_i_8_n_0\,
- O => \axi_rdata_reg[7]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[8]_i_1_n_0\,
- Q => s00_axi_rdata(8),
- R => rst_i
- );
-\axi_rdata_reg[8]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[8]_i_29_n_0\,
- I1 => \axi_rdata[8]_i_30_n_0\,
- O => \axi_rdata_reg[8]_i_11_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[8]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[8]_i_31_n_0\,
- I1 => \axi_rdata[8]_i_32_n_0\,
- O => \axi_rdata_reg[8]_i_12_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[8]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[8]_i_35_n_0\,
- I1 => \axi_rdata[8]_i_36_n_0\,
- O => \axi_rdata_reg[8]_i_18_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[8]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[8]_i_5_n_0\,
- I1 => \axi_rdata[8]_i_6_n_0\,
- O => \axi_rdata_reg[8]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[8]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][8]\,
- I1 => \axi_rdata[8]_i_39_n_0\,
- O => \axi_rdata_reg[8]_i_20_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[8]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[8]_i_42_n_0\,
- I1 => \axi_rdata[8]_i_43_n_0\,
- O => \axi_rdata_reg[8]_i_24_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[8]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[8]_i_7_n_0\,
- I1 => \axi_rdata[8]_i_8_n_0\,
- O => \axi_rdata_reg[8]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \axi_rdata[31]_i_1_n_0\,
- D => \axi_rdata[9]_i_1_n_0\,
- Q => s00_axi_rdata(9),
- R => rst_i
- );
-\axi_rdata_reg[9]_i_11\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[9]_i_29_n_0\,
- I1 => \axi_rdata[9]_i_30_n_0\,
- O => \axi_rdata_reg[9]_i_11_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[9]_i_12\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[9]_i_31_n_0\,
- I1 => \axi_rdata[9]_i_32_n_0\,
- O => \axi_rdata_reg[9]_i_12_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[9]_i_18\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[9]_i_35_n_0\,
- I1 => \axi_rdata[9]_i_36_n_0\,
- O => \axi_rdata_reg[9]_i_18_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[9]_i_2\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[9]_i_5_n_0\,
- I1 => \axi_rdata[9]_i_6_n_0\,
- O => \axi_rdata_reg[9]_i_2_n_0\,
- S => axi_araddr(7)
- );
-\axi_rdata_reg[9]_i_20\: unisim.vcomponents.MUXF7
- port map (
- I0 => \fmc_03287_channels[19].gen_chs.data_o_reg[67][9]\,
- I1 => \axi_rdata[9]_i_39_n_0\,
- O => \axi_rdata_reg[9]_i_20_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[9]_i_24\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[9]_i_42_n_0\,
- I1 => \axi_rdata[9]_i_43_n_0\,
- O => \axi_rdata_reg[9]_i_24_n_0\,
- S => \^axi_rdata_reg[9]_0\
- );
-\axi_rdata_reg[9]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[9]_i_7_n_0\,
- I1 => \axi_rdata[9]_i_8_n_0\,
- O => \axi_rdata_reg[9]_i_3_n_0\,
- S => axi_araddr(7)
- );
-\axi_rresp[1]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"F202F2F200000000"
- )
- port map (
- I0 => \^s00_axi_rresp\(0),
- I1 => axi_rvalid0,
- I2 => \axi_rdata[31]_i_1_n_0\,
- I3 => axi_araddr(10),
- I4 => \axi_rdata[23]_i_2_n_0\,
- I5 => s00_axi_aresetn,
- O => \axi_rresp[1]_i_1_n_0\
- );
-\axi_rresp[1]_i_2\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => s00_axi_rready,
- I1 => \^s00_axi_rvalid\,
- O => axi_rvalid0
- );
-\axi_rresp_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \axi_rresp[1]_i_1_n_0\,
- Q => \^s00_axi_rresp\(0),
- R => '0'
- );
-axi_rvalid_i_1: unisim.vcomponents.LUT4
- generic map(
- INIT => X"08F8"
- )
- port map (
- I0 => s00_axi_arvalid,
- I1 => \^s00_axi_arready\,
- I2 => \^s00_axi_rvalid\,
- I3 => s00_axi_rready,
- O => axi_rvalid_i_1_n_0
- );
-axi_rvalid_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => axi_rvalid_i_1_n_0,
- Q => \^s00_axi_rvalid\,
- R => rst_i
- );
-axi_wready_i_1: unisim.vcomponents.LUT3
- generic map(
- INIT => X"08"
- )
- port map (
- I0 => s00_axi_awvalid,
- I1 => s00_axi_wvalid,
- I2 => \^s00_axi_wready\,
- O => axi_wready_i_1_n_0
- );
-axi_wready_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => axi_wready_i_1_n_0,
- Q => \^s00_axi_wready\,
- R => rst_i
- );
-\data_rw_o[100][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[100][31]_i_2_n_0\,
- O => \data_rw_o[100][15]_i_1_n_0\
- );
-\data_rw_o[100][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[100][31]_i_2_n_0\,
- O => \data_rw_o[100][23]_i_1_n_0\
- );
-\data_rw_o[100][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[100][31]_i_2_n_0\,
- O => \data_rw_o[100][31]_i_1_n_0\
- );
-\data_rw_o[100][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFF7FFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(6),
- I2 => sel0(3),
- I3 => sel0(5),
- I4 => sel0(2),
- I5 => \data_rw_o[96][31]_i_3_n_0\,
- O => \data_rw_o[100][31]_i_2_n_0\
- );
-\data_rw_o[100][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[100][31]_i_2_n_0\,
- O => \data_rw_o[100][7]_i_1_n_0\
- );
-\data_rw_o[101][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[101][31]_i_2_n_0\,
- O => \data_rw_o[101][15]_i_1_n_0\
- );
-\data_rw_o[101][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[101][31]_i_2_n_0\,
- O => \data_rw_o[101][23]_i_1_n_0\
- );
-\data_rw_o[101][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[101][31]_i_2_n_0\,
- O => \data_rw_o[101][31]_i_1_n_0\
- );
-\data_rw_o[101][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFFFD"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[78][31]_i_3_n_0\,
- I2 => \data_rw_o[33][31]_i_3_n_0\,
- I3 => \data_rw_o[85][31]_i_4_n_0\,
- I4 => sel0(4),
- I5 => sel0(1),
- O => \data_rw_o[101][31]_i_2_n_0\
- );
-\data_rw_o[101][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[101][31]_i_2_n_0\,
- O => \data_rw_o[101][7]_i_1_n_0\
- );
-\data_rw_o[102][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[102][31]_i_2_n_0\,
- O => \data_rw_o[102][15]_i_1_n_0\
- );
-\data_rw_o[102][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[102][31]_i_2_n_0\,
- O => \data_rw_o[102][23]_i_1_n_0\
- );
-\data_rw_o[102][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[102][31]_i_2_n_0\,
- O => \data_rw_o[102][31]_i_1_n_0\
- );
-\data_rw_o[102][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFDFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[78][31]_i_3_n_0\,
- I2 => sel0(5),
- I3 => sel0(1),
- I4 => \data_rw_o[85][31]_i_4_n_0\,
- I5 => \data_rw_o[32][31]_i_4_n_0\,
- O => \data_rw_o[102][31]_i_2_n_0\
- );
-\data_rw_o[102][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[102][31]_i_2_n_0\,
- O => \data_rw_o[102][7]_i_1_n_0\
- );
-\data_rw_o[103][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[103][31]_i_2_n_0\,
- O => \data_rw_o[103][15]_i_1_n_0\
- );
-\data_rw_o[103][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[103][31]_i_2_n_0\,
- O => \data_rw_o[103][23]_i_1_n_0\
- );
-\data_rw_o[103][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[103][31]_i_2_n_0\,
- O => \data_rw_o[103][31]_i_1_n_0\
- );
-\data_rw_o[103][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFF7F"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(2),
- I2 => sel0(5),
- I3 => \data_rw_o[23][31]_i_4_n_0\,
- I4 => \data_rw_o[103][31]_i_3_n_0\,
- I5 => \data_rw_o[97][31]_i_3_n_0\,
- O => \data_rw_o[103][31]_i_2_n_0\
- );
-\data_rw_o[103][31]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => sel0(4),
- I1 => sel0(7),
- O => \data_rw_o[103][31]_i_3_n_0\
- );
-\data_rw_o[103][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[103][31]_i_2_n_0\,
- O => \data_rw_o[103][7]_i_1_n_0\
- );
-\data_rw_o[10][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[10][31]_i_2_n_0\,
- O => \data_rw_o[10][15]_i_1_n_0\
- );
-\data_rw_o[10][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[10][31]_i_2_n_0\,
- O => \data_rw_o[10][23]_i_1_n_0\
- );
-\data_rw_o[10][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[10][31]_i_2_n_0\,
- O => \data_rw_o[10][31]_i_1_n_0\
- );
-\data_rw_o[10][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFDFFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(2),
- I2 => sel0(0),
- I3 => sel0(1),
- I4 => sel0(3),
- I5 => \data_rw_o[3][31]_i_7_n_0\,
- O => \data_rw_o[10][31]_i_2_n_0\
- );
-\data_rw_o[10][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[10][31]_i_2_n_0\,
- O => \data_rw_o[10][7]_i_1_n_0\
- );
-\data_rw_o[11][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[11][31]_i_2_n_0\,
- O => \data_rw_o[11][15]_i_1_n_0\
- );
-\data_rw_o[11][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[11][31]_i_2_n_0\,
- O => \data_rw_o[11][23]_i_1_n_0\
- );
-\data_rw_o[11][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[11][31]_i_2_n_0\,
- O => \data_rw_o[11][31]_i_1_n_0\
- );
-\data_rw_o[11][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFF7FFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(3),
- I2 => sel0(2),
- I3 => sel0(0),
- I4 => sel0(1),
- I5 => \data_rw_o[3][31]_i_7_n_0\,
- O => \data_rw_o[11][31]_i_2_n_0\
- );
-\data_rw_o[11][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[11][31]_i_2_n_0\,
- O => \data_rw_o[11][7]_i_1_n_0\
- );
-\data_rw_o[16][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[16][31]_i_2_n_0\,
- O => \data_rw_o[16][15]_i_1_n_0\
- );
-\data_rw_o[16][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[16][31]_i_2_n_0\,
- O => \data_rw_o[16][23]_i_1_n_0\
- );
-\data_rw_o[16][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[16][31]_i_2_n_0\,
- O => \data_rw_o[16][31]_i_1_n_0\
- );
-\data_rw_o[16][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFDFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(2),
- I2 => sel0(3),
- I3 => sel0(4),
- I4 => sel0(1),
- I5 => \data_rw_o[16][31]_i_3_n_0\,
- O => \data_rw_o[16][31]_i_2_n_0\
- );
-\data_rw_o[16][31]_i_3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => sel0(7),
- I1 => sel0(6),
- I2 => sel0(0),
- I3 => sel0(5),
- O => \data_rw_o[16][31]_i_3_n_0\
- );
-\data_rw_o[16][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[16][31]_i_2_n_0\,
- O => \data_rw_o[16][7]_i_1_n_0\
- );
-\data_rw_o[17][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[17][31]_i_2_n_0\,
- O => \data_rw_o[17][15]_i_1_n_0\
- );
-\data_rw_o[17][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[17][31]_i_2_n_0\,
- O => \data_rw_o[17][23]_i_1_n_0\
- );
-\data_rw_o[17][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[17][31]_i_2_n_0\,
- O => \data_rw_o[17][31]_i_1_n_0\
- );
-\data_rw_o[17][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFDFFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(2),
- I2 => sel0(3),
- I3 => sel0(0),
- I4 => sel0(4),
- I5 => \data_rw_o[17][31]_i_3_n_0\,
- O => \data_rw_o[17][31]_i_2_n_0\
- );
-\data_rw_o[17][31]_i_3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => sel0(7),
- I1 => sel0(6),
- I2 => sel0(1),
- I3 => sel0(5),
- O => \data_rw_o[17][31]_i_3_n_0\
- );
-\data_rw_o[17][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[17][31]_i_2_n_0\,
- O => \data_rw_o[17][7]_i_1_n_0\
- );
-\data_rw_o[18][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[18][31]_i_2_n_0\,
- O => \data_rw_o[18][15]_i_1_n_0\
- );
-\data_rw_o[18][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[18][31]_i_2_n_0\,
- O => \data_rw_o[18][23]_i_1_n_0\
- );
-\data_rw_o[18][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[18][31]_i_2_n_0\,
- O => \data_rw_o[18][31]_i_1_n_0\
- );
-\data_rw_o[18][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFDFFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(2),
- I2 => sel0(3),
- I3 => sel0(1),
- I4 => sel0(4),
- I5 => \data_rw_o[16][31]_i_3_n_0\,
- O => \data_rw_o[18][31]_i_2_n_0\
- );
-\data_rw_o[18][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[18][31]_i_2_n_0\,
- O => \data_rw_o[18][7]_i_1_n_0\
- );
-\data_rw_o[19][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[19][31]_i_2_n_0\,
- O => \data_rw_o[19][15]_i_1_n_0\
- );
-\data_rw_o[19][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[19][31]_i_2_n_0\,
- O => \data_rw_o[19][23]_i_1_n_0\
- );
-\data_rw_o[19][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[19][31]_i_2_n_0\,
- O => \data_rw_o[19][31]_i_1_n_0\
- );
-\data_rw_o[19][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFF7FFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(4),
- I2 => sel0(3),
- I3 => sel0(0),
- I4 => sel0(1),
- I5 => \data_rw_o[19][31]_i_3_n_0\,
- O => \data_rw_o[19][31]_i_2_n_0\
- );
-\data_rw_o[19][31]_i_3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => sel0(7),
- I1 => sel0(6),
- I2 => sel0(2),
- I3 => sel0(5),
- O => \data_rw_o[19][31]_i_3_n_0\
- );
-\data_rw_o[19][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[19][31]_i_2_n_0\,
- O => \data_rw_o[19][7]_i_1_n_0\
- );
-\data_rw_o[20][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[20][31]_i_2_n_0\,
- O => \data_rw_o[20][15]_i_1_n_0\
- );
-\data_rw_o[20][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[20][31]_i_2_n_0\,
- O => \data_rw_o[20][23]_i_1_n_0\
- );
-\data_rw_o[20][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[20][31]_i_2_n_0\,
- O => \data_rw_o[20][31]_i_1_n_0\
- );
-\data_rw_o[20][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFDFFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(0),
- I2 => sel0(3),
- I3 => sel0(2),
- I4 => sel0(4),
- I5 => \data_rw_o[17][31]_i_3_n_0\,
- O => \data_rw_o[20][31]_i_2_n_0\
- );
-\data_rw_o[20][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[20][31]_i_2_n_0\,
- O => \data_rw_o[20][7]_i_1_n_0\
- );
-\data_rw_o[21][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[21][31]_i_2_n_0\,
- O => \data_rw_o[21][15]_i_1_n_0\
- );
-\data_rw_o[21][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[21][31]_i_2_n_0\,
- O => \data_rw_o[21][23]_i_1_n_0\
- );
-\data_rw_o[21][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[21][31]_i_2_n_0\,
- O => \data_rw_o[21][31]_i_1_n_0\
- );
-\data_rw_o[21][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFF7FFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(4),
- I2 => sel0(3),
- I3 => sel0(0),
- I4 => sel0(2),
- I5 => \data_rw_o[17][31]_i_3_n_0\,
- O => \data_rw_o[21][31]_i_2_n_0\
- );
-\data_rw_o[21][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[21][31]_i_2_n_0\,
- O => \data_rw_o[21][7]_i_1_n_0\
- );
-\data_rw_o[22][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[22][31]_i_2_n_0\,
- O => \data_rw_o[22][15]_i_1_n_0\
- );
-\data_rw_o[22][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[22][31]_i_2_n_0\,
- O => \data_rw_o[22][23]_i_1_n_0\
- );
-\data_rw_o[22][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[22][31]_i_2_n_0\,
- O => \data_rw_o[22][31]_i_1_n_0\
- );
-\data_rw_o[22][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFF7FFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(4),
- I2 => sel0(3),
- I3 => sel0(2),
- I4 => sel0(1),
- I5 => \data_rw_o[16][31]_i_3_n_0\,
- O => \data_rw_o[22][31]_i_2_n_0\
- );
-\data_rw_o[22][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[22][31]_i_2_n_0\,
- O => \data_rw_o[22][7]_i_1_n_0\
- );
-\data_rw_o[23][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[23][31]_i_2_n_0\,
- O => \data_rw_o[23][15]_i_1_n_0\
- );
-\data_rw_o[23][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[23][31]_i_2_n_0\,
- O => \data_rw_o[23][23]_i_1_n_0\
- );
-\data_rw_o[23][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[23][31]_i_2_n_0\,
- O => \data_rw_o[23][31]_i_1_n_0\
- );
-\data_rw_o[23][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFFFD"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[23][31]_i_3_n_0\,
- I2 => \data_rw_o[23][31]_i_4_n_0\,
- I3 => \data_rw_o[23][31]_i_5_n_0\,
- I4 => sel0(3),
- I5 => sel0(5),
- O => \data_rw_o[23][31]_i_2_n_0\
- );
-\data_rw_o[23][31]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"7"
- )
- port map (
- I0 => sel0(4),
- I1 => sel0(2),
- O => \data_rw_o[23][31]_i_3_n_0\
- );
-\data_rw_o[23][31]_i_4\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"7"
- )
- port map (
- I0 => sel0(1),
- I1 => sel0(0),
- O => \data_rw_o[23][31]_i_4_n_0\
- );
-\data_rw_o[23][31]_i_5\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => sel0(6),
- I1 => sel0(7),
- O => \data_rw_o[23][31]_i_5_n_0\
- );
-\data_rw_o[23][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[23][31]_i_2_n_0\,
- O => \data_rw_o[23][7]_i_1_n_0\
- );
-\data_rw_o[24][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[24][31]_i_2_n_0\,
- O => \data_rw_o[24][15]_i_1_n_0\
- );
-\data_rw_o[24][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[24][31]_i_2_n_0\,
- O => \data_rw_o[24][23]_i_1_n_0\
- );
-\data_rw_o[24][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[24][31]_i_2_n_0\,
- O => \data_rw_o[24][31]_i_1_n_0\
- );
-\data_rw_o[24][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFDFFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(2),
- I2 => sel0(0),
- I3 => sel0(3),
- I4 => sel0(4),
- I5 => \data_rw_o[17][31]_i_3_n_0\,
- O => \data_rw_o[24][31]_i_2_n_0\
- );
-\data_rw_o[24][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[24][31]_i_2_n_0\,
- O => \data_rw_o[24][7]_i_1_n_0\
- );
-\data_rw_o[25][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[25][31]_i_2_n_0\,
- O => \data_rw_o[25][15]_i_1_n_0\
- );
-\data_rw_o[25][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[25][31]_i_2_n_0\,
- O => \data_rw_o[25][23]_i_1_n_0\
- );
-\data_rw_o[25][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[25][31]_i_2_n_0\,
- O => \data_rw_o[25][31]_i_1_n_0\
- );
-\data_rw_o[25][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFF7FFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(4),
- I2 => sel0(1),
- I3 => sel0(0),
- I4 => sel0(3),
- I5 => \data_rw_o[19][31]_i_3_n_0\,
- O => \data_rw_o[25][31]_i_2_n_0\
- );
-\data_rw_o[25][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[25][31]_i_2_n_0\,
- O => \data_rw_o[25][7]_i_1_n_0\
- );
-\data_rw_o[26][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[26][31]_i_2_n_0\,
- O => \data_rw_o[26][15]_i_1_n_0\
- );
-\data_rw_o[26][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[26][31]_i_2_n_0\,
- O => \data_rw_o[26][23]_i_1_n_0\
- );
-\data_rw_o[26][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[26][31]_i_2_n_0\,
- O => \data_rw_o[26][31]_i_1_n_0\
- );
-\data_rw_o[26][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFF7FFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(4),
- I2 => sel0(0),
- I3 => sel0(3),
- I4 => sel0(1),
- I5 => \data_rw_o[19][31]_i_3_n_0\,
- O => \data_rw_o[26][31]_i_2_n_0\
- );
-\data_rw_o[26][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[26][31]_i_2_n_0\,
- O => \data_rw_o[26][7]_i_1_n_0\
- );
-\data_rw_o[27][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[27][31]_i_2_n_0\,
- O => \data_rw_o[27][15]_i_1_n_0\
- );
-\data_rw_o[27][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[27][31]_i_2_n_0\,
- O => \data_rw_o[27][23]_i_1_n_0\
- );
-\data_rw_o[27][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[27][31]_i_2_n_0\,
- O => \data_rw_o[27][31]_i_1_n_0\
- );
-\data_rw_o[27][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFF7FFFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(3),
- I2 => sel0(4),
- I3 => sel0(0),
- I4 => sel0(1),
- I5 => \data_rw_o[19][31]_i_3_n_0\,
- O => \data_rw_o[27][31]_i_2_n_0\
- );
-\data_rw_o[27][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[27][31]_i_2_n_0\,
- O => \data_rw_o[27][7]_i_1_n_0\
- );
-\data_rw_o[28][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[28][31]_i_2_n_0\,
- O => \data_rw_o[28][15]_i_1_n_0\
- );
-\data_rw_o[28][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[28][31]_i_2_n_0\,
- O => \data_rw_o[28][23]_i_1_n_0\
- );
-\data_rw_o[28][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[28][31]_i_2_n_0\,
- O => \data_rw_o[28][31]_i_1_n_0\
- );
-\data_rw_o[28][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFF7FFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(4),
- I2 => sel0(0),
- I3 => sel0(3),
- I4 => sel0(2),
- I5 => \data_rw_o[17][31]_i_3_n_0\,
- O => \data_rw_o[28][31]_i_2_n_0\
- );
-\data_rw_o[28][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[28][31]_i_2_n_0\,
- O => \data_rw_o[28][7]_i_1_n_0\
- );
-\data_rw_o[29][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[29][31]_i_2_n_0\,
- O => \data_rw_o[29][15]_i_1_n_0\
- );
-\data_rw_o[29][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[29][31]_i_2_n_0\,
- O => \data_rw_o[29][23]_i_1_n_0\
- );
-\data_rw_o[29][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[29][31]_i_2_n_0\,
- O => \data_rw_o[29][31]_i_1_n_0\
- );
-\data_rw_o[29][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFF7FFFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(2),
- I2 => sel0(4),
- I3 => sel0(0),
- I4 => sel0(3),
- I5 => \data_rw_o[17][31]_i_3_n_0\,
- O => \data_rw_o[29][31]_i_2_n_0\
- );
-\data_rw_o[29][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[29][31]_i_2_n_0\,
- O => \data_rw_o[29][7]_i_1_n_0\
- );
-\data_rw_o[30][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[30][31]_i_2_n_0\,
- O => \data_rw_o[30][15]_i_1_n_0\
- );
-\data_rw_o[30][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[30][31]_i_2_n_0\,
- O => \data_rw_o[30][23]_i_1_n_0\
- );
-\data_rw_o[30][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[30][31]_i_2_n_0\,
- O => \data_rw_o[30][31]_i_1_n_0\
- );
-\data_rw_o[30][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFF7FFFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(2),
- I2 => sel0(4),
- I3 => sel0(3),
- I4 => sel0(1),
- I5 => \data_rw_o[16][31]_i_3_n_0\,
- O => \data_rw_o[30][31]_i_2_n_0\
- );
-\data_rw_o[30][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[30][31]_i_2_n_0\,
- O => \data_rw_o[30][7]_i_1_n_0\
- );
-\data_rw_o[31][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[31][31]_i_2_n_0\,
- O => \data_rw_o[31][15]_i_1_n_0\
- );
-\data_rw_o[31][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[31][31]_i_2_n_0\,
- O => \data_rw_o[31][23]_i_1_n_0\
- );
-\data_rw_o[31][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[31][31]_i_2_n_0\,
- O => \data_rw_o[31][31]_i_1_n_0\
- );
-\data_rw_o[31][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFDFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[31][31]_i_3_n_0\,
- I2 => sel0(7),
- I3 => sel0(6),
- I4 => sel0(4),
- I5 => sel0(5),
- O => \data_rw_o[31][31]_i_2_n_0\
- );
-\data_rw_o[31][31]_i_3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"7FFF"
- )
- port map (
- I0 => sel0(2),
- I1 => sel0(3),
- I2 => sel0(0),
- I3 => sel0(1),
- O => \data_rw_o[31][31]_i_3_n_0\
- );
-\data_rw_o[31][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[31][31]_i_2_n_0\,
- O => \data_rw_o[31][7]_i_1_n_0\
- );
-\data_rw_o[32][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[32][31]_i_2_n_0\,
- O => \data_rw_o[32][15]_i_1_n_0\
- );
-\data_rw_o[32][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[32][31]_i_2_n_0\,
- O => \data_rw_o[32][23]_i_1_n_0\
- );
-\data_rw_o[32][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[32][31]_i_2_n_0\,
- O => \data_rw_o[32][31]_i_1_n_0\
- );
-\data_rw_o[32][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFFDF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[32][31]_i_3_n_0\,
- I2 => sel0(5),
- I3 => sel0(1),
- I4 => \data_rw_o[23][31]_i_5_n_0\,
- I5 => \data_rw_o[32][31]_i_4_n_0\,
- O => \data_rw_o[32][31]_i_2_n_0\
- );
-\data_rw_o[32][31]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => sel0(3),
- I1 => sel0(2),
- O => \data_rw_o[32][31]_i_3_n_0\
- );
-\data_rw_o[32][31]_i_4\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => sel0(0),
- I1 => sel0(4),
- O => \data_rw_o[32][31]_i_4_n_0\
- );
-\data_rw_o[32][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[32][31]_i_2_n_0\,
- O => \data_rw_o[32][7]_i_1_n_0\
- );
-\data_rw_o[33][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[33][31]_i_2_n_0\,
- O => \data_rw_o[33][15]_i_1_n_0\
- );
-\data_rw_o[33][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[33][31]_i_2_n_0\,
- O => \data_rw_o[33][23]_i_1_n_0\
- );
-\data_rw_o[33][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[33][31]_i_2_n_0\,
- O => \data_rw_o[33][31]_i_1_n_0\
- );
-\data_rw_o[33][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFFFD"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[32][31]_i_3_n_0\,
- I2 => \data_rw_o[33][31]_i_3_n_0\,
- I3 => \data_rw_o[23][31]_i_5_n_0\,
- I4 => sel0(4),
- I5 => sel0(1),
- O => \data_rw_o[33][31]_i_2_n_0\
- );
-\data_rw_o[33][31]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"7"
- )
- port map (
- I0 => sel0(5),
- I1 => sel0(0),
- O => \data_rw_o[33][31]_i_3_n_0\
- );
-\data_rw_o[33][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[33][31]_i_2_n_0\,
- O => \data_rw_o[33][7]_i_1_n_0\
- );
-\data_rw_o[34][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[34][31]_i_2_n_0\,
- O => \data_rw_o[34][15]_i_1_n_0\
- );
-\data_rw_o[34][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[34][31]_i_2_n_0\,
- O => \data_rw_o[34][23]_i_1_n_0\
- );
-\data_rw_o[34][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[34][31]_i_2_n_0\,
- O => \data_rw_o[34][31]_i_1_n_0\
- );
-\data_rw_o[34][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFDFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[32][31]_i_3_n_0\,
- I2 => sel0(1),
- I3 => sel0(5),
- I4 => \data_rw_o[23][31]_i_5_n_0\,
- I5 => \data_rw_o[32][31]_i_4_n_0\,
- O => \data_rw_o[34][31]_i_2_n_0\
- );
-\data_rw_o[34][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[34][31]_i_2_n_0\,
- O => \data_rw_o[34][7]_i_1_n_0\
- );
-\data_rw_o[35][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[35][31]_i_2_n_0\,
- O => \data_rw_o[35][15]_i_1_n_0\
- );
-\data_rw_o[35][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[35][31]_i_2_n_0\,
- O => \data_rw_o[35][23]_i_1_n_0\
- );
-\data_rw_o[35][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[35][31]_i_2_n_0\,
- O => \data_rw_o[35][31]_i_1_n_0\
- );
-\data_rw_o[35][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFFF7"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(5),
- I2 => sel0(3),
- I3 => \data_rw_o[23][31]_i_4_n_0\,
- I4 => \data_rw_o[23][31]_i_5_n_0\,
- I5 => \data_rw_o[35][31]_i_3_n_0\,
- O => \data_rw_o[35][31]_i_2_n_0\
- );
-\data_rw_o[35][31]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => sel0(2),
- I1 => sel0(4),
- O => \data_rw_o[35][31]_i_3_n_0\
- );
-\data_rw_o[35][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[35][31]_i_2_n_0\,
- O => \data_rw_o[35][7]_i_1_n_0\
- );
-\data_rw_o[3][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[3][31]_i_3_n_0\,
- O => \data_rw_o[3][15]_i_1_n_0\
- );
-\data_rw_o[3][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[3][31]_i_3_n_0\,
- O => \data_rw_o[3][23]_i_1_n_0\
- );
-\data_rw_o[3][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[3][31]_i_3_n_0\,
- O => \data_rw_o[3][31]_i_1_n_0\
- );
-\data_rw_o[3][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0F001F1F0F001010"
- )
- port map (
- I0 => sel0(5),
- I1 => sel0(4),
- I2 => sel0(7),
- I3 => \data_rw_o[3][31]_i_4_n_0\,
- I4 => sel0(6),
- I5 => \data_rw_o[3][31]_i_5_n_0\,
- O => \data_rw_o[3][31]_i_2_n_0\
- );
-\data_rw_o[3][31]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFDFFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(2),
- I2 => sel0(3),
- I3 => sel0(0),
- I4 => sel0(1),
- I5 => \data_rw_o[3][31]_i_7_n_0\,
- O => \data_rw_o[3][31]_i_3_n_0\
- );
-\data_rw_o[3][31]_i_4\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFF0037F"
- )
- port map (
- I0 => sel0(1),
- I1 => sel0(2),
- I2 => sel0(3),
- I3 => sel0(4),
- I4 => sel0(5),
- O => \data_rw_o[3][31]_i_4_n_0\
- );
-\data_rw_o[3][31]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFAA0000AFBF"
- )
- port map (
- I0 => sel0(2),
- I1 => sel0(0),
- I2 => sel0(1),
- I3 => sel0(3),
- I4 => sel0(4),
- I5 => sel0(5),
- O => \data_rw_o[3][31]_i_5_n_0\
- );
-\data_rw_o[3][31]_i_6\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"80000000"
- )
- port map (
- I0 => \^s00_axi_awready\,
- I1 => \axi_bresp[1]_i_3_n_0\,
- I2 => \^s00_axi_wready\,
- I3 => s00_axi_wvalid,
- I4 => s00_axi_awvalid,
- O => \data_rw_o[0]1\
- );
-\data_rw_o[3][31]_i_7\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => sel0(7),
- I1 => sel0(6),
- I2 => sel0(4),
- I3 => sel0(5),
- O => \data_rw_o[3][31]_i_7_n_0\
- );
-\data_rw_o[3][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[3][31]_i_3_n_0\,
- O => \data_rw_o[3][7]_i_1_n_0\
- );
-\data_rw_o[78][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[78][31]_i_2_n_0\,
- O => \data_rw_o[78][15]_i_1_n_0\
- );
-\data_rw_o[78][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[78][31]_i_2_n_0\,
- O => \data_rw_o[78][23]_i_1_n_0\
- );
-\data_rw_o[78][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[78][31]_i_2_n_0\,
- O => \data_rw_o[78][31]_i_1_n_0\
- );
-\data_rw_o[78][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFFFD"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[78][31]_i_3_n_0\,
- I2 => \data_rw_o[78][31]_i_4_n_0\,
- I3 => sel0(7),
- I4 => sel0(0),
- I5 => \data_rw_o[78][31]_i_5_n_0\,
- O => \data_rw_o[78][31]_i_2_n_0\
- );
-\data_rw_o[78][31]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"7"
- )
- port map (
- I0 => sel0(6),
- I1 => sel0(2),
- O => \data_rw_o[78][31]_i_3_n_0\
- );
-\data_rw_o[78][31]_i_4\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"7"
- )
- port map (
- I0 => sel0(1),
- I1 => sel0(3),
- O => \data_rw_o[78][31]_i_4_n_0\
- );
-\data_rw_o[78][31]_i_5\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => sel0(5),
- I1 => sel0(4),
- O => \data_rw_o[78][31]_i_5_n_0\
- );
-\data_rw_o[78][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[78][31]_i_2_n_0\,
- O => \data_rw_o[78][7]_i_1_n_0\
- );
-\data_rw_o[79][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[79][31]_i_2_n_0\,
- O => \data_rw_o[79][15]_i_1_n_0\
- );
-\data_rw_o[79][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[79][31]_i_2_n_0\,
- O => \data_rw_o[79][23]_i_1_n_0\
- );
-\data_rw_o[79][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[79][31]_i_2_n_0\,
- O => \data_rw_o[79][31]_i_1_n_0\
- );
-\data_rw_o[79][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFDFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[31][31]_i_3_n_0\,
- I2 => sel0(7),
- I3 => sel0(4),
- I4 => sel0(6),
- I5 => sel0(5),
- O => \data_rw_o[79][31]_i_2_n_0\
- );
-\data_rw_o[79][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[79][31]_i_2_n_0\,
- O => \data_rw_o[79][7]_i_1_n_0\
- );
-\data_rw_o[84][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[84][31]_i_2_n_0\,
- O => \data_rw_o[84][15]_i_1_n_0\
- );
-\data_rw_o[84][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[84][31]_i_2_n_0\,
- O => \data_rw_o[84][23]_i_1_n_0\
- );
-\data_rw_o[84][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[84][31]_i_2_n_0\,
- O => \data_rw_o[84][31]_i_1_n_0\
- );
-\data_rw_o[84][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFF7FFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(6),
- I2 => sel0(3),
- I3 => sel0(4),
- I4 => sel0(2),
- I5 => \data_rw_o[84][31]_i_3_n_0\,
- O => \data_rw_o[84][31]_i_2_n_0\
- );
-\data_rw_o[84][31]_i_3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => sel0(7),
- I1 => sel0(1),
- I2 => sel0(0),
- I3 => sel0(5),
- O => \data_rw_o[84][31]_i_3_n_0\
- );
-\data_rw_o[84][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[84][31]_i_2_n_0\,
- O => \data_rw_o[84][7]_i_1_n_0\
- );
-\data_rw_o[85][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[85][31]_i_2_n_0\,
- O => \data_rw_o[85][15]_i_1_n_0\
- );
-\data_rw_o[85][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[85][31]_i_2_n_0\,
- O => \data_rw_o[85][23]_i_1_n_0\
- );
-\data_rw_o[85][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[85][31]_i_2_n_0\,
- O => \data_rw_o[85][31]_i_1_n_0\
- );
-\data_rw_o[85][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFFFD"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[78][31]_i_3_n_0\,
- I2 => \data_rw_o[85][31]_i_3_n_0\,
- I3 => \data_rw_o[85][31]_i_4_n_0\,
- I4 => sel0(1),
- I5 => sel0(5),
- O => \data_rw_o[85][31]_i_2_n_0\
- );
-\data_rw_o[85][31]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"7"
- )
- port map (
- I0 => sel0(4),
- I1 => sel0(0),
- O => \data_rw_o[85][31]_i_3_n_0\
- );
-\data_rw_o[85][31]_i_4\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => sel0(3),
- I1 => sel0(7),
- O => \data_rw_o[85][31]_i_4_n_0\
- );
-\data_rw_o[85][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[85][31]_i_2_n_0\,
- O => \data_rw_o[85][7]_i_1_n_0\
- );
-\data_rw_o[86][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[86][31]_i_2_n_0\,
- O => \data_rw_o[86][15]_i_1_n_0\
- );
-\data_rw_o[86][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[86][31]_i_2_n_0\,
- O => \data_rw_o[86][23]_i_1_n_0\
- );
-\data_rw_o[86][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[86][31]_i_2_n_0\,
- O => \data_rw_o[86][31]_i_1_n_0\
- );
-\data_rw_o[86][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFDFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[78][31]_i_3_n_0\,
- I2 => sel0(4),
- I3 => sel0(1),
- I4 => \data_rw_o[85][31]_i_4_n_0\,
- I5 => \data_rw_o[86][31]_i_3_n_0\,
- O => \data_rw_o[86][31]_i_2_n_0\
- );
-\data_rw_o[86][31]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => sel0(5),
- I1 => sel0(0),
- O => \data_rw_o[86][31]_i_3_n_0\
- );
-\data_rw_o[86][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[86][31]_i_2_n_0\,
- O => \data_rw_o[86][7]_i_1_n_0\
- );
-\data_rw_o[87][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[87][31]_i_2_n_0\,
- O => \data_rw_o[87][15]_i_1_n_0\
- );
-\data_rw_o[87][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[87][31]_i_2_n_0\,
- O => \data_rw_o[87][23]_i_1_n_0\
- );
-\data_rw_o[87][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[87][31]_i_2_n_0\,
- O => \data_rw_o[87][31]_i_1_n_0\
- );
-\data_rw_o[87][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFF7F"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(2),
- I2 => sel0(4),
- I3 => \data_rw_o[23][31]_i_4_n_0\,
- I4 => \data_rw_o[85][31]_i_4_n_0\,
- I5 => \data_rw_o[87][31]_i_3_n_0\,
- O => \data_rw_o[87][31]_i_2_n_0\
- );
-\data_rw_o[87][31]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => sel0(5),
- I1 => sel0(6),
- O => \data_rw_o[87][31]_i_3_n_0\
- );
-\data_rw_o[87][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[87][31]_i_2_n_0\,
- O => \data_rw_o[87][7]_i_1_n_0\
- );
-\data_rw_o[88][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[88][31]_i_2_n_0\,
- O => \data_rw_o[88][15]_i_1_n_0\
- );
-\data_rw_o[88][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[88][31]_i_2_n_0\,
- O => \data_rw_o[88][23]_i_1_n_0\
- );
-\data_rw_o[88][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[88][31]_i_2_n_0\,
- O => \data_rw_o[88][31]_i_1_n_0\
- );
-\data_rw_o[88][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFF7FFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(6),
- I2 => sel0(1),
- I3 => sel0(4),
- I4 => sel0(3),
- I5 => \data_rw_o[88][31]_i_3_n_0\,
- O => \data_rw_o[88][31]_i_2_n_0\
- );
-\data_rw_o[88][31]_i_3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => sel0(7),
- I1 => sel0(2),
- I2 => sel0(0),
- I3 => sel0(5),
- O => \data_rw_o[88][31]_i_3_n_0\
- );
-\data_rw_o[88][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[88][31]_i_2_n_0\,
- O => \data_rw_o[88][7]_i_1_n_0\
- );
-\data_rw_o[89][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[89][31]_i_2_n_0\,
- O => \data_rw_o[89][15]_i_1_n_0\
- );
-\data_rw_o[89][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[89][31]_i_2_n_0\,
- O => \data_rw_o[89][23]_i_1_n_0\
- );
-\data_rw_o[89][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[89][31]_i_2_n_0\,
- O => \data_rw_o[89][31]_i_1_n_0\
- );
-\data_rw_o[89][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFF7F"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(3),
- I2 => sel0(6),
- I3 => \data_rw_o[85][31]_i_3_n_0\,
- I4 => \data_rw_o[89][31]_i_3_n_0\,
- I5 => \data_rw_o[89][31]_i_4_n_0\,
- O => \data_rw_o[89][31]_i_2_n_0\
- );
-\data_rw_o[89][31]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => sel0(2),
- I1 => sel0(7),
- O => \data_rw_o[89][31]_i_3_n_0\
- );
-\data_rw_o[89][31]_i_4\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => sel0(5),
- I1 => sel0(1),
- O => \data_rw_o[89][31]_i_4_n_0\
- );
-\data_rw_o[89][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[89][31]_i_2_n_0\,
- O => \data_rw_o[89][7]_i_1_n_0\
- );
-\data_rw_o[90][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[90][31]_i_2_n_0\,
- O => \data_rw_o[90][15]_i_1_n_0\
- );
-\data_rw_o[90][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[90][31]_i_2_n_0\,
- O => \data_rw_o[90][23]_i_1_n_0\
- );
-\data_rw_o[90][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[90][31]_i_2_n_0\,
- O => \data_rw_o[90][31]_i_1_n_0\
- );
-\data_rw_o[90][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFF7FFFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(3),
- I2 => sel0(6),
- I3 => sel0(4),
- I4 => sel0(1),
- I5 => \data_rw_o[88][31]_i_3_n_0\,
- O => \data_rw_o[90][31]_i_2_n_0\
- );
-\data_rw_o[90][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[90][31]_i_2_n_0\,
- O => \data_rw_o[90][7]_i_1_n_0\
- );
-\data_rw_o[91][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[91][31]_i_2_n_0\,
- O => \data_rw_o[91][15]_i_1_n_0\
- );
-\data_rw_o[91][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[91][31]_i_2_n_0\,
- O => \data_rw_o[91][23]_i_1_n_0\
- );
-\data_rw_o[91][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[91][31]_i_2_n_0\,
- O => \data_rw_o[91][31]_i_1_n_0\
- );
-\data_rw_o[91][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFF7F"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(4),
- I2 => sel0(3),
- I3 => \data_rw_o[23][31]_i_4_n_0\,
- I4 => \data_rw_o[89][31]_i_3_n_0\,
- I5 => \data_rw_o[87][31]_i_3_n_0\,
- O => \data_rw_o[91][31]_i_2_n_0\
- );
-\data_rw_o[91][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[91][31]_i_2_n_0\,
- O => \data_rw_o[91][7]_i_1_n_0\
- );
-\data_rw_o[92][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[92][31]_i_2_n_0\,
- O => \data_rw_o[92][15]_i_1_n_0\
- );
-\data_rw_o[92][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[92][31]_i_2_n_0\,
- O => \data_rw_o[92][23]_i_1_n_0\
- );
-\data_rw_o[92][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[92][31]_i_2_n_0\,
- O => \data_rw_o[92][31]_i_1_n_0\
- );
-\data_rw_o[92][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFF7FFFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(2),
- I2 => sel0(6),
- I3 => sel0(4),
- I4 => sel0(3),
- I5 => \data_rw_o[84][31]_i_3_n_0\,
- O => \data_rw_o[92][31]_i_2_n_0\
- );
-\data_rw_o[92][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[92][31]_i_2_n_0\,
- O => \data_rw_o[92][7]_i_1_n_0\
- );
-\data_rw_o[93][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[93][31]_i_2_n_0\,
- O => \data_rw_o[93][15]_i_1_n_0\
- );
-\data_rw_o[93][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[93][31]_i_2_n_0\,
- O => \data_rw_o[93][23]_i_1_n_0\
- );
-\data_rw_o[93][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[93][31]_i_2_n_0\,
- O => \data_rw_o[93][31]_i_1_n_0\
- );
-\data_rw_o[93][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFFFD"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[93][31]_i_3_n_0\,
- I2 => \data_rw_o[85][31]_i_3_n_0\,
- I3 => sel0(7),
- I4 => sel0(1),
- I5 => \data_rw_o[87][31]_i_3_n_0\,
- O => \data_rw_o[93][31]_i_2_n_0\
- );
-\data_rw_o[93][31]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"7"
- )
- port map (
- I0 => sel0(3),
- I1 => sel0(2),
- O => \data_rw_o[93][31]_i_3_n_0\
- );
-\data_rw_o[93][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[93][31]_i_2_n_0\,
- O => \data_rw_o[93][7]_i_1_n_0\
- );
-\data_rw_o[94][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[94][31]_i_2_n_0\,
- O => \data_rw_o[94][15]_i_1_n_0\
- );
-\data_rw_o[94][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[94][31]_i_2_n_0\,
- O => \data_rw_o[94][23]_i_1_n_0\
- );
-\data_rw_o[94][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[94][31]_i_2_n_0\,
- O => \data_rw_o[94][31]_i_1_n_0\
- );
-\data_rw_o[94][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFFFD"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[93][31]_i_3_n_0\,
- I2 => \data_rw_o[94][31]_i_3_n_0\,
- I3 => sel0(7),
- I4 => sel0(0),
- I5 => \data_rw_o[87][31]_i_3_n_0\,
- O => \data_rw_o[94][31]_i_2_n_0\
- );
-\data_rw_o[94][31]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"7"
- )
- port map (
- I0 => sel0(1),
- I1 => sel0(4),
- O => \data_rw_o[94][31]_i_3_n_0\
- );
-\data_rw_o[94][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[94][31]_i_2_n_0\,
- O => \data_rw_o[94][7]_i_1_n_0\
- );
-\data_rw_o[95][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[95][31]_i_2_n_0\,
- O => \data_rw_o[95][15]_i_1_n_0\
- );
-\data_rw_o[95][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[95][31]_i_2_n_0\,
- O => \data_rw_o[95][23]_i_1_n_0\
- );
-\data_rw_o[95][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[95][31]_i_2_n_0\,
- O => \data_rw_o[95][31]_i_1_n_0\
- );
-\data_rw_o[95][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFDFFFFFFFFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[31][31]_i_3_n_0\,
- I2 => sel0(7),
- I3 => sel0(5),
- I4 => sel0(4),
- I5 => sel0(6),
- O => \data_rw_o[95][31]_i_2_n_0\
- );
-\data_rw_o[95][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[95][31]_i_2_n_0\,
- O => \data_rw_o[95][7]_i_1_n_0\
- );
-\data_rw_o[96][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[96][31]_i_2_n_0\,
- O => \data_rw_o[96][15]_i_1_n_0\
- );
-\data_rw_o[96][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[96][31]_i_2_n_0\,
- O => \data_rw_o[96][23]_i_1_n_0\
- );
-\data_rw_o[96][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[96][31]_i_2_n_0\,
- O => \data_rw_o[96][31]_i_1_n_0\
- );
-\data_rw_o[96][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFDFFFFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => sel0(2),
- I2 => sel0(3),
- I3 => sel0(5),
- I4 => sel0(6),
- I5 => \data_rw_o[96][31]_i_3_n_0\,
- O => \data_rw_o[96][31]_i_2_n_0\
- );
-\data_rw_o[96][31]_i_3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => sel0(7),
- I1 => sel0(1),
- I2 => sel0(4),
- I3 => sel0(0),
- O => \data_rw_o[96][31]_i_3_n_0\
- );
-\data_rw_o[96][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[96][31]_i_2_n_0\,
- O => \data_rw_o[96][7]_i_1_n_0\
- );
-\data_rw_o[97][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[97][31]_i_2_n_0\,
- O => \data_rw_o[97][15]_i_1_n_0\
- );
-\data_rw_o[97][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[97][31]_i_2_n_0\,
- O => \data_rw_o[97][23]_i_1_n_0\
- );
-\data_rw_o[97][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[97][31]_i_2_n_0\,
- O => \data_rw_o[97][31]_i_1_n_0\
- );
-\data_rw_o[97][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFFFD"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[97][31]_i_3_n_0\,
- I2 => \data_rw_o[33][31]_i_3_n_0\,
- I3 => \data_rw_o[89][31]_i_3_n_0\,
- I4 => sel0(4),
- I5 => sel0(1),
- O => \data_rw_o[97][31]_i_2_n_0\
- );
-\data_rw_o[97][31]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => sel0(3),
- I1 => sel0(6),
- O => \data_rw_o[97][31]_i_3_n_0\
- );
-\data_rw_o[97][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[97][31]_i_2_n_0\,
- O => \data_rw_o[97][7]_i_1_n_0\
- );
-\data_rw_o[98][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[98][31]_i_2_n_0\,
- O => \data_rw_o[98][15]_i_1_n_0\
- );
-\data_rw_o[98][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[98][31]_i_2_n_0\,
- O => \data_rw_o[98][23]_i_1_n_0\
- );
-\data_rw_o[98][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[98][31]_i_2_n_0\,
- O => \data_rw_o[98][31]_i_1_n_0\
- );
-\data_rw_o[98][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFDFFF"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[97][31]_i_3_n_0\,
- I2 => sel0(5),
- I3 => sel0(1),
- I4 => \data_rw_o[89][31]_i_3_n_0\,
- I5 => \data_rw_o[32][31]_i_4_n_0\,
- O => \data_rw_o[98][31]_i_2_n_0\
- );
-\data_rw_o[98][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[98][31]_i_2_n_0\,
- O => \data_rw_o[98][7]_i_1_n_0\
- );
-\data_rw_o[99][15]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(1),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[99][31]_i_2_n_0\,
- O => \data_rw_o[99][15]_i_1_n_0\
- );
-\data_rw_o[99][23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(2),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[99][31]_i_2_n_0\,
- O => \data_rw_o[99][23]_i_1_n_0\
- );
-\data_rw_o[99][31]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(3),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[99][31]_i_2_n_0\,
- O => \data_rw_o[99][31]_i_1_n_0\
- );
-\data_rw_o[99][31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFFFFD"
- )
- port map (
- I0 => \data_rw_o[0]1\,
- I1 => \data_rw_o[99][31]_i_3_n_0\,
- I2 => \data_rw_o[23][31]_i_4_n_0\,
- I3 => \data_rw_o[85][31]_i_4_n_0\,
- I4 => sel0(4),
- I5 => sel0(2),
- O => \data_rw_o[99][31]_i_2_n_0\
- );
-\data_rw_o[99][31]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"7"
- )
- port map (
- I0 => sel0(6),
- I1 => sel0(5),
- O => \data_rw_o[99][31]_i_3_n_0\
- );
-\data_rw_o[99][7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"02"
- )
- port map (
- I0 => s00_axi_wstrb(0),
- I1 => \data_rw_o[3][31]_i_2_n_0\,
- I2 => \data_rw_o[99][31]_i_2_n_0\,
- O => \data_rw_o[99][7]_i_1_n_0\
- );
-\data_rw_o_reg[100][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[4].[0].s_reqs_reg[16][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[100][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[4].[0].s_reqs_reg[16][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[100][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[4].[0].s_reqs_reg[16][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[100][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[100][12]\,
- R => rst_i
- );
-\data_rw_o_reg[100][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[100][13]\,
- R => rst_i
- );
-\data_rw_o_reg[100][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[100][14]\,
- R => rst_i
- );
-\data_rw_o_reg[100][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[100][15]\,
- R => rst_i
- );
-\data_rw_o_reg[100][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[100][16]\,
- R => rst_i
- );
-\data_rw_o_reg[100][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[100][17]\,
- R => rst_i
- );
-\data_rw_o_reg[100][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[100][18]\,
- R => rst_i
- );
-\data_rw_o_reg[100][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[100][19]\,
- R => rst_i
- );
-\data_rw_o_reg[100][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[4].[0].s_reqs_reg[16][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[100][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[100][20]\,
- R => rst_i
- );
-\data_rw_o_reg[100][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[100][21]\,
- R => rst_i
- );
-\data_rw_o_reg[100][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[100][22]\,
- R => rst_i
- );
-\data_rw_o_reg[100][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[100][23]\,
- R => rst_i
- );
-\data_rw_o_reg[100][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[100][24]\,
- R => rst_i
- );
-\data_rw_o_reg[100][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[100][25]\,
- R => rst_i
- );
-\data_rw_o_reg[100][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[100][26]\,
- R => rst_i
- );
-\data_rw_o_reg[100][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[100][27]\,
- R => rst_i
- );
-\data_rw_o_reg[100][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[100][28]\,
- R => rst_i
- );
-\data_rw_o_reg[100][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[100][29]\,
- R => rst_i
- );
-\data_rw_o_reg[100][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[4].[0].s_reqs_reg[16][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[100][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[100][30]\,
- R => rst_i
- );
-\data_rw_o_reg[100][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[100][31]\,
- R => rst_i
- );
-\data_rw_o_reg[100][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[4].[0].s_reqs_reg[16][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[100][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[4].[0].s_reqs_reg[16][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[100][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[4].[0].s_reqs_reg[16][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[100][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[4].[0].s_reqs_reg[16][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[100][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[4].[0].s_reqs_reg[16][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[100][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[4].[0].s_reqs_reg[16][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[100][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[100][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[4].[0].s_reqs_reg[16][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[101][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[4].[1].s_reqs_reg[17][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[101][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[4].[1].s_reqs_reg[17][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[101][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[4].[1].s_reqs_reg[17][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[101][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[101][12]\,
- R => rst_i
- );
-\data_rw_o_reg[101][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[101][13]\,
- R => rst_i
- );
-\data_rw_o_reg[101][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[101][14]\,
- R => rst_i
- );
-\data_rw_o_reg[101][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[101][15]\,
- R => rst_i
- );
-\data_rw_o_reg[101][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[101][16]\,
- R => rst_i
- );
-\data_rw_o_reg[101][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[101][17]\,
- R => rst_i
- );
-\data_rw_o_reg[101][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[101][18]\,
- R => rst_i
- );
-\data_rw_o_reg[101][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[101][19]\,
- R => rst_i
- );
-\data_rw_o_reg[101][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[4].[1].s_reqs_reg[17][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[101][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[101][20]\,
- R => rst_i
- );
-\data_rw_o_reg[101][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[101][21]\,
- R => rst_i
- );
-\data_rw_o_reg[101][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[101][22]\,
- R => rst_i
- );
-\data_rw_o_reg[101][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[101][23]\,
- R => rst_i
- );
-\data_rw_o_reg[101][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[101][24]\,
- R => rst_i
- );
-\data_rw_o_reg[101][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[101][25]\,
- R => rst_i
- );
-\data_rw_o_reg[101][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[101][26]\,
- R => rst_i
- );
-\data_rw_o_reg[101][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[101][27]\,
- R => rst_i
- );
-\data_rw_o_reg[101][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[101][28]\,
- R => rst_i
- );
-\data_rw_o_reg[101][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[101][29]\,
- R => rst_i
- );
-\data_rw_o_reg[101][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[4].[1].s_reqs_reg[17][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[101][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[101][30]\,
- R => rst_i
- );
-\data_rw_o_reg[101][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[101][31]\,
- R => rst_i
- );
-\data_rw_o_reg[101][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[4].[1].s_reqs_reg[17][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[101][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[4].[1].s_reqs_reg[17][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[101][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[4].[1].s_reqs_reg[17][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[101][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[4].[1].s_reqs_reg[17][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[101][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[4].[1].s_reqs_reg[17][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[101][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[4].[1].s_reqs_reg[17][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[101][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[101][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[4].[1].s_reqs_reg[17][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[102][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[4].[2].s_reqs_reg[18][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[102][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[4].[2].s_reqs_reg[18][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[102][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[4].[2].s_reqs_reg[18][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[102][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[102][12]\,
- R => rst_i
- );
-\data_rw_o_reg[102][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[102][13]\,
- R => rst_i
- );
-\data_rw_o_reg[102][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[102][14]\,
- R => rst_i
- );
-\data_rw_o_reg[102][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[102][15]\,
- R => rst_i
- );
-\data_rw_o_reg[102][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[102][16]\,
- R => rst_i
- );
-\data_rw_o_reg[102][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[102][17]\,
- R => rst_i
- );
-\data_rw_o_reg[102][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[102][18]\,
- R => rst_i
- );
-\data_rw_o_reg[102][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[102][19]\,
- R => rst_i
- );
-\data_rw_o_reg[102][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[4].[2].s_reqs_reg[18][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[102][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[102][20]\,
- R => rst_i
- );
-\data_rw_o_reg[102][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[102][21]\,
- R => rst_i
- );
-\data_rw_o_reg[102][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[102][22]\,
- R => rst_i
- );
-\data_rw_o_reg[102][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[102][23]\,
- R => rst_i
- );
-\data_rw_o_reg[102][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[102][24]\,
- R => rst_i
- );
-\data_rw_o_reg[102][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[102][25]\,
- R => rst_i
- );
-\data_rw_o_reg[102][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[102][26]\,
- R => rst_i
- );
-\data_rw_o_reg[102][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[102][27]\,
- R => rst_i
- );
-\data_rw_o_reg[102][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[102][28]\,
- R => rst_i
- );
-\data_rw_o_reg[102][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[102][29]\,
- R => rst_i
- );
-\data_rw_o_reg[102][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[4].[2].s_reqs_reg[18][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[102][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[102][30]\,
- R => rst_i
- );
-\data_rw_o_reg[102][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[102][31]\,
- R => rst_i
- );
-\data_rw_o_reg[102][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[4].[2].s_reqs_reg[18][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[102][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[4].[2].s_reqs_reg[18][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[102][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[4].[2].s_reqs_reg[18][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[102][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[4].[2].s_reqs_reg[18][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[102][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[4].[2].s_reqs_reg[18][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[102][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[4].[2].s_reqs_reg[18][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[102][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[102][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[4].[2].s_reqs_reg[18][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[103][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[4].[3].s_reqs_reg[19][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[103][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[4].[3].s_reqs_reg[19][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[103][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[4].[3].s_reqs_reg[19][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[103][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[103][12]\,
- R => rst_i
- );
-\data_rw_o_reg[103][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[103][13]\,
- R => rst_i
- );
-\data_rw_o_reg[103][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[103][14]\,
- R => rst_i
- );
-\data_rw_o_reg[103][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[103][15]\,
- R => rst_i
- );
-\data_rw_o_reg[103][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[103][16]\,
- R => rst_i
- );
-\data_rw_o_reg[103][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[103][17]\,
- R => rst_i
- );
-\data_rw_o_reg[103][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[103][18]\,
- R => rst_i
- );
-\data_rw_o_reg[103][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[103][19]\,
- R => rst_i
- );
-\data_rw_o_reg[103][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[4].[3].s_reqs_reg[19][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[103][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[103][20]\,
- R => rst_i
- );
-\data_rw_o_reg[103][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[103][21]\,
- R => rst_i
- );
-\data_rw_o_reg[103][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[103][22]\,
- R => rst_i
- );
-\data_rw_o_reg[103][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[103][23]\,
- R => rst_i
- );
-\data_rw_o_reg[103][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[103][24]\,
- R => rst_i
- );
-\data_rw_o_reg[103][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[103][25]\,
- R => rst_i
- );
-\data_rw_o_reg[103][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[103][26]\,
- R => rst_i
- );
-\data_rw_o_reg[103][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[103][27]\,
- R => rst_i
- );
-\data_rw_o_reg[103][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[103][28]\,
- R => rst_i
- );
-\data_rw_o_reg[103][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[103][29]\,
- R => rst_i
- );
-\data_rw_o_reg[103][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[4].[3].s_reqs_reg[19][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[103][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[103][30]\,
- R => rst_i
- );
-\data_rw_o_reg[103][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[103][31]\,
- R => rst_i
- );
-\data_rw_o_reg[103][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[4].[3].s_reqs_reg[19][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[103][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[4].[3].s_reqs_reg[19][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[103][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[4].[3].s_reqs_reg[19][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[103][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[4].[3].s_reqs_reg[19][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[103][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[4].[3].s_reqs_reg[19][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[103][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[4].[3].s_reqs_reg[19][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[103][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[103][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[4].[3].s_reqs_reg[19][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[10][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \data_rw_o_reg_n_0_[10][0]\,
- R => rst_i
- );
-\data_rw_o_reg[10][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \data_rw_o_reg_n_0_[10][10]\,
- R => rst_i
- );
-\data_rw_o_reg[10][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \data_rw_o_reg_n_0_[10][11]\,
- R => rst_i
- );
-\data_rw_o_reg[10][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[10][12]\,
- R => rst_i
- );
-\data_rw_o_reg[10][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[10][13]\,
- R => rst_i
- );
-\data_rw_o_reg[10][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[10][14]\,
- R => rst_i
- );
-\data_rw_o_reg[10][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[10][15]\,
- R => rst_i
- );
-\data_rw_o_reg[10][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[10][16]\,
- R => rst_i
- );
-\data_rw_o_reg[10][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[10][17]\,
- R => rst_i
- );
-\data_rw_o_reg[10][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[10][18]\,
- R => rst_i
- );
-\data_rw_o_reg[10][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[10][19]\,
- R => rst_i
- );
-\data_rw_o_reg[10][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \data_rw_o_reg_n_0_[10][1]\,
- R => rst_i
- );
-\data_rw_o_reg[10][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[10][20]\,
- R => rst_i
- );
-\data_rw_o_reg[10][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[10][21]\,
- R => rst_i
- );
-\data_rw_o_reg[10][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[10][22]\,
- R => rst_i
- );
-\data_rw_o_reg[10][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[10][23]\,
- R => rst_i
- );
-\data_rw_o_reg[10][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[10][24]\,
- R => rst_i
- );
-\data_rw_o_reg[10][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[10][25]\,
- R => rst_i
- );
-\data_rw_o_reg[10][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[10][26]\,
- R => rst_i
- );
-\data_rw_o_reg[10][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[10][27]\,
- R => rst_i
- );
-\data_rw_o_reg[10][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[10][28]\,
- R => rst_i
- );
-\data_rw_o_reg[10][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[10][29]\,
- R => rst_i
- );
-\data_rw_o_reg[10][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \data_rw_o_reg_n_0_[10][2]\,
- R => rst_i
- );
-\data_rw_o_reg[10][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[10][30]\,
- R => rst_i
- );
-\data_rw_o_reg[10][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[10][31]\,
- R => rst_i
- );
-\data_rw_o_reg[10][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \data_rw_o_reg_n_0_[10][3]\,
- R => rst_i
- );
-\data_rw_o_reg[10][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \data_rw_o[10]\(4),
- R => rst_i
- );
-\data_rw_o_reg[10][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \data_rw_o[10]\(5),
- R => rst_i
- );
-\data_rw_o_reg[10][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \data_rw_o[10]\(6),
- R => rst_i
- );
-\data_rw_o_reg[10][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \data_rw_o[10]\(7),
- R => rst_i
- );
-\data_rw_o_reg[10][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \data_rw_o_reg_n_0_[10][8]\,
- R => rst_i
- );
-\data_rw_o_reg[10][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[10][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \data_rw_o_reg_n_0_[10][9]\,
- R => rst_i
- );
-\data_rw_o_reg[11][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \data_rw_o_reg_n_0_[11][0]\,
- R => rst_i
- );
-\data_rw_o_reg[11][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \data_rw_o_reg_n_0_[11][10]\,
- R => rst_i
- );
-\data_rw_o_reg[11][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \data_rw_o_reg_n_0_[11][11]\,
- R => rst_i
- );
-\data_rw_o_reg[11][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[11][12]\,
- R => rst_i
- );
-\data_rw_o_reg[11][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[11][13]\,
- R => rst_i
- );
-\data_rw_o_reg[11][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[11][14]\,
- R => rst_i
- );
-\data_rw_o_reg[11][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[11][15]\,
- R => rst_i
- );
-\data_rw_o_reg[11][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[11][16]\,
- R => rst_i
- );
-\data_rw_o_reg[11][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[11][17]\,
- R => rst_i
- );
-\data_rw_o_reg[11][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[11][18]\,
- R => rst_i
- );
-\data_rw_o_reg[11][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[11][19]\,
- R => rst_i
- );
-\data_rw_o_reg[11][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^v_dout_reg[7]\(0),
- S => rst_i
- );
-\data_rw_o_reg[11][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[11][20]\,
- R => rst_i
- );
-\data_rw_o_reg[11][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[11][21]\,
- R => rst_i
- );
-\data_rw_o_reg[11][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[11][22]\,
- R => rst_i
- );
-\data_rw_o_reg[11][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[11][23]\,
- R => rst_i
- );
-\data_rw_o_reg[11][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[11][24]\,
- R => rst_i
- );
-\data_rw_o_reg[11][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[11][25]\,
- R => rst_i
- );
-\data_rw_o_reg[11][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[11][26]\,
- R => rst_i
- );
-\data_rw_o_reg[11][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[11][27]\,
- R => rst_i
- );
-\data_rw_o_reg[11][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[11][28]\,
- R => rst_i
- );
-\data_rw_o_reg[11][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[11][29]\,
- R => rst_i
- );
-\data_rw_o_reg[11][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^v_dout_reg[7]\(1),
- R => rst_i
- );
-\data_rw_o_reg[11][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[11][30]\,
- R => rst_i
- );
-\data_rw_o_reg[11][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[11][31]\,
- R => rst_i
- );
-\data_rw_o_reg[11][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \data_rw_o_reg_n_0_[11][3]\,
- R => rst_i
- );
-\data_rw_o_reg[11][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \data_rw_o_reg_n_0_[11][4]\,
- R => rst_i
- );
-\data_rw_o_reg[11][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \data_rw_o_reg_n_0_[11][5]\,
- R => rst_i
- );
-\data_rw_o_reg[11][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \data_rw_o_reg_n_0_[11][6]\,
- R => rst_i
- );
-\data_rw_o_reg[11][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^v_dout_reg[7]\(2),
- R => rst_i
- );
-\data_rw_o_reg[11][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \data_rw_o_reg_n_0_[11][8]\,
- R => rst_i
- );
-\data_rw_o_reg[11][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[11][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \data_rw_o_reg_n_0_[11][9]\,
- R => rst_i
- );
-\data_rw_o_reg[16][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[0].[0].s_reqs_reg[0][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[16][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[0].[0].s_reqs_reg[0][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[16][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[0].[0].s_reqs_reg[0][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[16][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[16][12]\,
- R => rst_i
- );
-\data_rw_o_reg[16][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[16][13]\,
- R => rst_i
- );
-\data_rw_o_reg[16][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[16][14]\,
- R => rst_i
- );
-\data_rw_o_reg[16][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[16][15]\,
- R => rst_i
- );
-\data_rw_o_reg[16][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[16][16]\,
- R => rst_i
- );
-\data_rw_o_reg[16][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[16][17]\,
- R => rst_i
- );
-\data_rw_o_reg[16][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[16][18]\,
- R => rst_i
- );
-\data_rw_o_reg[16][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[16][19]\,
- R => rst_i
- );
-\data_rw_o_reg[16][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[0].[0].s_reqs_reg[0][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[16][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[16][20]\,
- R => rst_i
- );
-\data_rw_o_reg[16][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[16][21]\,
- R => rst_i
- );
-\data_rw_o_reg[16][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[16][22]\,
- R => rst_i
- );
-\data_rw_o_reg[16][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[16][23]\,
- R => rst_i
- );
-\data_rw_o_reg[16][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[16][24]\,
- R => rst_i
- );
-\data_rw_o_reg[16][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[16][25]\,
- R => rst_i
- );
-\data_rw_o_reg[16][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[16][26]\,
- R => rst_i
- );
-\data_rw_o_reg[16][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[16][27]\,
- R => rst_i
- );
-\data_rw_o_reg[16][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[16][28]\,
- R => rst_i
- );
-\data_rw_o_reg[16][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[16][29]\,
- R => rst_i
- );
-\data_rw_o_reg[16][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[0].[0].s_reqs_reg[0][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[16][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[16][30]\,
- R => rst_i
- );
-\data_rw_o_reg[16][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[16][31]\,
- R => rst_i
- );
-\data_rw_o_reg[16][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[0].[0].s_reqs_reg[0][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[16][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[0].[0].s_reqs_reg[0][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[16][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[0].[0].s_reqs_reg[0][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[16][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[0].[0].s_reqs_reg[0][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[16][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[0].[0].s_reqs_reg[0][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[16][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[0].[0].s_reqs_reg[0][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[16][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[16][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[0].[0].s_reqs_reg[0][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[17][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[0].[1].s_reqs_reg[1][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[17][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[0].[1].s_reqs_reg[1][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[17][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[0].[1].s_reqs_reg[1][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[17][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[17][12]\,
- R => rst_i
- );
-\data_rw_o_reg[17][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[17][13]\,
- R => rst_i
- );
-\data_rw_o_reg[17][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[17][14]\,
- R => rst_i
- );
-\data_rw_o_reg[17][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[17][15]\,
- R => rst_i
- );
-\data_rw_o_reg[17][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[17][16]\,
- R => rst_i
- );
-\data_rw_o_reg[17][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[17][17]\,
- R => rst_i
- );
-\data_rw_o_reg[17][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[17][18]\,
- R => rst_i
- );
-\data_rw_o_reg[17][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[17][19]\,
- R => rst_i
- );
-\data_rw_o_reg[17][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[0].[1].s_reqs_reg[1][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[17][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[17][20]\,
- R => rst_i
- );
-\data_rw_o_reg[17][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[17][21]\,
- R => rst_i
- );
-\data_rw_o_reg[17][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[17][22]\,
- R => rst_i
- );
-\data_rw_o_reg[17][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[17][23]\,
- R => rst_i
- );
-\data_rw_o_reg[17][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[17][24]\,
- R => rst_i
- );
-\data_rw_o_reg[17][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[17][25]\,
- R => rst_i
- );
-\data_rw_o_reg[17][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[17][26]\,
- R => rst_i
- );
-\data_rw_o_reg[17][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[17][27]\,
- R => rst_i
- );
-\data_rw_o_reg[17][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[17][28]\,
- R => rst_i
- );
-\data_rw_o_reg[17][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[17][29]\,
- R => rst_i
- );
-\data_rw_o_reg[17][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[0].[1].s_reqs_reg[1][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[17][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[17][30]\,
- R => rst_i
- );
-\data_rw_o_reg[17][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[17][31]\,
- R => rst_i
- );
-\data_rw_o_reg[17][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[0].[1].s_reqs_reg[1][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[17][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[0].[1].s_reqs_reg[1][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[17][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[0].[1].s_reqs_reg[1][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[17][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[0].[1].s_reqs_reg[1][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[17][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[0].[1].s_reqs_reg[1][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[17][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[0].[1].s_reqs_reg[1][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[17][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[17][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[0].[1].s_reqs_reg[1][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[18][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[0].[2].s_reqs_reg[2][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[18][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[0].[2].s_reqs_reg[2][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[18][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[0].[2].s_reqs_reg[2][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[18][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[18][12]\,
- R => rst_i
- );
-\data_rw_o_reg[18][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[18][13]\,
- R => rst_i
- );
-\data_rw_o_reg[18][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[18][14]\,
- R => rst_i
- );
-\data_rw_o_reg[18][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[18][15]\,
- R => rst_i
- );
-\data_rw_o_reg[18][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[18][16]\,
- R => rst_i
- );
-\data_rw_o_reg[18][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[18][17]\,
- R => rst_i
- );
-\data_rw_o_reg[18][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[18][18]\,
- R => rst_i
- );
-\data_rw_o_reg[18][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[18][19]\,
- R => rst_i
- );
-\data_rw_o_reg[18][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[0].[2].s_reqs_reg[2][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[18][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[18][20]\,
- R => rst_i
- );
-\data_rw_o_reg[18][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[18][21]\,
- R => rst_i
- );
-\data_rw_o_reg[18][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[18][22]\,
- R => rst_i
- );
-\data_rw_o_reg[18][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[18][23]\,
- R => rst_i
- );
-\data_rw_o_reg[18][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[18][24]\,
- R => rst_i
- );
-\data_rw_o_reg[18][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[18][25]\,
- R => rst_i
- );
-\data_rw_o_reg[18][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[18][26]\,
- R => rst_i
- );
-\data_rw_o_reg[18][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[18][27]\,
- R => rst_i
- );
-\data_rw_o_reg[18][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[18][28]\,
- R => rst_i
- );
-\data_rw_o_reg[18][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[18][29]\,
- R => rst_i
- );
-\data_rw_o_reg[18][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[0].[2].s_reqs_reg[2][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[18][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[18][30]\,
- R => rst_i
- );
-\data_rw_o_reg[18][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[18][31]\,
- R => rst_i
- );
-\data_rw_o_reg[18][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[0].[2].s_reqs_reg[2][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[18][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[0].[2].s_reqs_reg[2][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[18][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[0].[2].s_reqs_reg[2][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[18][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[0].[2].s_reqs_reg[2][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[18][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[0].[2].s_reqs_reg[2][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[18][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[0].[2].s_reqs_reg[2][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[18][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[18][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[0].[2].s_reqs_reg[2][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[19][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^q\(0),
- S => rst_i
- );
-\data_rw_o_reg[19][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^q\(10),
- R => rst_i
- );
-\data_rw_o_reg[19][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^q\(11),
- R => rst_i
- );
-\data_rw_o_reg[19][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[19][12]\,
- R => rst_i
- );
-\data_rw_o_reg[19][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[19][13]\,
- R => rst_i
- );
-\data_rw_o_reg[19][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[19][14]\,
- R => rst_i
- );
-\data_rw_o_reg[19][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[19][15]\,
- R => rst_i
- );
-\data_rw_o_reg[19][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[19][16]\,
- R => rst_i
- );
-\data_rw_o_reg[19][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[19][17]\,
- R => rst_i
- );
-\data_rw_o_reg[19][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[19][18]\,
- R => rst_i
- );
-\data_rw_o_reg[19][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[19][19]\,
- R => rst_i
- );
-\data_rw_o_reg[19][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^q\(1),
- S => rst_i
- );
-\data_rw_o_reg[19][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[19][20]\,
- R => rst_i
- );
-\data_rw_o_reg[19][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[19][21]\,
- R => rst_i
- );
-\data_rw_o_reg[19][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[19][22]\,
- R => rst_i
- );
-\data_rw_o_reg[19][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[19][23]\,
- R => rst_i
- );
-\data_rw_o_reg[19][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[19][24]\,
- R => rst_i
- );
-\data_rw_o_reg[19][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[19][25]\,
- R => rst_i
- );
-\data_rw_o_reg[19][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[19][26]\,
- R => rst_i
- );
-\data_rw_o_reg[19][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[19][27]\,
- R => rst_i
- );
-\data_rw_o_reg[19][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[19][28]\,
- R => rst_i
- );
-\data_rw_o_reg[19][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[19][29]\,
- R => rst_i
- );
-\data_rw_o_reg[19][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^q\(2),
- S => rst_i
- );
-\data_rw_o_reg[19][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[19][30]\,
- R => rst_i
- );
-\data_rw_o_reg[19][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[19][31]\,
- R => rst_i
- );
-\data_rw_o_reg[19][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^q\(3),
- S => rst_i
- );
-\data_rw_o_reg[19][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^q\(4),
- S => rst_i
- );
-\data_rw_o_reg[19][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^q\(5),
- S => rst_i
- );
-\data_rw_o_reg[19][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^q\(6),
- S => rst_i
- );
-\data_rw_o_reg[19][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^q\(7),
- S => rst_i
- );
-\data_rw_o_reg[19][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^q\(8),
- S => rst_i
- );
-\data_rw_o_reg[19][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[19][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^q\(9),
- S => rst_i
- );
-\data_rw_o_reg[20][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[1].[0].s_reqs_reg[4][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[20][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[1].[0].s_reqs_reg[4][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[20][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[1].[0].s_reqs_reg[4][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[20][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[20][12]\,
- R => rst_i
- );
-\data_rw_o_reg[20][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[20][13]\,
- R => rst_i
- );
-\data_rw_o_reg[20][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[20][14]\,
- R => rst_i
- );
-\data_rw_o_reg[20][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[20][15]\,
- R => rst_i
- );
-\data_rw_o_reg[20][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[20][16]\,
- R => rst_i
- );
-\data_rw_o_reg[20][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[20][17]\,
- R => rst_i
- );
-\data_rw_o_reg[20][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[20][18]\,
- R => rst_i
- );
-\data_rw_o_reg[20][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[20][19]\,
- R => rst_i
- );
-\data_rw_o_reg[20][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[1].[0].s_reqs_reg[4][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[20][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[20][20]\,
- R => rst_i
- );
-\data_rw_o_reg[20][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[20][21]\,
- R => rst_i
- );
-\data_rw_o_reg[20][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[20][22]\,
- R => rst_i
- );
-\data_rw_o_reg[20][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[20][23]\,
- R => rst_i
- );
-\data_rw_o_reg[20][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[20][24]\,
- R => rst_i
- );
-\data_rw_o_reg[20][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[20][25]\,
- R => rst_i
- );
-\data_rw_o_reg[20][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[20][26]\,
- R => rst_i
- );
-\data_rw_o_reg[20][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[20][27]\,
- R => rst_i
- );
-\data_rw_o_reg[20][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[20][28]\,
- R => rst_i
- );
-\data_rw_o_reg[20][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[20][29]\,
- R => rst_i
- );
-\data_rw_o_reg[20][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[1].[0].s_reqs_reg[4][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[20][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[20][30]\,
- R => rst_i
- );
-\data_rw_o_reg[20][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[20][31]\,
- R => rst_i
- );
-\data_rw_o_reg[20][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[1].[0].s_reqs_reg[4][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[20][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[1].[0].s_reqs_reg[4][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[20][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[1].[0].s_reqs_reg[4][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[20][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[1].[0].s_reqs_reg[4][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[20][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[1].[0].s_reqs_reg[4][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[20][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[1].[0].s_reqs_reg[4][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[20][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[20][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[1].[0].s_reqs_reg[4][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[21][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[1].[1].s_reqs_reg[5][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[21][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[1].[1].s_reqs_reg[5][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[21][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[1].[1].s_reqs_reg[5][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[21][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[21][12]\,
- R => rst_i
- );
-\data_rw_o_reg[21][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[21][13]\,
- R => rst_i
- );
-\data_rw_o_reg[21][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[21][14]\,
- R => rst_i
- );
-\data_rw_o_reg[21][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[21][15]\,
- R => rst_i
- );
-\data_rw_o_reg[21][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[21][16]\,
- R => rst_i
- );
-\data_rw_o_reg[21][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[21][17]\,
- R => rst_i
- );
-\data_rw_o_reg[21][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[21][18]\,
- R => rst_i
- );
-\data_rw_o_reg[21][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[21][19]\,
- R => rst_i
- );
-\data_rw_o_reg[21][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[1].[1].s_reqs_reg[5][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[21][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[21][20]\,
- R => rst_i
- );
-\data_rw_o_reg[21][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[21][21]\,
- R => rst_i
- );
-\data_rw_o_reg[21][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[21][22]\,
- R => rst_i
- );
-\data_rw_o_reg[21][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[21][23]\,
- R => rst_i
- );
-\data_rw_o_reg[21][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[21][24]\,
- R => rst_i
- );
-\data_rw_o_reg[21][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[21][25]\,
- R => rst_i
- );
-\data_rw_o_reg[21][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[21][26]\,
- R => rst_i
- );
-\data_rw_o_reg[21][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[21][27]\,
- R => rst_i
- );
-\data_rw_o_reg[21][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[21][28]\,
- R => rst_i
- );
-\data_rw_o_reg[21][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[21][29]\,
- R => rst_i
- );
-\data_rw_o_reg[21][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[1].[1].s_reqs_reg[5][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[21][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[21][30]\,
- R => rst_i
- );
-\data_rw_o_reg[21][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[21][31]\,
- R => rst_i
- );
-\data_rw_o_reg[21][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[1].[1].s_reqs_reg[5][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[21][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[1].[1].s_reqs_reg[5][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[21][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[1].[1].s_reqs_reg[5][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[21][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[1].[1].s_reqs_reg[5][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[21][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[1].[1].s_reqs_reg[5][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[21][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[1].[1].s_reqs_reg[5][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[21][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[21][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[1].[1].s_reqs_reg[5][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[22][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[1].[2].s_reqs_reg[6][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[22][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[1].[2].s_reqs_reg[6][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[22][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[1].[2].s_reqs_reg[6][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[22][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[22][12]\,
- R => rst_i
- );
-\data_rw_o_reg[22][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[22][13]\,
- R => rst_i
- );
-\data_rw_o_reg[22][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[22][14]\,
- R => rst_i
- );
-\data_rw_o_reg[22][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[22][15]\,
- R => rst_i
- );
-\data_rw_o_reg[22][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[22][16]\,
- R => rst_i
- );
-\data_rw_o_reg[22][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[22][17]\,
- R => rst_i
- );
-\data_rw_o_reg[22][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[22][18]\,
- R => rst_i
- );
-\data_rw_o_reg[22][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[22][19]\,
- R => rst_i
- );
-\data_rw_o_reg[22][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[1].[2].s_reqs_reg[6][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[22][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[22][20]\,
- R => rst_i
- );
-\data_rw_o_reg[22][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[22][21]\,
- R => rst_i
- );
-\data_rw_o_reg[22][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[22][22]\,
- R => rst_i
- );
-\data_rw_o_reg[22][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[22][23]\,
- R => rst_i
- );
-\data_rw_o_reg[22][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[22][24]\,
- R => rst_i
- );
-\data_rw_o_reg[22][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[22][25]\,
- R => rst_i
- );
-\data_rw_o_reg[22][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[22][26]\,
- R => rst_i
- );
-\data_rw_o_reg[22][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[22][27]\,
- R => rst_i
- );
-\data_rw_o_reg[22][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[22][28]\,
- R => rst_i
- );
-\data_rw_o_reg[22][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[22][29]\,
- R => rst_i
- );
-\data_rw_o_reg[22][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[1].[2].s_reqs_reg[6][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[22][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[22][30]\,
- R => rst_i
- );
-\data_rw_o_reg[22][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[22][31]\,
- R => rst_i
- );
-\data_rw_o_reg[22][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[1].[2].s_reqs_reg[6][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[22][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[1].[2].s_reqs_reg[6][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[22][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[1].[2].s_reqs_reg[6][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[22][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[1].[2].s_reqs_reg[6][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[22][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[1].[2].s_reqs_reg[6][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[22][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[1].[2].s_reqs_reg[6][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[22][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[22][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[1].[2].s_reqs_reg[6][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[23][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[1].[3].s_reqs_reg[7][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[23][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[1].[3].s_reqs_reg[7][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[23][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[1].[3].s_reqs_reg[7][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[23][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[23][12]\,
- R => rst_i
- );
-\data_rw_o_reg[23][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[23][13]\,
- R => rst_i
- );
-\data_rw_o_reg[23][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[23][14]\,
- R => rst_i
- );
-\data_rw_o_reg[23][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[23][15]\,
- R => rst_i
- );
-\data_rw_o_reg[23][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[23][16]\,
- R => rst_i
- );
-\data_rw_o_reg[23][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[23][17]\,
- R => rst_i
- );
-\data_rw_o_reg[23][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[23][18]\,
- R => rst_i
- );
-\data_rw_o_reg[23][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[23][19]\,
- R => rst_i
- );
-\data_rw_o_reg[23][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[1].[3].s_reqs_reg[7][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[23][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[23][20]\,
- R => rst_i
- );
-\data_rw_o_reg[23][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[23][21]\,
- R => rst_i
- );
-\data_rw_o_reg[23][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[23][22]\,
- R => rst_i
- );
-\data_rw_o_reg[23][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[23][23]\,
- R => rst_i
- );
-\data_rw_o_reg[23][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[23][24]\,
- R => rst_i
- );
-\data_rw_o_reg[23][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[23][25]\,
- R => rst_i
- );
-\data_rw_o_reg[23][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[23][26]\,
- R => rst_i
- );
-\data_rw_o_reg[23][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[23][27]\,
- R => rst_i
- );
-\data_rw_o_reg[23][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[23][28]\,
- R => rst_i
- );
-\data_rw_o_reg[23][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[23][29]\,
- R => rst_i
- );
-\data_rw_o_reg[23][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[1].[3].s_reqs_reg[7][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[23][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[23][30]\,
- R => rst_i
- );
-\data_rw_o_reg[23][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[23][31]\,
- R => rst_i
- );
-\data_rw_o_reg[23][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[1].[3].s_reqs_reg[7][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[23][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[1].[3].s_reqs_reg[7][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[23][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[1].[3].s_reqs_reg[7][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[23][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[1].[3].s_reqs_reg[7][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[23][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[1].[3].s_reqs_reg[7][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[23][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[1].[3].s_reqs_reg[7][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[23][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[23][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[1].[3].s_reqs_reg[7][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[24][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[2].[0].s_reqs_reg[8][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[24][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[2].[0].s_reqs_reg[8][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[24][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[2].[0].s_reqs_reg[8][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[24][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[24][12]\,
- R => rst_i
- );
-\data_rw_o_reg[24][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[24][13]\,
- R => rst_i
- );
-\data_rw_o_reg[24][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[24][14]\,
- R => rst_i
- );
-\data_rw_o_reg[24][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[24][15]\,
- R => rst_i
- );
-\data_rw_o_reg[24][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[24][16]\,
- R => rst_i
- );
-\data_rw_o_reg[24][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[24][17]\,
- R => rst_i
- );
-\data_rw_o_reg[24][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[24][18]\,
- R => rst_i
- );
-\data_rw_o_reg[24][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[24][19]\,
- R => rst_i
- );
-\data_rw_o_reg[24][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[2].[0].s_reqs_reg[8][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[24][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[24][20]\,
- R => rst_i
- );
-\data_rw_o_reg[24][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[24][21]\,
- R => rst_i
- );
-\data_rw_o_reg[24][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[24][22]\,
- R => rst_i
- );
-\data_rw_o_reg[24][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[24][23]\,
- R => rst_i
- );
-\data_rw_o_reg[24][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[24][24]\,
- R => rst_i
- );
-\data_rw_o_reg[24][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[24][25]\,
- R => rst_i
- );
-\data_rw_o_reg[24][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[24][26]\,
- R => rst_i
- );
-\data_rw_o_reg[24][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[24][27]\,
- R => rst_i
- );
-\data_rw_o_reg[24][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[24][28]\,
- R => rst_i
- );
-\data_rw_o_reg[24][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[24][29]\,
- R => rst_i
- );
-\data_rw_o_reg[24][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[2].[0].s_reqs_reg[8][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[24][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[24][30]\,
- R => rst_i
- );
-\data_rw_o_reg[24][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[24][31]\,
- R => rst_i
- );
-\data_rw_o_reg[24][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[2].[0].s_reqs_reg[8][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[24][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[2].[0].s_reqs_reg[8][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[24][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[2].[0].s_reqs_reg[8][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[24][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[2].[0].s_reqs_reg[8][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[24][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[2].[0].s_reqs_reg[8][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[24][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[2].[0].s_reqs_reg[8][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[24][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[24][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[2].[0].s_reqs_reg[8][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[25][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[2].[1].s_reqs_reg[9][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[25][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[2].[1].s_reqs_reg[9][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[25][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[2].[1].s_reqs_reg[9][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[25][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[25][12]\,
- R => rst_i
- );
-\data_rw_o_reg[25][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[25][13]\,
- R => rst_i
- );
-\data_rw_o_reg[25][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[25][14]\,
- R => rst_i
- );
-\data_rw_o_reg[25][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[25][15]\,
- R => rst_i
- );
-\data_rw_o_reg[25][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[25][16]\,
- R => rst_i
- );
-\data_rw_o_reg[25][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[25][17]\,
- R => rst_i
- );
-\data_rw_o_reg[25][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[25][18]\,
- R => rst_i
- );
-\data_rw_o_reg[25][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[25][19]\,
- R => rst_i
- );
-\data_rw_o_reg[25][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[2].[1].s_reqs_reg[9][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[25][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[25][20]\,
- R => rst_i
- );
-\data_rw_o_reg[25][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[25][21]\,
- R => rst_i
- );
-\data_rw_o_reg[25][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[25][22]\,
- R => rst_i
- );
-\data_rw_o_reg[25][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[25][23]\,
- R => rst_i
- );
-\data_rw_o_reg[25][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[25][24]\,
- R => rst_i
- );
-\data_rw_o_reg[25][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[25][25]\,
- R => rst_i
- );
-\data_rw_o_reg[25][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[25][26]\,
- R => rst_i
- );
-\data_rw_o_reg[25][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[25][27]\,
- R => rst_i
- );
-\data_rw_o_reg[25][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[25][28]\,
- R => rst_i
- );
-\data_rw_o_reg[25][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[25][29]\,
- R => rst_i
- );
-\data_rw_o_reg[25][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[2].[1].s_reqs_reg[9][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[25][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[25][30]\,
- R => rst_i
- );
-\data_rw_o_reg[25][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[25][31]\,
- R => rst_i
- );
-\data_rw_o_reg[25][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[2].[1].s_reqs_reg[9][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[25][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[2].[1].s_reqs_reg[9][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[25][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[2].[1].s_reqs_reg[9][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[25][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[2].[1].s_reqs_reg[9][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[25][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[2].[1].s_reqs_reg[9][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[25][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[2].[1].s_reqs_reg[9][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[25][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[25][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[2].[1].s_reqs_reg[9][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[26][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[2].[2].s_reqs_reg[10][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[26][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[2].[2].s_reqs_reg[10][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[26][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[2].[2].s_reqs_reg[10][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[26][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[26][12]\,
- R => rst_i
- );
-\data_rw_o_reg[26][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[26][13]\,
- R => rst_i
- );
-\data_rw_o_reg[26][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[26][14]\,
- R => rst_i
- );
-\data_rw_o_reg[26][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[26][15]\,
- R => rst_i
- );
-\data_rw_o_reg[26][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[26][16]\,
- R => rst_i
- );
-\data_rw_o_reg[26][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[26][17]\,
- R => rst_i
- );
-\data_rw_o_reg[26][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[26][18]\,
- R => rst_i
- );
-\data_rw_o_reg[26][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[26][19]\,
- R => rst_i
- );
-\data_rw_o_reg[26][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[2].[2].s_reqs_reg[10][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[26][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[26][20]\,
- R => rst_i
- );
-\data_rw_o_reg[26][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[26][21]\,
- R => rst_i
- );
-\data_rw_o_reg[26][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[26][22]\,
- R => rst_i
- );
-\data_rw_o_reg[26][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[26][23]\,
- R => rst_i
- );
-\data_rw_o_reg[26][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[26][24]\,
- R => rst_i
- );
-\data_rw_o_reg[26][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[26][25]\,
- R => rst_i
- );
-\data_rw_o_reg[26][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[26][26]\,
- R => rst_i
- );
-\data_rw_o_reg[26][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[26][27]\,
- R => rst_i
- );
-\data_rw_o_reg[26][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[26][28]\,
- R => rst_i
- );
-\data_rw_o_reg[26][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[26][29]\,
- R => rst_i
- );
-\data_rw_o_reg[26][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[2].[2].s_reqs_reg[10][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[26][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[26][30]\,
- R => rst_i
- );
-\data_rw_o_reg[26][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[26][31]\,
- R => rst_i
- );
-\data_rw_o_reg[26][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[2].[2].s_reqs_reg[10][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[26][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[2].[2].s_reqs_reg[10][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[26][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[2].[2].s_reqs_reg[10][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[26][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[2].[2].s_reqs_reg[10][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[26][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[2].[2].s_reqs_reg[10][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[26][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[2].[2].s_reqs_reg[10][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[26][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[26][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[2].[2].s_reqs_reg[10][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[27][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[2].[3].s_reqs_reg[11][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[27][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[2].[3].s_reqs_reg[11][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[27][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[2].[3].s_reqs_reg[11][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[27][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[27][12]\,
- R => rst_i
- );
-\data_rw_o_reg[27][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[27][13]\,
- R => rst_i
- );
-\data_rw_o_reg[27][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[27][14]\,
- R => rst_i
- );
-\data_rw_o_reg[27][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[27][15]\,
- R => rst_i
- );
-\data_rw_o_reg[27][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[27][16]\,
- R => rst_i
- );
-\data_rw_o_reg[27][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[27][17]\,
- R => rst_i
- );
-\data_rw_o_reg[27][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[27][18]\,
- R => rst_i
- );
-\data_rw_o_reg[27][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[27][19]\,
- R => rst_i
- );
-\data_rw_o_reg[27][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[2].[3].s_reqs_reg[11][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[27][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[27][20]\,
- R => rst_i
- );
-\data_rw_o_reg[27][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[27][21]\,
- R => rst_i
- );
-\data_rw_o_reg[27][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[27][22]\,
- R => rst_i
- );
-\data_rw_o_reg[27][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[27][23]\,
- R => rst_i
- );
-\data_rw_o_reg[27][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[27][24]\,
- R => rst_i
- );
-\data_rw_o_reg[27][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[27][25]\,
- R => rst_i
- );
-\data_rw_o_reg[27][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[27][26]\,
- R => rst_i
- );
-\data_rw_o_reg[27][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[27][27]\,
- R => rst_i
- );
-\data_rw_o_reg[27][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[27][28]\,
- R => rst_i
- );
-\data_rw_o_reg[27][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[27][29]\,
- R => rst_i
- );
-\data_rw_o_reg[27][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[2].[3].s_reqs_reg[11][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[27][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[27][30]\,
- R => rst_i
- );
-\data_rw_o_reg[27][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[27][31]\,
- R => rst_i
- );
-\data_rw_o_reg[27][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[2].[3].s_reqs_reg[11][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[27][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[2].[3].s_reqs_reg[11][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[27][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[2].[3].s_reqs_reg[11][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[27][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[2].[3].s_reqs_reg[11][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[27][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[2].[3].s_reqs_reg[11][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[27][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[2].[3].s_reqs_reg[11][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[27][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[27][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[2].[3].s_reqs_reg[11][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[28][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[3].[0].s_reqs_reg[12][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[28][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[3].[0].s_reqs_reg[12][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[28][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[3].[0].s_reqs_reg[12][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[28][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[28][12]\,
- R => rst_i
- );
-\data_rw_o_reg[28][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[28][13]\,
- R => rst_i
- );
-\data_rw_o_reg[28][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[28][14]\,
- R => rst_i
- );
-\data_rw_o_reg[28][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[28][15]\,
- R => rst_i
- );
-\data_rw_o_reg[28][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[28][16]\,
- R => rst_i
- );
-\data_rw_o_reg[28][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[28][17]\,
- R => rst_i
- );
-\data_rw_o_reg[28][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[28][18]\,
- R => rst_i
- );
-\data_rw_o_reg[28][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[28][19]\,
- R => rst_i
- );
-\data_rw_o_reg[28][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[3].[0].s_reqs_reg[12][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[28][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[28][20]\,
- R => rst_i
- );
-\data_rw_o_reg[28][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[28][21]\,
- R => rst_i
- );
-\data_rw_o_reg[28][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[28][22]\,
- R => rst_i
- );
-\data_rw_o_reg[28][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[28][23]\,
- R => rst_i
- );
-\data_rw_o_reg[28][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[28][24]\,
- R => rst_i
- );
-\data_rw_o_reg[28][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[28][25]\,
- R => rst_i
- );
-\data_rw_o_reg[28][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[28][26]\,
- R => rst_i
- );
-\data_rw_o_reg[28][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[28][27]\,
- R => rst_i
- );
-\data_rw_o_reg[28][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[28][28]\,
- R => rst_i
- );
-\data_rw_o_reg[28][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[28][29]\,
- R => rst_i
- );
-\data_rw_o_reg[28][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[3].[0].s_reqs_reg[12][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[28][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[28][30]\,
- R => rst_i
- );
-\data_rw_o_reg[28][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[28][31]\,
- R => rst_i
- );
-\data_rw_o_reg[28][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[3].[0].s_reqs_reg[12][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[28][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[3].[0].s_reqs_reg[12][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[28][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[3].[0].s_reqs_reg[12][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[28][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[3].[0].s_reqs_reg[12][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[28][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[3].[0].s_reqs_reg[12][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[28][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[3].[0].s_reqs_reg[12][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[28][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[28][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[3].[0].s_reqs_reg[12][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[29][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[3].[1].s_reqs_reg[13][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[29][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[3].[1].s_reqs_reg[13][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[29][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[3].[1].s_reqs_reg[13][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[29][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[29][12]\,
- R => rst_i
- );
-\data_rw_o_reg[29][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[29][13]\,
- R => rst_i
- );
-\data_rw_o_reg[29][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[29][14]\,
- R => rst_i
- );
-\data_rw_o_reg[29][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[29][15]\,
- R => rst_i
- );
-\data_rw_o_reg[29][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[29][16]\,
- R => rst_i
- );
-\data_rw_o_reg[29][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[29][17]\,
- R => rst_i
- );
-\data_rw_o_reg[29][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[29][18]\,
- R => rst_i
- );
-\data_rw_o_reg[29][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[29][19]\,
- R => rst_i
- );
-\data_rw_o_reg[29][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[3].[1].s_reqs_reg[13][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[29][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[29][20]\,
- R => rst_i
- );
-\data_rw_o_reg[29][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[29][21]\,
- R => rst_i
- );
-\data_rw_o_reg[29][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[29][22]\,
- R => rst_i
- );
-\data_rw_o_reg[29][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[29][23]\,
- R => rst_i
- );
-\data_rw_o_reg[29][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[29][24]\,
- R => rst_i
- );
-\data_rw_o_reg[29][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[29][25]\,
- R => rst_i
- );
-\data_rw_o_reg[29][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[29][26]\,
- R => rst_i
- );
-\data_rw_o_reg[29][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[29][27]\,
- R => rst_i
- );
-\data_rw_o_reg[29][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[29][28]\,
- R => rst_i
- );
-\data_rw_o_reg[29][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[29][29]\,
- R => rst_i
- );
-\data_rw_o_reg[29][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[3].[1].s_reqs_reg[13][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[29][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[29][30]\,
- R => rst_i
- );
-\data_rw_o_reg[29][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[29][31]\,
- R => rst_i
- );
-\data_rw_o_reg[29][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[3].[1].s_reqs_reg[13][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[29][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[3].[1].s_reqs_reg[13][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[29][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[3].[1].s_reqs_reg[13][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[29][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[3].[1].s_reqs_reg[13][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[29][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[3].[1].s_reqs_reg[13][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[29][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[3].[1].s_reqs_reg[13][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[29][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[29][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[3].[1].s_reqs_reg[13][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[30][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[3].[2].s_reqs_reg[14][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[30][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[3].[2].s_reqs_reg[14][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[30][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[3].[2].s_reqs_reg[14][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[30][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[30][12]\,
- R => rst_i
- );
-\data_rw_o_reg[30][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[30][13]\,
- R => rst_i
- );
-\data_rw_o_reg[30][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[30][14]\,
- R => rst_i
- );
-\data_rw_o_reg[30][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[30][15]\,
- R => rst_i
- );
-\data_rw_o_reg[30][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[30][16]\,
- R => rst_i
- );
-\data_rw_o_reg[30][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[30][17]\,
- R => rst_i
- );
-\data_rw_o_reg[30][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[30][18]\,
- R => rst_i
- );
-\data_rw_o_reg[30][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[30][19]\,
- R => rst_i
- );
-\data_rw_o_reg[30][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[3].[2].s_reqs_reg[14][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[30][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[30][20]\,
- R => rst_i
- );
-\data_rw_o_reg[30][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[30][21]\,
- R => rst_i
- );
-\data_rw_o_reg[30][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[30][22]\,
- R => rst_i
- );
-\data_rw_o_reg[30][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[30][23]\,
- R => rst_i
- );
-\data_rw_o_reg[30][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[30][24]\,
- R => rst_i
- );
-\data_rw_o_reg[30][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[30][25]\,
- R => rst_i
- );
-\data_rw_o_reg[30][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[30][26]\,
- R => rst_i
- );
-\data_rw_o_reg[30][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[30][27]\,
- R => rst_i
- );
-\data_rw_o_reg[30][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[30][28]\,
- R => rst_i
- );
-\data_rw_o_reg[30][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[30][29]\,
- R => rst_i
- );
-\data_rw_o_reg[30][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[3].[2].s_reqs_reg[14][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[30][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[30][30]\,
- R => rst_i
- );
-\data_rw_o_reg[30][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[30][31]\,
- R => rst_i
- );
-\data_rw_o_reg[30][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[3].[2].s_reqs_reg[14][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[30][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[3].[2].s_reqs_reg[14][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[30][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[3].[2].s_reqs_reg[14][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[30][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[3].[2].s_reqs_reg[14][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[30][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[3].[2].s_reqs_reg[14][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[30][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[3].[2].s_reqs_reg[14][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[30][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[30][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[3].[2].s_reqs_reg[14][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[31][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[3].[3].s_reqs_reg[15][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[31][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[3].[3].s_reqs_reg[15][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[31][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[3].[3].s_reqs_reg[15][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[31][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[31][12]\,
- R => rst_i
- );
-\data_rw_o_reg[31][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[31][13]\,
- R => rst_i
- );
-\data_rw_o_reg[31][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[31][14]\,
- R => rst_i
- );
-\data_rw_o_reg[31][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[31][15]\,
- R => rst_i
- );
-\data_rw_o_reg[31][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[31][16]\,
- R => rst_i
- );
-\data_rw_o_reg[31][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[31][17]\,
- R => rst_i
- );
-\data_rw_o_reg[31][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[31][18]\,
- R => rst_i
- );
-\data_rw_o_reg[31][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[31][19]\,
- R => rst_i
- );
-\data_rw_o_reg[31][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[3].[3].s_reqs_reg[15][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[31][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[31][20]\,
- R => rst_i
- );
-\data_rw_o_reg[31][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[31][21]\,
- R => rst_i
- );
-\data_rw_o_reg[31][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[31][22]\,
- R => rst_i
- );
-\data_rw_o_reg[31][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[31][23]\,
- R => rst_i
- );
-\data_rw_o_reg[31][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[31][24]\,
- R => rst_i
- );
-\data_rw_o_reg[31][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[31][25]\,
- R => rst_i
- );
-\data_rw_o_reg[31][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[31][26]\,
- R => rst_i
- );
-\data_rw_o_reg[31][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[31][27]\,
- R => rst_i
- );
-\data_rw_o_reg[31][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[31][28]\,
- R => rst_i
- );
-\data_rw_o_reg[31][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[31][29]\,
- R => rst_i
- );
-\data_rw_o_reg[31][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[3].[3].s_reqs_reg[15][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[31][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[31][30]\,
- R => rst_i
- );
-\data_rw_o_reg[31][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[31][31]\,
- R => rst_i
- );
-\data_rw_o_reg[31][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[3].[3].s_reqs_reg[15][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[31][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[3].[3].s_reqs_reg[15][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[31][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[3].[3].s_reqs_reg[15][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[31][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[3].[3].s_reqs_reg[15][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[31][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[3].[3].s_reqs_reg[15][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[31][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[3].[3].s_reqs_reg[15][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[31][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[31][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[3].[3].s_reqs_reg[15][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[32][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[4].[0].s_reqs_reg[16][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[32][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[4].[0].s_reqs_reg[16][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[32][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[4].[0].s_reqs_reg[16][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[32][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[32][12]\,
- R => rst_i
- );
-\data_rw_o_reg[32][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[32][13]\,
- R => rst_i
- );
-\data_rw_o_reg[32][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[32][14]\,
- R => rst_i
- );
-\data_rw_o_reg[32][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[32][15]\,
- R => rst_i
- );
-\data_rw_o_reg[32][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[32][16]\,
- R => rst_i
- );
-\data_rw_o_reg[32][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[32][17]\,
- R => rst_i
- );
-\data_rw_o_reg[32][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[32][18]\,
- R => rst_i
- );
-\data_rw_o_reg[32][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[32][19]\,
- R => rst_i
- );
-\data_rw_o_reg[32][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[4].[0].s_reqs_reg[16][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[32][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[32][20]\,
- R => rst_i
- );
-\data_rw_o_reg[32][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[32][21]\,
- R => rst_i
- );
-\data_rw_o_reg[32][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[32][22]\,
- R => rst_i
- );
-\data_rw_o_reg[32][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[32][23]\,
- R => rst_i
- );
-\data_rw_o_reg[32][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[32][24]\,
- R => rst_i
- );
-\data_rw_o_reg[32][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[32][25]\,
- R => rst_i
- );
-\data_rw_o_reg[32][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[32][26]\,
- R => rst_i
- );
-\data_rw_o_reg[32][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[32][27]\,
- R => rst_i
- );
-\data_rw_o_reg[32][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[32][28]\,
- R => rst_i
- );
-\data_rw_o_reg[32][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[32][29]\,
- R => rst_i
- );
-\data_rw_o_reg[32][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[4].[0].s_reqs_reg[16][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[32][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[32][30]\,
- R => rst_i
- );
-\data_rw_o_reg[32][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[32][31]\,
- R => rst_i
- );
-\data_rw_o_reg[32][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[4].[0].s_reqs_reg[16][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[32][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[4].[0].s_reqs_reg[16][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[32][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[4].[0].s_reqs_reg[16][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[32][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[4].[0].s_reqs_reg[16][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[32][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[4].[0].s_reqs_reg[16][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[32][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[4].[0].s_reqs_reg[16][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[32][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[32][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[4].[0].s_reqs_reg[16][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[33][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[4].[1].s_reqs_reg[17][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[33][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[4].[1].s_reqs_reg[17][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[33][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[4].[1].s_reqs_reg[17][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[33][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[33][12]\,
- R => rst_i
- );
-\data_rw_o_reg[33][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[33][13]\,
- R => rst_i
- );
-\data_rw_o_reg[33][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[33][14]\,
- R => rst_i
- );
-\data_rw_o_reg[33][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[33][15]\,
- R => rst_i
- );
-\data_rw_o_reg[33][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[33][16]\,
- R => rst_i
- );
-\data_rw_o_reg[33][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[33][17]\,
- R => rst_i
- );
-\data_rw_o_reg[33][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[33][18]\,
- R => rst_i
- );
-\data_rw_o_reg[33][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[33][19]\,
- R => rst_i
- );
-\data_rw_o_reg[33][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[4].[1].s_reqs_reg[17][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[33][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[33][20]\,
- R => rst_i
- );
-\data_rw_o_reg[33][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[33][21]\,
- R => rst_i
- );
-\data_rw_o_reg[33][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[33][22]\,
- R => rst_i
- );
-\data_rw_o_reg[33][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[33][23]\,
- R => rst_i
- );
-\data_rw_o_reg[33][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[33][24]\,
- R => rst_i
- );
-\data_rw_o_reg[33][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[33][25]\,
- R => rst_i
- );
-\data_rw_o_reg[33][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[33][26]\,
- R => rst_i
- );
-\data_rw_o_reg[33][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[33][27]\,
- R => rst_i
- );
-\data_rw_o_reg[33][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[33][28]\,
- R => rst_i
- );
-\data_rw_o_reg[33][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[33][29]\,
- R => rst_i
- );
-\data_rw_o_reg[33][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[4].[1].s_reqs_reg[17][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[33][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[33][30]\,
- R => rst_i
- );
-\data_rw_o_reg[33][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[33][31]\,
- R => rst_i
- );
-\data_rw_o_reg[33][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[4].[1].s_reqs_reg[17][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[33][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[4].[1].s_reqs_reg[17][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[33][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[4].[1].s_reqs_reg[17][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[33][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[4].[1].s_reqs_reg[17][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[33][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[4].[1].s_reqs_reg[17][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[33][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[4].[1].s_reqs_reg[17][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[33][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[33][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[4].[1].s_reqs_reg[17][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[34][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[4].[2].s_reqs_reg[18][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[34][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[4].[2].s_reqs_reg[18][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[34][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[4].[2].s_reqs_reg[18][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[34][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[34][12]\,
- R => rst_i
- );
-\data_rw_o_reg[34][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[34][13]\,
- R => rst_i
- );
-\data_rw_o_reg[34][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[34][14]\,
- R => rst_i
- );
-\data_rw_o_reg[34][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[34][15]\,
- R => rst_i
- );
-\data_rw_o_reg[34][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[34][16]\,
- R => rst_i
- );
-\data_rw_o_reg[34][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[34][17]\,
- R => rst_i
- );
-\data_rw_o_reg[34][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[34][18]\,
- R => rst_i
- );
-\data_rw_o_reg[34][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[34][19]\,
- R => rst_i
- );
-\data_rw_o_reg[34][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[4].[2].s_reqs_reg[18][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[34][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[34][20]\,
- R => rst_i
- );
-\data_rw_o_reg[34][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[34][21]\,
- R => rst_i
- );
-\data_rw_o_reg[34][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[34][22]\,
- R => rst_i
- );
-\data_rw_o_reg[34][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[34][23]\,
- R => rst_i
- );
-\data_rw_o_reg[34][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[34][24]\,
- R => rst_i
- );
-\data_rw_o_reg[34][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[34][25]\,
- R => rst_i
- );
-\data_rw_o_reg[34][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[34][26]\,
- R => rst_i
- );
-\data_rw_o_reg[34][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[34][27]\,
- R => rst_i
- );
-\data_rw_o_reg[34][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[34][28]\,
- R => rst_i
- );
-\data_rw_o_reg[34][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[34][29]\,
- R => rst_i
- );
-\data_rw_o_reg[34][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[4].[2].s_reqs_reg[18][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[34][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[34][30]\,
- R => rst_i
- );
-\data_rw_o_reg[34][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[34][31]\,
- R => rst_i
- );
-\data_rw_o_reg[34][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[4].[2].s_reqs_reg[18][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[34][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[4].[2].s_reqs_reg[18][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[34][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[4].[2].s_reqs_reg[18][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[34][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[4].[2].s_reqs_reg[18][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[34][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[4].[2].s_reqs_reg[18][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[34][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[4].[2].s_reqs_reg[18][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[34][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[34][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[4].[2].s_reqs_reg[18][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[35][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[4].[3].s_reqs_reg[19][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[35][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[4].[3].s_reqs_reg[19][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[35][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[4].[3].s_reqs_reg[19][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[35][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[35][12]\,
- R => rst_i
- );
-\data_rw_o_reg[35][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[35][13]\,
- R => rst_i
- );
-\data_rw_o_reg[35][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[35][14]\,
- R => rst_i
- );
-\data_rw_o_reg[35][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[35][15]\,
- R => rst_i
- );
-\data_rw_o_reg[35][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[35][16]\,
- R => rst_i
- );
-\data_rw_o_reg[35][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[35][17]\,
- R => rst_i
- );
-\data_rw_o_reg[35][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[35][18]\,
- R => rst_i
- );
-\data_rw_o_reg[35][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[35][19]\,
- R => rst_i
- );
-\data_rw_o_reg[35][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[4].[3].s_reqs_reg[19][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[35][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[35][20]\,
- R => rst_i
- );
-\data_rw_o_reg[35][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[35][21]\,
- R => rst_i
- );
-\data_rw_o_reg[35][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[35][22]\,
- R => rst_i
- );
-\data_rw_o_reg[35][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[35][23]\,
- R => rst_i
- );
-\data_rw_o_reg[35][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[35][24]\,
- R => rst_i
- );
-\data_rw_o_reg[35][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[35][25]\,
- R => rst_i
- );
-\data_rw_o_reg[35][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[35][26]\,
- R => rst_i
- );
-\data_rw_o_reg[35][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[35][27]\,
- R => rst_i
- );
-\data_rw_o_reg[35][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[35][28]\,
- R => rst_i
- );
-\data_rw_o_reg[35][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[35][29]\,
- R => rst_i
- );
-\data_rw_o_reg[35][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[4].[3].s_reqs_reg[19][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[35][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[35][30]\,
- R => rst_i
- );
-\data_rw_o_reg[35][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[35][31]\,
- R => rst_i
- );
-\data_rw_o_reg[35][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[4].[3].s_reqs_reg[19][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[35][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[4].[3].s_reqs_reg[19][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[35][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[4].[3].s_reqs_reg[19][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[35][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[4].[3].s_reqs_reg[19][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[35][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[4].[3].s_reqs_reg[19][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[35][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[4].[3].s_reqs_reg[19][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[35][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[35][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[4].[3].s_reqs_reg[19][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[3][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \data_rw_o[3]\(0),
- S => rst_i
- );
-\data_rw_o_reg[3][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \data_rw_o_reg_n_0_[3][10]\,
- R => rst_i
- );
-\data_rw_o_reg[3][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \data_rw_o_reg_n_0_[3][11]\,
- R => rst_i
- );
-\data_rw_o_reg[3][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[3][12]\,
- R => rst_i
- );
-\data_rw_o_reg[3][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[3][13]\,
- R => rst_i
- );
-\data_rw_o_reg[3][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[3][14]\,
- R => rst_i
- );
-\data_rw_o_reg[3][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[3][15]\,
- R => rst_i
- );
-\data_rw_o_reg[3][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[3][16]\,
- R => rst_i
- );
-\data_rw_o_reg[3][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[3][17]\,
- R => rst_i
- );
-\data_rw_o_reg[3][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[3][18]\,
- R => rst_i
- );
-\data_rw_o_reg[3][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[3][19]\,
- R => rst_i
- );
-\data_rw_o_reg[3][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \data_rw_o[3]\(1),
- R => rst_i
- );
-\data_rw_o_reg[3][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[3][20]\,
- R => rst_i
- );
-\data_rw_o_reg[3][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[3][21]\,
- R => rst_i
- );
-\data_rw_o_reg[3][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[3][22]\,
- R => rst_i
- );
-\data_rw_o_reg[3][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[3][23]\,
- R => rst_i
- );
-\data_rw_o_reg[3][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[3][24]\,
- R => rst_i
- );
-\data_rw_o_reg[3][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[3][25]\,
- R => rst_i
- );
-\data_rw_o_reg[3][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[3][26]\,
- R => rst_i
- );
-\data_rw_o_reg[3][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[3][27]\,
- R => rst_i
- );
-\data_rw_o_reg[3][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[3][28]\,
- R => rst_i
- );
-\data_rw_o_reg[3][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[3][29]\,
- R => rst_i
- );
-\data_rw_o_reg[3][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \data_rw_o_reg_n_0_[3][2]\,
- R => rst_i
- );
-\data_rw_o_reg[3][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[3][30]\,
- R => rst_i
- );
-\data_rw_o_reg[3][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[3][31]\,
- R => rst_i
- );
-\data_rw_o_reg[3][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \data_rw_o_reg_n_0_[3][3]\,
- R => rst_i
- );
-\data_rw_o_reg[3][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \data_rw_o_reg_n_0_[3][4]\,
- R => rst_i
- );
-\data_rw_o_reg[3][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \data_rw_o_reg_n_0_[3][5]\,
- R => rst_i
- );
-\data_rw_o_reg[3][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \data_rw_o_reg_n_0_[3][6]\,
- R => rst_i
- );
-\data_rw_o_reg[3][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \data_rw_o_reg_n_0_[3][7]\,
- R => rst_i
- );
-\data_rw_o_reg[3][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \data_rw_o_reg_n_0_[3][8]\,
- R => rst_i
- );
-\data_rw_o_reg[3][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[3][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \data_rw_o_reg_n_0_[3][9]\,
- R => rst_i
- );
-\data_rw_o_reg[78][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \data_rw_o_reg_n_0_[78][0]\,
- R => rst_i
- );
-\data_rw_o_reg[78][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \data_rw_o_reg_n_0_[78][10]\,
- R => rst_i
- );
-\data_rw_o_reg[78][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \data_rw_o_reg_n_0_[78][11]\,
- R => rst_i
- );
-\data_rw_o_reg[78][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[78][12]\,
- R => rst_i
- );
-\data_rw_o_reg[78][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[78][13]\,
- R => rst_i
- );
-\data_rw_o_reg[78][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[78][14]\,
- R => rst_i
- );
-\data_rw_o_reg[78][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[78][15]\,
- R => rst_i
- );
-\data_rw_o_reg[78][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[78][16]\,
- R => rst_i
- );
-\data_rw_o_reg[78][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[78][17]\,
- R => rst_i
- );
-\data_rw_o_reg[78][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[78][18]\,
- R => rst_i
- );
-\data_rw_o_reg[78][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[78][19]\,
- R => rst_i
- );
-\data_rw_o_reg[78][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \data_rw_o_reg_n_0_[78][1]\,
- R => rst_i
- );
-\data_rw_o_reg[78][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[78][20]\,
- R => rst_i
- );
-\data_rw_o_reg[78][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[78][21]\,
- R => rst_i
- );
-\data_rw_o_reg[78][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[78][22]\,
- R => rst_i
- );
-\data_rw_o_reg[78][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[78][23]\,
- R => rst_i
- );
-\data_rw_o_reg[78][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[78][24]\,
- R => rst_i
- );
-\data_rw_o_reg[78][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[78][25]\,
- R => rst_i
- );
-\data_rw_o_reg[78][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[78][26]\,
- R => rst_i
- );
-\data_rw_o_reg[78][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[78][27]\,
- R => rst_i
- );
-\data_rw_o_reg[78][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[78][28]\,
- R => rst_i
- );
-\data_rw_o_reg[78][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[78][29]\,
- R => rst_i
- );
-\data_rw_o_reg[78][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \data_rw_o_reg_n_0_[78][2]\,
- R => rst_i
- );
-\data_rw_o_reg[78][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[78][30]\,
- R => rst_i
- );
-\data_rw_o_reg[78][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[78][31]\,
- R => rst_i
- );
-\data_rw_o_reg[78][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \data_rw_o_reg_n_0_[78][3]\,
- R => rst_i
- );
-\data_rw_o_reg[78][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \data_rw_o[78]\(4),
- R => rst_i
- );
-\data_rw_o_reg[78][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \data_rw_o[78]\(5),
- R => rst_i
- );
-\data_rw_o_reg[78][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \data_rw_o[78]\(6),
- R => rst_i
- );
-\data_rw_o_reg[78][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \data_rw_o[78]\(7),
- R => rst_i
- );
-\data_rw_o_reg[78][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \data_rw_o_reg_n_0_[78][8]\,
- R => rst_i
- );
-\data_rw_o_reg[78][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[78][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \data_rw_o_reg_n_0_[78][9]\,
- R => rst_i
- );
-\data_rw_o_reg[79][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \data_rw_o_reg_n_0_[79][0]\,
- R => rst_i
- );
-\data_rw_o_reg[79][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \data_rw_o_reg_n_0_[79][10]\,
- R => rst_i
- );
-\data_rw_o_reg[79][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \data_rw_o_reg_n_0_[79][11]\,
- R => rst_i
- );
-\data_rw_o_reg[79][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[79][12]\,
- R => rst_i
- );
-\data_rw_o_reg[79][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[79][13]\,
- R => rst_i
- );
-\data_rw_o_reg[79][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[79][14]\,
- R => rst_i
- );
-\data_rw_o_reg[79][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[79][15]\,
- R => rst_i
- );
-\data_rw_o_reg[79][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[79][16]\,
- R => rst_i
- );
-\data_rw_o_reg[79][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[79][17]\,
- R => rst_i
- );
-\data_rw_o_reg[79][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[79][18]\,
- R => rst_i
- );
-\data_rw_o_reg[79][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[79][19]\,
- R => rst_i
- );
-\data_rw_o_reg[79][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^v_dout_reg[7]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[79][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[79][20]\,
- R => rst_i
- );
-\data_rw_o_reg[79][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[79][21]\,
- R => rst_i
- );
-\data_rw_o_reg[79][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[79][22]\,
- R => rst_i
- );
-\data_rw_o_reg[79][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[79][23]\,
- R => rst_i
- );
-\data_rw_o_reg[79][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[79][24]\,
- R => rst_i
- );
-\data_rw_o_reg[79][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[79][25]\,
- R => rst_i
- );
-\data_rw_o_reg[79][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[79][26]\,
- R => rst_i
- );
-\data_rw_o_reg[79][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[79][27]\,
- R => rst_i
- );
-\data_rw_o_reg[79][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[79][28]\,
- R => rst_i
- );
-\data_rw_o_reg[79][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[79][29]\,
- R => rst_i
- );
-\data_rw_o_reg[79][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^v_dout_reg[7]_0\(1),
- R => rst_i
- );
-\data_rw_o_reg[79][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[79][30]\,
- R => rst_i
- );
-\data_rw_o_reg[79][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[79][31]\,
- R => rst_i
- );
-\data_rw_o_reg[79][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \data_rw_o_reg_n_0_[79][3]\,
- R => rst_i
- );
-\data_rw_o_reg[79][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \data_rw_o_reg_n_0_[79][4]\,
- R => rst_i
- );
-\data_rw_o_reg[79][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \data_rw_o_reg_n_0_[79][5]\,
- R => rst_i
- );
-\data_rw_o_reg[79][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \data_rw_o_reg_n_0_[79][6]\,
- R => rst_i
- );
-\data_rw_o_reg[79][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^v_dout_reg[7]_0\(2),
- R => rst_i
- );
-\data_rw_o_reg[79][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \data_rw_o_reg_n_0_[79][8]\,
- R => rst_i
- );
-\data_rw_o_reg[79][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[79][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \data_rw_o_reg_n_0_[79][9]\,
- R => rst_i
- );
-\data_rw_o_reg[84][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[0].[0].s_reqs_reg[0][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[84][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[0].[0].s_reqs_reg[0][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[84][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[0].[0].s_reqs_reg[0][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[84][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[84][12]\,
- R => rst_i
- );
-\data_rw_o_reg[84][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[84][13]\,
- R => rst_i
- );
-\data_rw_o_reg[84][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[84][14]\,
- R => rst_i
- );
-\data_rw_o_reg[84][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[84][15]\,
- R => rst_i
- );
-\data_rw_o_reg[84][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[84][16]\,
- R => rst_i
- );
-\data_rw_o_reg[84][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[84][17]\,
- R => rst_i
- );
-\data_rw_o_reg[84][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[84][18]\,
- R => rst_i
- );
-\data_rw_o_reg[84][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[84][19]\,
- R => rst_i
- );
-\data_rw_o_reg[84][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[0].[0].s_reqs_reg[0][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[84][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[84][20]\,
- R => rst_i
- );
-\data_rw_o_reg[84][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[84][21]\,
- R => rst_i
- );
-\data_rw_o_reg[84][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[84][22]\,
- R => rst_i
- );
-\data_rw_o_reg[84][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[84][23]\,
- R => rst_i
- );
-\data_rw_o_reg[84][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[84][24]\,
- R => rst_i
- );
-\data_rw_o_reg[84][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[84][25]\,
- R => rst_i
- );
-\data_rw_o_reg[84][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[84][26]\,
- R => rst_i
- );
-\data_rw_o_reg[84][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[84][27]\,
- R => rst_i
- );
-\data_rw_o_reg[84][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[84][28]\,
- R => rst_i
- );
-\data_rw_o_reg[84][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[84][29]\,
- R => rst_i
- );
-\data_rw_o_reg[84][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[0].[0].s_reqs_reg[0][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[84][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[84][30]\,
- R => rst_i
- );
-\data_rw_o_reg[84][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[84][31]\,
- R => rst_i
- );
-\data_rw_o_reg[84][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[0].[0].s_reqs_reg[0][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[84][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[0].[0].s_reqs_reg[0][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[84][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[0].[0].s_reqs_reg[0][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[84][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[0].[0].s_reqs_reg[0][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[84][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[0].[0].s_reqs_reg[0][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[84][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[0].[0].s_reqs_reg[0][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[84][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[84][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[0].[0].s_reqs_reg[0][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[85][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[0].[1].s_reqs_reg[1][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[85][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[0].[1].s_reqs_reg[1][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[85][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[0].[1].s_reqs_reg[1][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[85][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[85][12]\,
- R => rst_i
- );
-\data_rw_o_reg[85][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[85][13]\,
- R => rst_i
- );
-\data_rw_o_reg[85][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[85][14]\,
- R => rst_i
- );
-\data_rw_o_reg[85][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[85][15]\,
- R => rst_i
- );
-\data_rw_o_reg[85][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[85][16]\,
- R => rst_i
- );
-\data_rw_o_reg[85][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[85][17]\,
- R => rst_i
- );
-\data_rw_o_reg[85][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[85][18]\,
- R => rst_i
- );
-\data_rw_o_reg[85][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[85][19]\,
- R => rst_i
- );
-\data_rw_o_reg[85][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[0].[1].s_reqs_reg[1][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[85][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[85][20]\,
- R => rst_i
- );
-\data_rw_o_reg[85][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[85][21]\,
- R => rst_i
- );
-\data_rw_o_reg[85][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[85][22]\,
- R => rst_i
- );
-\data_rw_o_reg[85][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[85][23]\,
- R => rst_i
- );
-\data_rw_o_reg[85][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[85][24]\,
- R => rst_i
- );
-\data_rw_o_reg[85][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[85][25]\,
- R => rst_i
- );
-\data_rw_o_reg[85][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[85][26]\,
- R => rst_i
- );
-\data_rw_o_reg[85][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[85][27]\,
- R => rst_i
- );
-\data_rw_o_reg[85][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[85][28]\,
- R => rst_i
- );
-\data_rw_o_reg[85][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[85][29]\,
- R => rst_i
- );
-\data_rw_o_reg[85][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[0].[1].s_reqs_reg[1][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[85][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[85][30]\,
- R => rst_i
- );
-\data_rw_o_reg[85][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[85][31]\,
- R => rst_i
- );
-\data_rw_o_reg[85][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[0].[1].s_reqs_reg[1][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[85][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[0].[1].s_reqs_reg[1][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[85][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[0].[1].s_reqs_reg[1][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[85][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[0].[1].s_reqs_reg[1][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[85][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[0].[1].s_reqs_reg[1][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[85][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[0].[1].s_reqs_reg[1][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[85][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[85][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[0].[1].s_reqs_reg[1][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[86][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[0].[2].s_reqs_reg[2][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[86][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[0].[2].s_reqs_reg[2][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[86][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[0].[2].s_reqs_reg[2][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[86][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[86][12]\,
- R => rst_i
- );
-\data_rw_o_reg[86][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[86][13]\,
- R => rst_i
- );
-\data_rw_o_reg[86][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[86][14]\,
- R => rst_i
- );
-\data_rw_o_reg[86][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[86][15]\,
- R => rst_i
- );
-\data_rw_o_reg[86][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[86][16]\,
- R => rst_i
- );
-\data_rw_o_reg[86][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[86][17]\,
- R => rst_i
- );
-\data_rw_o_reg[86][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[86][18]\,
- R => rst_i
- );
-\data_rw_o_reg[86][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[86][19]\,
- R => rst_i
- );
-\data_rw_o_reg[86][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[0].[2].s_reqs_reg[2][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[86][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[86][20]\,
- R => rst_i
- );
-\data_rw_o_reg[86][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[86][21]\,
- R => rst_i
- );
-\data_rw_o_reg[86][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[86][22]\,
- R => rst_i
- );
-\data_rw_o_reg[86][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[86][23]\,
- R => rst_i
- );
-\data_rw_o_reg[86][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[86][24]\,
- R => rst_i
- );
-\data_rw_o_reg[86][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[86][25]\,
- R => rst_i
- );
-\data_rw_o_reg[86][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[86][26]\,
- R => rst_i
- );
-\data_rw_o_reg[86][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[86][27]\,
- R => rst_i
- );
-\data_rw_o_reg[86][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[86][28]\,
- R => rst_i
- );
-\data_rw_o_reg[86][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[86][29]\,
- R => rst_i
- );
-\data_rw_o_reg[86][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[0].[2].s_reqs_reg[2][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[86][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[86][30]\,
- R => rst_i
- );
-\data_rw_o_reg[86][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[86][31]\,
- R => rst_i
- );
-\data_rw_o_reg[86][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[0].[2].s_reqs_reg[2][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[86][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[0].[2].s_reqs_reg[2][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[86][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[0].[2].s_reqs_reg[2][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[86][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[0].[2].s_reqs_reg[2][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[86][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[0].[2].s_reqs_reg[2][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[86][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[0].[2].s_reqs_reg[2][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[86][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[86][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[0].[2].s_reqs_reg[2][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[87][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[0].[3].s_reqs_reg[3][value][11]\(0),
- S => rst_i
- );
-\data_rw_o_reg[87][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[0].[3].s_reqs_reg[3][value][11]\(10),
- R => rst_i
- );
-\data_rw_o_reg[87][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[0].[3].s_reqs_reg[3][value][11]\(11),
- R => rst_i
- );
-\data_rw_o_reg[87][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[87][12]\,
- R => rst_i
- );
-\data_rw_o_reg[87][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[87][13]\,
- R => rst_i
- );
-\data_rw_o_reg[87][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[87][14]\,
- R => rst_i
- );
-\data_rw_o_reg[87][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[87][15]\,
- R => rst_i
- );
-\data_rw_o_reg[87][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[87][16]\,
- R => rst_i
- );
-\data_rw_o_reg[87][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[87][17]\,
- R => rst_i
- );
-\data_rw_o_reg[87][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[87][18]\,
- R => rst_i
- );
-\data_rw_o_reg[87][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[87][19]\,
- R => rst_i
- );
-\data_rw_o_reg[87][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[0].[3].s_reqs_reg[3][value][11]\(1),
- S => rst_i
- );
-\data_rw_o_reg[87][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[87][20]\,
- R => rst_i
- );
-\data_rw_o_reg[87][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[87][21]\,
- R => rst_i
- );
-\data_rw_o_reg[87][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[87][22]\,
- R => rst_i
- );
-\data_rw_o_reg[87][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[87][23]\,
- R => rst_i
- );
-\data_rw_o_reg[87][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[87][24]\,
- R => rst_i
- );
-\data_rw_o_reg[87][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[87][25]\,
- R => rst_i
- );
-\data_rw_o_reg[87][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[87][26]\,
- R => rst_i
- );
-\data_rw_o_reg[87][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[87][27]\,
- R => rst_i
- );
-\data_rw_o_reg[87][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[87][28]\,
- R => rst_i
- );
-\data_rw_o_reg[87][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[87][29]\,
- R => rst_i
- );
-\data_rw_o_reg[87][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[0].[3].s_reqs_reg[3][value][11]\(2),
- S => rst_i
- );
-\data_rw_o_reg[87][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[87][30]\,
- R => rst_i
- );
-\data_rw_o_reg[87][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[87][31]\,
- R => rst_i
- );
-\data_rw_o_reg[87][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[0].[3].s_reqs_reg[3][value][11]\(3),
- S => rst_i
- );
-\data_rw_o_reg[87][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[0].[3].s_reqs_reg[3][value][11]\(4),
- S => rst_i
- );
-\data_rw_o_reg[87][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[0].[3].s_reqs_reg[3][value][11]\(5),
- S => rst_i
- );
-\data_rw_o_reg[87][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[0].[3].s_reqs_reg[3][value][11]\(6),
- S => rst_i
- );
-\data_rw_o_reg[87][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[0].[3].s_reqs_reg[3][value][11]\(7),
- S => rst_i
- );
-\data_rw_o_reg[87][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[0].[3].s_reqs_reg[3][value][11]\(8),
- S => rst_i
- );
-\data_rw_o_reg[87][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[87][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[0].[3].s_reqs_reg[3][value][11]\(9),
- S => rst_i
- );
-\data_rw_o_reg[88][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[1].[0].s_reqs_reg[4][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[88][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[1].[0].s_reqs_reg[4][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[88][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[1].[0].s_reqs_reg[4][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[88][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[88][12]\,
- R => rst_i
- );
-\data_rw_o_reg[88][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[88][13]\,
- R => rst_i
- );
-\data_rw_o_reg[88][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[88][14]\,
- R => rst_i
- );
-\data_rw_o_reg[88][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[88][15]\,
- R => rst_i
- );
-\data_rw_o_reg[88][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[88][16]\,
- R => rst_i
- );
-\data_rw_o_reg[88][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[88][17]\,
- R => rst_i
- );
-\data_rw_o_reg[88][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[88][18]\,
- R => rst_i
- );
-\data_rw_o_reg[88][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[88][19]\,
- R => rst_i
- );
-\data_rw_o_reg[88][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[1].[0].s_reqs_reg[4][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[88][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[88][20]\,
- R => rst_i
- );
-\data_rw_o_reg[88][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[88][21]\,
- R => rst_i
- );
-\data_rw_o_reg[88][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[88][22]\,
- R => rst_i
- );
-\data_rw_o_reg[88][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[88][23]\,
- R => rst_i
- );
-\data_rw_o_reg[88][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[88][24]\,
- R => rst_i
- );
-\data_rw_o_reg[88][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[88][25]\,
- R => rst_i
- );
-\data_rw_o_reg[88][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[88][26]\,
- R => rst_i
- );
-\data_rw_o_reg[88][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[88][27]\,
- R => rst_i
- );
-\data_rw_o_reg[88][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[88][28]\,
- R => rst_i
- );
-\data_rw_o_reg[88][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[88][29]\,
- R => rst_i
- );
-\data_rw_o_reg[88][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[1].[0].s_reqs_reg[4][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[88][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[88][30]\,
- R => rst_i
- );
-\data_rw_o_reg[88][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[88][31]\,
- R => rst_i
- );
-\data_rw_o_reg[88][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[1].[0].s_reqs_reg[4][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[88][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[1].[0].s_reqs_reg[4][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[88][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[1].[0].s_reqs_reg[4][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[88][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[1].[0].s_reqs_reg[4][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[88][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[1].[0].s_reqs_reg[4][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[88][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[1].[0].s_reqs_reg[4][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[88][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[88][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[1].[0].s_reqs_reg[4][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[89][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[1].[1].s_reqs_reg[5][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[89][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[1].[1].s_reqs_reg[5][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[89][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[1].[1].s_reqs_reg[5][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[89][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[89][12]\,
- R => rst_i
- );
-\data_rw_o_reg[89][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[89][13]\,
- R => rst_i
- );
-\data_rw_o_reg[89][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[89][14]\,
- R => rst_i
- );
-\data_rw_o_reg[89][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[89][15]\,
- R => rst_i
- );
-\data_rw_o_reg[89][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[89][16]\,
- R => rst_i
- );
-\data_rw_o_reg[89][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[89][17]\,
- R => rst_i
- );
-\data_rw_o_reg[89][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[89][18]\,
- R => rst_i
- );
-\data_rw_o_reg[89][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[89][19]\,
- R => rst_i
- );
-\data_rw_o_reg[89][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[1].[1].s_reqs_reg[5][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[89][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[89][20]\,
- R => rst_i
- );
-\data_rw_o_reg[89][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[89][21]\,
- R => rst_i
- );
-\data_rw_o_reg[89][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[89][22]\,
- R => rst_i
- );
-\data_rw_o_reg[89][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[89][23]\,
- R => rst_i
- );
-\data_rw_o_reg[89][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[89][24]\,
- R => rst_i
- );
-\data_rw_o_reg[89][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[89][25]\,
- R => rst_i
- );
-\data_rw_o_reg[89][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[89][26]\,
- R => rst_i
- );
-\data_rw_o_reg[89][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[89][27]\,
- R => rst_i
- );
-\data_rw_o_reg[89][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[89][28]\,
- R => rst_i
- );
-\data_rw_o_reg[89][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[89][29]\,
- R => rst_i
- );
-\data_rw_o_reg[89][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[1].[1].s_reqs_reg[5][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[89][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[89][30]\,
- R => rst_i
- );
-\data_rw_o_reg[89][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[89][31]\,
- R => rst_i
- );
-\data_rw_o_reg[89][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[1].[1].s_reqs_reg[5][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[89][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[1].[1].s_reqs_reg[5][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[89][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[1].[1].s_reqs_reg[5][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[89][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[1].[1].s_reqs_reg[5][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[89][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[1].[1].s_reqs_reg[5][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[89][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[1].[1].s_reqs_reg[5][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[89][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[89][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[1].[1].s_reqs_reg[5][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[90][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[1].[2].s_reqs_reg[6][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[90][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[1].[2].s_reqs_reg[6][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[90][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[1].[2].s_reqs_reg[6][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[90][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[90][12]\,
- R => rst_i
- );
-\data_rw_o_reg[90][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[90][13]\,
- R => rst_i
- );
-\data_rw_o_reg[90][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[90][14]\,
- R => rst_i
- );
-\data_rw_o_reg[90][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[90][15]\,
- R => rst_i
- );
-\data_rw_o_reg[90][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[90][16]\,
- R => rst_i
- );
-\data_rw_o_reg[90][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[90][17]\,
- R => rst_i
- );
-\data_rw_o_reg[90][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[90][18]\,
- R => rst_i
- );
-\data_rw_o_reg[90][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[90][19]\,
- R => rst_i
- );
-\data_rw_o_reg[90][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[1].[2].s_reqs_reg[6][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[90][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[90][20]\,
- R => rst_i
- );
-\data_rw_o_reg[90][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[90][21]\,
- R => rst_i
- );
-\data_rw_o_reg[90][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[90][22]\,
- R => rst_i
- );
-\data_rw_o_reg[90][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[90][23]\,
- R => rst_i
- );
-\data_rw_o_reg[90][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[90][24]\,
- R => rst_i
- );
-\data_rw_o_reg[90][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[90][25]\,
- R => rst_i
- );
-\data_rw_o_reg[90][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[90][26]\,
- R => rst_i
- );
-\data_rw_o_reg[90][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[90][27]\,
- R => rst_i
- );
-\data_rw_o_reg[90][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[90][28]\,
- R => rst_i
- );
-\data_rw_o_reg[90][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[90][29]\,
- R => rst_i
- );
-\data_rw_o_reg[90][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[1].[2].s_reqs_reg[6][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[90][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[90][30]\,
- R => rst_i
- );
-\data_rw_o_reg[90][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[90][31]\,
- R => rst_i
- );
-\data_rw_o_reg[90][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[1].[2].s_reqs_reg[6][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[90][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[1].[2].s_reqs_reg[6][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[90][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[1].[2].s_reqs_reg[6][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[90][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[1].[2].s_reqs_reg[6][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[90][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[1].[2].s_reqs_reg[6][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[90][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[1].[2].s_reqs_reg[6][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[90][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[90][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[1].[2].s_reqs_reg[6][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[91][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[1].[3].s_reqs_reg[7][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[91][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[1].[3].s_reqs_reg[7][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[91][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[1].[3].s_reqs_reg[7][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[91][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[91][12]\,
- R => rst_i
- );
-\data_rw_o_reg[91][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[91][13]\,
- R => rst_i
- );
-\data_rw_o_reg[91][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[91][14]\,
- R => rst_i
- );
-\data_rw_o_reg[91][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[91][15]\,
- R => rst_i
- );
-\data_rw_o_reg[91][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[91][16]\,
- R => rst_i
- );
-\data_rw_o_reg[91][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[91][17]\,
- R => rst_i
- );
-\data_rw_o_reg[91][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[91][18]\,
- R => rst_i
- );
-\data_rw_o_reg[91][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[91][19]\,
- R => rst_i
- );
-\data_rw_o_reg[91][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[1].[3].s_reqs_reg[7][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[91][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[91][20]\,
- R => rst_i
- );
-\data_rw_o_reg[91][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[91][21]\,
- R => rst_i
- );
-\data_rw_o_reg[91][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[91][22]\,
- R => rst_i
- );
-\data_rw_o_reg[91][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[91][23]\,
- R => rst_i
- );
-\data_rw_o_reg[91][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[91][24]\,
- R => rst_i
- );
-\data_rw_o_reg[91][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[91][25]\,
- R => rst_i
- );
-\data_rw_o_reg[91][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[91][26]\,
- R => rst_i
- );
-\data_rw_o_reg[91][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[91][27]\,
- R => rst_i
- );
-\data_rw_o_reg[91][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[91][28]\,
- R => rst_i
- );
-\data_rw_o_reg[91][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[91][29]\,
- R => rst_i
- );
-\data_rw_o_reg[91][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[1].[3].s_reqs_reg[7][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[91][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[91][30]\,
- R => rst_i
- );
-\data_rw_o_reg[91][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[91][31]\,
- R => rst_i
- );
-\data_rw_o_reg[91][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[1].[3].s_reqs_reg[7][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[91][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[1].[3].s_reqs_reg[7][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[91][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[1].[3].s_reqs_reg[7][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[91][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[1].[3].s_reqs_reg[7][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[91][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[1].[3].s_reqs_reg[7][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[91][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[1].[3].s_reqs_reg[7][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[91][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[91][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[1].[3].s_reqs_reg[7][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[92][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[2].[0].s_reqs_reg[8][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[92][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[2].[0].s_reqs_reg[8][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[92][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[2].[0].s_reqs_reg[8][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[92][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[92][12]\,
- R => rst_i
- );
-\data_rw_o_reg[92][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[92][13]\,
- R => rst_i
- );
-\data_rw_o_reg[92][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[92][14]\,
- R => rst_i
- );
-\data_rw_o_reg[92][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[92][15]\,
- R => rst_i
- );
-\data_rw_o_reg[92][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[92][16]\,
- R => rst_i
- );
-\data_rw_o_reg[92][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[92][17]\,
- R => rst_i
- );
-\data_rw_o_reg[92][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[92][18]\,
- R => rst_i
- );
-\data_rw_o_reg[92][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[92][19]\,
- R => rst_i
- );
-\data_rw_o_reg[92][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[2].[0].s_reqs_reg[8][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[92][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[92][20]\,
- R => rst_i
- );
-\data_rw_o_reg[92][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[92][21]\,
- R => rst_i
- );
-\data_rw_o_reg[92][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[92][22]\,
- R => rst_i
- );
-\data_rw_o_reg[92][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[92][23]\,
- R => rst_i
- );
-\data_rw_o_reg[92][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[92][24]\,
- R => rst_i
- );
-\data_rw_o_reg[92][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[92][25]\,
- R => rst_i
- );
-\data_rw_o_reg[92][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[92][26]\,
- R => rst_i
- );
-\data_rw_o_reg[92][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[92][27]\,
- R => rst_i
- );
-\data_rw_o_reg[92][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[92][28]\,
- R => rst_i
- );
-\data_rw_o_reg[92][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[92][29]\,
- R => rst_i
- );
-\data_rw_o_reg[92][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[2].[0].s_reqs_reg[8][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[92][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[92][30]\,
- R => rst_i
- );
-\data_rw_o_reg[92][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[92][31]\,
- R => rst_i
- );
-\data_rw_o_reg[92][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[2].[0].s_reqs_reg[8][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[92][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[2].[0].s_reqs_reg[8][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[92][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[2].[0].s_reqs_reg[8][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[92][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[2].[0].s_reqs_reg[8][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[92][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[2].[0].s_reqs_reg[8][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[92][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[2].[0].s_reqs_reg[8][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[92][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[92][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[2].[0].s_reqs_reg[8][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[93][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[2].[1].s_reqs_reg[9][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[93][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[2].[1].s_reqs_reg[9][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[93][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[2].[1].s_reqs_reg[9][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[93][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[93][12]\,
- R => rst_i
- );
-\data_rw_o_reg[93][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[93][13]\,
- R => rst_i
- );
-\data_rw_o_reg[93][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[93][14]\,
- R => rst_i
- );
-\data_rw_o_reg[93][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[93][15]\,
- R => rst_i
- );
-\data_rw_o_reg[93][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[93][16]\,
- R => rst_i
- );
-\data_rw_o_reg[93][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[93][17]\,
- R => rst_i
- );
-\data_rw_o_reg[93][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[93][18]\,
- R => rst_i
- );
-\data_rw_o_reg[93][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[93][19]\,
- R => rst_i
- );
-\data_rw_o_reg[93][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[2].[1].s_reqs_reg[9][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[93][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[93][20]\,
- R => rst_i
- );
-\data_rw_o_reg[93][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[93][21]\,
- R => rst_i
- );
-\data_rw_o_reg[93][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[93][22]\,
- R => rst_i
- );
-\data_rw_o_reg[93][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[93][23]\,
- R => rst_i
- );
-\data_rw_o_reg[93][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[93][24]\,
- R => rst_i
- );
-\data_rw_o_reg[93][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[93][25]\,
- R => rst_i
- );
-\data_rw_o_reg[93][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[93][26]\,
- R => rst_i
- );
-\data_rw_o_reg[93][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[93][27]\,
- R => rst_i
- );
-\data_rw_o_reg[93][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[93][28]\,
- R => rst_i
- );
-\data_rw_o_reg[93][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[93][29]\,
- R => rst_i
- );
-\data_rw_o_reg[93][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[2].[1].s_reqs_reg[9][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[93][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[93][30]\,
- R => rst_i
- );
-\data_rw_o_reg[93][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[93][31]\,
- R => rst_i
- );
-\data_rw_o_reg[93][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[2].[1].s_reqs_reg[9][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[93][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[2].[1].s_reqs_reg[9][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[93][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[2].[1].s_reqs_reg[9][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[93][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[2].[1].s_reqs_reg[9][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[93][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[2].[1].s_reqs_reg[9][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[93][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[2].[1].s_reqs_reg[9][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[93][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[93][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[2].[1].s_reqs_reg[9][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[94][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[2].[2].s_reqs_reg[10][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[94][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[2].[2].s_reqs_reg[10][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[94][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[2].[2].s_reqs_reg[10][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[94][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[94][12]\,
- R => rst_i
- );
-\data_rw_o_reg[94][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[94][13]\,
- R => rst_i
- );
-\data_rw_o_reg[94][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[94][14]\,
- R => rst_i
- );
-\data_rw_o_reg[94][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[94][15]\,
- R => rst_i
- );
-\data_rw_o_reg[94][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[94][16]\,
- R => rst_i
- );
-\data_rw_o_reg[94][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[94][17]\,
- R => rst_i
- );
-\data_rw_o_reg[94][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[94][18]\,
- R => rst_i
- );
-\data_rw_o_reg[94][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[94][19]\,
- R => rst_i
- );
-\data_rw_o_reg[94][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[2].[2].s_reqs_reg[10][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[94][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[94][20]\,
- R => rst_i
- );
-\data_rw_o_reg[94][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[94][21]\,
- R => rst_i
- );
-\data_rw_o_reg[94][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[94][22]\,
- R => rst_i
- );
-\data_rw_o_reg[94][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[94][23]\,
- R => rst_i
- );
-\data_rw_o_reg[94][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[94][24]\,
- R => rst_i
- );
-\data_rw_o_reg[94][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[94][25]\,
- R => rst_i
- );
-\data_rw_o_reg[94][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[94][26]\,
- R => rst_i
- );
-\data_rw_o_reg[94][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[94][27]\,
- R => rst_i
- );
-\data_rw_o_reg[94][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[94][28]\,
- R => rst_i
- );
-\data_rw_o_reg[94][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[94][29]\,
- R => rst_i
- );
-\data_rw_o_reg[94][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[2].[2].s_reqs_reg[10][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[94][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[94][30]\,
- R => rst_i
- );
-\data_rw_o_reg[94][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[94][31]\,
- R => rst_i
- );
-\data_rw_o_reg[94][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[2].[2].s_reqs_reg[10][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[94][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[2].[2].s_reqs_reg[10][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[94][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[2].[2].s_reqs_reg[10][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[94][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[2].[2].s_reqs_reg[10][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[94][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[2].[2].s_reqs_reg[10][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[94][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[2].[2].s_reqs_reg[10][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[94][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[94][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[2].[2].s_reqs_reg[10][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[95][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[2].[3].s_reqs_reg[11][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[95][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[2].[3].s_reqs_reg[11][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[95][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[2].[3].s_reqs_reg[11][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[95][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[95][12]\,
- R => rst_i
- );
-\data_rw_o_reg[95][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[95][13]\,
- R => rst_i
- );
-\data_rw_o_reg[95][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[95][14]\,
- R => rst_i
- );
-\data_rw_o_reg[95][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[95][15]\,
- R => rst_i
- );
-\data_rw_o_reg[95][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[95][16]\,
- R => rst_i
- );
-\data_rw_o_reg[95][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[95][17]\,
- R => rst_i
- );
-\data_rw_o_reg[95][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[95][18]\,
- R => rst_i
- );
-\data_rw_o_reg[95][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[95][19]\,
- R => rst_i
- );
-\data_rw_o_reg[95][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[2].[3].s_reqs_reg[11][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[95][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[95][20]\,
- R => rst_i
- );
-\data_rw_o_reg[95][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[95][21]\,
- R => rst_i
- );
-\data_rw_o_reg[95][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[95][22]\,
- R => rst_i
- );
-\data_rw_o_reg[95][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[95][23]\,
- R => rst_i
- );
-\data_rw_o_reg[95][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[95][24]\,
- R => rst_i
- );
-\data_rw_o_reg[95][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[95][25]\,
- R => rst_i
- );
-\data_rw_o_reg[95][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[95][26]\,
- R => rst_i
- );
-\data_rw_o_reg[95][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[95][27]\,
- R => rst_i
- );
-\data_rw_o_reg[95][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[95][28]\,
- R => rst_i
- );
-\data_rw_o_reg[95][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[95][29]\,
- R => rst_i
- );
-\data_rw_o_reg[95][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[2].[3].s_reqs_reg[11][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[95][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[95][30]\,
- R => rst_i
- );
-\data_rw_o_reg[95][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[95][31]\,
- R => rst_i
- );
-\data_rw_o_reg[95][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[2].[3].s_reqs_reg[11][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[95][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[2].[3].s_reqs_reg[11][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[95][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[2].[3].s_reqs_reg[11][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[95][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[2].[3].s_reqs_reg[11][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[95][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[2].[3].s_reqs_reg[11][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[95][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[2].[3].s_reqs_reg[11][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[95][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[95][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[2].[3].s_reqs_reg[11][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[96][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[3].[0].s_reqs_reg[12][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[96][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[3].[0].s_reqs_reg[12][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[96][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[3].[0].s_reqs_reg[12][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[96][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[96][12]\,
- R => rst_i
- );
-\data_rw_o_reg[96][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[96][13]\,
- R => rst_i
- );
-\data_rw_o_reg[96][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[96][14]\,
- R => rst_i
- );
-\data_rw_o_reg[96][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[96][15]\,
- R => rst_i
- );
-\data_rw_o_reg[96][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[96][16]\,
- R => rst_i
- );
-\data_rw_o_reg[96][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[96][17]\,
- R => rst_i
- );
-\data_rw_o_reg[96][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[96][18]\,
- R => rst_i
- );
-\data_rw_o_reg[96][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[96][19]\,
- R => rst_i
- );
-\data_rw_o_reg[96][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[3].[0].s_reqs_reg[12][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[96][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[96][20]\,
- R => rst_i
- );
-\data_rw_o_reg[96][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[96][21]\,
- R => rst_i
- );
-\data_rw_o_reg[96][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[96][22]\,
- R => rst_i
- );
-\data_rw_o_reg[96][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[96][23]\,
- R => rst_i
- );
-\data_rw_o_reg[96][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[96][24]\,
- R => rst_i
- );
-\data_rw_o_reg[96][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[96][25]\,
- R => rst_i
- );
-\data_rw_o_reg[96][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[96][26]\,
- R => rst_i
- );
-\data_rw_o_reg[96][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[96][27]\,
- R => rst_i
- );
-\data_rw_o_reg[96][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[96][28]\,
- R => rst_i
- );
-\data_rw_o_reg[96][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[96][29]\,
- R => rst_i
- );
-\data_rw_o_reg[96][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[3].[0].s_reqs_reg[12][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[96][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[96][30]\,
- R => rst_i
- );
-\data_rw_o_reg[96][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[96][31]\,
- R => rst_i
- );
-\data_rw_o_reg[96][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[3].[0].s_reqs_reg[12][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[96][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[3].[0].s_reqs_reg[12][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[96][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[3].[0].s_reqs_reg[12][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[96][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[3].[0].s_reqs_reg[12][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[96][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[3].[0].s_reqs_reg[12][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[96][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[3].[0].s_reqs_reg[12][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[96][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[96][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[3].[0].s_reqs_reg[12][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[97][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[3].[1].s_reqs_reg[13][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[97][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[3].[1].s_reqs_reg[13][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[97][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[3].[1].s_reqs_reg[13][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[97][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[97][12]\,
- R => rst_i
- );
-\data_rw_o_reg[97][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[97][13]\,
- R => rst_i
- );
-\data_rw_o_reg[97][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[97][14]\,
- R => rst_i
- );
-\data_rw_o_reg[97][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[97][15]\,
- R => rst_i
- );
-\data_rw_o_reg[97][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[97][16]\,
- R => rst_i
- );
-\data_rw_o_reg[97][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[97][17]\,
- R => rst_i
- );
-\data_rw_o_reg[97][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[97][18]\,
- R => rst_i
- );
-\data_rw_o_reg[97][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[97][19]\,
- R => rst_i
- );
-\data_rw_o_reg[97][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[3].[1].s_reqs_reg[13][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[97][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[97][20]\,
- R => rst_i
- );
-\data_rw_o_reg[97][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[97][21]\,
- R => rst_i
- );
-\data_rw_o_reg[97][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[97][22]\,
- R => rst_i
- );
-\data_rw_o_reg[97][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[97][23]\,
- R => rst_i
- );
-\data_rw_o_reg[97][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[97][24]\,
- R => rst_i
- );
-\data_rw_o_reg[97][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[97][25]\,
- R => rst_i
- );
-\data_rw_o_reg[97][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[97][26]\,
- R => rst_i
- );
-\data_rw_o_reg[97][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[97][27]\,
- R => rst_i
- );
-\data_rw_o_reg[97][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[97][28]\,
- R => rst_i
- );
-\data_rw_o_reg[97][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[97][29]\,
- R => rst_i
- );
-\data_rw_o_reg[97][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[3].[1].s_reqs_reg[13][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[97][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[97][30]\,
- R => rst_i
- );
-\data_rw_o_reg[97][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[97][31]\,
- R => rst_i
- );
-\data_rw_o_reg[97][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[3].[1].s_reqs_reg[13][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[97][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[3].[1].s_reqs_reg[13][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[97][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[3].[1].s_reqs_reg[13][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[97][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[3].[1].s_reqs_reg[13][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[97][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[3].[1].s_reqs_reg[13][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[97][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[3].[1].s_reqs_reg[13][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[97][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[97][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[3].[1].s_reqs_reg[13][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[98][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[3].[2].s_reqs_reg[14][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[98][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[3].[2].s_reqs_reg[14][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[98][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[3].[2].s_reqs_reg[14][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[98][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[98][12]\,
- R => rst_i
- );
-\data_rw_o_reg[98][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[98][13]\,
- R => rst_i
- );
-\data_rw_o_reg[98][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[98][14]\,
- R => rst_i
- );
-\data_rw_o_reg[98][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[98][15]\,
- R => rst_i
- );
-\data_rw_o_reg[98][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[98][16]\,
- R => rst_i
- );
-\data_rw_o_reg[98][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[98][17]\,
- R => rst_i
- );
-\data_rw_o_reg[98][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[98][18]\,
- R => rst_i
- );
-\data_rw_o_reg[98][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[98][19]\,
- R => rst_i
- );
-\data_rw_o_reg[98][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[3].[2].s_reqs_reg[14][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[98][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[98][20]\,
- R => rst_i
- );
-\data_rw_o_reg[98][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[98][21]\,
- R => rst_i
- );
-\data_rw_o_reg[98][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[98][22]\,
- R => rst_i
- );
-\data_rw_o_reg[98][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[98][23]\,
- R => rst_i
- );
-\data_rw_o_reg[98][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[98][24]\,
- R => rst_i
- );
-\data_rw_o_reg[98][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[98][25]\,
- R => rst_i
- );
-\data_rw_o_reg[98][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[98][26]\,
- R => rst_i
- );
-\data_rw_o_reg[98][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[98][27]\,
- R => rst_i
- );
-\data_rw_o_reg[98][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[98][28]\,
- R => rst_i
- );
-\data_rw_o_reg[98][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[98][29]\,
- R => rst_i
- );
-\data_rw_o_reg[98][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[3].[2].s_reqs_reg[14][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[98][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[98][30]\,
- R => rst_i
- );
-\data_rw_o_reg[98][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[98][31]\,
- R => rst_i
- );
-\data_rw_o_reg[98][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[3].[2].s_reqs_reg[14][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[98][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[3].[2].s_reqs_reg[14][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[98][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[3].[2].s_reqs_reg[14][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[98][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[3].[2].s_reqs_reg[14][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[98][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[3].[2].s_reqs_reg[14][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[98][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[3].[2].s_reqs_reg[14][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[98][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[98][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[3].[2].s_reqs_reg[14][value][11]_0\(9),
- S => rst_i
- );
-\data_rw_o_reg[99][0]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][7]_i_1_n_0\,
- D => s00_axi_wdata(0),
- Q => \^[3].[3].s_reqs_reg[15][value][11]_0\(0),
- S => rst_i
- );
-\data_rw_o_reg[99][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][15]_i_1_n_0\,
- D => s00_axi_wdata(10),
- Q => \^[3].[3].s_reqs_reg[15][value][11]_0\(10),
- R => rst_i
- );
-\data_rw_o_reg[99][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][15]_i_1_n_0\,
- D => s00_axi_wdata(11),
- Q => \^[3].[3].s_reqs_reg[15][value][11]_0\(11),
- R => rst_i
- );
-\data_rw_o_reg[99][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][15]_i_1_n_0\,
- D => s00_axi_wdata(12),
- Q => \data_rw_o_reg_n_0_[99][12]\,
- R => rst_i
- );
-\data_rw_o_reg[99][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][15]_i_1_n_0\,
- D => s00_axi_wdata(13),
- Q => \data_rw_o_reg_n_0_[99][13]\,
- R => rst_i
- );
-\data_rw_o_reg[99][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][15]_i_1_n_0\,
- D => s00_axi_wdata(14),
- Q => \data_rw_o_reg_n_0_[99][14]\,
- R => rst_i
- );
-\data_rw_o_reg[99][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][15]_i_1_n_0\,
- D => s00_axi_wdata(15),
- Q => \data_rw_o_reg_n_0_[99][15]\,
- R => rst_i
- );
-\data_rw_o_reg[99][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][23]_i_1_n_0\,
- D => s00_axi_wdata(16),
- Q => \data_rw_o_reg_n_0_[99][16]\,
- R => rst_i
- );
-\data_rw_o_reg[99][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][23]_i_1_n_0\,
- D => s00_axi_wdata(17),
- Q => \data_rw_o_reg_n_0_[99][17]\,
- R => rst_i
- );
-\data_rw_o_reg[99][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][23]_i_1_n_0\,
- D => s00_axi_wdata(18),
- Q => \data_rw_o_reg_n_0_[99][18]\,
- R => rst_i
- );
-\data_rw_o_reg[99][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][23]_i_1_n_0\,
- D => s00_axi_wdata(19),
- Q => \data_rw_o_reg_n_0_[99][19]\,
- R => rst_i
- );
-\data_rw_o_reg[99][1]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][7]_i_1_n_0\,
- D => s00_axi_wdata(1),
- Q => \^[3].[3].s_reqs_reg[15][value][11]_0\(1),
- S => rst_i
- );
-\data_rw_o_reg[99][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][23]_i_1_n_0\,
- D => s00_axi_wdata(20),
- Q => \data_rw_o_reg_n_0_[99][20]\,
- R => rst_i
- );
-\data_rw_o_reg[99][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][23]_i_1_n_0\,
- D => s00_axi_wdata(21),
- Q => \data_rw_o_reg_n_0_[99][21]\,
- R => rst_i
- );
-\data_rw_o_reg[99][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][23]_i_1_n_0\,
- D => s00_axi_wdata(22),
- Q => \data_rw_o_reg_n_0_[99][22]\,
- R => rst_i
- );
-\data_rw_o_reg[99][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][23]_i_1_n_0\,
- D => s00_axi_wdata(23),
- Q => \data_rw_o_reg_n_0_[99][23]\,
- R => rst_i
- );
-\data_rw_o_reg[99][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][31]_i_1_n_0\,
- D => s00_axi_wdata(24),
- Q => \data_rw_o_reg_n_0_[99][24]\,
- R => rst_i
- );
-\data_rw_o_reg[99][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][31]_i_1_n_0\,
- D => s00_axi_wdata(25),
- Q => \data_rw_o_reg_n_0_[99][25]\,
- R => rst_i
- );
-\data_rw_o_reg[99][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][31]_i_1_n_0\,
- D => s00_axi_wdata(26),
- Q => \data_rw_o_reg_n_0_[99][26]\,
- R => rst_i
- );
-\data_rw_o_reg[99][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][31]_i_1_n_0\,
- D => s00_axi_wdata(27),
- Q => \data_rw_o_reg_n_0_[99][27]\,
- R => rst_i
- );
-\data_rw_o_reg[99][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][31]_i_1_n_0\,
- D => s00_axi_wdata(28),
- Q => \data_rw_o_reg_n_0_[99][28]\,
- R => rst_i
- );
-\data_rw_o_reg[99][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][31]_i_1_n_0\,
- D => s00_axi_wdata(29),
- Q => \data_rw_o_reg_n_0_[99][29]\,
- R => rst_i
- );
-\data_rw_o_reg[99][2]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][7]_i_1_n_0\,
- D => s00_axi_wdata(2),
- Q => \^[3].[3].s_reqs_reg[15][value][11]_0\(2),
- S => rst_i
- );
-\data_rw_o_reg[99][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][31]_i_1_n_0\,
- D => s00_axi_wdata(30),
- Q => \data_rw_o_reg_n_0_[99][30]\,
- R => rst_i
- );
-\data_rw_o_reg[99][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][31]_i_1_n_0\,
- D => s00_axi_wdata(31),
- Q => \data_rw_o_reg_n_0_[99][31]\,
- R => rst_i
- );
-\data_rw_o_reg[99][3]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][7]_i_1_n_0\,
- D => s00_axi_wdata(3),
- Q => \^[3].[3].s_reqs_reg[15][value][11]_0\(3),
- S => rst_i
- );
-\data_rw_o_reg[99][4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][7]_i_1_n_0\,
- D => s00_axi_wdata(4),
- Q => \^[3].[3].s_reqs_reg[15][value][11]_0\(4),
- S => rst_i
- );
-\data_rw_o_reg[99][5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][7]_i_1_n_0\,
- D => s00_axi_wdata(5),
- Q => \^[3].[3].s_reqs_reg[15][value][11]_0\(5),
- S => rst_i
- );
-\data_rw_o_reg[99][6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][7]_i_1_n_0\,
- D => s00_axi_wdata(6),
- Q => \^[3].[3].s_reqs_reg[15][value][11]_0\(6),
- S => rst_i
- );
-\data_rw_o_reg[99][7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][7]_i_1_n_0\,
- D => s00_axi_wdata(7),
- Q => \^[3].[3].s_reqs_reg[15][value][11]_0\(7),
- S => rst_i
- );
-\data_rw_o_reg[99][8]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][15]_i_1_n_0\,
- D => s00_axi_wdata(8),
- Q => \^[3].[3].s_reqs_reg[15][value][11]_0\(8),
- S => rst_i
- );
-\data_rw_o_reg[99][9]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => \data_rw_o[99][15]_i_1_n_0\,
- D => s00_axi_wdata(9),
- Q => \^[3].[3].s_reqs_reg[15][value][11]_0\(9),
- S => rst_i
- );
-dig_out6_n_INST_0: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4777"
- )
- port map (
- I0 => \s_ins_reg[3]\(0),
- I1 => \data_rw_o[3]\(0),
- I2 => \data_rw_o[3]\(1),
- I3 => s_tick,
- O => dig_out6_n
- );
-\dig_outs_i[0]_INST_0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"F808"
- )
- port map (
- I0 => s_tick,
- I1 => \data_rw_o[3]\(1),
- I2 => \data_rw_o[3]\(0),
- I3 => \s_ins_reg[3]\(0),
- O => dig_outs_i(0)
- );
-\v_dout[4]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => \data_rw_o[10]\(4),
- I1 => \^v_dout_reg[7]\(2),
- O => \v_dout_reg[4]\
- );
-\v_dout[4]_i_1__0\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => \data_rw_o[78]\(4),
- I1 => \^v_dout_reg[7]_0\(2),
- O => \v_dout_reg[4]_0\
- );
-\v_dout[5]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => \data_rw_o[10]\(5),
- I1 => \^v_dout_reg[7]\(2),
- O => \v_dout_reg[5]\
- );
-\v_dout[5]_i_1__0\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => \data_rw_o[78]\(5),
- I1 => \^v_dout_reg[7]_0\(2),
- O => \v_dout_reg[5]_0\
- );
-\v_dout[6]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => \data_rw_o[10]\(6),
- I1 => \^v_dout_reg[7]\(2),
- O => \v_dout_reg[6]\
- );
-\v_dout[6]_i_1__0\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => \data_rw_o[78]\(6),
- I1 => \^v_dout_reg[7]_0\(2),
- O => \v_dout_reg[6]_0\
- );
-\v_dout[7]_i_2\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => \data_rw_o[10]\(7),
- I1 => \^v_dout_reg[7]\(2),
- O => \v_dout_reg[7]_1\
- );
-\v_dout[7]_i_2__0\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => \data_rw_o[78]\(7),
- I1 => \^v_dout_reg[7]_0\(2),
- O => \v_dout_reg[7]_2\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_clockDivider is
- port (
- watchdog_pl_o : out STD_LOGIC;
- ps_clk_i : in STD_LOGIC;
- rst_i : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_clockDivider : entity is "clockDivider";
-end system_design_fasec_hwtest_0_0_clockDivider;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_clockDivider is
- signal I : STD_LOGIC;
- signal data0 : STD_LOGIC_VECTOR ( 31 downto 1 );
- signal s_counter : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal \s_counter[31]_i_10_n_0\ : STD_LOGIC;
- signal \s_counter[31]_i_2_n_0\ : STD_LOGIC;
- signal \s_counter[31]_i_3_n_0\ : STD_LOGIC;
- signal \s_counter[31]_i_4_n_0\ : STD_LOGIC;
- signal \s_counter[31]_i_5_n_0\ : STD_LOGIC;
- signal \s_counter[31]_i_7_n_0\ : STD_LOGIC;
- signal \s_counter[31]_i_8_n_0\ : STD_LOGIC;
- signal \s_counter[31]_i_9_n_0\ : STD_LOGIC;
- signal s_counter_0 : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal \s_counter_reg[12]_i_2_n_0\ : STD_LOGIC;
- signal \s_counter_reg[12]_i_2_n_1\ : STD_LOGIC;
- signal \s_counter_reg[12]_i_2_n_2\ : STD_LOGIC;
- signal \s_counter_reg[12]_i_2_n_3\ : STD_LOGIC;
- signal \s_counter_reg[16]_i_2_n_0\ : STD_LOGIC;
- signal \s_counter_reg[16]_i_2_n_1\ : STD_LOGIC;
- signal \s_counter_reg[16]_i_2_n_2\ : STD_LOGIC;
- signal \s_counter_reg[16]_i_2_n_3\ : STD_LOGIC;
- signal \s_counter_reg[20]_i_2_n_0\ : STD_LOGIC;
- signal \s_counter_reg[20]_i_2_n_1\ : STD_LOGIC;
- signal \s_counter_reg[20]_i_2_n_2\ : STD_LOGIC;
- signal \s_counter_reg[20]_i_2_n_3\ : STD_LOGIC;
- signal \s_counter_reg[24]_i_2_n_0\ : STD_LOGIC;
- signal \s_counter_reg[24]_i_2_n_1\ : STD_LOGIC;
- signal \s_counter_reg[24]_i_2_n_2\ : STD_LOGIC;
- signal \s_counter_reg[24]_i_2_n_3\ : STD_LOGIC;
- signal \s_counter_reg[28]_i_2_n_0\ : STD_LOGIC;
- signal \s_counter_reg[28]_i_2_n_1\ : STD_LOGIC;
- signal \s_counter_reg[28]_i_2_n_2\ : STD_LOGIC;
- signal \s_counter_reg[28]_i_2_n_3\ : STD_LOGIC;
- signal \s_counter_reg[31]_i_6_n_2\ : STD_LOGIC;
- signal \s_counter_reg[31]_i_6_n_3\ : STD_LOGIC;
- signal \s_counter_reg[4]_i_2_n_0\ : STD_LOGIC;
- signal \s_counter_reg[4]_i_2_n_1\ : STD_LOGIC;
- signal \s_counter_reg[4]_i_2_n_2\ : STD_LOGIC;
- signal \s_counter_reg[4]_i_2_n_3\ : STD_LOGIC;
- signal \s_counter_reg[8]_i_2_n_0\ : STD_LOGIC;
- signal \s_counter_reg[8]_i_2_n_1\ : STD_LOGIC;
- signal \s_counter_reg[8]_i_2_n_2\ : STD_LOGIC;
- signal \s_counter_reg[8]_i_2_n_3\ : STD_LOGIC;
- signal s_temp_i_1_n_0 : STD_LOGIC;
- signal \NLW_s_counter_reg[31]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
- signal \NLW_s_counter_reg[31]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
- attribute box_type : string;
- attribute box_type of cmp_BUFG : label is "PRIMITIVE";
-begin
-cmp_BUFG: unisim.vcomponents.BUFG
- port map (
- I => I,
- O => watchdog_pl_o
- );
-\s_counter[0]_i_1__1\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_counter(0),
- O => s_counter_0(0)
- );
-\s_counter[10]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(10),
- O => s_counter_0(10)
- );
-\s_counter[11]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(11),
- O => s_counter_0(11)
- );
-\s_counter[12]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(12),
- O => s_counter_0(12)
- );
-\s_counter[13]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(13),
- O => s_counter_0(13)
- );
-\s_counter[14]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(14),
- O => s_counter_0(14)
- );
-\s_counter[15]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(15),
- O => s_counter_0(15)
- );
-\s_counter[16]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(16),
- O => s_counter_0(16)
- );
-\s_counter[17]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(17),
- O => s_counter_0(17)
- );
-\s_counter[18]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(18),
- O => s_counter_0(18)
- );
-\s_counter[19]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(19),
- O => s_counter_0(19)
- );
-\s_counter[1]_i_1__1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(1),
- O => s_counter_0(1)
- );
-\s_counter[20]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(20),
- O => s_counter_0(20)
- );
-\s_counter[21]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(21),
- O => s_counter_0(21)
- );
-\s_counter[22]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(22),
- O => s_counter_0(22)
- );
-\s_counter[23]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(23),
- O => s_counter_0(23)
- );
-\s_counter[24]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(24),
- O => s_counter_0(24)
- );
-\s_counter[25]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(25),
- O => s_counter_0(25)
- );
-\s_counter[26]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(26),
- O => s_counter_0(26)
- );
-\s_counter[27]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(27),
- O => s_counter_0(27)
- );
-\s_counter[28]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(28),
- O => s_counter_0(28)
- );
-\s_counter[29]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(29),
- O => s_counter_0(29)
- );
-\s_counter[2]_i_1__1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(2),
- O => s_counter_0(2)
- );
-\s_counter[30]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(30),
- O => s_counter_0(30)
- );
-\s_counter[31]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(31),
- O => s_counter_0(31)
- );
-\s_counter[31]_i_10\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_counter(21),
- I1 => s_counter(20),
- I2 => s_counter(23),
- I3 => s_counter(22),
- O => \s_counter[31]_i_10_n_0\
- );
-\s_counter[31]_i_2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_counter(11),
- I1 => s_counter(10),
- I2 => s_counter(8),
- I3 => s_counter(9),
- I4 => \s_counter[31]_i_7_n_0\,
- O => \s_counter[31]_i_2_n_0\
- );
-\s_counter[31]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF7FFF"
- )
- port map (
- I0 => s_counter(2),
- I1 => s_counter(3),
- I2 => s_counter(0),
- I3 => s_counter(1),
- I4 => \s_counter[31]_i_8_n_0\,
- O => \s_counter[31]_i_3_n_0\
- );
-\s_counter[31]_i_4\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_counter(26),
- I1 => s_counter(27),
- I2 => s_counter(24),
- I3 => s_counter(25),
- I4 => \s_counter[31]_i_9_n_0\,
- O => \s_counter[31]_i_4_n_0\
- );
-\s_counter[31]_i_5\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFEFF"
- )
- port map (
- I0 => s_counter(18),
- I1 => s_counter(19),
- I2 => s_counter(17),
- I3 => s_counter(16),
- I4 => \s_counter[31]_i_10_n_0\,
- O => \s_counter[31]_i_5_n_0\
- );
-\s_counter[31]_i_7\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_counter(13),
- I1 => s_counter(12),
- I2 => s_counter(15),
- I3 => s_counter(14),
- O => \s_counter[31]_i_7_n_0\
- );
-\s_counter[31]_i_8\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_counter(4),
- I1 => s_counter(5),
- I2 => s_counter(7),
- I3 => s_counter(6),
- O => \s_counter[31]_i_8_n_0\
- );
-\s_counter[31]_i_9\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_counter(29),
- I1 => s_counter(28),
- I2 => s_counter(31),
- I3 => s_counter(30),
- O => \s_counter[31]_i_9_n_0\
- );
-\s_counter[3]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(3),
- O => s_counter_0(3)
- );
-\s_counter[4]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(4),
- O => s_counter_0(4)
- );
-\s_counter[5]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(5),
- O => s_counter_0(5)
- );
-\s_counter[6]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(6),
- O => s_counter_0(6)
- );
-\s_counter[7]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(7),
- O => s_counter_0(7)
- );
-\s_counter[8]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(8),
- O => s_counter_0(8)
- );
-\s_counter[9]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0000"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => data0(9),
- O => s_counter_0(9)
- );
-\s_counter_reg[0]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(0),
- Q => s_counter(0)
- );
-\s_counter_reg[10]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(10),
- Q => s_counter(10)
- );
-\s_counter_reg[11]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(11),
- Q => s_counter(11)
- );
-\s_counter_reg[12]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(12),
- Q => s_counter(12)
- );
-\s_counter_reg[12]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => \s_counter_reg[8]_i_2_n_0\,
- CO(3) => \s_counter_reg[12]_i_2_n_0\,
- CO(2) => \s_counter_reg[12]_i_2_n_1\,
- CO(1) => \s_counter_reg[12]_i_2_n_2\,
- CO(0) => \s_counter_reg[12]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3 downto 0) => data0(12 downto 9),
- S(3 downto 0) => s_counter(12 downto 9)
- );
-\s_counter_reg[13]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(13),
- Q => s_counter(13)
- );
-\s_counter_reg[14]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(14),
- Q => s_counter(14)
- );
-\s_counter_reg[15]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(15),
- Q => s_counter(15)
- );
-\s_counter_reg[16]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(16),
- Q => s_counter(16)
- );
-\s_counter_reg[16]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => \s_counter_reg[12]_i_2_n_0\,
- CO(3) => \s_counter_reg[16]_i_2_n_0\,
- CO(2) => \s_counter_reg[16]_i_2_n_1\,
- CO(1) => \s_counter_reg[16]_i_2_n_2\,
- CO(0) => \s_counter_reg[16]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3 downto 0) => data0(16 downto 13),
- S(3 downto 0) => s_counter(16 downto 13)
- );
-\s_counter_reg[17]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(17),
- Q => s_counter(17)
- );
-\s_counter_reg[18]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(18),
- Q => s_counter(18)
- );
-\s_counter_reg[19]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(19),
- Q => s_counter(19)
- );
-\s_counter_reg[1]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(1),
- Q => s_counter(1)
- );
-\s_counter_reg[20]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(20),
- Q => s_counter(20)
- );
-\s_counter_reg[20]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => \s_counter_reg[16]_i_2_n_0\,
- CO(3) => \s_counter_reg[20]_i_2_n_0\,
- CO(2) => \s_counter_reg[20]_i_2_n_1\,
- CO(1) => \s_counter_reg[20]_i_2_n_2\,
- CO(0) => \s_counter_reg[20]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3 downto 0) => data0(20 downto 17),
- S(3 downto 0) => s_counter(20 downto 17)
- );
-\s_counter_reg[21]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(21),
- Q => s_counter(21)
- );
-\s_counter_reg[22]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(22),
- Q => s_counter(22)
- );
-\s_counter_reg[23]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(23),
- Q => s_counter(23)
- );
-\s_counter_reg[24]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(24),
- Q => s_counter(24)
- );
-\s_counter_reg[24]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => \s_counter_reg[20]_i_2_n_0\,
- CO(3) => \s_counter_reg[24]_i_2_n_0\,
- CO(2) => \s_counter_reg[24]_i_2_n_1\,
- CO(1) => \s_counter_reg[24]_i_2_n_2\,
- CO(0) => \s_counter_reg[24]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3 downto 0) => data0(24 downto 21),
- S(3 downto 0) => s_counter(24 downto 21)
- );
-\s_counter_reg[25]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(25),
- Q => s_counter(25)
- );
-\s_counter_reg[26]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(26),
- Q => s_counter(26)
- );
-\s_counter_reg[27]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(27),
- Q => s_counter(27)
- );
-\s_counter_reg[28]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(28),
- Q => s_counter(28)
- );
-\s_counter_reg[28]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => \s_counter_reg[24]_i_2_n_0\,
- CO(3) => \s_counter_reg[28]_i_2_n_0\,
- CO(2) => \s_counter_reg[28]_i_2_n_1\,
- CO(1) => \s_counter_reg[28]_i_2_n_2\,
- CO(0) => \s_counter_reg[28]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3 downto 0) => data0(28 downto 25),
- S(3 downto 0) => s_counter(28 downto 25)
- );
-\s_counter_reg[29]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(29),
- Q => s_counter(29)
- );
-\s_counter_reg[2]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(2),
- Q => s_counter(2)
- );
-\s_counter_reg[30]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(30),
- Q => s_counter(30)
- );
-\s_counter_reg[31]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(31),
- Q => s_counter(31)
- );
-\s_counter_reg[31]_i_6\: unisim.vcomponents.CARRY4
- port map (
- CI => \s_counter_reg[28]_i_2_n_0\,
- CO(3 downto 2) => \NLW_s_counter_reg[31]_i_6_CO_UNCONNECTED\(3 downto 2),
- CO(1) => \s_counter_reg[31]_i_6_n_2\,
- CO(0) => \s_counter_reg[31]_i_6_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3) => \NLW_s_counter_reg[31]_i_6_O_UNCONNECTED\(3),
- O(2 downto 0) => data0(31 downto 29),
- S(3) => '0',
- S(2 downto 0) => s_counter(31 downto 29)
- );
-\s_counter_reg[3]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(3),
- Q => s_counter(3)
- );
-\s_counter_reg[4]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(4),
- Q => s_counter(4)
- );
-\s_counter_reg[4]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \s_counter_reg[4]_i_2_n_0\,
- CO(2) => \s_counter_reg[4]_i_2_n_1\,
- CO(1) => \s_counter_reg[4]_i_2_n_2\,
- CO(0) => \s_counter_reg[4]_i_2_n_3\,
- CYINIT => s_counter(0),
- DI(3 downto 0) => B"0000",
- O(3 downto 0) => data0(4 downto 1),
- S(3 downto 0) => s_counter(4 downto 1)
- );
-\s_counter_reg[5]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(5),
- Q => s_counter(5)
- );
-\s_counter_reg[6]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(6),
- Q => s_counter(6)
- );
-\s_counter_reg[7]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(7),
- Q => s_counter(7)
- );
-\s_counter_reg[8]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(8),
- Q => s_counter(8)
- );
-\s_counter_reg[8]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => \s_counter_reg[4]_i_2_n_0\,
- CO(3) => \s_counter_reg[8]_i_2_n_0\,
- CO(2) => \s_counter_reg[8]_i_2_n_1\,
- CO(1) => \s_counter_reg[8]_i_2_n_2\,
- CO(0) => \s_counter_reg[8]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3 downto 0) => data0(8 downto 5),
- S(3 downto 0) => s_counter(8 downto 5)
- );
-\s_counter_reg[9]\: unisim.vcomponents.FDCE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_counter_0(9),
- Q => s_counter(9)
- );
-s_temp_i_1: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFE0001"
- )
- port map (
- I0 => \s_counter[31]_i_2_n_0\,
- I1 => \s_counter[31]_i_3_n_0\,
- I2 => \s_counter[31]_i_4_n_0\,
- I3 => \s_counter[31]_i_5_n_0\,
- I4 => I,
- O => s_temp_i_1_n_0
- );
-s_temp_reg: unisim.vcomponents.FDCE
- generic map(
- INIT => '1'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- CLR => rst_i,
- D => s_temp_i_1_n_0,
- Q => I
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_147 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_147 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_147;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_147 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_150 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_150 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_150;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_150 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_153 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_153 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_153;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_153 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_156 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_156 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_156;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_156 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_159 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_159 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_159;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_159 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_162 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_162 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_162;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_162 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_165 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_165 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_165;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_165 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_168 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_168 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_168;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_168 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_171 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_171 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_171;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_171 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_174 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_174 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_174;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_174 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_177 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_177 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_177;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_177 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_180 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_180 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_180;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_180 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_183 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_183 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_183;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_183 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_186 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_186 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_186;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_186 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_189 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_189 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_189;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_189 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_192 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_192 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_192;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_192 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_195 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_195 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_195;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_195 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_198 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_198 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_198;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_198 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_201 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_201 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_201;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_201 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_204 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_204 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_204;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_204 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_44 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_44 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_44;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_44 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_47 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_47 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_47;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_47 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_50 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_50 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_50;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_50 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_53 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_53 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_53;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_53 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_56 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_56 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_56;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_56 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_59 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_59 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_59;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_59 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_62 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_62 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_62;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_62 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_65 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_65 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_65;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_65 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_68 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_68 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_68;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_68 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_71 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_71 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_71;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_71 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_74 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_74 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_74;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_74 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_77 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_77 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_77;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_77 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_80 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_80 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_80;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_80 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_83 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_83 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_83;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_83 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_86 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_86 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_86;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_86 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_89 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_89 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_89;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_89 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_92 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_92 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_92;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_92 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_95 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_95 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_95;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_95 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_counterUpDown_98 is
- port (
- count_o : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s_buff2_reg : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- E : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_counterUpDown_98 : entity is "counterUpDown";
-end system_design_fasec_hwtest_0_0_counterUpDown_98;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_counterUpDown_98 is
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 24 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_buff2_reg,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 24) => NLW_s_count_reg_P_UNCONNECTED(47 downto 24),
- P(23 downto 0) => count_o(23 downto 0),
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => E(0),
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__54_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__54_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__54_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__54_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__54_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__54_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__54_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__54_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__54\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__54_n_0\
- );
-\s_pulseLed_i_1__54\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__54_n_0\,
- I1 => \s_pulseLed_i_3__54_n_0\,
- I2 => \s_pulseLed_i_4__54_n_0\,
- I3 => \s_pulseLed_i_5__54_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__54\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__54_n_0\,
- O => \s_pulseLed_i_2__54_n_0\
- );
-\s_pulseLed_i_3__54\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__54_n_0\,
- O => \s_pulseLed_i_3__54_n_0\
- );
-\s_pulseLed_i_4__54\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__54_n_0\,
- O => \s_pulseLed_i_4__54_n_0\
- );
-\s_pulseLed_i_5__54\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__54_n_0\,
- O => \s_pulseLed_i_5__54_n_0\
- );
-\s_pulseLed_i_7__54\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__54_n_0\
- );
-\s_pulseLed_i_8__54\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__54_n_0\
- );
-\s_pulseLed_i_9__54\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__54_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_131\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_131\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_131\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_131\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__26_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__26_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__26_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__26_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__26_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__26_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__26_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__26_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__26\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__26_n_0\
- );
-\s_pulseLed_i_1__26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__26_n_0\,
- I1 => \s_pulseLed_i_3__26_n_0\,
- I2 => \s_pulseLed_i_4__26_n_0\,
- I3 => \s_pulseLed_i_5__26_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__26\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__26_n_0\,
- O => \s_pulseLed_i_2__26_n_0\
- );
-\s_pulseLed_i_3__26\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__26_n_0\,
- O => \s_pulseLed_i_3__26_n_0\
- );
-\s_pulseLed_i_4__26\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__26_n_0\,
- O => \s_pulseLed_i_4__26_n_0\
- );
-\s_pulseLed_i_5__26\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__26_n_0\,
- O => \s_pulseLed_i_5__26_n_0\
- );
-\s_pulseLed_i_7__26\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__26_n_0\
- );
-\s_pulseLed_i_8__26\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__26_n_0\
- );
-\s_pulseLed_i_9__26\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__26_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_133\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_133\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_133\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_133\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__25_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__25_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__25_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__25_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__25_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__25_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__25_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__25_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__25\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__25_n_0\
- );
-\s_pulseLed_i_1__25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__25_n_0\,
- I1 => \s_pulseLed_i_3__25_n_0\,
- I2 => \s_pulseLed_i_4__25_n_0\,
- I3 => \s_pulseLed_i_5__25_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__25\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__25_n_0\,
- O => \s_pulseLed_i_2__25_n_0\
- );
-\s_pulseLed_i_3__25\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__25_n_0\,
- O => \s_pulseLed_i_3__25_n_0\
- );
-\s_pulseLed_i_4__25\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__25_n_0\,
- O => \s_pulseLed_i_4__25_n_0\
- );
-\s_pulseLed_i_5__25\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__25_n_0\,
- O => \s_pulseLed_i_5__25_n_0\
- );
-\s_pulseLed_i_7__25\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__25_n_0\
- );
-\s_pulseLed_i_8__25\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__25_n_0\
- );
-\s_pulseLed_i_9__25\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__25_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_135\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_135\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_135\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_135\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__24_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__24_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__24_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__24_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__24_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__24_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__24_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__24_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__24\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__24_n_0\
- );
-\s_pulseLed_i_1__24\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__24_n_0\,
- I1 => \s_pulseLed_i_3__24_n_0\,
- I2 => \s_pulseLed_i_4__24_n_0\,
- I3 => \s_pulseLed_i_5__24_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__24\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__24_n_0\,
- O => \s_pulseLed_i_2__24_n_0\
- );
-\s_pulseLed_i_3__24\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__24_n_0\,
- O => \s_pulseLed_i_3__24_n_0\
- );
-\s_pulseLed_i_4__24\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__24_n_0\,
- O => \s_pulseLed_i_4__24_n_0\
- );
-\s_pulseLed_i_5__24\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__24_n_0\,
- O => \s_pulseLed_i_5__24_n_0\
- );
-\s_pulseLed_i_7__24\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__24_n_0\
- );
-\s_pulseLed_i_8__24\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__24_n_0\
- );
-\s_pulseLed_i_9__24\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__24_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_137\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_137\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_137\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_137\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__23_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__23_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__23_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__23_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__23_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__23_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__23_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__23_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__23_n_0\
- );
-\s_pulseLed_i_1__23\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__23_n_0\,
- I1 => \s_pulseLed_i_3__23_n_0\,
- I2 => \s_pulseLed_i_4__23_n_0\,
- I3 => \s_pulseLed_i_5__23_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__23\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__23_n_0\,
- O => \s_pulseLed_i_2__23_n_0\
- );
-\s_pulseLed_i_3__23\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__23_n_0\,
- O => \s_pulseLed_i_3__23_n_0\
- );
-\s_pulseLed_i_4__23\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__23_n_0\,
- O => \s_pulseLed_i_4__23_n_0\
- );
-\s_pulseLed_i_5__23\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__23_n_0\,
- O => \s_pulseLed_i_5__23_n_0\
- );
-\s_pulseLed_i_7__23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__23_n_0\
- );
-\s_pulseLed_i_8__23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__23_n_0\
- );
-\s_pulseLed_i_9__23\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__23_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_139\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_139\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_139\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_139\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__22_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__22_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__22_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__22_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__22_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__22_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__22_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__22_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__22\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__22_n_0\
- );
-\s_pulseLed_i_1__22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__22_n_0\,
- I1 => \s_pulseLed_i_3__22_n_0\,
- I2 => \s_pulseLed_i_4__22_n_0\,
- I3 => \s_pulseLed_i_5__22_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__22\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__22_n_0\,
- O => \s_pulseLed_i_2__22_n_0\
- );
-\s_pulseLed_i_3__22\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__22_n_0\,
- O => \s_pulseLed_i_3__22_n_0\
- );
-\s_pulseLed_i_4__22\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__22_n_0\,
- O => \s_pulseLed_i_4__22_n_0\
- );
-\s_pulseLed_i_5__22\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__22_n_0\,
- O => \s_pulseLed_i_5__22_n_0\
- );
-\s_pulseLed_i_7__22\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__22_n_0\
- );
-\s_pulseLed_i_8__22\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__22_n_0\
- );
-\s_pulseLed_i_9__22\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__22_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_141\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_141\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_141\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_141\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__21_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__21_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__21_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__21_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__21_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__21_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__21_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__21_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__21\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__21_n_0\
- );
-\s_pulseLed_i_1__21\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__21_n_0\,
- I1 => \s_pulseLed_i_3__21_n_0\,
- I2 => \s_pulseLed_i_4__21_n_0\,
- I3 => \s_pulseLed_i_5__21_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__21\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__21_n_0\,
- O => \s_pulseLed_i_2__21_n_0\
- );
-\s_pulseLed_i_3__21\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__21_n_0\,
- O => \s_pulseLed_i_3__21_n_0\
- );
-\s_pulseLed_i_4__21\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__21_n_0\,
- O => \s_pulseLed_i_4__21_n_0\
- );
-\s_pulseLed_i_5__21\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__21_n_0\,
- O => \s_pulseLed_i_5__21_n_0\
- );
-\s_pulseLed_i_7__21\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__21_n_0\
- );
-\s_pulseLed_i_8__21\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__21_n_0\
- );
-\s_pulseLed_i_9__21\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__21_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_143\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_143\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_143\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_143\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__20_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__20_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__20_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__20_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__20_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__20_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__20_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__20_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__20\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__20_n_0\
- );
-\s_pulseLed_i_1__20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__20_n_0\,
- I1 => \s_pulseLed_i_3__20_n_0\,
- I2 => \s_pulseLed_i_4__20_n_0\,
- I3 => \s_pulseLed_i_5__20_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__20\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__20_n_0\,
- O => \s_pulseLed_i_2__20_n_0\
- );
-\s_pulseLed_i_3__20\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__20_n_0\,
- O => \s_pulseLed_i_3__20_n_0\
- );
-\s_pulseLed_i_4__20\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__20_n_0\,
- O => \s_pulseLed_i_4__20_n_0\
- );
-\s_pulseLed_i_5__20\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__20_n_0\,
- O => \s_pulseLed_i_5__20_n_0\
- );
-\s_pulseLed_i_7__20\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__20_n_0\
- );
-\s_pulseLed_i_8__20\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__20_n_0\
- );
-\s_pulseLed_i_9__20\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__20_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_145\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_145\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_145\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_145\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__19_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__19_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__19_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__19_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__19_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__19_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__19_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__19_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__19\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__19_n_0\
- );
-\s_pulseLed_i_1__19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__19_n_0\,
- I1 => \s_pulseLed_i_3__19_n_0\,
- I2 => \s_pulseLed_i_4__19_n_0\,
- I3 => \s_pulseLed_i_5__19_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__19_n_0\,
- O => \s_pulseLed_i_2__19_n_0\
- );
-\s_pulseLed_i_3__19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__19_n_0\,
- O => \s_pulseLed_i_3__19_n_0\
- );
-\s_pulseLed_i_4__19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__19_n_0\,
- O => \s_pulseLed_i_4__19_n_0\
- );
-\s_pulseLed_i_5__19\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__19_n_0\,
- O => \s_pulseLed_i_5__19_n_0\
- );
-\s_pulseLed_i_7__19\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__19_n_0\
- );
-\s_pulseLed_i_8__19\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__19_n_0\
- );
-\s_pulseLed_i_9__19\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__19_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_148\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_148\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_148\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_148\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__8_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__8_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__8_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__8_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__8_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__8_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__8_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__8_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__8\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__8_n_0\
- );
-\s_pulseLed_i_1__8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__8_n_0\,
- I1 => \s_pulseLed_i_3__8_n_0\,
- I2 => \s_pulseLed_i_4__8_n_0\,
- I3 => \s_pulseLed_i_5__8_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__8\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__8_n_0\,
- O => \s_pulseLed_i_2__8_n_0\
- );
-\s_pulseLed_i_3__8\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__8_n_0\,
- O => \s_pulseLed_i_3__8_n_0\
- );
-\s_pulseLed_i_4__8\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__8_n_0\,
- O => \s_pulseLed_i_4__8_n_0\
- );
-\s_pulseLed_i_5__8\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__8_n_0\,
- O => \s_pulseLed_i_5__8_n_0\
- );
-\s_pulseLed_i_7__8\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__8_n_0\
- );
-\s_pulseLed_i_8__8\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__8_n_0\
- );
-\s_pulseLed_i_9__8\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__8_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_151\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_151\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_151\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_151\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__7_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__7_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__7_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__7_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__7_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__7_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__7_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__7_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__7\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__7_n_0\
- );
-\s_pulseLed_i_1__7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__7_n_0\,
- I1 => \s_pulseLed_i_3__7_n_0\,
- I2 => \s_pulseLed_i_4__7_n_0\,
- I3 => \s_pulseLed_i_5__7_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__7\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__7_n_0\,
- O => \s_pulseLed_i_2__7_n_0\
- );
-\s_pulseLed_i_3__7\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__7_n_0\,
- O => \s_pulseLed_i_3__7_n_0\
- );
-\s_pulseLed_i_4__7\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__7_n_0\,
- O => \s_pulseLed_i_4__7_n_0\
- );
-\s_pulseLed_i_5__7\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__7_n_0\,
- O => \s_pulseLed_i_5__7_n_0\
- );
-\s_pulseLed_i_7__7\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__7_n_0\
- );
-\s_pulseLed_i_8__7\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__7_n_0\
- );
-\s_pulseLed_i_9__7\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__7_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_154\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_154\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_154\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_154\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__6_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__6_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__6_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__6_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__6_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__6_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__6_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__6_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__6\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__6_n_0\
- );
-\s_pulseLed_i_1__6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__6_n_0\,
- I1 => \s_pulseLed_i_3__6_n_0\,
- I2 => \s_pulseLed_i_4__6_n_0\,
- I3 => \s_pulseLed_i_5__6_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__6\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__6_n_0\,
- O => \s_pulseLed_i_2__6_n_0\
- );
-\s_pulseLed_i_3__6\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__6_n_0\,
- O => \s_pulseLed_i_3__6_n_0\
- );
-\s_pulseLed_i_4__6\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__6_n_0\,
- O => \s_pulseLed_i_4__6_n_0\
- );
-\s_pulseLed_i_5__6\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__6_n_0\,
- O => \s_pulseLed_i_5__6_n_0\
- );
-\s_pulseLed_i_7__6\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__6_n_0\
- );
-\s_pulseLed_i_8__6\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__6_n_0\
- );
-\s_pulseLed_i_9__6\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__6_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_157\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_157\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_157\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_157\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__5_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__5_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__5_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__5_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__5_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__5_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__5_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__5_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__5\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__5_n_0\
- );
-\s_pulseLed_i_1__5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__5_n_0\,
- I1 => \s_pulseLed_i_3__5_n_0\,
- I2 => \s_pulseLed_i_4__5_n_0\,
- I3 => \s_pulseLed_i_5__5_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__5\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__5_n_0\,
- O => \s_pulseLed_i_2__5_n_0\
- );
-\s_pulseLed_i_3__5\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__5_n_0\,
- O => \s_pulseLed_i_3__5_n_0\
- );
-\s_pulseLed_i_4__5\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__5_n_0\,
- O => \s_pulseLed_i_4__5_n_0\
- );
-\s_pulseLed_i_5__5\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__5_n_0\,
- O => \s_pulseLed_i_5__5_n_0\
- );
-\s_pulseLed_i_7__5\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__5_n_0\
- );
-\s_pulseLed_i_8__5\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__5_n_0\
- );
-\s_pulseLed_i_9__5\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__5_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_160\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_160\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_160\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_160\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__4_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__4_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__4_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__4_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__4_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__4_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__4_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__4_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__4\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__4_n_0\
- );
-\s_pulseLed_i_1__4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__4_n_0\,
- I1 => \s_pulseLed_i_3__4_n_0\,
- I2 => \s_pulseLed_i_4__4_n_0\,
- I3 => \s_pulseLed_i_5__4_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__4\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__4_n_0\,
- O => \s_pulseLed_i_2__4_n_0\
- );
-\s_pulseLed_i_3__4\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__4_n_0\,
- O => \s_pulseLed_i_3__4_n_0\
- );
-\s_pulseLed_i_4__4\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__4_n_0\,
- O => \s_pulseLed_i_4__4_n_0\
- );
-\s_pulseLed_i_5__4\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__4_n_0\,
- O => \s_pulseLed_i_5__4_n_0\
- );
-\s_pulseLed_i_7__4\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__4_n_0\
- );
-\s_pulseLed_i_8__4\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__4_n_0\
- );
-\s_pulseLed_i_9__4\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__4_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_163\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_163\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_163\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_163\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__3_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__3_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__3_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__3_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__3_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__3_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__3_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__3_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__3_n_0\
- );
-\s_pulseLed_i_1__3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__3_n_0\,
- I1 => \s_pulseLed_i_3__3_n_0\,
- I2 => \s_pulseLed_i_4__3_n_0\,
- I3 => \s_pulseLed_i_5__3_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__3_n_0\,
- O => \s_pulseLed_i_2__3_n_0\
- );
-\s_pulseLed_i_3__3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__3_n_0\,
- O => \s_pulseLed_i_3__3_n_0\
- );
-\s_pulseLed_i_4__3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__3_n_0\,
- O => \s_pulseLed_i_4__3_n_0\
- );
-\s_pulseLed_i_5__3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__3_n_0\,
- O => \s_pulseLed_i_5__3_n_0\
- );
-\s_pulseLed_i_7__3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__3_n_0\
- );
-\s_pulseLed_i_8__3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__3_n_0\
- );
-\s_pulseLed_i_9__3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__3_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_166\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_166\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_166\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_166\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__2_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__2_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__2_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__2_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__2_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__2_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__2_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__2_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__2\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__2_n_0\
- );
-\s_pulseLed_i_1__2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__2_n_0\,
- I1 => \s_pulseLed_i_3__2_n_0\,
- I2 => \s_pulseLed_i_4__2_n_0\,
- I3 => \s_pulseLed_i_5__2_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__2_n_0\,
- O => \s_pulseLed_i_2__2_n_0\
- );
-\s_pulseLed_i_3__2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__2_n_0\,
- O => \s_pulseLed_i_3__2_n_0\
- );
-\s_pulseLed_i_4__2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__2_n_0\,
- O => \s_pulseLed_i_4__2_n_0\
- );
-\s_pulseLed_i_5__2\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__2_n_0\,
- O => \s_pulseLed_i_5__2_n_0\
- );
-\s_pulseLed_i_7__2\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__2_n_0\
- );
-\s_pulseLed_i_8__2\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__2_n_0\
- );
-\s_pulseLed_i_9__2\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__2_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_169\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_169\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_169\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_169\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__1_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__1_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__1_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__1_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__1_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__1_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__1_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__1_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__1_n_0\
- );
-\s_pulseLed_i_1__1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__1_n_0\,
- I1 => \s_pulseLed_i_3__1_n_0\,
- I2 => \s_pulseLed_i_4__1_n_0\,
- I3 => \s_pulseLed_i_5__1_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__1_n_0\,
- O => \s_pulseLed_i_2__1_n_0\
- );
-\s_pulseLed_i_3__1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__1_n_0\,
- O => \s_pulseLed_i_3__1_n_0\
- );
-\s_pulseLed_i_4__1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__1_n_0\,
- O => \s_pulseLed_i_4__1_n_0\
- );
-\s_pulseLed_i_5__1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__1_n_0\,
- O => \s_pulseLed_i_5__1_n_0\
- );
-\s_pulseLed_i_7__1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__1_n_0\
- );
-\s_pulseLed_i_8__1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__1_n_0\
- );
-\s_pulseLed_i_9__1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__1_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_172\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_172\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_172\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_172\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__0_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__0_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__0_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__0_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__0_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__0_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__0_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__0_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__0_n_0\
- );
-\s_pulseLed_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__0_n_0\,
- I1 => \s_pulseLed_i_3__0_n_0\,
- I2 => \s_pulseLed_i_4__0_n_0\,
- I3 => \s_pulseLed_i_5__0_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__0_n_0\,
- O => \s_pulseLed_i_2__0_n_0\
- );
-\s_pulseLed_i_3__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__0_n_0\,
- O => \s_pulseLed_i_3__0_n_0\
- );
-\s_pulseLed_i_4__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__0_n_0\,
- O => \s_pulseLed_i_4__0_n_0\
- );
-\s_pulseLed_i_5__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__0_n_0\,
- O => \s_pulseLed_i_5__0_n_0\
- );
-\s_pulseLed_i_7__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__0_n_0\
- );
-\s_pulseLed_i_8__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__0_n_0\
- );
-\s_pulseLed_i_9__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__0_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_175\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_175\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_175\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_175\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__18_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__18_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__18_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__18_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__18_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__18_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__18_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__18_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__18\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__18_n_0\
- );
-\s_pulseLed_i_1__18\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__18_n_0\,
- I1 => \s_pulseLed_i_3__18_n_0\,
- I2 => \s_pulseLed_i_4__18_n_0\,
- I3 => \s_pulseLed_i_5__18_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__18\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__18_n_0\,
- O => \s_pulseLed_i_2__18_n_0\
- );
-\s_pulseLed_i_3__18\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__18_n_0\,
- O => \s_pulseLed_i_3__18_n_0\
- );
-\s_pulseLed_i_4__18\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__18_n_0\,
- O => \s_pulseLed_i_4__18_n_0\
- );
-\s_pulseLed_i_5__18\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__18_n_0\,
- O => \s_pulseLed_i_5__18_n_0\
- );
-\s_pulseLed_i_7__18\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__18_n_0\
- );
-\s_pulseLed_i_8__18\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__18_n_0\
- );
-\s_pulseLed_i_9__18\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__18_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_178\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_178\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_178\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_178\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__17_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__17_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__17_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__17_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__17_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__17_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__17_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__17_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__17\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__17_n_0\
- );
-\s_pulseLed_i_1__17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__17_n_0\,
- I1 => \s_pulseLed_i_3__17_n_0\,
- I2 => \s_pulseLed_i_4__17_n_0\,
- I3 => \s_pulseLed_i_5__17_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__17\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__17_n_0\,
- O => \s_pulseLed_i_2__17_n_0\
- );
-\s_pulseLed_i_3__17\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__17_n_0\,
- O => \s_pulseLed_i_3__17_n_0\
- );
-\s_pulseLed_i_4__17\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__17_n_0\,
- O => \s_pulseLed_i_4__17_n_0\
- );
-\s_pulseLed_i_5__17\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__17_n_0\,
- O => \s_pulseLed_i_5__17_n_0\
- );
-\s_pulseLed_i_7__17\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__17_n_0\
- );
-\s_pulseLed_i_8__17\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__17_n_0\
- );
-\s_pulseLed_i_9__17\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__17_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_181\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_181\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_181\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_181\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__16_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__16_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__16_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__16_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__16_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__16_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__16_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__16_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__16\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__16_n_0\
- );
-\s_pulseLed_i_1__16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__16_n_0\,
- I1 => \s_pulseLed_i_3__16_n_0\,
- I2 => \s_pulseLed_i_4__16_n_0\,
- I3 => \s_pulseLed_i_5__16_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__16\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__16_n_0\,
- O => \s_pulseLed_i_2__16_n_0\
- );
-\s_pulseLed_i_3__16\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__16_n_0\,
- O => \s_pulseLed_i_3__16_n_0\
- );
-\s_pulseLed_i_4__16\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__16_n_0\,
- O => \s_pulseLed_i_4__16_n_0\
- );
-\s_pulseLed_i_5__16\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__16_n_0\,
- O => \s_pulseLed_i_5__16_n_0\
- );
-\s_pulseLed_i_7__16\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__16_n_0\
- );
-\s_pulseLed_i_8__16\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__16_n_0\
- );
-\s_pulseLed_i_9__16\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__16_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_184\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_184\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_184\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_184\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__15_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__15_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__15_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__15_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__15_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__15_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__15_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__15_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__15\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__15_n_0\
- );
-\s_pulseLed_i_1__15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__15_n_0\,
- I1 => \s_pulseLed_i_3__15_n_0\,
- I2 => \s_pulseLed_i_4__15_n_0\,
- I3 => \s_pulseLed_i_5__15_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__15\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__15_n_0\,
- O => \s_pulseLed_i_2__15_n_0\
- );
-\s_pulseLed_i_3__15\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__15_n_0\,
- O => \s_pulseLed_i_3__15_n_0\
- );
-\s_pulseLed_i_4__15\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__15_n_0\,
- O => \s_pulseLed_i_4__15_n_0\
- );
-\s_pulseLed_i_5__15\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__15_n_0\,
- O => \s_pulseLed_i_5__15_n_0\
- );
-\s_pulseLed_i_7__15\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__15_n_0\
- );
-\s_pulseLed_i_8__15\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__15_n_0\
- );
-\s_pulseLed_i_9__15\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__15_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_187\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_187\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_187\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_187\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__14_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__14_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__14_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__14_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__14_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__14_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__14_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__14_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__14\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__14_n_0\
- );
-\s_pulseLed_i_1__14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__14_n_0\,
- I1 => \s_pulseLed_i_3__14_n_0\,
- I2 => \s_pulseLed_i_4__14_n_0\,
- I3 => \s_pulseLed_i_5__14_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__14_n_0\,
- O => \s_pulseLed_i_2__14_n_0\
- );
-\s_pulseLed_i_3__14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__14_n_0\,
- O => \s_pulseLed_i_3__14_n_0\
- );
-\s_pulseLed_i_4__14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__14_n_0\,
- O => \s_pulseLed_i_4__14_n_0\
- );
-\s_pulseLed_i_5__14\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__14_n_0\,
- O => \s_pulseLed_i_5__14_n_0\
- );
-\s_pulseLed_i_7__14\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__14_n_0\
- );
-\s_pulseLed_i_8__14\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__14_n_0\
- );
-\s_pulseLed_i_9__14\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__14_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_190\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_190\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_190\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_190\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__13_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__13_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__13_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__13_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__13_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__13_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__13_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__13_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__13\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__13_n_0\
- );
-\s_pulseLed_i_1__13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__13_n_0\,
- I1 => \s_pulseLed_i_3__13_n_0\,
- I2 => \s_pulseLed_i_4__13_n_0\,
- I3 => \s_pulseLed_i_5__13_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__13_n_0\,
- O => \s_pulseLed_i_2__13_n_0\
- );
-\s_pulseLed_i_3__13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__13_n_0\,
- O => \s_pulseLed_i_3__13_n_0\
- );
-\s_pulseLed_i_4__13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__13_n_0\,
- O => \s_pulseLed_i_4__13_n_0\
- );
-\s_pulseLed_i_5__13\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__13_n_0\,
- O => \s_pulseLed_i_5__13_n_0\
- );
-\s_pulseLed_i_7__13\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__13_n_0\
- );
-\s_pulseLed_i_8__13\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__13_n_0\
- );
-\s_pulseLed_i_9__13\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__13_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_193\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_193\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_193\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_193\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__12_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__12_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__12_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__12_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__12_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__12_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__12_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__12_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__12\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__12_n_0\
- );
-\s_pulseLed_i_1__12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__12_n_0\,
- I1 => \s_pulseLed_i_3__12_n_0\,
- I2 => \s_pulseLed_i_4__12_n_0\,
- I3 => \s_pulseLed_i_5__12_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__12\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__12_n_0\,
- O => \s_pulseLed_i_2__12_n_0\
- );
-\s_pulseLed_i_3__12\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__12_n_0\,
- O => \s_pulseLed_i_3__12_n_0\
- );
-\s_pulseLed_i_4__12\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__12_n_0\,
- O => \s_pulseLed_i_4__12_n_0\
- );
-\s_pulseLed_i_5__12\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__12_n_0\,
- O => \s_pulseLed_i_5__12_n_0\
- );
-\s_pulseLed_i_7__12\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__12_n_0\
- );
-\s_pulseLed_i_8__12\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__12_n_0\
- );
-\s_pulseLed_i_9__12\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__12_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_196\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_196\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_196\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_196\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__11_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__11_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__11_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__11_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__11_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__11_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__11_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__11_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__11\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__11_n_0\
- );
-\s_pulseLed_i_1__11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__11_n_0\,
- I1 => \s_pulseLed_i_3__11_n_0\,
- I2 => \s_pulseLed_i_4__11_n_0\,
- I3 => \s_pulseLed_i_5__11_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__11\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__11_n_0\,
- O => \s_pulseLed_i_2__11_n_0\
- );
-\s_pulseLed_i_3__11\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__11_n_0\,
- O => \s_pulseLed_i_3__11_n_0\
- );
-\s_pulseLed_i_4__11\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__11_n_0\,
- O => \s_pulseLed_i_4__11_n_0\
- );
-\s_pulseLed_i_5__11\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__11_n_0\,
- O => \s_pulseLed_i_5__11_n_0\
- );
-\s_pulseLed_i_7__11\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__11_n_0\
- );
-\s_pulseLed_i_8__11\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__11_n_0\
- );
-\s_pulseLed_i_9__11\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__11_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_199\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_199\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_199\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_199\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__10_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__10_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__10_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__10_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__10_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__10_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__10_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__10_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__10\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__10_n_0\
- );
-\s_pulseLed_i_1__10\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__10_n_0\,
- I1 => \s_pulseLed_i_3__10_n_0\,
- I2 => \s_pulseLed_i_4__10_n_0\,
- I3 => \s_pulseLed_i_5__10_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__10\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__10_n_0\,
- O => \s_pulseLed_i_2__10_n_0\
- );
-\s_pulseLed_i_3__10\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__10_n_0\,
- O => \s_pulseLed_i_3__10_n_0\
- );
-\s_pulseLed_i_4__10\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__10_n_0\,
- O => \s_pulseLed_i_4__10_n_0\
- );
-\s_pulseLed_i_5__10\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__10_n_0\,
- O => \s_pulseLed_i_5__10_n_0\
- );
-\s_pulseLed_i_7__10\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__10_n_0\
- );
-\s_pulseLed_i_8__10\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__10_n_0\
- );
-\s_pulseLed_i_9__10\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__10_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_202\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_202\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_202\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_202\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__9_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__9_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__9_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__9_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__9_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__9_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__9_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__9_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__9\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__9_n_0\
- );
-\s_pulseLed_i_1__9\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__9_n_0\,
- I1 => \s_pulseLed_i_3__9_n_0\,
- I2 => \s_pulseLed_i_4__9_n_0\,
- I3 => \s_pulseLed_i_5__9_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__9\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__9_n_0\,
- O => \s_pulseLed_i_2__9_n_0\
- );
-\s_pulseLed_i_3__9\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__9_n_0\,
- O => \s_pulseLed_i_3__9_n_0\
- );
-\s_pulseLed_i_4__9\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__9_n_0\,
- O => \s_pulseLed_i_4__9_n_0\
- );
-\s_pulseLed_i_5__9\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__9_n_0\,
- O => \s_pulseLed_i_5__9_n_0\
- );
-\s_pulseLed_i_7__9\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__9_n_0\
- );
-\s_pulseLed_i_8__9\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__9_n_0\
- );
-\s_pulseLed_i_9__9\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__9_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_205\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_205\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_205\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_205\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal s_pulseLed_i_10_n_0 : STD_LOGIC;
- signal s_pulseLed_i_2_n_0 : STD_LOGIC;
- signal s_pulseLed_i_3_n_0 : STD_LOGIC;
- signal s_pulseLed_i_4_n_0 : STD_LOGIC;
- signal s_pulseLed_i_5_n_0 : STD_LOGIC;
- signal s_pulseLed_i_7_n_0 : STD_LOGIC;
- signal s_pulseLed_i_8_n_0 : STD_LOGIC;
- signal s_pulseLed_i_9_n_0 : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-s_pulseLed_i_1: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => s_pulseLed_i_2_n_0,
- I1 => s_pulseLed_i_3_n_0,
- I2 => s_pulseLed_i_4_n_0,
- I3 => s_pulseLed_i_5_n_0,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-s_pulseLed_i_10: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => s_pulseLed_i_10_n_0
- );
-s_pulseLed_i_2: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => s_pulseLed_i_7_n_0,
- O => s_pulseLed_i_2_n_0
- );
-s_pulseLed_i_3: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => s_pulseLed_i_8_n_0,
- O => s_pulseLed_i_3_n_0
- );
-s_pulseLed_i_4: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => s_pulseLed_i_9_n_0,
- O => s_pulseLed_i_4_n_0
- );
-s_pulseLed_i_5: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => s_pulseLed_i_10_n_0,
- O => s_pulseLed_i_5_n_0
- );
-s_pulseLed_i_7: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => s_pulseLed_i_7_n_0
- );
-s_pulseLed_i_8: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => s_pulseLed_i_8_n_0
- );
-s_pulseLed_i_9: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => s_pulseLed_i_9_n_0
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_28\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_28\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_28\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_28\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__53_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__53_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__53_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__53_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__53_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__53_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__53_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__53_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__53\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__53_n_0\
- );
-\s_pulseLed_i_1__53\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__53_n_0\,
- I1 => \s_pulseLed_i_3__53_n_0\,
- I2 => \s_pulseLed_i_4__53_n_0\,
- I3 => \s_pulseLed_i_5__53_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__53\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__53_n_0\,
- O => \s_pulseLed_i_2__53_n_0\
- );
-\s_pulseLed_i_3__53\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__53_n_0\,
- O => \s_pulseLed_i_3__53_n_0\
- );
-\s_pulseLed_i_4__53\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__53_n_0\,
- O => \s_pulseLed_i_4__53_n_0\
- );
-\s_pulseLed_i_5__53\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__53_n_0\,
- O => \s_pulseLed_i_5__53_n_0\
- );
-\s_pulseLed_i_7__53\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__53_n_0\
- );
-\s_pulseLed_i_8__53\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__53_n_0\
- );
-\s_pulseLed_i_9__53\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__53_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_30\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_30\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_30\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_30\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__52_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__52_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__52_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__52_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__52_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__52_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__52_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__52_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__52\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__52_n_0\
- );
-\s_pulseLed_i_1__52\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__52_n_0\,
- I1 => \s_pulseLed_i_3__52_n_0\,
- I2 => \s_pulseLed_i_4__52_n_0\,
- I3 => \s_pulseLed_i_5__52_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__52\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__52_n_0\,
- O => \s_pulseLed_i_2__52_n_0\
- );
-\s_pulseLed_i_3__52\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__52_n_0\,
- O => \s_pulseLed_i_3__52_n_0\
- );
-\s_pulseLed_i_4__52\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__52_n_0\,
- O => \s_pulseLed_i_4__52_n_0\
- );
-\s_pulseLed_i_5__52\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__52_n_0\,
- O => \s_pulseLed_i_5__52_n_0\
- );
-\s_pulseLed_i_7__52\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__52_n_0\
- );
-\s_pulseLed_i_8__52\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__52_n_0\
- );
-\s_pulseLed_i_9__52\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__52_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_32\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_32\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_32\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_32\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__51_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__51_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__51_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__51_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__51_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__51_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__51_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__51_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__51\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__51_n_0\
- );
-\s_pulseLed_i_1__51\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__51_n_0\,
- I1 => \s_pulseLed_i_3__51_n_0\,
- I2 => \s_pulseLed_i_4__51_n_0\,
- I3 => \s_pulseLed_i_5__51_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__51\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__51_n_0\,
- O => \s_pulseLed_i_2__51_n_0\
- );
-\s_pulseLed_i_3__51\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__51_n_0\,
- O => \s_pulseLed_i_3__51_n_0\
- );
-\s_pulseLed_i_4__51\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__51_n_0\,
- O => \s_pulseLed_i_4__51_n_0\
- );
-\s_pulseLed_i_5__51\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__51_n_0\,
- O => \s_pulseLed_i_5__51_n_0\
- );
-\s_pulseLed_i_7__51\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__51_n_0\
- );
-\s_pulseLed_i_8__51\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__51_n_0\
- );
-\s_pulseLed_i_9__51\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__51_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_34\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_34\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_34\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_34\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__50_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__50_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__50_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__50_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__50_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__50_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__50_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__50_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__50\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__50_n_0\
- );
-\s_pulseLed_i_1__50\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__50_n_0\,
- I1 => \s_pulseLed_i_3__50_n_0\,
- I2 => \s_pulseLed_i_4__50_n_0\,
- I3 => \s_pulseLed_i_5__50_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__50\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__50_n_0\,
- O => \s_pulseLed_i_2__50_n_0\
- );
-\s_pulseLed_i_3__50\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__50_n_0\,
- O => \s_pulseLed_i_3__50_n_0\
- );
-\s_pulseLed_i_4__50\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__50_n_0\,
- O => \s_pulseLed_i_4__50_n_0\
- );
-\s_pulseLed_i_5__50\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__50_n_0\,
- O => \s_pulseLed_i_5__50_n_0\
- );
-\s_pulseLed_i_7__50\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__50_n_0\
- );
-\s_pulseLed_i_8__50\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__50_n_0\
- );
-\s_pulseLed_i_9__50\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__50_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_36\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_36\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_36\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_36\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__49_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__49_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__49_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__49_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__49_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__49_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__49_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__49_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__49\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__49_n_0\
- );
-\s_pulseLed_i_1__49\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__49_n_0\,
- I1 => \s_pulseLed_i_3__49_n_0\,
- I2 => \s_pulseLed_i_4__49_n_0\,
- I3 => \s_pulseLed_i_5__49_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__49\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__49_n_0\,
- O => \s_pulseLed_i_2__49_n_0\
- );
-\s_pulseLed_i_3__49\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__49_n_0\,
- O => \s_pulseLed_i_3__49_n_0\
- );
-\s_pulseLed_i_4__49\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__49_n_0\,
- O => \s_pulseLed_i_4__49_n_0\
- );
-\s_pulseLed_i_5__49\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__49_n_0\,
- O => \s_pulseLed_i_5__49_n_0\
- );
-\s_pulseLed_i_7__49\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__49_n_0\
- );
-\s_pulseLed_i_8__49\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__49_n_0\
- );
-\s_pulseLed_i_9__49\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__49_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_38\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_38\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_38\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_38\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__48_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__48_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__48_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__48_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__48_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__48_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__48_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__48_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__48\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__48_n_0\
- );
-\s_pulseLed_i_1__48\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__48_n_0\,
- I1 => \s_pulseLed_i_3__48_n_0\,
- I2 => \s_pulseLed_i_4__48_n_0\,
- I3 => \s_pulseLed_i_5__48_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__48\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__48_n_0\,
- O => \s_pulseLed_i_2__48_n_0\
- );
-\s_pulseLed_i_3__48\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__48_n_0\,
- O => \s_pulseLed_i_3__48_n_0\
- );
-\s_pulseLed_i_4__48\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__48_n_0\,
- O => \s_pulseLed_i_4__48_n_0\
- );
-\s_pulseLed_i_5__48\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__48_n_0\,
- O => \s_pulseLed_i_5__48_n_0\
- );
-\s_pulseLed_i_7__48\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__48_n_0\
- );
-\s_pulseLed_i_8__48\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__48_n_0\
- );
-\s_pulseLed_i_9__48\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__48_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_40\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_40\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_40\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_40\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__47_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__47_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__47_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__47_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__47_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__47_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__47_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__47_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__47\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__47_n_0\
- );
-\s_pulseLed_i_1__47\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__47_n_0\,
- I1 => \s_pulseLed_i_3__47_n_0\,
- I2 => \s_pulseLed_i_4__47_n_0\,
- I3 => \s_pulseLed_i_5__47_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__47\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__47_n_0\,
- O => \s_pulseLed_i_2__47_n_0\
- );
-\s_pulseLed_i_3__47\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__47_n_0\,
- O => \s_pulseLed_i_3__47_n_0\
- );
-\s_pulseLed_i_4__47\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__47_n_0\,
- O => \s_pulseLed_i_4__47_n_0\
- );
-\s_pulseLed_i_5__47\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__47_n_0\,
- O => \s_pulseLed_i_5__47_n_0\
- );
-\s_pulseLed_i_7__47\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__47_n_0\
- );
-\s_pulseLed_i_8__47\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__47_n_0\
- );
-\s_pulseLed_i_9__47\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__47_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_42\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_42\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_42\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_42\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__36_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__36_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__36_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__36_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__36_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__36_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__36_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__36_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__36\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__36_n_0\
- );
-\s_pulseLed_i_1__36\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__36_n_0\,
- I1 => \s_pulseLed_i_3__36_n_0\,
- I2 => \s_pulseLed_i_4__36_n_0\,
- I3 => \s_pulseLed_i_5__36_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__36\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__36_n_0\,
- O => \s_pulseLed_i_2__36_n_0\
- );
-\s_pulseLed_i_3__36\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__36_n_0\,
- O => \s_pulseLed_i_3__36_n_0\
- );
-\s_pulseLed_i_4__36\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__36_n_0\,
- O => \s_pulseLed_i_4__36_n_0\
- );
-\s_pulseLed_i_5__36\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__36_n_0\,
- O => \s_pulseLed_i_5__36_n_0\
- );
-\s_pulseLed_i_7__36\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__36_n_0\
- );
-\s_pulseLed_i_8__36\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__36_n_0\
- );
-\s_pulseLed_i_9__36\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__36_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_45\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_45\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_45\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_45\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__35_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__35_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__35_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__35_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__35_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__35_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__35_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__35_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__35\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__35_n_0\
- );
-\s_pulseLed_i_1__35\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__35_n_0\,
- I1 => \s_pulseLed_i_3__35_n_0\,
- I2 => \s_pulseLed_i_4__35_n_0\,
- I3 => \s_pulseLed_i_5__35_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__35\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__35_n_0\,
- O => \s_pulseLed_i_2__35_n_0\
- );
-\s_pulseLed_i_3__35\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__35_n_0\,
- O => \s_pulseLed_i_3__35_n_0\
- );
-\s_pulseLed_i_4__35\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__35_n_0\,
- O => \s_pulseLed_i_4__35_n_0\
- );
-\s_pulseLed_i_5__35\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__35_n_0\,
- O => \s_pulseLed_i_5__35_n_0\
- );
-\s_pulseLed_i_7__35\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__35_n_0\
- );
-\s_pulseLed_i_8__35\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__35_n_0\
- );
-\s_pulseLed_i_9__35\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__35_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_48\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_48\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_48\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_48\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__34_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__34_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__34_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__34_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__34_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__34_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__34_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__34_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__34\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__34_n_0\
- );
-\s_pulseLed_i_1__34\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__34_n_0\,
- I1 => \s_pulseLed_i_3__34_n_0\,
- I2 => \s_pulseLed_i_4__34_n_0\,
- I3 => \s_pulseLed_i_5__34_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__34\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__34_n_0\,
- O => \s_pulseLed_i_2__34_n_0\
- );
-\s_pulseLed_i_3__34\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__34_n_0\,
- O => \s_pulseLed_i_3__34_n_0\
- );
-\s_pulseLed_i_4__34\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__34_n_0\,
- O => \s_pulseLed_i_4__34_n_0\
- );
-\s_pulseLed_i_5__34\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__34_n_0\,
- O => \s_pulseLed_i_5__34_n_0\
- );
-\s_pulseLed_i_7__34\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__34_n_0\
- );
-\s_pulseLed_i_8__34\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__34_n_0\
- );
-\s_pulseLed_i_9__34\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__34_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_51\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_51\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_51\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_51\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__33_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__33_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__33_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__33_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__33_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__33_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__33_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__33_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__33\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__33_n_0\
- );
-\s_pulseLed_i_1__33\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__33_n_0\,
- I1 => \s_pulseLed_i_3__33_n_0\,
- I2 => \s_pulseLed_i_4__33_n_0\,
- I3 => \s_pulseLed_i_5__33_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__33_n_0\,
- O => \s_pulseLed_i_2__33_n_0\
- );
-\s_pulseLed_i_3__33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__33_n_0\,
- O => \s_pulseLed_i_3__33_n_0\
- );
-\s_pulseLed_i_4__33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__33_n_0\,
- O => \s_pulseLed_i_4__33_n_0\
- );
-\s_pulseLed_i_5__33\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__33_n_0\,
- O => \s_pulseLed_i_5__33_n_0\
- );
-\s_pulseLed_i_7__33\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__33_n_0\
- );
-\s_pulseLed_i_8__33\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__33_n_0\
- );
-\s_pulseLed_i_9__33\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__33_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_54\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_54\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_54\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_54\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__32_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__32_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__32_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__32_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__32_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__32_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__32_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__32_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__32\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__32_n_0\
- );
-\s_pulseLed_i_1__32\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__32_n_0\,
- I1 => \s_pulseLed_i_3__32_n_0\,
- I2 => \s_pulseLed_i_4__32_n_0\,
- I3 => \s_pulseLed_i_5__32_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__32\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__32_n_0\,
- O => \s_pulseLed_i_2__32_n_0\
- );
-\s_pulseLed_i_3__32\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__32_n_0\,
- O => \s_pulseLed_i_3__32_n_0\
- );
-\s_pulseLed_i_4__32\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__32_n_0\,
- O => \s_pulseLed_i_4__32_n_0\
- );
-\s_pulseLed_i_5__32\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__32_n_0\,
- O => \s_pulseLed_i_5__32_n_0\
- );
-\s_pulseLed_i_7__32\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__32_n_0\
- );
-\s_pulseLed_i_8__32\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__32_n_0\
- );
-\s_pulseLed_i_9__32\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__32_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_57\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_57\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_57\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_57\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__31_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__31_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__31_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__31_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__31_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__31_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__31_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__31_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__31\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__31_n_0\
- );
-\s_pulseLed_i_1__31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__31_n_0\,
- I1 => \s_pulseLed_i_3__31_n_0\,
- I2 => \s_pulseLed_i_4__31_n_0\,
- I3 => \s_pulseLed_i_5__31_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__31\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__31_n_0\,
- O => \s_pulseLed_i_2__31_n_0\
- );
-\s_pulseLed_i_3__31\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__31_n_0\,
- O => \s_pulseLed_i_3__31_n_0\
- );
-\s_pulseLed_i_4__31\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__31_n_0\,
- O => \s_pulseLed_i_4__31_n_0\
- );
-\s_pulseLed_i_5__31\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__31_n_0\,
- O => \s_pulseLed_i_5__31_n_0\
- );
-\s_pulseLed_i_7__31\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__31_n_0\
- );
-\s_pulseLed_i_8__31\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__31_n_0\
- );
-\s_pulseLed_i_9__31\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__31_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_60\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_60\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_60\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_60\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__30_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__30_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__30_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__30_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__30_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__30_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__30_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__30_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__30\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__30_n_0\
- );
-\s_pulseLed_i_1__30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__30_n_0\,
- I1 => \s_pulseLed_i_3__30_n_0\,
- I2 => \s_pulseLed_i_4__30_n_0\,
- I3 => \s_pulseLed_i_5__30_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__30\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__30_n_0\,
- O => \s_pulseLed_i_2__30_n_0\
- );
-\s_pulseLed_i_3__30\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__30_n_0\,
- O => \s_pulseLed_i_3__30_n_0\
- );
-\s_pulseLed_i_4__30\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__30_n_0\,
- O => \s_pulseLed_i_4__30_n_0\
- );
-\s_pulseLed_i_5__30\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__30_n_0\,
- O => \s_pulseLed_i_5__30_n_0\
- );
-\s_pulseLed_i_7__30\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__30_n_0\
- );
-\s_pulseLed_i_8__30\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__30_n_0\
- );
-\s_pulseLed_i_9__30\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__30_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_63\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_63\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_63\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_63\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__29_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__29_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__29_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__29_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__29_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__29_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__29_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__29_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__29\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__29_n_0\
- );
-\s_pulseLed_i_1__29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__29_n_0\,
- I1 => \s_pulseLed_i_3__29_n_0\,
- I2 => \s_pulseLed_i_4__29_n_0\,
- I3 => \s_pulseLed_i_5__29_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__29\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__29_n_0\,
- O => \s_pulseLed_i_2__29_n_0\
- );
-\s_pulseLed_i_3__29\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__29_n_0\,
- O => \s_pulseLed_i_3__29_n_0\
- );
-\s_pulseLed_i_4__29\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__29_n_0\,
- O => \s_pulseLed_i_4__29_n_0\
- );
-\s_pulseLed_i_5__29\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__29_n_0\,
- O => \s_pulseLed_i_5__29_n_0\
- );
-\s_pulseLed_i_7__29\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__29_n_0\
- );
-\s_pulseLed_i_8__29\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__29_n_0\
- );
-\s_pulseLed_i_9__29\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__29_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_66\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_66\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_66\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_66\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__28_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__28_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__28_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__28_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__28_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__28_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__28_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__28_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__28\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__28_n_0\
- );
-\s_pulseLed_i_1__28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__28_n_0\,
- I1 => \s_pulseLed_i_3__28_n_0\,
- I2 => \s_pulseLed_i_4__28_n_0\,
- I3 => \s_pulseLed_i_5__28_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__28\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__28_n_0\,
- O => \s_pulseLed_i_2__28_n_0\
- );
-\s_pulseLed_i_3__28\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__28_n_0\,
- O => \s_pulseLed_i_3__28_n_0\
- );
-\s_pulseLed_i_4__28\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__28_n_0\,
- O => \s_pulseLed_i_4__28_n_0\
- );
-\s_pulseLed_i_5__28\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__28_n_0\,
- O => \s_pulseLed_i_5__28_n_0\
- );
-\s_pulseLed_i_7__28\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__28_n_0\
- );
-\s_pulseLed_i_8__28\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__28_n_0\
- );
-\s_pulseLed_i_9__28\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__28_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_69\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_69\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_69\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_69\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__46_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__46_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__46_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__46_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__46_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__46_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__46_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__46_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__46\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__46_n_0\
- );
-\s_pulseLed_i_1__46\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__46_n_0\,
- I1 => \s_pulseLed_i_3__46_n_0\,
- I2 => \s_pulseLed_i_4__46_n_0\,
- I3 => \s_pulseLed_i_5__46_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__46\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__46_n_0\,
- O => \s_pulseLed_i_2__46_n_0\
- );
-\s_pulseLed_i_3__46\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__46_n_0\,
- O => \s_pulseLed_i_3__46_n_0\
- );
-\s_pulseLed_i_4__46\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__46_n_0\,
- O => \s_pulseLed_i_4__46_n_0\
- );
-\s_pulseLed_i_5__46\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__46_n_0\,
- O => \s_pulseLed_i_5__46_n_0\
- );
-\s_pulseLed_i_7__46\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__46_n_0\
- );
-\s_pulseLed_i_8__46\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__46_n_0\
- );
-\s_pulseLed_i_9__46\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__46_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_72\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_72\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_72\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_72\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__45_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__45_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__45_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__45_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__45_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__45_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__45_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__45_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__45\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__45_n_0\
- );
-\s_pulseLed_i_1__45\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__45_n_0\,
- I1 => \s_pulseLed_i_3__45_n_0\,
- I2 => \s_pulseLed_i_4__45_n_0\,
- I3 => \s_pulseLed_i_5__45_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__45\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__45_n_0\,
- O => \s_pulseLed_i_2__45_n_0\
- );
-\s_pulseLed_i_3__45\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__45_n_0\,
- O => \s_pulseLed_i_3__45_n_0\
- );
-\s_pulseLed_i_4__45\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__45_n_0\,
- O => \s_pulseLed_i_4__45_n_0\
- );
-\s_pulseLed_i_5__45\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__45_n_0\,
- O => \s_pulseLed_i_5__45_n_0\
- );
-\s_pulseLed_i_7__45\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__45_n_0\
- );
-\s_pulseLed_i_8__45\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__45_n_0\
- );
-\s_pulseLed_i_9__45\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__45_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_75\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_75\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_75\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_75\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__44_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__44_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__44_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__44_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__44_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__44_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__44_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__44_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__44\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__44_n_0\
- );
-\s_pulseLed_i_1__44\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__44_n_0\,
- I1 => \s_pulseLed_i_3__44_n_0\,
- I2 => \s_pulseLed_i_4__44_n_0\,
- I3 => \s_pulseLed_i_5__44_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__44\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__44_n_0\,
- O => \s_pulseLed_i_2__44_n_0\
- );
-\s_pulseLed_i_3__44\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__44_n_0\,
- O => \s_pulseLed_i_3__44_n_0\
- );
-\s_pulseLed_i_4__44\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__44_n_0\,
- O => \s_pulseLed_i_4__44_n_0\
- );
-\s_pulseLed_i_5__44\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__44_n_0\,
- O => \s_pulseLed_i_5__44_n_0\
- );
-\s_pulseLed_i_7__44\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__44_n_0\
- );
-\s_pulseLed_i_8__44\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__44_n_0\
- );
-\s_pulseLed_i_9__44\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__44_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_78\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_78\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_78\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_78\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__43_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__43_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__43_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__43_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__43_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__43_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__43_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__43_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__43\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__43_n_0\
- );
-\s_pulseLed_i_1__43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__43_n_0\,
- I1 => \s_pulseLed_i_3__43_n_0\,
- I2 => \s_pulseLed_i_4__43_n_0\,
- I3 => \s_pulseLed_i_5__43_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__43\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__43_n_0\,
- O => \s_pulseLed_i_2__43_n_0\
- );
-\s_pulseLed_i_3__43\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__43_n_0\,
- O => \s_pulseLed_i_3__43_n_0\
- );
-\s_pulseLed_i_4__43\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__43_n_0\,
- O => \s_pulseLed_i_4__43_n_0\
- );
-\s_pulseLed_i_5__43\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__43_n_0\,
- O => \s_pulseLed_i_5__43_n_0\
- );
-\s_pulseLed_i_7__43\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__43_n_0\
- );
-\s_pulseLed_i_8__43\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__43_n_0\
- );
-\s_pulseLed_i_9__43\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__43_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_81\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_81\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_81\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_81\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__42_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__42_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__42_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__42_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__42_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__42_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__42_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__42_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__42\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__42_n_0\
- );
-\s_pulseLed_i_1__42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__42_n_0\,
- I1 => \s_pulseLed_i_3__42_n_0\,
- I2 => \s_pulseLed_i_4__42_n_0\,
- I3 => \s_pulseLed_i_5__42_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__42\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__42_n_0\,
- O => \s_pulseLed_i_2__42_n_0\
- );
-\s_pulseLed_i_3__42\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__42_n_0\,
- O => \s_pulseLed_i_3__42_n_0\
- );
-\s_pulseLed_i_4__42\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__42_n_0\,
- O => \s_pulseLed_i_4__42_n_0\
- );
-\s_pulseLed_i_5__42\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__42_n_0\,
- O => \s_pulseLed_i_5__42_n_0\
- );
-\s_pulseLed_i_7__42\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__42_n_0\
- );
-\s_pulseLed_i_8__42\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__42_n_0\
- );
-\s_pulseLed_i_9__42\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__42_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_84\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_84\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_84\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_84\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__41_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__41_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__41_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__41_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__41_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__41_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__41_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__41_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__41\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__41_n_0\
- );
-\s_pulseLed_i_1__41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__41_n_0\,
- I1 => \s_pulseLed_i_3__41_n_0\,
- I2 => \s_pulseLed_i_4__41_n_0\,
- I3 => \s_pulseLed_i_5__41_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__41\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__41_n_0\,
- O => \s_pulseLed_i_2__41_n_0\
- );
-\s_pulseLed_i_3__41\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__41_n_0\,
- O => \s_pulseLed_i_3__41_n_0\
- );
-\s_pulseLed_i_4__41\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__41_n_0\,
- O => \s_pulseLed_i_4__41_n_0\
- );
-\s_pulseLed_i_5__41\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__41_n_0\,
- O => \s_pulseLed_i_5__41_n_0\
- );
-\s_pulseLed_i_7__41\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__41_n_0\
- );
-\s_pulseLed_i_8__41\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__41_n_0\
- );
-\s_pulseLed_i_9__41\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__41_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_87\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_87\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_87\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_87\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__40_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__40_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__40_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__40_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__40_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__40_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__40_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__40_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__40\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__40_n_0\
- );
-\s_pulseLed_i_1__40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__40_n_0\,
- I1 => \s_pulseLed_i_3__40_n_0\,
- I2 => \s_pulseLed_i_4__40_n_0\,
- I3 => \s_pulseLed_i_5__40_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__40\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__40_n_0\,
- O => \s_pulseLed_i_2__40_n_0\
- );
-\s_pulseLed_i_3__40\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__40_n_0\,
- O => \s_pulseLed_i_3__40_n_0\
- );
-\s_pulseLed_i_4__40\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__40_n_0\,
- O => \s_pulseLed_i_4__40_n_0\
- );
-\s_pulseLed_i_5__40\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__40_n_0\,
- O => \s_pulseLed_i_5__40_n_0\
- );
-\s_pulseLed_i_7__40\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__40_n_0\
- );
-\s_pulseLed_i_8__40\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__40_n_0\
- );
-\s_pulseLed_i_9__40\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__40_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_90\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_90\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_90\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_90\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__39_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__39_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__39_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__39_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__39_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__39_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__39_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__39_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__39\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__39_n_0\
- );
-\s_pulseLed_i_1__39\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__39_n_0\,
- I1 => \s_pulseLed_i_3__39_n_0\,
- I2 => \s_pulseLed_i_4__39_n_0\,
- I3 => \s_pulseLed_i_5__39_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__39_n_0\,
- O => \s_pulseLed_i_2__39_n_0\
- );
-\s_pulseLed_i_3__39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__39_n_0\,
- O => \s_pulseLed_i_3__39_n_0\
- );
-\s_pulseLed_i_4__39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__39_n_0\,
- O => \s_pulseLed_i_4__39_n_0\
- );
-\s_pulseLed_i_5__39\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__39_n_0\,
- O => \s_pulseLed_i_5__39_n_0\
- );
-\s_pulseLed_i_7__39\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__39_n_0\
- );
-\s_pulseLed_i_8__39\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__39_n_0\
- );
-\s_pulseLed_i_9__39\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__39_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_93\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_93\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_93\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_93\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__38_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__38_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__38_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__38_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__38_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__38_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__38_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__38_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__38\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__38_n_0\
- );
-\s_pulseLed_i_1__38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__38_n_0\,
- I1 => \s_pulseLed_i_3__38_n_0\,
- I2 => \s_pulseLed_i_4__38_n_0\,
- I3 => \s_pulseLed_i_5__38_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__38\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__38_n_0\,
- O => \s_pulseLed_i_2__38_n_0\
- );
-\s_pulseLed_i_3__38\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__38_n_0\,
- O => \s_pulseLed_i_3__38_n_0\
- );
-\s_pulseLed_i_4__38\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__38_n_0\,
- O => \s_pulseLed_i_4__38_n_0\
- );
-\s_pulseLed_i_5__38\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__38_n_0\,
- O => \s_pulseLed_i_5__38_n_0\
- );
-\s_pulseLed_i_7__38\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__38_n_0\
- );
-\s_pulseLed_i_8__38\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__38_n_0\
- );
-\s_pulseLed_i_9__38\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__38_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_96\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_96\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_96\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_96\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__37_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__37_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__37_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__37_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__37_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__37_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__37_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__37_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__37\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__37_n_0\
- );
-\s_pulseLed_i_1__37\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__37_n_0\,
- I1 => \s_pulseLed_i_3__37_n_0\,
- I2 => \s_pulseLed_i_4__37_n_0\,
- I3 => \s_pulseLed_i_5__37_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__37\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__37_n_0\,
- O => \s_pulseLed_i_2__37_n_0\
- );
-\s_pulseLed_i_3__37\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__37_n_0\,
- O => \s_pulseLed_i_3__37_n_0\
- );
-\s_pulseLed_i_4__37\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__37_n_0\,
- O => \s_pulseLed_i_4__37_n_0\
- );
-\s_pulseLed_i_5__37\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__37_n_0\,
- O => \s_pulseLed_i_5__37_n_0\
- );
-\s_pulseLed_i_7__37\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__37_n_0\
- );
-\s_pulseLed_i_8__37\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__37_n_0\
- );
-\s_pulseLed_i_9__37\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__37_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_99\ is
- port (
- s_pulseLed_reg : out STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s_buff2_reg : in STD_LOGIC;
- s_buff3_reg : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_99\ : entity is "counterUpDown";
-end \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_99\;
-
-architecture STRUCTURE of \system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_99\ is
- signal s_count_reg_n_100 : STD_LOGIC;
- signal s_count_reg_n_101 : STD_LOGIC;
- signal s_count_reg_n_102 : STD_LOGIC;
- signal s_count_reg_n_103 : STD_LOGIC;
- signal s_count_reg_n_104 : STD_LOGIC;
- signal s_count_reg_n_105 : STD_LOGIC;
- signal s_count_reg_n_74 : STD_LOGIC;
- signal s_count_reg_n_75 : STD_LOGIC;
- signal s_count_reg_n_76 : STD_LOGIC;
- signal s_count_reg_n_77 : STD_LOGIC;
- signal s_count_reg_n_78 : STD_LOGIC;
- signal s_count_reg_n_79 : STD_LOGIC;
- signal s_count_reg_n_80 : STD_LOGIC;
- signal s_count_reg_n_81 : STD_LOGIC;
- signal s_count_reg_n_82 : STD_LOGIC;
- signal s_count_reg_n_83 : STD_LOGIC;
- signal s_count_reg_n_84 : STD_LOGIC;
- signal s_count_reg_n_85 : STD_LOGIC;
- signal s_count_reg_n_86 : STD_LOGIC;
- signal s_count_reg_n_87 : STD_LOGIC;
- signal s_count_reg_n_88 : STD_LOGIC;
- signal s_count_reg_n_89 : STD_LOGIC;
- signal s_count_reg_n_90 : STD_LOGIC;
- signal s_count_reg_n_91 : STD_LOGIC;
- signal s_count_reg_n_92 : STD_LOGIC;
- signal s_count_reg_n_93 : STD_LOGIC;
- signal s_count_reg_n_94 : STD_LOGIC;
- signal s_count_reg_n_95 : STD_LOGIC;
- signal s_count_reg_n_96 : STD_LOGIC;
- signal s_count_reg_n_97 : STD_LOGIC;
- signal s_count_reg_n_98 : STD_LOGIC;
- signal s_count_reg_n_99 : STD_LOGIC;
- signal \s_pulseLed_i_10__27_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_2__27_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_3__27_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_4__27_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_5__27_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_7__27_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_8__27_n_0\ : STD_LOGIC;
- signal \s_pulseLed_i_9__27_n_0\ : STD_LOGIC;
- signal NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
- signal NLW_s_count_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
- signal NLW_s_count_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
- signal NLW_s_count_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_s_count_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
- signal NLW_s_count_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
- attribute METHODOLOGY_DRC_VIOS : string;
- attribute METHODOLOGY_DRC_VIOS of s_count_reg : label is "{SYNTH-12 {cell *THIS*}}";
-begin
-s_count_reg: unisim.vcomponents.DSP48E1
- generic map(
- ACASCREG => 1,
- ADREG => 1,
- ALUMODEREG => 0,
- AREG => 1,
- AUTORESET_PATDET => "NO_RESET",
- A_INPUT => "DIRECT",
- BCASCREG => 1,
- BREG => 1,
- B_INPUT => "DIRECT",
- CARRYINREG => 0,
- CARRYINSELREG => 0,
- CREG => 0,
- DREG => 1,
- INMODEREG => 0,
- MASK => X"3FFFFFFFFFFF",
- MREG => 0,
- OPMODEREG => 0,
- PATTERN => X"000000000000",
- PREG => 1,
- SEL_MASK => "MASK",
- SEL_PATTERN => "PATTERN",
- USE_DPORT => false,
- USE_MULT => "NONE",
- USE_PATTERN_DETECT => "NO_PATDET",
- USE_SIMD => "ONE48"
- )
- port map (
- A(29 downto 0) => B"111111111111111111111111111111",
- ACIN(29 downto 0) => B"000000000000000000000000000000",
- ACOUT(29 downto 0) => NLW_s_count_reg_ACOUT_UNCONNECTED(29 downto 0),
- ALUMODE(3 downto 0) => B"0000",
- B(17 downto 0) => B"111111111111111111",
- BCIN(17 downto 0) => B"000000000000000000",
- BCOUT(17 downto 0) => NLW_s_count_reg_BCOUT_UNCONNECTED(17 downto 0),
- C(47 downto 0) => B"000000000000000000000000000000000000000000000001",
- CARRYCASCIN => '0',
- CARRYCASCOUT => NLW_s_count_reg_CARRYCASCOUT_UNCONNECTED,
- CARRYIN => '0',
- CARRYINSEL(2 downto 0) => B"000",
- CARRYOUT(3 downto 0) => NLW_s_count_reg_CARRYOUT_UNCONNECTED(3 downto 0),
- CEA1 => '0',
- CEA2 => '0',
- CEAD => '0',
- CEALUMODE => '0',
- CEB1 => '0',
- CEB2 => '0',
- CEC => '0',
- CECARRYIN => '0',
- CECTRL => '0',
- CED => '0',
- CEINMODE => '0',
- CEM => '0',
- CEP => s_pulseLed_reg_0,
- CLK => s00_axi_aclk,
- D(24 downto 0) => B"0000000000000000000000000",
- INMODE(4 downto 0) => B"00000",
- MULTSIGNIN => '0',
- MULTSIGNOUT => NLW_s_count_reg_MULTSIGNOUT_UNCONNECTED,
- OPMODE(6 downto 0) => B"0110010",
- OVERFLOW => NLW_s_count_reg_OVERFLOW_UNCONNECTED,
- P(47 downto 32) => NLW_s_count_reg_P_UNCONNECTED(47 downto 32),
- P(31) => s_count_reg_n_74,
- P(30) => s_count_reg_n_75,
- P(29) => s_count_reg_n_76,
- P(28) => s_count_reg_n_77,
- P(27) => s_count_reg_n_78,
- P(26) => s_count_reg_n_79,
- P(25) => s_count_reg_n_80,
- P(24) => s_count_reg_n_81,
- P(23) => s_count_reg_n_82,
- P(22) => s_count_reg_n_83,
- P(21) => s_count_reg_n_84,
- P(20) => s_count_reg_n_85,
- P(19) => s_count_reg_n_86,
- P(18) => s_count_reg_n_87,
- P(17) => s_count_reg_n_88,
- P(16) => s_count_reg_n_89,
- P(15) => s_count_reg_n_90,
- P(14) => s_count_reg_n_91,
- P(13) => s_count_reg_n_92,
- P(12) => s_count_reg_n_93,
- P(11) => s_count_reg_n_94,
- P(10) => s_count_reg_n_95,
- P(9) => s_count_reg_n_96,
- P(8) => s_count_reg_n_97,
- P(7) => s_count_reg_n_98,
- P(6) => s_count_reg_n_99,
- P(5) => s_count_reg_n_100,
- P(4) => s_count_reg_n_101,
- P(3) => s_count_reg_n_102,
- P(2) => s_count_reg_n_103,
- P(1) => s_count_reg_n_104,
- P(0) => s_count_reg_n_105,
- PATTERNBDETECT => NLW_s_count_reg_PATTERNBDETECT_UNCONNECTED,
- PATTERNDETECT => NLW_s_count_reg_PATTERNDETECT_UNCONNECTED,
- PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
- PCOUT(47 downto 0) => NLW_s_count_reg_PCOUT_UNCONNECTED(47 downto 0),
- RSTA => '0',
- RSTALLCARRYIN => '0',
- RSTALUMODE => '0',
- RSTB => '0',
- RSTC => '0',
- RSTCTRL => '0',
- RSTD => '0',
- RSTINMODE => '0',
- RSTM => '0',
- RSTP => s_buff2_reg,
- UNDERFLOW => NLW_s_count_reg_UNDERFLOW_UNCONNECTED
- );
-\s_pulseLed_i_10__27\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_93,
- I1 => s_count_reg_n_92,
- I2 => s_count_reg_n_90,
- I3 => s_count_reg_n_91,
- O => \s_pulseLed_i_10__27_n_0\
- );
-\s_pulseLed_i_1__27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFE0000FFFE"
- )
- port map (
- I0 => \s_pulseLed_i_2__27_n_0\,
- I1 => \s_pulseLed_i_3__27_n_0\,
- I2 => \s_pulseLed_i_4__27_n_0\,
- I3 => \s_pulseLed_i_5__27_n_0\,
- I4 => s_buff3_reg,
- I5 => s_pulseLed_reg_0,
- O => s_pulseLed_reg
- );
-\s_pulseLed_i_2__27\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => s_count_reg_n_87,
- I1 => s_count_reg_n_86,
- I2 => s_count_reg_n_89,
- I3 => s_count_reg_n_88,
- I4 => \s_pulseLed_i_7__27_n_0\,
- O => \s_pulseLed_i_2__27_n_0\
- );
-\s_pulseLed_i_3__27\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_79,
- I1 => s_count_reg_n_78,
- I2 => s_count_reg_n_81,
- I3 => s_count_reg_n_80,
- I4 => \s_pulseLed_i_8__27_n_0\,
- O => \s_pulseLed_i_3__27_n_0\
- );
-\s_pulseLed_i_4__27\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => s_count_reg_n_103,
- I1 => s_count_reg_n_102,
- I2 => s_count_reg_n_105,
- I3 => s_count_reg_n_104,
- I4 => \s_pulseLed_i_9__27_n_0\,
- O => \s_pulseLed_i_4__27_n_0\
- );
-\s_pulseLed_i_5__27\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFBFF"
- )
- port map (
- I0 => s_count_reg_n_94,
- I1 => s_count_reg_n_95,
- I2 => s_count_reg_n_97,
- I3 => s_count_reg_n_96,
- I4 => \s_pulseLed_i_10__27_n_0\,
- O => \s_pulseLed_i_5__27_n_0\
- );
-\s_pulseLed_i_7__27\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFDF"
- )
- port map (
- I0 => s_count_reg_n_85,
- I1 => s_count_reg_n_84,
- I2 => s_count_reg_n_82,
- I3 => s_count_reg_n_83,
- O => \s_pulseLed_i_7__27_n_0\
- );
-\s_pulseLed_i_8__27\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => s_count_reg_n_76,
- I1 => s_count_reg_n_77,
- I2 => s_count_reg_n_74,
- I3 => s_count_reg_n_75,
- O => \s_pulseLed_i_8__27_n_0\
- );
-\s_pulseLed_i_9__27\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFEF"
- )
- port map (
- I0 => s_count_reg_n_100,
- I1 => s_count_reg_n_101,
- I2 => s_count_reg_n_98,
- I3 => s_count_reg_n_99,
- O => \s_pulseLed_i_9__27_n_0\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => Q(0),
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__94\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__54\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_100 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- \v_dout_reg[7]\ : out STD_LOGIC;
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_0 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- \data_rw_o_reg[79][7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \v_cmp_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_100 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_100;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_100 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__19_n_0\ : STD_LOGIC;
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \s_pulseLed_i_6__27\ : label is "soft_lutpair47";
- attribute SOFT_HLUTNM of \v_dout[7]_i_1__0\ : label is "soft_lutpair47";
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\intr_o_i_9__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \v_cmp_reg[2]\(0),
- I1 => \^s_buff3_reg_0\,
- I2 => s_buff2_reg_1(1),
- I3 => \v_cmp_reg[2]\(2),
- I4 => s_buff2_reg_1(0),
- I5 => \v_cmp_reg[2]\(1),
- O => intr_o_reg(0)
- );
-\s_buff1_i_1__19\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_0,
- O => \s_buff1_i_1__19_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__19_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__19\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__67\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__27\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-\v_dout[7]_i_1__0\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => \data_rw_o_reg[79][7]\(0),
- O => \v_dout_reg[7]\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_132 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_132 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_132;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_132 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => Q(0),
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__66\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__26\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_134 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_134 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_134;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_134 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => Q(0),
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__65\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__25\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_136 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_136 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_136;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_136 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => Q(0),
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__64\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__24\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_138 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_138 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_138;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_138 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => Q(0),
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__63\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__23\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_140 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_140 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_140;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_140 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(0),
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__62\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__22\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_142 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_142 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_142;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_142 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(0),
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__61\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__21\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_144 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_144 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_144;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_144 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(0),
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__60\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__20\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_146 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_146 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_146;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_146 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(0),
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__59\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__19\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_149 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- CO : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_9 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- \v_cmp_reg[6]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \v_cmp_reg[18]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \v_cmp_reg[11]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_149 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_149;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_149 is
- signal intr_o_i_6_n_0 : STD_LOGIC;
- signal intr_o_reg_i_1_n_2 : STD_LOGIC;
- signal intr_o_reg_i_1_n_3 : STD_LOGIC;
- signal intr_o_reg_i_2_n_0 : STD_LOGIC;
- signal intr_o_reg_i_2_n_1 : STD_LOGIC;
- signal intr_o_reg_i_2_n_2 : STD_LOGIC;
- signal intr_o_reg_i_2_n_3 : STD_LOGIC;
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__8_n_0\ : STD_LOGIC;
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
- signal NLW_intr_o_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
- signal NLW_intr_o_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_intr_o_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-intr_o_i_6: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \v_cmp_reg[11]\(0),
- I1 => \^s_buff3_reg_0\,
- I2 => s_buff2_reg_1(1),
- I3 => \v_cmp_reg[11]\(2),
- I4 => s_buff2_reg_1(0),
- I5 => \v_cmp_reg[11]\(1),
- O => intr_o_i_6_n_0
- );
-intr_o_reg_i_1: unisim.vcomponents.CARRY4
- port map (
- CI => intr_o_reg_i_2_n_0,
- CO(3) => NLW_intr_o_reg_i_1_CO_UNCONNECTED(3),
- CO(2) => CO(0),
- CO(1) => intr_o_reg_i_1_n_2,
- CO(0) => intr_o_reg_i_1_n_3,
- CYINIT => '0',
- DI(3 downto 0) => B"0111",
- O(3 downto 0) => NLW_intr_o_reg_i_1_O_UNCONNECTED(3 downto 0),
- S(3) => '0',
- S(2 downto 0) => \v_cmp_reg[18]\(2 downto 0)
- );
-intr_o_reg_i_2: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => intr_o_reg_i_2_n_0,
- CO(2) => intr_o_reg_i_2_n_1,
- CO(1) => intr_o_reg_i_2_n_2,
- CO(0) => intr_o_reg_i_2_n_3,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => NLW_intr_o_reg_i_2_O_UNCONNECTED(3 downto 0),
- S(3) => intr_o_i_6_n_0,
- S(2 downto 0) => \v_cmp_reg[6]\(2 downto 0)
- );
-\s_buff1_i_1__8\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_9,
- O => \s_buff1_i_1__8_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__8_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__48\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_count_reg_i_1__8\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__8\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_152 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_8 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_152 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_152;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_152 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__7_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__7\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_8,
- O => \s_buff1_i_1__7_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__7_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__47\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_count_reg_i_1__7\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__7\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_155 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_7 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_155 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_155;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_155 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__6_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__6\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_7,
- O => \s_buff1_i_1__6_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__6_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__46\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0(0),
- O => s_count_reg
- );
-\s_count_reg_i_1__6\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__6\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_158 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_6 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- \v_cmp_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_158 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_158;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_158 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__5_n_0\ : STD_LOGIC;
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-intr_o_i_7: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \v_cmp_reg[8]\(0),
- I1 => \^s_buff3_reg_0\,
- I2 => s_buff2_reg_1(1),
- I3 => \v_cmp_reg[8]\(2),
- I4 => s_buff2_reg_1(0),
- I5 => \v_cmp_reg[8]\(1),
- O => intr_o_reg(0)
- );
-\s_buff1_i_1__5\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_6,
- O => \s_buff1_i_1__5_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__5_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__45\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_count_reg_i_1__5\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__5\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_161 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_5 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_161 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_161;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_161 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__4_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__4\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_5,
- O => \s_buff1_i_1__4_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__4_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__4\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__44\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__4\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_164 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_4 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_164 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_164;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_164 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__3_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__3\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_4,
- O => \s_buff1_i_1__3_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__3_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__3\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__43\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_167 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_3 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- \v_cmp_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_167 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_167;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_167 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__2_n_0\ : STD_LOGIC;
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-intr_o_i_8: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \v_cmp_reg[5]\(0),
- I1 => \^s_buff3_reg_0\,
- I2 => s_buff2_reg_1(1),
- I3 => \v_cmp_reg[5]\(2),
- I4 => s_buff2_reg_1(0),
- I5 => \v_cmp_reg[5]\(1),
- O => intr_o_reg(0)
- );
-\s_buff1_i_1__2\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_3,
- O => \s_buff1_i_1__2_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__2_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__2\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__42\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__2\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_170 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_2 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_170 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_170;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_170 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__1_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__1\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_2,
- O => \s_buff1_i_1__1_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__1_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__1\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__41\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_173 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_1 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_173 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_173;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_173 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__0_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__0\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_1,
- O => \s_buff1_i_1__0_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__0_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__0\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__40\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__0\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_176 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_19 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_176 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_176;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_176 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal pulse_i : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__18\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_19,
- O => pulse_i
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => pulse_i,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__18\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__58\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__18\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_179 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_18 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- \v_cmp_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_buff2_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_179 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_179;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_179 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__17_n_0\ : STD_LOGIC;
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-intr_o_i_3: unisim.vcomponents.LUT4
- generic map(
- INIT => X"9009"
- )
- port map (
- I0 => \v_cmp_reg[19]\(0),
- I1 => \^s_buff3_reg_0\,
- I2 => \v_cmp_reg[19]\(1),
- I3 => s_buff2_reg_1(0),
- O => intr_o_reg(0)
- );
-\s_buff1_i_1__17\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_18,
- O => \s_buff1_i_1__17_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__17_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__17\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__57\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__17\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_182 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_17 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_182 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_182;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_182 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__16_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__16\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_17,
- O => \s_buff1_i_1__16_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__16_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__16\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__56\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__16\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_185 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_16 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_185 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_185;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_185 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__15_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__15\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_16,
- O => \s_buff1_i_1__15_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__15_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__15\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__55\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__15\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_188 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_15 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- \v_cmp_reg[17]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_188 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_188;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_188 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__14_n_0\ : STD_LOGIC;
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-intr_o_i_4: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \v_cmp_reg[17]\(0),
- I1 => \^s_buff3_reg_0\,
- I2 => s_buff2_reg_1(1),
- I3 => \v_cmp_reg[17]\(2),
- I4 => s_buff2_reg_1(0),
- I5 => \v_cmp_reg[17]\(1),
- O => intr_o_reg(0)
- );
-\s_buff1_i_1__14\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_15,
- O => \s_buff1_i_1__14_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__14_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__14\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__54\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__14\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_191 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_14 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_191 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_191;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_191 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__13_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__13\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_14,
- O => \s_buff1_i_1__13_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__13_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__13\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__53\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__13\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_194 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_13 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_194 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_194;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_194 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__12_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__12\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_13,
- O => \s_buff1_i_1__12_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__12_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__12\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__52\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__12\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_197 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_12 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- \v_cmp_reg[14]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_197 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_197;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_197 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__11_n_0\ : STD_LOGIC;
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-intr_o_i_5: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \v_cmp_reg[14]\(0),
- I1 => \^s_buff3_reg_0\,
- I2 => s_buff2_reg_1(1),
- I3 => \v_cmp_reg[14]\(2),
- I4 => s_buff2_reg_1(0),
- I5 => \v_cmp_reg[14]\(1),
- O => intr_o_reg(0)
- );
-\s_buff1_i_1__11\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_12,
- O => \s_buff1_i_1__11_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__11_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__11\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__51\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__11\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_200 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_11 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_200 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_200;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_200 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__10_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__10\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_11,
- O => \s_buff1_i_1__10_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__10_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__10\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__50\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__10\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_203 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_10 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_203 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_203;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_203 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__9_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__9\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_10,
- O => \s_buff1_i_1__9_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__9_n_0\,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-\s_count_reg_i_1__49\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_count_reg_i_1__9\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__9\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_206 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- \v_dout_reg[7]\ : out STD_LOGIC;
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_0 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- \data_rw_o_reg[11][7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \v_cmp_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_206 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_206;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_206 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_buff1_i_1_n_0 : STD_LOGIC;
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of s_pulseLed_i_6 : label is "soft_lutpair36";
- attribute SOFT_HLUTNM of \v_dout[7]_i_1\ : label is "soft_lutpair36";
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-intr_o_i_9: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \v_cmp_reg[2]\(0),
- I1 => \^s_buff3_reg_0\,
- I2 => s_buff2_reg_1(1),
- I3 => \v_cmp_reg[2]\(2),
- I4 => s_buff2_reg_1(0),
- I5 => \v_cmp_reg[2]\(1),
- O => intr_o_reg(0)
- );
-s_buff1_i_1: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_0,
- O => s_buff1_i_1_n_0
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_buff1_i_1_n_0,
- Q => p_1_in(0),
- R => SR(0)
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => SR(0)
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => SR(0)
- );
-s_count_reg_i_1: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__39\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-s_pulseLed_i_6: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-\v_dout[7]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"8"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => \data_rw_o_reg[11][7]\(0),
- O => \v_dout_reg[7]\
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_29 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_29 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_29;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_29 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => Q(0),
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__93\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__53\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_31 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_31 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_31;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_31 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => Q(0),
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__92\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__52\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_33 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_33 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_33;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_33 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => Q(0),
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__91\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__51\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_35 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_35 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_35;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_35 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(0),
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__90\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__50\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_37 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_37 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_37;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_37 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(0),
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__89\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__49\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_39 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_39 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_39;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_39 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(0),
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__88\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__48\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_41 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_41 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_41;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_41 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(0),
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__87\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__47\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_43 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- CO : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_9 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- \v_cmp_reg[6]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \v_cmp_reg[18]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \v_cmp_reg[11]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_43 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_43;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_43 is
- signal \intr_o_i_6__0_n_0\ : STD_LOGIC;
- signal \intr_o_reg_i_1__0_n_2\ : STD_LOGIC;
- signal \intr_o_reg_i_1__0_n_3\ : STD_LOGIC;
- signal \intr_o_reg_i_2__0_n_0\ : STD_LOGIC;
- signal \intr_o_reg_i_2__0_n_1\ : STD_LOGIC;
- signal \intr_o_reg_i_2__0_n_2\ : STD_LOGIC;
- signal \intr_o_reg_i_2__0_n_3\ : STD_LOGIC;
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__28_n_0\ : STD_LOGIC;
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
- signal \NLW_intr_o_reg_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
- signal \NLW_intr_o_reg_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_intr_o_reg_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\intr_o_i_6__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \v_cmp_reg[11]\(0),
- I1 => \^s_buff3_reg_0\,
- I2 => s_buff2_reg_1(1),
- I3 => \v_cmp_reg[11]\(2),
- I4 => s_buff2_reg_1(0),
- I5 => \v_cmp_reg[11]\(1),
- O => \intr_o_i_6__0_n_0\
- );
-\intr_o_reg_i_1__0\: unisim.vcomponents.CARRY4
- port map (
- CI => \intr_o_reg_i_2__0_n_0\,
- CO(3) => \NLW_intr_o_reg_i_1__0_CO_UNCONNECTED\(3),
- CO(2) => CO(0),
- CO(1) => \intr_o_reg_i_1__0_n_2\,
- CO(0) => \intr_o_reg_i_1__0_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0111",
- O(3 downto 0) => \NLW_intr_o_reg_i_1__0_O_UNCONNECTED\(3 downto 0),
- S(3) => '0',
- S(2 downto 0) => \v_cmp_reg[18]\(2 downto 0)
- );
-\intr_o_reg_i_2__0\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \intr_o_reg_i_2__0_n_0\,
- CO(2) => \intr_o_reg_i_2__0_n_1\,
- CO(1) => \intr_o_reg_i_2__0_n_2\,
- CO(0) => \intr_o_reg_i_2__0_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_intr_o_reg_i_2__0_O_UNCONNECTED\(3 downto 0),
- S(3) => \intr_o_i_6__0_n_0\,
- S(2 downto 0) => \v_cmp_reg[6]\(2 downto 0)
- );
-\s_buff1_i_1__28\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_9,
- O => \s_buff1_i_1__28_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__28_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__28\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__76\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__36\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_46 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_8 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_46 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_46;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_46 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__27_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__27\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_8,
- O => \s_buff1_i_1__27_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__27_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__27\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__75\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__35\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_49 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_7 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_49 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_49;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_49 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__26_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__26\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_7,
- O => \s_buff1_i_1__26_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__26_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__26\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__74\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__34\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_52 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_6 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- \v_cmp_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_52 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_52;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_52 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__25_n_0\ : STD_LOGIC;
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\intr_o_i_7__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \v_cmp_reg[8]\(0),
- I1 => \^s_buff3_reg_0\,
- I2 => s_buff2_reg_1(1),
- I3 => \v_cmp_reg[8]\(2),
- I4 => s_buff2_reg_1(0),
- I5 => \v_cmp_reg[8]\(1),
- O => intr_o_reg(0)
- );
-\s_buff1_i_1__25\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_6,
- O => \s_buff1_i_1__25_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__25_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__25\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__73\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__33\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_55 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_5 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_55 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_55;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_55 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__24_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__24\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_5,
- O => \s_buff1_i_1__24_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__24_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__24\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__72\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__32\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_58 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_4 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_58 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_58;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_58 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__23_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__23\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_4,
- O => \s_buff1_i_1__23_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__23_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__23\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__71\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__31\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_61 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_3 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- \v_cmp_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_61 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_61;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_61 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__22_n_0\ : STD_LOGIC;
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\intr_o_i_8__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \v_cmp_reg[5]\(0),
- I1 => \^s_buff3_reg_0\,
- I2 => s_buff2_reg_1(1),
- I3 => \v_cmp_reg[5]\(2),
- I4 => s_buff2_reg_1(0),
- I5 => \v_cmp_reg[5]\(1),
- O => intr_o_reg(0)
- );
-\s_buff1_i_1__22\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_3,
- O => \s_buff1_i_1__22_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__22_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__22\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__70\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__30\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_64 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_2 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_64 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_64;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_64 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__21_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__21\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_2,
- O => \s_buff1_i_1__21_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__21_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__21\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__69\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__29\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_67 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_1 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_67 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_67;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_67 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__20_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__20\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_1,
- O => \s_buff1_i_1__20_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__20_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__20\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__68\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__28\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_70 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_19 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_70 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_70;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_70 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal pulse_i : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__38\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_19,
- O => pulse_i
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => pulse_i,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__38\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__86\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__46\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_73 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_18 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- \v_cmp_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_buff2_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_73 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_73;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_73 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__37_n_0\ : STD_LOGIC;
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\intr_o_i_3__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"9009"
- )
- port map (
- I0 => \v_cmp_reg[19]\(0),
- I1 => \^s_buff3_reg_0\,
- I2 => \v_cmp_reg[19]\(1),
- I3 => s_buff2_reg_1(0),
- O => intr_o_reg(0)
- );
-\s_buff1_i_1__37\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_18,
- O => \s_buff1_i_1__37_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__37_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__37\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__85\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__45\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_76 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_17 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_76 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_76;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_76 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__36_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__36\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_17,
- O => \s_buff1_i_1__36_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__36_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__36\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__84\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__44\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_79 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_16 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_79 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_79;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_79 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__35_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__35\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_16,
- O => \s_buff1_i_1__35_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__35_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__35\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__83\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__43\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_82 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_15 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- \v_cmp_reg[17]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_82 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_82;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_82 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__34_n_0\ : STD_LOGIC;
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\intr_o_i_4__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \v_cmp_reg[17]\(0),
- I1 => \^s_buff3_reg_0\,
- I2 => s_buff2_reg_1(1),
- I3 => \v_cmp_reg[17]\(2),
- I4 => s_buff2_reg_1(0),
- I5 => \v_cmp_reg[17]\(1),
- O => intr_o_reg(0)
- );
-\s_buff1_i_1__34\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_15,
- O => \s_buff1_i_1__34_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__34_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__34\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__82\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__42\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_85 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_14 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_85 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_85;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_85 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__33_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__33\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_14,
- O => \s_buff1_i_1__33_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__33_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__33\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__81\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__41\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_88 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_13 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_88 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_88;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_88 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__32_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__32\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_13,
- O => \s_buff1_i_1__32_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__32_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__32\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__80\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__40\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_91 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- s_buff2_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_12 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- \v_cmp_reg[14]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_91 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_91;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_91 is
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__31_n_0\ : STD_LOGIC;
- signal \^s_buff2_reg_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- s_buff2_reg_0(4 downto 0) <= \^s_buff2_reg_0\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\intr_o_i_5__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => \v_cmp_reg[14]\(0),
- I1 => \^s_buff3_reg_0\,
- I2 => s_buff2_reg_1(1),
- I3 => \v_cmp_reg[14]\(2),
- I4 => s_buff2_reg_1(0),
- I5 => \v_cmp_reg[14]\(1),
- O => intr_o_reg(0)
- );
-\s_buff1_i_1__31\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_12,
- O => \s_buff1_i_1__31_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__31_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__31\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__79\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => s_pulseLed_reg_0,
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^s_buff2_reg_0\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(0),
- Q => \^s_buff2_reg_0\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(1),
- Q => \^s_buff2_reg_0\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(2),
- Q => \^s_buff2_reg_0\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^s_buff2_reg_0\(3),
- Q => \^s_buff2_reg_0\(4),
- R => '0'
- );
-\s_pulseLed_i_6__39\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_94 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_11 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_94 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_94;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_94 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__30_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__30\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_11,
- O => \s_buff1_i_1__30_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__30_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__30\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__78\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__38\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_doubleBufferEdge_97 is
- port (
- s_buff3_reg_0 : out STD_LOGIC;
- s_count_reg : out STD_LOGIC;
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_pulseLed_reg : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- \s_debounce_reg[1]_0\ : in STD_LOGIC;
- s_comparators_i_10 : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_doubleBufferEdge_97 : entity is "doubleBufferEdge";
-end system_design_fasec_hwtest_0_0_doubleBufferEdge_97;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_doubleBufferEdge_97 is
- signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \s_buff1_i_1__29_n_0\ : STD_LOGIC;
- signal s_buff3 : STD_LOGIC;
- signal \^s_buff3_reg_0\ : STD_LOGIC;
-begin
- Q(4 downto 0) <= \^q\(4 downto 0);
- s_buff3_reg_0 <= \^s_buff3_reg_0\;
-\s_buff1_i_1__29\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_comparators_i_10,
- O => \s_buff1_i_1__29_n_0\
- );
-s_buff1_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_buff1_i_1__29_n_0\,
- Q => p_1_in(0),
- R => rst_i
- );
-s_buff2_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_debounce_reg[1]_0\,
- Q => \^s_buff3_reg_0\,
- R => rst_i
- );
-s_buff3_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_buff3_reg_0\,
- Q => s_buff3,
- R => rst_i
- );
-\s_count_reg_i_1__29\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- O => E(0)
- );
-\s_count_reg_i_1__77\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"2F"
- )
- port map (
- I0 => \^s_buff3_reg_0\,
- I1 => s_buff3,
- I2 => D(0),
- O => s_count_reg
- );
-\s_debounce_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => p_1_in(0),
- Q => \^q\(0),
- R => '0'
- );
-\s_debounce_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(0),
- Q => \^q\(1),
- R => '0'
- );
-\s_debounce_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(1),
- Q => \^q\(2),
- R => '0'
- );
-\s_debounce_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(2),
- Q => \^q\(3),
- R => '0'
- );
-\s_debounce_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => s00_axi_aresetn,
- D => \^q\(3),
- Q => \^q\(4),
- R => '0'
- );
-\s_pulseLed_i_6__37\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => s_buff3,
- I1 => \^s_buff3_reg_0\,
- O => s_pulseLed_reg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_spi_transceiver is
- port (
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- \v_ch_address_reg[0]\ : out STD_LOGIC;
- \v_ch_address_reg[1]\ : out STD_LOGIC;
- \s_state_reg[0]\ : out STD_LOGIC;
- \s_state_reg[1]\ : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 0 to 0 );
- \dac_ch_o_reg[0][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
- s_spi_mosi : out STD_LOGIC;
- s_spi_cs_n : out STD_LOGIC;
- \data_rw_o_reg[79][1]\ : in STD_LOGIC;
- \v_ch_address_reg[0]_0\ : in STD_LOGIC;
- \s_state_reg[1]_0\ : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- \s_state_reg[0]_0\ : in STD_LOGIC;
- \[0].[3].s_reqs_reg[3][changed]\ : in STD_LOGIC;
- \[0].[2].s_reqs_reg[2][changed]\ : in STD_LOGIC;
- ch_address : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \[0].[2].s_reqs_reg[2][changed]_0\ : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s_start_reg : in STD_LOGIC;
- \s_tx_data_reg[113]\ : in STD_LOGIC_VECTOR ( 61 downto 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_spi_transceiver : entity is "spi_transceiver";
-end system_design_fasec_hwtest_0_0_spi_transceiver;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_spi_transceiver is
- signal \FSM_sequential_s_state[0]_i_1__0_n_0\ : STD_LOGIC;
- signal \FSM_sequential_s_state[0]_i_2__0_n_0\ : STD_LOGIC;
- signal \FSM_sequential_s_state[0]_i_3__0_n_0\ : STD_LOGIC;
- signal \FSM_sequential_s_state[1]_i_1__0_n_0\ : STD_LOGIC;
- signal \FSM_sequential_s_state[2]_i_1__0_n_0\ : STD_LOGIC;
- signal \FSM_sequential_s_state[2]_i_2__0_n_0\ : STD_LOGIC;
- signal \FSM_sequential_s_state[2]_i_3__0_n_0\ : STD_LOGIC;
- signal \FSM_sequential_s_state[2]_i_4__0_n_0\ : STD_LOGIC;
- signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal p_0_in : STD_LOGIC;
- signal \rx_data_o[31]_i_1__0_n_0\ : STD_LOGIC;
- signal s_counter : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal \s_counter[0]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_counter[1]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_counter[2]_i_1__0_n_0\ : STD_LOGIC;
- signal s_done : STD_LOGIC;
- signal s_rxdat : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s_rxdat_0 : STD_LOGIC;
- signal s_state : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute RTL_KEEP : string;
- attribute RTL_KEEP of s_state : signal is "yes";
- signal \s_state[0]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_state[1]_i_4__0_n_0\ : STD_LOGIC;
- signal s_txdat : STD_LOGIC;
- signal \s_txdat[100]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[101]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[102]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[103]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[104]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[105]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[106]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[107]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[108]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[109]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[10]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[110]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[111]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[112]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[113]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[114]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[115]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[116]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[117]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[118]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[119]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_txdat[119]_i_3__0_n_0\ : STD_LOGIC;
- signal \s_txdat[119]_i_4__0_n_0\ : STD_LOGIC;
- signal \s_txdat[119]_i_5__0_n_0\ : STD_LOGIC;
- signal \s_txdat[11]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[12]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[13]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[14]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[15]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[16]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[17]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[18]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[19]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[20]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[21]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[22]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[23]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[24]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[25]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[26]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[27]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[28]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[29]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[30]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[31]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[32]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[33]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[34]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[35]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[36]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[37]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[38]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[39]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[40]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[41]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[42]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[43]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[44]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[45]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[46]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[47]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[48]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[49]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[4]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[50]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[51]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[52]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[53]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[54]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[55]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[56]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[57]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[58]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[59]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[5]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[60]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[61]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[62]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[63]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[64]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[65]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[66]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[67]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[68]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[69]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[6]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[70]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[71]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[72]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[73]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[74]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[75]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[76]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[77]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[78]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[79]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[7]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[80]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[81]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[82]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[83]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[84]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[85]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[86]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[87]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[88]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[89]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[8]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[90]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[91]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[92]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[93]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[94]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[95]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[96]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[97]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[98]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[99]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat[9]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[100]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[101]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[102]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[103]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[104]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[105]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[106]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[107]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[108]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[109]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[10]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[110]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[111]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[112]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[113]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[114]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[115]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[116]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[117]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[118]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[11]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[12]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[13]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[14]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[15]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[16]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[17]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[18]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[19]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[20]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[21]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[22]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[23]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[24]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[25]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[26]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[27]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[28]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[29]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[30]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[31]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[32]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[33]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[34]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[35]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[36]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[37]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[38]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[39]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[40]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[41]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[42]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[43]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[44]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[45]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[46]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[47]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[48]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[49]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[4]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[50]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[51]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[52]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[53]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[54]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[55]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[56]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[57]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[58]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[59]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[5]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[60]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[61]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[62]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[63]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[64]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[65]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[66]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[67]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[68]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[69]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[6]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[70]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[71]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[72]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[73]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[74]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[75]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[76]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[77]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[78]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[79]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[7]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[80]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[81]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[82]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[83]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[84]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[85]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[86]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[87]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[88]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[89]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[8]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[90]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[91]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[92]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[93]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[94]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[95]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[96]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[97]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[98]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[99]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[9]\ : STD_LOGIC;
- signal v_ch_address : STD_LOGIC;
- signal v_cnt : STD_LOGIC;
- signal \v_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
- signal \v_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
- signal \v_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
- signal \v_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
- signal \v_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
- signal \v_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
- signal \v_cnt[6]_i_2__0_n_0\ : STD_LOGIC;
- signal \v_cnt[6]_i_3__0_n_0\ : STD_LOGIC;
- signal \v_cnt[6]_i_4__0_n_0\ : STD_LOGIC;
- signal \v_cnt[6]_i_5__0_n_0\ : STD_LOGIC;
- signal \v_cnt_reg_n_0_[0]\ : STD_LOGIC;
- signal \v_cnt_reg_n_0_[1]\ : STD_LOGIC;
- signal \v_cnt_reg_n_0_[2]\ : STD_LOGIC;
- signal \v_cnt_reg_n_0_[3]\ : STD_LOGIC;
- signal \v_cnt_reg_n_0_[4]\ : STD_LOGIC;
- signal \v_cnt_reg_n_0_[5]\ : STD_LOGIC;
- signal \v_cnt_reg_n_0_[6]\ : STD_LOGIC;
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \FSM_sequential_s_state[2]_i_4__0\ : label is "soft_lutpair48";
- attribute KEEP : string;
- attribute KEEP of \FSM_sequential_s_state_reg[0]\ : label is "yes";
- attribute KEEP of \FSM_sequential_s_state_reg[1]\ : label is "yes";
- attribute KEEP of \FSM_sequential_s_state_reg[2]\ : label is "yes";
- attribute SOFT_HLUTNM of \s_counter[0]_i_1__0\ : label is "soft_lutpair52";
- attribute SOFT_HLUTNM of \s_counter[1]_i_1__0\ : label is "soft_lutpair52";
- attribute SOFT_HLUTNM of \s_counter[2]_i_1__0\ : label is "soft_lutpair51";
- attribute SOFT_HLUTNM of \s_txdat[119]_i_3__0\ : label is "soft_lutpair51";
- attribute SOFT_HLUTNM of \s_txdat[119]_i_4__0\ : label is "soft_lutpair49";
- attribute SOFT_HLUTNM of \s_txdat[119]_i_5__0\ : label is "soft_lutpair48";
- attribute SOFT_HLUTNM of \v_ch_address[0]_i_1__0\ : label is "soft_lutpair50";
- attribute SOFT_HLUTNM of \v_ch_address[1]_i_1__0\ : label is "soft_lutpair50";
- attribute SOFT_HLUTNM of \v_cnt[6]_i_5__0\ : label is "soft_lutpair49";
-begin
- Q(0) <= \^q\(0);
-\FSM_sequential_s_state[0]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => \FSM_sequential_s_state[0]_i_2__0_n_0\,
- I1 => \FSM_sequential_s_state[2]_i_2__0_n_0\,
- I2 => s_state(0),
- O => \FSM_sequential_s_state[0]_i_1__0_n_0\
- );
-\FSM_sequential_s_state[0]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFF00FFFFFF00"
- )
- port map (
- I0 => \v_cnt_reg_n_0_[0]\,
- I1 => \v_cnt_reg_n_0_[1]\,
- I2 => \v_cnt_reg_n_0_[2]\,
- I3 => \FSM_sequential_s_state[0]_i_3__0_n_0\,
- I4 => s_state(1),
- I5 => \v_cnt_reg_n_0_[3]\,
- O => \FSM_sequential_s_state[0]_i_2__0_n_0\
- );
-\FSM_sequential_s_state[0]_i_3__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"77C3FFC3FFC3FFC3"
- )
- port map (
- I0 => \v_cnt_reg_n_0_[4]\,
- I1 => s_state(0),
- I2 => s_state(2),
- I3 => s_state(1),
- I4 => \v_cnt_reg_n_0_[6]\,
- I5 => \v_cnt_reg_n_0_[5]\,
- O => \FSM_sequential_s_state[0]_i_3__0_n_0\
- );
-\FSM_sequential_s_state[1]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"6F60"
- )
- port map (
- I0 => s_state(0),
- I1 => s_state(1),
- I2 => \FSM_sequential_s_state[2]_i_2__0_n_0\,
- I3 => s_state(1),
- O => \FSM_sequential_s_state[1]_i_1__0_n_0\
- );
-\FSM_sequential_s_state[2]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"8F80"
- )
- port map (
- I0 => s_state(1),
- I1 => s_state(0),
- I2 => \FSM_sequential_s_state[2]_i_2__0_n_0\,
- I3 => s_state(2),
- O => \FSM_sequential_s_state[2]_i_1__0_n_0\
- );
-\FSM_sequential_s_state[2]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"ABEEAAAAAAEEAAAA"
- )
- port map (
- I0 => \FSM_sequential_s_state[2]_i_3__0_n_0\,
- I1 => s_state(0),
- I2 => s_state(1),
- I3 => s_state(2),
- I4 => \s_txdat[119]_i_3__0_n_0\,
- I5 => \FSM_sequential_s_state[2]_i_4__0_n_0\,
- O => \FSM_sequential_s_state[2]_i_2__0_n_0\
- );
-\FSM_sequential_s_state[2]_i_3__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF0010"
- )
- port map (
- I0 => s_state(1),
- I1 => s_state(2),
- I2 => s_start_reg,
- I3 => s_state(0),
- I4 => s_rxdat_0,
- O => \FSM_sequential_s_state[2]_i_3__0_n_0\
- );
-\FSM_sequential_s_state[2]_i_4__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => \v_cnt_reg_n_0_[2]\,
- I1 => \v_cnt_reg_n_0_[5]\,
- I2 => \v_cnt_reg_n_0_[6]\,
- I3 => \v_cnt_reg_n_0_[4]\,
- I4 => \v_cnt_reg_n_0_[3]\,
- O => \FSM_sequential_s_state[2]_i_4__0_n_0\
- );
-\FSM_sequential_s_state_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \FSM_sequential_s_state[0]_i_1__0_n_0\,
- Q => s_state(0),
- R => rst_i
- );
-\FSM_sequential_s_state_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \FSM_sequential_s_state[1]_i_1__0_n_0\,
- Q => s_state(1),
- R => rst_i
- );
-\FSM_sequential_s_state_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \FSM_sequential_s_state[2]_i_1__0_n_0\,
- Q => s_state(2),
- R => rst_i
- );
-\dac_ch_o[0][31]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000002000000"
- )
- port map (
- I0 => \s_state_reg[1]_0\,
- I1 => s_state(1),
- I2 => s_state(0),
- I3 => s00_axi_aresetn,
- I4 => \s_state_reg[0]_0\,
- I5 => \v_ch_address_reg[0]_0\,
- O => E(0)
- );
-\gen_spi.cmp_spi_cs_n_iobuf_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"07"
- )
- port map (
- I0 => s_state(0),
- I1 => s_state(2),
- I2 => s_state(1),
- O => s_spi_cs_n
- );
-\gen_spi.cmp_spi_mosi_iobuf_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"2B3B"
- )
- port map (
- I0 => p_0_in,
- I1 => s_state(1),
- I2 => s_state(2),
- I3 => s_state(0),
- O => s_spi_mosi
- );
-\rx_data_o[31]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0002"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s_state(0),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \rx_data_o[31]_i_1__0_n_0\
- );
-\rx_data_o_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(0),
- Q => \dac_ch_o_reg[0][31]\(0),
- R => '0'
- );
-\rx_data_o_reg[10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(10),
- Q => \dac_ch_o_reg[0][31]\(10),
- R => '0'
- );
-\rx_data_o_reg[11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(11),
- Q => \dac_ch_o_reg[0][31]\(11),
- R => '0'
- );
-\rx_data_o_reg[12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(12),
- Q => \dac_ch_o_reg[0][31]\(12),
- R => '0'
- );
-\rx_data_o_reg[13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(13),
- Q => \dac_ch_o_reg[0][31]\(13),
- R => '0'
- );
-\rx_data_o_reg[14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(14),
- Q => \dac_ch_o_reg[0][31]\(14),
- R => '0'
- );
-\rx_data_o_reg[15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(15),
- Q => \dac_ch_o_reg[0][31]\(15),
- R => '0'
- );
-\rx_data_o_reg[16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(16),
- Q => \dac_ch_o_reg[0][31]\(16),
- R => '0'
- );
-\rx_data_o_reg[17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(17),
- Q => \dac_ch_o_reg[0][31]\(17),
- R => '0'
- );
-\rx_data_o_reg[18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(18),
- Q => \dac_ch_o_reg[0][31]\(18),
- R => '0'
- );
-\rx_data_o_reg[19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(19),
- Q => \dac_ch_o_reg[0][31]\(19),
- R => '0'
- );
-\rx_data_o_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(1),
- Q => \dac_ch_o_reg[0][31]\(1),
- R => '0'
- );
-\rx_data_o_reg[20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(20),
- Q => \dac_ch_o_reg[0][31]\(20),
- R => '0'
- );
-\rx_data_o_reg[21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(21),
- Q => \dac_ch_o_reg[0][31]\(21),
- R => '0'
- );
-\rx_data_o_reg[22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(22),
- Q => \dac_ch_o_reg[0][31]\(22),
- R => '0'
- );
-\rx_data_o_reg[23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(23),
- Q => \dac_ch_o_reg[0][31]\(23),
- R => '0'
- );
-\rx_data_o_reg[24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(24),
- Q => \dac_ch_o_reg[0][31]\(24),
- R => '0'
- );
-\rx_data_o_reg[25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(25),
- Q => \dac_ch_o_reg[0][31]\(25),
- R => '0'
- );
-\rx_data_o_reg[26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(26),
- Q => \dac_ch_o_reg[0][31]\(26),
- R => '0'
- );
-\rx_data_o_reg[27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(27),
- Q => \dac_ch_o_reg[0][31]\(27),
- R => '0'
- );
-\rx_data_o_reg[28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(28),
- Q => \dac_ch_o_reg[0][31]\(28),
- R => '0'
- );
-\rx_data_o_reg[29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(29),
- Q => \dac_ch_o_reg[0][31]\(29),
- R => '0'
- );
-\rx_data_o_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(2),
- Q => \dac_ch_o_reg[0][31]\(2),
- R => '0'
- );
-\rx_data_o_reg[30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(30),
- Q => \dac_ch_o_reg[0][31]\(30),
- R => '0'
- );
-\rx_data_o_reg[31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(31),
- Q => \dac_ch_o_reg[0][31]\(31),
- R => '0'
- );
-\rx_data_o_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(3),
- Q => \dac_ch_o_reg[0][31]\(3),
- R => '0'
- );
-\rx_data_o_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(4),
- Q => \dac_ch_o_reg[0][31]\(4),
- R => '0'
- );
-\rx_data_o_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(5),
- Q => \dac_ch_o_reg[0][31]\(5),
- R => '0'
- );
-\rx_data_o_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(6),
- Q => \dac_ch_o_reg[0][31]\(6),
- R => '0'
- );
-\rx_data_o_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(7),
- Q => \dac_ch_o_reg[0][31]\(7),
- R => '0'
- );
-\rx_data_o_reg[8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(8),
- Q => \dac_ch_o_reg[0][31]\(8),
- R => '0'
- );
-\rx_data_o_reg[9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1__0_n_0\,
- D => s_rxdat(9),
- Q => \dac_ch_o_reg[0][31]\(9),
- R => '0'
- );
-\s_counter[0]_i_1__0\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_counter(0),
- O => \s_counter[0]_i_1__0_n_0\
- );
-\s_counter[1]_i_1__0\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"6"
- )
- port map (
- I0 => s_counter(0),
- I1 => s_counter(1),
- O => \s_counter[1]_i_1__0_n_0\
- );
-\s_counter[2]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"6A"
- )
- port map (
- I0 => \^q\(0),
- I1 => s_counter(0),
- I2 => s_counter(1),
- O => \s_counter[2]_i_1__0_n_0\
- );
-\s_counter_reg[0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_counter[0]_i_1__0_n_0\,
- Q => s_counter(0),
- R => rst_i
- );
-\s_counter_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_counter[1]_i_1__0_n_0\,
- Q => s_counter(1),
- R => rst_i
- );
-\s_counter_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_counter[2]_i_1__0_n_0\,
- Q => \^q\(0),
- R => rst_i
- );
-\s_rxdat[31]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"2400000000000000"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => s_state(0),
- I3 => s_counter(0),
- I4 => s_counter(1),
- I5 => \^q\(0),
- O => s_rxdat_0
- );
-\s_rxdat_reg[0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => D(0),
- Q => s_rxdat(0),
- R => rst_i
- );
-\s_rxdat_reg[10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(9),
- Q => s_rxdat(10),
- R => rst_i
- );
-\s_rxdat_reg[11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(10),
- Q => s_rxdat(11),
- R => rst_i
- );
-\s_rxdat_reg[12]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(11),
- Q => s_rxdat(12),
- R => rst_i
- );
-\s_rxdat_reg[13]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(12),
- Q => s_rxdat(13),
- R => rst_i
- );
-\s_rxdat_reg[14]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(13),
- Q => s_rxdat(14),
- R => rst_i
- );
-\s_rxdat_reg[15]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(14),
- Q => s_rxdat(15),
- R => rst_i
- );
-\s_rxdat_reg[16]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(15),
- Q => s_rxdat(16),
- R => rst_i
- );
-\s_rxdat_reg[17]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(16),
- Q => s_rxdat(17),
- R => rst_i
- );
-\s_rxdat_reg[18]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(17),
- Q => s_rxdat(18),
- R => rst_i
- );
-\s_rxdat_reg[19]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(18),
- Q => s_rxdat(19),
- R => rst_i
- );
-\s_rxdat_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(0),
- Q => s_rxdat(1),
- R => rst_i
- );
-\s_rxdat_reg[20]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(19),
- Q => s_rxdat(20),
- R => rst_i
- );
-\s_rxdat_reg[21]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(20),
- Q => s_rxdat(21),
- R => rst_i
- );
-\s_rxdat_reg[22]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(21),
- Q => s_rxdat(22),
- R => rst_i
- );
-\s_rxdat_reg[23]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(22),
- Q => s_rxdat(23),
- R => rst_i
- );
-\s_rxdat_reg[24]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(23),
- Q => s_rxdat(24),
- R => rst_i
- );
-\s_rxdat_reg[25]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(24),
- Q => s_rxdat(25),
- R => rst_i
- );
-\s_rxdat_reg[26]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(25),
- Q => s_rxdat(26),
- R => rst_i
- );
-\s_rxdat_reg[27]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(26),
- Q => s_rxdat(27),
- R => rst_i
- );
-\s_rxdat_reg[28]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(27),
- Q => s_rxdat(28),
- R => rst_i
- );
-\s_rxdat_reg[29]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(28),
- Q => s_rxdat(29),
- R => rst_i
- );
-\s_rxdat_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(1),
- Q => s_rxdat(2),
- R => rst_i
- );
-\s_rxdat_reg[30]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(29),
- Q => s_rxdat(30),
- R => rst_i
- );
-\s_rxdat_reg[31]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(30),
- Q => s_rxdat(31),
- R => rst_i
- );
-\s_rxdat_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(2),
- Q => s_rxdat(3),
- R => rst_i
- );
-\s_rxdat_reg[4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(3),
- Q => s_rxdat(4),
- R => rst_i
- );
-\s_rxdat_reg[5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(4),
- Q => s_rxdat(5),
- R => rst_i
- );
-\s_rxdat_reg[6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(5),
- Q => s_rxdat(6),
- R => rst_i
- );
-\s_rxdat_reg[7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(6),
- Q => s_rxdat(7),
- R => rst_i
- );
-\s_rxdat_reg[8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(7),
- Q => s_rxdat(8),
- R => rst_i
- );
-\s_rxdat_reg[9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(8),
- Q => s_rxdat(9),
- R => rst_i
- );
-\s_state[0]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"2AFFFF00"
- )
- port map (
- I0 => \s_state_reg[1]_0\,
- I1 => ch_address(0),
- I2 => ch_address(1),
- I3 => \s_state[0]_i_2__0_n_0\,
- I4 => \s_state_reg[0]_0\,
- O => \s_state_reg[0]\
- );
-\s_state[0]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FAFFAFFAFABFAFBA"
- )
- port map (
- I0 => \[0].[3].s_reqs_reg[3][changed]\,
- I1 => \v_ch_address_reg[0]_0\,
- I2 => \s_state_reg[0]_0\,
- I3 => \s_state_reg[1]_0\,
- I4 => s_done,
- I5 => \[0].[2].s_reqs_reg[2][changed]\,
- O => \s_state[0]_i_2__0_n_0\
- );
-\s_state[1]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FDFFFCF0"
- )
- port map (
- I0 => \s_state_reg[0]_0\,
- I1 => \[0].[2].s_reqs_reg[2][changed]_0\,
- I2 => \[0].[3].s_reqs_reg[3][changed]\,
- I3 => \s_state[1]_i_4__0_n_0\,
- I4 => \s_state_reg[1]_0\,
- O => \s_state_reg[1]\
- );
-\s_state[1]_i_4__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"CF3CCA3CCA3CCA3C"
- )
- port map (
- I0 => \[0].[2].s_reqs_reg[2][changed]\,
- I1 => s_done,
- I2 => \s_state_reg[1]_0\,
- I3 => \s_state_reg[0]_0\,
- I4 => ch_address(1),
- I5 => ch_address(0),
- O => \s_state[1]_i_4__0_n_0\
- );
-\s_txdat[100]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[99]\,
- I1 => \s_tx_data_reg[113]\(48),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[100]_i_1__0_n_0\
- );
-\s_txdat[101]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[100]\,
- I1 => \s_tx_data_reg[113]\(49),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[101]_i_1__0_n_0\
- );
-\s_txdat[102]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[101]\,
- I1 => \s_tx_data_reg[113]\(50),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[102]_i_1__0_n_0\
- );
-\s_txdat[103]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[102]\,
- I1 => \s_tx_data_reg[113]\(51),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[103]_i_1__0_n_0\
- );
-\s_txdat[104]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[103]\,
- I1 => \s_tx_data_reg[113]\(52),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[104]_i_1__0_n_0\
- );
-\s_txdat[105]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[104]\,
- I1 => \s_tx_data_reg[113]\(53),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[105]_i_1__0_n_0\
- );
-\s_txdat[106]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[105]\,
- I1 => \s_tx_data_reg[113]\(54),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[106]_i_1__0_n_0\
- );
-\s_txdat[107]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[106]\,
- I1 => \s_tx_data_reg[113]\(55),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[107]_i_1__0_n_0\
- );
-\s_txdat[108]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[107]\,
- I1 => \s_tx_data_reg[113]\(56),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[108]_i_1__0_n_0\
- );
-\s_txdat[109]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[108]\,
- I1 => \s_tx_data_reg[113]\(57),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[109]_i_1__0_n_0\
- );
-\s_txdat[10]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[9]\,
- I1 => \s_tx_data_reg[113]\(6),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[10]_i_1__0_n_0\
- );
-\s_txdat[110]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[109]\,
- I1 => \s_tx_data_reg[113]\(58),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[110]_i_1__0_n_0\
- );
-\s_txdat[111]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[110]\,
- I1 => \s_tx_data_reg[113]\(59),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[111]_i_1__0_n_0\
- );
-\s_txdat[112]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[111]\,
- I1 => \s_tx_data_reg[113]\(60),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[112]_i_1__0_n_0\
- );
-\s_txdat[113]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[112]\,
- I1 => \s_tx_data_reg[113]\(61),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[113]_i_1__0_n_0\
- );
-\s_txdat[114]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"23"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[113]\,
- I1 => s_state(2),
- I2 => s_state(1),
- O => \s_txdat[114]_i_1__0_n_0\
- );
-\s_txdat[115]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[114]\,
- O => \s_txdat[115]_i_1__0_n_0\
- );
-\s_txdat[116]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[115]\,
- O => \s_txdat[116]_i_1__0_n_0\
- );
-\s_txdat[117]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[116]\,
- O => \s_txdat[117]_i_1__0_n_0\
- );
-\s_txdat[118]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[117]\,
- O => \s_txdat[118]_i_1__0_n_0\
- );
-\s_txdat[119]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"00800080000F0000"
- )
- port map (
- I0 => \s_txdat[119]_i_3__0_n_0\,
- I1 => \s_txdat[119]_i_4__0_n_0\,
- I2 => s_state(1),
- I3 => s_state(2),
- I4 => s_start_reg,
- I5 => s_state(0),
- O => s_txdat
- );
-\s_txdat[119]_i_2__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[118]\,
- O => \s_txdat[119]_i_2__0_n_0\
- );
-\s_txdat[119]_i_3__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"08"
- )
- port map (
- I0 => s_counter(1),
- I1 => s_counter(0),
- I2 => \^q\(0),
- O => \s_txdat[119]_i_3__0_n_0\
- );
-\s_txdat[119]_i_4__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => \v_cnt_reg_n_0_[2]\,
- I1 => \v_cnt_reg_n_0_[6]\,
- I2 => \v_cnt_reg_n_0_[0]\,
- I3 => \v_cnt_reg_n_0_[1]\,
- I4 => \s_txdat[119]_i_5__0_n_0\,
- O => \s_txdat[119]_i_4__0_n_0\
- );
-\s_txdat[119]_i_5__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"7F"
- )
- port map (
- I0 => \v_cnt_reg_n_0_[4]\,
- I1 => \v_cnt_reg_n_0_[3]\,
- I2 => \v_cnt_reg_n_0_[5]\,
- O => \s_txdat[119]_i_5__0_n_0\
- );
-\s_txdat[11]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[10]\,
- I1 => \s_tx_data_reg[113]\(7),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[11]_i_1__0_n_0\
- );
-\s_txdat[12]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[11]\,
- I1 => \s_tx_data_reg[113]\(8),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[12]_i_1__0_n_0\
- );
-\s_txdat[13]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[12]\,
- I1 => \s_tx_data_reg[113]\(9),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[13]_i_1__0_n_0\
- );
-\s_txdat[14]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[13]\,
- I1 => \s_tx_data_reg[113]\(10),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[14]_i_1__0_n_0\
- );
-\s_txdat[15]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[14]\,
- I1 => \s_tx_data_reg[113]\(11),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[15]_i_1__0_n_0\
- );
-\s_txdat[16]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[15]\,
- I1 => \s_tx_data_reg[113]\(60),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[16]_i_1__0_n_0\
- );
-\s_txdat[17]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[16]\,
- I1 => \s_tx_data_reg[113]\(61),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[17]_i_1__0_n_0\
- );
-\s_txdat[18]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"23"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[17]\,
- I1 => s_state(2),
- I2 => s_state(1),
- O => \s_txdat[18]_i_1__0_n_0\
- );
-\s_txdat[19]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[18]\,
- O => \s_txdat[19]_i_1__0_n_0\
- );
-\s_txdat[20]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[19]\,
- O => \s_txdat[20]_i_1__0_n_0\
- );
-\s_txdat[21]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[20]\,
- O => \s_txdat[21]_i_1__0_n_0\
- );
-\s_txdat[22]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[21]\,
- O => \s_txdat[22]_i_1__0_n_0\
- );
-\s_txdat[23]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[22]\,
- O => \s_txdat[23]_i_1__0_n_0\
- );
-\s_txdat[24]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[23]\,
- O => \s_txdat[24]_i_1__0_n_0\
- );
-\s_txdat[25]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[24]\,
- O => \s_txdat[25]_i_1__0_n_0\
- );
-\s_txdat[26]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[25]\,
- O => \s_txdat[26]_i_1__0_n_0\
- );
-\s_txdat[27]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[26]\,
- O => \s_txdat[27]_i_1__0_n_0\
- );
-\s_txdat[28]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[27]\,
- I1 => \s_tx_data_reg[113]\(12),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[28]_i_1__0_n_0\
- );
-\s_txdat[29]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[28]\,
- I1 => \s_tx_data_reg[113]\(13),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[29]_i_1__0_n_0\
- );
-\s_txdat[30]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[29]\,
- I1 => \s_tx_data_reg[113]\(14),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[30]_i_1__0_n_0\
- );
-\s_txdat[31]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[30]\,
- I1 => \s_tx_data_reg[113]\(15),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[31]_i_1__0_n_0\
- );
-\s_txdat[32]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[31]\,
- I1 => \s_tx_data_reg[113]\(16),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[32]_i_1__0_n_0\
- );
-\s_txdat[33]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[32]\,
- I1 => \s_tx_data_reg[113]\(17),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[33]_i_1__0_n_0\
- );
-\s_txdat[34]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[33]\,
- I1 => \s_tx_data_reg[113]\(18),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[34]_i_1__0_n_0\
- );
-\s_txdat[35]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[34]\,
- I1 => \s_tx_data_reg[113]\(19),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[35]_i_1__0_n_0\
- );
-\s_txdat[36]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[35]\,
- I1 => \s_tx_data_reg[113]\(20),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[36]_i_1__0_n_0\
- );
-\s_txdat[37]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[36]\,
- I1 => \s_tx_data_reg[113]\(21),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[37]_i_1__0_n_0\
- );
-\s_txdat[38]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[37]\,
- I1 => \s_tx_data_reg[113]\(22),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[38]_i_1__0_n_0\
- );
-\s_txdat[39]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[38]\,
- I1 => \s_tx_data_reg[113]\(23),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[39]_i_1__0_n_0\
- );
-\s_txdat[40]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[39]\,
- I1 => \s_tx_data_reg[113]\(60),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[40]_i_1__0_n_0\
- );
-\s_txdat[41]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[40]\,
- I1 => \s_tx_data_reg[113]\(61),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[41]_i_1__0_n_0\
- );
-\s_txdat[42]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"23"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[41]\,
- I1 => s_state(2),
- I2 => s_state(1),
- O => \s_txdat[42]_i_1__0_n_0\
- );
-\s_txdat[43]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[42]\,
- O => \s_txdat[43]_i_1__0_n_0\
- );
-\s_txdat[44]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[43]\,
- O => \s_txdat[44]_i_1__0_n_0\
- );
-\s_txdat[45]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[44]\,
- O => \s_txdat[45]_i_1__0_n_0\
- );
-\s_txdat[46]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[45]\,
- O => \s_txdat[46]_i_1__0_n_0\
- );
-\s_txdat[47]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[46]\,
- O => \s_txdat[47]_i_1__0_n_0\
- );
-\s_txdat[48]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[47]\,
- O => \s_txdat[48]_i_1__0_n_0\
- );
-\s_txdat[49]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[48]\,
- O => \s_txdat[49]_i_1__0_n_0\
- );
-\s_txdat[4]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"10"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_tx_data_reg[113]\(0),
- O => \s_txdat[4]_i_1__0_n_0\
- );
-\s_txdat[50]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[49]\,
- O => \s_txdat[50]_i_1__0_n_0\
- );
-\s_txdat[51]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[50]\,
- O => \s_txdat[51]_i_1__0_n_0\
- );
-\s_txdat[52]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[51]\,
- I1 => \s_tx_data_reg[113]\(24),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[52]_i_1__0_n_0\
- );
-\s_txdat[53]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[52]\,
- I1 => \s_tx_data_reg[113]\(25),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[53]_i_1__0_n_0\
- );
-\s_txdat[54]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[53]\,
- I1 => \s_tx_data_reg[113]\(26),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[54]_i_1__0_n_0\
- );
-\s_txdat[55]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[54]\,
- I1 => \s_tx_data_reg[113]\(27),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[55]_i_1__0_n_0\
- );
-\s_txdat[56]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[55]\,
- I1 => \s_tx_data_reg[113]\(28),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[56]_i_1__0_n_0\
- );
-\s_txdat[57]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[56]\,
- I1 => \s_tx_data_reg[113]\(29),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[57]_i_1__0_n_0\
- );
-\s_txdat[58]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[57]\,
- I1 => \s_tx_data_reg[113]\(30),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[58]_i_1__0_n_0\
- );
-\s_txdat[59]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[58]\,
- I1 => \s_tx_data_reg[113]\(31),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[59]_i_1__0_n_0\
- );
-\s_txdat[5]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[4]\,
- I1 => \s_tx_data_reg[113]\(1),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[5]_i_1__0_n_0\
- );
-\s_txdat[60]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[59]\,
- I1 => \s_tx_data_reg[113]\(32),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[60]_i_1__0_n_0\
- );
-\s_txdat[61]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[60]\,
- I1 => \s_tx_data_reg[113]\(33),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[61]_i_1__0_n_0\
- );
-\s_txdat[62]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[61]\,
- I1 => \s_tx_data_reg[113]\(34),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[62]_i_1__0_n_0\
- );
-\s_txdat[63]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[62]\,
- I1 => \s_tx_data_reg[113]\(35),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[63]_i_1__0_n_0\
- );
-\s_txdat[64]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[63]\,
- I1 => \s_tx_data_reg[113]\(60),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[64]_i_1__0_n_0\
- );
-\s_txdat[65]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[64]\,
- I1 => \s_tx_data_reg[113]\(61),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[65]_i_1__0_n_0\
- );
-\s_txdat[66]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"23"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[65]\,
- I1 => s_state(2),
- I2 => s_state(1),
- O => \s_txdat[66]_i_1__0_n_0\
- );
-\s_txdat[67]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[66]\,
- O => \s_txdat[67]_i_1__0_n_0\
- );
-\s_txdat[68]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[67]\,
- O => \s_txdat[68]_i_1__0_n_0\
- );
-\s_txdat[69]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[68]\,
- O => \s_txdat[69]_i_1__0_n_0\
- );
-\s_txdat[6]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[5]\,
- I1 => \s_tx_data_reg[113]\(2),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[6]_i_1__0_n_0\
- );
-\s_txdat[70]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[69]\,
- O => \s_txdat[70]_i_1__0_n_0\
- );
-\s_txdat[71]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[70]\,
- O => \s_txdat[71]_i_1__0_n_0\
- );
-\s_txdat[72]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[71]\,
- O => \s_txdat[72]_i_1__0_n_0\
- );
-\s_txdat[73]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[72]\,
- O => \s_txdat[73]_i_1__0_n_0\
- );
-\s_txdat[74]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[73]\,
- O => \s_txdat[74]_i_1__0_n_0\
- );
-\s_txdat[75]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[74]\,
- O => \s_txdat[75]_i_1__0_n_0\
- );
-\s_txdat[76]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[75]\,
- I1 => \s_tx_data_reg[113]\(36),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[76]_i_1__0_n_0\
- );
-\s_txdat[77]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[76]\,
- I1 => \s_tx_data_reg[113]\(37),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[77]_i_1__0_n_0\
- );
-\s_txdat[78]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[77]\,
- I1 => \s_tx_data_reg[113]\(38),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[78]_i_1__0_n_0\
- );
-\s_txdat[79]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[78]\,
- I1 => \s_tx_data_reg[113]\(39),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[79]_i_1__0_n_0\
- );
-\s_txdat[7]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[6]\,
- I1 => \s_tx_data_reg[113]\(3),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[7]_i_1__0_n_0\
- );
-\s_txdat[80]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[79]\,
- I1 => \s_tx_data_reg[113]\(40),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[80]_i_1__0_n_0\
- );
-\s_txdat[81]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[80]\,
- I1 => \s_tx_data_reg[113]\(41),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[81]_i_1__0_n_0\
- );
-\s_txdat[82]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[81]\,
- I1 => \s_tx_data_reg[113]\(42),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[82]_i_1__0_n_0\
- );
-\s_txdat[83]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[82]\,
- I1 => \s_tx_data_reg[113]\(43),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[83]_i_1__0_n_0\
- );
-\s_txdat[84]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[83]\,
- I1 => \s_tx_data_reg[113]\(44),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[84]_i_1__0_n_0\
- );
-\s_txdat[85]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[84]\,
- I1 => \s_tx_data_reg[113]\(45),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[85]_i_1__0_n_0\
- );
-\s_txdat[86]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[85]\,
- I1 => \s_tx_data_reg[113]\(46),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[86]_i_1__0_n_0\
- );
-\s_txdat[87]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[86]\,
- I1 => \s_tx_data_reg[113]\(47),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[87]_i_1__0_n_0\
- );
-\s_txdat[88]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[87]\,
- I1 => \s_tx_data_reg[113]\(60),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[88]_i_1__0_n_0\
- );
-\s_txdat[89]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[88]\,
- I1 => \s_tx_data_reg[113]\(61),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[89]_i_1__0_n_0\
- );
-\s_txdat[8]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[7]\,
- I1 => \s_tx_data_reg[113]\(4),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[8]_i_1__0_n_0\
- );
-\s_txdat[90]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"23"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[89]\,
- I1 => s_state(2),
- I2 => s_state(1),
- O => \s_txdat[90]_i_1__0_n_0\
- );
-\s_txdat[91]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[90]\,
- O => \s_txdat[91]_i_1__0_n_0\
- );
-\s_txdat[92]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[91]\,
- O => \s_txdat[92]_i_1__0_n_0\
- );
-\s_txdat[93]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[92]\,
- O => \s_txdat[93]_i_1__0_n_0\
- );
-\s_txdat[94]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[93]\,
- O => \s_txdat[94]_i_1__0_n_0\
- );
-\s_txdat[95]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[94]\,
- O => \s_txdat[95]_i_1__0_n_0\
- );
-\s_txdat[96]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[95]\,
- O => \s_txdat[96]_i_1__0_n_0\
- );
-\s_txdat[97]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[96]\,
- O => \s_txdat[97]_i_1__0_n_0\
- );
-\s_txdat[98]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[97]\,
- O => \s_txdat[98]_i_1__0_n_0\
- );
-\s_txdat[99]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[98]\,
- O => \s_txdat[99]_i_1__0_n_0\
- );
-\s_txdat[9]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[8]\,
- I1 => \s_tx_data_reg[113]\(5),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[9]_i_1__0_n_0\
- );
-\s_txdat_reg[100]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[100]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[100]\,
- R => rst_i
- );
-\s_txdat_reg[101]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[101]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[101]\,
- R => rst_i
- );
-\s_txdat_reg[102]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[102]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[102]\,
- R => rst_i
- );
-\s_txdat_reg[103]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[103]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[103]\,
- R => rst_i
- );
-\s_txdat_reg[104]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[104]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[104]\,
- R => rst_i
- );
-\s_txdat_reg[105]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[105]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[105]\,
- R => rst_i
- );
-\s_txdat_reg[106]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[106]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[106]\,
- R => rst_i
- );
-\s_txdat_reg[107]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[107]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[107]\,
- R => rst_i
- );
-\s_txdat_reg[108]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[108]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[108]\,
- R => rst_i
- );
-\s_txdat_reg[109]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[109]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[109]\,
- R => rst_i
- );
-\s_txdat_reg[10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[10]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[10]\,
- R => rst_i
- );
-\s_txdat_reg[110]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[110]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[110]\,
- R => rst_i
- );
-\s_txdat_reg[111]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[111]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[111]\,
- R => rst_i
- );
-\s_txdat_reg[112]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[112]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[112]\,
- R => rst_i
- );
-\s_txdat_reg[113]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[113]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[113]\,
- R => rst_i
- );
-\s_txdat_reg[114]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[114]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[114]\,
- R => rst_i
- );
-\s_txdat_reg[115]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[115]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[115]\,
- R => rst_i
- );
-\s_txdat_reg[116]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[116]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[116]\,
- R => rst_i
- );
-\s_txdat_reg[117]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[117]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[117]\,
- R => rst_i
- );
-\s_txdat_reg[118]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[118]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[118]\,
- R => rst_i
- );
-\s_txdat_reg[119]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[119]_i_2__0_n_0\,
- Q => p_0_in,
- R => rst_i
- );
-\s_txdat_reg[11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[11]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[11]\,
- R => rst_i
- );
-\s_txdat_reg[12]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[12]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[12]\,
- R => rst_i
- );
-\s_txdat_reg[13]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[13]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[13]\,
- R => rst_i
- );
-\s_txdat_reg[14]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[14]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[14]\,
- R => rst_i
- );
-\s_txdat_reg[15]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[15]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[15]\,
- R => rst_i
- );
-\s_txdat_reg[16]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[16]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[16]\,
- R => rst_i
- );
-\s_txdat_reg[17]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[17]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[17]\,
- R => rst_i
- );
-\s_txdat_reg[18]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[18]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[18]\,
- R => rst_i
- );
-\s_txdat_reg[19]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[19]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[19]\,
- R => rst_i
- );
-\s_txdat_reg[20]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[20]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[20]\,
- R => rst_i
- );
-\s_txdat_reg[21]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[21]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[21]\,
- R => rst_i
- );
-\s_txdat_reg[22]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[22]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[22]\,
- R => rst_i
- );
-\s_txdat_reg[23]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[23]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[23]\,
- R => rst_i
- );
-\s_txdat_reg[24]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[24]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[24]\,
- R => rst_i
- );
-\s_txdat_reg[25]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[25]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[25]\,
- R => rst_i
- );
-\s_txdat_reg[26]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[26]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[26]\,
- R => rst_i
- );
-\s_txdat_reg[27]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[27]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[27]\,
- R => rst_i
- );
-\s_txdat_reg[28]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[28]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[28]\,
- R => rst_i
- );
-\s_txdat_reg[29]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[29]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[29]\,
- R => rst_i
- );
-\s_txdat_reg[30]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[30]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[30]\,
- R => rst_i
- );
-\s_txdat_reg[31]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[31]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[31]\,
- R => rst_i
- );
-\s_txdat_reg[32]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[32]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[32]\,
- R => rst_i
- );
-\s_txdat_reg[33]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[33]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[33]\,
- R => rst_i
- );
-\s_txdat_reg[34]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[34]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[34]\,
- R => rst_i
- );
-\s_txdat_reg[35]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[35]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[35]\,
- R => rst_i
- );
-\s_txdat_reg[36]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[36]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[36]\,
- R => rst_i
- );
-\s_txdat_reg[37]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[37]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[37]\,
- R => rst_i
- );
-\s_txdat_reg[38]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[38]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[38]\,
- R => rst_i
- );
-\s_txdat_reg[39]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[39]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[39]\,
- R => rst_i
- );
-\s_txdat_reg[40]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[40]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[40]\,
- R => rst_i
- );
-\s_txdat_reg[41]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[41]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[41]\,
- R => rst_i
- );
-\s_txdat_reg[42]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[42]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[42]\,
- R => rst_i
- );
-\s_txdat_reg[43]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[43]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[43]\,
- R => rst_i
- );
-\s_txdat_reg[44]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[44]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[44]\,
- R => rst_i
- );
-\s_txdat_reg[45]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[45]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[45]\,
- R => rst_i
- );
-\s_txdat_reg[46]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[46]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[46]\,
- R => rst_i
- );
-\s_txdat_reg[47]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[47]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[47]\,
- R => rst_i
- );
-\s_txdat_reg[48]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[48]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[48]\,
- R => rst_i
- );
-\s_txdat_reg[49]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[49]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[49]\,
- R => rst_i
- );
-\s_txdat_reg[4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[4]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[4]\,
- R => rst_i
- );
-\s_txdat_reg[50]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[50]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[50]\,
- R => rst_i
- );
-\s_txdat_reg[51]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[51]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[51]\,
- R => rst_i
- );
-\s_txdat_reg[52]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[52]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[52]\,
- R => rst_i
- );
-\s_txdat_reg[53]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[53]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[53]\,
- R => rst_i
- );
-\s_txdat_reg[54]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[54]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[54]\,
- R => rst_i
- );
-\s_txdat_reg[55]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[55]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[55]\,
- R => rst_i
- );
-\s_txdat_reg[56]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[56]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[56]\,
- R => rst_i
- );
-\s_txdat_reg[57]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[57]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[57]\,
- R => rst_i
- );
-\s_txdat_reg[58]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[58]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[58]\,
- R => rst_i
- );
-\s_txdat_reg[59]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[59]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[59]\,
- R => rst_i
- );
-\s_txdat_reg[5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[5]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[5]\,
- R => rst_i
- );
-\s_txdat_reg[60]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[60]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[60]\,
- R => rst_i
- );
-\s_txdat_reg[61]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[61]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[61]\,
- R => rst_i
- );
-\s_txdat_reg[62]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[62]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[62]\,
- R => rst_i
- );
-\s_txdat_reg[63]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[63]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[63]\,
- R => rst_i
- );
-\s_txdat_reg[64]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[64]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[64]\,
- R => rst_i
- );
-\s_txdat_reg[65]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[65]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[65]\,
- R => rst_i
- );
-\s_txdat_reg[66]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[66]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[66]\,
- R => rst_i
- );
-\s_txdat_reg[67]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[67]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[67]\,
- R => rst_i
- );
-\s_txdat_reg[68]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[68]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[68]\,
- R => rst_i
- );
-\s_txdat_reg[69]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[69]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[69]\,
- R => rst_i
- );
-\s_txdat_reg[6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[6]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[6]\,
- R => rst_i
- );
-\s_txdat_reg[70]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[70]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[70]\,
- R => rst_i
- );
-\s_txdat_reg[71]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[71]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[71]\,
- R => rst_i
- );
-\s_txdat_reg[72]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[72]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[72]\,
- R => rst_i
- );
-\s_txdat_reg[73]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[73]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[73]\,
- R => rst_i
- );
-\s_txdat_reg[74]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[74]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[74]\,
- R => rst_i
- );
-\s_txdat_reg[75]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[75]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[75]\,
- R => rst_i
- );
-\s_txdat_reg[76]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[76]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[76]\,
- R => rst_i
- );
-\s_txdat_reg[77]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[77]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[77]\,
- R => rst_i
- );
-\s_txdat_reg[78]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[78]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[78]\,
- R => rst_i
- );
-\s_txdat_reg[79]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[79]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[79]\,
- R => rst_i
- );
-\s_txdat_reg[7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[7]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[7]\,
- R => rst_i
- );
-\s_txdat_reg[80]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[80]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[80]\,
- R => rst_i
- );
-\s_txdat_reg[81]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[81]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[81]\,
- R => rst_i
- );
-\s_txdat_reg[82]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[82]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[82]\,
- R => rst_i
- );
-\s_txdat_reg[83]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[83]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[83]\,
- R => rst_i
- );
-\s_txdat_reg[84]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[84]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[84]\,
- R => rst_i
- );
-\s_txdat_reg[85]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[85]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[85]\,
- R => rst_i
- );
-\s_txdat_reg[86]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[86]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[86]\,
- R => rst_i
- );
-\s_txdat_reg[87]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[87]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[87]\,
- R => rst_i
- );
-\s_txdat_reg[88]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[88]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[88]\,
- R => rst_i
- );
-\s_txdat_reg[89]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[89]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[89]\,
- R => rst_i
- );
-\s_txdat_reg[8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[8]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[8]\,
- R => rst_i
- );
-\s_txdat_reg[90]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[90]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[90]\,
- R => rst_i
- );
-\s_txdat_reg[91]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[91]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[91]\,
- R => rst_i
- );
-\s_txdat_reg[92]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[92]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[92]\,
- R => rst_i
- );
-\s_txdat_reg[93]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[93]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[93]\,
- R => rst_i
- );
-\s_txdat_reg[94]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[94]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[94]\,
- R => rst_i
- );
-\s_txdat_reg[95]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[95]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[95]\,
- R => rst_i
- );
-\s_txdat_reg[96]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[96]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[96]\,
- R => rst_i
- );
-\s_txdat_reg[97]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[97]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[97]\,
- R => rst_i
- );
-\s_txdat_reg[98]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[98]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[98]\,
- R => rst_i
- );
-\s_txdat_reg[99]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[99]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[99]\,
- R => rst_i
- );
-\s_txdat_reg[9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[9]_i_1__0_n_0\,
- Q => \s_txdat_reg_n_0_[9]\,
- R => rst_i
- );
-\v_ch_address[0]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"38"
- )
- port map (
- I0 => \s_state_reg[0]_0\,
- I1 => v_ch_address,
- I2 => ch_address(0),
- O => \v_ch_address_reg[0]\
- );
-\v_ch_address[1]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4F80"
- )
- port map (
- I0 => ch_address(0),
- I1 => \s_state_reg[0]_0\,
- I2 => v_ch_address,
- I3 => ch_address(1),
- O => \v_ch_address_reg[1]\
- );
-\v_ch_address[1]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"CA000A000A000A00"
- )
- port map (
- I0 => \data_rw_o_reg[79][1]\,
- I1 => \v_ch_address_reg[0]_0\,
- I2 => \s_state_reg[1]_0\,
- I3 => s00_axi_aresetn,
- I4 => s_done,
- I5 => \s_state_reg[0]_0\,
- O => v_ch_address
- );
-\v_ch_address[1]_i_4__0\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_state(0),
- I1 => s_state(1),
- O => s_done
- );
-\v_cnt[0]_i_1__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0026"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => s_state(0),
- I3 => \v_cnt_reg_n_0_[0]\,
- O => \v_cnt[0]_i_1__0_n_0\
- );
-\v_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"00262600"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => s_state(0),
- I3 => \v_cnt_reg_n_0_[1]\,
- I4 => \v_cnt_reg_n_0_[0]\,
- O => \v_cnt[1]_i_1__0_n_0\
- );
-\v_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0026260026002600"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => s_state(0),
- I3 => \v_cnt_reg_n_0_[2]\,
- I4 => \v_cnt_reg_n_0_[0]\,
- I5 => \v_cnt_reg_n_0_[1]\,
- O => \v_cnt[2]_i_1__0_n_0\
- );
-\v_cnt[3]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"28888888"
- )
- port map (
- I0 => \v_cnt[6]_i_4__0_n_0\,
- I1 => \v_cnt_reg_n_0_[3]\,
- I2 => \v_cnt_reg_n_0_[1]\,
- I3 => \v_cnt_reg_n_0_[0]\,
- I4 => \v_cnt_reg_n_0_[2]\,
- O => \v_cnt[3]_i_1__0_n_0\
- );
-\v_cnt[4]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"2888888888888888"
- )
- port map (
- I0 => \v_cnt[6]_i_4__0_n_0\,
- I1 => \v_cnt_reg_n_0_[4]\,
- I2 => \v_cnt_reg_n_0_[2]\,
- I3 => \v_cnt_reg_n_0_[0]\,
- I4 => \v_cnt_reg_n_0_[1]\,
- I5 => \v_cnt_reg_n_0_[3]\,
- O => \v_cnt[4]_i_1__0_n_0\
- );
-\v_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88882888"
- )
- port map (
- I0 => \v_cnt[6]_i_4__0_n_0\,
- I1 => \v_cnt_reg_n_0_[5]\,
- I2 => \v_cnt_reg_n_0_[4]\,
- I3 => \v_cnt_reg_n_0_[3]\,
- I4 => \v_cnt[6]_i_5__0_n_0\,
- O => \v_cnt[5]_i_1__0_n_0\
- );
-\v_cnt[6]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"EEEEEEEEEEEEEFEE"
- )
- port map (
- I0 => \v_cnt[6]_i_3__0_n_0\,
- I1 => s_rxdat_0,
- I2 => s_state(0),
- I3 => s_start_reg,
- I4 => s_state(2),
- I5 => s_state(1),
- O => v_cnt
- );
-\v_cnt[6]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8888888828888888"
- )
- port map (
- I0 => \v_cnt[6]_i_4__0_n_0\,
- I1 => \v_cnt_reg_n_0_[6]\,
- I2 => \v_cnt_reg_n_0_[5]\,
- I3 => \v_cnt_reg_n_0_[3]\,
- I4 => \v_cnt_reg_n_0_[4]\,
- I5 => \v_cnt[6]_i_5__0_n_0\,
- O => \v_cnt[6]_i_2__0_n_0\
- );
-\v_cnt[6]_i_3__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000C000010101010"
- )
- port map (
- I0 => \FSM_sequential_s_state[2]_i_4__0_n_0\,
- I1 => s_state(1),
- I2 => s_state(2),
- I3 => \s_txdat[119]_i_4__0_n_0\,
- I4 => \s_txdat[119]_i_3__0_n_0\,
- I5 => s_state(0),
- O => \v_cnt[6]_i_3__0_n_0\
- );
-\v_cnt[6]_i_4__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"34"
- )
- port map (
- I0 => s_state(0),
- I1 => s_state(1),
- I2 => s_state(2),
- O => \v_cnt[6]_i_4__0_n_0\
- );
-\v_cnt[6]_i_5__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"7F"
- )
- port map (
- I0 => \v_cnt_reg_n_0_[1]\,
- I1 => \v_cnt_reg_n_0_[0]\,
- I2 => \v_cnt_reg_n_0_[2]\,
- O => \v_cnt[6]_i_5__0_n_0\
- );
-\v_cnt_reg[0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => v_cnt,
- D => \v_cnt[0]_i_1__0_n_0\,
- Q => \v_cnt_reg_n_0_[0]\,
- R => rst_i
- );
-\v_cnt_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => v_cnt,
- D => \v_cnt[1]_i_1__0_n_0\,
- Q => \v_cnt_reg_n_0_[1]\,
- R => rst_i
- );
-\v_cnt_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => v_cnt,
- D => \v_cnt[2]_i_1__0_n_0\,
- Q => \v_cnt_reg_n_0_[2]\,
- R => rst_i
- );
-\v_cnt_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => v_cnt,
- D => \v_cnt[3]_i_1__0_n_0\,
- Q => \v_cnt_reg_n_0_[3]\,
- R => rst_i
- );
-\v_cnt_reg[4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => v_cnt,
- D => \v_cnt[4]_i_1__0_n_0\,
- Q => \v_cnt_reg_n_0_[4]\,
- R => rst_i
- );
-\v_cnt_reg[5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => v_cnt,
- D => \v_cnt[5]_i_1__0_n_0\,
- Q => \v_cnt_reg_n_0_[5]\,
- R => rst_i
- );
-\v_cnt_reg[6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => v_cnt,
- D => \v_cnt[6]_i_2__0_n_0\,
- Q => \v_cnt_reg_n_0_[6]\,
- R => rst_i
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_spi_transceiver_130 is
- port (
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- \v_ch_address_reg[0]\ : out STD_LOGIC;
- \v_ch_address_reg[1]\ : out STD_LOGIC;
- \s_state_reg[0]\ : out STD_LOGIC;
- \s_state_reg[1]\ : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 0 to 0 );
- \dac_ch_o_reg[0][31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
- s_spi_mosi : out STD_LOGIC;
- s_spi_cs_n : out STD_LOGIC;
- \data_rw_o_reg[11][1]\ : in STD_LOGIC;
- \v_ch_address_reg[0]_0\ : in STD_LOGIC;
- \s_state_reg[1]_0\ : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- \s_state_reg[0]_0\ : in STD_LOGIC;
- \[0].[3].s_reqs_reg[3][changed]\ : in STD_LOGIC;
- \[0].[2].s_reqs_reg[2][changed]\ : in STD_LOGIC;
- ch_address : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \[0].[2].s_reqs_reg[2][changed]_0\ : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aclk : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s_start_reg : in STD_LOGIC;
- \s_tx_data_reg[113]\ : in STD_LOGIC_VECTOR ( 61 downto 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_spi_transceiver_130 : entity is "spi_transceiver";
-end system_design_fasec_hwtest_0_0_spi_transceiver_130;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_spi_transceiver_130 is
- signal \FSM_sequential_s_state[0]_i_1_n_0\ : STD_LOGIC;
- signal \FSM_sequential_s_state[0]_i_2_n_0\ : STD_LOGIC;
- signal \FSM_sequential_s_state[0]_i_3_n_0\ : STD_LOGIC;
- signal \FSM_sequential_s_state[1]_i_1_n_0\ : STD_LOGIC;
- signal \FSM_sequential_s_state[2]_i_1_n_0\ : STD_LOGIC;
- signal \FSM_sequential_s_state[2]_i_2_n_0\ : STD_LOGIC;
- signal \FSM_sequential_s_state[2]_i_3_n_0\ : STD_LOGIC;
- signal \FSM_sequential_s_state[2]_i_4_n_0\ : STD_LOGIC;
- signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal p_0_in : STD_LOGIC;
- signal \rx_data_o[31]_i_1_n_0\ : STD_LOGIC;
- signal s_counter : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal \s_counter[0]_i_1_n_0\ : STD_LOGIC;
- signal \s_counter[1]_i_1_n_0\ : STD_LOGIC;
- signal \s_counter[2]_i_1_n_0\ : STD_LOGIC;
- signal s_done : STD_LOGIC;
- signal s_rxdat : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal s_rxdat_0 : STD_LOGIC;
- signal s_state : STD_LOGIC_VECTOR ( 2 downto 0 );
- attribute RTL_KEEP : string;
- attribute RTL_KEEP of s_state : signal is "yes";
- signal \s_state[0]_i_2_n_0\ : STD_LOGIC;
- signal \s_state[1]_i_4_n_0\ : STD_LOGIC;
- signal s_txdat : STD_LOGIC;
- signal \s_txdat[100]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[101]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[102]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[103]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[104]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[105]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[106]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[107]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[108]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[109]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[10]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[110]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[111]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[112]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[113]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[114]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[115]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[116]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[117]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[118]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[119]_i_2_n_0\ : STD_LOGIC;
- signal \s_txdat[119]_i_3_n_0\ : STD_LOGIC;
- signal \s_txdat[119]_i_4_n_0\ : STD_LOGIC;
- signal \s_txdat[119]_i_5_n_0\ : STD_LOGIC;
- signal \s_txdat[11]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[12]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[13]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[14]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[15]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[16]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[17]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[18]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[19]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[20]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[21]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[22]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[23]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[24]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[25]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[26]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[27]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[28]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[29]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[30]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[31]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[32]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[33]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[34]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[35]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[36]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[37]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[38]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[39]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[40]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[41]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[42]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[43]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[44]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[45]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[46]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[47]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[48]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[49]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[4]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[50]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[51]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[52]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[53]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[54]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[55]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[56]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[57]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[58]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[59]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[5]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[60]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[61]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[62]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[63]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[64]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[65]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[66]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[67]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[68]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[69]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[6]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[70]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[71]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[72]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[73]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[74]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[75]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[76]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[77]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[78]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[79]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[7]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[80]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[81]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[82]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[83]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[84]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[85]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[86]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[87]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[88]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[89]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[8]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[90]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[91]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[92]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[93]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[94]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[95]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[96]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[97]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[98]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[99]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat[9]_i_1_n_0\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[100]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[101]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[102]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[103]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[104]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[105]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[106]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[107]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[108]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[109]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[10]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[110]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[111]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[112]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[113]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[114]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[115]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[116]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[117]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[118]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[11]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[12]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[13]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[14]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[15]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[16]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[17]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[18]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[19]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[20]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[21]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[22]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[23]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[24]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[25]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[26]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[27]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[28]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[29]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[30]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[31]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[32]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[33]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[34]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[35]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[36]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[37]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[38]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[39]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[40]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[41]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[42]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[43]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[44]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[45]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[46]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[47]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[48]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[49]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[4]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[50]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[51]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[52]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[53]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[54]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[55]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[56]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[57]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[58]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[59]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[5]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[60]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[61]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[62]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[63]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[64]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[65]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[66]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[67]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[68]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[69]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[6]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[70]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[71]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[72]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[73]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[74]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[75]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[76]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[77]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[78]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[79]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[7]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[80]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[81]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[82]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[83]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[84]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[85]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[86]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[87]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[88]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[89]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[8]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[90]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[91]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[92]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[93]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[94]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[95]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[96]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[97]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[98]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[99]\ : STD_LOGIC;
- signal \s_txdat_reg_n_0_[9]\ : STD_LOGIC;
- signal v_ch_address : STD_LOGIC;
- signal v_cnt : STD_LOGIC;
- signal \v_cnt[0]_i_1_n_0\ : STD_LOGIC;
- signal \v_cnt[1]_i_1_n_0\ : STD_LOGIC;
- signal \v_cnt[2]_i_1_n_0\ : STD_LOGIC;
- signal \v_cnt[3]_i_1_n_0\ : STD_LOGIC;
- signal \v_cnt[4]_i_1_n_0\ : STD_LOGIC;
- signal \v_cnt[5]_i_1_n_0\ : STD_LOGIC;
- signal \v_cnt[6]_i_2_n_0\ : STD_LOGIC;
- signal \v_cnt[6]_i_3_n_0\ : STD_LOGIC;
- signal \v_cnt[6]_i_4_n_0\ : STD_LOGIC;
- signal \v_cnt[6]_i_5_n_0\ : STD_LOGIC;
- signal \v_cnt_reg_n_0_[0]\ : STD_LOGIC;
- signal \v_cnt_reg_n_0_[1]\ : STD_LOGIC;
- signal \v_cnt_reg_n_0_[2]\ : STD_LOGIC;
- signal \v_cnt_reg_n_0_[3]\ : STD_LOGIC;
- signal \v_cnt_reg_n_0_[4]\ : STD_LOGIC;
- signal \v_cnt_reg_n_0_[5]\ : STD_LOGIC;
- signal \v_cnt_reg_n_0_[6]\ : STD_LOGIC;
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \FSM_sequential_s_state[2]_i_4\ : label is "soft_lutpair37";
- attribute KEEP : string;
- attribute KEEP of \FSM_sequential_s_state_reg[0]\ : label is "yes";
- attribute KEEP of \FSM_sequential_s_state_reg[1]\ : label is "yes";
- attribute KEEP of \FSM_sequential_s_state_reg[2]\ : label is "yes";
- attribute SOFT_HLUTNM of \s_counter[0]_i_1\ : label is "soft_lutpair41";
- attribute SOFT_HLUTNM of \s_counter[1]_i_1\ : label is "soft_lutpair41";
- attribute SOFT_HLUTNM of \s_counter[2]_i_1\ : label is "soft_lutpair40";
- attribute SOFT_HLUTNM of \s_txdat[119]_i_3\ : label is "soft_lutpair40";
- attribute SOFT_HLUTNM of \s_txdat[119]_i_4\ : label is "soft_lutpair38";
- attribute SOFT_HLUTNM of \s_txdat[119]_i_5\ : label is "soft_lutpair37";
- attribute SOFT_HLUTNM of \v_ch_address[0]_i_1\ : label is "soft_lutpair39";
- attribute SOFT_HLUTNM of \v_ch_address[1]_i_1\ : label is "soft_lutpair39";
- attribute SOFT_HLUTNM of \v_cnt[6]_i_5\ : label is "soft_lutpair38";
-begin
- Q(0) <= \^q\(0);
-\FSM_sequential_s_state[0]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => \FSM_sequential_s_state[0]_i_2_n_0\,
- I1 => \FSM_sequential_s_state[2]_i_2_n_0\,
- I2 => s_state(0),
- O => \FSM_sequential_s_state[0]_i_1_n_0\
- );
-\FSM_sequential_s_state[0]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFF00FFFFFF00"
- )
- port map (
- I0 => \v_cnt_reg_n_0_[0]\,
- I1 => \v_cnt_reg_n_0_[1]\,
- I2 => \v_cnt_reg_n_0_[2]\,
- I3 => \FSM_sequential_s_state[0]_i_3_n_0\,
- I4 => s_state(1),
- I5 => \v_cnt_reg_n_0_[3]\,
- O => \FSM_sequential_s_state[0]_i_2_n_0\
- );
-\FSM_sequential_s_state[0]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"77C3FFC3FFC3FFC3"
- )
- port map (
- I0 => \v_cnt_reg_n_0_[4]\,
- I1 => s_state(0),
- I2 => s_state(2),
- I3 => s_state(1),
- I4 => \v_cnt_reg_n_0_[6]\,
- I5 => \v_cnt_reg_n_0_[5]\,
- O => \FSM_sequential_s_state[0]_i_3_n_0\
- );
-\FSM_sequential_s_state[1]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"6F60"
- )
- port map (
- I0 => s_state(0),
- I1 => s_state(1),
- I2 => \FSM_sequential_s_state[2]_i_2_n_0\,
- I3 => s_state(1),
- O => \FSM_sequential_s_state[1]_i_1_n_0\
- );
-\FSM_sequential_s_state[2]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"8F80"
- )
- port map (
- I0 => s_state(1),
- I1 => s_state(0),
- I2 => \FSM_sequential_s_state[2]_i_2_n_0\,
- I3 => s_state(2),
- O => \FSM_sequential_s_state[2]_i_1_n_0\
- );
-\FSM_sequential_s_state[2]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"ABEEAAAAAAEEAAAA"
- )
- port map (
- I0 => \FSM_sequential_s_state[2]_i_3_n_0\,
- I1 => s_state(0),
- I2 => s_state(1),
- I3 => s_state(2),
- I4 => \s_txdat[119]_i_3_n_0\,
- I5 => \FSM_sequential_s_state[2]_i_4_n_0\,
- O => \FSM_sequential_s_state[2]_i_2_n_0\
- );
-\FSM_sequential_s_state[2]_i_3\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF0010"
- )
- port map (
- I0 => s_state(1),
- I1 => s_state(2),
- I2 => s_start_reg,
- I3 => s_state(0),
- I4 => s_rxdat_0,
- O => \FSM_sequential_s_state[2]_i_3_n_0\
- );
-\FSM_sequential_s_state[2]_i_4\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFE"
- )
- port map (
- I0 => \v_cnt_reg_n_0_[2]\,
- I1 => \v_cnt_reg_n_0_[5]\,
- I2 => \v_cnt_reg_n_0_[6]\,
- I3 => \v_cnt_reg_n_0_[4]\,
- I4 => \v_cnt_reg_n_0_[3]\,
- O => \FSM_sequential_s_state[2]_i_4_n_0\
- );
-\FSM_sequential_s_state_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \FSM_sequential_s_state[0]_i_1_n_0\,
- Q => s_state(0),
- R => SR(0)
- );
-\FSM_sequential_s_state_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \FSM_sequential_s_state[1]_i_1_n_0\,
- Q => s_state(1),
- R => SR(0)
- );
-\FSM_sequential_s_state_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \FSM_sequential_s_state[2]_i_1_n_0\,
- Q => s_state(2),
- R => SR(0)
- );
-\dac_ch_o[0][31]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000000002000000"
- )
- port map (
- I0 => \s_state_reg[1]_0\,
- I1 => s_state(1),
- I2 => s_state(0),
- I3 => s00_axi_aresetn,
- I4 => \s_state_reg[0]_0\,
- I5 => \v_ch_address_reg[0]_0\,
- O => E(0)
- );
-\gen_spi.cmp_spi_cs_n_iobuf_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"07"
- )
- port map (
- I0 => s_state(0),
- I1 => s_state(2),
- I2 => s_state(1),
- O => s_spi_cs_n
- );
-\gen_spi.cmp_spi_mosi_iobuf_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"2B3B"
- )
- port map (
- I0 => p_0_in,
- I1 => s_state(1),
- I2 => s_state(2),
- I3 => s_state(0),
- O => s_spi_mosi
- );
-\rx_data_o[31]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0002"
- )
- port map (
- I0 => s00_axi_aresetn,
- I1 => s_state(0),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \rx_data_o[31]_i_1_n_0\
- );
-\rx_data_o_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(0),
- Q => \dac_ch_o_reg[0][31]\(0),
- R => '0'
- );
-\rx_data_o_reg[10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(10),
- Q => \dac_ch_o_reg[0][31]\(10),
- R => '0'
- );
-\rx_data_o_reg[11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(11),
- Q => \dac_ch_o_reg[0][31]\(11),
- R => '0'
- );
-\rx_data_o_reg[12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(12),
- Q => \dac_ch_o_reg[0][31]\(12),
- R => '0'
- );
-\rx_data_o_reg[13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(13),
- Q => \dac_ch_o_reg[0][31]\(13),
- R => '0'
- );
-\rx_data_o_reg[14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(14),
- Q => \dac_ch_o_reg[0][31]\(14),
- R => '0'
- );
-\rx_data_o_reg[15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(15),
- Q => \dac_ch_o_reg[0][31]\(15),
- R => '0'
- );
-\rx_data_o_reg[16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(16),
- Q => \dac_ch_o_reg[0][31]\(16),
- R => '0'
- );
-\rx_data_o_reg[17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(17),
- Q => \dac_ch_o_reg[0][31]\(17),
- R => '0'
- );
-\rx_data_o_reg[18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(18),
- Q => \dac_ch_o_reg[0][31]\(18),
- R => '0'
- );
-\rx_data_o_reg[19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(19),
- Q => \dac_ch_o_reg[0][31]\(19),
- R => '0'
- );
-\rx_data_o_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(1),
- Q => \dac_ch_o_reg[0][31]\(1),
- R => '0'
- );
-\rx_data_o_reg[20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(20),
- Q => \dac_ch_o_reg[0][31]\(20),
- R => '0'
- );
-\rx_data_o_reg[21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(21),
- Q => \dac_ch_o_reg[0][31]\(21),
- R => '0'
- );
-\rx_data_o_reg[22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(22),
- Q => \dac_ch_o_reg[0][31]\(22),
- R => '0'
- );
-\rx_data_o_reg[23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(23),
- Q => \dac_ch_o_reg[0][31]\(23),
- R => '0'
- );
-\rx_data_o_reg[24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(24),
- Q => \dac_ch_o_reg[0][31]\(24),
- R => '0'
- );
-\rx_data_o_reg[25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(25),
- Q => \dac_ch_o_reg[0][31]\(25),
- R => '0'
- );
-\rx_data_o_reg[26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(26),
- Q => \dac_ch_o_reg[0][31]\(26),
- R => '0'
- );
-\rx_data_o_reg[27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(27),
- Q => \dac_ch_o_reg[0][31]\(27),
- R => '0'
- );
-\rx_data_o_reg[28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(28),
- Q => \dac_ch_o_reg[0][31]\(28),
- R => '0'
- );
-\rx_data_o_reg[29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(29),
- Q => \dac_ch_o_reg[0][31]\(29),
- R => '0'
- );
-\rx_data_o_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(2),
- Q => \dac_ch_o_reg[0][31]\(2),
- R => '0'
- );
-\rx_data_o_reg[30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(30),
- Q => \dac_ch_o_reg[0][31]\(30),
- R => '0'
- );
-\rx_data_o_reg[31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(31),
- Q => \dac_ch_o_reg[0][31]\(31),
- R => '0'
- );
-\rx_data_o_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(3),
- Q => \dac_ch_o_reg[0][31]\(3),
- R => '0'
- );
-\rx_data_o_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(4),
- Q => \dac_ch_o_reg[0][31]\(4),
- R => '0'
- );
-\rx_data_o_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(5),
- Q => \dac_ch_o_reg[0][31]\(5),
- R => '0'
- );
-\rx_data_o_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(6),
- Q => \dac_ch_o_reg[0][31]\(6),
- R => '0'
- );
-\rx_data_o_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(7),
- Q => \dac_ch_o_reg[0][31]\(7),
- R => '0'
- );
-\rx_data_o_reg[8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(8),
- Q => \dac_ch_o_reg[0][31]\(8),
- R => '0'
- );
-\rx_data_o_reg[9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \rx_data_o[31]_i_1_n_0\,
- D => s_rxdat(9),
- Q => \dac_ch_o_reg[0][31]\(9),
- R => '0'
- );
-\s_counter[0]_i_1\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_counter(0),
- O => \s_counter[0]_i_1_n_0\
- );
-\s_counter[1]_i_1\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"6"
- )
- port map (
- I0 => s_counter(0),
- I1 => s_counter(1),
- O => \s_counter[1]_i_1_n_0\
- );
-\s_counter[2]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"6A"
- )
- port map (
- I0 => \^q\(0),
- I1 => s_counter(0),
- I2 => s_counter(1),
- O => \s_counter[2]_i_1_n_0\
- );
-\s_counter_reg[0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_counter[0]_i_1_n_0\,
- Q => s_counter(0),
- R => SR(0)
- );
-\s_counter_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_counter[1]_i_1_n_0\,
- Q => s_counter(1),
- R => SR(0)
- );
-\s_counter_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_counter[2]_i_1_n_0\,
- Q => \^q\(0),
- R => SR(0)
- );
-\s_rxdat[31]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"2400000000000000"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => s_state(0),
- I3 => s_counter(0),
- I4 => s_counter(1),
- I5 => \^q\(0),
- O => s_rxdat_0
- );
-\s_rxdat_reg[0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => D(0),
- Q => s_rxdat(0),
- R => SR(0)
- );
-\s_rxdat_reg[10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(9),
- Q => s_rxdat(10),
- R => SR(0)
- );
-\s_rxdat_reg[11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(10),
- Q => s_rxdat(11),
- R => SR(0)
- );
-\s_rxdat_reg[12]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(11),
- Q => s_rxdat(12),
- R => SR(0)
- );
-\s_rxdat_reg[13]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(12),
- Q => s_rxdat(13),
- R => SR(0)
- );
-\s_rxdat_reg[14]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(13),
- Q => s_rxdat(14),
- R => SR(0)
- );
-\s_rxdat_reg[15]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(14),
- Q => s_rxdat(15),
- R => SR(0)
- );
-\s_rxdat_reg[16]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(15),
- Q => s_rxdat(16),
- R => SR(0)
- );
-\s_rxdat_reg[17]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(16),
- Q => s_rxdat(17),
- R => SR(0)
- );
-\s_rxdat_reg[18]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(17),
- Q => s_rxdat(18),
- R => SR(0)
- );
-\s_rxdat_reg[19]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(18),
- Q => s_rxdat(19),
- R => SR(0)
- );
-\s_rxdat_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(0),
- Q => s_rxdat(1),
- R => SR(0)
- );
-\s_rxdat_reg[20]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(19),
- Q => s_rxdat(20),
- R => SR(0)
- );
-\s_rxdat_reg[21]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(20),
- Q => s_rxdat(21),
- R => SR(0)
- );
-\s_rxdat_reg[22]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(21),
- Q => s_rxdat(22),
- R => SR(0)
- );
-\s_rxdat_reg[23]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(22),
- Q => s_rxdat(23),
- R => SR(0)
- );
-\s_rxdat_reg[24]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(23),
- Q => s_rxdat(24),
- R => SR(0)
- );
-\s_rxdat_reg[25]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(24),
- Q => s_rxdat(25),
- R => SR(0)
- );
-\s_rxdat_reg[26]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(25),
- Q => s_rxdat(26),
- R => SR(0)
- );
-\s_rxdat_reg[27]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(26),
- Q => s_rxdat(27),
- R => SR(0)
- );
-\s_rxdat_reg[28]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(27),
- Q => s_rxdat(28),
- R => SR(0)
- );
-\s_rxdat_reg[29]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(28),
- Q => s_rxdat(29),
- R => SR(0)
- );
-\s_rxdat_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(1),
- Q => s_rxdat(2),
- R => SR(0)
- );
-\s_rxdat_reg[30]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(29),
- Q => s_rxdat(30),
- R => SR(0)
- );
-\s_rxdat_reg[31]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(30),
- Q => s_rxdat(31),
- R => SR(0)
- );
-\s_rxdat_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(2),
- Q => s_rxdat(3),
- R => SR(0)
- );
-\s_rxdat_reg[4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(3),
- Q => s_rxdat(4),
- R => SR(0)
- );
-\s_rxdat_reg[5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(4),
- Q => s_rxdat(5),
- R => SR(0)
- );
-\s_rxdat_reg[6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(5),
- Q => s_rxdat(6),
- R => SR(0)
- );
-\s_rxdat_reg[7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(6),
- Q => s_rxdat(7),
- R => SR(0)
- );
-\s_rxdat_reg[8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(7),
- Q => s_rxdat(8),
- R => SR(0)
- );
-\s_rxdat_reg[9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_rxdat_0,
- D => s_rxdat(8),
- Q => s_rxdat(9),
- R => SR(0)
- );
-\s_state[0]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"2AFFFF00"
- )
- port map (
- I0 => \s_state_reg[1]_0\,
- I1 => ch_address(0),
- I2 => ch_address(1),
- I3 => \s_state[0]_i_2_n_0\,
- I4 => \s_state_reg[0]_0\,
- O => \s_state_reg[0]\
- );
-\s_state[0]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FAFFAFFAFABFAFBA"
- )
- port map (
- I0 => \[0].[3].s_reqs_reg[3][changed]\,
- I1 => \v_ch_address_reg[0]_0\,
- I2 => \s_state_reg[0]_0\,
- I3 => \s_state_reg[1]_0\,
- I4 => s_done,
- I5 => \[0].[2].s_reqs_reg[2][changed]\,
- O => \s_state[0]_i_2_n_0\
- );
-\s_state[1]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FDFFFCF0"
- )
- port map (
- I0 => \s_state_reg[0]_0\,
- I1 => \[0].[2].s_reqs_reg[2][changed]_0\,
- I2 => \[0].[3].s_reqs_reg[3][changed]\,
- I3 => \s_state[1]_i_4_n_0\,
- I4 => \s_state_reg[1]_0\,
- O => \s_state_reg[1]\
- );
-\s_state[1]_i_4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"CF3CCA3CCA3CCA3C"
- )
- port map (
- I0 => \[0].[2].s_reqs_reg[2][changed]\,
- I1 => s_done,
- I2 => \s_state_reg[1]_0\,
- I3 => \s_state_reg[0]_0\,
- I4 => ch_address(1),
- I5 => ch_address(0),
- O => \s_state[1]_i_4_n_0\
- );
-\s_txdat[100]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[99]\,
- I1 => \s_tx_data_reg[113]\(48),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[100]_i_1_n_0\
- );
-\s_txdat[101]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[100]\,
- I1 => \s_tx_data_reg[113]\(49),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[101]_i_1_n_0\
- );
-\s_txdat[102]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[101]\,
- I1 => \s_tx_data_reg[113]\(50),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[102]_i_1_n_0\
- );
-\s_txdat[103]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[102]\,
- I1 => \s_tx_data_reg[113]\(51),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[103]_i_1_n_0\
- );
-\s_txdat[104]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[103]\,
- I1 => \s_tx_data_reg[113]\(52),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[104]_i_1_n_0\
- );
-\s_txdat[105]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[104]\,
- I1 => \s_tx_data_reg[113]\(53),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[105]_i_1_n_0\
- );
-\s_txdat[106]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[105]\,
- I1 => \s_tx_data_reg[113]\(54),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[106]_i_1_n_0\
- );
-\s_txdat[107]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[106]\,
- I1 => \s_tx_data_reg[113]\(55),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[107]_i_1_n_0\
- );
-\s_txdat[108]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[107]\,
- I1 => \s_tx_data_reg[113]\(56),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[108]_i_1_n_0\
- );
-\s_txdat[109]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[108]\,
- I1 => \s_tx_data_reg[113]\(57),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[109]_i_1_n_0\
- );
-\s_txdat[10]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[9]\,
- I1 => \s_tx_data_reg[113]\(6),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[10]_i_1_n_0\
- );
-\s_txdat[110]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[109]\,
- I1 => \s_tx_data_reg[113]\(58),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[110]_i_1_n_0\
- );
-\s_txdat[111]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[110]\,
- I1 => \s_tx_data_reg[113]\(59),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[111]_i_1_n_0\
- );
-\s_txdat[112]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[111]\,
- I1 => \s_tx_data_reg[113]\(60),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[112]_i_1_n_0\
- );
-\s_txdat[113]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[112]\,
- I1 => \s_tx_data_reg[113]\(61),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[113]_i_1_n_0\
- );
-\s_txdat[114]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"23"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[113]\,
- I1 => s_state(2),
- I2 => s_state(1),
- O => \s_txdat[114]_i_1_n_0\
- );
-\s_txdat[115]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[114]\,
- O => \s_txdat[115]_i_1_n_0\
- );
-\s_txdat[116]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[115]\,
- O => \s_txdat[116]_i_1_n_0\
- );
-\s_txdat[117]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[116]\,
- O => \s_txdat[117]_i_1_n_0\
- );
-\s_txdat[118]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[117]\,
- O => \s_txdat[118]_i_1_n_0\
- );
-\s_txdat[119]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"00800080000F0000"
- )
- port map (
- I0 => \s_txdat[119]_i_3_n_0\,
- I1 => \s_txdat[119]_i_4_n_0\,
- I2 => s_state(1),
- I3 => s_state(2),
- I4 => s_start_reg,
- I5 => s_state(0),
- O => s_txdat
- );
-\s_txdat[119]_i_2\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[118]\,
- O => \s_txdat[119]_i_2_n_0\
- );
-\s_txdat[119]_i_3\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"08"
- )
- port map (
- I0 => s_counter(1),
- I1 => s_counter(0),
- I2 => \^q\(0),
- O => \s_txdat[119]_i_3_n_0\
- );
-\s_txdat[119]_i_4\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFFFFFB"
- )
- port map (
- I0 => \v_cnt_reg_n_0_[2]\,
- I1 => \v_cnt_reg_n_0_[6]\,
- I2 => \v_cnt_reg_n_0_[0]\,
- I3 => \v_cnt_reg_n_0_[1]\,
- I4 => \s_txdat[119]_i_5_n_0\,
- O => \s_txdat[119]_i_4_n_0\
- );
-\s_txdat[119]_i_5\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"7F"
- )
- port map (
- I0 => \v_cnt_reg_n_0_[4]\,
- I1 => \v_cnt_reg_n_0_[3]\,
- I2 => \v_cnt_reg_n_0_[5]\,
- O => \s_txdat[119]_i_5_n_0\
- );
-\s_txdat[11]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[10]\,
- I1 => \s_tx_data_reg[113]\(7),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[11]_i_1_n_0\
- );
-\s_txdat[12]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[11]\,
- I1 => \s_tx_data_reg[113]\(8),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[12]_i_1_n_0\
- );
-\s_txdat[13]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[12]\,
- I1 => \s_tx_data_reg[113]\(9),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[13]_i_1_n_0\
- );
-\s_txdat[14]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[13]\,
- I1 => \s_tx_data_reg[113]\(10),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[14]_i_1_n_0\
- );
-\s_txdat[15]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[14]\,
- I1 => \s_tx_data_reg[113]\(11),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[15]_i_1_n_0\
- );
-\s_txdat[16]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[15]\,
- I1 => \s_tx_data_reg[113]\(60),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[16]_i_1_n_0\
- );
-\s_txdat[17]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[16]\,
- I1 => \s_tx_data_reg[113]\(61),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[17]_i_1_n_0\
- );
-\s_txdat[18]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"23"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[17]\,
- I1 => s_state(2),
- I2 => s_state(1),
- O => \s_txdat[18]_i_1_n_0\
- );
-\s_txdat[19]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[18]\,
- O => \s_txdat[19]_i_1_n_0\
- );
-\s_txdat[20]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[19]\,
- O => \s_txdat[20]_i_1_n_0\
- );
-\s_txdat[21]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[20]\,
- O => \s_txdat[21]_i_1_n_0\
- );
-\s_txdat[22]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[21]\,
- O => \s_txdat[22]_i_1_n_0\
- );
-\s_txdat[23]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[22]\,
- O => \s_txdat[23]_i_1_n_0\
- );
-\s_txdat[24]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[23]\,
- O => \s_txdat[24]_i_1_n_0\
- );
-\s_txdat[25]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[24]\,
- O => \s_txdat[25]_i_1_n_0\
- );
-\s_txdat[26]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[25]\,
- O => \s_txdat[26]_i_1_n_0\
- );
-\s_txdat[27]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[26]\,
- O => \s_txdat[27]_i_1_n_0\
- );
-\s_txdat[28]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[27]\,
- I1 => \s_tx_data_reg[113]\(12),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[28]_i_1_n_0\
- );
-\s_txdat[29]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[28]\,
- I1 => \s_tx_data_reg[113]\(13),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[29]_i_1_n_0\
- );
-\s_txdat[30]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[29]\,
- I1 => \s_tx_data_reg[113]\(14),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[30]_i_1_n_0\
- );
-\s_txdat[31]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[30]\,
- I1 => \s_tx_data_reg[113]\(15),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[31]_i_1_n_0\
- );
-\s_txdat[32]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[31]\,
- I1 => \s_tx_data_reg[113]\(16),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[32]_i_1_n_0\
- );
-\s_txdat[33]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[32]\,
- I1 => \s_tx_data_reg[113]\(17),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[33]_i_1_n_0\
- );
-\s_txdat[34]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[33]\,
- I1 => \s_tx_data_reg[113]\(18),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[34]_i_1_n_0\
- );
-\s_txdat[35]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[34]\,
- I1 => \s_tx_data_reg[113]\(19),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[35]_i_1_n_0\
- );
-\s_txdat[36]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[35]\,
- I1 => \s_tx_data_reg[113]\(20),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[36]_i_1_n_0\
- );
-\s_txdat[37]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[36]\,
- I1 => \s_tx_data_reg[113]\(21),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[37]_i_1_n_0\
- );
-\s_txdat[38]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[37]\,
- I1 => \s_tx_data_reg[113]\(22),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[38]_i_1_n_0\
- );
-\s_txdat[39]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[38]\,
- I1 => \s_tx_data_reg[113]\(23),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[39]_i_1_n_0\
- );
-\s_txdat[40]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[39]\,
- I1 => \s_tx_data_reg[113]\(60),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[40]_i_1_n_0\
- );
-\s_txdat[41]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[40]\,
- I1 => \s_tx_data_reg[113]\(61),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[41]_i_1_n_0\
- );
-\s_txdat[42]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"23"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[41]\,
- I1 => s_state(2),
- I2 => s_state(1),
- O => \s_txdat[42]_i_1_n_0\
- );
-\s_txdat[43]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[42]\,
- O => \s_txdat[43]_i_1_n_0\
- );
-\s_txdat[44]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[43]\,
- O => \s_txdat[44]_i_1_n_0\
- );
-\s_txdat[45]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[44]\,
- O => \s_txdat[45]_i_1_n_0\
- );
-\s_txdat[46]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[45]\,
- O => \s_txdat[46]_i_1_n_0\
- );
-\s_txdat[47]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[46]\,
- O => \s_txdat[47]_i_1_n_0\
- );
-\s_txdat[48]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[47]\,
- O => \s_txdat[48]_i_1_n_0\
- );
-\s_txdat[49]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[48]\,
- O => \s_txdat[49]_i_1_n_0\
- );
-\s_txdat[4]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"10"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_tx_data_reg[113]\(0),
- O => \s_txdat[4]_i_1_n_0\
- );
-\s_txdat[50]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[49]\,
- O => \s_txdat[50]_i_1_n_0\
- );
-\s_txdat[51]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[50]\,
- O => \s_txdat[51]_i_1_n_0\
- );
-\s_txdat[52]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[51]\,
- I1 => \s_tx_data_reg[113]\(24),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[52]_i_1_n_0\
- );
-\s_txdat[53]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[52]\,
- I1 => \s_tx_data_reg[113]\(25),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[53]_i_1_n_0\
- );
-\s_txdat[54]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[53]\,
- I1 => \s_tx_data_reg[113]\(26),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[54]_i_1_n_0\
- );
-\s_txdat[55]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[54]\,
- I1 => \s_tx_data_reg[113]\(27),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[55]_i_1_n_0\
- );
-\s_txdat[56]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[55]\,
- I1 => \s_tx_data_reg[113]\(28),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[56]_i_1_n_0\
- );
-\s_txdat[57]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[56]\,
- I1 => \s_tx_data_reg[113]\(29),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[57]_i_1_n_0\
- );
-\s_txdat[58]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[57]\,
- I1 => \s_tx_data_reg[113]\(30),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[58]_i_1_n_0\
- );
-\s_txdat[59]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[58]\,
- I1 => \s_tx_data_reg[113]\(31),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[59]_i_1_n_0\
- );
-\s_txdat[5]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[4]\,
- I1 => \s_tx_data_reg[113]\(1),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[5]_i_1_n_0\
- );
-\s_txdat[60]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[59]\,
- I1 => \s_tx_data_reg[113]\(32),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[60]_i_1_n_0\
- );
-\s_txdat[61]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[60]\,
- I1 => \s_tx_data_reg[113]\(33),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[61]_i_1_n_0\
- );
-\s_txdat[62]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[61]\,
- I1 => \s_tx_data_reg[113]\(34),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[62]_i_1_n_0\
- );
-\s_txdat[63]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[62]\,
- I1 => \s_tx_data_reg[113]\(35),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[63]_i_1_n_0\
- );
-\s_txdat[64]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[63]\,
- I1 => \s_tx_data_reg[113]\(60),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[64]_i_1_n_0\
- );
-\s_txdat[65]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[64]\,
- I1 => \s_tx_data_reg[113]\(61),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[65]_i_1_n_0\
- );
-\s_txdat[66]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"23"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[65]\,
- I1 => s_state(2),
- I2 => s_state(1),
- O => \s_txdat[66]_i_1_n_0\
- );
-\s_txdat[67]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[66]\,
- O => \s_txdat[67]_i_1_n_0\
- );
-\s_txdat[68]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[67]\,
- O => \s_txdat[68]_i_1_n_0\
- );
-\s_txdat[69]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[68]\,
- O => \s_txdat[69]_i_1_n_0\
- );
-\s_txdat[6]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[5]\,
- I1 => \s_tx_data_reg[113]\(2),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[6]_i_1_n_0\
- );
-\s_txdat[70]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[69]\,
- O => \s_txdat[70]_i_1_n_0\
- );
-\s_txdat[71]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[70]\,
- O => \s_txdat[71]_i_1_n_0\
- );
-\s_txdat[72]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[71]\,
- O => \s_txdat[72]_i_1_n_0\
- );
-\s_txdat[73]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[72]\,
- O => \s_txdat[73]_i_1_n_0\
- );
-\s_txdat[74]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[73]\,
- O => \s_txdat[74]_i_1_n_0\
- );
-\s_txdat[75]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[74]\,
- O => \s_txdat[75]_i_1_n_0\
- );
-\s_txdat[76]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[75]\,
- I1 => \s_tx_data_reg[113]\(36),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[76]_i_1_n_0\
- );
-\s_txdat[77]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[76]\,
- I1 => \s_tx_data_reg[113]\(37),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[77]_i_1_n_0\
- );
-\s_txdat[78]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[77]\,
- I1 => \s_tx_data_reg[113]\(38),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[78]_i_1_n_0\
- );
-\s_txdat[79]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[78]\,
- I1 => \s_tx_data_reg[113]\(39),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[79]_i_1_n_0\
- );
-\s_txdat[7]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[6]\,
- I1 => \s_tx_data_reg[113]\(3),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[7]_i_1_n_0\
- );
-\s_txdat[80]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[79]\,
- I1 => \s_tx_data_reg[113]\(40),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[80]_i_1_n_0\
- );
-\s_txdat[81]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[80]\,
- I1 => \s_tx_data_reg[113]\(41),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[81]_i_1_n_0\
- );
-\s_txdat[82]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[81]\,
- I1 => \s_tx_data_reg[113]\(42),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[82]_i_1_n_0\
- );
-\s_txdat[83]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[82]\,
- I1 => \s_tx_data_reg[113]\(43),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[83]_i_1_n_0\
- );
-\s_txdat[84]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[83]\,
- I1 => \s_tx_data_reg[113]\(44),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[84]_i_1_n_0\
- );
-\s_txdat[85]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[84]\,
- I1 => \s_tx_data_reg[113]\(45),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[85]_i_1_n_0\
- );
-\s_txdat[86]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[85]\,
- I1 => \s_tx_data_reg[113]\(46),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[86]_i_1_n_0\
- );
-\s_txdat[87]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[86]\,
- I1 => \s_tx_data_reg[113]\(47),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[87]_i_1_n_0\
- );
-\s_txdat[88]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[87]\,
- I1 => \s_tx_data_reg[113]\(60),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[88]_i_1_n_0\
- );
-\s_txdat[89]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[88]\,
- I1 => \s_tx_data_reg[113]\(61),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[89]_i_1_n_0\
- );
-\s_txdat[8]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[7]\,
- I1 => \s_tx_data_reg[113]\(4),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[8]_i_1_n_0\
- );
-\s_txdat[90]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"23"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[89]\,
- I1 => s_state(2),
- I2 => s_state(1),
- O => \s_txdat[90]_i_1_n_0\
- );
-\s_txdat[91]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[90]\,
- O => \s_txdat[91]_i_1_n_0\
- );
-\s_txdat[92]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[91]\,
- O => \s_txdat[92]_i_1_n_0\
- );
-\s_txdat[93]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[92]\,
- O => \s_txdat[93]_i_1_n_0\
- );
-\s_txdat[94]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[93]\,
- O => \s_txdat[94]_i_1_n_0\
- );
-\s_txdat[95]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[94]\,
- O => \s_txdat[95]_i_1_n_0\
- );
-\s_txdat[96]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[95]\,
- O => \s_txdat[96]_i_1_n_0\
- );
-\s_txdat[97]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[96]\,
- O => \s_txdat[97]_i_1_n_0\
- );
-\s_txdat[98]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[97]\,
- O => \s_txdat[98]_i_1_n_0\
- );
-\s_txdat[99]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => \s_txdat_reg_n_0_[98]\,
- O => \s_txdat[99]_i_1_n_0\
- );
-\s_txdat[9]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"00AC"
- )
- port map (
- I0 => \s_txdat_reg_n_0_[8]\,
- I1 => \s_tx_data_reg[113]\(5),
- I2 => s_state(1),
- I3 => s_state(2),
- O => \s_txdat[9]_i_1_n_0\
- );
-\s_txdat_reg[100]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[100]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[100]\,
- R => SR(0)
- );
-\s_txdat_reg[101]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[101]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[101]\,
- R => SR(0)
- );
-\s_txdat_reg[102]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[102]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[102]\,
- R => SR(0)
- );
-\s_txdat_reg[103]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[103]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[103]\,
- R => SR(0)
- );
-\s_txdat_reg[104]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[104]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[104]\,
- R => SR(0)
- );
-\s_txdat_reg[105]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[105]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[105]\,
- R => SR(0)
- );
-\s_txdat_reg[106]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[106]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[106]\,
- R => SR(0)
- );
-\s_txdat_reg[107]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[107]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[107]\,
- R => SR(0)
- );
-\s_txdat_reg[108]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[108]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[108]\,
- R => SR(0)
- );
-\s_txdat_reg[109]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[109]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[109]\,
- R => SR(0)
- );
-\s_txdat_reg[10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[10]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[10]\,
- R => SR(0)
- );
-\s_txdat_reg[110]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[110]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[110]\,
- R => SR(0)
- );
-\s_txdat_reg[111]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[111]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[111]\,
- R => SR(0)
- );
-\s_txdat_reg[112]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[112]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[112]\,
- R => SR(0)
- );
-\s_txdat_reg[113]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[113]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[113]\,
- R => SR(0)
- );
-\s_txdat_reg[114]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[114]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[114]\,
- R => SR(0)
- );
-\s_txdat_reg[115]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[115]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[115]\,
- R => SR(0)
- );
-\s_txdat_reg[116]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[116]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[116]\,
- R => SR(0)
- );
-\s_txdat_reg[117]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[117]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[117]\,
- R => SR(0)
- );
-\s_txdat_reg[118]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[118]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[118]\,
- R => SR(0)
- );
-\s_txdat_reg[119]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[119]_i_2_n_0\,
- Q => p_0_in,
- R => SR(0)
- );
-\s_txdat_reg[11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[11]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[11]\,
- R => SR(0)
- );
-\s_txdat_reg[12]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[12]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[12]\,
- R => SR(0)
- );
-\s_txdat_reg[13]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[13]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[13]\,
- R => SR(0)
- );
-\s_txdat_reg[14]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[14]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[14]\,
- R => SR(0)
- );
-\s_txdat_reg[15]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[15]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[15]\,
- R => SR(0)
- );
-\s_txdat_reg[16]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[16]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[16]\,
- R => SR(0)
- );
-\s_txdat_reg[17]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[17]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[17]\,
- R => SR(0)
- );
-\s_txdat_reg[18]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[18]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[18]\,
- R => SR(0)
- );
-\s_txdat_reg[19]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[19]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[19]\,
- R => SR(0)
- );
-\s_txdat_reg[20]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[20]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[20]\,
- R => SR(0)
- );
-\s_txdat_reg[21]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[21]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[21]\,
- R => SR(0)
- );
-\s_txdat_reg[22]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[22]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[22]\,
- R => SR(0)
- );
-\s_txdat_reg[23]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[23]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[23]\,
- R => SR(0)
- );
-\s_txdat_reg[24]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[24]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[24]\,
- R => SR(0)
- );
-\s_txdat_reg[25]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[25]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[25]\,
- R => SR(0)
- );
-\s_txdat_reg[26]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[26]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[26]\,
- R => SR(0)
- );
-\s_txdat_reg[27]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[27]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[27]\,
- R => SR(0)
- );
-\s_txdat_reg[28]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[28]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[28]\,
- R => SR(0)
- );
-\s_txdat_reg[29]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[29]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[29]\,
- R => SR(0)
- );
-\s_txdat_reg[30]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[30]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[30]\,
- R => SR(0)
- );
-\s_txdat_reg[31]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[31]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[31]\,
- R => SR(0)
- );
-\s_txdat_reg[32]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[32]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[32]\,
- R => SR(0)
- );
-\s_txdat_reg[33]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[33]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[33]\,
- R => SR(0)
- );
-\s_txdat_reg[34]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[34]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[34]\,
- R => SR(0)
- );
-\s_txdat_reg[35]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[35]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[35]\,
- R => SR(0)
- );
-\s_txdat_reg[36]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[36]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[36]\,
- R => SR(0)
- );
-\s_txdat_reg[37]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[37]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[37]\,
- R => SR(0)
- );
-\s_txdat_reg[38]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[38]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[38]\,
- R => SR(0)
- );
-\s_txdat_reg[39]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[39]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[39]\,
- R => SR(0)
- );
-\s_txdat_reg[40]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[40]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[40]\,
- R => SR(0)
- );
-\s_txdat_reg[41]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[41]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[41]\,
- R => SR(0)
- );
-\s_txdat_reg[42]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[42]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[42]\,
- R => SR(0)
- );
-\s_txdat_reg[43]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[43]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[43]\,
- R => SR(0)
- );
-\s_txdat_reg[44]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[44]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[44]\,
- R => SR(0)
- );
-\s_txdat_reg[45]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[45]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[45]\,
- R => SR(0)
- );
-\s_txdat_reg[46]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[46]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[46]\,
- R => SR(0)
- );
-\s_txdat_reg[47]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[47]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[47]\,
- R => SR(0)
- );
-\s_txdat_reg[48]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[48]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[48]\,
- R => SR(0)
- );
-\s_txdat_reg[49]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[49]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[49]\,
- R => SR(0)
- );
-\s_txdat_reg[4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[4]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[4]\,
- R => SR(0)
- );
-\s_txdat_reg[50]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[50]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[50]\,
- R => SR(0)
- );
-\s_txdat_reg[51]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[51]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[51]\,
- R => SR(0)
- );
-\s_txdat_reg[52]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[52]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[52]\,
- R => SR(0)
- );
-\s_txdat_reg[53]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[53]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[53]\,
- R => SR(0)
- );
-\s_txdat_reg[54]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[54]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[54]\,
- R => SR(0)
- );
-\s_txdat_reg[55]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[55]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[55]\,
- R => SR(0)
- );
-\s_txdat_reg[56]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[56]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[56]\,
- R => SR(0)
- );
-\s_txdat_reg[57]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[57]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[57]\,
- R => SR(0)
- );
-\s_txdat_reg[58]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[58]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[58]\,
- R => SR(0)
- );
-\s_txdat_reg[59]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[59]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[59]\,
- R => SR(0)
- );
-\s_txdat_reg[5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[5]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[5]\,
- R => SR(0)
- );
-\s_txdat_reg[60]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[60]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[60]\,
- R => SR(0)
- );
-\s_txdat_reg[61]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[61]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[61]\,
- R => SR(0)
- );
-\s_txdat_reg[62]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[62]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[62]\,
- R => SR(0)
- );
-\s_txdat_reg[63]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[63]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[63]\,
- R => SR(0)
- );
-\s_txdat_reg[64]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[64]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[64]\,
- R => SR(0)
- );
-\s_txdat_reg[65]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[65]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[65]\,
- R => SR(0)
- );
-\s_txdat_reg[66]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[66]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[66]\,
- R => SR(0)
- );
-\s_txdat_reg[67]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[67]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[67]\,
- R => SR(0)
- );
-\s_txdat_reg[68]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[68]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[68]\,
- R => SR(0)
- );
-\s_txdat_reg[69]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[69]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[69]\,
- R => SR(0)
- );
-\s_txdat_reg[6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[6]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[6]\,
- R => SR(0)
- );
-\s_txdat_reg[70]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[70]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[70]\,
- R => SR(0)
- );
-\s_txdat_reg[71]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[71]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[71]\,
- R => SR(0)
- );
-\s_txdat_reg[72]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[72]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[72]\,
- R => SR(0)
- );
-\s_txdat_reg[73]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[73]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[73]\,
- R => SR(0)
- );
-\s_txdat_reg[74]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[74]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[74]\,
- R => SR(0)
- );
-\s_txdat_reg[75]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[75]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[75]\,
- R => SR(0)
- );
-\s_txdat_reg[76]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[76]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[76]\,
- R => SR(0)
- );
-\s_txdat_reg[77]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[77]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[77]\,
- R => SR(0)
- );
-\s_txdat_reg[78]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[78]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[78]\,
- R => SR(0)
- );
-\s_txdat_reg[79]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[79]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[79]\,
- R => SR(0)
- );
-\s_txdat_reg[7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[7]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[7]\,
- R => SR(0)
- );
-\s_txdat_reg[80]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[80]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[80]\,
- R => SR(0)
- );
-\s_txdat_reg[81]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[81]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[81]\,
- R => SR(0)
- );
-\s_txdat_reg[82]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[82]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[82]\,
- R => SR(0)
- );
-\s_txdat_reg[83]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[83]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[83]\,
- R => SR(0)
- );
-\s_txdat_reg[84]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[84]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[84]\,
- R => SR(0)
- );
-\s_txdat_reg[85]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[85]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[85]\,
- R => SR(0)
- );
-\s_txdat_reg[86]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[86]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[86]\,
- R => SR(0)
- );
-\s_txdat_reg[87]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[87]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[87]\,
- R => SR(0)
- );
-\s_txdat_reg[88]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[88]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[88]\,
- R => SR(0)
- );
-\s_txdat_reg[89]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[89]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[89]\,
- R => SR(0)
- );
-\s_txdat_reg[8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[8]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[8]\,
- R => SR(0)
- );
-\s_txdat_reg[90]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[90]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[90]\,
- R => SR(0)
- );
-\s_txdat_reg[91]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[91]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[91]\,
- R => SR(0)
- );
-\s_txdat_reg[92]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[92]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[92]\,
- R => SR(0)
- );
-\s_txdat_reg[93]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[93]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[93]\,
- R => SR(0)
- );
-\s_txdat_reg[94]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[94]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[94]\,
- R => SR(0)
- );
-\s_txdat_reg[95]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[95]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[95]\,
- R => SR(0)
- );
-\s_txdat_reg[96]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[96]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[96]\,
- R => SR(0)
- );
-\s_txdat_reg[97]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[97]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[97]\,
- R => SR(0)
- );
-\s_txdat_reg[98]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[98]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[98]\,
- R => SR(0)
- );
-\s_txdat_reg[99]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[99]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[99]\,
- R => SR(0)
- );
-\s_txdat_reg[9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => s_txdat,
- D => \s_txdat[9]_i_1_n_0\,
- Q => \s_txdat_reg_n_0_[9]\,
- R => SR(0)
- );
-\v_ch_address[0]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"38"
- )
- port map (
- I0 => \s_state_reg[0]_0\,
- I1 => v_ch_address,
- I2 => ch_address(0),
- O => \v_ch_address_reg[0]\
- );
-\v_ch_address[1]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"4F80"
- )
- port map (
- I0 => ch_address(0),
- I1 => \s_state_reg[0]_0\,
- I2 => v_ch_address,
- I3 => ch_address(1),
- O => \v_ch_address_reg[1]\
- );
-\v_ch_address[1]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"CA000A000A000A00"
- )
- port map (
- I0 => \data_rw_o_reg[11][1]\,
- I1 => \v_ch_address_reg[0]_0\,
- I2 => \s_state_reg[1]_0\,
- I3 => s00_axi_aresetn,
- I4 => s_done,
- I5 => \s_state_reg[0]_0\,
- O => v_ch_address
- );
-\v_ch_address[1]_i_4\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s_state(0),
- I1 => s_state(1),
- O => s_done
- );
-\v_cnt[0]_i_1\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"0026"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => s_state(0),
- I3 => \v_cnt_reg_n_0_[0]\,
- O => \v_cnt[0]_i_1_n_0\
- );
-\v_cnt[1]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"00262600"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => s_state(0),
- I3 => \v_cnt_reg_n_0_[1]\,
- I4 => \v_cnt_reg_n_0_[0]\,
- O => \v_cnt[1]_i_1_n_0\
- );
-\v_cnt[2]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0026260026002600"
- )
- port map (
- I0 => s_state(2),
- I1 => s_state(1),
- I2 => s_state(0),
- I3 => \v_cnt_reg_n_0_[2]\,
- I4 => \v_cnt_reg_n_0_[0]\,
- I5 => \v_cnt_reg_n_0_[1]\,
- O => \v_cnt[2]_i_1_n_0\
- );
-\v_cnt[3]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"28888888"
- )
- port map (
- I0 => \v_cnt[6]_i_4_n_0\,
- I1 => \v_cnt_reg_n_0_[3]\,
- I2 => \v_cnt_reg_n_0_[1]\,
- I3 => \v_cnt_reg_n_0_[0]\,
- I4 => \v_cnt_reg_n_0_[2]\,
- O => \v_cnt[3]_i_1_n_0\
- );
-\v_cnt[4]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"2888888888888888"
- )
- port map (
- I0 => \v_cnt[6]_i_4_n_0\,
- I1 => \v_cnt_reg_n_0_[4]\,
- I2 => \v_cnt_reg_n_0_[2]\,
- I3 => \v_cnt_reg_n_0_[0]\,
- I4 => \v_cnt_reg_n_0_[1]\,
- I5 => \v_cnt_reg_n_0_[3]\,
- O => \v_cnt[4]_i_1_n_0\
- );
-\v_cnt[5]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88882888"
- )
- port map (
- I0 => \v_cnt[6]_i_4_n_0\,
- I1 => \v_cnt_reg_n_0_[5]\,
- I2 => \v_cnt_reg_n_0_[4]\,
- I3 => \v_cnt_reg_n_0_[3]\,
- I4 => \v_cnt[6]_i_5_n_0\,
- O => \v_cnt[5]_i_1_n_0\
- );
-\v_cnt[6]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"EEEEEEEEEEEEEFEE"
- )
- port map (
- I0 => \v_cnt[6]_i_3_n_0\,
- I1 => s_rxdat_0,
- I2 => s_state(0),
- I3 => s_start_reg,
- I4 => s_state(2),
- I5 => s_state(1),
- O => v_cnt
- );
-\v_cnt[6]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"8888888828888888"
- )
- port map (
- I0 => \v_cnt[6]_i_4_n_0\,
- I1 => \v_cnt_reg_n_0_[6]\,
- I2 => \v_cnt_reg_n_0_[5]\,
- I3 => \v_cnt_reg_n_0_[3]\,
- I4 => \v_cnt_reg_n_0_[4]\,
- I5 => \v_cnt[6]_i_5_n_0\,
- O => \v_cnt[6]_i_2_n_0\
- );
-\v_cnt[6]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000C000010101010"
- )
- port map (
- I0 => \FSM_sequential_s_state[2]_i_4_n_0\,
- I1 => s_state(1),
- I2 => s_state(2),
- I3 => \s_txdat[119]_i_4_n_0\,
- I4 => \s_txdat[119]_i_3_n_0\,
- I5 => s_state(0),
- O => \v_cnt[6]_i_3_n_0\
- );
-\v_cnt[6]_i_4\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"34"
- )
- port map (
- I0 => s_state(0),
- I1 => s_state(1),
- I2 => s_state(2),
- O => \v_cnt[6]_i_4_n_0\
- );
-\v_cnt[6]_i_5\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"7F"
- )
- port map (
- I0 => \v_cnt_reg_n_0_[1]\,
- I1 => \v_cnt_reg_n_0_[0]\,
- I2 => \v_cnt_reg_n_0_[2]\,
- O => \v_cnt[6]_i_5_n_0\
- );
-\v_cnt_reg[0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => v_cnt,
- D => \v_cnt[0]_i_1_n_0\,
- Q => \v_cnt_reg_n_0_[0]\,
- R => SR(0)
- );
-\v_cnt_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => v_cnt,
- D => \v_cnt[1]_i_1_n_0\,
- Q => \v_cnt_reg_n_0_[1]\,
- R => SR(0)
- );
-\v_cnt_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => v_cnt,
- D => \v_cnt[2]_i_1_n_0\,
- Q => \v_cnt_reg_n_0_[2]\,
- R => SR(0)
- );
-\v_cnt_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => v_cnt,
- D => \v_cnt[3]_i_1_n_0\,
- Q => \v_cnt_reg_n_0_[3]\,
- R => SR(0)
- );
-\v_cnt_reg[4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => v_cnt,
- D => \v_cnt[4]_i_1_n_0\,
- Q => \v_cnt_reg_n_0_[4]\,
- R => SR(0)
- );
-\v_cnt_reg[5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => v_cnt,
- D => \v_cnt[5]_i_1_n_0\,
- Q => \v_cnt_reg_n_0_[5]\,
- R => SR(0)
- );
-\v_cnt_reg[6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => v_cnt,
- D => \v_cnt[6]_i_2_n_0\,
- Q => \v_cnt_reg_n_0_[6]\,
- R => SR(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_dac7716_spi is
- port (
- s_start : out STD_LOGIC;
- \dac_ch_o_reg[0][0]_0\ : out STD_LOGIC;
- \dac_ch_o_reg[0][0]_1\ : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[111]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[15]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[15]_1\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]_1\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]_2\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]_3\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_counter_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_rdata_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
- s_spi_mosi : out STD_LOGIC;
- s_spi_cs_n : out STD_LOGIC;
- rst_i : in STD_LOGIC;
- s_start_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- \data_rw_o_reg[79][2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \data_rw_o_reg[87][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[87][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[86][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[86][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[85][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[85][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[84][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[84][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[88][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[88][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[89][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[89][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[90][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[90][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[91][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[91][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[92][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[93][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[94][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[95][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[96][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[97][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[98][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[99][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[100][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[101][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[102][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[103][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- D : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_dac7716_spi : entity is "dac7716_spi";
-end system_design_fasec_hwtest_0_0_dac7716_spi;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_dac7716_spi is
- signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[0].[0].s_reqs[0][changed]_i_1__0_n_0\ : STD_LOGIC;
- signal \[0].[0].s_reqs_reg[0][changed_n_0_]\ : STD_LOGIC;
- signal \[0].[1].s_reqs[1][changed]_i_1__0_n_0\ : STD_LOGIC;
- signal \[0].[1].s_reqs_reg[1][changed_n_0_]\ : STD_LOGIC;
- signal \[0].[2].s_reqs[2][changed]_i_1__0_n_0\ : STD_LOGIC;
- signal \[0].[2].s_reqs_reg[2][changed_n_0_]\ : STD_LOGIC;
- signal \[0].[3].s_reqs[3][changed]_i_1__0_n_0\ : STD_LOGIC;
- signal \[0].[3].s_reqs_reg[3][changed_n_0_]\ : STD_LOGIC;
- signal \[1].[0].s_reqs[4][changed]_i_1__0_n_0\ : STD_LOGIC;
- signal \[1].[0].s_reqs_reg[4][changed]__1\ : STD_LOGIC;
- signal \[1].[1].s_reqs[5][changed]_i_1__0_n_0\ : STD_LOGIC;
- signal \[1].[1].s_reqs_reg[5][changed]__1\ : STD_LOGIC;
- signal \[1].[2].s_reqs[6][changed]_i_1__0_n_0\ : STD_LOGIC;
- signal \[1].[2].s_reqs_reg[6][changed]__1\ : STD_LOGIC;
- signal \[1].[3].s_reqs[7][changed]_i_1__0_n_0\ : STD_LOGIC;
- signal \[1].[3].s_reqs_reg[7][changed]__1\ : STD_LOGIC;
- signal \[2].[0].s_reqs_reg[8][value]__0__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[2].[1].s_reqs_reg[9][value]__0__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[2].[2].s_reqs_reg[10][value]__0__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[2].[3].s_reqs_reg[11][value]__0__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[3].[0].s_reqs_reg[12][value]__0__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[3].[1].s_reqs_reg[13][value]__0__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[3].[2].s_reqs_reg[14][value]__0__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[3].[3].s_reqs_reg[15][value]__0__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[4].[0].s_reqs_reg[16][value]__0__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[4].[1].s_reqs_reg[17][value]__0__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[4].[2].s_reqs_reg[18][value]__0__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[4].[3].s_reqs_reg[19][value]__0__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal ch_address : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal cmp_spi_n_0 : STD_LOGIC;
- signal cmp_spi_n_1 : STD_LOGIC;
- signal cmp_spi_n_2 : STD_LOGIC;
- signal cmp_spi_n_3 : STD_LOGIC;
- signal cmp_spi_n_4 : STD_LOGIC;
- signal \dac_ch_o[0][31]_i_2__0_n_0\ : STD_LOGIC;
- signal \^dac_ch_o_reg[0][0]_0\ : STD_LOGIC;
- signal \^dac_ch_o_reg[0][0]_1\ : STD_LOGIC;
- signal p_0_in : STD_LOGIC;
- signal p_1_in : STD_LOGIC;
- signal p_2_in : STD_LOGIC;
- signal rx_data_o : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal \s_flag_reset[0]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_flag_reset[1]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_flag_reset[2]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_flag_reset[3]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_flag_reset_reg_n_0_[0]\ : STD_LOGIC;
- signal \s_reqs[0][value]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_start\ : STD_LOGIC;
- signal \s_state[1]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_state[1]_i_3__0_n_0\ : STD_LOGIC;
- signal \s_state[1]_i_5__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[100]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[100]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[101]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[101]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[102]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[102]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[103]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[103]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[104]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[104]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[105]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[105]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[106]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[106]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[107]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[107]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[108]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[108]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[109]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[109]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[10]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[110]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[110]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[111]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[111]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[113]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[11]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[12]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[13]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[14]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[15]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[28]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[28]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[29]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[29]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[30]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[30]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[31]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[31]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[32]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[32]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[33]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[33]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[34]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[34]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[35]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[35]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[36]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[36]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[37]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[37]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[38]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[38]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[39]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[39]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[4]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[52]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[52]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[53]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[53]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[54]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[54]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[55]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[55]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[56]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[56]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[57]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[57]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[58]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[58]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[59]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[59]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[5]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[60]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[60]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[61]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[61]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[62]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[62]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[63]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[63]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[6]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[76]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[76]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[77]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[77]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[78]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[78]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[79]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[79]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[7]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[80]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[80]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[81]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[81]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[82]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[82]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[83]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[83]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[84]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[84]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[85]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[85]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[86]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[86]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[87]_i_1__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[87]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[8]_i_2__0_n_0\ : STD_LOGIC;
- signal \s_tx_data[9]_i_2__0_n_0\ : STD_LOGIC;
- signal \^s_tx_data_reg[111]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_tx_data_reg[15]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_tx_data_reg[15]_1\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_tx_data_reg[39]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_tx_data_reg[39]_1\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_tx_data_reg[39]_2\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_tx_data_reg[39]_3\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \s_tx_data_reg_n_0_[100]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[101]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[102]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[103]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[104]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[105]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[106]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[107]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[108]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[109]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[10]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[110]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[111]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[112]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[113]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[11]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[12]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[13]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[14]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[15]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[28]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[29]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[30]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[31]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[32]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[33]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[34]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[35]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[36]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[37]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[38]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[39]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[4]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[52]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[53]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[54]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[55]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[56]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[57]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[58]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[59]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[5]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[60]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[61]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[62]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[63]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[6]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[76]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[77]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[78]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[79]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[7]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[80]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[81]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[82]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[83]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[84]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[85]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[86]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[87]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[8]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[9]\ : STD_LOGIC;
- signal \v_ch_address[1]_i_3__0_n_0\ : STD_LOGIC;
- signal \v_ch_address[1]_i_5__0_n_0\ : STD_LOGIC;
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \[0].[0].s_reqs[0][changed]_i_1__0\ : label is "soft_lutpair56";
- attribute SOFT_HLUTNM of \[0].[1].s_reqs[1][changed]_i_1__0\ : label is "soft_lutpair54";
- attribute SOFT_HLUTNM of \[0].[2].s_reqs[2][changed]_i_1__0\ : label is "soft_lutpair55";
- attribute SOFT_HLUTNM of \[0].[3].s_reqs[3][changed]_i_1__0\ : label is "soft_lutpair57";
- attribute SOFT_HLUTNM of \[1].[0].s_reqs[4][changed]_i_1__0\ : label is "soft_lutpair56";
- attribute SOFT_HLUTNM of \[1].[1].s_reqs[5][changed]_i_1__0\ : label is "soft_lutpair54";
- attribute SOFT_HLUTNM of \[1].[2].s_reqs[6][changed]_i_1__0\ : label is "soft_lutpair55";
- attribute SOFT_HLUTNM of \[1].[3].s_reqs[7][changed]_i_1__0\ : label is "soft_lutpair57";
- attribute SOFT_HLUTNM of \dac_ch_o[0][31]_i_2__0\ : label is "soft_lutpair53";
- attribute SOFT_HLUTNM of \s_tx_data[14]_i_1__0\ : label is "soft_lutpair53";
-begin
- Q(11 downto 0) <= \^q\(11 downto 0);
- \dac_ch_o_reg[0][0]_0\ <= \^dac_ch_o_reg[0][0]_0\;
- \dac_ch_o_reg[0][0]_1\ <= \^dac_ch_o_reg[0][0]_1\;
- s_start <= \^s_start\;
- \s_tx_data_reg[111]_0\(11 downto 0) <= \^s_tx_data_reg[111]_0\(11 downto 0);
- \s_tx_data_reg[15]_0\(11 downto 0) <= \^s_tx_data_reg[15]_0\(11 downto 0);
- \s_tx_data_reg[15]_1\(11 downto 0) <= \^s_tx_data_reg[15]_1\(11 downto 0);
- \s_tx_data_reg[39]_0\(11 downto 0) <= \^s_tx_data_reg[39]_0\(11 downto 0);
- \s_tx_data_reg[39]_1\(11 downto 0) <= \^s_tx_data_reg[39]_1\(11 downto 0);
- \s_tx_data_reg[39]_2\(11 downto 0) <= \^s_tx_data_reg[39]_2\(11 downto 0);
- \s_tx_data_reg[39]_3\(11 downto 0) <= \^s_tx_data_reg[39]_3\(11 downto 0);
-\[0].[0].s_reqs[0][changed]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[0].[0].s_reqs_reg[0][changed_n_0_]\,
- I1 => \data_rw_o_reg[84][11]_0\(0),
- I2 => \s_flag_reset_reg_n_0_[0]\,
- O => \[0].[0].s_reqs[0][changed]_i_1__0_n_0\
- );
-\[0].[0].s_reqs_reg[0][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[0].[0].s_reqs[0][changed]_i_1__0_n_0\,
- Q => \[0].[0].s_reqs_reg[0][changed_n_0_]\,
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[84][11]\(0),
- Q => \^s_tx_data_reg[111]_0\(0),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[84][11]\(10),
- Q => \^s_tx_data_reg[111]_0\(10),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[84][11]\(11),
- Q => \^s_tx_data_reg[111]_0\(11),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[84][11]\(1),
- Q => \^s_tx_data_reg[111]_0\(1),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[84][11]\(2),
- Q => \^s_tx_data_reg[111]_0\(2),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[84][11]\(3),
- Q => \^s_tx_data_reg[111]_0\(3),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[84][11]\(4),
- Q => \^s_tx_data_reg[111]_0\(4),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[84][11]\(5),
- Q => \^s_tx_data_reg[111]_0\(5),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[84][11]\(6),
- Q => \^s_tx_data_reg[111]_0\(6),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[84][11]\(7),
- Q => \^s_tx_data_reg[111]_0\(7),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[84][11]\(8),
- Q => \^s_tx_data_reg[111]_0\(8),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[84][11]\(9),
- Q => \^s_tx_data_reg[111]_0\(9),
- R => '0'
- );
-\[0].[1].s_reqs[1][changed]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[0].[1].s_reqs_reg[1][changed_n_0_]\,
- I1 => \data_rw_o_reg[85][11]_0\(0),
- I2 => p_2_in,
- O => \[0].[1].s_reqs[1][changed]_i_1__0_n_0\
- );
-\[0].[1].s_reqs_reg[1][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[0].[1].s_reqs[1][changed]_i_1__0_n_0\,
- Q => \[0].[1].s_reqs_reg[1][changed_n_0_]\,
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[85][11]\(0),
- Q => \^s_tx_data_reg[15]_0\(0),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[85][11]\(10),
- Q => \^s_tx_data_reg[15]_0\(10),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[85][11]\(11),
- Q => \^s_tx_data_reg[15]_0\(11),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[85][11]\(1),
- Q => \^s_tx_data_reg[15]_0\(1),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[85][11]\(2),
- Q => \^s_tx_data_reg[15]_0\(2),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[85][11]\(3),
- Q => \^s_tx_data_reg[15]_0\(3),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[85][11]\(4),
- Q => \^s_tx_data_reg[15]_0\(4),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[85][11]\(5),
- Q => \^s_tx_data_reg[15]_0\(5),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[85][11]\(6),
- Q => \^s_tx_data_reg[15]_0\(6),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[85][11]\(7),
- Q => \^s_tx_data_reg[15]_0\(7),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[85][11]\(8),
- Q => \^s_tx_data_reg[15]_0\(8),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[85][11]\(9),
- Q => \^s_tx_data_reg[15]_0\(9),
- R => '0'
- );
-\[0].[2].s_reqs[2][changed]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[0].[2].s_reqs_reg[2][changed_n_0_]\,
- I1 => \data_rw_o_reg[86][11]_0\(0),
- I2 => p_1_in,
- O => \[0].[2].s_reqs[2][changed]_i_1__0_n_0\
- );
-\[0].[2].s_reqs_reg[2][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[0].[2].s_reqs[2][changed]_i_1__0_n_0\,
- Q => \[0].[2].s_reqs_reg[2][changed_n_0_]\,
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[86][11]\(0),
- Q => \^s_tx_data_reg[15]_1\(0),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[86][11]\(10),
- Q => \^s_tx_data_reg[15]_1\(10),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[86][11]\(11),
- Q => \^s_tx_data_reg[15]_1\(11),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[86][11]\(1),
- Q => \^s_tx_data_reg[15]_1\(1),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[86][11]\(2),
- Q => \^s_tx_data_reg[15]_1\(2),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[86][11]\(3),
- Q => \^s_tx_data_reg[15]_1\(3),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[86][11]\(4),
- Q => \^s_tx_data_reg[15]_1\(4),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[86][11]\(5),
- Q => \^s_tx_data_reg[15]_1\(5),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[86][11]\(6),
- Q => \^s_tx_data_reg[15]_1\(6),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[86][11]\(7),
- Q => \^s_tx_data_reg[15]_1\(7),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[86][11]\(8),
- Q => \^s_tx_data_reg[15]_1\(8),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[86][11]\(9),
- Q => \^s_tx_data_reg[15]_1\(9),
- R => '0'
- );
-\[0].[3].s_reqs[3][changed]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[0].[3].s_reqs_reg[3][changed_n_0_]\,
- I1 => \data_rw_o_reg[87][11]_0\(0),
- I2 => p_0_in,
- O => \[0].[3].s_reqs[3][changed]_i_1__0_n_0\
- );
-\[0].[3].s_reqs_reg[3][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[0].[3].s_reqs[3][changed]_i_1__0_n_0\,
- Q => \[0].[3].s_reqs_reg[3][changed_n_0_]\,
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[87][11]\(0),
- Q => \^q\(0),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[87][11]\(10),
- Q => \^q\(10),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[87][11]\(11),
- Q => \^q\(11),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[87][11]\(1),
- Q => \^q\(1),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[87][11]\(2),
- Q => \^q\(2),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[87][11]\(3),
- Q => \^q\(3),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[87][11]\(4),
- Q => \^q\(4),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[87][11]\(5),
- Q => \^q\(5),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[87][11]\(6),
- Q => \^q\(6),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[87][11]\(7),
- Q => \^q\(7),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[87][11]\(8),
- Q => \^q\(8),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[87][11]\(9),
- Q => \^q\(9),
- R => '0'
- );
-\[1].[0].s_reqs[4][changed]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[1].[0].s_reqs_reg[4][changed]__1\,
- I1 => \data_rw_o_reg[88][11]_0\(0),
- I2 => \s_flag_reset_reg_n_0_[0]\,
- O => \[1].[0].s_reqs[4][changed]_i_1__0_n_0\
- );
-\[1].[0].s_reqs_reg[4][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[1].[0].s_reqs[4][changed]_i_1__0_n_0\,
- Q => \[1].[0].s_reqs_reg[4][changed]__1\,
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[88][11]\(0),
- Q => \^s_tx_data_reg[39]_1\(0),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[88][11]\(10),
- Q => \^s_tx_data_reg[39]_1\(10),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[88][11]\(11),
- Q => \^s_tx_data_reg[39]_1\(11),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[88][11]\(1),
- Q => \^s_tx_data_reg[39]_1\(1),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[88][11]\(2),
- Q => \^s_tx_data_reg[39]_1\(2),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[88][11]\(3),
- Q => \^s_tx_data_reg[39]_1\(3),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[88][11]\(4),
- Q => \^s_tx_data_reg[39]_1\(4),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[88][11]\(5),
- Q => \^s_tx_data_reg[39]_1\(5),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[88][11]\(6),
- Q => \^s_tx_data_reg[39]_1\(6),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[88][11]\(7),
- Q => \^s_tx_data_reg[39]_1\(7),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[88][11]\(8),
- Q => \^s_tx_data_reg[39]_1\(8),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[88][11]\(9),
- Q => \^s_tx_data_reg[39]_1\(9),
- R => '0'
- );
-\[1].[1].s_reqs[5][changed]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[1].[1].s_reqs_reg[5][changed]__1\,
- I1 => \data_rw_o_reg[89][11]_0\(0),
- I2 => p_2_in,
- O => \[1].[1].s_reqs[5][changed]_i_1__0_n_0\
- );
-\[1].[1].s_reqs_reg[5][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[1].[1].s_reqs[5][changed]_i_1__0_n_0\,
- Q => \[1].[1].s_reqs_reg[5][changed]__1\,
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[89][11]\(0),
- Q => \^s_tx_data_reg[39]_2\(0),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[89][11]\(10),
- Q => \^s_tx_data_reg[39]_2\(10),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[89][11]\(11),
- Q => \^s_tx_data_reg[39]_2\(11),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[89][11]\(1),
- Q => \^s_tx_data_reg[39]_2\(1),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[89][11]\(2),
- Q => \^s_tx_data_reg[39]_2\(2),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[89][11]\(3),
- Q => \^s_tx_data_reg[39]_2\(3),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[89][11]\(4),
- Q => \^s_tx_data_reg[39]_2\(4),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[89][11]\(5),
- Q => \^s_tx_data_reg[39]_2\(5),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[89][11]\(6),
- Q => \^s_tx_data_reg[39]_2\(6),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[89][11]\(7),
- Q => \^s_tx_data_reg[39]_2\(7),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[89][11]\(8),
- Q => \^s_tx_data_reg[39]_2\(8),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[89][11]\(9),
- Q => \^s_tx_data_reg[39]_2\(9),
- R => '0'
- );
-\[1].[2].s_reqs[6][changed]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[1].[2].s_reqs_reg[6][changed]__1\,
- I1 => \data_rw_o_reg[90][11]_0\(0),
- I2 => p_1_in,
- O => \[1].[2].s_reqs[6][changed]_i_1__0_n_0\
- );
-\[1].[2].s_reqs_reg[6][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[1].[2].s_reqs[6][changed]_i_1__0_n_0\,
- Q => \[1].[2].s_reqs_reg[6][changed]__1\,
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[90][11]\(0),
- Q => \^s_tx_data_reg[39]_3\(0),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[90][11]\(10),
- Q => \^s_tx_data_reg[39]_3\(10),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[90][11]\(11),
- Q => \^s_tx_data_reg[39]_3\(11),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[90][11]\(1),
- Q => \^s_tx_data_reg[39]_3\(1),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[90][11]\(2),
- Q => \^s_tx_data_reg[39]_3\(2),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[90][11]\(3),
- Q => \^s_tx_data_reg[39]_3\(3),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[90][11]\(4),
- Q => \^s_tx_data_reg[39]_3\(4),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[90][11]\(5),
- Q => \^s_tx_data_reg[39]_3\(5),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[90][11]\(6),
- Q => \^s_tx_data_reg[39]_3\(6),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[90][11]\(7),
- Q => \^s_tx_data_reg[39]_3\(7),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[90][11]\(8),
- Q => \^s_tx_data_reg[39]_3\(8),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[90][11]\(9),
- Q => \^s_tx_data_reg[39]_3\(9),
- R => '0'
- );
-\[1].[3].s_reqs[7][changed]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[1].[3].s_reqs_reg[7][changed]__1\,
- I1 => \data_rw_o_reg[91][11]_0\(0),
- I2 => p_0_in,
- O => \[1].[3].s_reqs[7][changed]_i_1__0_n_0\
- );
-\[1].[3].s_reqs_reg[7][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[1].[3].s_reqs[7][changed]_i_1__0_n_0\,
- Q => \[1].[3].s_reqs_reg[7][changed]__1\,
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[91][11]\(0),
- Q => \^s_tx_data_reg[39]_0\(0),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[91][11]\(10),
- Q => \^s_tx_data_reg[39]_0\(10),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[91][11]\(11),
- Q => \^s_tx_data_reg[39]_0\(11),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[91][11]\(1),
- Q => \^s_tx_data_reg[39]_0\(1),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[91][11]\(2),
- Q => \^s_tx_data_reg[39]_0\(2),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[91][11]\(3),
- Q => \^s_tx_data_reg[39]_0\(3),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[91][11]\(4),
- Q => \^s_tx_data_reg[39]_0\(4),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[91][11]\(5),
- Q => \^s_tx_data_reg[39]_0\(5),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[91][11]\(6),
- Q => \^s_tx_data_reg[39]_0\(6),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[91][11]\(7),
- Q => \^s_tx_data_reg[39]_0\(7),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[91][11]\(8),
- Q => \^s_tx_data_reg[39]_0\(8),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[91][11]\(9),
- Q => \^s_tx_data_reg[39]_0\(9),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[92][11]\(0),
- Q => \[2].[0].s_reqs_reg[8][value]__0__0\(0),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[92][11]\(10),
- Q => \[2].[0].s_reqs_reg[8][value]__0__0\(10),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[92][11]\(11),
- Q => \[2].[0].s_reqs_reg[8][value]__0__0\(11),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[92][11]\(1),
- Q => \[2].[0].s_reqs_reg[8][value]__0__0\(1),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[92][11]\(2),
- Q => \[2].[0].s_reqs_reg[8][value]__0__0\(2),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[92][11]\(3),
- Q => \[2].[0].s_reqs_reg[8][value]__0__0\(3),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[92][11]\(4),
- Q => \[2].[0].s_reqs_reg[8][value]__0__0\(4),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[92][11]\(5),
- Q => \[2].[0].s_reqs_reg[8][value]__0__0\(5),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[92][11]\(6),
- Q => \[2].[0].s_reqs_reg[8][value]__0__0\(6),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[92][11]\(7),
- Q => \[2].[0].s_reqs_reg[8][value]__0__0\(7),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[92][11]\(8),
- Q => \[2].[0].s_reqs_reg[8][value]__0__0\(8),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[92][11]\(9),
- Q => \[2].[0].s_reqs_reg[8][value]__0__0\(9),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[93][11]\(0),
- Q => \[2].[1].s_reqs_reg[9][value]__0__0\(0),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[93][11]\(10),
- Q => \[2].[1].s_reqs_reg[9][value]__0__0\(10),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[93][11]\(11),
- Q => \[2].[1].s_reqs_reg[9][value]__0__0\(11),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[93][11]\(1),
- Q => \[2].[1].s_reqs_reg[9][value]__0__0\(1),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[93][11]\(2),
- Q => \[2].[1].s_reqs_reg[9][value]__0__0\(2),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[93][11]\(3),
- Q => \[2].[1].s_reqs_reg[9][value]__0__0\(3),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[93][11]\(4),
- Q => \[2].[1].s_reqs_reg[9][value]__0__0\(4),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[93][11]\(5),
- Q => \[2].[1].s_reqs_reg[9][value]__0__0\(5),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[93][11]\(6),
- Q => \[2].[1].s_reqs_reg[9][value]__0__0\(6),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[93][11]\(7),
- Q => \[2].[1].s_reqs_reg[9][value]__0__0\(7),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[93][11]\(8),
- Q => \[2].[1].s_reqs_reg[9][value]__0__0\(8),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[93][11]\(9),
- Q => \[2].[1].s_reqs_reg[9][value]__0__0\(9),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[94][11]\(0),
- Q => \[2].[2].s_reqs_reg[10][value]__0__0\(0),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[94][11]\(10),
- Q => \[2].[2].s_reqs_reg[10][value]__0__0\(10),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[94][11]\(11),
- Q => \[2].[2].s_reqs_reg[10][value]__0__0\(11),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[94][11]\(1),
- Q => \[2].[2].s_reqs_reg[10][value]__0__0\(1),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[94][11]\(2),
- Q => \[2].[2].s_reqs_reg[10][value]__0__0\(2),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[94][11]\(3),
- Q => \[2].[2].s_reqs_reg[10][value]__0__0\(3),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[94][11]\(4),
- Q => \[2].[2].s_reqs_reg[10][value]__0__0\(4),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[94][11]\(5),
- Q => \[2].[2].s_reqs_reg[10][value]__0__0\(5),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[94][11]\(6),
- Q => \[2].[2].s_reqs_reg[10][value]__0__0\(6),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[94][11]\(7),
- Q => \[2].[2].s_reqs_reg[10][value]__0__0\(7),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[94][11]\(8),
- Q => \[2].[2].s_reqs_reg[10][value]__0__0\(8),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[94][11]\(9),
- Q => \[2].[2].s_reqs_reg[10][value]__0__0\(9),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[95][11]\(0),
- Q => \[2].[3].s_reqs_reg[11][value]__0__0\(0),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[95][11]\(10),
- Q => \[2].[3].s_reqs_reg[11][value]__0__0\(10),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[95][11]\(11),
- Q => \[2].[3].s_reqs_reg[11][value]__0__0\(11),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[95][11]\(1),
- Q => \[2].[3].s_reqs_reg[11][value]__0__0\(1),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[95][11]\(2),
- Q => \[2].[3].s_reqs_reg[11][value]__0__0\(2),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[95][11]\(3),
- Q => \[2].[3].s_reqs_reg[11][value]__0__0\(3),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[95][11]\(4),
- Q => \[2].[3].s_reqs_reg[11][value]__0__0\(4),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[95][11]\(5),
- Q => \[2].[3].s_reqs_reg[11][value]__0__0\(5),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[95][11]\(6),
- Q => \[2].[3].s_reqs_reg[11][value]__0__0\(6),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[95][11]\(7),
- Q => \[2].[3].s_reqs_reg[11][value]__0__0\(7),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[95][11]\(8),
- Q => \[2].[3].s_reqs_reg[11][value]__0__0\(8),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[95][11]\(9),
- Q => \[2].[3].s_reqs_reg[11][value]__0__0\(9),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[96][11]\(0),
- Q => \[3].[0].s_reqs_reg[12][value]__0__0\(0),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[96][11]\(10),
- Q => \[3].[0].s_reqs_reg[12][value]__0__0\(10),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[96][11]\(11),
- Q => \[3].[0].s_reqs_reg[12][value]__0__0\(11),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[96][11]\(1),
- Q => \[3].[0].s_reqs_reg[12][value]__0__0\(1),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[96][11]\(2),
- Q => \[3].[0].s_reqs_reg[12][value]__0__0\(2),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[96][11]\(3),
- Q => \[3].[0].s_reqs_reg[12][value]__0__0\(3),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[96][11]\(4),
- Q => \[3].[0].s_reqs_reg[12][value]__0__0\(4),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[96][11]\(5),
- Q => \[3].[0].s_reqs_reg[12][value]__0__0\(5),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[96][11]\(6),
- Q => \[3].[0].s_reqs_reg[12][value]__0__0\(6),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[96][11]\(7),
- Q => \[3].[0].s_reqs_reg[12][value]__0__0\(7),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[96][11]\(8),
- Q => \[3].[0].s_reqs_reg[12][value]__0__0\(8),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[96][11]\(9),
- Q => \[3].[0].s_reqs_reg[12][value]__0__0\(9),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[97][11]\(0),
- Q => \[3].[1].s_reqs_reg[13][value]__0__0\(0),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[97][11]\(10),
- Q => \[3].[1].s_reqs_reg[13][value]__0__0\(10),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[97][11]\(11),
- Q => \[3].[1].s_reqs_reg[13][value]__0__0\(11),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[97][11]\(1),
- Q => \[3].[1].s_reqs_reg[13][value]__0__0\(1),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[97][11]\(2),
- Q => \[3].[1].s_reqs_reg[13][value]__0__0\(2),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[97][11]\(3),
- Q => \[3].[1].s_reqs_reg[13][value]__0__0\(3),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[97][11]\(4),
- Q => \[3].[1].s_reqs_reg[13][value]__0__0\(4),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[97][11]\(5),
- Q => \[3].[1].s_reqs_reg[13][value]__0__0\(5),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[97][11]\(6),
- Q => \[3].[1].s_reqs_reg[13][value]__0__0\(6),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[97][11]\(7),
- Q => \[3].[1].s_reqs_reg[13][value]__0__0\(7),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[97][11]\(8),
- Q => \[3].[1].s_reqs_reg[13][value]__0__0\(8),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[97][11]\(9),
- Q => \[3].[1].s_reqs_reg[13][value]__0__0\(9),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[98][11]\(0),
- Q => \[3].[2].s_reqs_reg[14][value]__0__0\(0),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[98][11]\(10),
- Q => \[3].[2].s_reqs_reg[14][value]__0__0\(10),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[98][11]\(11),
- Q => \[3].[2].s_reqs_reg[14][value]__0__0\(11),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[98][11]\(1),
- Q => \[3].[2].s_reqs_reg[14][value]__0__0\(1),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[98][11]\(2),
- Q => \[3].[2].s_reqs_reg[14][value]__0__0\(2),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[98][11]\(3),
- Q => \[3].[2].s_reqs_reg[14][value]__0__0\(3),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[98][11]\(4),
- Q => \[3].[2].s_reqs_reg[14][value]__0__0\(4),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[98][11]\(5),
- Q => \[3].[2].s_reqs_reg[14][value]__0__0\(5),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[98][11]\(6),
- Q => \[3].[2].s_reqs_reg[14][value]__0__0\(6),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[98][11]\(7),
- Q => \[3].[2].s_reqs_reg[14][value]__0__0\(7),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[98][11]\(8),
- Q => \[3].[2].s_reqs_reg[14][value]__0__0\(8),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[98][11]\(9),
- Q => \[3].[2].s_reqs_reg[14][value]__0__0\(9),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[99][11]\(0),
- Q => \[3].[3].s_reqs_reg[15][value]__0__0\(0),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[99][11]\(10),
- Q => \[3].[3].s_reqs_reg[15][value]__0__0\(10),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[99][11]\(11),
- Q => \[3].[3].s_reqs_reg[15][value]__0__0\(11),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[99][11]\(1),
- Q => \[3].[3].s_reqs_reg[15][value]__0__0\(1),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[99][11]\(2),
- Q => \[3].[3].s_reqs_reg[15][value]__0__0\(2),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[99][11]\(3),
- Q => \[3].[3].s_reqs_reg[15][value]__0__0\(3),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[99][11]\(4),
- Q => \[3].[3].s_reqs_reg[15][value]__0__0\(4),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[99][11]\(5),
- Q => \[3].[3].s_reqs_reg[15][value]__0__0\(5),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[99][11]\(6),
- Q => \[3].[3].s_reqs_reg[15][value]__0__0\(6),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[99][11]\(7),
- Q => \[3].[3].s_reqs_reg[15][value]__0__0\(7),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[99][11]\(8),
- Q => \[3].[3].s_reqs_reg[15][value]__0__0\(8),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[99][11]\(9),
- Q => \[3].[3].s_reqs_reg[15][value]__0__0\(9),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[100][11]\(0),
- Q => \[4].[0].s_reqs_reg[16][value]__0__0\(0),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[100][11]\(10),
- Q => \[4].[0].s_reqs_reg[16][value]__0__0\(10),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[100][11]\(11),
- Q => \[4].[0].s_reqs_reg[16][value]__0__0\(11),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[100][11]\(1),
- Q => \[4].[0].s_reqs_reg[16][value]__0__0\(1),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[100][11]\(2),
- Q => \[4].[0].s_reqs_reg[16][value]__0__0\(2),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[100][11]\(3),
- Q => \[4].[0].s_reqs_reg[16][value]__0__0\(3),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[100][11]\(4),
- Q => \[4].[0].s_reqs_reg[16][value]__0__0\(4),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[100][11]\(5),
- Q => \[4].[0].s_reqs_reg[16][value]__0__0\(5),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[100][11]\(6),
- Q => \[4].[0].s_reqs_reg[16][value]__0__0\(6),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[100][11]\(7),
- Q => \[4].[0].s_reqs_reg[16][value]__0__0\(7),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[100][11]\(8),
- Q => \[4].[0].s_reqs_reg[16][value]__0__0\(8),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[100][11]\(9),
- Q => \[4].[0].s_reqs_reg[16][value]__0__0\(9),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[101][11]\(0),
- Q => \[4].[1].s_reqs_reg[17][value]__0__0\(0),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[101][11]\(10),
- Q => \[4].[1].s_reqs_reg[17][value]__0__0\(10),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[101][11]\(11),
- Q => \[4].[1].s_reqs_reg[17][value]__0__0\(11),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[101][11]\(1),
- Q => \[4].[1].s_reqs_reg[17][value]__0__0\(1),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[101][11]\(2),
- Q => \[4].[1].s_reqs_reg[17][value]__0__0\(2),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[101][11]\(3),
- Q => \[4].[1].s_reqs_reg[17][value]__0__0\(3),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[101][11]\(4),
- Q => \[4].[1].s_reqs_reg[17][value]__0__0\(4),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[101][11]\(5),
- Q => \[4].[1].s_reqs_reg[17][value]__0__0\(5),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[101][11]\(6),
- Q => \[4].[1].s_reqs_reg[17][value]__0__0\(6),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[101][11]\(7),
- Q => \[4].[1].s_reqs_reg[17][value]__0__0\(7),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[101][11]\(8),
- Q => \[4].[1].s_reqs_reg[17][value]__0__0\(8),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[101][11]\(9),
- Q => \[4].[1].s_reqs_reg[17][value]__0__0\(9),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[102][11]\(0),
- Q => \[4].[2].s_reqs_reg[18][value]__0__0\(0),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[102][11]\(10),
- Q => \[4].[2].s_reqs_reg[18][value]__0__0\(10),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[102][11]\(11),
- Q => \[4].[2].s_reqs_reg[18][value]__0__0\(11),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[102][11]\(1),
- Q => \[4].[2].s_reqs_reg[18][value]__0__0\(1),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[102][11]\(2),
- Q => \[4].[2].s_reqs_reg[18][value]__0__0\(2),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[102][11]\(3),
- Q => \[4].[2].s_reqs_reg[18][value]__0__0\(3),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[102][11]\(4),
- Q => \[4].[2].s_reqs_reg[18][value]__0__0\(4),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[102][11]\(5),
- Q => \[4].[2].s_reqs_reg[18][value]__0__0\(5),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[102][11]\(6),
- Q => \[4].[2].s_reqs_reg[18][value]__0__0\(6),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[102][11]\(7),
- Q => \[4].[2].s_reqs_reg[18][value]__0__0\(7),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[102][11]\(8),
- Q => \[4].[2].s_reqs_reg[18][value]__0__0\(8),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[102][11]\(9),
- Q => \[4].[2].s_reqs_reg[18][value]__0__0\(9),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[103][11]\(0),
- Q => \[4].[3].s_reqs_reg[19][value]__0__0\(0),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[103][11]\(10),
- Q => \[4].[3].s_reqs_reg[19][value]__0__0\(10),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[103][11]\(11),
- Q => \[4].[3].s_reqs_reg[19][value]__0__0\(11),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[103][11]\(1),
- Q => \[4].[3].s_reqs_reg[19][value]__0__0\(1),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[103][11]\(2),
- Q => \[4].[3].s_reqs_reg[19][value]__0__0\(2),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[103][11]\(3),
- Q => \[4].[3].s_reqs_reg[19][value]__0__0\(3),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[103][11]\(4),
- Q => \[4].[3].s_reqs_reg[19][value]__0__0\(4),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[103][11]\(5),
- Q => \[4].[3].s_reqs_reg[19][value]__0__0\(5),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[103][11]\(6),
- Q => \[4].[3].s_reqs_reg[19][value]__0__0\(6),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[103][11]\(7),
- Q => \[4].[3].s_reqs_reg[19][value]__0__0\(7),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[103][11]\(8),
- Q => \[4].[3].s_reqs_reg[19][value]__0__0\(8),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[103][11]\(9),
- Q => \[4].[3].s_reqs_reg[19][value]__0__0\(9),
- R => '0'
- );
-cmp_spi: entity work.system_design_fasec_hwtest_0_0_spi_transceiver
- port map (
- D(0) => D(0),
- E(0) => cmp_spi_n_0,
- Q(0) => \s_counter_reg[2]\(0),
- \[0].[2].s_reqs_reg[2][changed]\ => \[0].[2].s_reqs_reg[2][changed_n_0_]\,
- \[0].[2].s_reqs_reg[2][changed]_0\ => \s_state[1]_i_2__0_n_0\,
- \[0].[3].s_reqs_reg[3][changed]\ => \s_state[1]_i_3__0_n_0\,
- ch_address(1 downto 0) => ch_address(1 downto 0),
- \dac_ch_o_reg[0][31]\(31 downto 0) => rx_data_o(31 downto 0),
- \data_rw_o_reg[79][1]\ => \v_ch_address[1]_i_3__0_n_0\,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_spi_cs_n => s_spi_cs_n,
- s_spi_mosi => s_spi_mosi,
- s_start_reg => \^s_start\,
- \s_state_reg[0]\ => cmp_spi_n_3,
- \s_state_reg[0]_0\ => \^dac_ch_o_reg[0][0]_1\,
- \s_state_reg[1]\ => cmp_spi_n_4,
- \s_state_reg[1]_0\ => \^dac_ch_o_reg[0][0]_0\,
- \s_tx_data_reg[113]\(61) => \s_tx_data_reg_n_0_[113]\,
- \s_tx_data_reg[113]\(60) => \s_tx_data_reg_n_0_[112]\,
- \s_tx_data_reg[113]\(59) => \s_tx_data_reg_n_0_[111]\,
- \s_tx_data_reg[113]\(58) => \s_tx_data_reg_n_0_[110]\,
- \s_tx_data_reg[113]\(57) => \s_tx_data_reg_n_0_[109]\,
- \s_tx_data_reg[113]\(56) => \s_tx_data_reg_n_0_[108]\,
- \s_tx_data_reg[113]\(55) => \s_tx_data_reg_n_0_[107]\,
- \s_tx_data_reg[113]\(54) => \s_tx_data_reg_n_0_[106]\,
- \s_tx_data_reg[113]\(53) => \s_tx_data_reg_n_0_[105]\,
- \s_tx_data_reg[113]\(52) => \s_tx_data_reg_n_0_[104]\,
- \s_tx_data_reg[113]\(51) => \s_tx_data_reg_n_0_[103]\,
- \s_tx_data_reg[113]\(50) => \s_tx_data_reg_n_0_[102]\,
- \s_tx_data_reg[113]\(49) => \s_tx_data_reg_n_0_[101]\,
- \s_tx_data_reg[113]\(48) => \s_tx_data_reg_n_0_[100]\,
- \s_tx_data_reg[113]\(47) => \s_tx_data_reg_n_0_[87]\,
- \s_tx_data_reg[113]\(46) => \s_tx_data_reg_n_0_[86]\,
- \s_tx_data_reg[113]\(45) => \s_tx_data_reg_n_0_[85]\,
- \s_tx_data_reg[113]\(44) => \s_tx_data_reg_n_0_[84]\,
- \s_tx_data_reg[113]\(43) => \s_tx_data_reg_n_0_[83]\,
- \s_tx_data_reg[113]\(42) => \s_tx_data_reg_n_0_[82]\,
- \s_tx_data_reg[113]\(41) => \s_tx_data_reg_n_0_[81]\,
- \s_tx_data_reg[113]\(40) => \s_tx_data_reg_n_0_[80]\,
- \s_tx_data_reg[113]\(39) => \s_tx_data_reg_n_0_[79]\,
- \s_tx_data_reg[113]\(38) => \s_tx_data_reg_n_0_[78]\,
- \s_tx_data_reg[113]\(37) => \s_tx_data_reg_n_0_[77]\,
- \s_tx_data_reg[113]\(36) => \s_tx_data_reg_n_0_[76]\,
- \s_tx_data_reg[113]\(35) => \s_tx_data_reg_n_0_[63]\,
- \s_tx_data_reg[113]\(34) => \s_tx_data_reg_n_0_[62]\,
- \s_tx_data_reg[113]\(33) => \s_tx_data_reg_n_0_[61]\,
- \s_tx_data_reg[113]\(32) => \s_tx_data_reg_n_0_[60]\,
- \s_tx_data_reg[113]\(31) => \s_tx_data_reg_n_0_[59]\,
- \s_tx_data_reg[113]\(30) => \s_tx_data_reg_n_0_[58]\,
- \s_tx_data_reg[113]\(29) => \s_tx_data_reg_n_0_[57]\,
- \s_tx_data_reg[113]\(28) => \s_tx_data_reg_n_0_[56]\,
- \s_tx_data_reg[113]\(27) => \s_tx_data_reg_n_0_[55]\,
- \s_tx_data_reg[113]\(26) => \s_tx_data_reg_n_0_[54]\,
- \s_tx_data_reg[113]\(25) => \s_tx_data_reg_n_0_[53]\,
- \s_tx_data_reg[113]\(24) => \s_tx_data_reg_n_0_[52]\,
- \s_tx_data_reg[113]\(23) => \s_tx_data_reg_n_0_[39]\,
- \s_tx_data_reg[113]\(22) => \s_tx_data_reg_n_0_[38]\,
- \s_tx_data_reg[113]\(21) => \s_tx_data_reg_n_0_[37]\,
- \s_tx_data_reg[113]\(20) => \s_tx_data_reg_n_0_[36]\,
- \s_tx_data_reg[113]\(19) => \s_tx_data_reg_n_0_[35]\,
- \s_tx_data_reg[113]\(18) => \s_tx_data_reg_n_0_[34]\,
- \s_tx_data_reg[113]\(17) => \s_tx_data_reg_n_0_[33]\,
- \s_tx_data_reg[113]\(16) => \s_tx_data_reg_n_0_[32]\,
- \s_tx_data_reg[113]\(15) => \s_tx_data_reg_n_0_[31]\,
- \s_tx_data_reg[113]\(14) => \s_tx_data_reg_n_0_[30]\,
- \s_tx_data_reg[113]\(13) => \s_tx_data_reg_n_0_[29]\,
- \s_tx_data_reg[113]\(12) => \s_tx_data_reg_n_0_[28]\,
- \s_tx_data_reg[113]\(11) => \s_tx_data_reg_n_0_[15]\,
- \s_tx_data_reg[113]\(10) => \s_tx_data_reg_n_0_[14]\,
- \s_tx_data_reg[113]\(9) => \s_tx_data_reg_n_0_[13]\,
- \s_tx_data_reg[113]\(8) => \s_tx_data_reg_n_0_[12]\,
- \s_tx_data_reg[113]\(7) => \s_tx_data_reg_n_0_[11]\,
- \s_tx_data_reg[113]\(6) => \s_tx_data_reg_n_0_[10]\,
- \s_tx_data_reg[113]\(5) => \s_tx_data_reg_n_0_[9]\,
- \s_tx_data_reg[113]\(4) => \s_tx_data_reg_n_0_[8]\,
- \s_tx_data_reg[113]\(3) => \s_tx_data_reg_n_0_[7]\,
- \s_tx_data_reg[113]\(2) => \s_tx_data_reg_n_0_[6]\,
- \s_tx_data_reg[113]\(1) => \s_tx_data_reg_n_0_[5]\,
- \s_tx_data_reg[113]\(0) => \s_tx_data_reg_n_0_[4]\,
- \v_ch_address_reg[0]\ => cmp_spi_n_1,
- \v_ch_address_reg[0]_0\ => \dac_ch_o[0][31]_i_2__0_n_0\,
- \v_ch_address_reg[1]\ => cmp_spi_n_2
- );
-\dac_ch_o[0][31]_i_2__0\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"7"
- )
- port map (
- I0 => ch_address(0),
- I1 => ch_address(1),
- O => \dac_ch_o[0][31]_i_2__0_n_0\
- );
-\dac_ch_o_reg[0][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(0),
- Q => \axi_rdata_reg[31]\(0),
- R => '0'
- );
-\dac_ch_o_reg[0][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(10),
- Q => \axi_rdata_reg[31]\(10),
- R => '0'
- );
-\dac_ch_o_reg[0][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(11),
- Q => \axi_rdata_reg[31]\(11),
- R => '0'
- );
-\dac_ch_o_reg[0][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(12),
- Q => \axi_rdata_reg[31]\(12),
- R => '0'
- );
-\dac_ch_o_reg[0][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(13),
- Q => \axi_rdata_reg[31]\(13),
- R => '0'
- );
-\dac_ch_o_reg[0][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(14),
- Q => \axi_rdata_reg[31]\(14),
- R => '0'
- );
-\dac_ch_o_reg[0][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(15),
- Q => \axi_rdata_reg[31]\(15),
- R => '0'
- );
-\dac_ch_o_reg[0][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(16),
- Q => \axi_rdata_reg[31]\(16),
- R => '0'
- );
-\dac_ch_o_reg[0][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(17),
- Q => \axi_rdata_reg[31]\(17),
- R => '0'
- );
-\dac_ch_o_reg[0][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(18),
- Q => \axi_rdata_reg[31]\(18),
- R => '0'
- );
-\dac_ch_o_reg[0][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(19),
- Q => \axi_rdata_reg[31]\(19),
- R => '0'
- );
-\dac_ch_o_reg[0][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(1),
- Q => \axi_rdata_reg[31]\(1),
- R => '0'
- );
-\dac_ch_o_reg[0][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(20),
- Q => \axi_rdata_reg[31]\(20),
- R => '0'
- );
-\dac_ch_o_reg[0][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(21),
- Q => \axi_rdata_reg[31]\(21),
- R => '0'
- );
-\dac_ch_o_reg[0][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(22),
- Q => \axi_rdata_reg[31]\(22),
- R => '0'
- );
-\dac_ch_o_reg[0][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(23),
- Q => \axi_rdata_reg[31]\(23),
- R => '0'
- );
-\dac_ch_o_reg[0][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(24),
- Q => \axi_rdata_reg[31]\(24),
- R => '0'
- );
-\dac_ch_o_reg[0][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(25),
- Q => \axi_rdata_reg[31]\(25),
- R => '0'
- );
-\dac_ch_o_reg[0][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(26),
- Q => \axi_rdata_reg[31]\(26),
- R => '0'
- );
-\dac_ch_o_reg[0][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(27),
- Q => \axi_rdata_reg[31]\(27),
- R => '0'
- );
-\dac_ch_o_reg[0][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(28),
- Q => \axi_rdata_reg[31]\(28),
- R => '0'
- );
-\dac_ch_o_reg[0][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(29),
- Q => \axi_rdata_reg[31]\(29),
- R => '0'
- );
-\dac_ch_o_reg[0][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(2),
- Q => \axi_rdata_reg[31]\(2),
- R => '0'
- );
-\dac_ch_o_reg[0][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(30),
- Q => \axi_rdata_reg[31]\(30),
- R => '0'
- );
-\dac_ch_o_reg[0][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(31),
- Q => \axi_rdata_reg[31]\(31),
- R => '0'
- );
-\dac_ch_o_reg[0][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(3),
- Q => \axi_rdata_reg[31]\(3),
- R => '0'
- );
-\dac_ch_o_reg[0][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(4),
- Q => \axi_rdata_reg[31]\(4),
- R => '0'
- );
-\dac_ch_o_reg[0][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(5),
- Q => \axi_rdata_reg[31]\(5),
- R => '0'
- );
-\dac_ch_o_reg[0][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(6),
- Q => \axi_rdata_reg[31]\(6),
- R => '0'
- );
-\dac_ch_o_reg[0][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(7),
- Q => \axi_rdata_reg[31]\(7),
- R => '0'
- );
-\dac_ch_o_reg[0][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(8),
- Q => \axi_rdata_reg[31]\(8),
- R => '0'
- );
-\dac_ch_o_reg[0][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(9),
- Q => \axi_rdata_reg[31]\(9),
- R => '0'
- );
-\s_flag_reset[0]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFF70004"
- )
- port map (
- I0 => \^dac_ch_o_reg[0][0]_1\,
- I1 => \^dac_ch_o_reg[0][0]_0\,
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \s_flag_reset_reg_n_0_[0]\,
- O => \s_flag_reset[0]_i_1__0_n_0\
- );
-\s_flag_reset[1]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"DFFF1000"
- )
- port map (
- I0 => \^dac_ch_o_reg[0][0]_1\,
- I1 => ch_address(1),
- I2 => \^dac_ch_o_reg[0][0]_0\,
- I3 => ch_address(0),
- I4 => p_2_in,
- O => \s_flag_reset[1]_i_1__0_n_0\
- );
-\s_flag_reset[2]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FF7F0040"
- )
- port map (
- I0 => \^dac_ch_o_reg[0][0]_1\,
- I1 => \^dac_ch_o_reg[0][0]_0\,
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => p_1_in,
- O => \s_flag_reset[2]_i_1__0_n_0\
- );
-\s_flag_reset[3]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"7FFF4000"
- )
- port map (
- I0 => \^dac_ch_o_reg[0][0]_1\,
- I1 => \^dac_ch_o_reg[0][0]_0\,
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => p_0_in,
- O => \s_flag_reset[3]_i_1__0_n_0\
- );
-\s_flag_reset_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_flag_reset[0]_i_1__0_n_0\,
- Q => \s_flag_reset_reg_n_0_[0]\,
- R => rst_i
- );
-\s_flag_reset_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_flag_reset[1]_i_1__0_n_0\,
- Q => p_2_in,
- R => rst_i
- );
-\s_flag_reset_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_flag_reset[2]_i_1__0_n_0\,
- Q => p_1_in,
- R => rst_i
- );
-\s_flag_reset_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_flag_reset[3]_i_1__0_n_0\,
- Q => p_0_in,
- R => rst_i
- );
-s_start_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_start_reg_0,
- Q => \^s_start\,
- R => rst_i
- );
-\s_state[1]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0C00080808080808"
- )
- port map (
- I0 => \[0].[2].s_reqs_reg[2][changed_n_0_]\,
- I1 => \^dac_ch_o_reg[0][0]_1\,
- I2 => \^dac_ch_o_reg[0][0]_0\,
- I3 => \[1].[3].s_reqs_reg[7][changed]__1\,
- I4 => ch_address(1),
- I5 => ch_address(0),
- O => \s_state[1]_i_2__0_n_0\
- );
-\s_state[1]_i_3__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000FFFE00000000"
- )
- port map (
- I0 => \[0].[3].s_reqs_reg[3][changed_n_0_]\,
- I1 => \[1].[0].s_reqs_reg[4][changed]__1\,
- I2 => \data_rw_o_reg[79][2]\(0),
- I3 => \s_state[1]_i_5__0_n_0\,
- I4 => \^dac_ch_o_reg[0][0]_0\,
- I5 => \^dac_ch_o_reg[0][0]_1\,
- O => \s_state[1]_i_3__0_n_0\
- );
-\s_state[1]_i_5__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFE2F0F0FFE2"
- )
- port map (
- I0 => \[0].[0].s_reqs_reg[0][changed_n_0_]\,
- I1 => ch_address(0),
- I2 => \[1].[1].s_reqs_reg[5][changed]__1\,
- I3 => \[0].[1].s_reqs_reg[1][changed_n_0_]\,
- I4 => ch_address(1),
- I5 => \[1].[2].s_reqs_reg[6][changed]__1\,
- O => \s_state[1]_i_5__0_n_0\
- );
-\s_state_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => cmp_spi_n_3,
- Q => \^dac_ch_o_reg[0][0]_1\,
- R => rst_i
- );
-\s_state_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => cmp_spi_n_4,
- Q => \^dac_ch_o_reg[0][0]_0\,
- R => rst_i
- );
-\s_tx_data[100]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(0),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0__0\(0),
- I5 => \s_tx_data[100]_i_2__0_n_0\,
- O => \s_tx_data[100]_i_1__0_n_0\
- );
-\s_tx_data[100]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0__0\(0),
- I1 => \[4].[1].s_reqs_reg[17][value]__0__0\(0),
- I2 => \[4].[2].s_reqs_reg[18][value]__0__0\(0),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[100]_i_2__0_n_0\
- );
-\s_tx_data[101]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(1),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0__0\(1),
- I5 => \s_tx_data[101]_i_2__0_n_0\,
- O => \s_tx_data[101]_i_1__0_n_0\
- );
-\s_tx_data[101]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0__0\(1),
- I1 => \[4].[1].s_reqs_reg[17][value]__0__0\(1),
- I2 => \[4].[2].s_reqs_reg[18][value]__0__0\(1),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[101]_i_2__0_n_0\
- );
-\s_tx_data[102]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(2),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0__0\(2),
- I5 => \s_tx_data[102]_i_2__0_n_0\,
- O => \s_tx_data[102]_i_1__0_n_0\
- );
-\s_tx_data[102]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0__0\(2),
- I1 => \[4].[1].s_reqs_reg[17][value]__0__0\(2),
- I2 => \[4].[2].s_reqs_reg[18][value]__0__0\(2),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[102]_i_2__0_n_0\
- );
-\s_tx_data[103]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(3),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0__0\(3),
- I5 => \s_tx_data[103]_i_2__0_n_0\,
- O => \s_tx_data[103]_i_1__0_n_0\
- );
-\s_tx_data[103]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0__0\(3),
- I1 => \[4].[1].s_reqs_reg[17][value]__0__0\(3),
- I2 => \[4].[2].s_reqs_reg[18][value]__0__0\(3),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[103]_i_2__0_n_0\
- );
-\s_tx_data[104]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(4),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0__0\(4),
- I5 => \s_tx_data[104]_i_2__0_n_0\,
- O => \s_tx_data[104]_i_1__0_n_0\
- );
-\s_tx_data[104]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0__0\(4),
- I1 => \[4].[1].s_reqs_reg[17][value]__0__0\(4),
- I2 => \[4].[2].s_reqs_reg[18][value]__0__0\(4),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[104]_i_2__0_n_0\
- );
-\s_tx_data[105]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(5),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0__0\(5),
- I5 => \s_tx_data[105]_i_2__0_n_0\,
- O => \s_tx_data[105]_i_1__0_n_0\
- );
-\s_tx_data[105]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0__0\(5),
- I1 => \[4].[1].s_reqs_reg[17][value]__0__0\(5),
- I2 => \[4].[2].s_reqs_reg[18][value]__0__0\(5),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[105]_i_2__0_n_0\
- );
-\s_tx_data[106]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(6),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0__0\(6),
- I5 => \s_tx_data[106]_i_2__0_n_0\,
- O => \s_tx_data[106]_i_1__0_n_0\
- );
-\s_tx_data[106]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0__0\(6),
- I1 => \[4].[1].s_reqs_reg[17][value]__0__0\(6),
- I2 => \[4].[2].s_reqs_reg[18][value]__0__0\(6),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[106]_i_2__0_n_0\
- );
-\s_tx_data[107]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(7),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0__0\(7),
- I5 => \s_tx_data[107]_i_2__0_n_0\,
- O => \s_tx_data[107]_i_1__0_n_0\
- );
-\s_tx_data[107]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0__0\(7),
- I1 => \[4].[1].s_reqs_reg[17][value]__0__0\(7),
- I2 => \[4].[2].s_reqs_reg[18][value]__0__0\(7),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[107]_i_2__0_n_0\
- );
-\s_tx_data[108]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(8),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0__0\(8),
- I5 => \s_tx_data[108]_i_2__0_n_0\,
- O => \s_tx_data[108]_i_1__0_n_0\
- );
-\s_tx_data[108]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0__0\(8),
- I1 => \[4].[1].s_reqs_reg[17][value]__0__0\(8),
- I2 => \[4].[2].s_reqs_reg[18][value]__0__0\(8),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[108]_i_2__0_n_0\
- );
-\s_tx_data[109]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(9),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0__0\(9),
- I5 => \s_tx_data[109]_i_2__0_n_0\,
- O => \s_tx_data[109]_i_1__0_n_0\
- );
-\s_tx_data[109]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0__0\(9),
- I1 => \[4].[1].s_reqs_reg[17][value]__0__0\(9),
- I2 => \[4].[2].s_reqs_reg[18][value]__0__0\(9),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[109]_i_2__0_n_0\
- );
-\s_tx_data[10]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(6),
- I1 => \data_rw_o_reg[79][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[10]_i_2__0_n_0\,
- O => \s_reqs[0][value]\(6)
- );
-\s_tx_data[10]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(6),
- I1 => \^s_tx_data_reg[15]_0\(6),
- I2 => \^s_tx_data_reg[15]_1\(6),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[10]_i_2__0_n_0\
- );
-\s_tx_data[110]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(10),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0__0\(10),
- I5 => \s_tx_data[110]_i_2__0_n_0\,
- O => \s_tx_data[110]_i_1__0_n_0\
- );
-\s_tx_data[110]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0__0\(10),
- I1 => \[4].[1].s_reqs_reg[17][value]__0__0\(10),
- I2 => \[4].[2].s_reqs_reg[18][value]__0__0\(10),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[110]_i_2__0_n_0\
- );
-\s_tx_data[111]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(11),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0__0\(11),
- I5 => \s_tx_data[111]_i_2__0_n_0\,
- O => \s_tx_data[111]_i_1__0_n_0\
- );
-\s_tx_data[111]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0__0\(11),
- I1 => \[4].[1].s_reqs_reg[17][value]__0__0\(11),
- I2 => \[4].[2].s_reqs_reg[18][value]__0__0\(11),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[111]_i_2__0_n_0\
- );
-\s_tx_data[113]_i_1__0\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => \^dac_ch_o_reg[0][0]_1\,
- I1 => \^dac_ch_o_reg[0][0]_0\,
- I2 => s00_axi_aresetn,
- O => \s_tx_data[113]_i_1__0_n_0\
- );
-\s_tx_data[11]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(7),
- I1 => \data_rw_o_reg[79][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[11]_i_2__0_n_0\,
- O => \s_reqs[0][value]\(7)
- );
-\s_tx_data[11]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(7),
- I1 => \^s_tx_data_reg[15]_0\(7),
- I2 => \^s_tx_data_reg[15]_1\(7),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[11]_i_2__0_n_0\
- );
-\s_tx_data[12]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(8),
- I1 => \data_rw_o_reg[79][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[12]_i_2__0_n_0\,
- O => \s_reqs[0][value]\(8)
- );
-\s_tx_data[12]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(8),
- I1 => \^s_tx_data_reg[15]_0\(8),
- I2 => \^s_tx_data_reg[15]_1\(8),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[12]_i_2__0_n_0\
- );
-\s_tx_data[13]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(9),
- I1 => \data_rw_o_reg[79][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[13]_i_2__0_n_0\,
- O => \s_reqs[0][value]\(9)
- );
-\s_tx_data[13]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(9),
- I1 => \^s_tx_data_reg[15]_0\(9),
- I2 => \^s_tx_data_reg[15]_1\(9),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[13]_i_2__0_n_0\
- );
-\s_tx_data[14]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(10),
- I1 => \data_rw_o_reg[79][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[14]_i_2__0_n_0\,
- O => \s_reqs[0][value]\(10)
- );
-\s_tx_data[14]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(10),
- I1 => \^s_tx_data_reg[15]_0\(10),
- I2 => \^s_tx_data_reg[15]_1\(10),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[14]_i_2__0_n_0\
- );
-\s_tx_data[15]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(11),
- I1 => \data_rw_o_reg[79][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[15]_i_2__0_n_0\,
- O => \s_reqs[0][value]\(11)
- );
-\s_tx_data[15]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(11),
- I1 => \^s_tx_data_reg[15]_0\(11),
- I2 => \^s_tx_data_reg[15]_1\(11),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[15]_i_2__0_n_0\
- );
-\s_tx_data[28]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(0),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(0),
- I5 => \s_tx_data[28]_i_2__0_n_0\,
- O => \s_tx_data[28]_i_1__0_n_0\
- );
-\s_tx_data[28]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(0),
- I1 => \^s_tx_data_reg[39]_2\(0),
- I2 => \^s_tx_data_reg[39]_3\(0),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[28]_i_2__0_n_0\
- );
-\s_tx_data[29]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(1),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(1),
- I5 => \s_tx_data[29]_i_2__0_n_0\,
- O => \s_tx_data[29]_i_1__0_n_0\
- );
-\s_tx_data[29]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(1),
- I1 => \^s_tx_data_reg[39]_2\(1),
- I2 => \^s_tx_data_reg[39]_3\(1),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[29]_i_2__0_n_0\
- );
-\s_tx_data[30]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(2),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(2),
- I5 => \s_tx_data[30]_i_2__0_n_0\,
- O => \s_tx_data[30]_i_1__0_n_0\
- );
-\s_tx_data[30]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(2),
- I1 => \^s_tx_data_reg[39]_2\(2),
- I2 => \^s_tx_data_reg[39]_3\(2),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[30]_i_2__0_n_0\
- );
-\s_tx_data[31]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(3),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(3),
- I5 => \s_tx_data[31]_i_2__0_n_0\,
- O => \s_tx_data[31]_i_1__0_n_0\
- );
-\s_tx_data[31]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(3),
- I1 => \^s_tx_data_reg[39]_2\(3),
- I2 => \^s_tx_data_reg[39]_3\(3),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[31]_i_2__0_n_0\
- );
-\s_tx_data[32]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(4),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(4),
- I5 => \s_tx_data[32]_i_2__0_n_0\,
- O => \s_tx_data[32]_i_1__0_n_0\
- );
-\s_tx_data[32]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(4),
- I1 => \^s_tx_data_reg[39]_2\(4),
- I2 => \^s_tx_data_reg[39]_3\(4),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[32]_i_2__0_n_0\
- );
-\s_tx_data[33]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(5),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(5),
- I5 => \s_tx_data[33]_i_2__0_n_0\,
- O => \s_tx_data[33]_i_1__0_n_0\
- );
-\s_tx_data[33]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(5),
- I1 => \^s_tx_data_reg[39]_2\(5),
- I2 => \^s_tx_data_reg[39]_3\(5),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[33]_i_2__0_n_0\
- );
-\s_tx_data[34]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(6),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(6),
- I5 => \s_tx_data[34]_i_2__0_n_0\,
- O => \s_tx_data[34]_i_1__0_n_0\
- );
-\s_tx_data[34]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(6),
- I1 => \^s_tx_data_reg[39]_2\(6),
- I2 => \^s_tx_data_reg[39]_3\(6),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[34]_i_2__0_n_0\
- );
-\s_tx_data[35]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(7),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(7),
- I5 => \s_tx_data[35]_i_2__0_n_0\,
- O => \s_tx_data[35]_i_1__0_n_0\
- );
-\s_tx_data[35]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(7),
- I1 => \^s_tx_data_reg[39]_2\(7),
- I2 => \^s_tx_data_reg[39]_3\(7),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[35]_i_2__0_n_0\
- );
-\s_tx_data[36]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(8),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(8),
- I5 => \s_tx_data[36]_i_2__0_n_0\,
- O => \s_tx_data[36]_i_1__0_n_0\
- );
-\s_tx_data[36]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(8),
- I1 => \^s_tx_data_reg[39]_2\(8),
- I2 => \^s_tx_data_reg[39]_3\(8),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[36]_i_2__0_n_0\
- );
-\s_tx_data[37]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(9),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(9),
- I5 => \s_tx_data[37]_i_2__0_n_0\,
- O => \s_tx_data[37]_i_1__0_n_0\
- );
-\s_tx_data[37]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(9),
- I1 => \^s_tx_data_reg[39]_2\(9),
- I2 => \^s_tx_data_reg[39]_3\(9),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[37]_i_2__0_n_0\
- );
-\s_tx_data[38]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(10),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(10),
- I5 => \s_tx_data[38]_i_2__0_n_0\,
- O => \s_tx_data[38]_i_1__0_n_0\
- );
-\s_tx_data[38]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(10),
- I1 => \^s_tx_data_reg[39]_2\(10),
- I2 => \^s_tx_data_reg[39]_3\(10),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[38]_i_2__0_n_0\
- );
-\s_tx_data[39]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(11),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(11),
- I5 => \s_tx_data[39]_i_2__0_n_0\,
- O => \s_tx_data[39]_i_1__0_n_0\
- );
-\s_tx_data[39]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(11),
- I1 => \^s_tx_data_reg[39]_2\(11),
- I2 => \^s_tx_data_reg[39]_3\(11),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[39]_i_2__0_n_0\
- );
-\s_tx_data[4]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(0),
- I1 => \data_rw_o_reg[79][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[4]_i_2__0_n_0\,
- O => \s_reqs[0][value]\(0)
- );
-\s_tx_data[4]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(0),
- I1 => \^s_tx_data_reg[15]_0\(0),
- I2 => \^s_tx_data_reg[15]_1\(0),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[4]_i_2__0_n_0\
- );
-\s_tx_data[52]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(0),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0__0\(0),
- I5 => \s_tx_data[52]_i_2__0_n_0\,
- O => \s_tx_data[52]_i_1__0_n_0\
- );
-\s_tx_data[52]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0__0\(0),
- I1 => \[2].[1].s_reqs_reg[9][value]__0__0\(0),
- I2 => \[2].[2].s_reqs_reg[10][value]__0__0\(0),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[52]_i_2__0_n_0\
- );
-\s_tx_data[53]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(1),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0__0\(1),
- I5 => \s_tx_data[53]_i_2__0_n_0\,
- O => \s_tx_data[53]_i_1__0_n_0\
- );
-\s_tx_data[53]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0__0\(1),
- I1 => \[2].[1].s_reqs_reg[9][value]__0__0\(1),
- I2 => \[2].[2].s_reqs_reg[10][value]__0__0\(1),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[53]_i_2__0_n_0\
- );
-\s_tx_data[54]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(2),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0__0\(2),
- I5 => \s_tx_data[54]_i_2__0_n_0\,
- O => \s_tx_data[54]_i_1__0_n_0\
- );
-\s_tx_data[54]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0__0\(2),
- I1 => \[2].[1].s_reqs_reg[9][value]__0__0\(2),
- I2 => \[2].[2].s_reqs_reg[10][value]__0__0\(2),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[54]_i_2__0_n_0\
- );
-\s_tx_data[55]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(3),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0__0\(3),
- I5 => \s_tx_data[55]_i_2__0_n_0\,
- O => \s_tx_data[55]_i_1__0_n_0\
- );
-\s_tx_data[55]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0__0\(3),
- I1 => \[2].[1].s_reqs_reg[9][value]__0__0\(3),
- I2 => \[2].[2].s_reqs_reg[10][value]__0__0\(3),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[55]_i_2__0_n_0\
- );
-\s_tx_data[56]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(4),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0__0\(4),
- I5 => \s_tx_data[56]_i_2__0_n_0\,
- O => \s_tx_data[56]_i_1__0_n_0\
- );
-\s_tx_data[56]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0__0\(4),
- I1 => \[2].[1].s_reqs_reg[9][value]__0__0\(4),
- I2 => \[2].[2].s_reqs_reg[10][value]__0__0\(4),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[56]_i_2__0_n_0\
- );
-\s_tx_data[57]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(5),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0__0\(5),
- I5 => \s_tx_data[57]_i_2__0_n_0\,
- O => \s_tx_data[57]_i_1__0_n_0\
- );
-\s_tx_data[57]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0__0\(5),
- I1 => \[2].[1].s_reqs_reg[9][value]__0__0\(5),
- I2 => \[2].[2].s_reqs_reg[10][value]__0__0\(5),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[57]_i_2__0_n_0\
- );
-\s_tx_data[58]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(6),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0__0\(6),
- I5 => \s_tx_data[58]_i_2__0_n_0\,
- O => \s_tx_data[58]_i_1__0_n_0\
- );
-\s_tx_data[58]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0__0\(6),
- I1 => \[2].[1].s_reqs_reg[9][value]__0__0\(6),
- I2 => \[2].[2].s_reqs_reg[10][value]__0__0\(6),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[58]_i_2__0_n_0\
- );
-\s_tx_data[59]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(7),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0__0\(7),
- I5 => \s_tx_data[59]_i_2__0_n_0\,
- O => \s_tx_data[59]_i_1__0_n_0\
- );
-\s_tx_data[59]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0__0\(7),
- I1 => \[2].[1].s_reqs_reg[9][value]__0__0\(7),
- I2 => \[2].[2].s_reqs_reg[10][value]__0__0\(7),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[59]_i_2__0_n_0\
- );
-\s_tx_data[5]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(1),
- I1 => \data_rw_o_reg[79][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[5]_i_2__0_n_0\,
- O => \s_reqs[0][value]\(1)
- );
-\s_tx_data[5]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(1),
- I1 => \^s_tx_data_reg[15]_0\(1),
- I2 => \^s_tx_data_reg[15]_1\(1),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[5]_i_2__0_n_0\
- );
-\s_tx_data[60]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(8),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0__0\(8),
- I5 => \s_tx_data[60]_i_2__0_n_0\,
- O => \s_tx_data[60]_i_1__0_n_0\
- );
-\s_tx_data[60]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0__0\(8),
- I1 => \[2].[1].s_reqs_reg[9][value]__0__0\(8),
- I2 => \[2].[2].s_reqs_reg[10][value]__0__0\(8),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[60]_i_2__0_n_0\
- );
-\s_tx_data[61]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(9),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0__0\(9),
- I5 => \s_tx_data[61]_i_2__0_n_0\,
- O => \s_tx_data[61]_i_1__0_n_0\
- );
-\s_tx_data[61]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0__0\(9),
- I1 => \[2].[1].s_reqs_reg[9][value]__0__0\(9),
- I2 => \[2].[2].s_reqs_reg[10][value]__0__0\(9),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[61]_i_2__0_n_0\
- );
-\s_tx_data[62]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(10),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0__0\(10),
- I5 => \s_tx_data[62]_i_2__0_n_0\,
- O => \s_tx_data[62]_i_1__0_n_0\
- );
-\s_tx_data[62]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0__0\(10),
- I1 => \[2].[1].s_reqs_reg[9][value]__0__0\(10),
- I2 => \[2].[2].s_reqs_reg[10][value]__0__0\(10),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[62]_i_2__0_n_0\
- );
-\s_tx_data[63]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(11),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0__0\(11),
- I5 => \s_tx_data[63]_i_2__0_n_0\,
- O => \s_tx_data[63]_i_1__0_n_0\
- );
-\s_tx_data[63]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0__0\(11),
- I1 => \[2].[1].s_reqs_reg[9][value]__0__0\(11),
- I2 => \[2].[2].s_reqs_reg[10][value]__0__0\(11),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[63]_i_2__0_n_0\
- );
-\s_tx_data[6]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(2),
- I1 => \data_rw_o_reg[79][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[6]_i_2__0_n_0\,
- O => \s_reqs[0][value]\(2)
- );
-\s_tx_data[6]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(2),
- I1 => \^s_tx_data_reg[15]_0\(2),
- I2 => \^s_tx_data_reg[15]_1\(2),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[6]_i_2__0_n_0\
- );
-\s_tx_data[76]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(0),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0__0\(0),
- I5 => \s_tx_data[76]_i_2__0_n_0\,
- O => \s_tx_data[76]_i_1__0_n_0\
- );
-\s_tx_data[76]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0__0\(0),
- I1 => \[3].[1].s_reqs_reg[13][value]__0__0\(0),
- I2 => \[3].[2].s_reqs_reg[14][value]__0__0\(0),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[76]_i_2__0_n_0\
- );
-\s_tx_data[77]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(1),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0__0\(1),
- I5 => \s_tx_data[77]_i_2__0_n_0\,
- O => \s_tx_data[77]_i_1__0_n_0\
- );
-\s_tx_data[77]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0__0\(1),
- I1 => \[3].[1].s_reqs_reg[13][value]__0__0\(1),
- I2 => \[3].[2].s_reqs_reg[14][value]__0__0\(1),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[77]_i_2__0_n_0\
- );
-\s_tx_data[78]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(2),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0__0\(2),
- I5 => \s_tx_data[78]_i_2__0_n_0\,
- O => \s_tx_data[78]_i_1__0_n_0\
- );
-\s_tx_data[78]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0__0\(2),
- I1 => \[3].[1].s_reqs_reg[13][value]__0__0\(2),
- I2 => \[3].[2].s_reqs_reg[14][value]__0__0\(2),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[78]_i_2__0_n_0\
- );
-\s_tx_data[79]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(3),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0__0\(3),
- I5 => \s_tx_data[79]_i_2__0_n_0\,
- O => \s_tx_data[79]_i_1__0_n_0\
- );
-\s_tx_data[79]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0__0\(3),
- I1 => \[3].[1].s_reqs_reg[13][value]__0__0\(3),
- I2 => \[3].[2].s_reqs_reg[14][value]__0__0\(3),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[79]_i_2__0_n_0\
- );
-\s_tx_data[7]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(3),
- I1 => \data_rw_o_reg[79][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[7]_i_2__0_n_0\,
- O => \s_reqs[0][value]\(3)
- );
-\s_tx_data[7]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(3),
- I1 => \^s_tx_data_reg[15]_0\(3),
- I2 => \^s_tx_data_reg[15]_1\(3),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[7]_i_2__0_n_0\
- );
-\s_tx_data[80]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(4),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0__0\(4),
- I5 => \s_tx_data[80]_i_2__0_n_0\,
- O => \s_tx_data[80]_i_1__0_n_0\
- );
-\s_tx_data[80]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0__0\(4),
- I1 => \[3].[1].s_reqs_reg[13][value]__0__0\(4),
- I2 => \[3].[2].s_reqs_reg[14][value]__0__0\(4),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[80]_i_2__0_n_0\
- );
-\s_tx_data[81]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(5),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0__0\(5),
- I5 => \s_tx_data[81]_i_2__0_n_0\,
- O => \s_tx_data[81]_i_1__0_n_0\
- );
-\s_tx_data[81]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0__0\(5),
- I1 => \[3].[1].s_reqs_reg[13][value]__0__0\(5),
- I2 => \[3].[2].s_reqs_reg[14][value]__0__0\(5),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[81]_i_2__0_n_0\
- );
-\s_tx_data[82]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(6),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0__0\(6),
- I5 => \s_tx_data[82]_i_2__0_n_0\,
- O => \s_tx_data[82]_i_1__0_n_0\
- );
-\s_tx_data[82]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0__0\(6),
- I1 => \[3].[1].s_reqs_reg[13][value]__0__0\(6),
- I2 => \[3].[2].s_reqs_reg[14][value]__0__0\(6),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[82]_i_2__0_n_0\
- );
-\s_tx_data[83]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(7),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0__0\(7),
- I5 => \s_tx_data[83]_i_2__0_n_0\,
- O => \s_tx_data[83]_i_1__0_n_0\
- );
-\s_tx_data[83]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0__0\(7),
- I1 => \[3].[1].s_reqs_reg[13][value]__0__0\(7),
- I2 => \[3].[2].s_reqs_reg[14][value]__0__0\(7),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[83]_i_2__0_n_0\
- );
-\s_tx_data[84]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(8),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0__0\(8),
- I5 => \s_tx_data[84]_i_2__0_n_0\,
- O => \s_tx_data[84]_i_1__0_n_0\
- );
-\s_tx_data[84]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0__0\(8),
- I1 => \[3].[1].s_reqs_reg[13][value]__0__0\(8),
- I2 => \[3].[2].s_reqs_reg[14][value]__0__0\(8),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[84]_i_2__0_n_0\
- );
-\s_tx_data[85]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(9),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0__0\(9),
- I5 => \s_tx_data[85]_i_2__0_n_0\,
- O => \s_tx_data[85]_i_1__0_n_0\
- );
-\s_tx_data[85]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0__0\(9),
- I1 => \[3].[1].s_reqs_reg[13][value]__0__0\(9),
- I2 => \[3].[2].s_reqs_reg[14][value]__0__0\(9),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[85]_i_2__0_n_0\
- );
-\s_tx_data[86]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(10),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0__0\(10),
- I5 => \s_tx_data[86]_i_2__0_n_0\,
- O => \s_tx_data[86]_i_1__0_n_0\
- );
-\s_tx_data[86]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0__0\(10),
- I1 => \[3].[1].s_reqs_reg[13][value]__0__0\(10),
- I2 => \[3].[2].s_reqs_reg[14][value]__0__0\(10),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[86]_i_2__0_n_0\
- );
-\s_tx_data[87]_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[79][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(11),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0__0\(11),
- I5 => \s_tx_data[87]_i_2__0_n_0\,
- O => \s_tx_data[87]_i_1__0_n_0\
- );
-\s_tx_data[87]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0__0\(11),
- I1 => \[3].[1].s_reqs_reg[13][value]__0__0\(11),
- I2 => \[3].[2].s_reqs_reg[14][value]__0__0\(11),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[87]_i_2__0_n_0\
- );
-\s_tx_data[8]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(4),
- I1 => \data_rw_o_reg[79][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[8]_i_2__0_n_0\,
- O => \s_reqs[0][value]\(4)
- );
-\s_tx_data[8]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(4),
- I1 => \^s_tx_data_reg[15]_0\(4),
- I2 => \^s_tx_data_reg[15]_1\(4),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[8]_i_2__0_n_0\
- );
-\s_tx_data[9]_i_1__0\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(5),
- I1 => \data_rw_o_reg[79][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[9]_i_2__0_n_0\,
- O => \s_reqs[0][value]\(5)
- );
-\s_tx_data[9]_i_2__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(5),
- I1 => \^s_tx_data_reg[15]_0\(5),
- I2 => \^s_tx_data_reg[15]_1\(5),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[79][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[9]_i_2__0_n_0\
- );
-\s_tx_data_reg[100]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[100]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[100]\,
- R => '0'
- );
-\s_tx_data_reg[101]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[101]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[101]\,
- R => '0'
- );
-\s_tx_data_reg[102]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[102]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[102]\,
- R => '0'
- );
-\s_tx_data_reg[103]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[103]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[103]\,
- R => '0'
- );
-\s_tx_data_reg[104]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[104]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[104]\,
- R => '0'
- );
-\s_tx_data_reg[105]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[105]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[105]\,
- R => '0'
- );
-\s_tx_data_reg[106]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[106]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[106]\,
- R => '0'
- );
-\s_tx_data_reg[107]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[107]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[107]\,
- R => '0'
- );
-\s_tx_data_reg[108]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[108]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[108]\,
- R => '0'
- );
-\s_tx_data_reg[109]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[109]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[109]\,
- R => '0'
- );
-\s_tx_data_reg[10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_reqs[0][value]\(6),
- Q => \s_tx_data_reg_n_0_[10]\,
- R => '0'
- );
-\s_tx_data_reg[110]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[110]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[110]\,
- R => '0'
- );
-\s_tx_data_reg[111]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[111]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[111]\,
- R => '0'
- );
-\s_tx_data_reg[112]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => ch_address(0),
- Q => \s_tx_data_reg_n_0_[112]\,
- R => '0'
- );
-\s_tx_data_reg[113]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => ch_address(1),
- Q => \s_tx_data_reg_n_0_[113]\,
- R => '0'
- );
-\s_tx_data_reg[11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_reqs[0][value]\(7),
- Q => \s_tx_data_reg_n_0_[11]\,
- R => '0'
- );
-\s_tx_data_reg[12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_reqs[0][value]\(8),
- Q => \s_tx_data_reg_n_0_[12]\,
- R => '0'
- );
-\s_tx_data_reg[13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_reqs[0][value]\(9),
- Q => \s_tx_data_reg_n_0_[13]\,
- R => '0'
- );
-\s_tx_data_reg[14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_reqs[0][value]\(10),
- Q => \s_tx_data_reg_n_0_[14]\,
- R => '0'
- );
-\s_tx_data_reg[15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_reqs[0][value]\(11),
- Q => \s_tx_data_reg_n_0_[15]\,
- R => '0'
- );
-\s_tx_data_reg[28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[28]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[28]\,
- R => '0'
- );
-\s_tx_data_reg[29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[29]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[29]\,
- R => '0'
- );
-\s_tx_data_reg[30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[30]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[30]\,
- R => '0'
- );
-\s_tx_data_reg[31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[31]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[31]\,
- R => '0'
- );
-\s_tx_data_reg[32]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[32]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[32]\,
- R => '0'
- );
-\s_tx_data_reg[33]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[33]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[33]\,
- R => '0'
- );
-\s_tx_data_reg[34]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[34]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[34]\,
- R => '0'
- );
-\s_tx_data_reg[35]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[35]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[35]\,
- R => '0'
- );
-\s_tx_data_reg[36]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[36]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[36]\,
- R => '0'
- );
-\s_tx_data_reg[37]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[37]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[37]\,
- R => '0'
- );
-\s_tx_data_reg[38]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[38]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[38]\,
- R => '0'
- );
-\s_tx_data_reg[39]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[39]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[39]\,
- R => '0'
- );
-\s_tx_data_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_reqs[0][value]\(0),
- Q => \s_tx_data_reg_n_0_[4]\,
- R => '0'
- );
-\s_tx_data_reg[52]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[52]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[52]\,
- R => '0'
- );
-\s_tx_data_reg[53]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[53]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[53]\,
- R => '0'
- );
-\s_tx_data_reg[54]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[54]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[54]\,
- R => '0'
- );
-\s_tx_data_reg[55]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[55]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[55]\,
- R => '0'
- );
-\s_tx_data_reg[56]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[56]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[56]\,
- R => '0'
- );
-\s_tx_data_reg[57]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[57]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[57]\,
- R => '0'
- );
-\s_tx_data_reg[58]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[58]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[58]\,
- R => '0'
- );
-\s_tx_data_reg[59]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[59]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[59]\,
- R => '0'
- );
-\s_tx_data_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_reqs[0][value]\(1),
- Q => \s_tx_data_reg_n_0_[5]\,
- R => '0'
- );
-\s_tx_data_reg[60]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[60]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[60]\,
- R => '0'
- );
-\s_tx_data_reg[61]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[61]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[61]\,
- R => '0'
- );
-\s_tx_data_reg[62]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[62]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[62]\,
- R => '0'
- );
-\s_tx_data_reg[63]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[63]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[63]\,
- R => '0'
- );
-\s_tx_data_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_reqs[0][value]\(2),
- Q => \s_tx_data_reg_n_0_[6]\,
- R => '0'
- );
-\s_tx_data_reg[76]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[76]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[76]\,
- R => '0'
- );
-\s_tx_data_reg[77]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[77]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[77]\,
- R => '0'
- );
-\s_tx_data_reg[78]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[78]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[78]\,
- R => '0'
- );
-\s_tx_data_reg[79]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[79]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[79]\,
- R => '0'
- );
-\s_tx_data_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_reqs[0][value]\(3),
- Q => \s_tx_data_reg_n_0_[7]\,
- R => '0'
- );
-\s_tx_data_reg[80]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[80]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[80]\,
- R => '0'
- );
-\s_tx_data_reg[81]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[81]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[81]\,
- R => '0'
- );
-\s_tx_data_reg[82]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[82]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[82]\,
- R => '0'
- );
-\s_tx_data_reg[83]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[83]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[83]\,
- R => '0'
- );
-\s_tx_data_reg[84]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[84]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[84]\,
- R => '0'
- );
-\s_tx_data_reg[85]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[85]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[85]\,
- R => '0'
- );
-\s_tx_data_reg[86]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[86]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[86]\,
- R => '0'
- );
-\s_tx_data_reg[87]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_tx_data[87]_i_1__0_n_0\,
- Q => \s_tx_data_reg_n_0_[87]\,
- R => '0'
- );
-\s_tx_data_reg[8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_reqs[0][value]\(4),
- Q => \s_tx_data_reg_n_0_[8]\,
- R => '0'
- );
-\s_tx_data_reg[9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1__0_n_0\,
- D => \s_reqs[0][value]\(5),
- Q => \s_tx_data_reg_n_0_[9]\,
- R => '0'
- );
-\v_ch_address[1]_i_3__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"00000002FFFFFFFF"
- )
- port map (
- I0 => \v_ch_address[1]_i_5__0_n_0\,
- I1 => \data_rw_o_reg[79][2]\(0),
- I2 => \[1].[0].s_reqs_reg[4][changed]__1\,
- I3 => \[0].[3].s_reqs_reg[3][changed_n_0_]\,
- I4 => \[0].[2].s_reqs_reg[2][changed_n_0_]\,
- I5 => \^dac_ch_o_reg[0][0]_1\,
- O => \v_ch_address[1]_i_3__0_n_0\
- );
-\v_ch_address[1]_i_5__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0003000000033355"
- )
- port map (
- I0 => \[0].[0].s_reqs_reg[0][changed_n_0_]\,
- I1 => \[1].[1].s_reqs_reg[5][changed]__1\,
- I2 => \[1].[2].s_reqs_reg[6][changed]__1\,
- I3 => ch_address(0),
- I4 => ch_address(1),
- I5 => \[0].[1].s_reqs_reg[1][changed_n_0_]\,
- O => \v_ch_address[1]_i_5__0_n_0\
- );
-\v_ch_address_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => cmp_spi_n_1,
- Q => ch_address(0),
- R => '0'
- );
-\v_ch_address_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => cmp_spi_n_2,
- Q => ch_address(1),
- R => '0'
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_dac7716_spi_129 is
- port (
- s_start : out STD_LOGIC;
- \dac_ch_o_reg[0][0]_0\ : out STD_LOGIC;
- \dac_ch_o_reg[0][0]_1\ : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[111]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[15]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[15]_1\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]_1\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]_2\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]_3\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_counter_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_rdata_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
- s_spi_mosi : out STD_LOGIC;
- s_spi_cs_n : out STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- s_start_reg_0 : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- \data_rw_o_reg[11][2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \data_rw_o_reg[19][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- CO : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[18][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[18][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[17][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[17][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[16][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[16][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[20][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[20][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[21][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[21][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[22][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[22][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[23][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[23][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[24][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[25][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[26][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[27][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[28][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[29][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[30][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[31][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[32][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[33][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[34][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[35][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- D : in STD_LOGIC_VECTOR ( 0 to 0 )
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_dac7716_spi_129 : entity is "dac7716_spi";
-end system_design_fasec_hwtest_0_0_dac7716_spi_129;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_dac7716_spi_129 is
- signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[0].[0].s_reqs[0][changed]_i_1_n_0\ : STD_LOGIC;
- signal \[0].[0].s_reqs_reg[0][changed_n_0_]\ : STD_LOGIC;
- signal \[0].[1].s_reqs[1][changed]_i_1_n_0\ : STD_LOGIC;
- signal \[0].[1].s_reqs_reg[1][changed_n_0_]\ : STD_LOGIC;
- signal \[0].[2].s_reqs[2][changed]_i_1_n_0\ : STD_LOGIC;
- signal \[0].[2].s_reqs_reg[2][changed_n_0_]\ : STD_LOGIC;
- signal \[0].[3].s_reqs[3][changed]_i_1_n_0\ : STD_LOGIC;
- signal \[0].[3].s_reqs_reg[3][changed_n_0_]\ : STD_LOGIC;
- signal \[1].[0].s_reqs[4][changed]_i_1_n_0\ : STD_LOGIC;
- signal \[1].[0].s_reqs_reg[4][changed]__1\ : STD_LOGIC;
- signal \[1].[1].s_reqs[5][changed]_i_1_n_0\ : STD_LOGIC;
- signal \[1].[1].s_reqs_reg[5][changed]__1\ : STD_LOGIC;
- signal \[1].[2].s_reqs[6][changed]_i_1_n_0\ : STD_LOGIC;
- signal \[1].[2].s_reqs_reg[6][changed]__1\ : STD_LOGIC;
- signal \[1].[3].s_reqs[7][changed]_i_1_n_0\ : STD_LOGIC;
- signal \[1].[3].s_reqs_reg[7][changed]__1\ : STD_LOGIC;
- signal \[2].[0].s_reqs_reg[8][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[2].[1].s_reqs_reg[9][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[2].[2].s_reqs_reg[10][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[2].[3].s_reqs_reg[11][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[3].[0].s_reqs_reg[12][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[3].[1].s_reqs_reg[13][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[3].[2].s_reqs_reg[14][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[3].[3].s_reqs_reg[15][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[4].[0].s_reqs_reg[16][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[4].[1].s_reqs_reg[17][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[4].[2].s_reqs_reg[18][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \[4].[3].s_reqs_reg[19][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal ch_address : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal cmp_spi_n_0 : STD_LOGIC;
- signal cmp_spi_n_1 : STD_LOGIC;
- signal cmp_spi_n_2 : STD_LOGIC;
- signal cmp_spi_n_3 : STD_LOGIC;
- signal cmp_spi_n_4 : STD_LOGIC;
- signal \dac_ch_o[0][31]_i_2_n_0\ : STD_LOGIC;
- signal \^dac_ch_o_reg[0][0]_0\ : STD_LOGIC;
- signal \^dac_ch_o_reg[0][0]_1\ : STD_LOGIC;
- signal p_0_in : STD_LOGIC;
- signal p_1_in : STD_LOGIC;
- signal p_2_in : STD_LOGIC;
- signal rx_data_o : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal \s_flag_reset[0]_i_1_n_0\ : STD_LOGIC;
- signal \s_flag_reset[1]_i_1_n_0\ : STD_LOGIC;
- signal \s_flag_reset[2]_i_1_n_0\ : STD_LOGIC;
- signal \s_flag_reset[3]_i_1_n_0\ : STD_LOGIC;
- signal \s_flag_reset_reg_n_0_[0]\ : STD_LOGIC;
- signal \s_reqs[0][value]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_start\ : STD_LOGIC;
- signal \s_state[1]_i_2_n_0\ : STD_LOGIC;
- signal \s_state[1]_i_3_n_0\ : STD_LOGIC;
- signal \s_state[1]_i_5_n_0\ : STD_LOGIC;
- signal \s_tx_data[100]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[100]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[101]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[101]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[102]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[102]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[103]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[103]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[104]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[104]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[105]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[105]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[106]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[106]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[107]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[107]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[108]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[108]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[109]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[109]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[10]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[110]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[110]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[111]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[111]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[113]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[11]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[12]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[13]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[14]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[15]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[28]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[28]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[29]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[29]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[30]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[30]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[31]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[31]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[32]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[32]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[33]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[33]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[34]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[34]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[35]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[35]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[36]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[36]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[37]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[37]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[38]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[38]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[39]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[39]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[4]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[52]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[52]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[53]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[53]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[54]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[54]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[55]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[55]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[56]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[56]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[57]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[57]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[58]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[58]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[59]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[59]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[5]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[60]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[60]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[61]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[61]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[62]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[62]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[63]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[63]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[6]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[76]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[76]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[77]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[77]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[78]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[78]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[79]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[79]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[7]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[80]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[80]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[81]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[81]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[82]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[82]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[83]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[83]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[84]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[84]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[85]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[85]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[86]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[86]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[87]_i_1_n_0\ : STD_LOGIC;
- signal \s_tx_data[87]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[8]_i_2_n_0\ : STD_LOGIC;
- signal \s_tx_data[9]_i_2_n_0\ : STD_LOGIC;
- signal \^s_tx_data_reg[111]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_tx_data_reg[15]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_tx_data_reg[15]_1\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_tx_data_reg[39]_0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_tx_data_reg[39]_1\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_tx_data_reg[39]_2\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_tx_data_reg[39]_3\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \s_tx_data_reg_n_0_[100]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[101]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[102]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[103]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[104]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[105]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[106]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[107]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[108]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[109]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[10]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[110]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[111]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[112]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[113]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[11]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[12]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[13]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[14]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[15]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[28]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[29]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[30]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[31]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[32]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[33]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[34]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[35]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[36]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[37]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[38]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[39]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[4]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[52]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[53]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[54]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[55]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[56]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[57]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[58]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[59]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[5]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[60]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[61]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[62]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[63]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[6]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[76]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[77]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[78]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[79]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[7]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[80]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[81]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[82]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[83]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[84]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[85]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[86]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[87]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[8]\ : STD_LOGIC;
- signal \s_tx_data_reg_n_0_[9]\ : STD_LOGIC;
- signal \v_ch_address[1]_i_3_n_0\ : STD_LOGIC;
- signal \v_ch_address[1]_i_5_n_0\ : STD_LOGIC;
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \[0].[0].s_reqs[0][changed]_i_1\ : label is "soft_lutpair45";
- attribute SOFT_HLUTNM of \[0].[1].s_reqs[1][changed]_i_1\ : label is "soft_lutpair43";
- attribute SOFT_HLUTNM of \[0].[2].s_reqs[2][changed]_i_1\ : label is "soft_lutpair44";
- attribute SOFT_HLUTNM of \[0].[3].s_reqs[3][changed]_i_1\ : label is "soft_lutpair46";
- attribute SOFT_HLUTNM of \[1].[0].s_reqs[4][changed]_i_1\ : label is "soft_lutpair45";
- attribute SOFT_HLUTNM of \[1].[1].s_reqs[5][changed]_i_1\ : label is "soft_lutpair43";
- attribute SOFT_HLUTNM of \[1].[2].s_reqs[6][changed]_i_1\ : label is "soft_lutpair44";
- attribute SOFT_HLUTNM of \[1].[3].s_reqs[7][changed]_i_1\ : label is "soft_lutpair46";
- attribute SOFT_HLUTNM of \dac_ch_o[0][31]_i_2\ : label is "soft_lutpair42";
- attribute SOFT_HLUTNM of \s_tx_data[14]_i_1\ : label is "soft_lutpair42";
-begin
- Q(11 downto 0) <= \^q\(11 downto 0);
- \dac_ch_o_reg[0][0]_0\ <= \^dac_ch_o_reg[0][0]_0\;
- \dac_ch_o_reg[0][0]_1\ <= \^dac_ch_o_reg[0][0]_1\;
- s_start <= \^s_start\;
- \s_tx_data_reg[111]_0\(11 downto 0) <= \^s_tx_data_reg[111]_0\(11 downto 0);
- \s_tx_data_reg[15]_0\(11 downto 0) <= \^s_tx_data_reg[15]_0\(11 downto 0);
- \s_tx_data_reg[15]_1\(11 downto 0) <= \^s_tx_data_reg[15]_1\(11 downto 0);
- \s_tx_data_reg[39]_0\(11 downto 0) <= \^s_tx_data_reg[39]_0\(11 downto 0);
- \s_tx_data_reg[39]_1\(11 downto 0) <= \^s_tx_data_reg[39]_1\(11 downto 0);
- \s_tx_data_reg[39]_2\(11 downto 0) <= \^s_tx_data_reg[39]_2\(11 downto 0);
- \s_tx_data_reg[39]_3\(11 downto 0) <= \^s_tx_data_reg[39]_3\(11 downto 0);
-\[0].[0].s_reqs[0][changed]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[0].[0].s_reqs_reg[0][changed_n_0_]\,
- I1 => \data_rw_o_reg[16][11]_0\(0),
- I2 => \s_flag_reset_reg_n_0_[0]\,
- O => \[0].[0].s_reqs[0][changed]_i_1_n_0\
- );
-\[0].[0].s_reqs_reg[0][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[0].[0].s_reqs[0][changed]_i_1_n_0\,
- Q => \[0].[0].s_reqs_reg[0][changed_n_0_]\,
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[16][11]\(0),
- Q => \^s_tx_data_reg[111]_0\(0),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[16][11]\(10),
- Q => \^s_tx_data_reg[111]_0\(10),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[16][11]\(11),
- Q => \^s_tx_data_reg[111]_0\(11),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[16][11]\(1),
- Q => \^s_tx_data_reg[111]_0\(1),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[16][11]\(2),
- Q => \^s_tx_data_reg[111]_0\(2),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[16][11]\(3),
- Q => \^s_tx_data_reg[111]_0\(3),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[16][11]\(4),
- Q => \^s_tx_data_reg[111]_0\(4),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[16][11]\(5),
- Q => \^s_tx_data_reg[111]_0\(5),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[16][11]\(6),
- Q => \^s_tx_data_reg[111]_0\(6),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[16][11]\(7),
- Q => \^s_tx_data_reg[111]_0\(7),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[16][11]\(8),
- Q => \^s_tx_data_reg[111]_0\(8),
- R => '0'
- );
-\[0].[0].s_reqs_reg[0][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[16][11]\(9),
- Q => \^s_tx_data_reg[111]_0\(9),
- R => '0'
- );
-\[0].[1].s_reqs[1][changed]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[0].[1].s_reqs_reg[1][changed_n_0_]\,
- I1 => \data_rw_o_reg[17][11]_0\(0),
- I2 => p_2_in,
- O => \[0].[1].s_reqs[1][changed]_i_1_n_0\
- );
-\[0].[1].s_reqs_reg[1][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[0].[1].s_reqs[1][changed]_i_1_n_0\,
- Q => \[0].[1].s_reqs_reg[1][changed_n_0_]\,
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[17][11]\(0),
- Q => \^s_tx_data_reg[15]_0\(0),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[17][11]\(10),
- Q => \^s_tx_data_reg[15]_0\(10),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[17][11]\(11),
- Q => \^s_tx_data_reg[15]_0\(11),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[17][11]\(1),
- Q => \^s_tx_data_reg[15]_0\(1),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[17][11]\(2),
- Q => \^s_tx_data_reg[15]_0\(2),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[17][11]\(3),
- Q => \^s_tx_data_reg[15]_0\(3),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[17][11]\(4),
- Q => \^s_tx_data_reg[15]_0\(4),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[17][11]\(5),
- Q => \^s_tx_data_reg[15]_0\(5),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[17][11]\(6),
- Q => \^s_tx_data_reg[15]_0\(6),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[17][11]\(7),
- Q => \^s_tx_data_reg[15]_0\(7),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[17][11]\(8),
- Q => \^s_tx_data_reg[15]_0\(8),
- R => '0'
- );
-\[0].[1].s_reqs_reg[1][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[17][11]\(9),
- Q => \^s_tx_data_reg[15]_0\(9),
- R => '0'
- );
-\[0].[2].s_reqs[2][changed]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[0].[2].s_reqs_reg[2][changed_n_0_]\,
- I1 => \data_rw_o_reg[18][11]_0\(0),
- I2 => p_1_in,
- O => \[0].[2].s_reqs[2][changed]_i_1_n_0\
- );
-\[0].[2].s_reqs_reg[2][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[0].[2].s_reqs[2][changed]_i_1_n_0\,
- Q => \[0].[2].s_reqs_reg[2][changed_n_0_]\,
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[18][11]\(0),
- Q => \^s_tx_data_reg[15]_1\(0),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[18][11]\(10),
- Q => \^s_tx_data_reg[15]_1\(10),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[18][11]\(11),
- Q => \^s_tx_data_reg[15]_1\(11),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[18][11]\(1),
- Q => \^s_tx_data_reg[15]_1\(1),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[18][11]\(2),
- Q => \^s_tx_data_reg[15]_1\(2),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[18][11]\(3),
- Q => \^s_tx_data_reg[15]_1\(3),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[18][11]\(4),
- Q => \^s_tx_data_reg[15]_1\(4),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[18][11]\(5),
- Q => \^s_tx_data_reg[15]_1\(5),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[18][11]\(6),
- Q => \^s_tx_data_reg[15]_1\(6),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[18][11]\(7),
- Q => \^s_tx_data_reg[15]_1\(7),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[18][11]\(8),
- Q => \^s_tx_data_reg[15]_1\(8),
- R => '0'
- );
-\[0].[2].s_reqs_reg[2][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[18][11]\(9),
- Q => \^s_tx_data_reg[15]_1\(9),
- R => '0'
- );
-\[0].[3].s_reqs[3][changed]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[0].[3].s_reqs_reg[3][changed_n_0_]\,
- I1 => CO(0),
- I2 => p_0_in,
- O => \[0].[3].s_reqs[3][changed]_i_1_n_0\
- );
-\[0].[3].s_reqs_reg[3][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[0].[3].s_reqs[3][changed]_i_1_n_0\,
- Q => \[0].[3].s_reqs_reg[3][changed_n_0_]\,
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[19][11]\(0),
- Q => \^q\(0),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[19][11]\(10),
- Q => \^q\(10),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[19][11]\(11),
- Q => \^q\(11),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[19][11]\(1),
- Q => \^q\(1),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[19][11]\(2),
- Q => \^q\(2),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[19][11]\(3),
- Q => \^q\(3),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[19][11]\(4),
- Q => \^q\(4),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[19][11]\(5),
- Q => \^q\(5),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[19][11]\(6),
- Q => \^q\(6),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[19][11]\(7),
- Q => \^q\(7),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[19][11]\(8),
- Q => \^q\(8),
- R => '0'
- );
-\[0].[3].s_reqs_reg[3][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[19][11]\(9),
- Q => \^q\(9),
- R => '0'
- );
-\[1].[0].s_reqs[4][changed]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[1].[0].s_reqs_reg[4][changed]__1\,
- I1 => \data_rw_o_reg[20][11]_0\(0),
- I2 => \s_flag_reset_reg_n_0_[0]\,
- O => \[1].[0].s_reqs[4][changed]_i_1_n_0\
- );
-\[1].[0].s_reqs_reg[4][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[1].[0].s_reqs[4][changed]_i_1_n_0\,
- Q => \[1].[0].s_reqs_reg[4][changed]__1\,
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[20][11]\(0),
- Q => \^s_tx_data_reg[39]_1\(0),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[20][11]\(10),
- Q => \^s_tx_data_reg[39]_1\(10),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[20][11]\(11),
- Q => \^s_tx_data_reg[39]_1\(11),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[20][11]\(1),
- Q => \^s_tx_data_reg[39]_1\(1),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[20][11]\(2),
- Q => \^s_tx_data_reg[39]_1\(2),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[20][11]\(3),
- Q => \^s_tx_data_reg[39]_1\(3),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[20][11]\(4),
- Q => \^s_tx_data_reg[39]_1\(4),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[20][11]\(5),
- Q => \^s_tx_data_reg[39]_1\(5),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[20][11]\(6),
- Q => \^s_tx_data_reg[39]_1\(6),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[20][11]\(7),
- Q => \^s_tx_data_reg[39]_1\(7),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[20][11]\(8),
- Q => \^s_tx_data_reg[39]_1\(8),
- R => '0'
- );
-\[1].[0].s_reqs_reg[4][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[20][11]\(9),
- Q => \^s_tx_data_reg[39]_1\(9),
- R => '0'
- );
-\[1].[1].s_reqs[5][changed]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[1].[1].s_reqs_reg[5][changed]__1\,
- I1 => \data_rw_o_reg[21][11]_0\(0),
- I2 => p_2_in,
- O => \[1].[1].s_reqs[5][changed]_i_1_n_0\
- );
-\[1].[1].s_reqs_reg[5][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[1].[1].s_reqs[5][changed]_i_1_n_0\,
- Q => \[1].[1].s_reqs_reg[5][changed]__1\,
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[21][11]\(0),
- Q => \^s_tx_data_reg[39]_2\(0),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[21][11]\(10),
- Q => \^s_tx_data_reg[39]_2\(10),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[21][11]\(11),
- Q => \^s_tx_data_reg[39]_2\(11),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[21][11]\(1),
- Q => \^s_tx_data_reg[39]_2\(1),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[21][11]\(2),
- Q => \^s_tx_data_reg[39]_2\(2),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[21][11]\(3),
- Q => \^s_tx_data_reg[39]_2\(3),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[21][11]\(4),
- Q => \^s_tx_data_reg[39]_2\(4),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[21][11]\(5),
- Q => \^s_tx_data_reg[39]_2\(5),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[21][11]\(6),
- Q => \^s_tx_data_reg[39]_2\(6),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[21][11]\(7),
- Q => \^s_tx_data_reg[39]_2\(7),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[21][11]\(8),
- Q => \^s_tx_data_reg[39]_2\(8),
- R => '0'
- );
-\[1].[1].s_reqs_reg[5][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[21][11]\(9),
- Q => \^s_tx_data_reg[39]_2\(9),
- R => '0'
- );
-\[1].[2].s_reqs[6][changed]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[1].[2].s_reqs_reg[6][changed]__1\,
- I1 => \data_rw_o_reg[22][11]_0\(0),
- I2 => p_1_in,
- O => \[1].[2].s_reqs[6][changed]_i_1_n_0\
- );
-\[1].[2].s_reqs_reg[6][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[1].[2].s_reqs[6][changed]_i_1_n_0\,
- Q => \[1].[2].s_reqs_reg[6][changed]__1\,
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[22][11]\(0),
- Q => \^s_tx_data_reg[39]_3\(0),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[22][11]\(10),
- Q => \^s_tx_data_reg[39]_3\(10),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[22][11]\(11),
- Q => \^s_tx_data_reg[39]_3\(11),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[22][11]\(1),
- Q => \^s_tx_data_reg[39]_3\(1),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[22][11]\(2),
- Q => \^s_tx_data_reg[39]_3\(2),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[22][11]\(3),
- Q => \^s_tx_data_reg[39]_3\(3),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[22][11]\(4),
- Q => \^s_tx_data_reg[39]_3\(4),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[22][11]\(5),
- Q => \^s_tx_data_reg[39]_3\(5),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[22][11]\(6),
- Q => \^s_tx_data_reg[39]_3\(6),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[22][11]\(7),
- Q => \^s_tx_data_reg[39]_3\(7),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[22][11]\(8),
- Q => \^s_tx_data_reg[39]_3\(8),
- R => '0'
- );
-\[1].[2].s_reqs_reg[6][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[22][11]\(9),
- Q => \^s_tx_data_reg[39]_3\(9),
- R => '0'
- );
-\[1].[3].s_reqs[7][changed]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"0E"
- )
- port map (
- I0 => \[1].[3].s_reqs_reg[7][changed]__1\,
- I1 => \data_rw_o_reg[23][11]_0\(0),
- I2 => p_0_in,
- O => \[1].[3].s_reqs[7][changed]_i_1_n_0\
- );
-\[1].[3].s_reqs_reg[7][changed]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \[1].[3].s_reqs[7][changed]_i_1_n_0\,
- Q => \[1].[3].s_reqs_reg[7][changed]__1\,
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[23][11]\(0),
- Q => \^s_tx_data_reg[39]_0\(0),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[23][11]\(10),
- Q => \^s_tx_data_reg[39]_0\(10),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[23][11]\(11),
- Q => \^s_tx_data_reg[39]_0\(11),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[23][11]\(1),
- Q => \^s_tx_data_reg[39]_0\(1),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[23][11]\(2),
- Q => \^s_tx_data_reg[39]_0\(2),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[23][11]\(3),
- Q => \^s_tx_data_reg[39]_0\(3),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[23][11]\(4),
- Q => \^s_tx_data_reg[39]_0\(4),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[23][11]\(5),
- Q => \^s_tx_data_reg[39]_0\(5),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[23][11]\(6),
- Q => \^s_tx_data_reg[39]_0\(6),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[23][11]\(7),
- Q => \^s_tx_data_reg[39]_0\(7),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[23][11]\(8),
- Q => \^s_tx_data_reg[39]_0\(8),
- R => '0'
- );
-\[1].[3].s_reqs_reg[7][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[23][11]\(9),
- Q => \^s_tx_data_reg[39]_0\(9),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[24][11]\(0),
- Q => \[2].[0].s_reqs_reg[8][value]__0\(0),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[24][11]\(10),
- Q => \[2].[0].s_reqs_reg[8][value]__0\(10),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[24][11]\(11),
- Q => \[2].[0].s_reqs_reg[8][value]__0\(11),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[24][11]\(1),
- Q => \[2].[0].s_reqs_reg[8][value]__0\(1),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[24][11]\(2),
- Q => \[2].[0].s_reqs_reg[8][value]__0\(2),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[24][11]\(3),
- Q => \[2].[0].s_reqs_reg[8][value]__0\(3),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[24][11]\(4),
- Q => \[2].[0].s_reqs_reg[8][value]__0\(4),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[24][11]\(5),
- Q => \[2].[0].s_reqs_reg[8][value]__0\(5),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[24][11]\(6),
- Q => \[2].[0].s_reqs_reg[8][value]__0\(6),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[24][11]\(7),
- Q => \[2].[0].s_reqs_reg[8][value]__0\(7),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[24][11]\(8),
- Q => \[2].[0].s_reqs_reg[8][value]__0\(8),
- R => '0'
- );
-\[2].[0].s_reqs_reg[8][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[24][11]\(9),
- Q => \[2].[0].s_reqs_reg[8][value]__0\(9),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[25][11]\(0),
- Q => \[2].[1].s_reqs_reg[9][value]__0\(0),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[25][11]\(10),
- Q => \[2].[1].s_reqs_reg[9][value]__0\(10),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[25][11]\(11),
- Q => \[2].[1].s_reqs_reg[9][value]__0\(11),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[25][11]\(1),
- Q => \[2].[1].s_reqs_reg[9][value]__0\(1),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[25][11]\(2),
- Q => \[2].[1].s_reqs_reg[9][value]__0\(2),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[25][11]\(3),
- Q => \[2].[1].s_reqs_reg[9][value]__0\(3),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[25][11]\(4),
- Q => \[2].[1].s_reqs_reg[9][value]__0\(4),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[25][11]\(5),
- Q => \[2].[1].s_reqs_reg[9][value]__0\(5),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[25][11]\(6),
- Q => \[2].[1].s_reqs_reg[9][value]__0\(6),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[25][11]\(7),
- Q => \[2].[1].s_reqs_reg[9][value]__0\(7),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[25][11]\(8),
- Q => \[2].[1].s_reqs_reg[9][value]__0\(8),
- R => '0'
- );
-\[2].[1].s_reqs_reg[9][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[25][11]\(9),
- Q => \[2].[1].s_reqs_reg[9][value]__0\(9),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[26][11]\(0),
- Q => \[2].[2].s_reqs_reg[10][value]__0\(0),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[26][11]\(10),
- Q => \[2].[2].s_reqs_reg[10][value]__0\(10),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[26][11]\(11),
- Q => \[2].[2].s_reqs_reg[10][value]__0\(11),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[26][11]\(1),
- Q => \[2].[2].s_reqs_reg[10][value]__0\(1),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[26][11]\(2),
- Q => \[2].[2].s_reqs_reg[10][value]__0\(2),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[26][11]\(3),
- Q => \[2].[2].s_reqs_reg[10][value]__0\(3),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[26][11]\(4),
- Q => \[2].[2].s_reqs_reg[10][value]__0\(4),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[26][11]\(5),
- Q => \[2].[2].s_reqs_reg[10][value]__0\(5),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[26][11]\(6),
- Q => \[2].[2].s_reqs_reg[10][value]__0\(6),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[26][11]\(7),
- Q => \[2].[2].s_reqs_reg[10][value]__0\(7),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[26][11]\(8),
- Q => \[2].[2].s_reqs_reg[10][value]__0\(8),
- R => '0'
- );
-\[2].[2].s_reqs_reg[10][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[26][11]\(9),
- Q => \[2].[2].s_reqs_reg[10][value]__0\(9),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[27][11]\(0),
- Q => \[2].[3].s_reqs_reg[11][value]__0\(0),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[27][11]\(10),
- Q => \[2].[3].s_reqs_reg[11][value]__0\(10),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[27][11]\(11),
- Q => \[2].[3].s_reqs_reg[11][value]__0\(11),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[27][11]\(1),
- Q => \[2].[3].s_reqs_reg[11][value]__0\(1),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[27][11]\(2),
- Q => \[2].[3].s_reqs_reg[11][value]__0\(2),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[27][11]\(3),
- Q => \[2].[3].s_reqs_reg[11][value]__0\(3),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[27][11]\(4),
- Q => \[2].[3].s_reqs_reg[11][value]__0\(4),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[27][11]\(5),
- Q => \[2].[3].s_reqs_reg[11][value]__0\(5),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[27][11]\(6),
- Q => \[2].[3].s_reqs_reg[11][value]__0\(6),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[27][11]\(7),
- Q => \[2].[3].s_reqs_reg[11][value]__0\(7),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[27][11]\(8),
- Q => \[2].[3].s_reqs_reg[11][value]__0\(8),
- R => '0'
- );
-\[2].[3].s_reqs_reg[11][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[27][11]\(9),
- Q => \[2].[3].s_reqs_reg[11][value]__0\(9),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[28][11]\(0),
- Q => \[3].[0].s_reqs_reg[12][value]__0\(0),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[28][11]\(10),
- Q => \[3].[0].s_reqs_reg[12][value]__0\(10),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[28][11]\(11),
- Q => \[3].[0].s_reqs_reg[12][value]__0\(11),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[28][11]\(1),
- Q => \[3].[0].s_reqs_reg[12][value]__0\(1),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[28][11]\(2),
- Q => \[3].[0].s_reqs_reg[12][value]__0\(2),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[28][11]\(3),
- Q => \[3].[0].s_reqs_reg[12][value]__0\(3),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[28][11]\(4),
- Q => \[3].[0].s_reqs_reg[12][value]__0\(4),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[28][11]\(5),
- Q => \[3].[0].s_reqs_reg[12][value]__0\(5),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[28][11]\(6),
- Q => \[3].[0].s_reqs_reg[12][value]__0\(6),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[28][11]\(7),
- Q => \[3].[0].s_reqs_reg[12][value]__0\(7),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[28][11]\(8),
- Q => \[3].[0].s_reqs_reg[12][value]__0\(8),
- R => '0'
- );
-\[3].[0].s_reqs_reg[12][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[28][11]\(9),
- Q => \[3].[0].s_reqs_reg[12][value]__0\(9),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[29][11]\(0),
- Q => \[3].[1].s_reqs_reg[13][value]__0\(0),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[29][11]\(10),
- Q => \[3].[1].s_reqs_reg[13][value]__0\(10),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[29][11]\(11),
- Q => \[3].[1].s_reqs_reg[13][value]__0\(11),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[29][11]\(1),
- Q => \[3].[1].s_reqs_reg[13][value]__0\(1),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[29][11]\(2),
- Q => \[3].[1].s_reqs_reg[13][value]__0\(2),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[29][11]\(3),
- Q => \[3].[1].s_reqs_reg[13][value]__0\(3),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[29][11]\(4),
- Q => \[3].[1].s_reqs_reg[13][value]__0\(4),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[29][11]\(5),
- Q => \[3].[1].s_reqs_reg[13][value]__0\(5),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[29][11]\(6),
- Q => \[3].[1].s_reqs_reg[13][value]__0\(6),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[29][11]\(7),
- Q => \[3].[1].s_reqs_reg[13][value]__0\(7),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[29][11]\(8),
- Q => \[3].[1].s_reqs_reg[13][value]__0\(8),
- R => '0'
- );
-\[3].[1].s_reqs_reg[13][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[29][11]\(9),
- Q => \[3].[1].s_reqs_reg[13][value]__0\(9),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[30][11]\(0),
- Q => \[3].[2].s_reqs_reg[14][value]__0\(0),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[30][11]\(10),
- Q => \[3].[2].s_reqs_reg[14][value]__0\(10),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[30][11]\(11),
- Q => \[3].[2].s_reqs_reg[14][value]__0\(11),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[30][11]\(1),
- Q => \[3].[2].s_reqs_reg[14][value]__0\(1),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[30][11]\(2),
- Q => \[3].[2].s_reqs_reg[14][value]__0\(2),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[30][11]\(3),
- Q => \[3].[2].s_reqs_reg[14][value]__0\(3),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[30][11]\(4),
- Q => \[3].[2].s_reqs_reg[14][value]__0\(4),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[30][11]\(5),
- Q => \[3].[2].s_reqs_reg[14][value]__0\(5),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[30][11]\(6),
- Q => \[3].[2].s_reqs_reg[14][value]__0\(6),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[30][11]\(7),
- Q => \[3].[2].s_reqs_reg[14][value]__0\(7),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[30][11]\(8),
- Q => \[3].[2].s_reqs_reg[14][value]__0\(8),
- R => '0'
- );
-\[3].[2].s_reqs_reg[14][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[30][11]\(9),
- Q => \[3].[2].s_reqs_reg[14][value]__0\(9),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[31][11]\(0),
- Q => \[3].[3].s_reqs_reg[15][value]__0\(0),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[31][11]\(10),
- Q => \[3].[3].s_reqs_reg[15][value]__0\(10),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[31][11]\(11),
- Q => \[3].[3].s_reqs_reg[15][value]__0\(11),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[31][11]\(1),
- Q => \[3].[3].s_reqs_reg[15][value]__0\(1),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[31][11]\(2),
- Q => \[3].[3].s_reqs_reg[15][value]__0\(2),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[31][11]\(3),
- Q => \[3].[3].s_reqs_reg[15][value]__0\(3),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[31][11]\(4),
- Q => \[3].[3].s_reqs_reg[15][value]__0\(4),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[31][11]\(5),
- Q => \[3].[3].s_reqs_reg[15][value]__0\(5),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[31][11]\(6),
- Q => \[3].[3].s_reqs_reg[15][value]__0\(6),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[31][11]\(7),
- Q => \[3].[3].s_reqs_reg[15][value]__0\(7),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[31][11]\(8),
- Q => \[3].[3].s_reqs_reg[15][value]__0\(8),
- R => '0'
- );
-\[3].[3].s_reqs_reg[15][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[31][11]\(9),
- Q => \[3].[3].s_reqs_reg[15][value]__0\(9),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[32][11]\(0),
- Q => \[4].[0].s_reqs_reg[16][value]__0\(0),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[32][11]\(10),
- Q => \[4].[0].s_reqs_reg[16][value]__0\(10),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[32][11]\(11),
- Q => \[4].[0].s_reqs_reg[16][value]__0\(11),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[32][11]\(1),
- Q => \[4].[0].s_reqs_reg[16][value]__0\(1),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[32][11]\(2),
- Q => \[4].[0].s_reqs_reg[16][value]__0\(2),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[32][11]\(3),
- Q => \[4].[0].s_reqs_reg[16][value]__0\(3),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[32][11]\(4),
- Q => \[4].[0].s_reqs_reg[16][value]__0\(4),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[32][11]\(5),
- Q => \[4].[0].s_reqs_reg[16][value]__0\(5),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[32][11]\(6),
- Q => \[4].[0].s_reqs_reg[16][value]__0\(6),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[32][11]\(7),
- Q => \[4].[0].s_reqs_reg[16][value]__0\(7),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[32][11]\(8),
- Q => \[4].[0].s_reqs_reg[16][value]__0\(8),
- R => '0'
- );
-\[4].[0].s_reqs_reg[16][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[32][11]\(9),
- Q => \[4].[0].s_reqs_reg[16][value]__0\(9),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[33][11]\(0),
- Q => \[4].[1].s_reqs_reg[17][value]__0\(0),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[33][11]\(10),
- Q => \[4].[1].s_reqs_reg[17][value]__0\(10),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[33][11]\(11),
- Q => \[4].[1].s_reqs_reg[17][value]__0\(11),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[33][11]\(1),
- Q => \[4].[1].s_reqs_reg[17][value]__0\(1),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[33][11]\(2),
- Q => \[4].[1].s_reqs_reg[17][value]__0\(2),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[33][11]\(3),
- Q => \[4].[1].s_reqs_reg[17][value]__0\(3),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[33][11]\(4),
- Q => \[4].[1].s_reqs_reg[17][value]__0\(4),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[33][11]\(5),
- Q => \[4].[1].s_reqs_reg[17][value]__0\(5),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[33][11]\(6),
- Q => \[4].[1].s_reqs_reg[17][value]__0\(6),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[33][11]\(7),
- Q => \[4].[1].s_reqs_reg[17][value]__0\(7),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[33][11]\(8),
- Q => \[4].[1].s_reqs_reg[17][value]__0\(8),
- R => '0'
- );
-\[4].[1].s_reqs_reg[17][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[33][11]\(9),
- Q => \[4].[1].s_reqs_reg[17][value]__0\(9),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[34][11]\(0),
- Q => \[4].[2].s_reqs_reg[18][value]__0\(0),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[34][11]\(10),
- Q => \[4].[2].s_reqs_reg[18][value]__0\(10),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[34][11]\(11),
- Q => \[4].[2].s_reqs_reg[18][value]__0\(11),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[34][11]\(1),
- Q => \[4].[2].s_reqs_reg[18][value]__0\(1),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[34][11]\(2),
- Q => \[4].[2].s_reqs_reg[18][value]__0\(2),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[34][11]\(3),
- Q => \[4].[2].s_reqs_reg[18][value]__0\(3),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[34][11]\(4),
- Q => \[4].[2].s_reqs_reg[18][value]__0\(4),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[34][11]\(5),
- Q => \[4].[2].s_reqs_reg[18][value]__0\(5),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[34][11]\(6),
- Q => \[4].[2].s_reqs_reg[18][value]__0\(6),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[34][11]\(7),
- Q => \[4].[2].s_reqs_reg[18][value]__0\(7),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[34][11]\(8),
- Q => \[4].[2].s_reqs_reg[18][value]__0\(8),
- R => '0'
- );
-\[4].[2].s_reqs_reg[18][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[34][11]\(9),
- Q => \[4].[2].s_reqs_reg[18][value]__0\(9),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[35][11]\(0),
- Q => \[4].[3].s_reqs_reg[19][value]__0\(0),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[35][11]\(10),
- Q => \[4].[3].s_reqs_reg[19][value]__0\(10),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[35][11]\(11),
- Q => \[4].[3].s_reqs_reg[19][value]__0\(11),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[35][11]\(1),
- Q => \[4].[3].s_reqs_reg[19][value]__0\(1),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[35][11]\(2),
- Q => \[4].[3].s_reqs_reg[19][value]__0\(2),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[35][11]\(3),
- Q => \[4].[3].s_reqs_reg[19][value]__0\(3),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[35][11]\(4),
- Q => \[4].[3].s_reqs_reg[19][value]__0\(4),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[35][11]\(5),
- Q => \[4].[3].s_reqs_reg[19][value]__0\(5),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[35][11]\(6),
- Q => \[4].[3].s_reqs_reg[19][value]__0\(6),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[35][11]\(7),
- Q => \[4].[3].s_reqs_reg[19][value]__0\(7),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[35][11]\(8),
- Q => \[4].[3].s_reqs_reg[19][value]__0\(8),
- R => '0'
- );
-\[4].[3].s_reqs_reg[19][value][9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[35][11]\(9),
- Q => \[4].[3].s_reqs_reg[19][value]__0\(9),
- R => '0'
- );
-cmp_spi: entity work.system_design_fasec_hwtest_0_0_spi_transceiver_130
- port map (
- D(0) => D(0),
- E(0) => cmp_spi_n_0,
- Q(0) => \s_counter_reg[2]\(0),
- SR(0) => SR(0),
- \[0].[2].s_reqs_reg[2][changed]\ => \[0].[2].s_reqs_reg[2][changed_n_0_]\,
- \[0].[2].s_reqs_reg[2][changed]_0\ => \s_state[1]_i_2_n_0\,
- \[0].[3].s_reqs_reg[3][changed]\ => \s_state[1]_i_3_n_0\,
- ch_address(1 downto 0) => ch_address(1 downto 0),
- \dac_ch_o_reg[0][31]\(31 downto 0) => rx_data_o(31 downto 0),
- \data_rw_o_reg[11][1]\ => \v_ch_address[1]_i_3_n_0\,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_spi_cs_n => s_spi_cs_n,
- s_spi_mosi => s_spi_mosi,
- s_start_reg => \^s_start\,
- \s_state_reg[0]\ => cmp_spi_n_3,
- \s_state_reg[0]_0\ => \^dac_ch_o_reg[0][0]_1\,
- \s_state_reg[1]\ => cmp_spi_n_4,
- \s_state_reg[1]_0\ => \^dac_ch_o_reg[0][0]_0\,
- \s_tx_data_reg[113]\(61) => \s_tx_data_reg_n_0_[113]\,
- \s_tx_data_reg[113]\(60) => \s_tx_data_reg_n_0_[112]\,
- \s_tx_data_reg[113]\(59) => \s_tx_data_reg_n_0_[111]\,
- \s_tx_data_reg[113]\(58) => \s_tx_data_reg_n_0_[110]\,
- \s_tx_data_reg[113]\(57) => \s_tx_data_reg_n_0_[109]\,
- \s_tx_data_reg[113]\(56) => \s_tx_data_reg_n_0_[108]\,
- \s_tx_data_reg[113]\(55) => \s_tx_data_reg_n_0_[107]\,
- \s_tx_data_reg[113]\(54) => \s_tx_data_reg_n_0_[106]\,
- \s_tx_data_reg[113]\(53) => \s_tx_data_reg_n_0_[105]\,
- \s_tx_data_reg[113]\(52) => \s_tx_data_reg_n_0_[104]\,
- \s_tx_data_reg[113]\(51) => \s_tx_data_reg_n_0_[103]\,
- \s_tx_data_reg[113]\(50) => \s_tx_data_reg_n_0_[102]\,
- \s_tx_data_reg[113]\(49) => \s_tx_data_reg_n_0_[101]\,
- \s_tx_data_reg[113]\(48) => \s_tx_data_reg_n_0_[100]\,
- \s_tx_data_reg[113]\(47) => \s_tx_data_reg_n_0_[87]\,
- \s_tx_data_reg[113]\(46) => \s_tx_data_reg_n_0_[86]\,
- \s_tx_data_reg[113]\(45) => \s_tx_data_reg_n_0_[85]\,
- \s_tx_data_reg[113]\(44) => \s_tx_data_reg_n_0_[84]\,
- \s_tx_data_reg[113]\(43) => \s_tx_data_reg_n_0_[83]\,
- \s_tx_data_reg[113]\(42) => \s_tx_data_reg_n_0_[82]\,
- \s_tx_data_reg[113]\(41) => \s_tx_data_reg_n_0_[81]\,
- \s_tx_data_reg[113]\(40) => \s_tx_data_reg_n_0_[80]\,
- \s_tx_data_reg[113]\(39) => \s_tx_data_reg_n_0_[79]\,
- \s_tx_data_reg[113]\(38) => \s_tx_data_reg_n_0_[78]\,
- \s_tx_data_reg[113]\(37) => \s_tx_data_reg_n_0_[77]\,
- \s_tx_data_reg[113]\(36) => \s_tx_data_reg_n_0_[76]\,
- \s_tx_data_reg[113]\(35) => \s_tx_data_reg_n_0_[63]\,
- \s_tx_data_reg[113]\(34) => \s_tx_data_reg_n_0_[62]\,
- \s_tx_data_reg[113]\(33) => \s_tx_data_reg_n_0_[61]\,
- \s_tx_data_reg[113]\(32) => \s_tx_data_reg_n_0_[60]\,
- \s_tx_data_reg[113]\(31) => \s_tx_data_reg_n_0_[59]\,
- \s_tx_data_reg[113]\(30) => \s_tx_data_reg_n_0_[58]\,
- \s_tx_data_reg[113]\(29) => \s_tx_data_reg_n_0_[57]\,
- \s_tx_data_reg[113]\(28) => \s_tx_data_reg_n_0_[56]\,
- \s_tx_data_reg[113]\(27) => \s_tx_data_reg_n_0_[55]\,
- \s_tx_data_reg[113]\(26) => \s_tx_data_reg_n_0_[54]\,
- \s_tx_data_reg[113]\(25) => \s_tx_data_reg_n_0_[53]\,
- \s_tx_data_reg[113]\(24) => \s_tx_data_reg_n_0_[52]\,
- \s_tx_data_reg[113]\(23) => \s_tx_data_reg_n_0_[39]\,
- \s_tx_data_reg[113]\(22) => \s_tx_data_reg_n_0_[38]\,
- \s_tx_data_reg[113]\(21) => \s_tx_data_reg_n_0_[37]\,
- \s_tx_data_reg[113]\(20) => \s_tx_data_reg_n_0_[36]\,
- \s_tx_data_reg[113]\(19) => \s_tx_data_reg_n_0_[35]\,
- \s_tx_data_reg[113]\(18) => \s_tx_data_reg_n_0_[34]\,
- \s_tx_data_reg[113]\(17) => \s_tx_data_reg_n_0_[33]\,
- \s_tx_data_reg[113]\(16) => \s_tx_data_reg_n_0_[32]\,
- \s_tx_data_reg[113]\(15) => \s_tx_data_reg_n_0_[31]\,
- \s_tx_data_reg[113]\(14) => \s_tx_data_reg_n_0_[30]\,
- \s_tx_data_reg[113]\(13) => \s_tx_data_reg_n_0_[29]\,
- \s_tx_data_reg[113]\(12) => \s_tx_data_reg_n_0_[28]\,
- \s_tx_data_reg[113]\(11) => \s_tx_data_reg_n_0_[15]\,
- \s_tx_data_reg[113]\(10) => \s_tx_data_reg_n_0_[14]\,
- \s_tx_data_reg[113]\(9) => \s_tx_data_reg_n_0_[13]\,
- \s_tx_data_reg[113]\(8) => \s_tx_data_reg_n_0_[12]\,
- \s_tx_data_reg[113]\(7) => \s_tx_data_reg_n_0_[11]\,
- \s_tx_data_reg[113]\(6) => \s_tx_data_reg_n_0_[10]\,
- \s_tx_data_reg[113]\(5) => \s_tx_data_reg_n_0_[9]\,
- \s_tx_data_reg[113]\(4) => \s_tx_data_reg_n_0_[8]\,
- \s_tx_data_reg[113]\(3) => \s_tx_data_reg_n_0_[7]\,
- \s_tx_data_reg[113]\(2) => \s_tx_data_reg_n_0_[6]\,
- \s_tx_data_reg[113]\(1) => \s_tx_data_reg_n_0_[5]\,
- \s_tx_data_reg[113]\(0) => \s_tx_data_reg_n_0_[4]\,
- \v_ch_address_reg[0]\ => cmp_spi_n_1,
- \v_ch_address_reg[0]_0\ => \dac_ch_o[0][31]_i_2_n_0\,
- \v_ch_address_reg[1]\ => cmp_spi_n_2
- );
-\dac_ch_o[0][31]_i_2\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"7"
- )
- port map (
- I0 => ch_address(0),
- I1 => ch_address(1),
- O => \dac_ch_o[0][31]_i_2_n_0\
- );
-\dac_ch_o_reg[0][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(0),
- Q => \axi_rdata_reg[31]\(0),
- R => '0'
- );
-\dac_ch_o_reg[0][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(10),
- Q => \axi_rdata_reg[31]\(10),
- R => '0'
- );
-\dac_ch_o_reg[0][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(11),
- Q => \axi_rdata_reg[31]\(11),
- R => '0'
- );
-\dac_ch_o_reg[0][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(12),
- Q => \axi_rdata_reg[31]\(12),
- R => '0'
- );
-\dac_ch_o_reg[0][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(13),
- Q => \axi_rdata_reg[31]\(13),
- R => '0'
- );
-\dac_ch_o_reg[0][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(14),
- Q => \axi_rdata_reg[31]\(14),
- R => '0'
- );
-\dac_ch_o_reg[0][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(15),
- Q => \axi_rdata_reg[31]\(15),
- R => '0'
- );
-\dac_ch_o_reg[0][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(16),
- Q => \axi_rdata_reg[31]\(16),
- R => '0'
- );
-\dac_ch_o_reg[0][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(17),
- Q => \axi_rdata_reg[31]\(17),
- R => '0'
- );
-\dac_ch_o_reg[0][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(18),
- Q => \axi_rdata_reg[31]\(18),
- R => '0'
- );
-\dac_ch_o_reg[0][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(19),
- Q => \axi_rdata_reg[31]\(19),
- R => '0'
- );
-\dac_ch_o_reg[0][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(1),
- Q => \axi_rdata_reg[31]\(1),
- R => '0'
- );
-\dac_ch_o_reg[0][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(20),
- Q => \axi_rdata_reg[31]\(20),
- R => '0'
- );
-\dac_ch_o_reg[0][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(21),
- Q => \axi_rdata_reg[31]\(21),
- R => '0'
- );
-\dac_ch_o_reg[0][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(22),
- Q => \axi_rdata_reg[31]\(22),
- R => '0'
- );
-\dac_ch_o_reg[0][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(23),
- Q => \axi_rdata_reg[31]\(23),
- R => '0'
- );
-\dac_ch_o_reg[0][24]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(24),
- Q => \axi_rdata_reg[31]\(24),
- R => '0'
- );
-\dac_ch_o_reg[0][25]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(25),
- Q => \axi_rdata_reg[31]\(25),
- R => '0'
- );
-\dac_ch_o_reg[0][26]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(26),
- Q => \axi_rdata_reg[31]\(26),
- R => '0'
- );
-\dac_ch_o_reg[0][27]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(27),
- Q => \axi_rdata_reg[31]\(27),
- R => '0'
- );
-\dac_ch_o_reg[0][28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(28),
- Q => \axi_rdata_reg[31]\(28),
- R => '0'
- );
-\dac_ch_o_reg[0][29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(29),
- Q => \axi_rdata_reg[31]\(29),
- R => '0'
- );
-\dac_ch_o_reg[0][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(2),
- Q => \axi_rdata_reg[31]\(2),
- R => '0'
- );
-\dac_ch_o_reg[0][30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(30),
- Q => \axi_rdata_reg[31]\(30),
- R => '0'
- );
-\dac_ch_o_reg[0][31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(31),
- Q => \axi_rdata_reg[31]\(31),
- R => '0'
- );
-\dac_ch_o_reg[0][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(3),
- Q => \axi_rdata_reg[31]\(3),
- R => '0'
- );
-\dac_ch_o_reg[0][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(4),
- Q => \axi_rdata_reg[31]\(4),
- R => '0'
- );
-\dac_ch_o_reg[0][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(5),
- Q => \axi_rdata_reg[31]\(5),
- R => '0'
- );
-\dac_ch_o_reg[0][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(6),
- Q => \axi_rdata_reg[31]\(6),
- R => '0'
- );
-\dac_ch_o_reg[0][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(7),
- Q => \axi_rdata_reg[31]\(7),
- R => '0'
- );
-\dac_ch_o_reg[0][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(8),
- Q => \axi_rdata_reg[31]\(8),
- R => '0'
- );
-\dac_ch_o_reg[0][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => cmp_spi_n_0,
- D => rx_data_o(9),
- Q => \axi_rdata_reg[31]\(9),
- R => '0'
- );
-\s_flag_reset[0]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFF70004"
- )
- port map (
- I0 => \^dac_ch_o_reg[0][0]_1\,
- I1 => \^dac_ch_o_reg[0][0]_0\,
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \s_flag_reset_reg_n_0_[0]\,
- O => \s_flag_reset[0]_i_1_n_0\
- );
-\s_flag_reset[1]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"DFFF1000"
- )
- port map (
- I0 => \^dac_ch_o_reg[0][0]_1\,
- I1 => ch_address(1),
- I2 => \^dac_ch_o_reg[0][0]_0\,
- I3 => ch_address(0),
- I4 => p_2_in,
- O => \s_flag_reset[1]_i_1_n_0\
- );
-\s_flag_reset[2]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FF7F0040"
- )
- port map (
- I0 => \^dac_ch_o_reg[0][0]_1\,
- I1 => \^dac_ch_o_reg[0][0]_0\,
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => p_1_in,
- O => \s_flag_reset[2]_i_1_n_0\
- );
-\s_flag_reset[3]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"7FFF4000"
- )
- port map (
- I0 => \^dac_ch_o_reg[0][0]_1\,
- I1 => \^dac_ch_o_reg[0][0]_0\,
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => p_0_in,
- O => \s_flag_reset[3]_i_1_n_0\
- );
-\s_flag_reset_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_flag_reset[0]_i_1_n_0\,
- Q => \s_flag_reset_reg_n_0_[0]\,
- R => SR(0)
- );
-\s_flag_reset_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_flag_reset[1]_i_1_n_0\,
- Q => p_2_in,
- R => SR(0)
- );
-\s_flag_reset_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_flag_reset[2]_i_1_n_0\,
- Q => p_1_in,
- R => SR(0)
- );
-\s_flag_reset_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_flag_reset[3]_i_1_n_0\,
- Q => p_0_in,
- R => SR(0)
- );
-s_start_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_start_reg_0,
- Q => \^s_start\,
- R => SR(0)
- );
-\s_state[1]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0C00080808080808"
- )
- port map (
- I0 => \[0].[2].s_reqs_reg[2][changed_n_0_]\,
- I1 => \^dac_ch_o_reg[0][0]_1\,
- I2 => \^dac_ch_o_reg[0][0]_0\,
- I3 => \[1].[3].s_reqs_reg[7][changed]__1\,
- I4 => ch_address(1),
- I5 => ch_address(0),
- O => \s_state[1]_i_2_n_0\
- );
-\s_state[1]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0000FFFE00000000"
- )
- port map (
- I0 => \[0].[3].s_reqs_reg[3][changed_n_0_]\,
- I1 => \[1].[0].s_reqs_reg[4][changed]__1\,
- I2 => \data_rw_o_reg[11][2]\(0),
- I3 => \s_state[1]_i_5_n_0\,
- I4 => \^dac_ch_o_reg[0][0]_0\,
- I5 => \^dac_ch_o_reg[0][0]_1\,
- O => \s_state[1]_i_3_n_0\
- );
-\s_state[1]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFE2F0F0FFE2"
- )
- port map (
- I0 => \[0].[0].s_reqs_reg[0][changed_n_0_]\,
- I1 => ch_address(0),
- I2 => \[1].[1].s_reqs_reg[5][changed]__1\,
- I3 => \[0].[1].s_reqs_reg[1][changed_n_0_]\,
- I4 => ch_address(1),
- I5 => \[1].[2].s_reqs_reg[6][changed]__1\,
- O => \s_state[1]_i_5_n_0\
- );
-\s_state_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => cmp_spi_n_3,
- Q => \^dac_ch_o_reg[0][0]_1\,
- R => SR(0)
- );
-\s_state_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => cmp_spi_n_4,
- Q => \^dac_ch_o_reg[0][0]_0\,
- R => SR(0)
- );
-\s_tx_data[100]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(0),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0\(0),
- I5 => \s_tx_data[100]_i_2_n_0\,
- O => \s_tx_data[100]_i_1_n_0\
- );
-\s_tx_data[100]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0\(0),
- I1 => \[4].[1].s_reqs_reg[17][value]__0\(0),
- I2 => \[4].[2].s_reqs_reg[18][value]__0\(0),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[100]_i_2_n_0\
- );
-\s_tx_data[101]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(1),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0\(1),
- I5 => \s_tx_data[101]_i_2_n_0\,
- O => \s_tx_data[101]_i_1_n_0\
- );
-\s_tx_data[101]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0\(1),
- I1 => \[4].[1].s_reqs_reg[17][value]__0\(1),
- I2 => \[4].[2].s_reqs_reg[18][value]__0\(1),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[101]_i_2_n_0\
- );
-\s_tx_data[102]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(2),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0\(2),
- I5 => \s_tx_data[102]_i_2_n_0\,
- O => \s_tx_data[102]_i_1_n_0\
- );
-\s_tx_data[102]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0\(2),
- I1 => \[4].[1].s_reqs_reg[17][value]__0\(2),
- I2 => \[4].[2].s_reqs_reg[18][value]__0\(2),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[102]_i_2_n_0\
- );
-\s_tx_data[103]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(3),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0\(3),
- I5 => \s_tx_data[103]_i_2_n_0\,
- O => \s_tx_data[103]_i_1_n_0\
- );
-\s_tx_data[103]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0\(3),
- I1 => \[4].[1].s_reqs_reg[17][value]__0\(3),
- I2 => \[4].[2].s_reqs_reg[18][value]__0\(3),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[103]_i_2_n_0\
- );
-\s_tx_data[104]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(4),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0\(4),
- I5 => \s_tx_data[104]_i_2_n_0\,
- O => \s_tx_data[104]_i_1_n_0\
- );
-\s_tx_data[104]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0\(4),
- I1 => \[4].[1].s_reqs_reg[17][value]__0\(4),
- I2 => \[4].[2].s_reqs_reg[18][value]__0\(4),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[104]_i_2_n_0\
- );
-\s_tx_data[105]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(5),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0\(5),
- I5 => \s_tx_data[105]_i_2_n_0\,
- O => \s_tx_data[105]_i_1_n_0\
- );
-\s_tx_data[105]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0\(5),
- I1 => \[4].[1].s_reqs_reg[17][value]__0\(5),
- I2 => \[4].[2].s_reqs_reg[18][value]__0\(5),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[105]_i_2_n_0\
- );
-\s_tx_data[106]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(6),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0\(6),
- I5 => \s_tx_data[106]_i_2_n_0\,
- O => \s_tx_data[106]_i_1_n_0\
- );
-\s_tx_data[106]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0\(6),
- I1 => \[4].[1].s_reqs_reg[17][value]__0\(6),
- I2 => \[4].[2].s_reqs_reg[18][value]__0\(6),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[106]_i_2_n_0\
- );
-\s_tx_data[107]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(7),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0\(7),
- I5 => \s_tx_data[107]_i_2_n_0\,
- O => \s_tx_data[107]_i_1_n_0\
- );
-\s_tx_data[107]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0\(7),
- I1 => \[4].[1].s_reqs_reg[17][value]__0\(7),
- I2 => \[4].[2].s_reqs_reg[18][value]__0\(7),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[107]_i_2_n_0\
- );
-\s_tx_data[108]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(8),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0\(8),
- I5 => \s_tx_data[108]_i_2_n_0\,
- O => \s_tx_data[108]_i_1_n_0\
- );
-\s_tx_data[108]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0\(8),
- I1 => \[4].[1].s_reqs_reg[17][value]__0\(8),
- I2 => \[4].[2].s_reqs_reg[18][value]__0\(8),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[108]_i_2_n_0\
- );
-\s_tx_data[109]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(9),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0\(9),
- I5 => \s_tx_data[109]_i_2_n_0\,
- O => \s_tx_data[109]_i_1_n_0\
- );
-\s_tx_data[109]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0\(9),
- I1 => \[4].[1].s_reqs_reg[17][value]__0\(9),
- I2 => \[4].[2].s_reqs_reg[18][value]__0\(9),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[109]_i_2_n_0\
- );
-\s_tx_data[10]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(6),
- I1 => \data_rw_o_reg[11][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[10]_i_2_n_0\,
- O => \s_reqs[0][value]\(6)
- );
-\s_tx_data[10]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(6),
- I1 => \^s_tx_data_reg[15]_0\(6),
- I2 => \^s_tx_data_reg[15]_1\(6),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[10]_i_2_n_0\
- );
-\s_tx_data[110]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(10),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0\(10),
- I5 => \s_tx_data[110]_i_2_n_0\,
- O => \s_tx_data[110]_i_1_n_0\
- );
-\s_tx_data[110]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0\(10),
- I1 => \[4].[1].s_reqs_reg[17][value]__0\(10),
- I2 => \[4].[2].s_reqs_reg[18][value]__0\(10),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[110]_i_2_n_0\
- );
-\s_tx_data[111]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(11),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[4].[3].s_reqs_reg[19][value]__0\(11),
- I5 => \s_tx_data[111]_i_2_n_0\,
- O => \s_tx_data[111]_i_1_n_0\
- );
-\s_tx_data[111]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[4].[0].s_reqs_reg[16][value]__0\(11),
- I1 => \[4].[1].s_reqs_reg[17][value]__0\(11),
- I2 => \[4].[2].s_reqs_reg[18][value]__0\(11),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[111]_i_2_n_0\
- );
-\s_tx_data[113]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"40"
- )
- port map (
- I0 => \^dac_ch_o_reg[0][0]_1\,
- I1 => \^dac_ch_o_reg[0][0]_0\,
- I2 => s00_axi_aresetn,
- O => \s_tx_data[113]_i_1_n_0\
- );
-\s_tx_data[11]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(7),
- I1 => \data_rw_o_reg[11][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[11]_i_2_n_0\,
- O => \s_reqs[0][value]\(7)
- );
-\s_tx_data[11]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(7),
- I1 => \^s_tx_data_reg[15]_0\(7),
- I2 => \^s_tx_data_reg[15]_1\(7),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[11]_i_2_n_0\
- );
-\s_tx_data[12]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(8),
- I1 => \data_rw_o_reg[11][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[12]_i_2_n_0\,
- O => \s_reqs[0][value]\(8)
- );
-\s_tx_data[12]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(8),
- I1 => \^s_tx_data_reg[15]_0\(8),
- I2 => \^s_tx_data_reg[15]_1\(8),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[12]_i_2_n_0\
- );
-\s_tx_data[13]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(9),
- I1 => \data_rw_o_reg[11][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[13]_i_2_n_0\,
- O => \s_reqs[0][value]\(9)
- );
-\s_tx_data[13]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(9),
- I1 => \^s_tx_data_reg[15]_0\(9),
- I2 => \^s_tx_data_reg[15]_1\(9),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[13]_i_2_n_0\
- );
-\s_tx_data[14]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(10),
- I1 => \data_rw_o_reg[11][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[14]_i_2_n_0\,
- O => \s_reqs[0][value]\(10)
- );
-\s_tx_data[14]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(10),
- I1 => \^s_tx_data_reg[15]_0\(10),
- I2 => \^s_tx_data_reg[15]_1\(10),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[14]_i_2_n_0\
- );
-\s_tx_data[15]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(11),
- I1 => \data_rw_o_reg[11][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[15]_i_2_n_0\,
- O => \s_reqs[0][value]\(11)
- );
-\s_tx_data[15]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(11),
- I1 => \^s_tx_data_reg[15]_0\(11),
- I2 => \^s_tx_data_reg[15]_1\(11),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[15]_i_2_n_0\
- );
-\s_tx_data[28]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(0),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(0),
- I5 => \s_tx_data[28]_i_2_n_0\,
- O => \s_tx_data[28]_i_1_n_0\
- );
-\s_tx_data[28]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(0),
- I1 => \^s_tx_data_reg[39]_2\(0),
- I2 => \^s_tx_data_reg[39]_3\(0),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[28]_i_2_n_0\
- );
-\s_tx_data[29]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(1),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(1),
- I5 => \s_tx_data[29]_i_2_n_0\,
- O => \s_tx_data[29]_i_1_n_0\
- );
-\s_tx_data[29]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(1),
- I1 => \^s_tx_data_reg[39]_2\(1),
- I2 => \^s_tx_data_reg[39]_3\(1),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[29]_i_2_n_0\
- );
-\s_tx_data[30]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(2),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(2),
- I5 => \s_tx_data[30]_i_2_n_0\,
- O => \s_tx_data[30]_i_1_n_0\
- );
-\s_tx_data[30]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(2),
- I1 => \^s_tx_data_reg[39]_2\(2),
- I2 => \^s_tx_data_reg[39]_3\(2),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[30]_i_2_n_0\
- );
-\s_tx_data[31]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(3),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(3),
- I5 => \s_tx_data[31]_i_2_n_0\,
- O => \s_tx_data[31]_i_1_n_0\
- );
-\s_tx_data[31]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(3),
- I1 => \^s_tx_data_reg[39]_2\(3),
- I2 => \^s_tx_data_reg[39]_3\(3),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[31]_i_2_n_0\
- );
-\s_tx_data[32]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(4),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(4),
- I5 => \s_tx_data[32]_i_2_n_0\,
- O => \s_tx_data[32]_i_1_n_0\
- );
-\s_tx_data[32]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(4),
- I1 => \^s_tx_data_reg[39]_2\(4),
- I2 => \^s_tx_data_reg[39]_3\(4),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[32]_i_2_n_0\
- );
-\s_tx_data[33]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(5),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(5),
- I5 => \s_tx_data[33]_i_2_n_0\,
- O => \s_tx_data[33]_i_1_n_0\
- );
-\s_tx_data[33]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(5),
- I1 => \^s_tx_data_reg[39]_2\(5),
- I2 => \^s_tx_data_reg[39]_3\(5),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[33]_i_2_n_0\
- );
-\s_tx_data[34]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(6),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(6),
- I5 => \s_tx_data[34]_i_2_n_0\,
- O => \s_tx_data[34]_i_1_n_0\
- );
-\s_tx_data[34]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(6),
- I1 => \^s_tx_data_reg[39]_2\(6),
- I2 => \^s_tx_data_reg[39]_3\(6),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[34]_i_2_n_0\
- );
-\s_tx_data[35]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(7),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(7),
- I5 => \s_tx_data[35]_i_2_n_0\,
- O => \s_tx_data[35]_i_1_n_0\
- );
-\s_tx_data[35]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(7),
- I1 => \^s_tx_data_reg[39]_2\(7),
- I2 => \^s_tx_data_reg[39]_3\(7),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[35]_i_2_n_0\
- );
-\s_tx_data[36]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(8),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(8),
- I5 => \s_tx_data[36]_i_2_n_0\,
- O => \s_tx_data[36]_i_1_n_0\
- );
-\s_tx_data[36]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(8),
- I1 => \^s_tx_data_reg[39]_2\(8),
- I2 => \^s_tx_data_reg[39]_3\(8),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[36]_i_2_n_0\
- );
-\s_tx_data[37]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(9),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(9),
- I5 => \s_tx_data[37]_i_2_n_0\,
- O => \s_tx_data[37]_i_1_n_0\
- );
-\s_tx_data[37]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(9),
- I1 => \^s_tx_data_reg[39]_2\(9),
- I2 => \^s_tx_data_reg[39]_3\(9),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[37]_i_2_n_0\
- );
-\s_tx_data[38]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(10),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(10),
- I5 => \s_tx_data[38]_i_2_n_0\,
- O => \s_tx_data[38]_i_1_n_0\
- );
-\s_tx_data[38]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(10),
- I1 => \^s_tx_data_reg[39]_2\(10),
- I2 => \^s_tx_data_reg[39]_3\(10),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[38]_i_2_n_0\
- );
-\s_tx_data[39]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(11),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \^s_tx_data_reg[39]_0\(11),
- I5 => \s_tx_data[39]_i_2_n_0\,
- O => \s_tx_data[39]_i_1_n_0\
- );
-\s_tx_data[39]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[39]_1\(11),
- I1 => \^s_tx_data_reg[39]_2\(11),
- I2 => \^s_tx_data_reg[39]_3\(11),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[39]_i_2_n_0\
- );
-\s_tx_data[4]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(0),
- I1 => \data_rw_o_reg[11][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[4]_i_2_n_0\,
- O => \s_reqs[0][value]\(0)
- );
-\s_tx_data[4]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(0),
- I1 => \^s_tx_data_reg[15]_0\(0),
- I2 => \^s_tx_data_reg[15]_1\(0),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[4]_i_2_n_0\
- );
-\s_tx_data[52]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(0),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0\(0),
- I5 => \s_tx_data[52]_i_2_n_0\,
- O => \s_tx_data[52]_i_1_n_0\
- );
-\s_tx_data[52]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0\(0),
- I1 => \[2].[1].s_reqs_reg[9][value]__0\(0),
- I2 => \[2].[2].s_reqs_reg[10][value]__0\(0),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[52]_i_2_n_0\
- );
-\s_tx_data[53]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(1),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0\(1),
- I5 => \s_tx_data[53]_i_2_n_0\,
- O => \s_tx_data[53]_i_1_n_0\
- );
-\s_tx_data[53]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0\(1),
- I1 => \[2].[1].s_reqs_reg[9][value]__0\(1),
- I2 => \[2].[2].s_reqs_reg[10][value]__0\(1),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[53]_i_2_n_0\
- );
-\s_tx_data[54]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(2),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0\(2),
- I5 => \s_tx_data[54]_i_2_n_0\,
- O => \s_tx_data[54]_i_1_n_0\
- );
-\s_tx_data[54]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0\(2),
- I1 => \[2].[1].s_reqs_reg[9][value]__0\(2),
- I2 => \[2].[2].s_reqs_reg[10][value]__0\(2),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[54]_i_2_n_0\
- );
-\s_tx_data[55]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(3),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0\(3),
- I5 => \s_tx_data[55]_i_2_n_0\,
- O => \s_tx_data[55]_i_1_n_0\
- );
-\s_tx_data[55]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0\(3),
- I1 => \[2].[1].s_reqs_reg[9][value]__0\(3),
- I2 => \[2].[2].s_reqs_reg[10][value]__0\(3),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[55]_i_2_n_0\
- );
-\s_tx_data[56]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(4),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0\(4),
- I5 => \s_tx_data[56]_i_2_n_0\,
- O => \s_tx_data[56]_i_1_n_0\
- );
-\s_tx_data[56]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0\(4),
- I1 => \[2].[1].s_reqs_reg[9][value]__0\(4),
- I2 => \[2].[2].s_reqs_reg[10][value]__0\(4),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[56]_i_2_n_0\
- );
-\s_tx_data[57]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(5),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0\(5),
- I5 => \s_tx_data[57]_i_2_n_0\,
- O => \s_tx_data[57]_i_1_n_0\
- );
-\s_tx_data[57]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0\(5),
- I1 => \[2].[1].s_reqs_reg[9][value]__0\(5),
- I2 => \[2].[2].s_reqs_reg[10][value]__0\(5),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[57]_i_2_n_0\
- );
-\s_tx_data[58]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(6),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0\(6),
- I5 => \s_tx_data[58]_i_2_n_0\,
- O => \s_tx_data[58]_i_1_n_0\
- );
-\s_tx_data[58]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0\(6),
- I1 => \[2].[1].s_reqs_reg[9][value]__0\(6),
- I2 => \[2].[2].s_reqs_reg[10][value]__0\(6),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[58]_i_2_n_0\
- );
-\s_tx_data[59]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(7),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0\(7),
- I5 => \s_tx_data[59]_i_2_n_0\,
- O => \s_tx_data[59]_i_1_n_0\
- );
-\s_tx_data[59]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0\(7),
- I1 => \[2].[1].s_reqs_reg[9][value]__0\(7),
- I2 => \[2].[2].s_reqs_reg[10][value]__0\(7),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[59]_i_2_n_0\
- );
-\s_tx_data[5]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(1),
- I1 => \data_rw_o_reg[11][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[5]_i_2_n_0\,
- O => \s_reqs[0][value]\(1)
- );
-\s_tx_data[5]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(1),
- I1 => \^s_tx_data_reg[15]_0\(1),
- I2 => \^s_tx_data_reg[15]_1\(1),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[5]_i_2_n_0\
- );
-\s_tx_data[60]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(8),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0\(8),
- I5 => \s_tx_data[60]_i_2_n_0\,
- O => \s_tx_data[60]_i_1_n_0\
- );
-\s_tx_data[60]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0\(8),
- I1 => \[2].[1].s_reqs_reg[9][value]__0\(8),
- I2 => \[2].[2].s_reqs_reg[10][value]__0\(8),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[60]_i_2_n_0\
- );
-\s_tx_data[61]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(9),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0\(9),
- I5 => \s_tx_data[61]_i_2_n_0\,
- O => \s_tx_data[61]_i_1_n_0\
- );
-\s_tx_data[61]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0\(9),
- I1 => \[2].[1].s_reqs_reg[9][value]__0\(9),
- I2 => \[2].[2].s_reqs_reg[10][value]__0\(9),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[61]_i_2_n_0\
- );
-\s_tx_data[62]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(10),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0\(10),
- I5 => \s_tx_data[62]_i_2_n_0\,
- O => \s_tx_data[62]_i_1_n_0\
- );
-\s_tx_data[62]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0\(10),
- I1 => \[2].[1].s_reqs_reg[9][value]__0\(10),
- I2 => \[2].[2].s_reqs_reg[10][value]__0\(10),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[62]_i_2_n_0\
- );
-\s_tx_data[63]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(11),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[2].[3].s_reqs_reg[11][value]__0\(11),
- I5 => \s_tx_data[63]_i_2_n_0\,
- O => \s_tx_data[63]_i_1_n_0\
- );
-\s_tx_data[63]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[2].[0].s_reqs_reg[8][value]__0\(11),
- I1 => \[2].[1].s_reqs_reg[9][value]__0\(11),
- I2 => \[2].[2].s_reqs_reg[10][value]__0\(11),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[63]_i_2_n_0\
- );
-\s_tx_data[6]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(2),
- I1 => \data_rw_o_reg[11][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[6]_i_2_n_0\,
- O => \s_reqs[0][value]\(2)
- );
-\s_tx_data[6]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(2),
- I1 => \^s_tx_data_reg[15]_0\(2),
- I2 => \^s_tx_data_reg[15]_1\(2),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[6]_i_2_n_0\
- );
-\s_tx_data[76]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(0),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0\(0),
- I5 => \s_tx_data[76]_i_2_n_0\,
- O => \s_tx_data[76]_i_1_n_0\
- );
-\s_tx_data[76]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0\(0),
- I1 => \[3].[1].s_reqs_reg[13][value]__0\(0),
- I2 => \[3].[2].s_reqs_reg[14][value]__0\(0),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[76]_i_2_n_0\
- );
-\s_tx_data[77]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(1),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0\(1),
- I5 => \s_tx_data[77]_i_2_n_0\,
- O => \s_tx_data[77]_i_1_n_0\
- );
-\s_tx_data[77]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0\(1),
- I1 => \[3].[1].s_reqs_reg[13][value]__0\(1),
- I2 => \[3].[2].s_reqs_reg[14][value]__0\(1),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[77]_i_2_n_0\
- );
-\s_tx_data[78]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(2),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0\(2),
- I5 => \s_tx_data[78]_i_2_n_0\,
- O => \s_tx_data[78]_i_1_n_0\
- );
-\s_tx_data[78]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0\(2),
- I1 => \[3].[1].s_reqs_reg[13][value]__0\(2),
- I2 => \[3].[2].s_reqs_reg[14][value]__0\(2),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[78]_i_2_n_0\
- );
-\s_tx_data[79]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(3),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0\(3),
- I5 => \s_tx_data[79]_i_2_n_0\,
- O => \s_tx_data[79]_i_1_n_0\
- );
-\s_tx_data[79]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0\(3),
- I1 => \[3].[1].s_reqs_reg[13][value]__0\(3),
- I2 => \[3].[2].s_reqs_reg[14][value]__0\(3),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[79]_i_2_n_0\
- );
-\s_tx_data[7]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(3),
- I1 => \data_rw_o_reg[11][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[7]_i_2_n_0\,
- O => \s_reqs[0][value]\(3)
- );
-\s_tx_data[7]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(3),
- I1 => \^s_tx_data_reg[15]_0\(3),
- I2 => \^s_tx_data_reg[15]_1\(3),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[7]_i_2_n_0\
- );
-\s_tx_data[80]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(4),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0\(4),
- I5 => \s_tx_data[80]_i_2_n_0\,
- O => \s_tx_data[80]_i_1_n_0\
- );
-\s_tx_data[80]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0\(4),
- I1 => \[3].[1].s_reqs_reg[13][value]__0\(4),
- I2 => \[3].[2].s_reqs_reg[14][value]__0\(4),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[80]_i_2_n_0\
- );
-\s_tx_data[81]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(5),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0\(5),
- I5 => \s_tx_data[81]_i_2_n_0\,
- O => \s_tx_data[81]_i_1_n_0\
- );
-\s_tx_data[81]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0\(5),
- I1 => \[3].[1].s_reqs_reg[13][value]__0\(5),
- I2 => \[3].[2].s_reqs_reg[14][value]__0\(5),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[81]_i_2_n_0\
- );
-\s_tx_data[82]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(6),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0\(6),
- I5 => \s_tx_data[82]_i_2_n_0\,
- O => \s_tx_data[82]_i_1_n_0\
- );
-\s_tx_data[82]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0\(6),
- I1 => \[3].[1].s_reqs_reg[13][value]__0\(6),
- I2 => \[3].[2].s_reqs_reg[14][value]__0\(6),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[82]_i_2_n_0\
- );
-\s_tx_data[83]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(7),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0\(7),
- I5 => \s_tx_data[83]_i_2_n_0\,
- O => \s_tx_data[83]_i_1_n_0\
- );
-\s_tx_data[83]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0\(7),
- I1 => \[3].[1].s_reqs_reg[13][value]__0\(7),
- I2 => \[3].[2].s_reqs_reg[14][value]__0\(7),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[83]_i_2_n_0\
- );
-\s_tx_data[84]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(8),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0\(8),
- I5 => \s_tx_data[84]_i_2_n_0\,
- O => \s_tx_data[84]_i_1_n_0\
- );
-\s_tx_data[84]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0\(8),
- I1 => \[3].[1].s_reqs_reg[13][value]__0\(8),
- I2 => \[3].[2].s_reqs_reg[14][value]__0\(8),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[84]_i_2_n_0\
- );
-\s_tx_data[85]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(9),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0\(9),
- I5 => \s_tx_data[85]_i_2_n_0\,
- O => \s_tx_data[85]_i_1_n_0\
- );
-\s_tx_data[85]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0\(9),
- I1 => \[3].[1].s_reqs_reg[13][value]__0\(9),
- I2 => \[3].[2].s_reqs_reg[14][value]__0\(9),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[85]_i_2_n_0\
- );
-\s_tx_data[86]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(10),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0\(10),
- I5 => \s_tx_data[86]_i_2_n_0\,
- O => \s_tx_data[86]_i_1_n_0\
- );
-\s_tx_data[86]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0\(10),
- I1 => \[3].[1].s_reqs_reg[13][value]__0\(10),
- I2 => \[3].[2].s_reqs_reg[14][value]__0\(10),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[86]_i_2_n_0\
- );
-\s_tx_data[87]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFD8888888"
- )
- port map (
- I0 => \data_rw_o_reg[11][2]\(1),
- I1 => \^s_tx_data_reg[111]_0\(11),
- I2 => ch_address(1),
- I3 => ch_address(0),
- I4 => \[3].[3].s_reqs_reg[15][value]__0\(11),
- I5 => \s_tx_data[87]_i_2_n_0\,
- O => \s_tx_data[87]_i_1_n_0\
- );
-\s_tx_data[87]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"000000F00000CCAA"
- )
- port map (
- I0 => \[3].[0].s_reqs_reg[12][value]__0\(11),
- I1 => \[3].[1].s_reqs_reg[13][value]__0\(11),
- I2 => \[3].[2].s_reqs_reg[14][value]__0\(11),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[87]_i_2_n_0\
- );
-\s_tx_data[8]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(4),
- I1 => \data_rw_o_reg[11][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[8]_i_2_n_0\,
- O => \s_reqs[0][value]\(4)
- );
-\s_tx_data[8]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(4),
- I1 => \^s_tx_data_reg[15]_0\(4),
- I2 => \^s_tx_data_reg[15]_1\(4),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[8]_i_2_n_0\
- );
-\s_tx_data[9]_i_1\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"FFFF2000"
- )
- port map (
- I0 => \^q\(5),
- I1 => \data_rw_o_reg[11][2]\(1),
- I2 => ch_address(0),
- I3 => ch_address(1),
- I4 => \s_tx_data[9]_i_2_n_0\,
- O => \s_reqs[0][value]\(5)
- );
-\s_tx_data[9]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AAAA00F0AAAACCAA"
- )
- port map (
- I0 => \^s_tx_data_reg[111]_0\(5),
- I1 => \^s_tx_data_reg[15]_0\(5),
- I2 => \^s_tx_data_reg[15]_1\(5),
- I3 => ch_address(0),
- I4 => \data_rw_o_reg[11][2]\(1),
- I5 => ch_address(1),
- O => \s_tx_data[9]_i_2_n_0\
- );
-\s_tx_data_reg[100]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[100]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[100]\,
- R => '0'
- );
-\s_tx_data_reg[101]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[101]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[101]\,
- R => '0'
- );
-\s_tx_data_reg[102]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[102]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[102]\,
- R => '0'
- );
-\s_tx_data_reg[103]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[103]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[103]\,
- R => '0'
- );
-\s_tx_data_reg[104]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[104]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[104]\,
- R => '0'
- );
-\s_tx_data_reg[105]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[105]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[105]\,
- R => '0'
- );
-\s_tx_data_reg[106]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[106]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[106]\,
- R => '0'
- );
-\s_tx_data_reg[107]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[107]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[107]\,
- R => '0'
- );
-\s_tx_data_reg[108]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[108]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[108]\,
- R => '0'
- );
-\s_tx_data_reg[109]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[109]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[109]\,
- R => '0'
- );
-\s_tx_data_reg[10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_reqs[0][value]\(6),
- Q => \s_tx_data_reg_n_0_[10]\,
- R => '0'
- );
-\s_tx_data_reg[110]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[110]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[110]\,
- R => '0'
- );
-\s_tx_data_reg[111]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[111]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[111]\,
- R => '0'
- );
-\s_tx_data_reg[112]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => ch_address(0),
- Q => \s_tx_data_reg_n_0_[112]\,
- R => '0'
- );
-\s_tx_data_reg[113]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => ch_address(1),
- Q => \s_tx_data_reg_n_0_[113]\,
- R => '0'
- );
-\s_tx_data_reg[11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_reqs[0][value]\(7),
- Q => \s_tx_data_reg_n_0_[11]\,
- R => '0'
- );
-\s_tx_data_reg[12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_reqs[0][value]\(8),
- Q => \s_tx_data_reg_n_0_[12]\,
- R => '0'
- );
-\s_tx_data_reg[13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_reqs[0][value]\(9),
- Q => \s_tx_data_reg_n_0_[13]\,
- R => '0'
- );
-\s_tx_data_reg[14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_reqs[0][value]\(10),
- Q => \s_tx_data_reg_n_0_[14]\,
- R => '0'
- );
-\s_tx_data_reg[15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_reqs[0][value]\(11),
- Q => \s_tx_data_reg_n_0_[15]\,
- R => '0'
- );
-\s_tx_data_reg[28]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[28]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[28]\,
- R => '0'
- );
-\s_tx_data_reg[29]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[29]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[29]\,
- R => '0'
- );
-\s_tx_data_reg[30]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[30]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[30]\,
- R => '0'
- );
-\s_tx_data_reg[31]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[31]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[31]\,
- R => '0'
- );
-\s_tx_data_reg[32]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[32]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[32]\,
- R => '0'
- );
-\s_tx_data_reg[33]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[33]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[33]\,
- R => '0'
- );
-\s_tx_data_reg[34]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[34]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[34]\,
- R => '0'
- );
-\s_tx_data_reg[35]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[35]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[35]\,
- R => '0'
- );
-\s_tx_data_reg[36]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[36]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[36]\,
- R => '0'
- );
-\s_tx_data_reg[37]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[37]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[37]\,
- R => '0'
- );
-\s_tx_data_reg[38]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[38]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[38]\,
- R => '0'
- );
-\s_tx_data_reg[39]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[39]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[39]\,
- R => '0'
- );
-\s_tx_data_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_reqs[0][value]\(0),
- Q => \s_tx_data_reg_n_0_[4]\,
- R => '0'
- );
-\s_tx_data_reg[52]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[52]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[52]\,
- R => '0'
- );
-\s_tx_data_reg[53]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[53]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[53]\,
- R => '0'
- );
-\s_tx_data_reg[54]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[54]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[54]\,
- R => '0'
- );
-\s_tx_data_reg[55]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[55]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[55]\,
- R => '0'
- );
-\s_tx_data_reg[56]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[56]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[56]\,
- R => '0'
- );
-\s_tx_data_reg[57]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[57]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[57]\,
- R => '0'
- );
-\s_tx_data_reg[58]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[58]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[58]\,
- R => '0'
- );
-\s_tx_data_reg[59]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[59]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[59]\,
- R => '0'
- );
-\s_tx_data_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_reqs[0][value]\(1),
- Q => \s_tx_data_reg_n_0_[5]\,
- R => '0'
- );
-\s_tx_data_reg[60]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[60]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[60]\,
- R => '0'
- );
-\s_tx_data_reg[61]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[61]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[61]\,
- R => '0'
- );
-\s_tx_data_reg[62]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[62]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[62]\,
- R => '0'
- );
-\s_tx_data_reg[63]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[63]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[63]\,
- R => '0'
- );
-\s_tx_data_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_reqs[0][value]\(2),
- Q => \s_tx_data_reg_n_0_[6]\,
- R => '0'
- );
-\s_tx_data_reg[76]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[76]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[76]\,
- R => '0'
- );
-\s_tx_data_reg[77]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[77]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[77]\,
- R => '0'
- );
-\s_tx_data_reg[78]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[78]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[78]\,
- R => '0'
- );
-\s_tx_data_reg[79]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[79]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[79]\,
- R => '0'
- );
-\s_tx_data_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_reqs[0][value]\(3),
- Q => \s_tx_data_reg_n_0_[7]\,
- R => '0'
- );
-\s_tx_data_reg[80]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[80]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[80]\,
- R => '0'
- );
-\s_tx_data_reg[81]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[81]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[81]\,
- R => '0'
- );
-\s_tx_data_reg[82]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[82]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[82]\,
- R => '0'
- );
-\s_tx_data_reg[83]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[83]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[83]\,
- R => '0'
- );
-\s_tx_data_reg[84]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[84]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[84]\,
- R => '0'
- );
-\s_tx_data_reg[85]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[85]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[85]\,
- R => '0'
- );
-\s_tx_data_reg[86]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[86]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[86]\,
- R => '0'
- );
-\s_tx_data_reg[87]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_tx_data[87]_i_1_n_0\,
- Q => \s_tx_data_reg_n_0_[87]\,
- R => '0'
- );
-\s_tx_data_reg[8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_reqs[0][value]\(4),
- Q => \s_tx_data_reg_n_0_[8]\,
- R => '0'
- );
-\s_tx_data_reg[9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \s_tx_data[113]_i_1_n_0\,
- D => \s_reqs[0][value]\(5),
- Q => \s_tx_data_reg_n_0_[9]\,
- R => '0'
- );
-\v_ch_address[1]_i_3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"00000002FFFFFFFF"
- )
- port map (
- I0 => \v_ch_address[1]_i_5_n_0\,
- I1 => \data_rw_o_reg[11][2]\(0),
- I2 => \[1].[0].s_reqs_reg[4][changed]__1\,
- I3 => \[0].[3].s_reqs_reg[3][changed_n_0_]\,
- I4 => \[0].[2].s_reqs_reg[2][changed_n_0_]\,
- I5 => \^dac_ch_o_reg[0][0]_1\,
- O => \v_ch_address[1]_i_3_n_0\
- );
-\v_ch_address[1]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"0003000000033355"
- )
- port map (
- I0 => \[0].[0].s_reqs_reg[0][changed_n_0_]\,
- I1 => \[1].[1].s_reqs_reg[5][changed]__1\,
- I2 => \[1].[2].s_reqs_reg[6][changed]__1\,
- I3 => ch_address(0),
- I4 => ch_address(1),
- I5 => \[0].[1].s_reqs_reg[1][changed_n_0_]\,
- O => \v_ch_address[1]_i_5_n_0\
- );
-\v_ch_address_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => cmp_spi_n_1,
- Q => ch_address(0),
- R => '0'
- );
-\v_ch_address_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => cmp_spi_n_2,
- Q => ch_address(1),
- R => '0'
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure is
- port (
- \s_datao_fmc2[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- \v_dout_reg[7]\ : out STD_LOGIC;
- S : out STD_LOGIC_VECTOR ( 0 to 0 );
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_0 : in STD_LOGIC;
- \data_rw_o_reg[79][7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \v_cmp_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_5 : STD_LOGIC;
- signal \^s_datao_fmc2[4]\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- \s_datao_fmc2[4]\(0) <= \^s_datao_fmc2[4]\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_98
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_99\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_5,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_datao_fmc2[4]\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_100
- port map (
- E(0) => \^e\(0),
- \data_rw_o_reg[79][7]\(0) => \data_rw_o_reg[79][7]\(0),
- intr_o_reg(0) => intr_o_reg(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff2_reg_1(1 downto 0) => s_buff2_reg_0(1 downto 0),
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_0 => s_comparators_i_0,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_5,
- s_pulseLed_reg_0 => \^s_datao_fmc2[4]\(0),
- \v_cmp_reg[2]\(2 downto 0) => \v_cmp_reg[2]\(2 downto 0),
- \v_dout_reg[7]\ => \v_dout_reg[7]\
- );
-\intr_led_o_i_13__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => Q(0),
- I1 => \^s_datao_fmc2[4]\(0),
- I2 => s_pulseLed_reg_0(1),
- I3 => Q(2),
- I4 => s_pulseLed_reg_0(0),
- I5 => Q(1),
- O => S(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_datao_fmc2[4]\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_1 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_10 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_1 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_1;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_1 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_95
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_96\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_97
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_10 => s_comparators_i_10,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_10 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_19 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_10 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_10;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_10 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_68
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_69\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_70
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_19 => s_comparators_i_19,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_101 is
- port (
- \s_datao_fmc1[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- \v_dout_reg[7]\ : out STD_LOGIC;
- S : out STD_LOGIC_VECTOR ( 0 to 0 );
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_0 : in STD_LOGIC;
- \data_rw_o_reg[11][7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \v_cmp_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_101 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_101;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_101 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_5 : STD_LOGIC;
- signal \^s_datao_fmc1[4]\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- \s_datao_fmc1[4]\(0) <= \^s_datao_fmc1[4]\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_204
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_205\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_5,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_datao_fmc1[4]\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_206
- port map (
- E(0) => \^e\(0),
- SR(0) => SR(0),
- \data_rw_o_reg[11][7]\(0) => \data_rw_o_reg[11][7]\(0),
- intr_o_reg(0) => intr_o_reg(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff2_reg_1(1 downto 0) => s_buff2_reg_0(1 downto 0),
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_0 => s_comparators_i_0,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_5,
- s_pulseLed_reg_0 => \^s_datao_fmc1[4]\(0),
- \v_cmp_reg[2]\(2 downto 0) => \v_cmp_reg[2]\(2 downto 0),
- \v_dout_reg[7]\ => \v_dout_reg[7]\
- );
-intr_led_o_i_13: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => Q(0),
- I1 => \^s_datao_fmc1[4]\(0),
- I2 => s_pulseLed_reg_0(1),
- I3 => Q(2),
- I4 => s_pulseLed_reg_0(0),
- I5 => Q(1),
- O => S(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_datao_fmc1[4]\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_102 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_10 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_102 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_102;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_102 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_201
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_202\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_203
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_10 => s_comparators_i_10,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_103 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_11 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_103 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_103;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_103 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_198
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_199\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_200
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_11 => s_comparators_i_11,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_104 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- S : out STD_LOGIC_VECTOR ( 0 to 0 );
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_12 : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \v_cmp_reg[14]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_104 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_104;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_104 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_4 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_195
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_196\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_197
- port map (
- E(0) => \^e\(0),
- SR(0) => SR(0),
- intr_o_reg(0) => intr_o_reg(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff2_reg_1(1 downto 0) => s_buff2_reg_0(1 downto 0),
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_12 => s_comparators_i_12,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg_0 => \^d\(0),
- \v_cmp_reg[14]\(2 downto 0) => \v_cmp_reg[14]\(2 downto 0)
- );
-intr_led_o_i_7: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => Q(0),
- I1 => \^d\(0),
- I2 => s_pulseLed_reg_0(1),
- I3 => Q(2),
- I4 => s_pulseLed_reg_0(0),
- I5 => Q(1),
- O => S(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_105 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_13 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_105 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_105;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_105 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_192
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_193\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_194
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_13 => s_comparators_i_13,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_106 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_14 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_106 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_106;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_106 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_189
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_190\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_191
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_14 => s_comparators_i_14,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_107 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- S : out STD_LOGIC_VECTOR ( 0 to 0 );
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_15 : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \v_cmp_reg[17]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_107 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_107;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_107 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_4 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_186
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_187\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_188
- port map (
- E(0) => \^e\(0),
- SR(0) => SR(0),
- intr_o_reg(0) => intr_o_reg(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff2_reg_1(1 downto 0) => s_buff2_reg_0(1 downto 0),
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_15 => s_comparators_i_15,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg_0 => \^d\(0),
- \v_cmp_reg[17]\(2 downto 0) => \v_cmp_reg[17]\(2 downto 0)
- );
-intr_led_o_i_6: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => Q(0),
- I1 => \^d\(0),
- I2 => s_pulseLed_reg_0(1),
- I3 => Q(2),
- I4 => s_pulseLed_reg_0(0),
- I5 => Q(1),
- O => S(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_108 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_16 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_108 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_108;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_108 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_183
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_184\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_185
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_16 => s_comparators_i_16,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_109 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_17 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_109 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_109;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_109 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_180
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_181\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_182
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_17 => s_comparators_i_17,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_11 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_1 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_11 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_11;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_11 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_count_reg(0) <= \^s_count_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_65
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_66\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_67
- port map (
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_1 => s_comparators_i_1,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg_0(0) => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_110 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- S : out STD_LOGIC_VECTOR ( 0 to 0 );
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_18 : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- \v_cmp_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_buff2_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_110 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_110;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_110 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_4 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_177
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_178\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_179
- port map (
- E(0) => \^e\(0),
- SR(0) => SR(0),
- intr_o_reg(0) => intr_o_reg(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff2_reg_1(0) => s_buff2_reg_0(0),
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_18 => s_comparators_i_18,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg_0 => \^d\(0),
- \v_cmp_reg[19]\(1 downto 0) => \v_cmp_reg[19]\(1 downto 0)
- );
-intr_led_o_i_5: unisim.vcomponents.LUT4
- generic map(
- INIT => X"9009"
- )
- port map (
- I0 => Q(0),
- I1 => \^d\(0),
- I2 => Q(1),
- I3 => s_pulseLed_reg_0(0),
- O => S(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_111 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_19 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_111 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_111;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_111 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_174
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_175\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_176
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_19 => s_comparators_i_19,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_112 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_1 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_112 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_112;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_112 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_count_reg(0) <= \^s_count_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_171
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_172\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_173
- port map (
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_1 => s_comparators_i_1,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg_0(0) => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_113 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_2 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_113 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_113;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_113 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_count_reg(0) <= \^s_count_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_168
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_169\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_170
- port map (
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_2 => s_comparators_i_2,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg_0(0) => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_114 is
- port (
- \s_datao_fmc1[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- S : out STD_LOGIC_VECTOR ( 0 to 0 );
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_3 : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \v_cmp_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_114 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_114;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_114 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_4 : STD_LOGIC;
- signal \^s_datao_fmc1[4]\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- \s_datao_fmc1[4]\(0) <= \^s_datao_fmc1[4]\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_165
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_166\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_datao_fmc1[4]\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_167
- port map (
- E(0) => \^e\(0),
- SR(0) => SR(0),
- intr_o_reg(0) => intr_o_reg(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff2_reg_1(1 downto 0) => s_buff2_reg_0(1 downto 0),
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_3 => s_comparators_i_3,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg_0 => \^s_datao_fmc1[4]\(0),
- \v_cmp_reg[5]\(2 downto 0) => \v_cmp_reg[5]\(2 downto 0)
- );
-intr_led_o_i_12: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => Q(0),
- I1 => \^s_datao_fmc1[4]\(0),
- I2 => s_pulseLed_reg_0(1),
- I3 => Q(2),
- I4 => s_pulseLed_reg_0(0),
- I5 => Q(1),
- O => S(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_datao_fmc1[4]\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_115 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_4 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_115 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_115;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_115 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_count_reg(0) <= \^s_count_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_162
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_163\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_164
- port map (
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_4 => s_comparators_i_4,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg_0(0) => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_116 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_5 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_116 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_116;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_116 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_count_reg(0) <= \^s_count_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_159
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_160\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_161
- port map (
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_5 => s_comparators_i_5,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg_0(0) => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_117 is
- port (
- \s_datao_fmc1[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- S : out STD_LOGIC_VECTOR ( 0 to 0 );
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_6 : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \v_cmp_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_117 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_117;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_117 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_4 : STD_LOGIC;
- signal \^s_datao_fmc1[4]\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- \s_datao_fmc1[4]\(0) <= \^s_datao_fmc1[4]\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_156
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_157\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_datao_fmc1[4]\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_158
- port map (
- E(0) => \^e\(0),
- SR(0) => SR(0),
- intr_o_reg(0) => intr_o_reg(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff2_reg_1(1 downto 0) => s_buff2_reg_0(1 downto 0),
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_6 => s_comparators_i_6,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg_0 => \^s_datao_fmc1[4]\(0),
- \v_cmp_reg[8]\(2 downto 0) => \v_cmp_reg[8]\(2 downto 0)
- );
-intr_led_o_i_11: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => Q(0),
- I1 => \^s_datao_fmc1[4]\(0),
- I2 => s_pulseLed_reg_0(1),
- I3 => Q(2),
- I4 => s_pulseLed_reg_0(0),
- I5 => Q(1),
- O => S(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_datao_fmc1[4]\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_118 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_7 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_118 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_118;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_118 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_count_reg(0) <= \^s_count_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_153
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_154\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_155
- port map (
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_7 => s_comparators_i_7,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg_0(0) => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_119 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_8 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_119 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_119;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_119 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_150
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_151\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_152
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_8 => s_comparators_i_8,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_12 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_2 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_12 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_12;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_12 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_count_reg(0) <= \^s_count_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_62
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_63\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_64
- port map (
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_2 => s_comparators_i_2,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg_0(0) => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_120 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- intr_led_o_reg : out STD_LOGIC;
- CO : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_9 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \v_cmpled_reg[18]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \v_cmp_reg[6]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \v_cmp_reg[18]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \v_cmp_reg[11]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_120 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_120;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_120 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_4 : STD_LOGIC;
- signal intr_led_o1 : STD_LOGIC;
- signal intr_led_o_i_10_n_0 : STD_LOGIC;
- signal intr_led_o_reg_i_2_n_2 : STD_LOGIC;
- signal intr_led_o_reg_i_2_n_3 : STD_LOGIC;
- signal intr_led_o_reg_i_4_n_0 : STD_LOGIC;
- signal intr_led_o_reg_i_4_n_1 : STD_LOGIC;
- signal intr_led_o_reg_i_4_n_2 : STD_LOGIC;
- signal intr_led_o_reg_i_4_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
- signal NLW_intr_led_o_reg_i_2_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
- signal NLW_intr_led_o_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_intr_led_o_reg_i_4_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_147
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_148\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_149
- port map (
- CO(0) => CO(0),
- E(0) => \^e\(0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff2_reg_1(1 downto 0) => s_buff2_reg_0(1 downto 0),
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_9 => s_comparators_i_9,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg_0 => \^d\(0),
- \v_cmp_reg[11]\(2 downto 0) => \v_cmp_reg[11]\(2 downto 0),
- \v_cmp_reg[18]\(2 downto 0) => \v_cmp_reg[18]\(2 downto 0),
- \v_cmp_reg[6]\(2 downto 0) => \v_cmp_reg[6]\(2 downto 0)
- );
-intr_led_o_i_1: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => intr_led_o1,
- I1 => s_pulseLed_reg_0,
- O => intr_led_o_reg
- );
-intr_led_o_i_10: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => Q(0),
- I1 => \^d\(0),
- I2 => s_pulseLed_reg_1(1),
- I3 => Q(2),
- I4 => s_pulseLed_reg_1(0),
- I5 => Q(1),
- O => intr_led_o_i_10_n_0
- );
-intr_led_o_reg_i_2: unisim.vcomponents.CARRY4
- port map (
- CI => intr_led_o_reg_i_4_n_0,
- CO(3) => NLW_intr_led_o_reg_i_2_CO_UNCONNECTED(3),
- CO(2) => intr_led_o1,
- CO(1) => intr_led_o_reg_i_2_n_2,
- CO(0) => intr_led_o_reg_i_2_n_3,
- CYINIT => '0',
- DI(3 downto 0) => B"0111",
- O(3 downto 0) => NLW_intr_led_o_reg_i_2_O_UNCONNECTED(3 downto 0),
- S(3) => '0',
- S(2 downto 0) => \v_cmpled_reg[18]\(2 downto 0)
- );
-intr_led_o_reg_i_4: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => intr_led_o_reg_i_4_n_0,
- CO(2) => intr_led_o_reg_i_4_n_1,
- CO(1) => intr_led_o_reg_i_4_n_2,
- CO(0) => intr_led_o_reg_i_4_n_3,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => NLW_intr_led_o_reg_i_4_O_UNCONNECTED(3 downto 0),
- S(3) => intr_led_o_i_10_n_0,
- S(2 downto 0) => S(2 downto 0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => SR(0),
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_121 is
- port (
- \s_datao_fmc1[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[0]\ : out STD_LOGIC;
- intr_led_o_reg : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__3\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__3\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- \v_outleds_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_121 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_121;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_121 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_datao_fmc1[5]\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- \s_datao_fmc1[5]\(0) <= \^s_datao_fmc1[5]\(0);
-\axi_rdata[0]_i_34\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => Q(0),
- I1 => \axi_araddr_reg[3]_rep__3\,
- I2 => \^s_datao_fmc1[5]\(0),
- I3 => \axi_araddr_reg[2]_rep__3\,
- I4 => s_pulseLed_reg_0(0),
- O => \axi_rdata_reg[0]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_145\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_datao_fmc1[5]\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_146
- port map (
- D(0) => D(0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_datao_fmc1[5]\(0)
- );
-intr_led_o_i_9: unisim.vcomponents.LUT6
- generic map(
- INIT => X"6FF6FFFFFFFF6FF6"
- )
- port map (
- I0 => \v_outleds_reg[2]\(0),
- I1 => \^s_datao_fmc1[5]\(0),
- I2 => s_pulseLed_reg_1(1),
- I3 => \v_outleds_reg[2]\(2),
- I4 => s_pulseLed_reg_1(0),
- I5 => \v_outleds_reg[2]\(1),
- O => intr_led_o_reg
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_datao_fmc1[5]\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_122 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[1]\ : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__3\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__3\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_122 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_122;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_122 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- s_count_reg(0) <= \^s_count_reg\(0);
-\axi_rdata[1]_i_34\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => Q(0),
- I1 => \axi_araddr_reg[3]_rep__3\,
- I2 => \^s_count_reg\(0),
- I3 => \axi_araddr_reg[2]_rep__3\,
- I4 => s_pulseLed_reg_0(0),
- O => \axi_rdata_reg[1]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_143\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_144
- port map (
- D(0) => D(0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_123 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[2]\ : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__3\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__3\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_123 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_123;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_123 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- s_count_reg(0) <= \^s_count_reg\(0);
-\axi_rdata[2]_i_34\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => Q(0),
- I1 => \axi_araddr_reg[3]_rep__3\,
- I2 => \^s_count_reg\(0),
- I3 => \axi_araddr_reg[2]_rep__3\,
- I4 => s_pulseLed_reg_0(0),
- O => \axi_rdata_reg[2]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_141\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_142
- port map (
- D(0) => D(0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_124 is
- port (
- \s_datao_fmc1[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[3]\ : out STD_LOGIC;
- intr_led_o_reg : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__2\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__2\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- \v_outleds_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_124 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_124;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_124 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_datao_fmc1[5]\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- \s_datao_fmc1[5]\(0) <= \^s_datao_fmc1[5]\(0);
-\axi_rdata[3]_i_34\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => Q(0),
- I1 => \axi_araddr_reg[3]_rep__2\,
- I2 => \^s_datao_fmc1[5]\(0),
- I3 => \axi_araddr_reg[2]_rep__2\,
- I4 => s_pulseLed_reg_0(0),
- O => \axi_rdata_reg[3]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_139\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_datao_fmc1[5]\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_140
- port map (
- D(0) => D(0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_datao_fmc1[5]\(0)
- );
-intr_led_o_i_8: unisim.vcomponents.LUT6
- generic map(
- INIT => X"6FF6FFFFFFFF6FF6"
- )
- port map (
- I0 => \v_outleds_reg[5]\(0),
- I1 => \^s_datao_fmc1[5]\(0),
- I2 => s_pulseLed_reg_1(1),
- I3 => \v_outleds_reg[5]\(2),
- I4 => s_pulseLed_reg_1(0),
- I5 => \v_outleds_reg[5]\(1),
- O => intr_led_o_reg
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_datao_fmc1[5]\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_125 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[4]\ : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- \data_o_reg[6][4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__2\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__2\ : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_125 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_125;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_125 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- s_count_reg(0) <= \^s_count_reg\(0);
-\axi_rdata[4]_i_34\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \data_o_reg[6][4]\(0),
- I1 => \axi_araddr_reg[3]_rep__2\,
- I2 => \^s_count_reg\(0),
- I3 => \axi_araddr_reg[2]_rep__2\,
- I4 => D(0),
- O => \axi_rdata_reg[4]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_137\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_138
- port map (
- Q(0) => Q(0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_126 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[5]\ : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- \data_o_reg[6][5]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__2\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__2\ : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_126 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_126;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_126 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- s_count_reg(0) <= \^s_count_reg\(0);
-\axi_rdata[5]_i_34\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \data_o_reg[6][5]\(0),
- I1 => \axi_araddr_reg[3]_rep__2\,
- I2 => \^s_count_reg\(0),
- I3 => \axi_araddr_reg[2]_rep__2\,
- I4 => D(0),
- O => \axi_rdata_reg[5]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_135\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_136
- port map (
- Q(0) => Q(0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_127 is
- port (
- \s_datao_fmc1[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[6]\ : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- \data_o_reg[6][6]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__2\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__2\ : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_127 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_127;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_127 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_datao_fmc1[5]\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- \s_datao_fmc1[5]\(0) <= \^s_datao_fmc1[5]\(0);
-\axi_rdata[6]_i_34\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \data_o_reg[6][6]\(0),
- I1 => \axi_araddr_reg[3]_rep__2\,
- I2 => \^s_datao_fmc1[5]\(0),
- I3 => \axi_araddr_reg[2]_rep__2\,
- I4 => D(0),
- O => \axi_rdata_reg[6]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_133\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_datao_fmc1[5]\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_134
- port map (
- Q(0) => Q(0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_datao_fmc1[5]\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_datao_fmc1[5]\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_128 is
- port (
- \s_datao_fmc1[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[7]\ : out STD_LOGIC;
- intr_led_o_reg : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- \data_o_reg[6][7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__2\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__2\ : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- \v_outleds_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- \v_outleds_reg[3]\ : in STD_LOGIC;
- \v_outleds_reg[0]\ : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_128 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_128;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_128 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_datao_fmc1[5]\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- \s_datao_fmc1[5]\(0) <= \^s_datao_fmc1[5]\(0);
-\axi_rdata[7]_i_34\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \data_o_reg[6][7]\(0),
- I1 => \axi_araddr_reg[3]_rep__2\,
- I2 => \^s_datao_fmc1[5]\(0),
- I3 => \axi_araddr_reg[2]_rep__2\,
- I4 => D(0),
- O => \axi_rdata_reg[7]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_131\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_datao_fmc1[5]\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_132
- port map (
- Q(0) => Q(0),
- SR(0) => SR(0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_datao_fmc1[5]\(0)
- );
-intr_led_o_i_3: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFF6FF6"
- )
- port map (
- I0 => \^s_datao_fmc1[5]\(0),
- I1 => \v_outleds_reg[7]\(1),
- I2 => s_pulseLed_reg_0(0),
- I3 => \v_outleds_reg[7]\(0),
- I4 => \v_outleds_reg[3]\,
- I5 => \v_outleds_reg[0]\,
- O => intr_led_o_reg
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => SR(0),
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_datao_fmc1[5]\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_13 is
- port (
- \s_datao_fmc2[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- S : out STD_LOGIC_VECTOR ( 0 to 0 );
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_3 : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \v_cmp_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_13 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_13;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_13 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_4 : STD_LOGIC;
- signal \^s_datao_fmc2[4]\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- \s_datao_fmc2[4]\(0) <= \^s_datao_fmc2[4]\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_59
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_60\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_datao_fmc2[4]\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_61
- port map (
- E(0) => \^e\(0),
- intr_o_reg(0) => intr_o_reg(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff2_reg_1(1 downto 0) => s_buff2_reg_0(1 downto 0),
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_3 => s_comparators_i_3,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg_0 => \^s_datao_fmc2[4]\(0),
- \v_cmp_reg[5]\(2 downto 0) => \v_cmp_reg[5]\(2 downto 0)
- );
-\intr_led_o_i_12__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => Q(0),
- I1 => \^s_datao_fmc2[4]\(0),
- I2 => s_pulseLed_reg_0(1),
- I3 => Q(2),
- I4 => s_pulseLed_reg_0(0),
- I5 => Q(1),
- O => S(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_datao_fmc2[4]\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_14 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_4 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_14 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_14;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_14 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_count_reg(0) <= \^s_count_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_56
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_57\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_58
- port map (
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_4 => s_comparators_i_4,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg_0(0) => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_15 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_5 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_15 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_15;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_15 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_count_reg(0) <= \^s_count_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_53
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_54\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_55
- port map (
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_5 => s_comparators_i_5,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg_0(0) => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_16 is
- port (
- \s_datao_fmc2[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- S : out STD_LOGIC_VECTOR ( 0 to 0 );
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_6 : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \v_cmp_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_16 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_16;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_16 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_4 : STD_LOGIC;
- signal \^s_datao_fmc2[4]\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- \s_datao_fmc2[4]\(0) <= \^s_datao_fmc2[4]\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_50
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_51\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_datao_fmc2[4]\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_52
- port map (
- E(0) => \^e\(0),
- intr_o_reg(0) => intr_o_reg(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff2_reg_1(1 downto 0) => s_buff2_reg_0(1 downto 0),
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_6 => s_comparators_i_6,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg_0 => \^s_datao_fmc2[4]\(0),
- \v_cmp_reg[8]\(2 downto 0) => \v_cmp_reg[8]\(2 downto 0)
- );
-\intr_led_o_i_11__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => Q(0),
- I1 => \^s_datao_fmc2[4]\(0),
- I2 => s_pulseLed_reg_0(1),
- I3 => Q(2),
- I4 => s_pulseLed_reg_0(0),
- I5 => Q(1),
- O => S(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_datao_fmc2[4]\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_17 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_7 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_17 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_17;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_17 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_count_reg(0) <= \^s_count_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_47
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^d\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_48\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_49
- port map (
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^d\(0),
- s_comparators_i_7 => s_comparators_i_7,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg_0(0) => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^d\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_18 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_8 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_18 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_18;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_18 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_44
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_45\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_46
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_8 => s_comparators_i_8,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_19 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- intr_led_o_reg : out STD_LOGIC;
- CO : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_9 : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- S : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \v_cmpled_reg[18]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \v_cmp_reg[6]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \v_cmp_reg[18]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \v_cmp_reg[11]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_19 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_19;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_19 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_4 : STD_LOGIC;
- signal intr_led_o1 : STD_LOGIC;
- signal \intr_led_o_i_10__0_n_0\ : STD_LOGIC;
- signal \intr_led_o_reg_i_2__0_n_2\ : STD_LOGIC;
- signal \intr_led_o_reg_i_2__0_n_3\ : STD_LOGIC;
- signal \intr_led_o_reg_i_4__0_n_0\ : STD_LOGIC;
- signal \intr_led_o_reg_i_4__0_n_1\ : STD_LOGIC;
- signal \intr_led_o_reg_i_4__0_n_2\ : STD_LOGIC;
- signal \intr_led_o_reg_i_4__0_n_3\ : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
- signal \NLW_intr_led_o_reg_i_2__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
- signal \NLW_intr_led_o_reg_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \NLW_intr_led_o_reg_i_4__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_42\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_43
- port map (
- CO(0) => CO(0),
- E(0) => \^e\(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff2_reg_1(1 downto 0) => s_buff2_reg_0(1 downto 0),
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_9 => s_comparators_i_9,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg_0 => \^d\(0),
- \v_cmp_reg[11]\(2 downto 0) => \v_cmp_reg[11]\(2 downto 0),
- \v_cmp_reg[18]\(2 downto 0) => \v_cmp_reg[18]\(2 downto 0),
- \v_cmp_reg[6]\(2 downto 0) => \v_cmp_reg[6]\(2 downto 0)
- );
-\intr_led_o_i_10__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => Q(0),
- I1 => \^d\(0),
- I2 => s_pulseLed_reg_1(1),
- I3 => Q(2),
- I4 => s_pulseLed_reg_1(0),
- I5 => Q(1),
- O => \intr_led_o_i_10__0_n_0\
- );
-\intr_led_o_i_1__0\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => intr_led_o1,
- I1 => s_pulseLed_reg_0,
- O => intr_led_o_reg
- );
-\intr_led_o_reg_i_2__0\: unisim.vcomponents.CARRY4
- port map (
- CI => \intr_led_o_reg_i_4__0_n_0\,
- CO(3) => \NLW_intr_led_o_reg_i_2__0_CO_UNCONNECTED\(3),
- CO(2) => intr_led_o1,
- CO(1) => \intr_led_o_reg_i_2__0_n_2\,
- CO(0) => \intr_led_o_reg_i_2__0_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0111",
- O(3 downto 0) => \NLW_intr_led_o_reg_i_2__0_O_UNCONNECTED\(3 downto 0),
- S(3) => '0',
- S(2 downto 0) => \v_cmpled_reg[18]\(2 downto 0)
- );
-\intr_led_o_reg_i_4__0\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \intr_led_o_reg_i_4__0_n_0\,
- CO(2) => \intr_led_o_reg_i_4__0_n_1\,
- CO(1) => \intr_led_o_reg_i_4__0_n_2\,
- CO(0) => \intr_led_o_reg_i_4__0_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"1111",
- O(3 downto 0) => \NLW_intr_led_o_reg_i_4__0_O_UNCONNECTED\(3 downto 0),
- S(3) => \intr_led_o_i_10__0_n_0\,
- S(2 downto 0) => S(2 downto 0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_2 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_11 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_2 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_2;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_2 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_92
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_93\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_94
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_11 => s_comparators_i_11,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_20 is
- port (
- \s_datao_fmc2[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[0]\ : out STD_LOGIC;
- intr_led_o_reg : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__3\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__3\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- \v_outleds_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_20 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_20;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_20 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_datao_fmc2[5]\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- \s_datao_fmc2[5]\(0) <= \^s_datao_fmc2[5]\(0);
-\axi_rdata[0]_i_38\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => Q(0),
- I1 => \axi_araddr_reg[3]_rep__3\,
- I2 => \^s_datao_fmc2[5]\(0),
- I3 => \axi_araddr_reg[2]_rep__3\,
- I4 => s_pulseLed_reg_0(0),
- O => \axi_rdata_reg[0]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_40\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_datao_fmc2[5]\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_41
- port map (
- D(0) => D(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_datao_fmc2[5]\(0)
- );
-\intr_led_o_i_9__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"6FF6FFFFFFFF6FF6"
- )
- port map (
- I0 => \v_outleds_reg[2]\(0),
- I1 => \^s_datao_fmc2[5]\(0),
- I2 => s_pulseLed_reg_1(1),
- I3 => \v_outleds_reg[2]\(2),
- I4 => s_pulseLed_reg_1(0),
- I5 => \v_outleds_reg[2]\(1),
- O => intr_led_o_reg
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_datao_fmc2[5]\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_21 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[1]\ : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__3\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__3\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_21 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_21;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_21 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- s_count_reg(0) <= \^s_count_reg\(0);
-\axi_rdata[1]_i_38\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => Q(0),
- I1 => \axi_araddr_reg[3]_rep__3\,
- I2 => \^s_count_reg\(0),
- I3 => \axi_araddr_reg[2]_rep__3\,
- I4 => s_pulseLed_reg_0(0),
- O => \axi_rdata_reg[1]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_38\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_39
- port map (
- D(0) => D(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_22 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[2]\ : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__3\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__3\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_22 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_22;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_22 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- s_count_reg(0) <= \^s_count_reg\(0);
-\axi_rdata[2]_i_38\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => Q(0),
- I1 => \axi_araddr_reg[3]_rep__3\,
- I2 => \^s_count_reg\(0),
- I3 => \axi_araddr_reg[2]_rep__3\,
- I4 => s_pulseLed_reg_0(0),
- O => \axi_rdata_reg[2]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_36\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_37
- port map (
- D(0) => D(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_23 is
- port (
- \s_datao_fmc2[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[3]\ : out STD_LOGIC;
- intr_led_o_reg : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__2\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__2\ : in STD_LOGIC;
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- \v_outleds_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_23 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_23;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_23 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_datao_fmc2[5]\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- \s_datao_fmc2[5]\(0) <= \^s_datao_fmc2[5]\(0);
-\axi_rdata[3]_i_38\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => Q(0),
- I1 => \axi_araddr_reg[3]_rep__2\,
- I2 => \^s_datao_fmc2[5]\(0),
- I3 => \axi_araddr_reg[2]_rep__2\,
- I4 => s_pulseLed_reg_0(0),
- O => \axi_rdata_reg[3]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_34\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_datao_fmc2[5]\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_35
- port map (
- D(0) => D(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_datao_fmc2[5]\(0)
- );
-\intr_led_o_i_8__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"6FF6FFFFFFFF6FF6"
- )
- port map (
- I0 => \v_outleds_reg[5]\(0),
- I1 => \^s_datao_fmc2[5]\(0),
- I2 => s_pulseLed_reg_1(1),
- I3 => \v_outleds_reg[5]\(2),
- I4 => s_pulseLed_reg_1(0),
- I5 => \v_outleds_reg[5]\(1),
- O => intr_led_o_reg
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_datao_fmc2[5]\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_24 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[4]\ : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- \data_o_reg[6][4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__2\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__2\ : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_24 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_24;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_24 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- s_count_reg(0) <= \^s_count_reg\(0);
-\axi_rdata[4]_i_38\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \data_o_reg[6][4]\(0),
- I1 => \axi_araddr_reg[3]_rep__2\,
- I2 => \^s_count_reg\(0),
- I3 => \axi_araddr_reg[2]_rep__2\,
- I4 => D(0),
- O => \axi_rdata_reg[4]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_32\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_33
- port map (
- Q(0) => Q(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_25 is
- port (
- s_count_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[5]\ : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- \data_o_reg[6][5]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__2\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__2\ : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_25 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_25;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_25 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- s_count_reg(0) <= \^s_count_reg\(0);
-\axi_rdata[5]_i_38\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \data_o_reg[6][5]\(0),
- I1 => \axi_araddr_reg[3]_rep__2\,
- I2 => \^s_count_reg\(0),
- I3 => \axi_araddr_reg[2]_rep__2\,
- I4 => D(0),
- O => \axi_rdata_reg[5]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_30\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_31
- port map (
- Q(0) => Q(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_count_reg\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_count_reg\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_26 is
- port (
- \s_datao_fmc2[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[6]\ : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- \data_o_reg[6][6]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__2\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__2\ : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_26 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_26;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_26 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_datao_fmc2[5]\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- \s_datao_fmc2[5]\(0) <= \^s_datao_fmc2[5]\(0);
-\axi_rdata[6]_i_38\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \data_o_reg[6][6]\(0),
- I1 => \axi_araddr_reg[3]_rep__2\,
- I2 => \^s_datao_fmc2[5]\(0),
- I3 => \axi_araddr_reg[2]_rep__2\,
- I4 => D(0),
- O => \axi_rdata_reg[6]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_28\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_datao_fmc2[5]\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_29
- port map (
- Q(0) => Q(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_datao_fmc2[5]\(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_datao_fmc2[5]\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_27 is
- port (
- \s_datao_fmc2[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC;
- \axi_rdata_reg[7]\ : out STD_LOGIC;
- intr_led_o_reg : out STD_LOGIC;
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \s_debounce_reg[1]\ : in STD_LOGIC;
- \data_o_reg[6][7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \axi_araddr_reg[3]_rep__2\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__2\ : in STD_LOGIC;
- D : in STD_LOGIC_VECTOR ( 0 to 0 );
- \v_outleds_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- \v_outleds_reg[3]\ : in STD_LOGIC;
- \v_outleds_reg[0]\ : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_27 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_27;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_27 is
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_2 : STD_LOGIC;
- signal \^s_datao_fmc2[5]\ : STD_LOGIC_VECTOR ( 0 to 0 );
-begin
- \s_datao_fmc2[5]\(0) <= \^s_datao_fmc2[5]\(0);
-\axi_rdata[7]_i_38\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"30BB3088"
- )
- port map (
- I0 => \data_o_reg[6][7]\(0),
- I1 => \axi_araddr_reg[3]_rep__2\,
- I2 => \^s_datao_fmc2[5]\(0),
- I3 => \axi_araddr_reg[2]_rep__2\,
- I4 => D(0),
- O => \axi_rdata_reg[7]\
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^s_datao_fmc2[5]\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge
- port map (
- Q(0) => Q(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff3_reg_0 => s_buff3_reg,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_2,
- s_pulseLed_reg_0 => \^s_datao_fmc2[5]\(0)
- );
-\intr_led_o_i_3__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFF6FF6"
- )
- port map (
- I0 => \^s_datao_fmc2[5]\(0),
- I1 => \v_outleds_reg[7]\(1),
- I2 => s_pulseLed_reg_0(0),
- I3 => \v_outleds_reg[7]\(0),
- I4 => \v_outleds_reg[3]\,
- I5 => \v_outleds_reg[0]\,
- O => intr_led_o_reg
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^s_datao_fmc2[5]\(0)
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_3 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- S : out STD_LOGIC_VECTOR ( 0 to 0 );
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_12 : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \v_cmp_reg[14]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_3 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_3;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_3 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_4 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_89
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_90\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_91
- port map (
- E(0) => \^e\(0),
- intr_o_reg(0) => intr_o_reg(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff2_reg_1(1 downto 0) => s_buff2_reg_0(1 downto 0),
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_12 => s_comparators_i_12,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg_0 => \^d\(0),
- \v_cmp_reg[14]\(2 downto 0) => \v_cmp_reg[14]\(2 downto 0)
- );
-\intr_led_o_i_7__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => Q(0),
- I1 => \^d\(0),
- I2 => s_pulseLed_reg_0(1),
- I3 => Q(2),
- I4 => s_pulseLed_reg_0(0),
- I5 => Q(1),
- O => S(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_4 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_13 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_4 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_4;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_4 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_86
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_87\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_88
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_13 => s_comparators_i_13,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_5 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_14 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_5 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_5;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_5 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_83
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_84\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_85
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_14 => s_comparators_i_14,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_6 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- S : out STD_LOGIC_VECTOR ( 0 to 0 );
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_15 : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- \v_cmp_reg[17]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_buff2_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_6 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_6;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_6 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_4 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_80
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_81\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_82
- port map (
- E(0) => \^e\(0),
- intr_o_reg(0) => intr_o_reg(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff2_reg_1(1 downto 0) => s_buff2_reg_0(1 downto 0),
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_15 => s_comparators_i_15,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg_0 => \^d\(0),
- \v_cmp_reg[17]\(2 downto 0) => \v_cmp_reg[17]\(2 downto 0)
- );
-\intr_led_o_i_6__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"9009000000009009"
- )
- port map (
- I0 => Q(0),
- I1 => \^d\(0),
- I2 => s_pulseLed_reg_0(1),
- I3 => Q(2),
- I4 => s_pulseLed_reg_0(0),
- I5 => Q(1),
- O => S(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_7 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_16 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_7 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_7;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_7 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_77
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_78\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_79
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_16 => s_comparators_i_16,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_8 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_17 : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_8 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_8;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_8 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_3 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_74
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_75\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_3,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_76
- port map (
- D(0) => \^d\(0),
- E(0) => \^e\(0),
- Q(4 downto 0) => Q(4 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_17 => s_comparators_i_17,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_3
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_pulseMeasure_9 is
- port (
- D : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff3_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- S : out STD_LOGIC_VECTOR ( 0 to 0 );
- intr_o_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
- E : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_buff2_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
- \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- rst_i : in STD_LOGIC;
- \s_debounce_reg[1]\ : in STD_LOGIC;
- s_comparators_i_18 : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_pulseLed_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- \v_cmp_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_buff2_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- s00_axi_aresetn : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_pulseMeasure_9 : entity is "pulseMeasure";
-end system_design_fasec_hwtest_0_0_pulseMeasure_9;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_pulseMeasure_9 is
- signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal cmp_pulseCounterLED_n_0 : STD_LOGIC;
- signal cmp_pulseSync_n_1 : STD_LOGIC;
- signal cmp_pulseSync_n_4 : STD_LOGIC;
- signal \^s_buff3_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal s_pulseLength : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_pulseReg : STD_LOGIC;
-begin
- D(0) <= \^d\(0);
- E(0) <= \^e\(0);
- s_buff3_reg(0) <= \^s_buff3_reg\(0);
-cmp_lengthCounter: entity work.system_design_fasec_hwtest_0_0_counterUpDown_71
- port map (
- E(0) => \^e\(0),
- count_o(23 downto 0) => s_pulseLength(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => \^s_buff3_reg\(0)
- );
-cmp_pulseCounterLED: entity work.\system_design_fasec_hwtest_0_0_counterUpDown__parameterized1_72\
- port map (
- s00_axi_aclk => s00_axi_aclk,
- s_buff2_reg => cmp_pulseSync_n_1,
- s_buff3_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg => cmp_pulseCounterLED_n_0,
- s_pulseLed_reg_0 => \^d\(0)
- );
-cmp_pulseSync: entity work.system_design_fasec_hwtest_0_0_doubleBufferEdge_73
- port map (
- E(0) => \^e\(0),
- intr_o_reg(0) => intr_o_reg(0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg_0(4 downto 0) => s_buff2_reg(4 downto 0),
- s_buff2_reg_1(0) => s_buff2_reg_0(0),
- s_buff3_reg_0 => \^s_buff3_reg\(0),
- s_comparators_i_18 => s_comparators_i_18,
- s_count_reg => cmp_pulseSync_n_1,
- \s_debounce_reg[1]_0\ => \s_debounce_reg[1]\,
- s_pulseLed_reg => cmp_pulseSync_n_4,
- s_pulseLed_reg_0 => \^d\(0),
- \v_cmp_reg[19]\(1 downto 0) => \v_cmp_reg[19]\(1 downto 0)
- );
-\intr_led_o_i_5__0\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"9009"
- )
- port map (
- I0 => Q(0),
- I1 => \^d\(0),
- I2 => Q(1),
- I3 => s_pulseLed_reg_0(0),
- O => S(0)
- );
-s_pulseLed_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => cmp_pulseCounterLED_n_0,
- Q => \^d\(0)
- );
-\s_pulseLengthLatch_reg[0]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(0),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(0)
- );
-\s_pulseLengthLatch_reg[10]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(10),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(10)
- );
-\s_pulseLengthLatch_reg[11]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(11),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(11)
- );
-\s_pulseLengthLatch_reg[12]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(12),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(12)
- );
-\s_pulseLengthLatch_reg[13]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(13),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(13)
- );
-\s_pulseLengthLatch_reg[14]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(14),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(14)
- );
-\s_pulseLengthLatch_reg[15]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(15),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(15)
- );
-\s_pulseLengthLatch_reg[16]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(16),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(16)
- );
-\s_pulseLengthLatch_reg[17]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(17),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(17)
- );
-\s_pulseLengthLatch_reg[18]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(18),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(18)
- );
-\s_pulseLengthLatch_reg[19]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(19),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(19)
- );
-\s_pulseLengthLatch_reg[1]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(1),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(1)
- );
-\s_pulseLengthLatch_reg[20]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(20),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(20)
- );
-\s_pulseLengthLatch_reg[21]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(21),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(21)
- );
-\s_pulseLengthLatch_reg[22]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(22),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(22)
- );
-\s_pulseLengthLatch_reg[23]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(23),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(23)
- );
-\s_pulseLengthLatch_reg[2]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(2),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(2)
- );
-\s_pulseLengthLatch_reg[3]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(3),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(3)
- );
-\s_pulseLengthLatch_reg[4]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(4),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(4)
- );
-\s_pulseLengthLatch_reg[5]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(5),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(5)
- );
-\s_pulseLengthLatch_reg[6]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(6),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(6)
- );
-\s_pulseLengthLatch_reg[7]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(7),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(7)
- );
-\s_pulseLengthLatch_reg[8]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(8),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(8)
- );
-\s_pulseLengthLatch_reg[9]\: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => s_pulseReg,
- CLR => rst_i,
- D => s_pulseLength(9),
- Q => \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(9)
- );
-s_pulseReg_reg: unisim.vcomponents.FDCE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- CLR => rst_i,
- D => \^s_buff3_reg\(0),
- Q => s_pulseReg
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_general_fmc is
- port (
- \FMC1_LA_P_b[27]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
- \FMC1_LA_N_b[27]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
- rst_i : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[111]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[15]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[15]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]_1\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]_2\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \axi_rdata_reg[0]\ : out STD_LOGIC;
- s_count_reg : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \axi_rdata_reg[0]_0\ : out STD_LOGIC;
- \axi_rdata_reg[0]_1\ : out STD_LOGIC;
- \axi_rdata_reg[0]_2\ : out STD_LOGIC;
- \axi_rdata_reg[0]_3\ : out STD_LOGIC;
- \axi_rdata_reg[1]\ : out STD_LOGIC;
- \axi_rdata_reg[1]_0\ : out STD_LOGIC;
- \axi_rdata_reg[1]_1\ : out STD_LOGIC;
- \axi_rdata_reg[1]_2\ : out STD_LOGIC;
- \axi_rdata_reg[1]_3\ : out STD_LOGIC;
- \axi_rdata_reg[2]\ : out STD_LOGIC;
- \axi_rdata_reg[2]_0\ : out STD_LOGIC;
- \axi_rdata_reg[2]_1\ : out STD_LOGIC;
- \axi_rdata_reg[2]_2\ : out STD_LOGIC;
- \axi_rdata_reg[2]_3\ : out STD_LOGIC;
- \axi_rdata_reg[3]\ : out STD_LOGIC;
- \axi_rdata_reg[3]_0\ : out STD_LOGIC;
- \axi_rdata_reg[3]_1\ : out STD_LOGIC;
- \axi_rdata_reg[3]_2\ : out STD_LOGIC;
- \axi_rdata_reg[3]_3\ : out STD_LOGIC;
- \axi_rdata_reg[4]\ : out STD_LOGIC;
- \axi_rdata_reg[4]_0\ : out STD_LOGIC;
- \axi_rdata_reg[4]_1\ : out STD_LOGIC;
- \axi_rdata_reg[4]_2\ : out STD_LOGIC;
- \axi_rdata_reg[4]_3\ : out STD_LOGIC;
- \axi_rdata_reg[5]\ : out STD_LOGIC;
- \axi_rdata_reg[5]_0\ : out STD_LOGIC;
- \axi_rdata_reg[5]_1\ : out STD_LOGIC;
- \axi_rdata_reg[5]_2\ : out STD_LOGIC;
- \axi_rdata_reg[5]_3\ : out STD_LOGIC;
- \axi_rdata_reg[6]\ : out STD_LOGIC;
- \axi_rdata_reg[6]_0\ : out STD_LOGIC;
- \axi_rdata_reg[6]_1\ : out STD_LOGIC;
- \axi_rdata_reg[6]_2\ : out STD_LOGIC;
- \axi_rdata_reg[6]_3\ : out STD_LOGIC;
- \axi_rdata_reg[7]\ : out STD_LOGIC;
- \axi_rdata_reg[7]_0\ : out STD_LOGIC;
- \axi_rdata_reg[7]_1\ : out STD_LOGIC;
- \axi_rdata_reg[7]_2\ : out STD_LOGIC;
- \axi_rdata_reg[7]_3\ : out STD_LOGIC;
- \axi_rdata_reg[8]\ : out STD_LOGIC;
- \axi_rdata_reg[8]_0\ : out STD_LOGIC;
- \axi_rdata_reg[8]_1\ : out STD_LOGIC;
- \axi_rdata_reg[8]_2\ : out STD_LOGIC;
- \axi_rdata_reg[9]\ : out STD_LOGIC;
- \axi_rdata_reg[9]_0\ : out STD_LOGIC;
- \axi_rdata_reg[9]_1\ : out STD_LOGIC;
- \axi_rdata_reg[9]_2\ : out STD_LOGIC;
- \axi_rdata_reg[10]\ : out STD_LOGIC;
- \axi_rdata_reg[10]_0\ : out STD_LOGIC;
- \axi_rdata_reg[10]_1\ : out STD_LOGIC;
- \axi_rdata_reg[10]_2\ : out STD_LOGIC;
- \axi_rdata_reg[11]\ : out STD_LOGIC;
- \axi_rdata_reg[11]_0\ : out STD_LOGIC;
- \axi_rdata_reg[11]_1\ : out STD_LOGIC;
- \axi_rdata_reg[11]_2\ : out STD_LOGIC;
- \axi_rdata_reg[12]\ : out STD_LOGIC;
- \axi_rdata_reg[12]_0\ : out STD_LOGIC;
- \axi_rdata_reg[12]_1\ : out STD_LOGIC;
- \axi_rdata_reg[12]_2\ : out STD_LOGIC;
- \axi_rdata_reg[13]\ : out STD_LOGIC;
- \axi_rdata_reg[13]_0\ : out STD_LOGIC;
- \axi_rdata_reg[13]_1\ : out STD_LOGIC;
- \axi_rdata_reg[13]_2\ : out STD_LOGIC;
- \axi_rdata_reg[14]\ : out STD_LOGIC;
- \axi_rdata_reg[14]_0\ : out STD_LOGIC;
- \axi_rdata_reg[14]_1\ : out STD_LOGIC;
- \axi_rdata_reg[14]_2\ : out STD_LOGIC;
- \axi_rdata_reg[15]\ : out STD_LOGIC;
- \axi_rdata_reg[15]_0\ : out STD_LOGIC;
- \axi_rdata_reg[15]_1\ : out STD_LOGIC;
- \axi_rdata_reg[15]_2\ : out STD_LOGIC;
- \axi_rdata_reg[16]\ : out STD_LOGIC;
- \axi_rdata_reg[16]_0\ : out STD_LOGIC;
- \axi_rdata_reg[16]_1\ : out STD_LOGIC;
- \axi_rdata_reg[16]_2\ : out STD_LOGIC;
- \axi_rdata_reg[17]\ : out STD_LOGIC;
- \axi_rdata_reg[17]_0\ : out STD_LOGIC;
- \axi_rdata_reg[17]_1\ : out STD_LOGIC;
- \axi_rdata_reg[17]_2\ : out STD_LOGIC;
- \axi_rdata_reg[18]\ : out STD_LOGIC;
- \axi_rdata_reg[18]_0\ : out STD_LOGIC;
- \axi_rdata_reg[18]_1\ : out STD_LOGIC;
- \axi_rdata_reg[18]_2\ : out STD_LOGIC;
- \axi_rdata_reg[19]\ : out STD_LOGIC;
- \axi_rdata_reg[19]_0\ : out STD_LOGIC;
- \axi_rdata_reg[19]_1\ : out STD_LOGIC;
- \axi_rdata_reg[19]_2\ : out STD_LOGIC;
- \axi_rdata_reg[20]\ : out STD_LOGIC;
- \axi_rdata_reg[20]_0\ : out STD_LOGIC;
- \axi_rdata_reg[20]_1\ : out STD_LOGIC;
- \axi_rdata_reg[20]_2\ : out STD_LOGIC;
- \axi_rdata_reg[20]_3\ : out STD_LOGIC;
- \axi_rdata_reg[21]\ : out STD_LOGIC;
- \axi_rdata_reg[21]_0\ : out STD_LOGIC;
- \axi_rdata_reg[21]_1\ : out STD_LOGIC;
- \axi_rdata_reg[21]_2\ : out STD_LOGIC;
- \axi_rdata_reg[21]_3\ : out STD_LOGIC;
- \axi_rdata_reg[22]\ : out STD_LOGIC;
- \axi_rdata_reg[22]_0\ : out STD_LOGIC;
- \axi_rdata_reg[22]_1\ : out STD_LOGIC;
- \axi_rdata_reg[22]_2\ : out STD_LOGIC;
- \axi_rdata_reg[22]_3\ : out STD_LOGIC;
- \axi_rdata_reg[23]\ : out STD_LOGIC;
- \axi_rdata_reg[23]_0\ : out STD_LOGIC;
- \axi_rdata_reg[23]_1\ : out STD_LOGIC;
- \axi_rdata_reg[23]_2\ : out STD_LOGIC;
- \axi_rdata_reg[23]_3\ : out STD_LOGIC;
- \s_datao_fmc1[0]\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
- intr_o : out STD_LOGIC;
- intr_led_o : out STD_LOGIC;
- \axi_rdata_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
- \axi_rdata_reg[3]_4\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
- FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 1 downto 0 );
- FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 1 downto 0 );
- \FMC1_LA_P_b[32]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
- \FMC1_LA_N_b[32]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
- D : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- \data_rw_o_reg[11][7]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \axi_araddr_reg[3]_rep__3\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__3\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep__1\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep__0\ : in STD_LOGIC;
- \axi_araddr_reg[3]_rep__2\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__2\ : in STD_LOGIC;
- \axi_araddr_reg[3]_rep__1\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__1\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep\ : in STD_LOGIC;
- \axi_araddr_reg[3]_rep__0\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__0\ : in STD_LOGIC;
- \axi_araddr_reg[3]_rep\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep\ : in STD_LOGIC;
- \axi_araddr_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- fmc2_intr : in STD_LOGIC;
- fmc2_intr_led : in STD_LOGIC;
- \data_rw_o_reg[19][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- CO : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[18][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[18][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[17][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[17][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[16][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[16][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[20][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[20][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[21][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[21][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[22][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[22][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[23][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[23][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[24][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[25][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[26][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[27][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[28][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[29][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[30][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[31][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[32][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[33][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[34][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[35][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[10][7]\ : in STD_LOGIC;
- \data_rw_o_reg[10][6]\ : in STD_LOGIC;
- \data_rw_o_reg[10][5]\ : in STD_LOGIC;
- \data_rw_o_reg[10][4]\ : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_general_fmc : entity is "general_fmc";
-end system_design_fasec_hwtest_0_0_general_fmc;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_general_fmc is
- signal \axi_rdata[0]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_40_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_40_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_40_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_40_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_40_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_40_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_40_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_40_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_40_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_40_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_42_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_43_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_40_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_41_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_40_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_41_n_0\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_1\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_11\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_13\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_15\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_17\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_19\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_21\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_23\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_25\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_27\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_29\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_3\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_31\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_33\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_35\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_37\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_5\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_7\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_9\ : STD_LOGIC;
- signal \cmp_pulseSync/s_debounce\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_10\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_12\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_14\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_16\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_18\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_2\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_20\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_22\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_24\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_26\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_28\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_30\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_32\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_34\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_36\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_38\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_39\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_4\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_40\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_41\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_42\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_43\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_44\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_45\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_6\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_8\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal fmc1_intr : STD_LOGIC;
- signal fmc1_intr_led : STD_LOGIC;
- signal \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2\ : STD_LOGIC;
- signal \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_4\ : STD_LOGIC;
- signal \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_2\ : STD_LOGIC;
- signal \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_2\ : STD_LOGIC;
- signal \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_2\ : STD_LOGIC;
- signal \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_2\ : STD_LOGIC;
- signal \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_2\ : STD_LOGIC;
- signal \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure_n_2\ : STD_LOGIC;
- signal \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_3\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi_n_1\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi_n_2\ : STD_LOGIC;
- signal intr_o0 : STD_LOGIC;
- signal \^rst_i\ : STD_LOGIC;
- signal \s_buff2_i_1__0_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__10_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__11_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__12_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__13_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__14_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__15_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__16_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__17_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__18_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__19_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__1_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__20_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__21_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__22_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__23_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__24_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__25_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__26_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__2_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__3_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__4_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__5_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__6_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__7_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__8_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__9_n_0\ : STD_LOGIC;
- signal s_buff2_i_1_n_0 : STD_LOGIC;
- signal \s_cmp_lengths[0]_0\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[10]_10\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[11]_11\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[12]_12\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[13]_13\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[14]_14\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[15]_15\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[16]_16\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[17]_17\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[18]_18\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[19]_19\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[1]_1\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[2]_2\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[3]_3\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[4]_4\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[5]_5\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[6]_6\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[7]_7\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[8]_8\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[9]_9\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_comparators_i_0 : STD_LOGIC;
- signal s_comparators_i_1 : STD_LOGIC;
- signal s_comparators_i_10 : STD_LOGIC;
- signal s_comparators_i_11 : STD_LOGIC;
- signal s_comparators_i_12 : STD_LOGIC;
- signal s_comparators_i_13 : STD_LOGIC;
- signal s_comparators_i_14 : STD_LOGIC;
- signal s_comparators_i_15 : STD_LOGIC;
- signal s_comparators_i_16 : STD_LOGIC;
- signal s_comparators_i_17 : STD_LOGIC;
- signal s_comparators_i_18 : STD_LOGIC;
- signal s_comparators_i_19 : STD_LOGIC;
- signal s_comparators_i_2 : STD_LOGIC;
- signal s_comparators_i_3 : STD_LOGIC;
- signal s_comparators_i_4 : STD_LOGIC;
- signal s_comparators_i_5 : STD_LOGIC;
- signal s_comparators_i_6 : STD_LOGIC;
- signal s_comparators_i_7 : STD_LOGIC;
- signal s_comparators_i_8 : STD_LOGIC;
- signal s_comparators_i_9 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_datao_fmc1[0]\ : STD_LOGIC_VECTOR ( 19 downto 0 );
- signal \s_datao_fmc1[48]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[49]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[4]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal \s_datao_fmc1[50]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[51]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[52]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[53]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[54]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[55]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[56]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[57]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[58]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[59]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[5]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal \s_datao_fmc1[60]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[61]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[62]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[63]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[64]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[65]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[66]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[67]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc1[6]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal s_diffouts_o : STD_LOGIC_VECTOR ( 7 downto 4 );
- signal s_spi_cs_n : STD_LOGIC;
- signal s_spi_mosi : STD_LOGIC;
- signal s_spi_sclk : STD_LOGIC;
- signal s_start : STD_LOGIC;
- signal s_start_i_1_n_0 : STD_LOGIC;
- signal spi_sdo_i : STD_LOGIC;
- signal v_cmp : STD_LOGIC_VECTOR ( 19 downto 0 );
- signal v_cmpled : STD_LOGIC_VECTOR ( 19 downto 0 );
- signal v_dout : STD_LOGIC_VECTOR ( 7 downto 4 );
- signal v_fbd : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal v_outleds : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal \NLW_gen_spi.cmp_spi_cs_n_iobuf_O_UNCONNECTED\ : STD_LOGIC;
- signal \NLW_gen_spi.cmp_spi_mosi_iobuf_O_UNCONNECTED\ : STD_LOGIC;
- signal \NLW_gen_spi.cmp_spi_sclk_iobuf_O_UNCONNECTED\ : STD_LOGIC;
- attribute CAPACITANCE : string;
- attribute CAPACITANCE of \fmc_03287_channels[0].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE : string;
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[0].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE : string;
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[0].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type : string;
- attribute box_type of \fmc_03287_channels[0].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[10].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[10].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[10].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[10].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[11].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[11].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[11].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[11].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[12].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[12].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[12].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[12].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[13].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[13].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[13].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[13].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[14].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[14].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[14].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[14].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[15].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[15].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[15].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[15].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[16].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[16].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[16].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[16].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[17].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[17].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[17].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[17].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[18].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[18].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[18].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[18].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[19].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[19].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[19].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[19].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[1].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[1].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[1].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[1].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[2].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[2].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[2].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[2].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[3].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[3].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[3].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[3].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[4].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[4].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[4].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[4].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[5].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[5].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[5].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[5].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[6].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[6].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[6].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[6].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[7].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[7].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[7].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[7].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[8].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[8].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[8].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[8].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[9].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[9].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[9].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[9].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[0].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM : string;
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[0].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[0].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[1].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[1].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[1].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[2].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[2].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[2].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[3].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[3].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[3].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[4].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[4].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[4].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[5].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[5].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[5].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[6].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[6].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[6].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[7].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[7].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[7].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute box_type of \gen_spi.cmp_spi_cs_n_iobuf\ : label is "PRIMITIVE";
- attribute box_type of \gen_spi.cmp_spi_miso_iobuf\ : label is "PRIMITIVE";
- attribute box_type of \gen_spi.cmp_spi_mosi_iobuf\ : label is "PRIMITIVE";
- attribute box_type of \gen_spi.cmp_spi_sclk_iobuf\ : label is "PRIMITIVE";
-begin
- rst_i <= \^rst_i\;
- s_count_reg(11 downto 0) <= \^s_count_reg\(11 downto 0);
- \s_datao_fmc1[0]\(19 downto 0) <= \^s_datao_fmc1[0]\(19 downto 0);
-axi_awready_i_1: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => s00_axi_aresetn,
- O => \^rst_i\
- );
-\axi_rdata[0]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(0),
- I1 => \s_datao_fmc1[50]\(0),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[49]\(0),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[48]\(0),
- O => \axi_rdata_reg[0]_0\
- );
-\axi_rdata[0]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(0),
- I1 => \s_datao_fmc1[54]\(0),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[53]\(0),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[52]\(0),
- O => \axi_rdata_reg[0]_1\
- );
-\axi_rdata[0]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(0),
- I1 => \s_datao_fmc1[66]\(0),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[65]\(0),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[64]\(0),
- O => \axi_rdata_reg[0]_3\
- );
-\axi_rdata[0]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(0),
- I1 => \s_datao_fmc1[58]\(0),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[57]\(0),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[56]\(0),
- O => \axi_rdata[0]_i_42_n_0\
- );
-\axi_rdata[0]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(0),
- I1 => \s_datao_fmc1[62]\(0),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[61]\(0),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[60]\(0),
- O => \axi_rdata[0]_i_43_n_0\
- );
-\axi_rdata[10]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(10),
- I1 => \s_datao_fmc1[50]\(10),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[49]\(10),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[48]\(10),
- O => \axi_rdata_reg[10]\
- );
-\axi_rdata[10]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(10),
- I1 => \s_datao_fmc1[54]\(10),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[53]\(10),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[52]\(10),
- O => \axi_rdata_reg[10]_0\
- );
-\axi_rdata[10]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(10),
- I1 => \s_datao_fmc1[66]\(10),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[65]\(10),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[64]\(10),
- O => \axi_rdata_reg[10]_2\
- );
-\axi_rdata[10]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(10),
- I1 => \s_datao_fmc1[58]\(10),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[57]\(10),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[56]\(10),
- O => \axi_rdata[10]_i_40_n_0\
- );
-\axi_rdata[10]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(10),
- I1 => \s_datao_fmc1[62]\(10),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[61]\(10),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[60]\(10),
- O => \axi_rdata[10]_i_41_n_0\
- );
-\axi_rdata[11]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(11),
- I1 => \s_datao_fmc1[50]\(11),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[49]\(11),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[48]\(11),
- O => \axi_rdata_reg[11]\
- );
-\axi_rdata[11]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(11),
- I1 => \s_datao_fmc1[54]\(11),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[53]\(11),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[52]\(11),
- O => \axi_rdata_reg[11]_0\
- );
-\axi_rdata[11]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(11),
- I1 => \s_datao_fmc1[66]\(11),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[65]\(11),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[64]\(11),
- O => \axi_rdata_reg[11]_2\
- );
-\axi_rdata[11]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(11),
- I1 => \s_datao_fmc1[58]\(11),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[57]\(11),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[56]\(11),
- O => \axi_rdata[11]_i_40_n_0\
- );
-\axi_rdata[11]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(11),
- I1 => \s_datao_fmc1[62]\(11),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[61]\(11),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[60]\(11),
- O => \axi_rdata[11]_i_41_n_0\
- );
-\axi_rdata[12]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(12),
- I1 => \s_datao_fmc1[50]\(12),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[49]\(12),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[48]\(12),
- O => \axi_rdata_reg[12]\
- );
-\axi_rdata[12]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(12),
- I1 => \s_datao_fmc1[54]\(12),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[53]\(12),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[52]\(12),
- O => \axi_rdata_reg[12]_0\
- );
-\axi_rdata[12]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(12),
- I1 => \s_datao_fmc1[66]\(12),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[65]\(12),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[64]\(12),
- O => \axi_rdata_reg[12]_2\
- );
-\axi_rdata[12]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(12),
- I1 => \s_datao_fmc1[58]\(12),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[57]\(12),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[56]\(12),
- O => \axi_rdata[12]_i_40_n_0\
- );
-\axi_rdata[12]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(12),
- I1 => \s_datao_fmc1[62]\(12),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[61]\(12),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[60]\(12),
- O => \axi_rdata[12]_i_41_n_0\
- );
-\axi_rdata[13]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(13),
- I1 => \s_datao_fmc1[50]\(13),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[49]\(13),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[48]\(13),
- O => \axi_rdata_reg[13]\
- );
-\axi_rdata[13]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(13),
- I1 => \s_datao_fmc1[54]\(13),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[53]\(13),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[52]\(13),
- O => \axi_rdata_reg[13]_0\
- );
-\axi_rdata[13]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(13),
- I1 => \s_datao_fmc1[66]\(13),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[65]\(13),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[64]\(13),
- O => \axi_rdata_reg[13]_2\
- );
-\axi_rdata[13]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(13),
- I1 => \s_datao_fmc1[58]\(13),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[57]\(13),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[56]\(13),
- O => \axi_rdata[13]_i_40_n_0\
- );
-\axi_rdata[13]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(13),
- I1 => \s_datao_fmc1[62]\(13),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[61]\(13),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[60]\(13),
- O => \axi_rdata[13]_i_41_n_0\
- );
-\axi_rdata[14]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(14),
- I1 => \s_datao_fmc1[50]\(14),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[49]\(14),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[48]\(14),
- O => \axi_rdata_reg[14]\
- );
-\axi_rdata[14]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(14),
- I1 => \s_datao_fmc1[54]\(14),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[53]\(14),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[52]\(14),
- O => \axi_rdata_reg[14]_0\
- );
-\axi_rdata[14]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(14),
- I1 => \s_datao_fmc1[66]\(14),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[65]\(14),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[64]\(14),
- O => \axi_rdata_reg[14]_2\
- );
-\axi_rdata[14]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(14),
- I1 => \s_datao_fmc1[58]\(14),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[57]\(14),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[56]\(14),
- O => \axi_rdata[14]_i_40_n_0\
- );
-\axi_rdata[14]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(14),
- I1 => \s_datao_fmc1[62]\(14),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[61]\(14),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[60]\(14),
- O => \axi_rdata[14]_i_41_n_0\
- );
-\axi_rdata[15]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(15),
- I1 => \s_datao_fmc1[50]\(15),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[49]\(15),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[48]\(15),
- O => \axi_rdata_reg[15]\
- );
-\axi_rdata[15]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(15),
- I1 => \s_datao_fmc1[54]\(15),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[53]\(15),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[52]\(15),
- O => \axi_rdata_reg[15]_0\
- );
-\axi_rdata[15]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(15),
- I1 => \s_datao_fmc1[66]\(15),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[65]\(15),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[64]\(15),
- O => \axi_rdata_reg[15]_2\
- );
-\axi_rdata[15]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(15),
- I1 => \s_datao_fmc1[58]\(15),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[57]\(15),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[56]\(15),
- O => \axi_rdata[15]_i_40_n_0\
- );
-\axi_rdata[15]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(15),
- I1 => \s_datao_fmc1[62]\(15),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[61]\(15),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[60]\(15),
- O => \axi_rdata[15]_i_41_n_0\
- );
-\axi_rdata[16]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(16),
- I1 => \s_datao_fmc1[50]\(16),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[49]\(16),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[48]\(16),
- O => \axi_rdata_reg[16]\
- );
-\axi_rdata[16]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(16),
- I1 => \s_datao_fmc1[54]\(16),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[53]\(16),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[52]\(16),
- O => \axi_rdata_reg[16]_0\
- );
-\axi_rdata[16]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(16),
- I1 => \s_datao_fmc1[66]\(16),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[65]\(16),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[64]\(16),
- O => \axi_rdata_reg[16]_2\
- );
-\axi_rdata[16]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(16),
- I1 => \s_datao_fmc1[58]\(16),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[57]\(16),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[56]\(16),
- O => \axi_rdata[16]_i_40_n_0\
- );
-\axi_rdata[16]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(16),
- I1 => \s_datao_fmc1[62]\(16),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[61]\(16),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[60]\(16),
- O => \axi_rdata[16]_i_41_n_0\
- );
-\axi_rdata[17]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(17),
- I1 => \s_datao_fmc1[50]\(17),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[49]\(17),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[48]\(17),
- O => \axi_rdata_reg[17]\
- );
-\axi_rdata[17]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(17),
- I1 => \s_datao_fmc1[54]\(17),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[53]\(17),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[52]\(17),
- O => \axi_rdata_reg[17]_0\
- );
-\axi_rdata[17]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(17),
- I1 => \s_datao_fmc1[66]\(17),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[65]\(17),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[64]\(17),
- O => \axi_rdata_reg[17]_2\
- );
-\axi_rdata[17]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(17),
- I1 => \s_datao_fmc1[58]\(17),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[57]\(17),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[56]\(17),
- O => \axi_rdata[17]_i_40_n_0\
- );
-\axi_rdata[17]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(17),
- I1 => \s_datao_fmc1[62]\(17),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc1[61]\(17),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc1[60]\(17),
- O => \axi_rdata[17]_i_41_n_0\
- );
-\axi_rdata[18]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(18),
- I1 => \s_datao_fmc1[50]\(18),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[49]\(18),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[48]\(18),
- O => \axi_rdata_reg[18]\
- );
-\axi_rdata[18]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(18),
- I1 => \s_datao_fmc1[54]\(18),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[53]\(18),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[52]\(18),
- O => \axi_rdata_reg[18]_0\
- );
-\axi_rdata[18]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(18),
- I1 => \s_datao_fmc1[66]\(18),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[65]\(18),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[64]\(18),
- O => \axi_rdata_reg[18]_2\
- );
-\axi_rdata[18]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(18),
- I1 => \s_datao_fmc1[58]\(18),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[57]\(18),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[56]\(18),
- O => \axi_rdata[18]_i_40_n_0\
- );
-\axi_rdata[18]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(18),
- I1 => \s_datao_fmc1[62]\(18),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[61]\(18),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[60]\(18),
- O => \axi_rdata[18]_i_41_n_0\
- );
-\axi_rdata[19]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(19),
- I1 => \s_datao_fmc1[50]\(19),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[49]\(19),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[48]\(19),
- O => \axi_rdata_reg[19]\
- );
-\axi_rdata[19]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(19),
- I1 => \s_datao_fmc1[54]\(19),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[53]\(19),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[52]\(19),
- O => \axi_rdata_reg[19]_0\
- );
-\axi_rdata[19]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(19),
- I1 => \s_datao_fmc1[66]\(19),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[65]\(19),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[64]\(19),
- O => \axi_rdata_reg[19]_2\
- );
-\axi_rdata[19]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(19),
- I1 => \s_datao_fmc1[58]\(19),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[57]\(19),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[56]\(19),
- O => \axi_rdata[19]_i_40_n_0\
- );
-\axi_rdata[19]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(19),
- I1 => \s_datao_fmc1[62]\(19),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[61]\(19),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[60]\(19),
- O => \axi_rdata[19]_i_41_n_0\
- );
-\axi_rdata[1]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(1),
- I1 => \s_datao_fmc1[50]\(1),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[49]\(1),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[48]\(1),
- O => \axi_rdata_reg[1]_0\
- );
-\axi_rdata[1]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(1),
- I1 => \s_datao_fmc1[54]\(1),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[53]\(1),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[52]\(1),
- O => \axi_rdata_reg[1]_1\
- );
-\axi_rdata[1]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(1),
- I1 => \s_datao_fmc1[66]\(1),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[65]\(1),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[64]\(1),
- O => \axi_rdata_reg[1]_3\
- );
-\axi_rdata[1]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(1),
- I1 => \s_datao_fmc1[58]\(1),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[57]\(1),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[56]\(1),
- O => \axi_rdata[1]_i_42_n_0\
- );
-\axi_rdata[1]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(1),
- I1 => \s_datao_fmc1[62]\(1),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[61]\(1),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[60]\(1),
- O => \axi_rdata[1]_i_43_n_0\
- );
-\axi_rdata[20]_i_18\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(20),
- I1 => \s_datao_fmc1[50]\(20),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[49]\(20),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[48]\(20),
- O => \axi_rdata_reg[20]\
- );
-\axi_rdata[20]_i_19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(20),
- I1 => \s_datao_fmc1[54]\(20),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[53]\(20),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[52]\(20),
- O => \axi_rdata_reg[20]_0\
- );
-\axi_rdata[20]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(20),
- I1 => \s_datao_fmc1[66]\(20),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[65]\(20),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[64]\(20),
- O => \axi_rdata_reg[20]_3\
- );
-\axi_rdata[20]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(20),
- I1 => \s_datao_fmc1[62]\(20),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[61]\(20),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[60]\(20),
- O => \axi_rdata_reg[20]_2\
- );
-\axi_rdata[20]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(20),
- I1 => \s_datao_fmc1[58]\(20),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[57]\(20),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[56]\(20),
- O => \axi_rdata_reg[20]_1\
- );
-\axi_rdata[21]_i_18\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(21),
- I1 => \s_datao_fmc1[50]\(21),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[49]\(21),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[48]\(21),
- O => \axi_rdata_reg[21]\
- );
-\axi_rdata[21]_i_19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(21),
- I1 => \s_datao_fmc1[54]\(21),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[53]\(21),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[52]\(21),
- O => \axi_rdata_reg[21]_0\
- );
-\axi_rdata[21]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(21),
- I1 => \s_datao_fmc1[66]\(21),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[65]\(21),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[64]\(21),
- O => \axi_rdata_reg[21]_3\
- );
-\axi_rdata[21]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(21),
- I1 => \s_datao_fmc1[62]\(21),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[61]\(21),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[60]\(21),
- O => \axi_rdata_reg[21]_2\
- );
-\axi_rdata[21]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(21),
- I1 => \s_datao_fmc1[58]\(21),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[57]\(21),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[56]\(21),
- O => \axi_rdata_reg[21]_1\
- );
-\axi_rdata[22]_i_18\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(22),
- I1 => \s_datao_fmc1[50]\(22),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[49]\(22),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[48]\(22),
- O => \axi_rdata_reg[22]\
- );
-\axi_rdata[22]_i_19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(22),
- I1 => \s_datao_fmc1[54]\(22),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[53]\(22),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[52]\(22),
- O => \axi_rdata_reg[22]_0\
- );
-\axi_rdata[22]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(22),
- I1 => \s_datao_fmc1[66]\(22),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[65]\(22),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[64]\(22),
- O => \axi_rdata_reg[22]_3\
- );
-\axi_rdata[22]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(22),
- I1 => \s_datao_fmc1[62]\(22),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[61]\(22),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[60]\(22),
- O => \axi_rdata_reg[22]_2\
- );
-\axi_rdata[22]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(22),
- I1 => \s_datao_fmc1[58]\(22),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc1[57]\(22),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc1[56]\(22),
- O => \axi_rdata_reg[22]_1\
- );
-\axi_rdata[23]_i_19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(23),
- I1 => \s_datao_fmc1[50]\(23),
- I2 => \axi_araddr_reg[4]\(1),
- I3 => \s_datao_fmc1[49]\(23),
- I4 => \axi_araddr_reg[4]\(0),
- I5 => \s_datao_fmc1[48]\(23),
- O => \axi_rdata_reg[23]\
- );
-\axi_rdata[23]_i_20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(23),
- I1 => \s_datao_fmc1[54]\(23),
- I2 => \axi_araddr_reg[4]\(1),
- I3 => \s_datao_fmc1[53]\(23),
- I4 => \axi_araddr_reg[4]\(0),
- I5 => \s_datao_fmc1[52]\(23),
- O => \axi_rdata_reg[23]_0\
- );
-\axi_rdata[23]_i_29\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(23),
- I1 => \s_datao_fmc1[66]\(23),
- I2 => \axi_araddr_reg[4]\(1),
- I3 => \s_datao_fmc1[65]\(23),
- I4 => \axi_araddr_reg[4]\(0),
- I5 => \s_datao_fmc1[64]\(23),
- O => \axi_rdata_reg[23]_3\
- );
-\axi_rdata[23]_i_30\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(23),
- I1 => \s_datao_fmc1[62]\(23),
- I2 => \axi_araddr_reg[4]\(1),
- I3 => \s_datao_fmc1[61]\(23),
- I4 => \axi_araddr_reg[4]\(0),
- I5 => \s_datao_fmc1[60]\(23),
- O => \axi_rdata_reg[23]_2\
- );
-\axi_rdata[23]_i_31\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(23),
- I1 => \s_datao_fmc1[58]\(23),
- I2 => \axi_araddr_reg[4]\(1),
- I3 => \s_datao_fmc1[57]\(23),
- I4 => \axi_araddr_reg[4]\(0),
- I5 => \s_datao_fmc1[56]\(23),
- O => \axi_rdata_reg[23]_1\
- );
-\axi_rdata[2]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(2),
- I1 => \s_datao_fmc1[50]\(2),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[49]\(2),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[48]\(2),
- O => \axi_rdata_reg[2]_0\
- );
-\axi_rdata[2]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(2),
- I1 => \s_datao_fmc1[54]\(2),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[53]\(2),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[52]\(2),
- O => \axi_rdata_reg[2]_1\
- );
-\axi_rdata[2]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(2),
- I1 => \s_datao_fmc1[66]\(2),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[65]\(2),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[64]\(2),
- O => \axi_rdata_reg[2]_3\
- );
-\axi_rdata[2]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(2),
- I1 => \s_datao_fmc1[58]\(2),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[57]\(2),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[56]\(2),
- O => \axi_rdata[2]_i_42_n_0\
- );
-\axi_rdata[2]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(2),
- I1 => \s_datao_fmc1[62]\(2),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc1[61]\(2),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc1[60]\(2),
- O => \axi_rdata[2]_i_43_n_0\
- );
-\axi_rdata[3]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(3),
- I1 => \s_datao_fmc1[50]\(3),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[49]\(3),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[48]\(3),
- O => \axi_rdata_reg[3]_0\
- );
-\axi_rdata[3]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(3),
- I1 => \s_datao_fmc1[54]\(3),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[53]\(3),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[52]\(3),
- O => \axi_rdata_reg[3]_1\
- );
-\axi_rdata[3]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(3),
- I1 => \s_datao_fmc1[66]\(3),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[65]\(3),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[64]\(3),
- O => \axi_rdata_reg[3]_3\
- );
-\axi_rdata[3]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(3),
- I1 => \s_datao_fmc1[58]\(3),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[57]\(3),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[56]\(3),
- O => \axi_rdata[3]_i_42_n_0\
- );
-\axi_rdata[3]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(3),
- I1 => \s_datao_fmc1[62]\(3),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[61]\(3),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[60]\(3),
- O => \axi_rdata[3]_i_43_n_0\
- );
-\axi_rdata[4]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(4),
- I1 => \s_datao_fmc1[50]\(4),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[49]\(4),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[48]\(4),
- O => \axi_rdata_reg[4]_0\
- );
-\axi_rdata[4]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(4),
- I1 => \s_datao_fmc1[54]\(4),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[53]\(4),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[52]\(4),
- O => \axi_rdata_reg[4]_1\
- );
-\axi_rdata[4]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(4),
- I1 => \s_datao_fmc1[66]\(4),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[65]\(4),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[64]\(4),
- O => \axi_rdata_reg[4]_3\
- );
-\axi_rdata[4]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(4),
- I1 => \s_datao_fmc1[58]\(4),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[57]\(4),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[56]\(4),
- O => \axi_rdata[4]_i_42_n_0\
- );
-\axi_rdata[4]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(4),
- I1 => \s_datao_fmc1[62]\(4),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[61]\(4),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[60]\(4),
- O => \axi_rdata[4]_i_43_n_0\
- );
-\axi_rdata[5]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(5),
- I1 => \s_datao_fmc1[50]\(5),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[49]\(5),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[48]\(5),
- O => \axi_rdata_reg[5]_0\
- );
-\axi_rdata[5]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(5),
- I1 => \s_datao_fmc1[54]\(5),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[53]\(5),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[52]\(5),
- O => \axi_rdata_reg[5]_1\
- );
-\axi_rdata[5]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(5),
- I1 => \s_datao_fmc1[66]\(5),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[65]\(5),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[64]\(5),
- O => \axi_rdata_reg[5]_3\
- );
-\axi_rdata[5]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(5),
- I1 => \s_datao_fmc1[58]\(5),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[57]\(5),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[56]\(5),
- O => \axi_rdata[5]_i_42_n_0\
- );
-\axi_rdata[5]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(5),
- I1 => \s_datao_fmc1[62]\(5),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[61]\(5),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[60]\(5),
- O => \axi_rdata[5]_i_43_n_0\
- );
-\axi_rdata[6]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(6),
- I1 => \s_datao_fmc1[50]\(6),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[49]\(6),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[48]\(6),
- O => \axi_rdata_reg[6]_0\
- );
-\axi_rdata[6]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(6),
- I1 => \s_datao_fmc1[54]\(6),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[53]\(6),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[52]\(6),
- O => \axi_rdata_reg[6]_1\
- );
-\axi_rdata[6]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(6),
- I1 => \s_datao_fmc1[66]\(6),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[65]\(6),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[64]\(6),
- O => \axi_rdata_reg[6]_3\
- );
-\axi_rdata[6]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(6),
- I1 => \s_datao_fmc1[58]\(6),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[57]\(6),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[56]\(6),
- O => \axi_rdata[6]_i_42_n_0\
- );
-\axi_rdata[6]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(6),
- I1 => \s_datao_fmc1[62]\(6),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[61]\(6),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[60]\(6),
- O => \axi_rdata[6]_i_43_n_0\
- );
-\axi_rdata[7]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(7),
- I1 => \s_datao_fmc1[50]\(7),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[49]\(7),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[48]\(7),
- O => \axi_rdata_reg[7]_0\
- );
-\axi_rdata[7]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(7),
- I1 => \s_datao_fmc1[54]\(7),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[53]\(7),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[52]\(7),
- O => \axi_rdata_reg[7]_1\
- );
-\axi_rdata[7]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(7),
- I1 => \s_datao_fmc1[66]\(7),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[65]\(7),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[64]\(7),
- O => \axi_rdata_reg[7]_3\
- );
-\axi_rdata[7]_i_42\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(7),
- I1 => \s_datao_fmc1[58]\(7),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[57]\(7),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[56]\(7),
- O => \axi_rdata[7]_i_42_n_0\
- );
-\axi_rdata[7]_i_43\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(7),
- I1 => \s_datao_fmc1[62]\(7),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc1[61]\(7),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc1[60]\(7),
- O => \axi_rdata[7]_i_43_n_0\
- );
-\axi_rdata[8]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(8),
- I1 => \s_datao_fmc1[50]\(8),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[49]\(8),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[48]\(8),
- O => \axi_rdata_reg[8]\
- );
-\axi_rdata[8]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(8),
- I1 => \s_datao_fmc1[54]\(8),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[53]\(8),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[52]\(8),
- O => \axi_rdata_reg[8]_0\
- );
-\axi_rdata[8]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(8),
- I1 => \s_datao_fmc1[66]\(8),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[65]\(8),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[64]\(8),
- O => \axi_rdata_reg[8]_2\
- );
-\axi_rdata[8]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(8),
- I1 => \s_datao_fmc1[58]\(8),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[57]\(8),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[56]\(8),
- O => \axi_rdata[8]_i_40_n_0\
- );
-\axi_rdata[8]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(8),
- I1 => \s_datao_fmc1[62]\(8),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[61]\(8),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[60]\(8),
- O => \axi_rdata[8]_i_41_n_0\
- );
-\axi_rdata[9]_i_15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[51]\(9),
- I1 => \s_datao_fmc1[50]\(9),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[49]\(9),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[48]\(9),
- O => \axi_rdata_reg[9]\
- );
-\axi_rdata[9]_i_16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[55]\(9),
- I1 => \s_datao_fmc1[54]\(9),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[53]\(9),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[52]\(9),
- O => \axi_rdata_reg[9]_0\
- );
-\axi_rdata[9]_i_38\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[67]\(9),
- I1 => \s_datao_fmc1[66]\(9),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[65]\(9),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[64]\(9),
- O => \axi_rdata_reg[9]_2\
- );
-\axi_rdata[9]_i_40\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[59]\(9),
- I1 => \s_datao_fmc1[58]\(9),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[57]\(9),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[56]\(9),
- O => \axi_rdata[9]_i_40_n_0\
- );
-\axi_rdata[9]_i_41\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc1[63]\(9),
- I1 => \s_datao_fmc1[62]\(9),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc1[61]\(9),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc1[60]\(9),
- O => \axi_rdata[9]_i_41_n_0\
- );
-\axi_rdata_reg[0]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[0]_i_42_n_0\,
- I1 => \axi_rdata[0]_i_43_n_0\,
- O => \axi_rdata_reg[0]_2\,
- S => \axi_araddr_reg[4]_rep__1\
- );
-\axi_rdata_reg[10]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[10]_i_40_n_0\,
- I1 => \axi_rdata[10]_i_41_n_0\,
- O => \axi_rdata_reg[10]_1\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[11]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[11]_i_40_n_0\,
- I1 => \axi_rdata[11]_i_41_n_0\,
- O => \axi_rdata_reg[11]_1\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[12]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[12]_i_40_n_0\,
- I1 => \axi_rdata[12]_i_41_n_0\,
- O => \axi_rdata_reg[12]_1\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[13]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[13]_i_40_n_0\,
- I1 => \axi_rdata[13]_i_41_n_0\,
- O => \axi_rdata_reg[13]_1\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[14]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[14]_i_40_n_0\,
- I1 => \axi_rdata[14]_i_41_n_0\,
- O => \axi_rdata_reg[14]_1\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[15]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[15]_i_40_n_0\,
- I1 => \axi_rdata[15]_i_41_n_0\,
- O => \axi_rdata_reg[15]_1\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[16]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[16]_i_40_n_0\,
- I1 => \axi_rdata[16]_i_41_n_0\,
- O => \axi_rdata_reg[16]_1\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[17]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[17]_i_40_n_0\,
- I1 => \axi_rdata[17]_i_41_n_0\,
- O => \axi_rdata_reg[17]_1\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[18]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[18]_i_40_n_0\,
- I1 => \axi_rdata[18]_i_41_n_0\,
- O => \axi_rdata_reg[18]_1\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[19]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[19]_i_40_n_0\,
- I1 => \axi_rdata[19]_i_41_n_0\,
- O => \axi_rdata_reg[19]_1\,
- S => \axi_araddr_reg[4]\(2)
- );
-\axi_rdata_reg[1]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[1]_i_42_n_0\,
- I1 => \axi_rdata[1]_i_43_n_0\,
- O => \axi_rdata_reg[1]_2\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[2]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[2]_i_42_n_0\,
- I1 => \axi_rdata[2]_i_43_n_0\,
- O => \axi_rdata_reg[2]_2\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[3]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[3]_i_42_n_0\,
- I1 => \axi_rdata[3]_i_43_n_0\,
- O => \axi_rdata_reg[3]_2\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[4]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[4]_i_42_n_0\,
- I1 => \axi_rdata[4]_i_43_n_0\,
- O => \axi_rdata_reg[4]_2\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[5]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[5]_i_42_n_0\,
- I1 => \axi_rdata[5]_i_43_n_0\,
- O => \axi_rdata_reg[5]_2\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[6]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[6]_i_42_n_0\,
- I1 => \axi_rdata[6]_i_43_n_0\,
- O => \axi_rdata_reg[6]_2\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[7]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[7]_i_42_n_0\,
- I1 => \axi_rdata[7]_i_43_n_0\,
- O => \axi_rdata_reg[7]_2\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[8]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[8]_i_40_n_0\,
- I1 => \axi_rdata[8]_i_41_n_0\,
- O => \axi_rdata_reg[8]_1\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[9]_i_21\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[9]_i_40_n_0\,
- I1 => \axi_rdata[9]_i_41_n_0\,
- O => \axi_rdata_reg[9]_1\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\data_o_reg[1][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_fbd(0),
- Q => \axi_rdata_reg[3]_4\(0),
- R => '0'
- );
-\data_o_reg[1][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_fbd(1),
- Q => \axi_rdata_reg[3]_4\(1),
- R => '0'
- );
-\data_o_reg[1][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_fbd(2),
- Q => \axi_rdata_reg[3]_4\(2),
- R => '0'
- );
-\data_o_reg[1][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_fbd(3),
- Q => \axi_rdata_reg[3]_4\(3),
- R => '0'
- );
-\data_o_reg[6][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(0),
- Q => \s_datao_fmc1[6]\(0),
- R => '0'
- );
-\data_o_reg[6][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(1),
- Q => \s_datao_fmc1[6]\(1),
- R => '0'
- );
-\data_o_reg[6][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(2),
- Q => \s_datao_fmc1[6]\(2),
- R => '0'
- );
-\data_o_reg[6][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(3),
- Q => \s_datao_fmc1[6]\(3),
- R => '0'
- );
-\data_o_reg[6][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_diffouts_o(4),
- Q => \s_datao_fmc1[6]\(4),
- R => '0'
- );
-\data_o_reg[6][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_diffouts_o(5),
- Q => \s_datao_fmc1[6]\(5),
- R => '0'
- );
-\data_o_reg[6][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_diffouts_o(6),
- Q => \s_datao_fmc1[6]\(6),
- R => '0'
- );
-\data_o_reg[6][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_diffouts_o(7),
- Q => \s_datao_fmc1[6]\(7),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(0),
- IB => \FMC1_LA_N_b[32]\(0),
- O => s_comparators_i_0
- );
-\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_101
- port map (
- D(0) => \^s_datao_fmc1[0]\(0),
- E(0) => \cmp_lengthCounter/RSTP\,
- Q(2 downto 0) => v_cmpled(2 downto 0),
- S(0) => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_3\,
- SR(0) => \^rst_i\,
- \data_rw_o_reg[11][7]\(0) => \data_rw_o_reg[11][7]\(2),
- \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(23 downto 0) => \s_cmp_lengths[0]_0\(23 downto 0),
- intr_o_reg(0) => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_4\,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce\(4 downto 0),
- s_buff2_reg_0(1 downto 0) => \^s_datao_fmc1[0]\(2 downto 1),
- s_comparators_i_0 => s_comparators_i_0,
- \s_datao_fmc1[4]\(0) => \s_datao_fmc1[4]\(0),
- \s_debounce_reg[1]\ => s_buff2_i_1_n_0,
- s_pulseLed_reg_0(1 downto 0) => \s_datao_fmc1[4]\(2 downto 1),
- \v_cmp_reg[2]\(2 downto 0) => v_cmp(2 downto 0),
- \v_dout_reg[7]\ => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2\
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(0),
- Q => \s_datao_fmc1[48]\(0),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(10),
- Q => \s_datao_fmc1[48]\(10),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(11),
- Q => \s_datao_fmc1[48]\(11),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(12),
- Q => \s_datao_fmc1[48]\(12),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(13),
- Q => \s_datao_fmc1[48]\(13),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(14),
- Q => \s_datao_fmc1[48]\(14),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(15),
- Q => \s_datao_fmc1[48]\(15),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(16),
- Q => \s_datao_fmc1[48]\(16),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(17),
- Q => \s_datao_fmc1[48]\(17),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(18),
- Q => \s_datao_fmc1[48]\(18),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(19),
- Q => \s_datao_fmc1[48]\(19),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(1),
- Q => \s_datao_fmc1[48]\(1),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(20),
- Q => \s_datao_fmc1[48]\(20),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(21),
- Q => \s_datao_fmc1[48]\(21),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(22),
- Q => \s_datao_fmc1[48]\(22),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(23),
- Q => \s_datao_fmc1[48]\(23),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(2),
- Q => \s_datao_fmc1[48]\(2),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(3),
- Q => \s_datao_fmc1[48]\(3),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(4),
- Q => \s_datao_fmc1[48]\(4),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(5),
- Q => \s_datao_fmc1[48]\(5),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(6),
- Q => \s_datao_fmc1[48]\(6),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(7),
- Q => \s_datao_fmc1[48]\(7),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(8),
- Q => \s_datao_fmc1[48]\(8),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(9),
- Q => \s_datao_fmc1[48]\(9),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(10),
- IB => \FMC1_LA_N_b[32]\(10),
- O => s_comparators_i_10
- );
-\fmc_03287_channels[10].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_102
- port map (
- D(0) => \^s_count_reg\(2),
- E(0) => \cmp_lengthCounter/RSTP_1\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_0\(4 downto 0),
- SR(0) => \^rst_i\,
- \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(23 downto 0) => \s_cmp_lengths[10]_10\(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc1[0]\(10),
- s_comparators_i_10 => s_comparators_i_10,
- \s_debounce_reg[1]\ => \s_buff2_i_1__9_n_0\
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(0),
- Q => \s_datao_fmc1[58]\(0),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(10),
- Q => \s_datao_fmc1[58]\(10),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(11),
- Q => \s_datao_fmc1[58]\(11),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(12),
- Q => \s_datao_fmc1[58]\(12),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(13),
- Q => \s_datao_fmc1[58]\(13),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(14),
- Q => \s_datao_fmc1[58]\(14),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(15),
- Q => \s_datao_fmc1[58]\(15),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(16),
- Q => \s_datao_fmc1[58]\(16),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(17),
- Q => \s_datao_fmc1[58]\(17),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(18),
- Q => \s_datao_fmc1[58]\(18),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(19),
- Q => \s_datao_fmc1[58]\(19),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(1),
- Q => \s_datao_fmc1[58]\(1),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(20),
- Q => \s_datao_fmc1[58]\(20),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(21),
- Q => \s_datao_fmc1[58]\(21),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(22),
- Q => \s_datao_fmc1[58]\(22),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(23),
- Q => \s_datao_fmc1[58]\(23),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(2),
- Q => \s_datao_fmc1[58]\(2),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(3),
- Q => \s_datao_fmc1[58]\(3),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(4),
- Q => \s_datao_fmc1[58]\(4),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(5),
- Q => \s_datao_fmc1[58]\(5),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(6),
- Q => \s_datao_fmc1[58]\(6),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(7),
- Q => \s_datao_fmc1[58]\(7),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(8),
- Q => \s_datao_fmc1[58]\(8),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(9),
- Q => \s_datao_fmc1[58]\(9),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(11),
- IB => \FMC1_LA_N_b[32]\(11),
- O => s_comparators_i_11
- );
-\fmc_03287_channels[11].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_103
- port map (
- D(0) => \^s_count_reg\(3),
- E(0) => \cmp_lengthCounter/RSTP_3\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_2\(4 downto 0),
- SR(0) => \^rst_i\,
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(23 downto 0) => \s_cmp_lengths[11]_11\(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc1[0]\(11),
- s_comparators_i_11 => s_comparators_i_11,
- \s_debounce_reg[1]\ => \s_buff2_i_1__10_n_0\
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(0),
- Q => \s_datao_fmc1[59]\(0),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(10),
- Q => \s_datao_fmc1[59]\(10),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(11),
- Q => \s_datao_fmc1[59]\(11),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(12),
- Q => \s_datao_fmc1[59]\(12),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(13),
- Q => \s_datao_fmc1[59]\(13),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(14),
- Q => \s_datao_fmc1[59]\(14),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(15),
- Q => \s_datao_fmc1[59]\(15),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(16),
- Q => \s_datao_fmc1[59]\(16),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(17),
- Q => \s_datao_fmc1[59]\(17),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(18),
- Q => \s_datao_fmc1[59]\(18),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(19),
- Q => \s_datao_fmc1[59]\(19),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(1),
- Q => \s_datao_fmc1[59]\(1),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(20),
- Q => \s_datao_fmc1[59]\(20),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(21),
- Q => \s_datao_fmc1[59]\(21),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(22),
- Q => \s_datao_fmc1[59]\(22),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(23),
- Q => \s_datao_fmc1[59]\(23),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(2),
- Q => \s_datao_fmc1[59]\(2),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(3),
- Q => \s_datao_fmc1[59]\(3),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(4),
- Q => \s_datao_fmc1[59]\(4),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(5),
- Q => \s_datao_fmc1[59]\(5),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(6),
- Q => \s_datao_fmc1[59]\(6),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(7),
- Q => \s_datao_fmc1[59]\(7),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(8),
- Q => \s_datao_fmc1[59]\(8),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(9),
- Q => \s_datao_fmc1[59]\(9),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(12),
- IB => \FMC1_LA_N_b[32]\(12),
- O => s_comparators_i_12
- );
-\fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_104
- port map (
- D(0) => \^s_count_reg\(4),
- E(0) => \cmp_lengthCounter/RSTP_5\,
- Q(2 downto 0) => v_cmpled(14 downto 12),
- S(0) => \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_2\,
- SR(0) => \^rst_i\,
- \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(23 downto 0) => \s_cmp_lengths[12]_12\(23 downto 0),
- intr_o_reg(0) => \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_3\,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_4\(4 downto 0),
- s_buff2_reg_0(1 downto 0) => \^s_datao_fmc1[0]\(14 downto 13),
- s_buff3_reg(0) => \^s_datao_fmc1[0]\(12),
- s_comparators_i_12 => s_comparators_i_12,
- \s_debounce_reg[1]\ => \s_buff2_i_1__11_n_0\,
- s_pulseLed_reg_0(1 downto 0) => \^s_count_reg\(6 downto 5),
- \v_cmp_reg[14]\(2 downto 0) => v_cmp(14 downto 12)
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(0),
- Q => \s_datao_fmc1[60]\(0),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(10),
- Q => \s_datao_fmc1[60]\(10),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(11),
- Q => \s_datao_fmc1[60]\(11),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(12),
- Q => \s_datao_fmc1[60]\(12),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(13),
- Q => \s_datao_fmc1[60]\(13),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(14),
- Q => \s_datao_fmc1[60]\(14),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(15),
- Q => \s_datao_fmc1[60]\(15),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(16),
- Q => \s_datao_fmc1[60]\(16),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(17),
- Q => \s_datao_fmc1[60]\(17),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(18),
- Q => \s_datao_fmc1[60]\(18),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(19),
- Q => \s_datao_fmc1[60]\(19),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(1),
- Q => \s_datao_fmc1[60]\(1),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(20),
- Q => \s_datao_fmc1[60]\(20),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(21),
- Q => \s_datao_fmc1[60]\(21),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(22),
- Q => \s_datao_fmc1[60]\(22),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(23),
- Q => \s_datao_fmc1[60]\(23),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(2),
- Q => \s_datao_fmc1[60]\(2),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(3),
- Q => \s_datao_fmc1[60]\(3),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(4),
- Q => \s_datao_fmc1[60]\(4),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(5),
- Q => \s_datao_fmc1[60]\(5),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(6),
- Q => \s_datao_fmc1[60]\(6),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(7),
- Q => \s_datao_fmc1[60]\(7),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(8),
- Q => \s_datao_fmc1[60]\(8),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(9),
- Q => \s_datao_fmc1[60]\(9),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(13),
- IB => \FMC1_LA_N_b[32]\(13),
- O => s_comparators_i_13
- );
-\fmc_03287_channels[13].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_105
- port map (
- D(0) => \^s_count_reg\(5),
- E(0) => \cmp_lengthCounter/RSTP_7\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_6\(4 downto 0),
- SR(0) => \^rst_i\,
- \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(23 downto 0) => \s_cmp_lengths[13]_13\(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc1[0]\(13),
- s_comparators_i_13 => s_comparators_i_13,
- \s_debounce_reg[1]\ => \s_buff2_i_1__12_n_0\
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(0),
- Q => \s_datao_fmc1[61]\(0),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(10),
- Q => \s_datao_fmc1[61]\(10),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(11),
- Q => \s_datao_fmc1[61]\(11),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(12),
- Q => \s_datao_fmc1[61]\(12),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(13),
- Q => \s_datao_fmc1[61]\(13),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(14),
- Q => \s_datao_fmc1[61]\(14),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(15),
- Q => \s_datao_fmc1[61]\(15),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(16),
- Q => \s_datao_fmc1[61]\(16),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(17),
- Q => \s_datao_fmc1[61]\(17),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(18),
- Q => \s_datao_fmc1[61]\(18),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(19),
- Q => \s_datao_fmc1[61]\(19),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(1),
- Q => \s_datao_fmc1[61]\(1),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(20),
- Q => \s_datao_fmc1[61]\(20),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(21),
- Q => \s_datao_fmc1[61]\(21),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(22),
- Q => \s_datao_fmc1[61]\(22),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(23),
- Q => \s_datao_fmc1[61]\(23),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(2),
- Q => \s_datao_fmc1[61]\(2),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(3),
- Q => \s_datao_fmc1[61]\(3),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(4),
- Q => \s_datao_fmc1[61]\(4),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(5),
- Q => \s_datao_fmc1[61]\(5),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(6),
- Q => \s_datao_fmc1[61]\(6),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(7),
- Q => \s_datao_fmc1[61]\(7),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(8),
- Q => \s_datao_fmc1[61]\(8),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(9),
- Q => \s_datao_fmc1[61]\(9),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(14),
- IB => \FMC1_LA_N_b[32]\(14),
- O => s_comparators_i_14
- );
-\fmc_03287_channels[14].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_106
- port map (
- D(0) => \^s_count_reg\(6),
- E(0) => \cmp_lengthCounter/RSTP_9\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_8\(4 downto 0),
- SR(0) => \^rst_i\,
- \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(23 downto 0) => \s_cmp_lengths[14]_14\(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc1[0]\(14),
- s_comparators_i_14 => s_comparators_i_14,
- \s_debounce_reg[1]\ => \s_buff2_i_1__13_n_0\
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(0),
- Q => \s_datao_fmc1[62]\(0),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(10),
- Q => \s_datao_fmc1[62]\(10),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(11),
- Q => \s_datao_fmc1[62]\(11),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(12),
- Q => \s_datao_fmc1[62]\(12),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(13),
- Q => \s_datao_fmc1[62]\(13),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(14),
- Q => \s_datao_fmc1[62]\(14),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(15),
- Q => \s_datao_fmc1[62]\(15),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(16),
- Q => \s_datao_fmc1[62]\(16),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(17),
- Q => \s_datao_fmc1[62]\(17),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(18),
- Q => \s_datao_fmc1[62]\(18),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(19),
- Q => \s_datao_fmc1[62]\(19),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(1),
- Q => \s_datao_fmc1[62]\(1),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(20),
- Q => \s_datao_fmc1[62]\(20),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(21),
- Q => \s_datao_fmc1[62]\(21),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(22),
- Q => \s_datao_fmc1[62]\(22),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(23),
- Q => \s_datao_fmc1[62]\(23),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(2),
- Q => \s_datao_fmc1[62]\(2),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(3),
- Q => \s_datao_fmc1[62]\(3),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(4),
- Q => \s_datao_fmc1[62]\(4),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(5),
- Q => \s_datao_fmc1[62]\(5),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(6),
- Q => \s_datao_fmc1[62]\(6),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(7),
- Q => \s_datao_fmc1[62]\(7),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(8),
- Q => \s_datao_fmc1[62]\(8),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(9),
- Q => \s_datao_fmc1[62]\(9),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(15),
- IB => \FMC1_LA_N_b[32]\(15),
- O => s_comparators_i_15
- );
-\fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_107
- port map (
- D(0) => \^s_count_reg\(7),
- E(0) => \cmp_lengthCounter/RSTP_11\,
- Q(2 downto 0) => v_cmpled(17 downto 15),
- S(0) => \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_2\,
- SR(0) => \^rst_i\,
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(23 downto 0) => \s_cmp_lengths[15]_15\(23 downto 0),
- intr_o_reg(0) => \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_3\,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_10\(4 downto 0),
- s_buff2_reg_0(1 downto 0) => \^s_datao_fmc1[0]\(17 downto 16),
- s_buff3_reg(0) => \^s_datao_fmc1[0]\(15),
- s_comparators_i_15 => s_comparators_i_15,
- \s_debounce_reg[1]\ => \s_buff2_i_1__14_n_0\,
- s_pulseLed_reg_0(1 downto 0) => \^s_count_reg\(9 downto 8),
- \v_cmp_reg[17]\(2 downto 0) => v_cmp(17 downto 15)
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(0),
- Q => \s_datao_fmc1[63]\(0),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(10),
- Q => \s_datao_fmc1[63]\(10),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(11),
- Q => \s_datao_fmc1[63]\(11),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(12),
- Q => \s_datao_fmc1[63]\(12),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(13),
- Q => \s_datao_fmc1[63]\(13),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(14),
- Q => \s_datao_fmc1[63]\(14),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(15),
- Q => \s_datao_fmc1[63]\(15),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(16),
- Q => \s_datao_fmc1[63]\(16),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(17),
- Q => \s_datao_fmc1[63]\(17),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(18),
- Q => \s_datao_fmc1[63]\(18),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(19),
- Q => \s_datao_fmc1[63]\(19),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(1),
- Q => \s_datao_fmc1[63]\(1),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(20),
- Q => \s_datao_fmc1[63]\(20),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(21),
- Q => \s_datao_fmc1[63]\(21),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(22),
- Q => \s_datao_fmc1[63]\(22),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(23),
- Q => \s_datao_fmc1[63]\(23),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(2),
- Q => \s_datao_fmc1[63]\(2),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(3),
- Q => \s_datao_fmc1[63]\(3),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(4),
- Q => \s_datao_fmc1[63]\(4),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(5),
- Q => \s_datao_fmc1[63]\(5),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(6),
- Q => \s_datao_fmc1[63]\(6),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(7),
- Q => \s_datao_fmc1[63]\(7),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(8),
- Q => \s_datao_fmc1[63]\(8),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(9),
- Q => \s_datao_fmc1[63]\(9),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(16),
- IB => \FMC1_LA_N_b[32]\(16),
- O => s_comparators_i_16
- );
-\fmc_03287_channels[16].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_108
- port map (
- D(0) => \^s_count_reg\(8),
- E(0) => \cmp_lengthCounter/RSTP_13\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_12\(4 downto 0),
- SR(0) => \^rst_i\,
- \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(23 downto 0) => \s_cmp_lengths[16]_16\(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc1[0]\(16),
- s_comparators_i_16 => s_comparators_i_16,
- \s_debounce_reg[1]\ => \s_buff2_i_1__15_n_0\
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(0),
- Q => \s_datao_fmc1[64]\(0),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(10),
- Q => \s_datao_fmc1[64]\(10),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(11),
- Q => \s_datao_fmc1[64]\(11),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(12),
- Q => \s_datao_fmc1[64]\(12),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(13),
- Q => \s_datao_fmc1[64]\(13),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(14),
- Q => \s_datao_fmc1[64]\(14),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(15),
- Q => \s_datao_fmc1[64]\(15),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(16),
- Q => \s_datao_fmc1[64]\(16),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(17),
- Q => \s_datao_fmc1[64]\(17),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(18),
- Q => \s_datao_fmc1[64]\(18),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(19),
- Q => \s_datao_fmc1[64]\(19),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(1),
- Q => \s_datao_fmc1[64]\(1),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(20),
- Q => \s_datao_fmc1[64]\(20),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(21),
- Q => \s_datao_fmc1[64]\(21),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(22),
- Q => \s_datao_fmc1[64]\(22),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(23),
- Q => \s_datao_fmc1[64]\(23),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(2),
- Q => \s_datao_fmc1[64]\(2),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(3),
- Q => \s_datao_fmc1[64]\(3),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(4),
- Q => \s_datao_fmc1[64]\(4),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(5),
- Q => \s_datao_fmc1[64]\(5),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(6),
- Q => \s_datao_fmc1[64]\(6),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(7),
- Q => \s_datao_fmc1[64]\(7),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(8),
- Q => \s_datao_fmc1[64]\(8),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(9),
- Q => \s_datao_fmc1[64]\(9),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(17),
- IB => \FMC1_LA_N_b[32]\(17),
- O => s_comparators_i_17
- );
-\fmc_03287_channels[17].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_109
- port map (
- D(0) => \^s_count_reg\(9),
- E(0) => \cmp_lengthCounter/RSTP_15\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_14\(4 downto 0),
- SR(0) => \^rst_i\,
- \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(23 downto 0) => \s_cmp_lengths[17]_17\(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc1[0]\(17),
- s_comparators_i_17 => s_comparators_i_17,
- \s_debounce_reg[1]\ => \s_buff2_i_1__16_n_0\
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(0),
- Q => \s_datao_fmc1[65]\(0),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(10),
- Q => \s_datao_fmc1[65]\(10),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(11),
- Q => \s_datao_fmc1[65]\(11),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(12),
- Q => \s_datao_fmc1[65]\(12),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(13),
- Q => \s_datao_fmc1[65]\(13),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(14),
- Q => \s_datao_fmc1[65]\(14),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(15),
- Q => \s_datao_fmc1[65]\(15),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(16),
- Q => \s_datao_fmc1[65]\(16),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(17),
- Q => \s_datao_fmc1[65]\(17),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(18),
- Q => \s_datao_fmc1[65]\(18),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(19),
- Q => \s_datao_fmc1[65]\(19),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(1),
- Q => \s_datao_fmc1[65]\(1),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(20),
- Q => \s_datao_fmc1[65]\(20),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(21),
- Q => \s_datao_fmc1[65]\(21),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(22),
- Q => \s_datao_fmc1[65]\(22),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(23),
- Q => \s_datao_fmc1[65]\(23),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(2),
- Q => \s_datao_fmc1[65]\(2),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(3),
- Q => \s_datao_fmc1[65]\(3),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(4),
- Q => \s_datao_fmc1[65]\(4),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(5),
- Q => \s_datao_fmc1[65]\(5),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(6),
- Q => \s_datao_fmc1[65]\(6),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(7),
- Q => \s_datao_fmc1[65]\(7),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(8),
- Q => \s_datao_fmc1[65]\(8),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(9),
- Q => \s_datao_fmc1[65]\(9),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(18),
- IB => \FMC1_LA_N_b[32]\(18),
- O => s_comparators_i_18
- );
-\fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_110
- port map (
- D(0) => \^s_count_reg\(10),
- E(0) => \cmp_lengthCounter/RSTP_17\,
- Q(1 downto 0) => v_cmpled(19 downto 18),
- S(0) => \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_2\,
- SR(0) => \^rst_i\,
- \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(23 downto 0) => \s_cmp_lengths[18]_18\(23 downto 0),
- intr_o_reg(0) => \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_3\,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_16\(4 downto 0),
- s_buff2_reg_0(0) => \^s_datao_fmc1[0]\(19),
- s_buff3_reg(0) => \^s_datao_fmc1[0]\(18),
- s_comparators_i_18 => s_comparators_i_18,
- \s_debounce_reg[1]\ => \s_buff2_i_1__17_n_0\,
- s_pulseLed_reg_0(0) => \^s_count_reg\(11),
- \v_cmp_reg[19]\(1 downto 0) => v_cmp(19 downto 18)
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(0),
- Q => \s_datao_fmc1[66]\(0),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(10),
- Q => \s_datao_fmc1[66]\(10),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(11),
- Q => \s_datao_fmc1[66]\(11),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(12),
- Q => \s_datao_fmc1[66]\(12),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(13),
- Q => \s_datao_fmc1[66]\(13),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(14),
- Q => \s_datao_fmc1[66]\(14),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(15),
- Q => \s_datao_fmc1[66]\(15),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(16),
- Q => \s_datao_fmc1[66]\(16),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(17),
- Q => \s_datao_fmc1[66]\(17),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(18),
- Q => \s_datao_fmc1[66]\(18),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(19),
- Q => \s_datao_fmc1[66]\(19),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(1),
- Q => \s_datao_fmc1[66]\(1),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(20),
- Q => \s_datao_fmc1[66]\(20),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(21),
- Q => \s_datao_fmc1[66]\(21),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(22),
- Q => \s_datao_fmc1[66]\(22),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(23),
- Q => \s_datao_fmc1[66]\(23),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(2),
- Q => \s_datao_fmc1[66]\(2),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(3),
- Q => \s_datao_fmc1[66]\(3),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(4),
- Q => \s_datao_fmc1[66]\(4),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(5),
- Q => \s_datao_fmc1[66]\(5),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(6),
- Q => \s_datao_fmc1[66]\(6),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(7),
- Q => \s_datao_fmc1[66]\(7),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(8),
- Q => \s_datao_fmc1[66]\(8),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(9),
- Q => \s_datao_fmc1[66]\(9),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(19),
- IB => \FMC1_LA_N_b[32]\(19),
- O => s_comparators_i_19
- );
-\fmc_03287_channels[19].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_111
- port map (
- D(0) => \^s_count_reg\(11),
- E(0) => \cmp_lengthCounter/RSTP_19\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_18\(4 downto 0),
- SR(0) => \^rst_i\,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(23 downto 0) => \s_cmp_lengths[19]_19\(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc1[0]\(19),
- s_comparators_i_19 => s_comparators_i_19,
- \s_debounce_reg[1]\ => \s_buff2_i_1__18_n_0\
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(0),
- Q => \s_datao_fmc1[67]\(0),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(10),
- Q => \s_datao_fmc1[67]\(10),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(11),
- Q => \s_datao_fmc1[67]\(11),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(12),
- Q => \s_datao_fmc1[67]\(12),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(13),
- Q => \s_datao_fmc1[67]\(13),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(14),
- Q => \s_datao_fmc1[67]\(14),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(15),
- Q => \s_datao_fmc1[67]\(15),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(16),
- Q => \s_datao_fmc1[67]\(16),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(17),
- Q => \s_datao_fmc1[67]\(17),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(18),
- Q => \s_datao_fmc1[67]\(18),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(19),
- Q => \s_datao_fmc1[67]\(19),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(1),
- Q => \s_datao_fmc1[67]\(1),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(20),
- Q => \s_datao_fmc1[67]\(20),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(21),
- Q => \s_datao_fmc1[67]\(21),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(22),
- Q => \s_datao_fmc1[67]\(22),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(23),
- Q => \s_datao_fmc1[67]\(23),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(2),
- Q => \s_datao_fmc1[67]\(2),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(3),
- Q => \s_datao_fmc1[67]\(3),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(4),
- Q => \s_datao_fmc1[67]\(4),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(5),
- Q => \s_datao_fmc1[67]\(5),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(6),
- Q => \s_datao_fmc1[67]\(6),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(7),
- Q => \s_datao_fmc1[67]\(7),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(8),
- Q => \s_datao_fmc1[67]\(8),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(9),
- Q => \s_datao_fmc1[67]\(9),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(1),
- IB => \FMC1_LA_N_b[32]\(1),
- O => s_comparators_i_1
- );
-\fmc_03287_channels[1].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_112
- port map (
- D(0) => \^s_datao_fmc1[0]\(1),
- E(0) => \cmp_lengthCounter/RSTP_21\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_20\(4 downto 0),
- SR(0) => \^rst_i\,
- \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(23 downto 0) => \s_cmp_lengths[1]_1\(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_comparators_i_1 => s_comparators_i_1,
- s_count_reg(0) => \s_datao_fmc1[4]\(1),
- \s_debounce_reg[1]\ => \s_buff2_i_1__0_n_0\
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(0),
- Q => \s_datao_fmc1[49]\(0),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(10),
- Q => \s_datao_fmc1[49]\(10),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(11),
- Q => \s_datao_fmc1[49]\(11),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(12),
- Q => \s_datao_fmc1[49]\(12),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(13),
- Q => \s_datao_fmc1[49]\(13),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(14),
- Q => \s_datao_fmc1[49]\(14),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(15),
- Q => \s_datao_fmc1[49]\(15),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(16),
- Q => \s_datao_fmc1[49]\(16),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(17),
- Q => \s_datao_fmc1[49]\(17),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(18),
- Q => \s_datao_fmc1[49]\(18),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(19),
- Q => \s_datao_fmc1[49]\(19),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(1),
- Q => \s_datao_fmc1[49]\(1),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(20),
- Q => \s_datao_fmc1[49]\(20),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(21),
- Q => \s_datao_fmc1[49]\(21),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(22),
- Q => \s_datao_fmc1[49]\(22),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(23),
- Q => \s_datao_fmc1[49]\(23),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(2),
- Q => \s_datao_fmc1[49]\(2),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(3),
- Q => \s_datao_fmc1[49]\(3),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(4),
- Q => \s_datao_fmc1[49]\(4),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(5),
- Q => \s_datao_fmc1[49]\(5),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(6),
- Q => \s_datao_fmc1[49]\(6),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(7),
- Q => \s_datao_fmc1[49]\(7),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(8),
- Q => \s_datao_fmc1[49]\(8),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(9),
- Q => \s_datao_fmc1[49]\(9),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(2),
- IB => \FMC1_LA_N_b[32]\(2),
- O => s_comparators_i_2
- );
-\fmc_03287_channels[2].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_113
- port map (
- D(0) => \^s_datao_fmc1[0]\(2),
- E(0) => \cmp_lengthCounter/RSTP_23\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_22\(4 downto 0),
- SR(0) => \^rst_i\,
- \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(23 downto 0) => \s_cmp_lengths[2]_2\(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_comparators_i_2 => s_comparators_i_2,
- s_count_reg(0) => \s_datao_fmc1[4]\(2),
- \s_debounce_reg[1]\ => \s_buff2_i_1__1_n_0\
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(0),
- Q => \s_datao_fmc1[50]\(0),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(10),
- Q => \s_datao_fmc1[50]\(10),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(11),
- Q => \s_datao_fmc1[50]\(11),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(12),
- Q => \s_datao_fmc1[50]\(12),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(13),
- Q => \s_datao_fmc1[50]\(13),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(14),
- Q => \s_datao_fmc1[50]\(14),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(15),
- Q => \s_datao_fmc1[50]\(15),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(16),
- Q => \s_datao_fmc1[50]\(16),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(17),
- Q => \s_datao_fmc1[50]\(17),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(18),
- Q => \s_datao_fmc1[50]\(18),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(19),
- Q => \s_datao_fmc1[50]\(19),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(1),
- Q => \s_datao_fmc1[50]\(1),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(20),
- Q => \s_datao_fmc1[50]\(20),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(21),
- Q => \s_datao_fmc1[50]\(21),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(22),
- Q => \s_datao_fmc1[50]\(22),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(23),
- Q => \s_datao_fmc1[50]\(23),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(2),
- Q => \s_datao_fmc1[50]\(2),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(3),
- Q => \s_datao_fmc1[50]\(3),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(4),
- Q => \s_datao_fmc1[50]\(4),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(5),
- Q => \s_datao_fmc1[50]\(5),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(6),
- Q => \s_datao_fmc1[50]\(6),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(7),
- Q => \s_datao_fmc1[50]\(7),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(8),
- Q => \s_datao_fmc1[50]\(8),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(9),
- Q => \s_datao_fmc1[50]\(9),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(3),
- IB => \FMC1_LA_N_b[32]\(3),
- O => s_comparators_i_3
- );
-\fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_114
- port map (
- D(0) => \^s_datao_fmc1[0]\(3),
- E(0) => \cmp_lengthCounter/RSTP_25\,
- Q(2 downto 0) => v_cmpled(5 downto 3),
- S(0) => \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_2\,
- SR(0) => \^rst_i\,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(23 downto 0) => \s_cmp_lengths[3]_3\(23 downto 0),
- intr_o_reg(0) => \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_3\,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_24\(4 downto 0),
- s_buff2_reg_0(1 downto 0) => \^s_datao_fmc1[0]\(5 downto 4),
- s_comparators_i_3 => s_comparators_i_3,
- \s_datao_fmc1[4]\(0) => \s_datao_fmc1[4]\(3),
- \s_debounce_reg[1]\ => \s_buff2_i_1__2_n_0\,
- s_pulseLed_reg_0(1 downto 0) => \s_datao_fmc1[4]\(5 downto 4),
- \v_cmp_reg[5]\(2 downto 0) => v_cmp(5 downto 3)
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(0),
- Q => \s_datao_fmc1[51]\(0),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(10),
- Q => \s_datao_fmc1[51]\(10),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(11),
- Q => \s_datao_fmc1[51]\(11),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(12),
- Q => \s_datao_fmc1[51]\(12),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(13),
- Q => \s_datao_fmc1[51]\(13),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(14),
- Q => \s_datao_fmc1[51]\(14),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(15),
- Q => \s_datao_fmc1[51]\(15),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(16),
- Q => \s_datao_fmc1[51]\(16),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(17),
- Q => \s_datao_fmc1[51]\(17),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(18),
- Q => \s_datao_fmc1[51]\(18),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(19),
- Q => \s_datao_fmc1[51]\(19),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(1),
- Q => \s_datao_fmc1[51]\(1),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(20),
- Q => \s_datao_fmc1[51]\(20),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(21),
- Q => \s_datao_fmc1[51]\(21),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(22),
- Q => \s_datao_fmc1[51]\(22),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(23),
- Q => \s_datao_fmc1[51]\(23),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(2),
- Q => \s_datao_fmc1[51]\(2),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(3),
- Q => \s_datao_fmc1[51]\(3),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(4),
- Q => \s_datao_fmc1[51]\(4),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(5),
- Q => \s_datao_fmc1[51]\(5),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(6),
- Q => \s_datao_fmc1[51]\(6),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(7),
- Q => \s_datao_fmc1[51]\(7),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(8),
- Q => \s_datao_fmc1[51]\(8),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(9),
- Q => \s_datao_fmc1[51]\(9),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(4),
- IB => \FMC1_LA_N_b[32]\(4),
- O => s_comparators_i_4
- );
-\fmc_03287_channels[4].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_115
- port map (
- D(0) => \^s_datao_fmc1[0]\(4),
- E(0) => \cmp_lengthCounter/RSTP_27\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_26\(4 downto 0),
- SR(0) => \^rst_i\,
- \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(23 downto 0) => \s_cmp_lengths[4]_4\(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_comparators_i_4 => s_comparators_i_4,
- s_count_reg(0) => \s_datao_fmc1[4]\(4),
- \s_debounce_reg[1]\ => \s_buff2_i_1__3_n_0\
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(0),
- Q => \s_datao_fmc1[52]\(0),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(10),
- Q => \s_datao_fmc1[52]\(10),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(11),
- Q => \s_datao_fmc1[52]\(11),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(12),
- Q => \s_datao_fmc1[52]\(12),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(13),
- Q => \s_datao_fmc1[52]\(13),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(14),
- Q => \s_datao_fmc1[52]\(14),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(15),
- Q => \s_datao_fmc1[52]\(15),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(16),
- Q => \s_datao_fmc1[52]\(16),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(17),
- Q => \s_datao_fmc1[52]\(17),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(18),
- Q => \s_datao_fmc1[52]\(18),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(19),
- Q => \s_datao_fmc1[52]\(19),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(1),
- Q => \s_datao_fmc1[52]\(1),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(20),
- Q => \s_datao_fmc1[52]\(20),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(21),
- Q => \s_datao_fmc1[52]\(21),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(22),
- Q => \s_datao_fmc1[52]\(22),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(23),
- Q => \s_datao_fmc1[52]\(23),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(2),
- Q => \s_datao_fmc1[52]\(2),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(3),
- Q => \s_datao_fmc1[52]\(3),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(4),
- Q => \s_datao_fmc1[52]\(4),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(5),
- Q => \s_datao_fmc1[52]\(5),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(6),
- Q => \s_datao_fmc1[52]\(6),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(7),
- Q => \s_datao_fmc1[52]\(7),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(8),
- Q => \s_datao_fmc1[52]\(8),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(9),
- Q => \s_datao_fmc1[52]\(9),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(5),
- IB => \FMC1_LA_N_b[32]\(5),
- O => s_comparators_i_5
- );
-\fmc_03287_channels[5].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_116
- port map (
- D(0) => \^s_datao_fmc1[0]\(5),
- E(0) => \cmp_lengthCounter/RSTP_29\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_28\(4 downto 0),
- SR(0) => \^rst_i\,
- \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(23 downto 0) => \s_cmp_lengths[5]_5\(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_comparators_i_5 => s_comparators_i_5,
- s_count_reg(0) => \s_datao_fmc1[4]\(5),
- \s_debounce_reg[1]\ => \s_buff2_i_1__4_n_0\
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(0),
- Q => \s_datao_fmc1[53]\(0),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(10),
- Q => \s_datao_fmc1[53]\(10),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(11),
- Q => \s_datao_fmc1[53]\(11),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(12),
- Q => \s_datao_fmc1[53]\(12),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(13),
- Q => \s_datao_fmc1[53]\(13),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(14),
- Q => \s_datao_fmc1[53]\(14),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(15),
- Q => \s_datao_fmc1[53]\(15),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(16),
- Q => \s_datao_fmc1[53]\(16),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(17),
- Q => \s_datao_fmc1[53]\(17),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(18),
- Q => \s_datao_fmc1[53]\(18),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(19),
- Q => \s_datao_fmc1[53]\(19),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(1),
- Q => \s_datao_fmc1[53]\(1),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(20),
- Q => \s_datao_fmc1[53]\(20),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(21),
- Q => \s_datao_fmc1[53]\(21),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(22),
- Q => \s_datao_fmc1[53]\(22),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(23),
- Q => \s_datao_fmc1[53]\(23),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(2),
- Q => \s_datao_fmc1[53]\(2),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(3),
- Q => \s_datao_fmc1[53]\(3),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(4),
- Q => \s_datao_fmc1[53]\(4),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(5),
- Q => \s_datao_fmc1[53]\(5),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(6),
- Q => \s_datao_fmc1[53]\(6),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(7),
- Q => \s_datao_fmc1[53]\(7),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(8),
- Q => \s_datao_fmc1[53]\(8),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(9),
- Q => \s_datao_fmc1[53]\(9),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(6),
- IB => \FMC1_LA_N_b[32]\(6),
- O => s_comparators_i_6
- );
-\fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_117
- port map (
- D(0) => \^s_datao_fmc1[0]\(6),
- E(0) => \cmp_lengthCounter/RSTP_31\,
- Q(2 downto 0) => v_cmpled(8 downto 6),
- S(0) => \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_2\,
- SR(0) => \^rst_i\,
- \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(23 downto 0) => \s_cmp_lengths[6]_6\(23 downto 0),
- intr_o_reg(0) => \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_3\,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_30\(4 downto 0),
- s_buff2_reg_0(1 downto 0) => \^s_datao_fmc1[0]\(8 downto 7),
- s_comparators_i_6 => s_comparators_i_6,
- \s_datao_fmc1[4]\(0) => \s_datao_fmc1[4]\(6),
- \s_debounce_reg[1]\ => \s_buff2_i_1__5_n_0\,
- s_pulseLed_reg_0(1) => \^s_count_reg\(0),
- s_pulseLed_reg_0(0) => \s_datao_fmc1[4]\(7),
- \v_cmp_reg[8]\(2 downto 0) => v_cmp(8 downto 6)
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(0),
- Q => \s_datao_fmc1[54]\(0),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(10),
- Q => \s_datao_fmc1[54]\(10),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(11),
- Q => \s_datao_fmc1[54]\(11),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(12),
- Q => \s_datao_fmc1[54]\(12),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(13),
- Q => \s_datao_fmc1[54]\(13),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(14),
- Q => \s_datao_fmc1[54]\(14),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(15),
- Q => \s_datao_fmc1[54]\(15),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(16),
- Q => \s_datao_fmc1[54]\(16),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(17),
- Q => \s_datao_fmc1[54]\(17),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(18),
- Q => \s_datao_fmc1[54]\(18),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(19),
- Q => \s_datao_fmc1[54]\(19),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(1),
- Q => \s_datao_fmc1[54]\(1),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(20),
- Q => \s_datao_fmc1[54]\(20),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(21),
- Q => \s_datao_fmc1[54]\(21),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(22),
- Q => \s_datao_fmc1[54]\(22),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(23),
- Q => \s_datao_fmc1[54]\(23),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(2),
- Q => \s_datao_fmc1[54]\(2),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(3),
- Q => \s_datao_fmc1[54]\(3),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(4),
- Q => \s_datao_fmc1[54]\(4),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(5),
- Q => \s_datao_fmc1[54]\(5),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(6),
- Q => \s_datao_fmc1[54]\(6),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(7),
- Q => \s_datao_fmc1[54]\(7),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(8),
- Q => \s_datao_fmc1[54]\(8),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(9),
- Q => \s_datao_fmc1[54]\(9),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(7),
- IB => \FMC1_LA_N_b[32]\(7),
- O => s_comparators_i_7
- );
-\fmc_03287_channels[7].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_118
- port map (
- D(0) => \^s_datao_fmc1[0]\(7),
- E(0) => \cmp_lengthCounter/RSTP_33\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_32\(4 downto 0),
- SR(0) => \^rst_i\,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(23 downto 0) => \s_cmp_lengths[7]_7\(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_comparators_i_7 => s_comparators_i_7,
- s_count_reg(0) => \s_datao_fmc1[4]\(7),
- \s_debounce_reg[1]\ => \s_buff2_i_1__6_n_0\
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(0),
- Q => \s_datao_fmc1[55]\(0),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(10),
- Q => \s_datao_fmc1[55]\(10),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(11),
- Q => \s_datao_fmc1[55]\(11),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(12),
- Q => \s_datao_fmc1[55]\(12),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(13),
- Q => \s_datao_fmc1[55]\(13),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(14),
- Q => \s_datao_fmc1[55]\(14),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(15),
- Q => \s_datao_fmc1[55]\(15),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(16),
- Q => \s_datao_fmc1[55]\(16),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(17),
- Q => \s_datao_fmc1[55]\(17),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(18),
- Q => \s_datao_fmc1[55]\(18),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(19),
- Q => \s_datao_fmc1[55]\(19),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(1),
- Q => \s_datao_fmc1[55]\(1),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(20),
- Q => \s_datao_fmc1[55]\(20),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(21),
- Q => \s_datao_fmc1[55]\(21),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(22),
- Q => \s_datao_fmc1[55]\(22),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(23),
- Q => \s_datao_fmc1[55]\(23),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(2),
- Q => \s_datao_fmc1[55]\(2),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(3),
- Q => \s_datao_fmc1[55]\(3),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(4),
- Q => \s_datao_fmc1[55]\(4),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(5),
- Q => \s_datao_fmc1[55]\(5),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(6),
- Q => \s_datao_fmc1[55]\(6),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(7),
- Q => \s_datao_fmc1[55]\(7),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(8),
- Q => \s_datao_fmc1[55]\(8),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(9),
- Q => \s_datao_fmc1[55]\(9),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(8),
- IB => \FMC1_LA_N_b[32]\(8),
- O => s_comparators_i_8
- );
-\fmc_03287_channels[8].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_119
- port map (
- D(0) => \^s_count_reg\(0),
- E(0) => \cmp_lengthCounter/RSTP_35\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_34\(4 downto 0),
- SR(0) => \^rst_i\,
- \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(23 downto 0) => \s_cmp_lengths[8]_8\(23 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc1[0]\(8),
- s_comparators_i_8 => s_comparators_i_8,
- \s_debounce_reg[1]\ => \s_buff2_i_1__7_n_0\
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(0),
- Q => \s_datao_fmc1[56]\(0),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(10),
- Q => \s_datao_fmc1[56]\(10),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(11),
- Q => \s_datao_fmc1[56]\(11),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(12),
- Q => \s_datao_fmc1[56]\(12),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(13),
- Q => \s_datao_fmc1[56]\(13),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(14),
- Q => \s_datao_fmc1[56]\(14),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(15),
- Q => \s_datao_fmc1[56]\(15),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(16),
- Q => \s_datao_fmc1[56]\(16),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(17),
- Q => \s_datao_fmc1[56]\(17),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(18),
- Q => \s_datao_fmc1[56]\(18),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(19),
- Q => \s_datao_fmc1[56]\(19),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(1),
- Q => \s_datao_fmc1[56]\(1),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(20),
- Q => \s_datao_fmc1[56]\(20),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(21),
- Q => \s_datao_fmc1[56]\(21),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(22),
- Q => \s_datao_fmc1[56]\(22),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(23),
- Q => \s_datao_fmc1[56]\(23),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(2),
- Q => \s_datao_fmc1[56]\(2),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(3),
- Q => \s_datao_fmc1[56]\(3),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(4),
- Q => \s_datao_fmc1[56]\(4),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(5),
- Q => \s_datao_fmc1[56]\(5),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(6),
- Q => \s_datao_fmc1[56]\(6),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(7),
- Q => \s_datao_fmc1[56]\(7),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(8),
- Q => \s_datao_fmc1[56]\(8),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(9),
- Q => \s_datao_fmc1[56]\(9),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC1_LA_P_b[32]\(9),
- IB => \FMC1_LA_N_b[32]\(9),
- O => s_comparators_i_9
- );
-\fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_120
- port map (
- CO(0) => intr_o0,
- D(0) => \^s_count_reg\(1),
- E(0) => \cmp_lengthCounter/RSTP_37\,
- Q(2 downto 0) => v_cmpled(11 downto 9),
- S(2) => \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_2\,
- S(1) => \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_2\,
- S(0) => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_3\,
- SR(0) => \^rst_i\,
- \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(23 downto 0) => \s_cmp_lengths[9]_9\(23 downto 0),
- intr_led_o_reg => \fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure_n_2\,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_36\(4 downto 0),
- s_buff2_reg_0(1 downto 0) => \^s_datao_fmc1[0]\(11 downto 10),
- s_buff3_reg(0) => \^s_datao_fmc1[0]\(9),
- s_comparators_i_9 => s_comparators_i_9,
- \s_debounce_reg[1]\ => \s_buff2_i_1__8_n_0\,
- s_pulseLed_reg_0 => \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_3\,
- s_pulseLed_reg_1(1 downto 0) => \^s_count_reg\(3 downto 2),
- \v_cmp_reg[11]\(2 downto 0) => v_cmp(11 downto 9),
- \v_cmp_reg[18]\(2) => \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_3\,
- \v_cmp_reg[18]\(1) => \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_3\,
- \v_cmp_reg[18]\(0) => \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_3\,
- \v_cmp_reg[6]\(2) => \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_3\,
- \v_cmp_reg[6]\(1) => \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_3\,
- \v_cmp_reg[6]\(0) => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_4\,
- \v_cmpled_reg[18]\(2) => \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_2\,
- \v_cmpled_reg[18]\(1) => \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_2\,
- \v_cmpled_reg[18]\(0) => \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_2\
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(0),
- Q => \s_datao_fmc1[57]\(0),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(10),
- Q => \s_datao_fmc1[57]\(10),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(11),
- Q => \s_datao_fmc1[57]\(11),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(12),
- Q => \s_datao_fmc1[57]\(12),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(13),
- Q => \s_datao_fmc1[57]\(13),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(14),
- Q => \s_datao_fmc1[57]\(14),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(15),
- Q => \s_datao_fmc1[57]\(15),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(16),
- Q => \s_datao_fmc1[57]\(16),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(17),
- Q => \s_datao_fmc1[57]\(17),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(18),
- Q => \s_datao_fmc1[57]\(18),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(19),
- Q => \s_datao_fmc1[57]\(19),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(1),
- Q => \s_datao_fmc1[57]\(1),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(20),
- Q => \s_datao_fmc1[57]\(20),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(21),
- Q => \s_datao_fmc1[57]\(21),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(22),
- Q => \s_datao_fmc1[57]\(22),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(23),
- Q => \s_datao_fmc1[57]\(23),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(2),
- Q => \s_datao_fmc1[57]\(2),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(3),
- Q => \s_datao_fmc1[57]\(3),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(4),
- Q => \s_datao_fmc1[57]\(4),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(5),
- Q => \s_datao_fmc1[57]\(5),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(6),
- Q => \s_datao_fmc1[57]\(6),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(7),
- Q => \s_datao_fmc1[57]\(7),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(8),
- Q => \s_datao_fmc1[57]\(8),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(9),
- Q => \s_datao_fmc1[57]\(9),
- R => '0'
- );
-\fmc_03287_obufds[0].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => D(0),
- O => \FMC1_LA_P_b[27]\(0),
- OB => \FMC1_LA_N_b[27]\(0)
- );
-\fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_121
- port map (
- D(0) => D(0),
- Q(0) => \s_datao_fmc1[6]\(0),
- SR(0) => \^rst_i\,
- \axi_araddr_reg[2]_rep__3\ => \axi_araddr_reg[2]_rep__3\,
- \axi_araddr_reg[3]_rep__3\ => \axi_araddr_reg[3]_rep__3\,
- \axi_rdata_reg[0]\ => \axi_rdata_reg[0]\,
- intr_led_o_reg => \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_3\,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_38\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_1\,
- \s_datao_fmc1[5]\(0) => \s_datao_fmc1[5]\(0),
- \s_debounce_reg[1]\ => \s_buff2_i_1__19_n_0\,
- s_pulseLed_reg_0(0) => \s_datao_fmc1[4]\(0),
- s_pulseLed_reg_1(1 downto 0) => \s_datao_fmc1[5]\(2 downto 1),
- \v_outleds_reg[2]\(2 downto 0) => v_outleds(2 downto 0)
- );
-\fmc_03287_obufds[1].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => D(1),
- O => \FMC1_LA_P_b[27]\(1),
- OB => \FMC1_LA_N_b[27]\(1)
- );
-\fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_122
- port map (
- D(0) => D(1),
- Q(0) => \s_datao_fmc1[6]\(1),
- SR(0) => \^rst_i\,
- \axi_araddr_reg[2]_rep__3\ => \axi_araddr_reg[2]_rep__3\,
- \axi_araddr_reg[3]_rep__3\ => \axi_araddr_reg[3]_rep__3\,
- \axi_rdata_reg[1]\ => \axi_rdata_reg[1]\,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_39\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure_n_1\,
- s_count_reg(0) => \s_datao_fmc1[5]\(1),
- \s_debounce_reg[1]\ => \s_buff2_i_1__20_n_0\,
- s_pulseLed_reg_0(0) => \s_datao_fmc1[4]\(1)
- );
-\fmc_03287_obufds[2].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => D(2),
- O => \FMC1_LA_P_b[27]\(2),
- OB => \FMC1_LA_N_b[27]\(2)
- );
-\fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_123
- port map (
- D(0) => D(2),
- Q(0) => \s_datao_fmc1[6]\(2),
- SR(0) => \^rst_i\,
- \axi_araddr_reg[2]_rep__3\ => \axi_araddr_reg[2]_rep__3\,
- \axi_araddr_reg[3]_rep__3\ => \axi_araddr_reg[3]_rep__3\,
- \axi_rdata_reg[2]\ => \axi_rdata_reg[2]\,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_40\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure_n_1\,
- s_count_reg(0) => \s_datao_fmc1[5]\(2),
- \s_debounce_reg[1]\ => \s_buff2_i_1__21_n_0\,
- s_pulseLed_reg_0(0) => \s_datao_fmc1[4]\(2)
- );
-\fmc_03287_obufds[3].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => D(3),
- O => \FMC1_LA_P_b[27]\(3),
- OB => \FMC1_LA_N_b[27]\(3)
- );
-\fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_124
- port map (
- D(0) => D(3),
- Q(0) => \s_datao_fmc1[6]\(3),
- SR(0) => \^rst_i\,
- \axi_araddr_reg[2]_rep__2\ => \axi_araddr_reg[2]_rep__2\,
- \axi_araddr_reg[3]_rep__2\ => \axi_araddr_reg[3]_rep__2\,
- \axi_rdata_reg[3]\ => \axi_rdata_reg[3]\,
- intr_led_o_reg => \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_3\,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_41\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_1\,
- \s_datao_fmc1[5]\(0) => \s_datao_fmc1[5]\(3),
- \s_debounce_reg[1]\ => \s_buff2_i_1__22_n_0\,
- s_pulseLed_reg_0(0) => \s_datao_fmc1[4]\(3),
- s_pulseLed_reg_1(1 downto 0) => \s_datao_fmc1[5]\(5 downto 4),
- \v_outleds_reg[5]\(2 downto 0) => v_outleds(5 downto 3)
- );
-\fmc_03287_obufds[4].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => s_diffouts_o(4),
- O => \FMC1_LA_P_b[27]\(4),
- OB => \FMC1_LA_N_b[27]\(4)
- );
-\fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_125
- port map (
- D(0) => \s_datao_fmc1[4]\(4),
- Q(0) => s_diffouts_o(4),
- SR(0) => \^rst_i\,
- \axi_araddr_reg[2]_rep__2\ => \axi_araddr_reg[2]_rep__2\,
- \axi_araddr_reg[3]_rep__2\ => \axi_araddr_reg[3]_rep__2\,
- \axi_rdata_reg[4]\ => \axi_rdata_reg[4]\,
- \data_o_reg[6][4]\(0) => \s_datao_fmc1[6]\(4),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_42\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure_n_1\,
- s_count_reg(0) => \s_datao_fmc1[5]\(4),
- \s_debounce_reg[1]\ => \s_buff2_i_1__23_n_0\
- );
-\fmc_03287_obufds[5].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => s_diffouts_o(5),
- O => \FMC1_LA_P_b[27]\(5),
- OB => \FMC1_LA_N_b[27]\(5)
- );
-\fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_126
- port map (
- D(0) => \s_datao_fmc1[4]\(5),
- Q(0) => s_diffouts_o(5),
- SR(0) => \^rst_i\,
- \axi_araddr_reg[2]_rep__2\ => \axi_araddr_reg[2]_rep__2\,
- \axi_araddr_reg[3]_rep__2\ => \axi_araddr_reg[3]_rep__2\,
- \axi_rdata_reg[5]\ => \axi_rdata_reg[5]\,
- \data_o_reg[6][5]\(0) => \s_datao_fmc1[6]\(5),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_43\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure_n_1\,
- s_count_reg(0) => \s_datao_fmc1[5]\(5),
- \s_debounce_reg[1]\ => \s_buff2_i_1__24_n_0\
- );
-\fmc_03287_obufds[6].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => s_diffouts_o(6),
- O => \FMC1_LA_P_b[27]\(6),
- OB => \FMC1_LA_N_b[27]\(6)
- );
-\fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_127
- port map (
- D(0) => \s_datao_fmc1[4]\(6),
- Q(0) => s_diffouts_o(6),
- SR(0) => \^rst_i\,
- \axi_araddr_reg[2]_rep__2\ => \axi_araddr_reg[2]_rep__2\,
- \axi_araddr_reg[3]_rep__2\ => \axi_araddr_reg[3]_rep__2\,
- \axi_rdata_reg[6]\ => \axi_rdata_reg[6]\,
- \data_o_reg[6][6]\(0) => \s_datao_fmc1[6]\(6),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_44\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure_n_1\,
- \s_datao_fmc1[5]\(0) => \s_datao_fmc1[5]\(6),
- \s_debounce_reg[1]\ => \s_buff2_i_1__25_n_0\
- );
-\fmc_03287_obufds[7].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => s_diffouts_o(7),
- O => \FMC1_LA_P_b[27]\(7),
- OB => \FMC1_LA_N_b[27]\(7)
- );
-\fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_128
- port map (
- D(0) => \s_datao_fmc1[4]\(7),
- Q(0) => s_diffouts_o(7),
- SR(0) => \^rst_i\,
- \axi_araddr_reg[2]_rep__2\ => \axi_araddr_reg[2]_rep__2\,
- \axi_araddr_reg[3]_rep__2\ => \axi_araddr_reg[3]_rep__2\,
- \axi_rdata_reg[7]\ => \axi_rdata_reg[7]\,
- \data_o_reg[6][7]\(0) => \s_datao_fmc1[6]\(7),
- intr_led_o_reg => \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_3\,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_45\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_1\,
- \s_datao_fmc1[5]\(0) => \s_datao_fmc1[5]\(7),
- \s_debounce_reg[1]\ => \s_buff2_i_1__26_n_0\,
- s_pulseLed_reg_0(0) => \s_datao_fmc1[5]\(6),
- \v_outleds_reg[0]\ => \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_3\,
- \v_outleds_reg[3]\ => \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_3\,
- \v_outleds_reg[7]\(1 downto 0) => v_outleds(7 downto 6)
- );
-\gen_spi.cmp_dac7716_spi\: entity work.system_design_fasec_hwtest_0_0_dac7716_spi_129
- port map (
- CO(0) => CO(0),
- D(0) => spi_sdo_i,
- Q(11 downto 0) => Q(11 downto 0),
- SR(0) => \^rst_i\,
- \axi_rdata_reg[31]\(31 downto 0) => \axi_rdata_reg[31]\(31 downto 0),
- \dac_ch_o_reg[0][0]_0\ => \gen_spi.cmp_dac7716_spi_n_1\,
- \dac_ch_o_reg[0][0]_1\ => \gen_spi.cmp_dac7716_spi_n_2\,
- \data_rw_o_reg[11][2]\(1 downto 0) => \data_rw_o_reg[11][7]\(1 downto 0),
- \data_rw_o_reg[16][11]\(11 downto 0) => \data_rw_o_reg[16][11]\(11 downto 0),
- \data_rw_o_reg[16][11]_0\(0) => \data_rw_o_reg[16][11]_0\(0),
- \data_rw_o_reg[17][11]\(11 downto 0) => \data_rw_o_reg[17][11]\(11 downto 0),
- \data_rw_o_reg[17][11]_0\(0) => \data_rw_o_reg[17][11]_0\(0),
- \data_rw_o_reg[18][11]\(11 downto 0) => \data_rw_o_reg[18][11]\(11 downto 0),
- \data_rw_o_reg[18][11]_0\(0) => \data_rw_o_reg[18][11]_0\(0),
- \data_rw_o_reg[19][11]\(11 downto 0) => \data_rw_o_reg[19][11]\(11 downto 0),
- \data_rw_o_reg[20][11]\(11 downto 0) => \data_rw_o_reg[20][11]\(11 downto 0),
- \data_rw_o_reg[20][11]_0\(0) => \data_rw_o_reg[20][11]_0\(0),
- \data_rw_o_reg[21][11]\(11 downto 0) => \data_rw_o_reg[21][11]\(11 downto 0),
- \data_rw_o_reg[21][11]_0\(0) => \data_rw_o_reg[21][11]_0\(0),
- \data_rw_o_reg[22][11]\(11 downto 0) => \data_rw_o_reg[22][11]\(11 downto 0),
- \data_rw_o_reg[22][11]_0\(0) => \data_rw_o_reg[22][11]_0\(0),
- \data_rw_o_reg[23][11]\(11 downto 0) => \data_rw_o_reg[23][11]\(11 downto 0),
- \data_rw_o_reg[23][11]_0\(0) => \data_rw_o_reg[23][11]_0\(0),
- \data_rw_o_reg[24][11]\(11 downto 0) => \data_rw_o_reg[24][11]\(11 downto 0),
- \data_rw_o_reg[25][11]\(11 downto 0) => \data_rw_o_reg[25][11]\(11 downto 0),
- \data_rw_o_reg[26][11]\(11 downto 0) => \data_rw_o_reg[26][11]\(11 downto 0),
- \data_rw_o_reg[27][11]\(11 downto 0) => \data_rw_o_reg[27][11]\(11 downto 0),
- \data_rw_o_reg[28][11]\(11 downto 0) => \data_rw_o_reg[28][11]\(11 downto 0),
- \data_rw_o_reg[29][11]\(11 downto 0) => \data_rw_o_reg[29][11]\(11 downto 0),
- \data_rw_o_reg[30][11]\(11 downto 0) => \data_rw_o_reg[30][11]\(11 downto 0),
- \data_rw_o_reg[31][11]\(11 downto 0) => \data_rw_o_reg[31][11]\(11 downto 0),
- \data_rw_o_reg[32][11]\(11 downto 0) => \data_rw_o_reg[32][11]\(11 downto 0),
- \data_rw_o_reg[33][11]\(11 downto 0) => \data_rw_o_reg[33][11]\(11 downto 0),
- \data_rw_o_reg[34][11]\(11 downto 0) => \data_rw_o_reg[34][11]\(11 downto 0),
- \data_rw_o_reg[35][11]\(11 downto 0) => \data_rw_o_reg[35][11]\(11 downto 0),
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- \s_counter_reg[2]\(0) => s_spi_sclk,
- s_spi_cs_n => s_spi_cs_n,
- s_spi_mosi => s_spi_mosi,
- s_start => s_start,
- s_start_reg_0 => s_start_i_1_n_0,
- \s_tx_data_reg[111]_0\(11 downto 0) => \s_tx_data_reg[111]\(11 downto 0),
- \s_tx_data_reg[15]_0\(11 downto 0) => \s_tx_data_reg[15]\(11 downto 0),
- \s_tx_data_reg[15]_1\(11 downto 0) => \s_tx_data_reg[15]_0\(11 downto 0),
- \s_tx_data_reg[39]_0\(11 downto 0) => \s_tx_data_reg[39]\(11 downto 0),
- \s_tx_data_reg[39]_1\(11 downto 0) => \s_tx_data_reg[39]_0\(11 downto 0),
- \s_tx_data_reg[39]_2\(11 downto 0) => \s_tx_data_reg[39]_1\(11 downto 0),
- \s_tx_data_reg[39]_3\(11 downto 0) => \s_tx_data_reg[39]_2\(11 downto 0)
- );
-\gen_spi.cmp_spi_cs_n_iobuf\: unisim.vcomponents.IOBUF
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => s_spi_cs_n,
- IO => FMC1_LA_N_b(1),
- O => \NLW_gen_spi.cmp_spi_cs_n_iobuf_O_UNCONNECTED\,
- T => '0'
- );
-\gen_spi.cmp_spi_miso_iobuf\: unisim.vcomponents.IOBUF
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => '0',
- IO => FMC1_LA_P_b(1),
- O => spi_sdo_i,
- T => '1'
- );
-\gen_spi.cmp_spi_mosi_iobuf\: unisim.vcomponents.IOBUF
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => s_spi_mosi,
- IO => FMC1_LA_N_b(0),
- O => \NLW_gen_spi.cmp_spi_mosi_iobuf_O_UNCONNECTED\,
- T => '0'
- );
-\gen_spi.cmp_spi_sclk_iobuf\: unisim.vcomponents.IOBUF
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => s_spi_sclk,
- IO => FMC1_LA_P_b(0),
- O => \NLW_gen_spi.cmp_spi_sclk_iobuf_O_UNCONNECTED\,
- T => '0'
- );
-intr_led_o_INST_0: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => fmc1_intr_led,
- I1 => fmc2_intr_led,
- O => intr_led_o
- );
-intr_led_o_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure_n_2\,
- Q => fmc1_intr_led,
- R => '0'
- );
-intr_o_INST_0: unisim.vcomponents.LUT2
- generic map(
- INIT => X"E"
- )
- port map (
- I0 => fmc1_intr,
- I1 => fmc2_intr,
- O => intr_o
- );
-intr_o_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => intr_o0,
- Q => fmc1_intr,
- R => '0'
- );
-s_buff2_i_1: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce\(1),
- I1 => \cmp_pulseSync/s_debounce\(0),
- I2 => \cmp_pulseSync/s_debounce\(4),
- I3 => \cmp_pulseSync/s_debounce\(3),
- I4 => \cmp_pulseSync/s_debounce\(2),
- I5 => \^s_datao_fmc1[0]\(0),
- O => s_buff2_i_1_n_0
- );
-\s_buff2_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_20\(1),
- I1 => \cmp_pulseSync/s_debounce_20\(0),
- I2 => \cmp_pulseSync/s_debounce_20\(4),
- I3 => \cmp_pulseSync/s_debounce_20\(3),
- I4 => \cmp_pulseSync/s_debounce_20\(2),
- I5 => \^s_datao_fmc1[0]\(1),
- O => \s_buff2_i_1__0_n_0\
- );
-\s_buff2_i_1__1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_22\(1),
- I1 => \cmp_pulseSync/s_debounce_22\(0),
- I2 => \cmp_pulseSync/s_debounce_22\(4),
- I3 => \cmp_pulseSync/s_debounce_22\(3),
- I4 => \cmp_pulseSync/s_debounce_22\(2),
- I5 => \^s_datao_fmc1[0]\(2),
- O => \s_buff2_i_1__1_n_0\
- );
-\s_buff2_i_1__10\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_2\(1),
- I1 => \cmp_pulseSync/s_debounce_2\(0),
- I2 => \cmp_pulseSync/s_debounce_2\(4),
- I3 => \cmp_pulseSync/s_debounce_2\(3),
- I4 => \cmp_pulseSync/s_debounce_2\(2),
- I5 => \^s_datao_fmc1[0]\(11),
- O => \s_buff2_i_1__10_n_0\
- );
-\s_buff2_i_1__11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_4\(1),
- I1 => \cmp_pulseSync/s_debounce_4\(0),
- I2 => \cmp_pulseSync/s_debounce_4\(4),
- I3 => \cmp_pulseSync/s_debounce_4\(3),
- I4 => \cmp_pulseSync/s_debounce_4\(2),
- I5 => \^s_datao_fmc1[0]\(12),
- O => \s_buff2_i_1__11_n_0\
- );
-\s_buff2_i_1__12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_6\(1),
- I1 => \cmp_pulseSync/s_debounce_6\(0),
- I2 => \cmp_pulseSync/s_debounce_6\(4),
- I3 => \cmp_pulseSync/s_debounce_6\(3),
- I4 => \cmp_pulseSync/s_debounce_6\(2),
- I5 => \^s_datao_fmc1[0]\(13),
- O => \s_buff2_i_1__12_n_0\
- );
-\s_buff2_i_1__13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_8\(1),
- I1 => \cmp_pulseSync/s_debounce_8\(0),
- I2 => \cmp_pulseSync/s_debounce_8\(4),
- I3 => \cmp_pulseSync/s_debounce_8\(3),
- I4 => \cmp_pulseSync/s_debounce_8\(2),
- I5 => \^s_datao_fmc1[0]\(14),
- O => \s_buff2_i_1__13_n_0\
- );
-\s_buff2_i_1__14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_10\(1),
- I1 => \cmp_pulseSync/s_debounce_10\(0),
- I2 => \cmp_pulseSync/s_debounce_10\(4),
- I3 => \cmp_pulseSync/s_debounce_10\(3),
- I4 => \cmp_pulseSync/s_debounce_10\(2),
- I5 => \^s_datao_fmc1[0]\(15),
- O => \s_buff2_i_1__14_n_0\
- );
-\s_buff2_i_1__15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_12\(1),
- I1 => \cmp_pulseSync/s_debounce_12\(0),
- I2 => \cmp_pulseSync/s_debounce_12\(4),
- I3 => \cmp_pulseSync/s_debounce_12\(3),
- I4 => \cmp_pulseSync/s_debounce_12\(2),
- I5 => \^s_datao_fmc1[0]\(16),
- O => \s_buff2_i_1__15_n_0\
- );
-\s_buff2_i_1__16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_14\(1),
- I1 => \cmp_pulseSync/s_debounce_14\(0),
- I2 => \cmp_pulseSync/s_debounce_14\(4),
- I3 => \cmp_pulseSync/s_debounce_14\(3),
- I4 => \cmp_pulseSync/s_debounce_14\(2),
- I5 => \^s_datao_fmc1[0]\(17),
- O => \s_buff2_i_1__16_n_0\
- );
-\s_buff2_i_1__17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_16\(1),
- I1 => \cmp_pulseSync/s_debounce_16\(0),
- I2 => \cmp_pulseSync/s_debounce_16\(4),
- I3 => \cmp_pulseSync/s_debounce_16\(3),
- I4 => \cmp_pulseSync/s_debounce_16\(2),
- I5 => \^s_datao_fmc1[0]\(18),
- O => \s_buff2_i_1__17_n_0\
- );
-\s_buff2_i_1__18\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_18\(1),
- I1 => \cmp_pulseSync/s_debounce_18\(0),
- I2 => \cmp_pulseSync/s_debounce_18\(4),
- I3 => \cmp_pulseSync/s_debounce_18\(3),
- I4 => \cmp_pulseSync/s_debounce_18\(2),
- I5 => \^s_datao_fmc1[0]\(19),
- O => \s_buff2_i_1__18_n_0\
- );
-\s_buff2_i_1__19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_38\(1),
- I1 => \cmp_pulseSync/s_debounce_38\(0),
- I2 => \cmp_pulseSync/s_debounce_38\(4),
- I3 => \cmp_pulseSync/s_debounce_38\(3),
- I4 => \cmp_pulseSync/s_debounce_38\(2),
- I5 => \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__19_n_0\
- );
-\s_buff2_i_1__2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_24\(1),
- I1 => \cmp_pulseSync/s_debounce_24\(0),
- I2 => \cmp_pulseSync/s_debounce_24\(4),
- I3 => \cmp_pulseSync/s_debounce_24\(3),
- I4 => \cmp_pulseSync/s_debounce_24\(2),
- I5 => \^s_datao_fmc1[0]\(3),
- O => \s_buff2_i_1__2_n_0\
- );
-\s_buff2_i_1__20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_39\(1),
- I1 => \cmp_pulseSync/s_debounce_39\(0),
- I2 => \cmp_pulseSync/s_debounce_39\(4),
- I3 => \cmp_pulseSync/s_debounce_39\(3),
- I4 => \cmp_pulseSync/s_debounce_39\(2),
- I5 => \fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__20_n_0\
- );
-\s_buff2_i_1__21\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_40\(1),
- I1 => \cmp_pulseSync/s_debounce_40\(0),
- I2 => \cmp_pulseSync/s_debounce_40\(4),
- I3 => \cmp_pulseSync/s_debounce_40\(3),
- I4 => \cmp_pulseSync/s_debounce_40\(2),
- I5 => \fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__21_n_0\
- );
-\s_buff2_i_1__22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_41\(1),
- I1 => \cmp_pulseSync/s_debounce_41\(0),
- I2 => \cmp_pulseSync/s_debounce_41\(4),
- I3 => \cmp_pulseSync/s_debounce_41\(3),
- I4 => \cmp_pulseSync/s_debounce_41\(2),
- I5 => \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__22_n_0\
- );
-\s_buff2_i_1__23\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_42\(1),
- I1 => \cmp_pulseSync/s_debounce_42\(0),
- I2 => \cmp_pulseSync/s_debounce_42\(4),
- I3 => \cmp_pulseSync/s_debounce_42\(3),
- I4 => \cmp_pulseSync/s_debounce_42\(2),
- I5 => \fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__23_n_0\
- );
-\s_buff2_i_1__24\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_43\(1),
- I1 => \cmp_pulseSync/s_debounce_43\(0),
- I2 => \cmp_pulseSync/s_debounce_43\(4),
- I3 => \cmp_pulseSync/s_debounce_43\(3),
- I4 => \cmp_pulseSync/s_debounce_43\(2),
- I5 => \fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__24_n_0\
- );
-\s_buff2_i_1__25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_44\(1),
- I1 => \cmp_pulseSync/s_debounce_44\(0),
- I2 => \cmp_pulseSync/s_debounce_44\(4),
- I3 => \cmp_pulseSync/s_debounce_44\(3),
- I4 => \cmp_pulseSync/s_debounce_44\(2),
- I5 => \fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__25_n_0\
- );
-\s_buff2_i_1__26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_45\(1),
- I1 => \cmp_pulseSync/s_debounce_45\(0),
- I2 => \cmp_pulseSync/s_debounce_45\(4),
- I3 => \cmp_pulseSync/s_debounce_45\(3),
- I4 => \cmp_pulseSync/s_debounce_45\(2),
- I5 => \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__26_n_0\
- );
-\s_buff2_i_1__3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_26\(1),
- I1 => \cmp_pulseSync/s_debounce_26\(0),
- I2 => \cmp_pulseSync/s_debounce_26\(4),
- I3 => \cmp_pulseSync/s_debounce_26\(3),
- I4 => \cmp_pulseSync/s_debounce_26\(2),
- I5 => \^s_datao_fmc1[0]\(4),
- O => \s_buff2_i_1__3_n_0\
- );
-\s_buff2_i_1__4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_28\(1),
- I1 => \cmp_pulseSync/s_debounce_28\(0),
- I2 => \cmp_pulseSync/s_debounce_28\(4),
- I3 => \cmp_pulseSync/s_debounce_28\(3),
- I4 => \cmp_pulseSync/s_debounce_28\(2),
- I5 => \^s_datao_fmc1[0]\(5),
- O => \s_buff2_i_1__4_n_0\
- );
-\s_buff2_i_1__5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_30\(1),
- I1 => \cmp_pulseSync/s_debounce_30\(0),
- I2 => \cmp_pulseSync/s_debounce_30\(4),
- I3 => \cmp_pulseSync/s_debounce_30\(3),
- I4 => \cmp_pulseSync/s_debounce_30\(2),
- I5 => \^s_datao_fmc1[0]\(6),
- O => \s_buff2_i_1__5_n_0\
- );
-\s_buff2_i_1__6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_32\(1),
- I1 => \cmp_pulseSync/s_debounce_32\(0),
- I2 => \cmp_pulseSync/s_debounce_32\(4),
- I3 => \cmp_pulseSync/s_debounce_32\(3),
- I4 => \cmp_pulseSync/s_debounce_32\(2),
- I5 => \^s_datao_fmc1[0]\(7),
- O => \s_buff2_i_1__6_n_0\
- );
-\s_buff2_i_1__7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_34\(1),
- I1 => \cmp_pulseSync/s_debounce_34\(0),
- I2 => \cmp_pulseSync/s_debounce_34\(4),
- I3 => \cmp_pulseSync/s_debounce_34\(3),
- I4 => \cmp_pulseSync/s_debounce_34\(2),
- I5 => \^s_datao_fmc1[0]\(8),
- O => \s_buff2_i_1__7_n_0\
- );
-\s_buff2_i_1__8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_36\(1),
- I1 => \cmp_pulseSync/s_debounce_36\(0),
- I2 => \cmp_pulseSync/s_debounce_36\(4),
- I3 => \cmp_pulseSync/s_debounce_36\(3),
- I4 => \cmp_pulseSync/s_debounce_36\(2),
- I5 => \^s_datao_fmc1[0]\(9),
- O => \s_buff2_i_1__8_n_0\
- );
-\s_buff2_i_1__9\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_0\(1),
- I1 => \cmp_pulseSync/s_debounce_0\(0),
- I2 => \cmp_pulseSync/s_debounce_0\(4),
- I3 => \cmp_pulseSync/s_debounce_0\(3),
- I4 => \cmp_pulseSync/s_debounce_0\(2),
- I5 => \^s_datao_fmc1[0]\(10),
- O => \s_buff2_i_1__9_n_0\
- );
-\s_diffouts_o_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_dout(4),
- Q => s_diffouts_o(4),
- R => '0'
- );
-\s_diffouts_o_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_dout(5),
- Q => s_diffouts_o(5),
- R => '0'
- );
-\s_diffouts_o_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_dout(6),
- Q => s_diffouts_o(6),
- R => '0'
- );
-\s_diffouts_o_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_dout(7),
- Q => s_diffouts_o(7),
- R => '0'
- );
-s_start_i_1: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => s_start,
- I1 => \gen_spi.cmp_dac7716_spi_n_2\,
- I2 => \gen_spi.cmp_dac7716_spi_n_1\,
- O => s_start_i_1_n_0
- );
-\v_cmp_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(0),
- Q => v_cmp(0),
- R => '0'
- );
-\v_cmp_reg[10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(10),
- Q => v_cmp(10),
- R => '0'
- );
-\v_cmp_reg[11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(11),
- Q => v_cmp(11),
- R => '0'
- );
-\v_cmp_reg[12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(12),
- Q => v_cmp(12),
- R => '0'
- );
-\v_cmp_reg[13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(13),
- Q => v_cmp(13),
- R => '0'
- );
-\v_cmp_reg[14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(14),
- Q => v_cmp(14),
- R => '0'
- );
-\v_cmp_reg[15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(15),
- Q => v_cmp(15),
- R => '0'
- );
-\v_cmp_reg[16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(16),
- Q => v_cmp(16),
- R => '0'
- );
-\v_cmp_reg[17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(17),
- Q => v_cmp(17),
- R => '0'
- );
-\v_cmp_reg[18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(18),
- Q => v_cmp(18),
- R => '0'
- );
-\v_cmp_reg[19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(19),
- Q => v_cmp(19),
- R => '0'
- );
-\v_cmp_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(1),
- Q => v_cmp(1),
- R => '0'
- );
-\v_cmp_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(2),
- Q => v_cmp(2),
- R => '0'
- );
-\v_cmp_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(3),
- Q => v_cmp(3),
- R => '0'
- );
-\v_cmp_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(4),
- Q => v_cmp(4),
- R => '0'
- );
-\v_cmp_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(5),
- Q => v_cmp(5),
- R => '0'
- );
-\v_cmp_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(6),
- Q => v_cmp(6),
- R => '0'
- );
-\v_cmp_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(7),
- Q => v_cmp(7),
- R => '0'
- );
-\v_cmp_reg[8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(8),
- Q => v_cmp(8),
- R => '0'
- );
-\v_cmp_reg[9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc1[0]\(9),
- Q => v_cmp(9),
- R => '0'
- );
-\v_cmpled_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[4]\(0),
- Q => v_cmpled(0),
- R => '0'
- );
-\v_cmpled_reg[10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(2),
- Q => v_cmpled(10),
- R => '0'
- );
-\v_cmpled_reg[11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(3),
- Q => v_cmpled(11),
- R => '0'
- );
-\v_cmpled_reg[12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(4),
- Q => v_cmpled(12),
- R => '0'
- );
-\v_cmpled_reg[13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(5),
- Q => v_cmpled(13),
- R => '0'
- );
-\v_cmpled_reg[14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(6),
- Q => v_cmpled(14),
- R => '0'
- );
-\v_cmpled_reg[15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(7),
- Q => v_cmpled(15),
- R => '0'
- );
-\v_cmpled_reg[16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(8),
- Q => v_cmpled(16),
- R => '0'
- );
-\v_cmpled_reg[17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(9),
- Q => v_cmpled(17),
- R => '0'
- );
-\v_cmpled_reg[18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(10),
- Q => v_cmpled(18),
- R => '0'
- );
-\v_cmpled_reg[19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(11),
- Q => v_cmpled(19),
- R => '0'
- );
-\v_cmpled_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[4]\(1),
- Q => v_cmpled(1),
- R => '0'
- );
-\v_cmpled_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[4]\(2),
- Q => v_cmpled(2),
- R => '0'
- );
-\v_cmpled_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[4]\(3),
- Q => v_cmpled(3),
- R => '0'
- );
-\v_cmpled_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[4]\(4),
- Q => v_cmpled(4),
- R => '0'
- );
-\v_cmpled_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[4]\(5),
- Q => v_cmpled(5),
- R => '0'
- );
-\v_cmpled_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[4]\(6),
- Q => v_cmpled(6),
- R => '0'
- );
-\v_cmpled_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[4]\(7),
- Q => v_cmpled(7),
- R => '0'
- );
-\v_cmpled_reg[8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(0),
- Q => v_cmpled(8),
- R => '0'
- );
-\v_cmpled_reg[9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(1),
- Q => v_cmpled(9),
- R => '0'
- );
-\v_dout_reg[4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[10][4]\,
- Q => v_dout(4),
- S => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2\
- );
-\v_dout_reg[5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[10][5]\,
- Q => v_dout(5),
- S => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2\
- );
-\v_dout_reg[6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[10][6]\,
- Q => v_dout(6),
- S => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2\
- );
-\v_dout_reg[7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[10][7]\,
- Q => v_dout(7),
- S => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2\
- );
-\v_fbd_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \FMC1_LA_N_b[32]\(21),
- Q => v_fbd(0),
- R => '0'
- );
-\v_fbd_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \FMC1_LA_P_b[32]\(21),
- Q => v_fbd(1),
- R => '0'
- );
-\v_fbd_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \FMC1_LA_N_b[32]\(20),
- Q => v_fbd(2),
- R => '0'
- );
-\v_fbd_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \FMC1_LA_P_b[32]\(20),
- Q => v_fbd(3),
- R => '0'
- );
-\v_outleds_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[5]\(0),
- Q => v_outleds(0),
- R => '0'
- );
-\v_outleds_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[5]\(1),
- Q => v_outleds(1),
- R => '0'
- );
-\v_outleds_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[5]\(2),
- Q => v_outleds(2),
- R => '0'
- );
-\v_outleds_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[5]\(3),
- Q => v_outleds(3),
- R => '0'
- );
-\v_outleds_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[5]\(4),
- Q => v_outleds(4),
- R => '0'
- );
-\v_outleds_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[5]\(5),
- Q => v_outleds(5),
- R => '0'
- );
-\v_outleds_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[5]\(6),
- Q => v_outleds(6),
- R => '0'
- );
-\v_outleds_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc1[5]\(7),
- Q => v_outleds(7),
- R => '0'
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_general_fmc_0 is
- port (
- \FMC2_LA_P_b[27]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
- \FMC2_LA_N_b[27]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
- fmc2_intr : out STD_LOGIC;
- fmc2_intr_led : out STD_LOGIC;
- Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[111]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[15]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[15]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]_1\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \s_tx_data_reg[39]_2\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \axi_rdata_reg[0]\ : out STD_LOGIC;
- s_count_reg : out STD_LOGIC_VECTOR ( 11 downto 0 );
- \axi_rdata_reg[0]_0\ : out STD_LOGIC;
- \axi_rdata_reg[0]_1\ : out STD_LOGIC;
- \axi_rdata_reg[1]\ : out STD_LOGIC;
- \axi_rdata_reg[1]_0\ : out STD_LOGIC;
- \axi_rdata_reg[1]_1\ : out STD_LOGIC;
- \axi_rdata_reg[2]\ : out STD_LOGIC;
- \axi_rdata_reg[2]_0\ : out STD_LOGIC;
- \axi_rdata_reg[2]_1\ : out STD_LOGIC;
- \axi_rdata_reg[3]\ : out STD_LOGIC;
- \axi_rdata_reg[3]_0\ : out STD_LOGIC;
- \axi_rdata_reg[3]_1\ : out STD_LOGIC;
- \axi_rdata_reg[4]\ : out STD_LOGIC;
- \axi_rdata_reg[4]_0\ : out STD_LOGIC;
- \axi_rdata_reg[4]_1\ : out STD_LOGIC;
- \axi_rdata_reg[5]\ : out STD_LOGIC;
- \axi_rdata_reg[5]_0\ : out STD_LOGIC;
- \axi_rdata_reg[5]_1\ : out STD_LOGIC;
- \axi_rdata_reg[6]\ : out STD_LOGIC;
- \axi_rdata_reg[6]_0\ : out STD_LOGIC;
- \axi_rdata_reg[6]_1\ : out STD_LOGIC;
- \axi_rdata_reg[7]\ : out STD_LOGIC;
- \axi_rdata_reg[7]_0\ : out STD_LOGIC;
- \axi_rdata_reg[7]_1\ : out STD_LOGIC;
- \axi_rdata_reg[8]\ : out STD_LOGIC;
- \axi_rdata_reg[8]_0\ : out STD_LOGIC;
- \axi_rdata_reg[9]\ : out STD_LOGIC;
- \axi_rdata_reg[9]_0\ : out STD_LOGIC;
- \axi_rdata_reg[10]\ : out STD_LOGIC;
- \axi_rdata_reg[10]_0\ : out STD_LOGIC;
- \axi_rdata_reg[11]\ : out STD_LOGIC;
- \axi_rdata_reg[11]_0\ : out STD_LOGIC;
- \axi_rdata_reg[12]\ : out STD_LOGIC;
- \axi_rdata_reg[12]_0\ : out STD_LOGIC;
- \axi_rdata_reg[13]\ : out STD_LOGIC;
- \axi_rdata_reg[13]_0\ : out STD_LOGIC;
- \axi_rdata_reg[14]\ : out STD_LOGIC;
- \axi_rdata_reg[14]_0\ : out STD_LOGIC;
- \axi_rdata_reg[15]\ : out STD_LOGIC;
- \axi_rdata_reg[15]_0\ : out STD_LOGIC;
- \axi_rdata_reg[16]\ : out STD_LOGIC;
- \axi_rdata_reg[16]_0\ : out STD_LOGIC;
- \axi_rdata_reg[17]\ : out STD_LOGIC;
- \axi_rdata_reg[17]_0\ : out STD_LOGIC;
- \axi_rdata_reg[18]\ : out STD_LOGIC;
- \axi_rdata_reg[18]_0\ : out STD_LOGIC;
- \axi_rdata_reg[19]\ : out STD_LOGIC;
- \axi_rdata_reg[19]_0\ : out STD_LOGIC;
- \axi_rdata_reg[20]\ : out STD_LOGIC;
- \axi_rdata_reg[20]_0\ : out STD_LOGIC;
- \axi_rdata_reg[20]_1\ : out STD_LOGIC;
- \axi_rdata_reg[21]\ : out STD_LOGIC;
- \axi_rdata_reg[21]_0\ : out STD_LOGIC;
- \axi_rdata_reg[21]_1\ : out STD_LOGIC;
- \axi_rdata_reg[22]\ : out STD_LOGIC;
- \axi_rdata_reg[22]_0\ : out STD_LOGIC;
- \axi_rdata_reg[22]_1\ : out STD_LOGIC;
- \axi_rdata_reg[23]\ : out STD_LOGIC;
- \axi_rdata_reg[23]_0\ : out STD_LOGIC;
- \axi_rdata_reg[23]_1\ : out STD_LOGIC;
- \s_datao_fmc2[0]\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
- \axi_rdata_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
- \axi_rdata_reg[3]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
- FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 1 downto 0 );
- FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 1 downto 0 );
- \FMC2_LA_P_b[32]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
- \FMC2_LA_N_b[32]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
- D : in STD_LOGIC_VECTOR ( 3 downto 0 );
- rst_i : in STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- \data_rw_o_reg[79][7]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \axi_araddr_reg[3]_rep__3\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__3\ : in STD_LOGIC;
- \axi_araddr_reg[5]_rep\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep__1\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep__0\ : in STD_LOGIC;
- \axi_araddr_reg[3]_rep__2\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__2\ : in STD_LOGIC;
- \axi_araddr_reg[3]_rep__1\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__1\ : in STD_LOGIC;
- \axi_araddr_reg[4]_rep\ : in STD_LOGIC;
- \axi_araddr_reg[5]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
- \axi_araddr_reg[3]_rep__0\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep__0\ : in STD_LOGIC;
- \axi_araddr_reg[3]_rep\ : in STD_LOGIC;
- \axi_araddr_reg[2]_rep\ : in STD_LOGIC;
- \data_rw_o_reg[87][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[87][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[86][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[86][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[85][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[85][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[84][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[84][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[88][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[88][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[89][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[89][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[90][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[90][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[91][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[91][11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
- \data_rw_o_reg[92][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[93][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[94][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[95][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[96][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[97][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[98][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[99][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[100][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[101][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[102][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[103][11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
- \data_rw_o_reg[78][7]\ : in STD_LOGIC;
- \data_rw_o_reg[78][6]\ : in STD_LOGIC;
- \data_rw_o_reg[78][5]\ : in STD_LOGIC;
- \data_rw_o_reg[78][4]\ : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_general_fmc_0 : entity is "general_fmc";
-end system_design_fasec_hwtest_0_0_general_fmc_0;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_general_fmc_0 is
- signal \axi_rdata[0]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[0]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[10]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[11]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[12]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[13]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[14]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[15]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[16]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[17]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[18]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[19]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[1]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata[20]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata[21]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata[22]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_11_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_12_n_0\ : STD_LOGIC;
- signal \axi_rdata[23]_i_13_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[2]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[3]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[4]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[5]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[6]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[7]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[8]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_25_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_26_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_27_n_0\ : STD_LOGIC;
- signal \axi_rdata[9]_i_28_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[0]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[0]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[10]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[10]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[11]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[11]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[12]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[12]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[13]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[13]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[14]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[14]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[15]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[15]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[16]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[16]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[17]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[17]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[18]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[18]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[19]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[19]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[1]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[1]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[2]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[2]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[3]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[3]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[4]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[4]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[5]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[5]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[6]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[6]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[7]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[7]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[8]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[8]_i_9_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[9]_i_10_n_0\ : STD_LOGIC;
- signal \axi_rdata_reg[9]_i_9_n_0\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_1\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_11\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_13\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_15\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_17\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_19\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_21\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_23\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_25\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_27\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_29\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_3\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_31\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_33\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_35\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_37\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_5\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_7\ : STD_LOGIC;
- signal \cmp_lengthCounter/RSTP_9\ : STD_LOGIC;
- signal \cmp_pulseSync/s_debounce\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_10\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_12\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_14\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_16\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_18\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_2\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_20\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_22\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_24\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_26\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_28\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_30\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_32\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_34\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_36\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_38\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_39\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_4\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_40\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_41\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_42\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_43\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_44\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_45\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_6\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \cmp_pulseSync/s_debounce_8\ : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2\ : STD_LOGIC;
- signal \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_4\ : STD_LOGIC;
- signal \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_2\ : STD_LOGIC;
- signal \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_2\ : STD_LOGIC;
- signal \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_2\ : STD_LOGIC;
- signal \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_2\ : STD_LOGIC;
- signal \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_2\ : STD_LOGIC;
- signal \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure_n_2\ : STD_LOGIC;
- signal \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_3\ : STD_LOGIC;
- signal \fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_1\ : STD_LOGIC;
- signal \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_3\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi_n_1\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi_n_2\ : STD_LOGIC;
- signal intr_o0 : STD_LOGIC;
- signal \s_buff2_i_1__0_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__10_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__11_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__12_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__13_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__14_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__15_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__16_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__17_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__18_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__19_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__1_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__20_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__21_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__22_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__23_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__24_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__25_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__26_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__2_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__3_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__4_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__5_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__6_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__7_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__8_n_0\ : STD_LOGIC;
- signal \s_buff2_i_1__9_n_0\ : STD_LOGIC;
- signal s_buff2_i_1_n_0 : STD_LOGIC;
- signal \s_cmp_lengths[0]_0\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[10]_10\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[11]_11\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[12]_12\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[13]_13\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[14]_14\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[15]_15\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[16]_16\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[17]_17\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[18]_18\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[19]_19\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[1]_1\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[2]_2\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[3]_3\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[4]_4\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[5]_5\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[6]_6\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[7]_7\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[8]_8\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_cmp_lengths[9]_9\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal s_comparators_i_0 : STD_LOGIC;
- signal s_comparators_i_1 : STD_LOGIC;
- signal s_comparators_i_10 : STD_LOGIC;
- signal s_comparators_i_11 : STD_LOGIC;
- signal s_comparators_i_12 : STD_LOGIC;
- signal s_comparators_i_13 : STD_LOGIC;
- signal s_comparators_i_14 : STD_LOGIC;
- signal s_comparators_i_15 : STD_LOGIC;
- signal s_comparators_i_16 : STD_LOGIC;
- signal s_comparators_i_17 : STD_LOGIC;
- signal s_comparators_i_18 : STD_LOGIC;
- signal s_comparators_i_19 : STD_LOGIC;
- signal s_comparators_i_2 : STD_LOGIC;
- signal s_comparators_i_3 : STD_LOGIC;
- signal s_comparators_i_4 : STD_LOGIC;
- signal s_comparators_i_5 : STD_LOGIC;
- signal s_comparators_i_6 : STD_LOGIC;
- signal s_comparators_i_7 : STD_LOGIC;
- signal s_comparators_i_8 : STD_LOGIC;
- signal s_comparators_i_9 : STD_LOGIC;
- signal \^s_count_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^s_datao_fmc2[0]\ : STD_LOGIC_VECTOR ( 19 downto 0 );
- signal \s_datao_fmc2[48]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[49]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[4]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal \s_datao_fmc2[50]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[51]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[52]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[53]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[54]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[55]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[56]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[57]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[58]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[59]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[5]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal \s_datao_fmc2[60]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[61]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[62]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[63]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[64]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[65]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[66]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[67]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
- signal \s_datao_fmc2[6]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal s_diffouts_o : STD_LOGIC_VECTOR ( 7 downto 4 );
- signal s_spi_cs_n : STD_LOGIC;
- signal s_spi_mosi : STD_LOGIC;
- signal s_spi_sclk : STD_LOGIC;
- signal s_start : STD_LOGIC;
- signal s_start_i_1_n_0 : STD_LOGIC;
- signal spi_sdo_i : STD_LOGIC;
- signal v_cmp : STD_LOGIC_VECTOR ( 19 downto 0 );
- signal v_cmpled : STD_LOGIC_VECTOR ( 19 downto 0 );
- signal v_dout : STD_LOGIC_VECTOR ( 7 downto 4 );
- signal v_fbd : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal v_outleds : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal \NLW_gen_spi.cmp_spi_cs_n_iobuf_O_UNCONNECTED\ : STD_LOGIC;
- signal \NLW_gen_spi.cmp_spi_mosi_iobuf_O_UNCONNECTED\ : STD_LOGIC;
- signal \NLW_gen_spi.cmp_spi_sclk_iobuf_O_UNCONNECTED\ : STD_LOGIC;
- attribute CAPACITANCE : string;
- attribute CAPACITANCE of \fmc_03287_channels[0].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE : string;
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[0].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE : string;
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[0].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type : string;
- attribute box_type of \fmc_03287_channels[0].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[10].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[10].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[10].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[10].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[11].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[11].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[11].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[11].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[12].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[12].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[12].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[12].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[13].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[13].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[13].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[13].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[14].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[14].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[14].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[14].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[15].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[15].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[15].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[15].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[16].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[16].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[16].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[16].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[17].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[17].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[17].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[17].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[18].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[18].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[18].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[18].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[19].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[19].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[19].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[19].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[1].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[1].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[1].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[1].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[2].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[2].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[2].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[2].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[3].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[3].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[3].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[3].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[4].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[4].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[4].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[4].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[5].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[5].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[5].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[5].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[6].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[6].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[6].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[6].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[7].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[7].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[7].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[7].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[8].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[8].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[8].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[8].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_channels[9].gen_chs.cmp_IBUFDS_fmc\ : label is "DONT_CARE";
- attribute IBUF_DELAY_VALUE of \fmc_03287_channels[9].gen_chs.cmp_IBUFDS_fmc\ : label is "0";
- attribute IFD_DELAY_VALUE of \fmc_03287_channels[9].gen_chs.cmp_IBUFDS_fmc\ : label is "AUTO";
- attribute box_type of \fmc_03287_channels[9].gen_chs.cmp_IBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[0].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM : string;
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[0].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[0].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[1].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[1].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[1].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[2].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[2].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[2].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[3].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[3].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[3].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[4].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[4].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[4].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[5].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[5].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[5].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[6].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[6].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[6].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute CAPACITANCE of \fmc_03287_obufds[7].gen_outs.cmp_OBUFDS_fmc\ : label is "DONT_CARE";
- attribute XILINX_LEGACY_PRIM of \fmc_03287_obufds[7].gen_outs.cmp_OBUFDS_fmc\ : label is "OBUFDS";
- attribute box_type of \fmc_03287_obufds[7].gen_outs.cmp_OBUFDS_fmc\ : label is "PRIMITIVE";
- attribute box_type of \gen_spi.cmp_spi_cs_n_iobuf\ : label is "PRIMITIVE";
- attribute box_type of \gen_spi.cmp_spi_miso_iobuf\ : label is "PRIMITIVE";
- attribute box_type of \gen_spi.cmp_spi_mosi_iobuf\ : label is "PRIMITIVE";
- attribute box_type of \gen_spi.cmp_spi_sclk_iobuf\ : label is "PRIMITIVE";
-begin
- s_count_reg(11 downto 0) <= \^s_count_reg\(11 downto 0);
- \s_datao_fmc2[0]\(19 downto 0) <= \^s_datao_fmc2[0]\(19 downto 0);
-\axi_rdata[0]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(0),
- I1 => \s_datao_fmc2[50]\(0),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[49]\(0),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[48]\(0),
- O => \axi_rdata_reg[0]_0\
- );
-\axi_rdata[0]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(0),
- I1 => \s_datao_fmc2[54]\(0),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[53]\(0),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[52]\(0),
- O => \axi_rdata[0]_i_25_n_0\
- );
-\axi_rdata[0]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(0),
- I1 => \s_datao_fmc2[58]\(0),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[57]\(0),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[56]\(0),
- O => \axi_rdata[0]_i_26_n_0\
- );
-\axi_rdata[0]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(0),
- I1 => \s_datao_fmc2[62]\(0),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[61]\(0),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[60]\(0),
- O => \axi_rdata[0]_i_27_n_0\
- );
-\axi_rdata[0]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(0),
- I1 => \s_datao_fmc2[66]\(0),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[65]\(0),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[64]\(0),
- O => \axi_rdata[0]_i_28_n_0\
- );
-\axi_rdata[10]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(10),
- I1 => \s_datao_fmc2[50]\(10),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[49]\(10),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[48]\(10),
- O => \axi_rdata_reg[10]\
- );
-\axi_rdata[10]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(10),
- I1 => \s_datao_fmc2[54]\(10),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[53]\(10),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[52]\(10),
- O => \axi_rdata[10]_i_25_n_0\
- );
-\axi_rdata[10]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(10),
- I1 => \s_datao_fmc2[58]\(10),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[57]\(10),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[56]\(10),
- O => \axi_rdata[10]_i_26_n_0\
- );
-\axi_rdata[10]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(10),
- I1 => \s_datao_fmc2[62]\(10),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[61]\(10),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[60]\(10),
- O => \axi_rdata[10]_i_27_n_0\
- );
-\axi_rdata[10]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(10),
- I1 => \s_datao_fmc2[66]\(10),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[65]\(10),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[64]\(10),
- O => \axi_rdata[10]_i_28_n_0\
- );
-\axi_rdata[11]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(11),
- I1 => \s_datao_fmc2[50]\(11),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[49]\(11),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[48]\(11),
- O => \axi_rdata_reg[11]\
- );
-\axi_rdata[11]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(11),
- I1 => \s_datao_fmc2[54]\(11),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[53]\(11),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[52]\(11),
- O => \axi_rdata[11]_i_25_n_0\
- );
-\axi_rdata[11]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(11),
- I1 => \s_datao_fmc2[58]\(11),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[57]\(11),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[56]\(11),
- O => \axi_rdata[11]_i_26_n_0\
- );
-\axi_rdata[11]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(11),
- I1 => \s_datao_fmc2[62]\(11),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[61]\(11),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[60]\(11),
- O => \axi_rdata[11]_i_27_n_0\
- );
-\axi_rdata[11]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(11),
- I1 => \s_datao_fmc2[66]\(11),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[65]\(11),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[64]\(11),
- O => \axi_rdata[11]_i_28_n_0\
- );
-\axi_rdata[12]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(12),
- I1 => \s_datao_fmc2[50]\(12),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[49]\(12),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[48]\(12),
- O => \axi_rdata_reg[12]\
- );
-\axi_rdata[12]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(12),
- I1 => \s_datao_fmc2[54]\(12),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[53]\(12),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[52]\(12),
- O => \axi_rdata[12]_i_25_n_0\
- );
-\axi_rdata[12]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(12),
- I1 => \s_datao_fmc2[58]\(12),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[57]\(12),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[56]\(12),
- O => \axi_rdata[12]_i_26_n_0\
- );
-\axi_rdata[12]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(12),
- I1 => \s_datao_fmc2[62]\(12),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[61]\(12),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[60]\(12),
- O => \axi_rdata[12]_i_27_n_0\
- );
-\axi_rdata[12]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(12),
- I1 => \s_datao_fmc2[66]\(12),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[65]\(12),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[64]\(12),
- O => \axi_rdata[12]_i_28_n_0\
- );
-\axi_rdata[13]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(13),
- I1 => \s_datao_fmc2[50]\(13),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[49]\(13),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[48]\(13),
- O => \axi_rdata_reg[13]\
- );
-\axi_rdata[13]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(13),
- I1 => \s_datao_fmc2[54]\(13),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[53]\(13),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[52]\(13),
- O => \axi_rdata[13]_i_25_n_0\
- );
-\axi_rdata[13]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(13),
- I1 => \s_datao_fmc2[58]\(13),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[57]\(13),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[56]\(13),
- O => \axi_rdata[13]_i_26_n_0\
- );
-\axi_rdata[13]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(13),
- I1 => \s_datao_fmc2[62]\(13),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[61]\(13),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[60]\(13),
- O => \axi_rdata[13]_i_27_n_0\
- );
-\axi_rdata[13]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(13),
- I1 => \s_datao_fmc2[66]\(13),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[65]\(13),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[64]\(13),
- O => \axi_rdata[13]_i_28_n_0\
- );
-\axi_rdata[14]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(14),
- I1 => \s_datao_fmc2[50]\(14),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[49]\(14),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[48]\(14),
- O => \axi_rdata_reg[14]\
- );
-\axi_rdata[14]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(14),
- I1 => \s_datao_fmc2[54]\(14),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[53]\(14),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[52]\(14),
- O => \axi_rdata[14]_i_25_n_0\
- );
-\axi_rdata[14]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(14),
- I1 => \s_datao_fmc2[58]\(14),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[57]\(14),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[56]\(14),
- O => \axi_rdata[14]_i_26_n_0\
- );
-\axi_rdata[14]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(14),
- I1 => \s_datao_fmc2[62]\(14),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[61]\(14),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[60]\(14),
- O => \axi_rdata[14]_i_27_n_0\
- );
-\axi_rdata[14]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(14),
- I1 => \s_datao_fmc2[66]\(14),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[65]\(14),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[64]\(14),
- O => \axi_rdata[14]_i_28_n_0\
- );
-\axi_rdata[15]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(15),
- I1 => \s_datao_fmc2[50]\(15),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[49]\(15),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[48]\(15),
- O => \axi_rdata_reg[15]\
- );
-\axi_rdata[15]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(15),
- I1 => \s_datao_fmc2[54]\(15),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[53]\(15),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[52]\(15),
- O => \axi_rdata[15]_i_25_n_0\
- );
-\axi_rdata[15]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(15),
- I1 => \s_datao_fmc2[58]\(15),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[57]\(15),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[56]\(15),
- O => \axi_rdata[15]_i_26_n_0\
- );
-\axi_rdata[15]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(15),
- I1 => \s_datao_fmc2[62]\(15),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[61]\(15),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[60]\(15),
- O => \axi_rdata[15]_i_27_n_0\
- );
-\axi_rdata[15]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(15),
- I1 => \s_datao_fmc2[66]\(15),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[65]\(15),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[64]\(15),
- O => \axi_rdata[15]_i_28_n_0\
- );
-\axi_rdata[16]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(16),
- I1 => \s_datao_fmc2[50]\(16),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[49]\(16),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[48]\(16),
- O => \axi_rdata_reg[16]\
- );
-\axi_rdata[16]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(16),
- I1 => \s_datao_fmc2[54]\(16),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[53]\(16),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[52]\(16),
- O => \axi_rdata[16]_i_25_n_0\
- );
-\axi_rdata[16]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(16),
- I1 => \s_datao_fmc2[58]\(16),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[57]\(16),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[56]\(16),
- O => \axi_rdata[16]_i_26_n_0\
- );
-\axi_rdata[16]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(16),
- I1 => \s_datao_fmc2[62]\(16),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[61]\(16),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[60]\(16),
- O => \axi_rdata[16]_i_27_n_0\
- );
-\axi_rdata[16]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(16),
- I1 => \s_datao_fmc2[66]\(16),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[65]\(16),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[64]\(16),
- O => \axi_rdata[16]_i_28_n_0\
- );
-\axi_rdata[17]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(17),
- I1 => \s_datao_fmc2[50]\(17),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[49]\(17),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[48]\(17),
- O => \axi_rdata_reg[17]\
- );
-\axi_rdata[17]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(17),
- I1 => \s_datao_fmc2[54]\(17),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[53]\(17),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[52]\(17),
- O => \axi_rdata[17]_i_25_n_0\
- );
-\axi_rdata[17]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(17),
- I1 => \s_datao_fmc2[58]\(17),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[57]\(17),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[56]\(17),
- O => \axi_rdata[17]_i_26_n_0\
- );
-\axi_rdata[17]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(17),
- I1 => \s_datao_fmc2[62]\(17),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[61]\(17),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[60]\(17),
- O => \axi_rdata[17]_i_27_n_0\
- );
-\axi_rdata[17]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(17),
- I1 => \s_datao_fmc2[66]\(17),
- I2 => \axi_araddr_reg[3]_rep__0\,
- I3 => \s_datao_fmc2[65]\(17),
- I4 => \axi_araddr_reg[2]_rep__0\,
- I5 => \s_datao_fmc2[64]\(17),
- O => \axi_rdata[17]_i_28_n_0\
- );
-\axi_rdata[18]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(18),
- I1 => \s_datao_fmc2[50]\(18),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[49]\(18),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[48]\(18),
- O => \axi_rdata_reg[18]\
- );
-\axi_rdata[18]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(18),
- I1 => \s_datao_fmc2[54]\(18),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[53]\(18),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[52]\(18),
- O => \axi_rdata[18]_i_25_n_0\
- );
-\axi_rdata[18]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(18),
- I1 => \s_datao_fmc2[58]\(18),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[57]\(18),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[56]\(18),
- O => \axi_rdata[18]_i_26_n_0\
- );
-\axi_rdata[18]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(18),
- I1 => \s_datao_fmc2[62]\(18),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[61]\(18),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[60]\(18),
- O => \axi_rdata[18]_i_27_n_0\
- );
-\axi_rdata[18]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(18),
- I1 => \s_datao_fmc2[66]\(18),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[65]\(18),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[64]\(18),
- O => \axi_rdata[18]_i_28_n_0\
- );
-\axi_rdata[19]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(19),
- I1 => \s_datao_fmc2[50]\(19),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[49]\(19),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[48]\(19),
- O => \axi_rdata_reg[19]\
- );
-\axi_rdata[19]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(19),
- I1 => \s_datao_fmc2[54]\(19),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[53]\(19),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[52]\(19),
- O => \axi_rdata[19]_i_25_n_0\
- );
-\axi_rdata[19]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(19),
- I1 => \s_datao_fmc2[58]\(19),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[57]\(19),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[56]\(19),
- O => \axi_rdata[19]_i_26_n_0\
- );
-\axi_rdata[19]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(19),
- I1 => \s_datao_fmc2[62]\(19),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[61]\(19),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[60]\(19),
- O => \axi_rdata[19]_i_27_n_0\
- );
-\axi_rdata[19]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(19),
- I1 => \s_datao_fmc2[66]\(19),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[65]\(19),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[64]\(19),
- O => \axi_rdata[19]_i_28_n_0\
- );
-\axi_rdata[1]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(1),
- I1 => \s_datao_fmc2[50]\(1),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[49]\(1),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[48]\(1),
- O => \axi_rdata_reg[1]_0\
- );
-\axi_rdata[1]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(1),
- I1 => \s_datao_fmc2[54]\(1),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[53]\(1),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[52]\(1),
- O => \axi_rdata[1]_i_25_n_0\
- );
-\axi_rdata[1]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(1),
- I1 => \s_datao_fmc2[58]\(1),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[57]\(1),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[56]\(1),
- O => \axi_rdata[1]_i_26_n_0\
- );
-\axi_rdata[1]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(1),
- I1 => \s_datao_fmc2[62]\(1),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[61]\(1),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[60]\(1),
- O => \axi_rdata[1]_i_27_n_0\
- );
-\axi_rdata[1]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(1),
- I1 => \s_datao_fmc2[66]\(1),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[65]\(1),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[64]\(1),
- O => \axi_rdata[1]_i_28_n_0\
- );
-\axi_rdata[20]_i_10\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(20),
- I1 => \s_datao_fmc2[58]\(20),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[57]\(20),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[56]\(20),
- O => \axi_rdata[20]_i_10_n_0\
- );
-\axi_rdata[20]_i_11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(20),
- I1 => \s_datao_fmc2[62]\(20),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[61]\(20),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[60]\(20),
- O => \axi_rdata[20]_i_11_n_0\
- );
-\axi_rdata[20]_i_12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(20),
- I1 => \s_datao_fmc2[66]\(20),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[65]\(20),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[64]\(20),
- O => \axi_rdata[20]_i_12_n_0\
- );
-\axi_rdata[20]_i_13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(20),
- I1 => \s_datao_fmc2[50]\(20),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[49]\(20),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[48]\(20),
- O => \axi_rdata_reg[20]\
- );
-\axi_rdata[20]_i_9\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(20),
- I1 => \s_datao_fmc2[54]\(20),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[53]\(20),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[52]\(20),
- O => \axi_rdata[20]_i_9_n_0\
- );
-\axi_rdata[21]_i_10\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(21),
- I1 => \s_datao_fmc2[58]\(21),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[57]\(21),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[56]\(21),
- O => \axi_rdata[21]_i_10_n_0\
- );
-\axi_rdata[21]_i_11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(21),
- I1 => \s_datao_fmc2[62]\(21),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[61]\(21),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[60]\(21),
- O => \axi_rdata[21]_i_11_n_0\
- );
-\axi_rdata[21]_i_12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(21),
- I1 => \s_datao_fmc2[66]\(21),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[65]\(21),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[64]\(21),
- O => \axi_rdata[21]_i_12_n_0\
- );
-\axi_rdata[21]_i_13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(21),
- I1 => \s_datao_fmc2[50]\(21),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[49]\(21),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[48]\(21),
- O => \axi_rdata_reg[21]\
- );
-\axi_rdata[21]_i_9\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(21),
- I1 => \s_datao_fmc2[54]\(21),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[53]\(21),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[52]\(21),
- O => \axi_rdata[21]_i_9_n_0\
- );
-\axi_rdata[22]_i_10\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(22),
- I1 => \s_datao_fmc2[58]\(22),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[57]\(22),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[56]\(22),
- O => \axi_rdata[22]_i_10_n_0\
- );
-\axi_rdata[22]_i_11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(22),
- I1 => \s_datao_fmc2[62]\(22),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[61]\(22),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[60]\(22),
- O => \axi_rdata[22]_i_11_n_0\
- );
-\axi_rdata[22]_i_12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(22),
- I1 => \s_datao_fmc2[66]\(22),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[65]\(22),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[64]\(22),
- O => \axi_rdata[22]_i_12_n_0\
- );
-\axi_rdata[22]_i_13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(22),
- I1 => \s_datao_fmc2[50]\(22),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[49]\(22),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[48]\(22),
- O => \axi_rdata_reg[22]\
- );
-\axi_rdata[22]_i_9\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(22),
- I1 => \s_datao_fmc2[54]\(22),
- I2 => \axi_araddr_reg[3]_rep\,
- I3 => \s_datao_fmc2[53]\(22),
- I4 => \axi_araddr_reg[2]_rep\,
- I5 => \s_datao_fmc2[52]\(22),
- O => \axi_rdata[22]_i_9_n_0\
- );
-\axi_rdata[23]_i_10\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(23),
- I1 => \s_datao_fmc2[54]\(23),
- I2 => \axi_araddr_reg[5]\(1),
- I3 => \s_datao_fmc2[53]\(23),
- I4 => \axi_araddr_reg[5]\(0),
- I5 => \s_datao_fmc2[52]\(23),
- O => \axi_rdata[23]_i_10_n_0\
- );
-\axi_rdata[23]_i_11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(23),
- I1 => \s_datao_fmc2[58]\(23),
- I2 => \axi_araddr_reg[5]\(1),
- I3 => \s_datao_fmc2[57]\(23),
- I4 => \axi_araddr_reg[5]\(0),
- I5 => \s_datao_fmc2[56]\(23),
- O => \axi_rdata[23]_i_11_n_0\
- );
-\axi_rdata[23]_i_12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(23),
- I1 => \s_datao_fmc2[62]\(23),
- I2 => \axi_araddr_reg[5]\(1),
- I3 => \s_datao_fmc2[61]\(23),
- I4 => \axi_araddr_reg[5]\(0),
- I5 => \s_datao_fmc2[60]\(23),
- O => \axi_rdata[23]_i_12_n_0\
- );
-\axi_rdata[23]_i_13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(23),
- I1 => \s_datao_fmc2[66]\(23),
- I2 => \axi_araddr_reg[5]\(1),
- I3 => \s_datao_fmc2[65]\(23),
- I4 => \axi_araddr_reg[5]\(0),
- I5 => \s_datao_fmc2[64]\(23),
- O => \axi_rdata[23]_i_13_n_0\
- );
-\axi_rdata[23]_i_14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(23),
- I1 => \s_datao_fmc2[50]\(23),
- I2 => \axi_araddr_reg[5]\(1),
- I3 => \s_datao_fmc2[49]\(23),
- I4 => \axi_araddr_reg[5]\(0),
- I5 => \s_datao_fmc2[48]\(23),
- O => \axi_rdata_reg[23]\
- );
-\axi_rdata[2]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(2),
- I1 => \s_datao_fmc2[50]\(2),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[49]\(2),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[48]\(2),
- O => \axi_rdata_reg[2]_0\
- );
-\axi_rdata[2]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(2),
- I1 => \s_datao_fmc2[54]\(2),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[53]\(2),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[52]\(2),
- O => \axi_rdata[2]_i_25_n_0\
- );
-\axi_rdata[2]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(2),
- I1 => \s_datao_fmc2[58]\(2),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[57]\(2),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[56]\(2),
- O => \axi_rdata[2]_i_26_n_0\
- );
-\axi_rdata[2]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(2),
- I1 => \s_datao_fmc2[62]\(2),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[61]\(2),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[60]\(2),
- O => \axi_rdata[2]_i_27_n_0\
- );
-\axi_rdata[2]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(2),
- I1 => \s_datao_fmc2[66]\(2),
- I2 => \axi_araddr_reg[3]_rep__3\,
- I3 => \s_datao_fmc2[65]\(2),
- I4 => \axi_araddr_reg[2]_rep__3\,
- I5 => \s_datao_fmc2[64]\(2),
- O => \axi_rdata[2]_i_28_n_0\
- );
-\axi_rdata[3]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(3),
- I1 => \s_datao_fmc2[50]\(3),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[49]\(3),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[48]\(3),
- O => \axi_rdata_reg[3]_0\
- );
-\axi_rdata[3]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(3),
- I1 => \s_datao_fmc2[54]\(3),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[53]\(3),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[52]\(3),
- O => \axi_rdata[3]_i_25_n_0\
- );
-\axi_rdata[3]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(3),
- I1 => \s_datao_fmc2[58]\(3),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[57]\(3),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[56]\(3),
- O => \axi_rdata[3]_i_26_n_0\
- );
-\axi_rdata[3]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(3),
- I1 => \s_datao_fmc2[62]\(3),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[61]\(3),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[60]\(3),
- O => \axi_rdata[3]_i_27_n_0\
- );
-\axi_rdata[3]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(3),
- I1 => \s_datao_fmc2[66]\(3),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[65]\(3),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[64]\(3),
- O => \axi_rdata[3]_i_28_n_0\
- );
-\axi_rdata[4]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(4),
- I1 => \s_datao_fmc2[50]\(4),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[49]\(4),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[48]\(4),
- O => \axi_rdata_reg[4]_0\
- );
-\axi_rdata[4]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(4),
- I1 => \s_datao_fmc2[54]\(4),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[53]\(4),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[52]\(4),
- O => \axi_rdata[4]_i_25_n_0\
- );
-\axi_rdata[4]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(4),
- I1 => \s_datao_fmc2[58]\(4),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[57]\(4),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[56]\(4),
- O => \axi_rdata[4]_i_26_n_0\
- );
-\axi_rdata[4]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(4),
- I1 => \s_datao_fmc2[62]\(4),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[61]\(4),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[60]\(4),
- O => \axi_rdata[4]_i_27_n_0\
- );
-\axi_rdata[4]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(4),
- I1 => \s_datao_fmc2[66]\(4),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[65]\(4),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[64]\(4),
- O => \axi_rdata[4]_i_28_n_0\
- );
-\axi_rdata[5]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(5),
- I1 => \s_datao_fmc2[50]\(5),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[49]\(5),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[48]\(5),
- O => \axi_rdata_reg[5]_0\
- );
-\axi_rdata[5]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(5),
- I1 => \s_datao_fmc2[54]\(5),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[53]\(5),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[52]\(5),
- O => \axi_rdata[5]_i_25_n_0\
- );
-\axi_rdata[5]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(5),
- I1 => \s_datao_fmc2[58]\(5),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[57]\(5),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[56]\(5),
- O => \axi_rdata[5]_i_26_n_0\
- );
-\axi_rdata[5]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(5),
- I1 => \s_datao_fmc2[62]\(5),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[61]\(5),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[60]\(5),
- O => \axi_rdata[5]_i_27_n_0\
- );
-\axi_rdata[5]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(5),
- I1 => \s_datao_fmc2[66]\(5),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[65]\(5),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[64]\(5),
- O => \axi_rdata[5]_i_28_n_0\
- );
-\axi_rdata[6]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(6),
- I1 => \s_datao_fmc2[50]\(6),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[49]\(6),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[48]\(6),
- O => \axi_rdata_reg[6]_0\
- );
-\axi_rdata[6]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(6),
- I1 => \s_datao_fmc2[54]\(6),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[53]\(6),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[52]\(6),
- O => \axi_rdata[6]_i_25_n_0\
- );
-\axi_rdata[6]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(6),
- I1 => \s_datao_fmc2[58]\(6),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[57]\(6),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[56]\(6),
- O => \axi_rdata[6]_i_26_n_0\
- );
-\axi_rdata[6]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(6),
- I1 => \s_datao_fmc2[62]\(6),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[61]\(6),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[60]\(6),
- O => \axi_rdata[6]_i_27_n_0\
- );
-\axi_rdata[6]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(6),
- I1 => \s_datao_fmc2[66]\(6),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[65]\(6),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[64]\(6),
- O => \axi_rdata[6]_i_28_n_0\
- );
-\axi_rdata[7]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(7),
- I1 => \s_datao_fmc2[50]\(7),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[49]\(7),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[48]\(7),
- O => \axi_rdata_reg[7]_0\
- );
-\axi_rdata[7]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(7),
- I1 => \s_datao_fmc2[54]\(7),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[53]\(7),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[52]\(7),
- O => \axi_rdata[7]_i_25_n_0\
- );
-\axi_rdata[7]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(7),
- I1 => \s_datao_fmc2[58]\(7),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[57]\(7),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[56]\(7),
- O => \axi_rdata[7]_i_26_n_0\
- );
-\axi_rdata[7]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(7),
- I1 => \s_datao_fmc2[62]\(7),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[61]\(7),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[60]\(7),
- O => \axi_rdata[7]_i_27_n_0\
- );
-\axi_rdata[7]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(7),
- I1 => \s_datao_fmc2[66]\(7),
- I2 => \axi_araddr_reg[3]_rep__2\,
- I3 => \s_datao_fmc2[65]\(7),
- I4 => \axi_araddr_reg[2]_rep__2\,
- I5 => \s_datao_fmc2[64]\(7),
- O => \axi_rdata[7]_i_28_n_0\
- );
-\axi_rdata[8]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(8),
- I1 => \s_datao_fmc2[50]\(8),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[49]\(8),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[48]\(8),
- O => \axi_rdata_reg[8]\
- );
-\axi_rdata[8]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(8),
- I1 => \s_datao_fmc2[54]\(8),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[53]\(8),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[52]\(8),
- O => \axi_rdata[8]_i_25_n_0\
- );
-\axi_rdata[8]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(8),
- I1 => \s_datao_fmc2[58]\(8),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[57]\(8),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[56]\(8),
- O => \axi_rdata[8]_i_26_n_0\
- );
-\axi_rdata[8]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(8),
- I1 => \s_datao_fmc2[62]\(8),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[61]\(8),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[60]\(8),
- O => \axi_rdata[8]_i_27_n_0\
- );
-\axi_rdata[8]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(8),
- I1 => \s_datao_fmc2[66]\(8),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[65]\(8),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[64]\(8),
- O => \axi_rdata[8]_i_28_n_0\
- );
-\axi_rdata[9]_i_22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[51]\(9),
- I1 => \s_datao_fmc2[50]\(9),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[49]\(9),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[48]\(9),
- O => \axi_rdata_reg[9]\
- );
-\axi_rdata[9]_i_25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[55]\(9),
- I1 => \s_datao_fmc2[54]\(9),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[53]\(9),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[52]\(9),
- O => \axi_rdata[9]_i_25_n_0\
- );
-\axi_rdata[9]_i_26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[59]\(9),
- I1 => \s_datao_fmc2[58]\(9),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[57]\(9),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[56]\(9),
- O => \axi_rdata[9]_i_26_n_0\
- );
-\axi_rdata[9]_i_27\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[63]\(9),
- I1 => \s_datao_fmc2[62]\(9),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[61]\(9),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[60]\(9),
- O => \axi_rdata[9]_i_27_n_0\
- );
-\axi_rdata[9]_i_28\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"AFA0CFCFAFA0C0C0"
- )
- port map (
- I0 => \s_datao_fmc2[67]\(9),
- I1 => \s_datao_fmc2[66]\(9),
- I2 => \axi_araddr_reg[3]_rep__1\,
- I3 => \s_datao_fmc2[65]\(9),
- I4 => \axi_araddr_reg[2]_rep__1\,
- I5 => \s_datao_fmc2[64]\(9),
- O => \axi_rdata[9]_i_28_n_0\
- );
-\axi_rdata_reg[0]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[0]_i_27_n_0\,
- I1 => \axi_rdata[0]_i_28_n_0\,
- O => \axi_rdata_reg[0]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep__1\
- );
-\axi_rdata_reg[0]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[0]_i_9_n_0\,
- I1 => \axi_rdata_reg[0]_i_10_n_0\,
- O => \axi_rdata_reg[0]_1\,
- S => \axi_araddr_reg[5]_rep\
- );
-\axi_rdata_reg[0]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[0]_i_25_n_0\,
- I1 => \axi_rdata[0]_i_26_n_0\,
- O => \axi_rdata_reg[0]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep__1\
- );
-\axi_rdata_reg[10]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[10]_i_27_n_0\,
- I1 => \axi_rdata[10]_i_28_n_0\,
- O => \axi_rdata_reg[10]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[10]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[10]_i_9_n_0\,
- I1 => \axi_rdata_reg[10]_i_10_n_0\,
- O => \axi_rdata_reg[10]_0\,
- S => \axi_araddr_reg[5]_rep\
- );
-\axi_rdata_reg[10]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[10]_i_25_n_0\,
- I1 => \axi_rdata[10]_i_26_n_0\,
- O => \axi_rdata_reg[10]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[11]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[11]_i_27_n_0\,
- I1 => \axi_rdata[11]_i_28_n_0\,
- O => \axi_rdata_reg[11]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[11]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[11]_i_9_n_0\,
- I1 => \axi_rdata_reg[11]_i_10_n_0\,
- O => \axi_rdata_reg[11]_0\,
- S => \axi_araddr_reg[5]\(3)
- );
-\axi_rdata_reg[11]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[11]_i_25_n_0\,
- I1 => \axi_rdata[11]_i_26_n_0\,
- O => \axi_rdata_reg[11]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[12]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[12]_i_27_n_0\,
- I1 => \axi_rdata[12]_i_28_n_0\,
- O => \axi_rdata_reg[12]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[12]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[12]_i_9_n_0\,
- I1 => \axi_rdata_reg[12]_i_10_n_0\,
- O => \axi_rdata_reg[12]_0\,
- S => \axi_araddr_reg[5]\(3)
- );
-\axi_rdata_reg[12]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[12]_i_25_n_0\,
- I1 => \axi_rdata[12]_i_26_n_0\,
- O => \axi_rdata_reg[12]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[13]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[13]_i_27_n_0\,
- I1 => \axi_rdata[13]_i_28_n_0\,
- O => \axi_rdata_reg[13]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[13]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[13]_i_9_n_0\,
- I1 => \axi_rdata_reg[13]_i_10_n_0\,
- O => \axi_rdata_reg[13]_0\,
- S => \axi_araddr_reg[5]\(3)
- );
-\axi_rdata_reg[13]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[13]_i_25_n_0\,
- I1 => \axi_rdata[13]_i_26_n_0\,
- O => \axi_rdata_reg[13]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[14]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[14]_i_27_n_0\,
- I1 => \axi_rdata[14]_i_28_n_0\,
- O => \axi_rdata_reg[14]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[14]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[14]_i_9_n_0\,
- I1 => \axi_rdata_reg[14]_i_10_n_0\,
- O => \axi_rdata_reg[14]_0\,
- S => \axi_araddr_reg[5]\(3)
- );
-\axi_rdata_reg[14]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[14]_i_25_n_0\,
- I1 => \axi_rdata[14]_i_26_n_0\,
- O => \axi_rdata_reg[14]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[15]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[15]_i_27_n_0\,
- I1 => \axi_rdata[15]_i_28_n_0\,
- O => \axi_rdata_reg[15]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[15]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[15]_i_9_n_0\,
- I1 => \axi_rdata_reg[15]_i_10_n_0\,
- O => \axi_rdata_reg[15]_0\,
- S => \axi_araddr_reg[5]\(3)
- );
-\axi_rdata_reg[15]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[15]_i_25_n_0\,
- I1 => \axi_rdata[15]_i_26_n_0\,
- O => \axi_rdata_reg[15]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[16]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[16]_i_27_n_0\,
- I1 => \axi_rdata[16]_i_28_n_0\,
- O => \axi_rdata_reg[16]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[16]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[16]_i_9_n_0\,
- I1 => \axi_rdata_reg[16]_i_10_n_0\,
- O => \axi_rdata_reg[16]_0\,
- S => \axi_araddr_reg[5]\(3)
- );
-\axi_rdata_reg[16]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[16]_i_25_n_0\,
- I1 => \axi_rdata[16]_i_26_n_0\,
- O => \axi_rdata_reg[16]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[17]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[17]_i_27_n_0\,
- I1 => \axi_rdata[17]_i_28_n_0\,
- O => \axi_rdata_reg[17]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[17]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[17]_i_9_n_0\,
- I1 => \axi_rdata_reg[17]_i_10_n_0\,
- O => \axi_rdata_reg[17]_0\,
- S => \axi_araddr_reg[5]\(3)
- );
-\axi_rdata_reg[17]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[17]_i_25_n_0\,
- I1 => \axi_rdata[17]_i_26_n_0\,
- O => \axi_rdata_reg[17]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[18]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[18]_i_27_n_0\,
- I1 => \axi_rdata[18]_i_28_n_0\,
- O => \axi_rdata_reg[18]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[18]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[18]_i_9_n_0\,
- I1 => \axi_rdata_reg[18]_i_10_n_0\,
- O => \axi_rdata_reg[18]_0\,
- S => \axi_araddr_reg[5]\(3)
- );
-\axi_rdata_reg[18]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[18]_i_25_n_0\,
- I1 => \axi_rdata[18]_i_26_n_0\,
- O => \axi_rdata_reg[18]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep\
- );
-\axi_rdata_reg[19]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[19]_i_27_n_0\,
- I1 => \axi_rdata[19]_i_28_n_0\,
- O => \axi_rdata_reg[19]_i_10_n_0\,
- S => \axi_araddr_reg[5]\(2)
- );
-\axi_rdata_reg[19]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[19]_i_9_n_0\,
- I1 => \axi_rdata_reg[19]_i_10_n_0\,
- O => \axi_rdata_reg[19]_0\,
- S => \axi_araddr_reg[5]\(3)
- );
-\axi_rdata_reg[19]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[19]_i_25_n_0\,
- I1 => \axi_rdata[19]_i_26_n_0\,
- O => \axi_rdata_reg[19]_i_9_n_0\,
- S => \axi_araddr_reg[5]\(2)
- );
-\axi_rdata_reg[1]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[1]_i_27_n_0\,
- I1 => \axi_rdata[1]_i_28_n_0\,
- O => \axi_rdata_reg[1]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[1]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[1]_i_9_n_0\,
- I1 => \axi_rdata_reg[1]_i_10_n_0\,
- O => \axi_rdata_reg[1]_1\,
- S => \axi_araddr_reg[5]_rep\
- );
-\axi_rdata_reg[1]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[1]_i_25_n_0\,
- I1 => \axi_rdata[1]_i_26_n_0\,
- O => \axi_rdata_reg[1]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[20]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[20]_i_9_n_0\,
- I1 => \axi_rdata[20]_i_10_n_0\,
- O => \axi_rdata_reg[20]_0\,
- S => \axi_araddr_reg[5]\(2)
- );
-\axi_rdata_reg[20]_i_4\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[20]_i_11_n_0\,
- I1 => \axi_rdata[20]_i_12_n_0\,
- O => \axi_rdata_reg[20]_1\,
- S => \axi_araddr_reg[5]\(2)
- );
-\axi_rdata_reg[21]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[21]_i_9_n_0\,
- I1 => \axi_rdata[21]_i_10_n_0\,
- O => \axi_rdata_reg[21]_0\,
- S => \axi_araddr_reg[5]\(2)
- );
-\axi_rdata_reg[21]_i_4\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[21]_i_11_n_0\,
- I1 => \axi_rdata[21]_i_12_n_0\,
- O => \axi_rdata_reg[21]_1\,
- S => \axi_araddr_reg[5]\(2)
- );
-\axi_rdata_reg[22]_i_3\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[22]_i_9_n_0\,
- I1 => \axi_rdata[22]_i_10_n_0\,
- O => \axi_rdata_reg[22]_0\,
- S => \axi_araddr_reg[5]\(2)
- );
-\axi_rdata_reg[22]_i_4\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[22]_i_11_n_0\,
- I1 => \axi_rdata[22]_i_12_n_0\,
- O => \axi_rdata_reg[22]_1\,
- S => \axi_araddr_reg[5]\(2)
- );
-\axi_rdata_reg[23]_i_4\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[23]_i_10_n_0\,
- I1 => \axi_rdata[23]_i_11_n_0\,
- O => \axi_rdata_reg[23]_0\,
- S => \axi_araddr_reg[5]\(2)
- );
-\axi_rdata_reg[23]_i_5\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[23]_i_12_n_0\,
- I1 => \axi_rdata[23]_i_13_n_0\,
- O => \axi_rdata_reg[23]_1\,
- S => \axi_araddr_reg[5]\(2)
- );
-\axi_rdata_reg[2]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[2]_i_27_n_0\,
- I1 => \axi_rdata[2]_i_28_n_0\,
- O => \axi_rdata_reg[2]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[2]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[2]_i_9_n_0\,
- I1 => \axi_rdata_reg[2]_i_10_n_0\,
- O => \axi_rdata_reg[2]_1\,
- S => \axi_araddr_reg[5]_rep\
- );
-\axi_rdata_reg[2]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[2]_i_25_n_0\,
- I1 => \axi_rdata[2]_i_26_n_0\,
- O => \axi_rdata_reg[2]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[3]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[3]_i_27_n_0\,
- I1 => \axi_rdata[3]_i_28_n_0\,
- O => \axi_rdata_reg[3]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[3]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[3]_i_9_n_0\,
- I1 => \axi_rdata_reg[3]_i_10_n_0\,
- O => \axi_rdata_reg[3]_1\,
- S => \axi_araddr_reg[5]_rep\
- );
-\axi_rdata_reg[3]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[3]_i_25_n_0\,
- I1 => \axi_rdata[3]_i_26_n_0\,
- O => \axi_rdata_reg[3]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[4]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[4]_i_27_n_0\,
- I1 => \axi_rdata[4]_i_28_n_0\,
- O => \axi_rdata_reg[4]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[4]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[4]_i_9_n_0\,
- I1 => \axi_rdata_reg[4]_i_10_n_0\,
- O => \axi_rdata_reg[4]_1\,
- S => \axi_araddr_reg[5]_rep\
- );
-\axi_rdata_reg[4]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[4]_i_25_n_0\,
- I1 => \axi_rdata[4]_i_26_n_0\,
- O => \axi_rdata_reg[4]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[5]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[5]_i_27_n_0\,
- I1 => \axi_rdata[5]_i_28_n_0\,
- O => \axi_rdata_reg[5]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[5]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[5]_i_9_n_0\,
- I1 => \axi_rdata_reg[5]_i_10_n_0\,
- O => \axi_rdata_reg[5]_1\,
- S => \axi_araddr_reg[5]_rep\
- );
-\axi_rdata_reg[5]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[5]_i_25_n_0\,
- I1 => \axi_rdata[5]_i_26_n_0\,
- O => \axi_rdata_reg[5]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[6]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[6]_i_27_n_0\,
- I1 => \axi_rdata[6]_i_28_n_0\,
- O => \axi_rdata_reg[6]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[6]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[6]_i_9_n_0\,
- I1 => \axi_rdata_reg[6]_i_10_n_0\,
- O => \axi_rdata_reg[6]_1\,
- S => \axi_araddr_reg[5]_rep\
- );
-\axi_rdata_reg[6]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[6]_i_25_n_0\,
- I1 => \axi_rdata[6]_i_26_n_0\,
- O => \axi_rdata_reg[6]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[7]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[7]_i_27_n_0\,
- I1 => \axi_rdata[7]_i_28_n_0\,
- O => \axi_rdata_reg[7]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[7]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[7]_i_9_n_0\,
- I1 => \axi_rdata_reg[7]_i_10_n_0\,
- O => \axi_rdata_reg[7]_1\,
- S => \axi_araddr_reg[5]_rep\
- );
-\axi_rdata_reg[7]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[7]_i_25_n_0\,
- I1 => \axi_rdata[7]_i_26_n_0\,
- O => \axi_rdata_reg[7]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[8]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[8]_i_27_n_0\,
- I1 => \axi_rdata[8]_i_28_n_0\,
- O => \axi_rdata_reg[8]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[8]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[8]_i_9_n_0\,
- I1 => \axi_rdata_reg[8]_i_10_n_0\,
- O => \axi_rdata_reg[8]_0\,
- S => \axi_araddr_reg[5]_rep\
- );
-\axi_rdata_reg[8]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[8]_i_25_n_0\,
- I1 => \axi_rdata[8]_i_26_n_0\,
- O => \axi_rdata_reg[8]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[9]_i_10\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[9]_i_27_n_0\,
- I1 => \axi_rdata[9]_i_28_n_0\,
- O => \axi_rdata_reg[9]_i_10_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\axi_rdata_reg[9]_i_4\: unisim.vcomponents.MUXF8
- port map (
- I0 => \axi_rdata_reg[9]_i_9_n_0\,
- I1 => \axi_rdata_reg[9]_i_10_n_0\,
- O => \axi_rdata_reg[9]_0\,
- S => \axi_araddr_reg[5]_rep\
- );
-\axi_rdata_reg[9]_i_9\: unisim.vcomponents.MUXF7
- port map (
- I0 => \axi_rdata[9]_i_25_n_0\,
- I1 => \axi_rdata[9]_i_26_n_0\,
- O => \axi_rdata_reg[9]_i_9_n_0\,
- S => \axi_araddr_reg[4]_rep__0\
- );
-\data_o_reg[1][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_fbd(0),
- Q => \axi_rdata_reg[3]_2\(0),
- R => '0'
- );
-\data_o_reg[1][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_fbd(1),
- Q => \axi_rdata_reg[3]_2\(1),
- R => '0'
- );
-\data_o_reg[1][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_fbd(2),
- Q => \axi_rdata_reg[3]_2\(2),
- R => '0'
- );
-\data_o_reg[1][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_fbd(3),
- Q => \axi_rdata_reg[3]_2\(3),
- R => '0'
- );
-\data_o_reg[6][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(0),
- Q => \s_datao_fmc2[6]\(0),
- R => '0'
- );
-\data_o_reg[6][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(1),
- Q => \s_datao_fmc2[6]\(1),
- R => '0'
- );
-\data_o_reg[6][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(2),
- Q => \s_datao_fmc2[6]\(2),
- R => '0'
- );
-\data_o_reg[6][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => D(3),
- Q => \s_datao_fmc2[6]\(3),
- R => '0'
- );
-\data_o_reg[6][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_diffouts_o(4),
- Q => \s_datao_fmc2[6]\(4),
- R => '0'
- );
-\data_o_reg[6][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_diffouts_o(5),
- Q => \s_datao_fmc2[6]\(5),
- R => '0'
- );
-\data_o_reg[6][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_diffouts_o(6),
- Q => \s_datao_fmc2[6]\(6),
- R => '0'
- );
-\data_o_reg[6][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => s_diffouts_o(7),
- Q => \s_datao_fmc2[6]\(7),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(0),
- IB => \FMC2_LA_N_b[32]\(0),
- O => s_comparators_i_0
- );
-\fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure
- port map (
- D(0) => \^s_datao_fmc2[0]\(0),
- E(0) => \cmp_lengthCounter/RSTP\,
- Q(2 downto 0) => v_cmpled(2 downto 0),
- S(0) => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_3\,
- \data_rw_o_reg[79][7]\(0) => \data_rw_o_reg[79][7]\(2),
- \fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\(23 downto 0) => \s_cmp_lengths[0]_0\(23 downto 0),
- intr_o_reg(0) => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_4\,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce\(4 downto 0),
- s_buff2_reg_0(1 downto 0) => \^s_datao_fmc2[0]\(2 downto 1),
- s_comparators_i_0 => s_comparators_i_0,
- \s_datao_fmc2[4]\(0) => \s_datao_fmc2[4]\(0),
- \s_debounce_reg[1]\ => s_buff2_i_1_n_0,
- s_pulseLed_reg_0(1 downto 0) => \s_datao_fmc2[4]\(2 downto 1),
- \v_cmp_reg[2]\(2 downto 0) => v_cmp(2 downto 0),
- \v_dout_reg[7]\ => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2\
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(0),
- Q => \s_datao_fmc2[48]\(0),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(10),
- Q => \s_datao_fmc2[48]\(10),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(11),
- Q => \s_datao_fmc2[48]\(11),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(12),
- Q => \s_datao_fmc2[48]\(12),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(13),
- Q => \s_datao_fmc2[48]\(13),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(14),
- Q => \s_datao_fmc2[48]\(14),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(15),
- Q => \s_datao_fmc2[48]\(15),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(16),
- Q => \s_datao_fmc2[48]\(16),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(17),
- Q => \s_datao_fmc2[48]\(17),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(18),
- Q => \s_datao_fmc2[48]\(18),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(19),
- Q => \s_datao_fmc2[48]\(19),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(1),
- Q => \s_datao_fmc2[48]\(1),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(20),
- Q => \s_datao_fmc2[48]\(20),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(21),
- Q => \s_datao_fmc2[48]\(21),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(22),
- Q => \s_datao_fmc2[48]\(22),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(23),
- Q => \s_datao_fmc2[48]\(23),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(2),
- Q => \s_datao_fmc2[48]\(2),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(3),
- Q => \s_datao_fmc2[48]\(3),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(4),
- Q => \s_datao_fmc2[48]\(4),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(5),
- Q => \s_datao_fmc2[48]\(5),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(6),
- Q => \s_datao_fmc2[48]\(6),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(7),
- Q => \s_datao_fmc2[48]\(7),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(8),
- Q => \s_datao_fmc2[48]\(8),
- R => '0'
- );
-\fmc_03287_channels[0].gen_chs.data_o_reg[48][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP\,
- D => \s_cmp_lengths[0]_0\(9),
- Q => \s_datao_fmc2[48]\(9),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(10),
- IB => \FMC2_LA_N_b[32]\(10),
- O => s_comparators_i_10
- );
-\fmc_03287_channels[10].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_1
- port map (
- D(0) => \^s_count_reg\(2),
- E(0) => \cmp_lengthCounter/RSTP_1\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_0\(4 downto 0),
- \fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\(23 downto 0) => \s_cmp_lengths[10]_10\(23 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc2[0]\(10),
- s_comparators_i_10 => s_comparators_i_10,
- \s_debounce_reg[1]\ => \s_buff2_i_1__9_n_0\
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(0),
- Q => \s_datao_fmc2[58]\(0),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(10),
- Q => \s_datao_fmc2[58]\(10),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(11),
- Q => \s_datao_fmc2[58]\(11),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(12),
- Q => \s_datao_fmc2[58]\(12),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(13),
- Q => \s_datao_fmc2[58]\(13),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(14),
- Q => \s_datao_fmc2[58]\(14),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(15),
- Q => \s_datao_fmc2[58]\(15),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(16),
- Q => \s_datao_fmc2[58]\(16),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(17),
- Q => \s_datao_fmc2[58]\(17),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(18),
- Q => \s_datao_fmc2[58]\(18),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(19),
- Q => \s_datao_fmc2[58]\(19),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(1),
- Q => \s_datao_fmc2[58]\(1),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(20),
- Q => \s_datao_fmc2[58]\(20),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(21),
- Q => \s_datao_fmc2[58]\(21),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(22),
- Q => \s_datao_fmc2[58]\(22),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(23),
- Q => \s_datao_fmc2[58]\(23),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(2),
- Q => \s_datao_fmc2[58]\(2),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(3),
- Q => \s_datao_fmc2[58]\(3),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(4),
- Q => \s_datao_fmc2[58]\(4),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(5),
- Q => \s_datao_fmc2[58]\(5),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(6),
- Q => \s_datao_fmc2[58]\(6),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(7),
- Q => \s_datao_fmc2[58]\(7),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(8),
- Q => \s_datao_fmc2[58]\(8),
- R => '0'
- );
-\fmc_03287_channels[10].gen_chs.data_o_reg[58][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_1\,
- D => \s_cmp_lengths[10]_10\(9),
- Q => \s_datao_fmc2[58]\(9),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(11),
- IB => \FMC2_LA_N_b[32]\(11),
- O => s_comparators_i_11
- );
-\fmc_03287_channels[11].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_2
- port map (
- D(0) => \^s_count_reg\(3),
- E(0) => \cmp_lengthCounter/RSTP_3\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_2\(4 downto 0),
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\(23 downto 0) => \s_cmp_lengths[11]_11\(23 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc2[0]\(11),
- s_comparators_i_11 => s_comparators_i_11,
- \s_debounce_reg[1]\ => \s_buff2_i_1__10_n_0\
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(0),
- Q => \s_datao_fmc2[59]\(0),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(10),
- Q => \s_datao_fmc2[59]\(10),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(11),
- Q => \s_datao_fmc2[59]\(11),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(12),
- Q => \s_datao_fmc2[59]\(12),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(13),
- Q => \s_datao_fmc2[59]\(13),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(14),
- Q => \s_datao_fmc2[59]\(14),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(15),
- Q => \s_datao_fmc2[59]\(15),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(16),
- Q => \s_datao_fmc2[59]\(16),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(17),
- Q => \s_datao_fmc2[59]\(17),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(18),
- Q => \s_datao_fmc2[59]\(18),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(19),
- Q => \s_datao_fmc2[59]\(19),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(1),
- Q => \s_datao_fmc2[59]\(1),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(20),
- Q => \s_datao_fmc2[59]\(20),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(21),
- Q => \s_datao_fmc2[59]\(21),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(22),
- Q => \s_datao_fmc2[59]\(22),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(23),
- Q => \s_datao_fmc2[59]\(23),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(2),
- Q => \s_datao_fmc2[59]\(2),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(3),
- Q => \s_datao_fmc2[59]\(3),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(4),
- Q => \s_datao_fmc2[59]\(4),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(5),
- Q => \s_datao_fmc2[59]\(5),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(6),
- Q => \s_datao_fmc2[59]\(6),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(7),
- Q => \s_datao_fmc2[59]\(7),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(8),
- Q => \s_datao_fmc2[59]\(8),
- R => '0'
- );
-\fmc_03287_channels[11].gen_chs.data_o_reg[59][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_3\,
- D => \s_cmp_lengths[11]_11\(9),
- Q => \s_datao_fmc2[59]\(9),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(12),
- IB => \FMC2_LA_N_b[32]\(12),
- O => s_comparators_i_12
- );
-\fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_3
- port map (
- D(0) => \^s_count_reg\(4),
- E(0) => \cmp_lengthCounter/RSTP_5\,
- Q(2 downto 0) => v_cmpled(14 downto 12),
- S(0) => \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_2\,
- \fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\(23 downto 0) => \s_cmp_lengths[12]_12\(23 downto 0),
- intr_o_reg(0) => \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_3\,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_4\(4 downto 0),
- s_buff2_reg_0(1 downto 0) => \^s_datao_fmc2[0]\(14 downto 13),
- s_buff3_reg(0) => \^s_datao_fmc2[0]\(12),
- s_comparators_i_12 => s_comparators_i_12,
- \s_debounce_reg[1]\ => \s_buff2_i_1__11_n_0\,
- s_pulseLed_reg_0(1 downto 0) => \^s_count_reg\(6 downto 5),
- \v_cmp_reg[14]\(2 downto 0) => v_cmp(14 downto 12)
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(0),
- Q => \s_datao_fmc2[60]\(0),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(10),
- Q => \s_datao_fmc2[60]\(10),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(11),
- Q => \s_datao_fmc2[60]\(11),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(12),
- Q => \s_datao_fmc2[60]\(12),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(13),
- Q => \s_datao_fmc2[60]\(13),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(14),
- Q => \s_datao_fmc2[60]\(14),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(15),
- Q => \s_datao_fmc2[60]\(15),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(16),
- Q => \s_datao_fmc2[60]\(16),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(17),
- Q => \s_datao_fmc2[60]\(17),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(18),
- Q => \s_datao_fmc2[60]\(18),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(19),
- Q => \s_datao_fmc2[60]\(19),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(1),
- Q => \s_datao_fmc2[60]\(1),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(20),
- Q => \s_datao_fmc2[60]\(20),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(21),
- Q => \s_datao_fmc2[60]\(21),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(22),
- Q => \s_datao_fmc2[60]\(22),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(23),
- Q => \s_datao_fmc2[60]\(23),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(2),
- Q => \s_datao_fmc2[60]\(2),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(3),
- Q => \s_datao_fmc2[60]\(3),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(4),
- Q => \s_datao_fmc2[60]\(4),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(5),
- Q => \s_datao_fmc2[60]\(5),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(6),
- Q => \s_datao_fmc2[60]\(6),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(7),
- Q => \s_datao_fmc2[60]\(7),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(8),
- Q => \s_datao_fmc2[60]\(8),
- R => '0'
- );
-\fmc_03287_channels[12].gen_chs.data_o_reg[60][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_5\,
- D => \s_cmp_lengths[12]_12\(9),
- Q => \s_datao_fmc2[60]\(9),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(13),
- IB => \FMC2_LA_N_b[32]\(13),
- O => s_comparators_i_13
- );
-\fmc_03287_channels[13].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_4
- port map (
- D(0) => \^s_count_reg\(5),
- E(0) => \cmp_lengthCounter/RSTP_7\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_6\(4 downto 0),
- \fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\(23 downto 0) => \s_cmp_lengths[13]_13\(23 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc2[0]\(13),
- s_comparators_i_13 => s_comparators_i_13,
- \s_debounce_reg[1]\ => \s_buff2_i_1__12_n_0\
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(0),
- Q => \s_datao_fmc2[61]\(0),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(10),
- Q => \s_datao_fmc2[61]\(10),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(11),
- Q => \s_datao_fmc2[61]\(11),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(12),
- Q => \s_datao_fmc2[61]\(12),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(13),
- Q => \s_datao_fmc2[61]\(13),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(14),
- Q => \s_datao_fmc2[61]\(14),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(15),
- Q => \s_datao_fmc2[61]\(15),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(16),
- Q => \s_datao_fmc2[61]\(16),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(17),
- Q => \s_datao_fmc2[61]\(17),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(18),
- Q => \s_datao_fmc2[61]\(18),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(19),
- Q => \s_datao_fmc2[61]\(19),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(1),
- Q => \s_datao_fmc2[61]\(1),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(20),
- Q => \s_datao_fmc2[61]\(20),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(21),
- Q => \s_datao_fmc2[61]\(21),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(22),
- Q => \s_datao_fmc2[61]\(22),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(23),
- Q => \s_datao_fmc2[61]\(23),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(2),
- Q => \s_datao_fmc2[61]\(2),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(3),
- Q => \s_datao_fmc2[61]\(3),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(4),
- Q => \s_datao_fmc2[61]\(4),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(5),
- Q => \s_datao_fmc2[61]\(5),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(6),
- Q => \s_datao_fmc2[61]\(6),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(7),
- Q => \s_datao_fmc2[61]\(7),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(8),
- Q => \s_datao_fmc2[61]\(8),
- R => '0'
- );
-\fmc_03287_channels[13].gen_chs.data_o_reg[61][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_7\,
- D => \s_cmp_lengths[13]_13\(9),
- Q => \s_datao_fmc2[61]\(9),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(14),
- IB => \FMC2_LA_N_b[32]\(14),
- O => s_comparators_i_14
- );
-\fmc_03287_channels[14].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_5
- port map (
- D(0) => \^s_count_reg\(6),
- E(0) => \cmp_lengthCounter/RSTP_9\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_8\(4 downto 0),
- \fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\(23 downto 0) => \s_cmp_lengths[14]_14\(23 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc2[0]\(14),
- s_comparators_i_14 => s_comparators_i_14,
- \s_debounce_reg[1]\ => \s_buff2_i_1__13_n_0\
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(0),
- Q => \s_datao_fmc2[62]\(0),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(10),
- Q => \s_datao_fmc2[62]\(10),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(11),
- Q => \s_datao_fmc2[62]\(11),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(12),
- Q => \s_datao_fmc2[62]\(12),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(13),
- Q => \s_datao_fmc2[62]\(13),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(14),
- Q => \s_datao_fmc2[62]\(14),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(15),
- Q => \s_datao_fmc2[62]\(15),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(16),
- Q => \s_datao_fmc2[62]\(16),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(17),
- Q => \s_datao_fmc2[62]\(17),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(18),
- Q => \s_datao_fmc2[62]\(18),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(19),
- Q => \s_datao_fmc2[62]\(19),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(1),
- Q => \s_datao_fmc2[62]\(1),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(20),
- Q => \s_datao_fmc2[62]\(20),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(21),
- Q => \s_datao_fmc2[62]\(21),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(22),
- Q => \s_datao_fmc2[62]\(22),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(23),
- Q => \s_datao_fmc2[62]\(23),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(2),
- Q => \s_datao_fmc2[62]\(2),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(3),
- Q => \s_datao_fmc2[62]\(3),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(4),
- Q => \s_datao_fmc2[62]\(4),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(5),
- Q => \s_datao_fmc2[62]\(5),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(6),
- Q => \s_datao_fmc2[62]\(6),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(7),
- Q => \s_datao_fmc2[62]\(7),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(8),
- Q => \s_datao_fmc2[62]\(8),
- R => '0'
- );
-\fmc_03287_channels[14].gen_chs.data_o_reg[62][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_9\,
- D => \s_cmp_lengths[14]_14\(9),
- Q => \s_datao_fmc2[62]\(9),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(15),
- IB => \FMC2_LA_N_b[32]\(15),
- O => s_comparators_i_15
- );
-\fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_6
- port map (
- D(0) => \^s_count_reg\(7),
- E(0) => \cmp_lengthCounter/RSTP_11\,
- Q(2 downto 0) => v_cmpled(17 downto 15),
- S(0) => \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_2\,
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\(23 downto 0) => \s_cmp_lengths[15]_15\(23 downto 0),
- intr_o_reg(0) => \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_3\,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_10\(4 downto 0),
- s_buff2_reg_0(1 downto 0) => \^s_datao_fmc2[0]\(17 downto 16),
- s_buff3_reg(0) => \^s_datao_fmc2[0]\(15),
- s_comparators_i_15 => s_comparators_i_15,
- \s_debounce_reg[1]\ => \s_buff2_i_1__14_n_0\,
- s_pulseLed_reg_0(1 downto 0) => \^s_count_reg\(9 downto 8),
- \v_cmp_reg[17]\(2 downto 0) => v_cmp(17 downto 15)
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(0),
- Q => \s_datao_fmc2[63]\(0),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(10),
- Q => \s_datao_fmc2[63]\(10),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(11),
- Q => \s_datao_fmc2[63]\(11),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(12),
- Q => \s_datao_fmc2[63]\(12),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(13),
- Q => \s_datao_fmc2[63]\(13),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(14),
- Q => \s_datao_fmc2[63]\(14),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(15),
- Q => \s_datao_fmc2[63]\(15),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(16),
- Q => \s_datao_fmc2[63]\(16),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(17),
- Q => \s_datao_fmc2[63]\(17),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(18),
- Q => \s_datao_fmc2[63]\(18),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(19),
- Q => \s_datao_fmc2[63]\(19),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(1),
- Q => \s_datao_fmc2[63]\(1),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(20),
- Q => \s_datao_fmc2[63]\(20),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(21),
- Q => \s_datao_fmc2[63]\(21),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(22),
- Q => \s_datao_fmc2[63]\(22),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(23),
- Q => \s_datao_fmc2[63]\(23),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(2),
- Q => \s_datao_fmc2[63]\(2),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(3),
- Q => \s_datao_fmc2[63]\(3),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(4),
- Q => \s_datao_fmc2[63]\(4),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(5),
- Q => \s_datao_fmc2[63]\(5),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(6),
- Q => \s_datao_fmc2[63]\(6),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(7),
- Q => \s_datao_fmc2[63]\(7),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(8),
- Q => \s_datao_fmc2[63]\(8),
- R => '0'
- );
-\fmc_03287_channels[15].gen_chs.data_o_reg[63][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_11\,
- D => \s_cmp_lengths[15]_15\(9),
- Q => \s_datao_fmc2[63]\(9),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(16),
- IB => \FMC2_LA_N_b[32]\(16),
- O => s_comparators_i_16
- );
-\fmc_03287_channels[16].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_7
- port map (
- D(0) => \^s_count_reg\(8),
- E(0) => \cmp_lengthCounter/RSTP_13\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_12\(4 downto 0),
- \fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\(23 downto 0) => \s_cmp_lengths[16]_16\(23 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc2[0]\(16),
- s_comparators_i_16 => s_comparators_i_16,
- \s_debounce_reg[1]\ => \s_buff2_i_1__15_n_0\
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(0),
- Q => \s_datao_fmc2[64]\(0),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(10),
- Q => \s_datao_fmc2[64]\(10),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(11),
- Q => \s_datao_fmc2[64]\(11),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(12),
- Q => \s_datao_fmc2[64]\(12),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(13),
- Q => \s_datao_fmc2[64]\(13),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(14),
- Q => \s_datao_fmc2[64]\(14),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(15),
- Q => \s_datao_fmc2[64]\(15),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(16),
- Q => \s_datao_fmc2[64]\(16),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(17),
- Q => \s_datao_fmc2[64]\(17),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(18),
- Q => \s_datao_fmc2[64]\(18),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(19),
- Q => \s_datao_fmc2[64]\(19),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(1),
- Q => \s_datao_fmc2[64]\(1),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(20),
- Q => \s_datao_fmc2[64]\(20),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(21),
- Q => \s_datao_fmc2[64]\(21),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(22),
- Q => \s_datao_fmc2[64]\(22),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(23),
- Q => \s_datao_fmc2[64]\(23),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(2),
- Q => \s_datao_fmc2[64]\(2),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(3),
- Q => \s_datao_fmc2[64]\(3),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(4),
- Q => \s_datao_fmc2[64]\(4),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(5),
- Q => \s_datao_fmc2[64]\(5),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(6),
- Q => \s_datao_fmc2[64]\(6),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(7),
- Q => \s_datao_fmc2[64]\(7),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(8),
- Q => \s_datao_fmc2[64]\(8),
- R => '0'
- );
-\fmc_03287_channels[16].gen_chs.data_o_reg[64][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_13\,
- D => \s_cmp_lengths[16]_16\(9),
- Q => \s_datao_fmc2[64]\(9),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(17),
- IB => \FMC2_LA_N_b[32]\(17),
- O => s_comparators_i_17
- );
-\fmc_03287_channels[17].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_8
- port map (
- D(0) => \^s_count_reg\(9),
- E(0) => \cmp_lengthCounter/RSTP_15\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_14\(4 downto 0),
- \fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\(23 downto 0) => \s_cmp_lengths[17]_17\(23 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc2[0]\(17),
- s_comparators_i_17 => s_comparators_i_17,
- \s_debounce_reg[1]\ => \s_buff2_i_1__16_n_0\
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(0),
- Q => \s_datao_fmc2[65]\(0),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(10),
- Q => \s_datao_fmc2[65]\(10),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(11),
- Q => \s_datao_fmc2[65]\(11),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(12),
- Q => \s_datao_fmc2[65]\(12),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(13),
- Q => \s_datao_fmc2[65]\(13),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(14),
- Q => \s_datao_fmc2[65]\(14),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(15),
- Q => \s_datao_fmc2[65]\(15),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(16),
- Q => \s_datao_fmc2[65]\(16),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(17),
- Q => \s_datao_fmc2[65]\(17),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(18),
- Q => \s_datao_fmc2[65]\(18),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(19),
- Q => \s_datao_fmc2[65]\(19),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(1),
- Q => \s_datao_fmc2[65]\(1),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(20),
- Q => \s_datao_fmc2[65]\(20),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(21),
- Q => \s_datao_fmc2[65]\(21),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(22),
- Q => \s_datao_fmc2[65]\(22),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(23),
- Q => \s_datao_fmc2[65]\(23),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(2),
- Q => \s_datao_fmc2[65]\(2),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(3),
- Q => \s_datao_fmc2[65]\(3),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(4),
- Q => \s_datao_fmc2[65]\(4),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(5),
- Q => \s_datao_fmc2[65]\(5),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(6),
- Q => \s_datao_fmc2[65]\(6),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(7),
- Q => \s_datao_fmc2[65]\(7),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(8),
- Q => \s_datao_fmc2[65]\(8),
- R => '0'
- );
-\fmc_03287_channels[17].gen_chs.data_o_reg[65][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_15\,
- D => \s_cmp_lengths[17]_17\(9),
- Q => \s_datao_fmc2[65]\(9),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(18),
- IB => \FMC2_LA_N_b[32]\(18),
- O => s_comparators_i_18
- );
-\fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_9
- port map (
- D(0) => \^s_count_reg\(10),
- E(0) => \cmp_lengthCounter/RSTP_17\,
- Q(1 downto 0) => v_cmpled(19 downto 18),
- S(0) => \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_2\,
- \fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\(23 downto 0) => \s_cmp_lengths[18]_18\(23 downto 0),
- intr_o_reg(0) => \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_3\,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_16\(4 downto 0),
- s_buff2_reg_0(0) => \^s_datao_fmc2[0]\(19),
- s_buff3_reg(0) => \^s_datao_fmc2[0]\(18),
- s_comparators_i_18 => s_comparators_i_18,
- \s_debounce_reg[1]\ => \s_buff2_i_1__17_n_0\,
- s_pulseLed_reg_0(0) => \^s_count_reg\(11),
- \v_cmp_reg[19]\(1 downto 0) => v_cmp(19 downto 18)
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(0),
- Q => \s_datao_fmc2[66]\(0),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(10),
- Q => \s_datao_fmc2[66]\(10),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(11),
- Q => \s_datao_fmc2[66]\(11),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(12),
- Q => \s_datao_fmc2[66]\(12),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(13),
- Q => \s_datao_fmc2[66]\(13),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(14),
- Q => \s_datao_fmc2[66]\(14),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(15),
- Q => \s_datao_fmc2[66]\(15),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(16),
- Q => \s_datao_fmc2[66]\(16),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(17),
- Q => \s_datao_fmc2[66]\(17),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(18),
- Q => \s_datao_fmc2[66]\(18),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(19),
- Q => \s_datao_fmc2[66]\(19),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(1),
- Q => \s_datao_fmc2[66]\(1),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(20),
- Q => \s_datao_fmc2[66]\(20),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(21),
- Q => \s_datao_fmc2[66]\(21),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(22),
- Q => \s_datao_fmc2[66]\(22),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(23),
- Q => \s_datao_fmc2[66]\(23),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(2),
- Q => \s_datao_fmc2[66]\(2),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(3),
- Q => \s_datao_fmc2[66]\(3),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(4),
- Q => \s_datao_fmc2[66]\(4),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(5),
- Q => \s_datao_fmc2[66]\(5),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(6),
- Q => \s_datao_fmc2[66]\(6),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(7),
- Q => \s_datao_fmc2[66]\(7),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(8),
- Q => \s_datao_fmc2[66]\(8),
- R => '0'
- );
-\fmc_03287_channels[18].gen_chs.data_o_reg[66][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_17\,
- D => \s_cmp_lengths[18]_18\(9),
- Q => \s_datao_fmc2[66]\(9),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(19),
- IB => \FMC2_LA_N_b[32]\(19),
- O => s_comparators_i_19
- );
-\fmc_03287_channels[19].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_10
- port map (
- D(0) => \^s_count_reg\(11),
- E(0) => \cmp_lengthCounter/RSTP_19\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_18\(4 downto 0),
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\(23 downto 0) => \s_cmp_lengths[19]_19\(23 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc2[0]\(19),
- s_comparators_i_19 => s_comparators_i_19,
- \s_debounce_reg[1]\ => \s_buff2_i_1__18_n_0\
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(0),
- Q => \s_datao_fmc2[67]\(0),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(10),
- Q => \s_datao_fmc2[67]\(10),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(11),
- Q => \s_datao_fmc2[67]\(11),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(12),
- Q => \s_datao_fmc2[67]\(12),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(13),
- Q => \s_datao_fmc2[67]\(13),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(14),
- Q => \s_datao_fmc2[67]\(14),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(15),
- Q => \s_datao_fmc2[67]\(15),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(16),
- Q => \s_datao_fmc2[67]\(16),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(17),
- Q => \s_datao_fmc2[67]\(17),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(18),
- Q => \s_datao_fmc2[67]\(18),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(19),
- Q => \s_datao_fmc2[67]\(19),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(1),
- Q => \s_datao_fmc2[67]\(1),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(20),
- Q => \s_datao_fmc2[67]\(20),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(21),
- Q => \s_datao_fmc2[67]\(21),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(22),
- Q => \s_datao_fmc2[67]\(22),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(23),
- Q => \s_datao_fmc2[67]\(23),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(2),
- Q => \s_datao_fmc2[67]\(2),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(3),
- Q => \s_datao_fmc2[67]\(3),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(4),
- Q => \s_datao_fmc2[67]\(4),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(5),
- Q => \s_datao_fmc2[67]\(5),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(6),
- Q => \s_datao_fmc2[67]\(6),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(7),
- Q => \s_datao_fmc2[67]\(7),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(8),
- Q => \s_datao_fmc2[67]\(8),
- R => '0'
- );
-\fmc_03287_channels[19].gen_chs.data_o_reg[67][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_19\,
- D => \s_cmp_lengths[19]_19\(9),
- Q => \s_datao_fmc2[67]\(9),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(1),
- IB => \FMC2_LA_N_b[32]\(1),
- O => s_comparators_i_1
- );
-\fmc_03287_channels[1].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_11
- port map (
- D(0) => \^s_datao_fmc2[0]\(1),
- E(0) => \cmp_lengthCounter/RSTP_21\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_20\(4 downto 0),
- \fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\(23 downto 0) => \s_cmp_lengths[1]_1\(23 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_comparators_i_1 => s_comparators_i_1,
- s_count_reg(0) => \s_datao_fmc2[4]\(1),
- \s_debounce_reg[1]\ => \s_buff2_i_1__0_n_0\
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(0),
- Q => \s_datao_fmc2[49]\(0),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(10),
- Q => \s_datao_fmc2[49]\(10),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(11),
- Q => \s_datao_fmc2[49]\(11),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(12),
- Q => \s_datao_fmc2[49]\(12),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(13),
- Q => \s_datao_fmc2[49]\(13),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(14),
- Q => \s_datao_fmc2[49]\(14),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(15),
- Q => \s_datao_fmc2[49]\(15),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(16),
- Q => \s_datao_fmc2[49]\(16),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(17),
- Q => \s_datao_fmc2[49]\(17),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(18),
- Q => \s_datao_fmc2[49]\(18),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(19),
- Q => \s_datao_fmc2[49]\(19),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(1),
- Q => \s_datao_fmc2[49]\(1),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(20),
- Q => \s_datao_fmc2[49]\(20),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(21),
- Q => \s_datao_fmc2[49]\(21),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(22),
- Q => \s_datao_fmc2[49]\(22),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(23),
- Q => \s_datao_fmc2[49]\(23),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(2),
- Q => \s_datao_fmc2[49]\(2),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(3),
- Q => \s_datao_fmc2[49]\(3),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(4),
- Q => \s_datao_fmc2[49]\(4),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(5),
- Q => \s_datao_fmc2[49]\(5),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(6),
- Q => \s_datao_fmc2[49]\(6),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(7),
- Q => \s_datao_fmc2[49]\(7),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(8),
- Q => \s_datao_fmc2[49]\(8),
- R => '0'
- );
-\fmc_03287_channels[1].gen_chs.data_o_reg[49][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_21\,
- D => \s_cmp_lengths[1]_1\(9),
- Q => \s_datao_fmc2[49]\(9),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(2),
- IB => \FMC2_LA_N_b[32]\(2),
- O => s_comparators_i_2
- );
-\fmc_03287_channels[2].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_12
- port map (
- D(0) => \^s_datao_fmc2[0]\(2),
- E(0) => \cmp_lengthCounter/RSTP_23\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_22\(4 downto 0),
- \fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\(23 downto 0) => \s_cmp_lengths[2]_2\(23 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_comparators_i_2 => s_comparators_i_2,
- s_count_reg(0) => \s_datao_fmc2[4]\(2),
- \s_debounce_reg[1]\ => \s_buff2_i_1__1_n_0\
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(0),
- Q => \s_datao_fmc2[50]\(0),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(10),
- Q => \s_datao_fmc2[50]\(10),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(11),
- Q => \s_datao_fmc2[50]\(11),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(12),
- Q => \s_datao_fmc2[50]\(12),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(13),
- Q => \s_datao_fmc2[50]\(13),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(14),
- Q => \s_datao_fmc2[50]\(14),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(15),
- Q => \s_datao_fmc2[50]\(15),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(16),
- Q => \s_datao_fmc2[50]\(16),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(17),
- Q => \s_datao_fmc2[50]\(17),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(18),
- Q => \s_datao_fmc2[50]\(18),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(19),
- Q => \s_datao_fmc2[50]\(19),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(1),
- Q => \s_datao_fmc2[50]\(1),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(20),
- Q => \s_datao_fmc2[50]\(20),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(21),
- Q => \s_datao_fmc2[50]\(21),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(22),
- Q => \s_datao_fmc2[50]\(22),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(23),
- Q => \s_datao_fmc2[50]\(23),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(2),
- Q => \s_datao_fmc2[50]\(2),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(3),
- Q => \s_datao_fmc2[50]\(3),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(4),
- Q => \s_datao_fmc2[50]\(4),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(5),
- Q => \s_datao_fmc2[50]\(5),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(6),
- Q => \s_datao_fmc2[50]\(6),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(7),
- Q => \s_datao_fmc2[50]\(7),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(8),
- Q => \s_datao_fmc2[50]\(8),
- R => '0'
- );
-\fmc_03287_channels[2].gen_chs.data_o_reg[50][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_23\,
- D => \s_cmp_lengths[2]_2\(9),
- Q => \s_datao_fmc2[50]\(9),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(3),
- IB => \FMC2_LA_N_b[32]\(3),
- O => s_comparators_i_3
- );
-\fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_13
- port map (
- D(0) => \^s_datao_fmc2[0]\(3),
- E(0) => \cmp_lengthCounter/RSTP_25\,
- Q(2 downto 0) => v_cmpled(5 downto 3),
- S(0) => \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_2\,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\(23 downto 0) => \s_cmp_lengths[3]_3\(23 downto 0),
- intr_o_reg(0) => \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_3\,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_24\(4 downto 0),
- s_buff2_reg_0(1 downto 0) => \^s_datao_fmc2[0]\(5 downto 4),
- s_comparators_i_3 => s_comparators_i_3,
- \s_datao_fmc2[4]\(0) => \s_datao_fmc2[4]\(3),
- \s_debounce_reg[1]\ => \s_buff2_i_1__2_n_0\,
- s_pulseLed_reg_0(1 downto 0) => \s_datao_fmc2[4]\(5 downto 4),
- \v_cmp_reg[5]\(2 downto 0) => v_cmp(5 downto 3)
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(0),
- Q => \s_datao_fmc2[51]\(0),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(10),
- Q => \s_datao_fmc2[51]\(10),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(11),
- Q => \s_datao_fmc2[51]\(11),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(12),
- Q => \s_datao_fmc2[51]\(12),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(13),
- Q => \s_datao_fmc2[51]\(13),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(14),
- Q => \s_datao_fmc2[51]\(14),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(15),
- Q => \s_datao_fmc2[51]\(15),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(16),
- Q => \s_datao_fmc2[51]\(16),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(17),
- Q => \s_datao_fmc2[51]\(17),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(18),
- Q => \s_datao_fmc2[51]\(18),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(19),
- Q => \s_datao_fmc2[51]\(19),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(1),
- Q => \s_datao_fmc2[51]\(1),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(20),
- Q => \s_datao_fmc2[51]\(20),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(21),
- Q => \s_datao_fmc2[51]\(21),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(22),
- Q => \s_datao_fmc2[51]\(22),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(23),
- Q => \s_datao_fmc2[51]\(23),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(2),
- Q => \s_datao_fmc2[51]\(2),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(3),
- Q => \s_datao_fmc2[51]\(3),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(4),
- Q => \s_datao_fmc2[51]\(4),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(5),
- Q => \s_datao_fmc2[51]\(5),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(6),
- Q => \s_datao_fmc2[51]\(6),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(7),
- Q => \s_datao_fmc2[51]\(7),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(8),
- Q => \s_datao_fmc2[51]\(8),
- R => '0'
- );
-\fmc_03287_channels[3].gen_chs.data_o_reg[51][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_25\,
- D => \s_cmp_lengths[3]_3\(9),
- Q => \s_datao_fmc2[51]\(9),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(4),
- IB => \FMC2_LA_N_b[32]\(4),
- O => s_comparators_i_4
- );
-\fmc_03287_channels[4].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_14
- port map (
- D(0) => \^s_datao_fmc2[0]\(4),
- E(0) => \cmp_lengthCounter/RSTP_27\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_26\(4 downto 0),
- \fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\(23 downto 0) => \s_cmp_lengths[4]_4\(23 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_comparators_i_4 => s_comparators_i_4,
- s_count_reg(0) => \s_datao_fmc2[4]\(4),
- \s_debounce_reg[1]\ => \s_buff2_i_1__3_n_0\
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(0),
- Q => \s_datao_fmc2[52]\(0),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(10),
- Q => \s_datao_fmc2[52]\(10),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(11),
- Q => \s_datao_fmc2[52]\(11),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(12),
- Q => \s_datao_fmc2[52]\(12),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(13),
- Q => \s_datao_fmc2[52]\(13),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(14),
- Q => \s_datao_fmc2[52]\(14),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(15),
- Q => \s_datao_fmc2[52]\(15),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(16),
- Q => \s_datao_fmc2[52]\(16),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(17),
- Q => \s_datao_fmc2[52]\(17),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(18),
- Q => \s_datao_fmc2[52]\(18),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(19),
- Q => \s_datao_fmc2[52]\(19),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(1),
- Q => \s_datao_fmc2[52]\(1),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(20),
- Q => \s_datao_fmc2[52]\(20),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(21),
- Q => \s_datao_fmc2[52]\(21),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(22),
- Q => \s_datao_fmc2[52]\(22),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(23),
- Q => \s_datao_fmc2[52]\(23),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(2),
- Q => \s_datao_fmc2[52]\(2),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(3),
- Q => \s_datao_fmc2[52]\(3),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(4),
- Q => \s_datao_fmc2[52]\(4),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(5),
- Q => \s_datao_fmc2[52]\(5),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(6),
- Q => \s_datao_fmc2[52]\(6),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(7),
- Q => \s_datao_fmc2[52]\(7),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(8),
- Q => \s_datao_fmc2[52]\(8),
- R => '0'
- );
-\fmc_03287_channels[4].gen_chs.data_o_reg[52][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_27\,
- D => \s_cmp_lengths[4]_4\(9),
- Q => \s_datao_fmc2[52]\(9),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(5),
- IB => \FMC2_LA_N_b[32]\(5),
- O => s_comparators_i_5
- );
-\fmc_03287_channels[5].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_15
- port map (
- D(0) => \^s_datao_fmc2[0]\(5),
- E(0) => \cmp_lengthCounter/RSTP_29\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_28\(4 downto 0),
- \fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\(23 downto 0) => \s_cmp_lengths[5]_5\(23 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_comparators_i_5 => s_comparators_i_5,
- s_count_reg(0) => \s_datao_fmc2[4]\(5),
- \s_debounce_reg[1]\ => \s_buff2_i_1__4_n_0\
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(0),
- Q => \s_datao_fmc2[53]\(0),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(10),
- Q => \s_datao_fmc2[53]\(10),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(11),
- Q => \s_datao_fmc2[53]\(11),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(12),
- Q => \s_datao_fmc2[53]\(12),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(13),
- Q => \s_datao_fmc2[53]\(13),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(14),
- Q => \s_datao_fmc2[53]\(14),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(15),
- Q => \s_datao_fmc2[53]\(15),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(16),
- Q => \s_datao_fmc2[53]\(16),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(17),
- Q => \s_datao_fmc2[53]\(17),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(18),
- Q => \s_datao_fmc2[53]\(18),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(19),
- Q => \s_datao_fmc2[53]\(19),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(1),
- Q => \s_datao_fmc2[53]\(1),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(20),
- Q => \s_datao_fmc2[53]\(20),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(21),
- Q => \s_datao_fmc2[53]\(21),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(22),
- Q => \s_datao_fmc2[53]\(22),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(23),
- Q => \s_datao_fmc2[53]\(23),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(2),
- Q => \s_datao_fmc2[53]\(2),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(3),
- Q => \s_datao_fmc2[53]\(3),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(4),
- Q => \s_datao_fmc2[53]\(4),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(5),
- Q => \s_datao_fmc2[53]\(5),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(6),
- Q => \s_datao_fmc2[53]\(6),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(7),
- Q => \s_datao_fmc2[53]\(7),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(8),
- Q => \s_datao_fmc2[53]\(8),
- R => '0'
- );
-\fmc_03287_channels[5].gen_chs.data_o_reg[53][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_29\,
- D => \s_cmp_lengths[5]_5\(9),
- Q => \s_datao_fmc2[53]\(9),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(6),
- IB => \FMC2_LA_N_b[32]\(6),
- O => s_comparators_i_6
- );
-\fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_16
- port map (
- D(0) => \^s_datao_fmc2[0]\(6),
- E(0) => \cmp_lengthCounter/RSTP_31\,
- Q(2 downto 0) => v_cmpled(8 downto 6),
- S(0) => \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_2\,
- \fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\(23 downto 0) => \s_cmp_lengths[6]_6\(23 downto 0),
- intr_o_reg(0) => \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_3\,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_30\(4 downto 0),
- s_buff2_reg_0(1 downto 0) => \^s_datao_fmc2[0]\(8 downto 7),
- s_comparators_i_6 => s_comparators_i_6,
- \s_datao_fmc2[4]\(0) => \s_datao_fmc2[4]\(6),
- \s_debounce_reg[1]\ => \s_buff2_i_1__5_n_0\,
- s_pulseLed_reg_0(1) => \^s_count_reg\(0),
- s_pulseLed_reg_0(0) => \s_datao_fmc2[4]\(7),
- \v_cmp_reg[8]\(2 downto 0) => v_cmp(8 downto 6)
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(0),
- Q => \s_datao_fmc2[54]\(0),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(10),
- Q => \s_datao_fmc2[54]\(10),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(11),
- Q => \s_datao_fmc2[54]\(11),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(12),
- Q => \s_datao_fmc2[54]\(12),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(13),
- Q => \s_datao_fmc2[54]\(13),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(14),
- Q => \s_datao_fmc2[54]\(14),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(15),
- Q => \s_datao_fmc2[54]\(15),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(16),
- Q => \s_datao_fmc2[54]\(16),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(17),
- Q => \s_datao_fmc2[54]\(17),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(18),
- Q => \s_datao_fmc2[54]\(18),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(19),
- Q => \s_datao_fmc2[54]\(19),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(1),
- Q => \s_datao_fmc2[54]\(1),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(20),
- Q => \s_datao_fmc2[54]\(20),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(21),
- Q => \s_datao_fmc2[54]\(21),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(22),
- Q => \s_datao_fmc2[54]\(22),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(23),
- Q => \s_datao_fmc2[54]\(23),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(2),
- Q => \s_datao_fmc2[54]\(2),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(3),
- Q => \s_datao_fmc2[54]\(3),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(4),
- Q => \s_datao_fmc2[54]\(4),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(5),
- Q => \s_datao_fmc2[54]\(5),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(6),
- Q => \s_datao_fmc2[54]\(6),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(7),
- Q => \s_datao_fmc2[54]\(7),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(8),
- Q => \s_datao_fmc2[54]\(8),
- R => '0'
- );
-\fmc_03287_channels[6].gen_chs.data_o_reg[54][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_31\,
- D => \s_cmp_lengths[6]_6\(9),
- Q => \s_datao_fmc2[54]\(9),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(7),
- IB => \FMC2_LA_N_b[32]\(7),
- O => s_comparators_i_7
- );
-\fmc_03287_channels[7].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_17
- port map (
- D(0) => \^s_datao_fmc2[0]\(7),
- E(0) => \cmp_lengthCounter/RSTP_33\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_32\(4 downto 0),
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\(23 downto 0) => \s_cmp_lengths[7]_7\(23 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_comparators_i_7 => s_comparators_i_7,
- s_count_reg(0) => \s_datao_fmc2[4]\(7),
- \s_debounce_reg[1]\ => \s_buff2_i_1__6_n_0\
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(0),
- Q => \s_datao_fmc2[55]\(0),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(10),
- Q => \s_datao_fmc2[55]\(10),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(11),
- Q => \s_datao_fmc2[55]\(11),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(12),
- Q => \s_datao_fmc2[55]\(12),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(13),
- Q => \s_datao_fmc2[55]\(13),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(14),
- Q => \s_datao_fmc2[55]\(14),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(15),
- Q => \s_datao_fmc2[55]\(15),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(16),
- Q => \s_datao_fmc2[55]\(16),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(17),
- Q => \s_datao_fmc2[55]\(17),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(18),
- Q => \s_datao_fmc2[55]\(18),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(19),
- Q => \s_datao_fmc2[55]\(19),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(1),
- Q => \s_datao_fmc2[55]\(1),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(20),
- Q => \s_datao_fmc2[55]\(20),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(21),
- Q => \s_datao_fmc2[55]\(21),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(22),
- Q => \s_datao_fmc2[55]\(22),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(23),
- Q => \s_datao_fmc2[55]\(23),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(2),
- Q => \s_datao_fmc2[55]\(2),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(3),
- Q => \s_datao_fmc2[55]\(3),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(4),
- Q => \s_datao_fmc2[55]\(4),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(5),
- Q => \s_datao_fmc2[55]\(5),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(6),
- Q => \s_datao_fmc2[55]\(6),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(7),
- Q => \s_datao_fmc2[55]\(7),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(8),
- Q => \s_datao_fmc2[55]\(8),
- R => '0'
- );
-\fmc_03287_channels[7].gen_chs.data_o_reg[55][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_33\,
- D => \s_cmp_lengths[7]_7\(9),
- Q => \s_datao_fmc2[55]\(9),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(8),
- IB => \FMC2_LA_N_b[32]\(8),
- O => s_comparators_i_8
- );
-\fmc_03287_channels[8].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_18
- port map (
- D(0) => \^s_count_reg\(0),
- E(0) => \cmp_lengthCounter/RSTP_35\,
- Q(4 downto 0) => \cmp_pulseSync/s_debounce_34\(4 downto 0),
- \fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\(23 downto 0) => \s_cmp_lengths[8]_8\(23 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff3_reg(0) => \^s_datao_fmc2[0]\(8),
- s_comparators_i_8 => s_comparators_i_8,
- \s_debounce_reg[1]\ => \s_buff2_i_1__7_n_0\
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(0),
- Q => \s_datao_fmc2[56]\(0),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(10),
- Q => \s_datao_fmc2[56]\(10),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(11),
- Q => \s_datao_fmc2[56]\(11),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(12),
- Q => \s_datao_fmc2[56]\(12),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(13),
- Q => \s_datao_fmc2[56]\(13),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(14),
- Q => \s_datao_fmc2[56]\(14),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(15),
- Q => \s_datao_fmc2[56]\(15),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(16),
- Q => \s_datao_fmc2[56]\(16),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(17),
- Q => \s_datao_fmc2[56]\(17),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(18),
- Q => \s_datao_fmc2[56]\(18),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(19),
- Q => \s_datao_fmc2[56]\(19),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(1),
- Q => \s_datao_fmc2[56]\(1),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(20),
- Q => \s_datao_fmc2[56]\(20),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(21),
- Q => \s_datao_fmc2[56]\(21),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(22),
- Q => \s_datao_fmc2[56]\(22),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(23),
- Q => \s_datao_fmc2[56]\(23),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(2),
- Q => \s_datao_fmc2[56]\(2),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(3),
- Q => \s_datao_fmc2[56]\(3),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(4),
- Q => \s_datao_fmc2[56]\(4),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(5),
- Q => \s_datao_fmc2[56]\(5),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(6),
- Q => \s_datao_fmc2[56]\(6),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(7),
- Q => \s_datao_fmc2[56]\(7),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(8),
- Q => \s_datao_fmc2[56]\(8),
- R => '0'
- );
-\fmc_03287_channels[8].gen_chs.data_o_reg[56][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_35\,
- D => \s_cmp_lengths[8]_8\(9),
- Q => \s_datao_fmc2[56]\(9),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.cmp_IBUFDS_fmc\: unisim.vcomponents.IBUFDS
- generic map(
- DQS_BIAS => "FALSE",
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => \FMC2_LA_P_b[32]\(9),
- IB => \FMC2_LA_N_b[32]\(9),
- O => s_comparators_i_9
- );
-\fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_19
- port map (
- CO(0) => intr_o0,
- D(0) => \^s_count_reg\(1),
- E(0) => \cmp_lengthCounter/RSTP_37\,
- Q(2 downto 0) => v_cmpled(11 downto 9),
- S(2) => \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_2\,
- S(1) => \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_2\,
- S(0) => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_3\,
- \fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\(23 downto 0) => \s_cmp_lengths[9]_9\(23 downto 0),
- intr_led_o_reg => \fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure_n_2\,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_36\(4 downto 0),
- s_buff2_reg_0(1 downto 0) => \^s_datao_fmc2[0]\(11 downto 10),
- s_buff3_reg(0) => \^s_datao_fmc2[0]\(9),
- s_comparators_i_9 => s_comparators_i_9,
- \s_debounce_reg[1]\ => \s_buff2_i_1__8_n_0\,
- s_pulseLed_reg_0 => \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_3\,
- s_pulseLed_reg_1(1 downto 0) => \^s_count_reg\(3 downto 2),
- \v_cmp_reg[11]\(2 downto 0) => v_cmp(11 downto 9),
- \v_cmp_reg[18]\(2) => \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_3\,
- \v_cmp_reg[18]\(1) => \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_3\,
- \v_cmp_reg[18]\(0) => \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_3\,
- \v_cmp_reg[6]\(2) => \fmc_03287_channels[6].gen_chs.cmp_ch_pulseMeasure_n_3\,
- \v_cmp_reg[6]\(1) => \fmc_03287_channels[3].gen_chs.cmp_ch_pulseMeasure_n_3\,
- \v_cmp_reg[6]\(0) => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_4\,
- \v_cmpled_reg[18]\(2) => \fmc_03287_channels[18].gen_chs.cmp_ch_pulseMeasure_n_2\,
- \v_cmpled_reg[18]\(1) => \fmc_03287_channels[15].gen_chs.cmp_ch_pulseMeasure_n_2\,
- \v_cmpled_reg[18]\(0) => \fmc_03287_channels[12].gen_chs.cmp_ch_pulseMeasure_n_2\
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(0),
- Q => \s_datao_fmc2[57]\(0),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(10),
- Q => \s_datao_fmc2[57]\(10),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(11),
- Q => \s_datao_fmc2[57]\(11),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(12),
- Q => \s_datao_fmc2[57]\(12),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(13),
- Q => \s_datao_fmc2[57]\(13),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(14),
- Q => \s_datao_fmc2[57]\(14),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(15),
- Q => \s_datao_fmc2[57]\(15),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(16),
- Q => \s_datao_fmc2[57]\(16),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(17),
- Q => \s_datao_fmc2[57]\(17),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(18),
- Q => \s_datao_fmc2[57]\(18),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(19),
- Q => \s_datao_fmc2[57]\(19),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(1),
- Q => \s_datao_fmc2[57]\(1),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][20]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(20),
- Q => \s_datao_fmc2[57]\(20),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][21]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(21),
- Q => \s_datao_fmc2[57]\(21),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][22]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(22),
- Q => \s_datao_fmc2[57]\(22),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][23]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(23),
- Q => \s_datao_fmc2[57]\(23),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(2),
- Q => \s_datao_fmc2[57]\(2),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(3),
- Q => \s_datao_fmc2[57]\(3),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(4),
- Q => \s_datao_fmc2[57]\(4),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(5),
- Q => \s_datao_fmc2[57]\(5),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(6),
- Q => \s_datao_fmc2[57]\(6),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(7),
- Q => \s_datao_fmc2[57]\(7),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(8),
- Q => \s_datao_fmc2[57]\(8),
- R => '0'
- );
-\fmc_03287_channels[9].gen_chs.data_o_reg[57][9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => \cmp_lengthCounter/RSTP_37\,
- D => \s_cmp_lengths[9]_9\(9),
- Q => \s_datao_fmc2[57]\(9),
- R => '0'
- );
-\fmc_03287_obufds[0].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => D(0),
- O => \FMC2_LA_P_b[27]\(0),
- OB => \FMC2_LA_N_b[27]\(0)
- );
-\fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_20
- port map (
- D(0) => D(0),
- Q(0) => \s_datao_fmc2[6]\(0),
- \axi_araddr_reg[2]_rep__3\ => \axi_araddr_reg[2]_rep__3\,
- \axi_araddr_reg[3]_rep__3\ => \axi_araddr_reg[3]_rep__3\,
- \axi_rdata_reg[0]\ => \axi_rdata_reg[0]\,
- intr_led_o_reg => \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_3\,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_38\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_1\,
- \s_datao_fmc2[5]\(0) => \s_datao_fmc2[5]\(0),
- \s_debounce_reg[1]\ => \s_buff2_i_1__19_n_0\,
- s_pulseLed_reg_0(0) => \s_datao_fmc2[4]\(0),
- s_pulseLed_reg_1(1 downto 0) => \s_datao_fmc2[5]\(2 downto 1),
- \v_outleds_reg[2]\(2 downto 0) => v_outleds(2 downto 0)
- );
-\fmc_03287_obufds[1].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => D(1),
- O => \FMC2_LA_P_b[27]\(1),
- OB => \FMC2_LA_N_b[27]\(1)
- );
-\fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_21
- port map (
- D(0) => D(1),
- Q(0) => \s_datao_fmc2[6]\(1),
- \axi_araddr_reg[2]_rep__3\ => \axi_araddr_reg[2]_rep__3\,
- \axi_araddr_reg[3]_rep__3\ => \axi_araddr_reg[3]_rep__3\,
- \axi_rdata_reg[1]\ => \axi_rdata_reg[1]\,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_39\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure_n_1\,
- s_count_reg(0) => \s_datao_fmc2[5]\(1),
- \s_debounce_reg[1]\ => \s_buff2_i_1__20_n_0\,
- s_pulseLed_reg_0(0) => \s_datao_fmc2[4]\(1)
- );
-\fmc_03287_obufds[2].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => D(2),
- O => \FMC2_LA_P_b[27]\(2),
- OB => \FMC2_LA_N_b[27]\(2)
- );
-\fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_22
- port map (
- D(0) => D(2),
- Q(0) => \s_datao_fmc2[6]\(2),
- \axi_araddr_reg[2]_rep__3\ => \axi_araddr_reg[2]_rep__3\,
- \axi_araddr_reg[3]_rep__3\ => \axi_araddr_reg[3]_rep__3\,
- \axi_rdata_reg[2]\ => \axi_rdata_reg[2]\,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_40\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure_n_1\,
- s_count_reg(0) => \s_datao_fmc2[5]\(2),
- \s_debounce_reg[1]\ => \s_buff2_i_1__21_n_0\,
- s_pulseLed_reg_0(0) => \s_datao_fmc2[4]\(2)
- );
-\fmc_03287_obufds[3].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => D(3),
- O => \FMC2_LA_P_b[27]\(3),
- OB => \FMC2_LA_N_b[27]\(3)
- );
-\fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_23
- port map (
- D(0) => D(3),
- Q(0) => \s_datao_fmc2[6]\(3),
- \axi_araddr_reg[2]_rep__2\ => \axi_araddr_reg[2]_rep__2\,
- \axi_araddr_reg[3]_rep__2\ => \axi_araddr_reg[3]_rep__2\,
- \axi_rdata_reg[3]\ => \axi_rdata_reg[3]\,
- intr_led_o_reg => \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_3\,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_41\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_1\,
- \s_datao_fmc2[5]\(0) => \s_datao_fmc2[5]\(3),
- \s_debounce_reg[1]\ => \s_buff2_i_1__22_n_0\,
- s_pulseLed_reg_0(0) => \s_datao_fmc2[4]\(3),
- s_pulseLed_reg_1(1 downto 0) => \s_datao_fmc2[5]\(5 downto 4),
- \v_outleds_reg[5]\(2 downto 0) => v_outleds(5 downto 3)
- );
-\fmc_03287_obufds[4].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => s_diffouts_o(4),
- O => \FMC2_LA_P_b[27]\(4),
- OB => \FMC2_LA_N_b[27]\(4)
- );
-\fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_24
- port map (
- D(0) => \s_datao_fmc2[4]\(4),
- Q(0) => s_diffouts_o(4),
- \axi_araddr_reg[2]_rep__2\ => \axi_araddr_reg[2]_rep__2\,
- \axi_araddr_reg[3]_rep__2\ => \axi_araddr_reg[3]_rep__2\,
- \axi_rdata_reg[4]\ => \axi_rdata_reg[4]\,
- \data_o_reg[6][4]\(0) => \s_datao_fmc2[6]\(4),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_42\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure_n_1\,
- s_count_reg(0) => \s_datao_fmc2[5]\(4),
- \s_debounce_reg[1]\ => \s_buff2_i_1__23_n_0\
- );
-\fmc_03287_obufds[5].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => s_diffouts_o(5),
- O => \FMC2_LA_P_b[27]\(5),
- OB => \FMC2_LA_N_b[27]\(5)
- );
-\fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_25
- port map (
- D(0) => \s_datao_fmc2[4]\(5),
- Q(0) => s_diffouts_o(5),
- \axi_araddr_reg[2]_rep__2\ => \axi_araddr_reg[2]_rep__2\,
- \axi_araddr_reg[3]_rep__2\ => \axi_araddr_reg[3]_rep__2\,
- \axi_rdata_reg[5]\ => \axi_rdata_reg[5]\,
- \data_o_reg[6][5]\(0) => \s_datao_fmc2[6]\(5),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_43\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure_n_1\,
- s_count_reg(0) => \s_datao_fmc2[5]\(5),
- \s_debounce_reg[1]\ => \s_buff2_i_1__24_n_0\
- );
-\fmc_03287_obufds[6].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => s_diffouts_o(6),
- O => \FMC2_LA_P_b[27]\(6),
- OB => \FMC2_LA_N_b[27]\(6)
- );
-\fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_26
- port map (
- D(0) => \s_datao_fmc2[4]\(6),
- Q(0) => s_diffouts_o(6),
- \axi_araddr_reg[2]_rep__2\ => \axi_araddr_reg[2]_rep__2\,
- \axi_araddr_reg[3]_rep__2\ => \axi_araddr_reg[3]_rep__2\,
- \axi_rdata_reg[6]\ => \axi_rdata_reg[6]\,
- \data_o_reg[6][6]\(0) => \s_datao_fmc2[6]\(6),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_44\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure_n_1\,
- \s_datao_fmc2[5]\(0) => \s_datao_fmc2[5]\(6),
- \s_debounce_reg[1]\ => \s_buff2_i_1__25_n_0\
- );
-\fmc_03287_obufds[7].gen_outs.cmp_OBUFDS_fmc\: unisim.vcomponents.OBUFDS
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => s_diffouts_o(7),
- O => \FMC2_LA_P_b[27]\(7),
- OB => \FMC2_LA_N_b[27]\(7)
- );
-\fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure\: entity work.system_design_fasec_hwtest_0_0_pulseMeasure_27
- port map (
- D(0) => \s_datao_fmc2[4]\(7),
- Q(0) => s_diffouts_o(7),
- \axi_araddr_reg[2]_rep__2\ => \axi_araddr_reg[2]_rep__2\,
- \axi_araddr_reg[3]_rep__2\ => \axi_araddr_reg[3]_rep__2\,
- \axi_rdata_reg[7]\ => \axi_rdata_reg[7]\,
- \data_o_reg[6][7]\(0) => \s_datao_fmc2[6]\(7),
- intr_led_o_reg => \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_3\,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_buff2_reg(4 downto 0) => \cmp_pulseSync/s_debounce_45\(4 downto 0),
- s_buff3_reg => \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_1\,
- \s_datao_fmc2[5]\(0) => \s_datao_fmc2[5]\(7),
- \s_debounce_reg[1]\ => \s_buff2_i_1__26_n_0\,
- s_pulseLed_reg_0(0) => \s_datao_fmc2[5]\(6),
- \v_outleds_reg[0]\ => \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_3\,
- \v_outleds_reg[3]\ => \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_3\,
- \v_outleds_reg[7]\(1 downto 0) => v_outleds(7 downto 6)
- );
-\gen_spi.cmp_dac7716_spi\: entity work.system_design_fasec_hwtest_0_0_dac7716_spi
- port map (
- D(0) => spi_sdo_i,
- Q(11 downto 0) => Q(11 downto 0),
- \axi_rdata_reg[31]\(31 downto 0) => \axi_rdata_reg[31]\(31 downto 0),
- \dac_ch_o_reg[0][0]_0\ => \gen_spi.cmp_dac7716_spi_n_1\,
- \dac_ch_o_reg[0][0]_1\ => \gen_spi.cmp_dac7716_spi_n_2\,
- \data_rw_o_reg[100][11]\(11 downto 0) => \data_rw_o_reg[100][11]\(11 downto 0),
- \data_rw_o_reg[101][11]\(11 downto 0) => \data_rw_o_reg[101][11]\(11 downto 0),
- \data_rw_o_reg[102][11]\(11 downto 0) => \data_rw_o_reg[102][11]\(11 downto 0),
- \data_rw_o_reg[103][11]\(11 downto 0) => \data_rw_o_reg[103][11]\(11 downto 0),
- \data_rw_o_reg[79][2]\(1 downto 0) => \data_rw_o_reg[79][7]\(1 downto 0),
- \data_rw_o_reg[84][11]\(11 downto 0) => \data_rw_o_reg[84][11]\(11 downto 0),
- \data_rw_o_reg[84][11]_0\(0) => \data_rw_o_reg[84][11]_0\(0),
- \data_rw_o_reg[85][11]\(11 downto 0) => \data_rw_o_reg[85][11]\(11 downto 0),
- \data_rw_o_reg[85][11]_0\(0) => \data_rw_o_reg[85][11]_0\(0),
- \data_rw_o_reg[86][11]\(11 downto 0) => \data_rw_o_reg[86][11]\(11 downto 0),
- \data_rw_o_reg[86][11]_0\(0) => \data_rw_o_reg[86][11]_0\(0),
- \data_rw_o_reg[87][11]\(11 downto 0) => \data_rw_o_reg[87][11]\(11 downto 0),
- \data_rw_o_reg[87][11]_0\(0) => \data_rw_o_reg[87][11]_0\(0),
- \data_rw_o_reg[88][11]\(11 downto 0) => \data_rw_o_reg[88][11]\(11 downto 0),
- \data_rw_o_reg[88][11]_0\(0) => \data_rw_o_reg[88][11]_0\(0),
- \data_rw_o_reg[89][11]\(11 downto 0) => \data_rw_o_reg[89][11]\(11 downto 0),
- \data_rw_o_reg[89][11]_0\(0) => \data_rw_o_reg[89][11]_0\(0),
- \data_rw_o_reg[90][11]\(11 downto 0) => \data_rw_o_reg[90][11]\(11 downto 0),
- \data_rw_o_reg[90][11]_0\(0) => \data_rw_o_reg[90][11]_0\(0),
- \data_rw_o_reg[91][11]\(11 downto 0) => \data_rw_o_reg[91][11]\(11 downto 0),
- \data_rw_o_reg[91][11]_0\(0) => \data_rw_o_reg[91][11]_0\(0),
- \data_rw_o_reg[92][11]\(11 downto 0) => \data_rw_o_reg[92][11]\(11 downto 0),
- \data_rw_o_reg[93][11]\(11 downto 0) => \data_rw_o_reg[93][11]\(11 downto 0),
- \data_rw_o_reg[94][11]\(11 downto 0) => \data_rw_o_reg[94][11]\(11 downto 0),
- \data_rw_o_reg[95][11]\(11 downto 0) => \data_rw_o_reg[95][11]\(11 downto 0),
- \data_rw_o_reg[96][11]\(11 downto 0) => \data_rw_o_reg[96][11]\(11 downto 0),
- \data_rw_o_reg[97][11]\(11 downto 0) => \data_rw_o_reg[97][11]\(11 downto 0),
- \data_rw_o_reg[98][11]\(11 downto 0) => \data_rw_o_reg[98][11]\(11 downto 0),
- \data_rw_o_reg[99][11]\(11 downto 0) => \data_rw_o_reg[99][11]\(11 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- \s_counter_reg[2]\(0) => s_spi_sclk,
- s_spi_cs_n => s_spi_cs_n,
- s_spi_mosi => s_spi_mosi,
- s_start => s_start,
- s_start_reg_0 => s_start_i_1_n_0,
- \s_tx_data_reg[111]_0\(11 downto 0) => \s_tx_data_reg[111]\(11 downto 0),
- \s_tx_data_reg[15]_0\(11 downto 0) => \s_tx_data_reg[15]\(11 downto 0),
- \s_tx_data_reg[15]_1\(11 downto 0) => \s_tx_data_reg[15]_0\(11 downto 0),
- \s_tx_data_reg[39]_0\(11 downto 0) => \s_tx_data_reg[39]\(11 downto 0),
- \s_tx_data_reg[39]_1\(11 downto 0) => \s_tx_data_reg[39]_0\(11 downto 0),
- \s_tx_data_reg[39]_2\(11 downto 0) => \s_tx_data_reg[39]_1\(11 downto 0),
- \s_tx_data_reg[39]_3\(11 downto 0) => \s_tx_data_reg[39]_2\(11 downto 0)
- );
-\gen_spi.cmp_spi_cs_n_iobuf\: unisim.vcomponents.IOBUF
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => s_spi_cs_n,
- IO => FMC2_LA_N_b(1),
- O => \NLW_gen_spi.cmp_spi_cs_n_iobuf_O_UNCONNECTED\,
- T => '0'
- );
-\gen_spi.cmp_spi_miso_iobuf\: unisim.vcomponents.IOBUF
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => '0',
- IO => FMC2_LA_P_b(1),
- O => spi_sdo_i,
- T => '1'
- );
-\gen_spi.cmp_spi_mosi_iobuf\: unisim.vcomponents.IOBUF
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => s_spi_mosi,
- IO => FMC2_LA_N_b(0),
- O => \NLW_gen_spi.cmp_spi_mosi_iobuf_O_UNCONNECTED\,
- T => '0'
- );
-\gen_spi.cmp_spi_sclk_iobuf\: unisim.vcomponents.IOBUF
- generic map(
- IOSTANDARD => "DEFAULT"
- )
- port map (
- I => s_spi_sclk,
- IO => FMC2_LA_P_b(0),
- O => \NLW_gen_spi.cmp_spi_sclk_iobuf_O_UNCONNECTED\,
- T => '0'
- );
-intr_led_o_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \fmc_03287_channels[9].gen_chs.cmp_ch_pulseMeasure_n_2\,
- Q => fmc2_intr_led,
- R => '0'
- );
-intr_o_reg: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => intr_o0,
- Q => fmc2_intr,
- R => '0'
- );
-s_buff2_i_1: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce\(1),
- I1 => \cmp_pulseSync/s_debounce\(0),
- I2 => \cmp_pulseSync/s_debounce\(4),
- I3 => \cmp_pulseSync/s_debounce\(3),
- I4 => \cmp_pulseSync/s_debounce\(2),
- I5 => \^s_datao_fmc2[0]\(0),
- O => s_buff2_i_1_n_0
- );
-\s_buff2_i_1__0\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_20\(1),
- I1 => \cmp_pulseSync/s_debounce_20\(0),
- I2 => \cmp_pulseSync/s_debounce_20\(4),
- I3 => \cmp_pulseSync/s_debounce_20\(3),
- I4 => \cmp_pulseSync/s_debounce_20\(2),
- I5 => \^s_datao_fmc2[0]\(1),
- O => \s_buff2_i_1__0_n_0\
- );
-\s_buff2_i_1__1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_22\(1),
- I1 => \cmp_pulseSync/s_debounce_22\(0),
- I2 => \cmp_pulseSync/s_debounce_22\(4),
- I3 => \cmp_pulseSync/s_debounce_22\(3),
- I4 => \cmp_pulseSync/s_debounce_22\(2),
- I5 => \^s_datao_fmc2[0]\(2),
- O => \s_buff2_i_1__1_n_0\
- );
-\s_buff2_i_1__10\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_2\(1),
- I1 => \cmp_pulseSync/s_debounce_2\(0),
- I2 => \cmp_pulseSync/s_debounce_2\(4),
- I3 => \cmp_pulseSync/s_debounce_2\(3),
- I4 => \cmp_pulseSync/s_debounce_2\(2),
- I5 => \^s_datao_fmc2[0]\(11),
- O => \s_buff2_i_1__10_n_0\
- );
-\s_buff2_i_1__11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_4\(1),
- I1 => \cmp_pulseSync/s_debounce_4\(0),
- I2 => \cmp_pulseSync/s_debounce_4\(4),
- I3 => \cmp_pulseSync/s_debounce_4\(3),
- I4 => \cmp_pulseSync/s_debounce_4\(2),
- I5 => \^s_datao_fmc2[0]\(12),
- O => \s_buff2_i_1__11_n_0\
- );
-\s_buff2_i_1__12\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_6\(1),
- I1 => \cmp_pulseSync/s_debounce_6\(0),
- I2 => \cmp_pulseSync/s_debounce_6\(4),
- I3 => \cmp_pulseSync/s_debounce_6\(3),
- I4 => \cmp_pulseSync/s_debounce_6\(2),
- I5 => \^s_datao_fmc2[0]\(13),
- O => \s_buff2_i_1__12_n_0\
- );
-\s_buff2_i_1__13\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_8\(1),
- I1 => \cmp_pulseSync/s_debounce_8\(0),
- I2 => \cmp_pulseSync/s_debounce_8\(4),
- I3 => \cmp_pulseSync/s_debounce_8\(3),
- I4 => \cmp_pulseSync/s_debounce_8\(2),
- I5 => \^s_datao_fmc2[0]\(14),
- O => \s_buff2_i_1__13_n_0\
- );
-\s_buff2_i_1__14\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_10\(1),
- I1 => \cmp_pulseSync/s_debounce_10\(0),
- I2 => \cmp_pulseSync/s_debounce_10\(4),
- I3 => \cmp_pulseSync/s_debounce_10\(3),
- I4 => \cmp_pulseSync/s_debounce_10\(2),
- I5 => \^s_datao_fmc2[0]\(15),
- O => \s_buff2_i_1__14_n_0\
- );
-\s_buff2_i_1__15\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_12\(1),
- I1 => \cmp_pulseSync/s_debounce_12\(0),
- I2 => \cmp_pulseSync/s_debounce_12\(4),
- I3 => \cmp_pulseSync/s_debounce_12\(3),
- I4 => \cmp_pulseSync/s_debounce_12\(2),
- I5 => \^s_datao_fmc2[0]\(16),
- O => \s_buff2_i_1__15_n_0\
- );
-\s_buff2_i_1__16\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_14\(1),
- I1 => \cmp_pulseSync/s_debounce_14\(0),
- I2 => \cmp_pulseSync/s_debounce_14\(4),
- I3 => \cmp_pulseSync/s_debounce_14\(3),
- I4 => \cmp_pulseSync/s_debounce_14\(2),
- I5 => \^s_datao_fmc2[0]\(17),
- O => \s_buff2_i_1__16_n_0\
- );
-\s_buff2_i_1__17\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_16\(1),
- I1 => \cmp_pulseSync/s_debounce_16\(0),
- I2 => \cmp_pulseSync/s_debounce_16\(4),
- I3 => \cmp_pulseSync/s_debounce_16\(3),
- I4 => \cmp_pulseSync/s_debounce_16\(2),
- I5 => \^s_datao_fmc2[0]\(18),
- O => \s_buff2_i_1__17_n_0\
- );
-\s_buff2_i_1__18\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_18\(1),
- I1 => \cmp_pulseSync/s_debounce_18\(0),
- I2 => \cmp_pulseSync/s_debounce_18\(4),
- I3 => \cmp_pulseSync/s_debounce_18\(3),
- I4 => \cmp_pulseSync/s_debounce_18\(2),
- I5 => \^s_datao_fmc2[0]\(19),
- O => \s_buff2_i_1__18_n_0\
- );
-\s_buff2_i_1__19\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_38\(1),
- I1 => \cmp_pulseSync/s_debounce_38\(0),
- I2 => \cmp_pulseSync/s_debounce_38\(4),
- I3 => \cmp_pulseSync/s_debounce_38\(3),
- I4 => \cmp_pulseSync/s_debounce_38\(2),
- I5 => \fmc_03287_obufds[0].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__19_n_0\
- );
-\s_buff2_i_1__2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_24\(1),
- I1 => \cmp_pulseSync/s_debounce_24\(0),
- I2 => \cmp_pulseSync/s_debounce_24\(4),
- I3 => \cmp_pulseSync/s_debounce_24\(3),
- I4 => \cmp_pulseSync/s_debounce_24\(2),
- I5 => \^s_datao_fmc2[0]\(3),
- O => \s_buff2_i_1__2_n_0\
- );
-\s_buff2_i_1__20\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_39\(1),
- I1 => \cmp_pulseSync/s_debounce_39\(0),
- I2 => \cmp_pulseSync/s_debounce_39\(4),
- I3 => \cmp_pulseSync/s_debounce_39\(3),
- I4 => \cmp_pulseSync/s_debounce_39\(2),
- I5 => \fmc_03287_obufds[1].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__20_n_0\
- );
-\s_buff2_i_1__21\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_40\(1),
- I1 => \cmp_pulseSync/s_debounce_40\(0),
- I2 => \cmp_pulseSync/s_debounce_40\(4),
- I3 => \cmp_pulseSync/s_debounce_40\(3),
- I4 => \cmp_pulseSync/s_debounce_40\(2),
- I5 => \fmc_03287_obufds[2].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__21_n_0\
- );
-\s_buff2_i_1__22\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_41\(1),
- I1 => \cmp_pulseSync/s_debounce_41\(0),
- I2 => \cmp_pulseSync/s_debounce_41\(4),
- I3 => \cmp_pulseSync/s_debounce_41\(3),
- I4 => \cmp_pulseSync/s_debounce_41\(2),
- I5 => \fmc_03287_obufds[3].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__22_n_0\
- );
-\s_buff2_i_1__23\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_42\(1),
- I1 => \cmp_pulseSync/s_debounce_42\(0),
- I2 => \cmp_pulseSync/s_debounce_42\(4),
- I3 => \cmp_pulseSync/s_debounce_42\(3),
- I4 => \cmp_pulseSync/s_debounce_42\(2),
- I5 => \fmc_03287_obufds[4].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__23_n_0\
- );
-\s_buff2_i_1__24\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_43\(1),
- I1 => \cmp_pulseSync/s_debounce_43\(0),
- I2 => \cmp_pulseSync/s_debounce_43\(4),
- I3 => \cmp_pulseSync/s_debounce_43\(3),
- I4 => \cmp_pulseSync/s_debounce_43\(2),
- I5 => \fmc_03287_obufds[5].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__24_n_0\
- );
-\s_buff2_i_1__25\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_44\(1),
- I1 => \cmp_pulseSync/s_debounce_44\(0),
- I2 => \cmp_pulseSync/s_debounce_44\(4),
- I3 => \cmp_pulseSync/s_debounce_44\(3),
- I4 => \cmp_pulseSync/s_debounce_44\(2),
- I5 => \fmc_03287_obufds[6].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__25_n_0\
- );
-\s_buff2_i_1__26\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_45\(1),
- I1 => \cmp_pulseSync/s_debounce_45\(0),
- I2 => \cmp_pulseSync/s_debounce_45\(4),
- I3 => \cmp_pulseSync/s_debounce_45\(3),
- I4 => \cmp_pulseSync/s_debounce_45\(2),
- I5 => \fmc_03287_obufds[7].gen_outs.cmp_outs_pulseMeasure_n_1\,
- O => \s_buff2_i_1__26_n_0\
- );
-\s_buff2_i_1__3\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_26\(1),
- I1 => \cmp_pulseSync/s_debounce_26\(0),
- I2 => \cmp_pulseSync/s_debounce_26\(4),
- I3 => \cmp_pulseSync/s_debounce_26\(3),
- I4 => \cmp_pulseSync/s_debounce_26\(2),
- I5 => \^s_datao_fmc2[0]\(4),
- O => \s_buff2_i_1__3_n_0\
- );
-\s_buff2_i_1__4\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_28\(1),
- I1 => \cmp_pulseSync/s_debounce_28\(0),
- I2 => \cmp_pulseSync/s_debounce_28\(4),
- I3 => \cmp_pulseSync/s_debounce_28\(3),
- I4 => \cmp_pulseSync/s_debounce_28\(2),
- I5 => \^s_datao_fmc2[0]\(5),
- O => \s_buff2_i_1__4_n_0\
- );
-\s_buff2_i_1__5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_30\(1),
- I1 => \cmp_pulseSync/s_debounce_30\(0),
- I2 => \cmp_pulseSync/s_debounce_30\(4),
- I3 => \cmp_pulseSync/s_debounce_30\(3),
- I4 => \cmp_pulseSync/s_debounce_30\(2),
- I5 => \^s_datao_fmc2[0]\(6),
- O => \s_buff2_i_1__5_n_0\
- );
-\s_buff2_i_1__6\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_32\(1),
- I1 => \cmp_pulseSync/s_debounce_32\(0),
- I2 => \cmp_pulseSync/s_debounce_32\(4),
- I3 => \cmp_pulseSync/s_debounce_32\(3),
- I4 => \cmp_pulseSync/s_debounce_32\(2),
- I5 => \^s_datao_fmc2[0]\(7),
- O => \s_buff2_i_1__6_n_0\
- );
-\s_buff2_i_1__7\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_34\(1),
- I1 => \cmp_pulseSync/s_debounce_34\(0),
- I2 => \cmp_pulseSync/s_debounce_34\(4),
- I3 => \cmp_pulseSync/s_debounce_34\(3),
- I4 => \cmp_pulseSync/s_debounce_34\(2),
- I5 => \^s_datao_fmc2[0]\(8),
- O => \s_buff2_i_1__7_n_0\
- );
-\s_buff2_i_1__8\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_36\(1),
- I1 => \cmp_pulseSync/s_debounce_36\(0),
- I2 => \cmp_pulseSync/s_debounce_36\(4),
- I3 => \cmp_pulseSync/s_debounce_36\(3),
- I4 => \cmp_pulseSync/s_debounce_36\(2),
- I5 => \^s_datao_fmc2[0]\(9),
- O => \s_buff2_i_1__8_n_0\
- );
-\s_buff2_i_1__9\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFE80000000"
- )
- port map (
- I0 => \cmp_pulseSync/s_debounce_0\(1),
- I1 => \cmp_pulseSync/s_debounce_0\(0),
- I2 => \cmp_pulseSync/s_debounce_0\(4),
- I3 => \cmp_pulseSync/s_debounce_0\(3),
- I4 => \cmp_pulseSync/s_debounce_0\(2),
- I5 => \^s_datao_fmc2[0]\(10),
- O => \s_buff2_i_1__9_n_0\
- );
-\s_diffouts_o_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_dout(4),
- Q => s_diffouts_o(4),
- R => '0'
- );
-\s_diffouts_o_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_dout(5),
- Q => s_diffouts_o(5),
- R => '0'
- );
-\s_diffouts_o_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_dout(6),
- Q => s_diffouts_o(6),
- R => '0'
- );
-\s_diffouts_o_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => v_dout(7),
- Q => s_diffouts_o(7),
- R => '0'
- );
-s_start_i_1: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => s_start,
- I1 => \gen_spi.cmp_dac7716_spi_n_2\,
- I2 => \gen_spi.cmp_dac7716_spi_n_1\,
- O => s_start_i_1_n_0
- );
-\v_cmp_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(0),
- Q => v_cmp(0),
- R => '0'
- );
-\v_cmp_reg[10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(10),
- Q => v_cmp(10),
- R => '0'
- );
-\v_cmp_reg[11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(11),
- Q => v_cmp(11),
- R => '0'
- );
-\v_cmp_reg[12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(12),
- Q => v_cmp(12),
- R => '0'
- );
-\v_cmp_reg[13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(13),
- Q => v_cmp(13),
- R => '0'
- );
-\v_cmp_reg[14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(14),
- Q => v_cmp(14),
- R => '0'
- );
-\v_cmp_reg[15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(15),
- Q => v_cmp(15),
- R => '0'
- );
-\v_cmp_reg[16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(16),
- Q => v_cmp(16),
- R => '0'
- );
-\v_cmp_reg[17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(17),
- Q => v_cmp(17),
- R => '0'
- );
-\v_cmp_reg[18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(18),
- Q => v_cmp(18),
- R => '0'
- );
-\v_cmp_reg[19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(19),
- Q => v_cmp(19),
- R => '0'
- );
-\v_cmp_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(1),
- Q => v_cmp(1),
- R => '0'
- );
-\v_cmp_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(2),
- Q => v_cmp(2),
- R => '0'
- );
-\v_cmp_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(3),
- Q => v_cmp(3),
- R => '0'
- );
-\v_cmp_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(4),
- Q => v_cmp(4),
- R => '0'
- );
-\v_cmp_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(5),
- Q => v_cmp(5),
- R => '0'
- );
-\v_cmp_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(6),
- Q => v_cmp(6),
- R => '0'
- );
-\v_cmp_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(7),
- Q => v_cmp(7),
- R => '0'
- );
-\v_cmp_reg[8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(8),
- Q => v_cmp(8),
- R => '0'
- );
-\v_cmp_reg[9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_datao_fmc2[0]\(9),
- Q => v_cmp(9),
- R => '0'
- );
-\v_cmpled_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[4]\(0),
- Q => v_cmpled(0),
- R => '0'
- );
-\v_cmpled_reg[10]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(2),
- Q => v_cmpled(10),
- R => '0'
- );
-\v_cmpled_reg[11]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(3),
- Q => v_cmpled(11),
- R => '0'
- );
-\v_cmpled_reg[12]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(4),
- Q => v_cmpled(12),
- R => '0'
- );
-\v_cmpled_reg[13]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(5),
- Q => v_cmpled(13),
- R => '0'
- );
-\v_cmpled_reg[14]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(6),
- Q => v_cmpled(14),
- R => '0'
- );
-\v_cmpled_reg[15]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(7),
- Q => v_cmpled(15),
- R => '0'
- );
-\v_cmpled_reg[16]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(8),
- Q => v_cmpled(16),
- R => '0'
- );
-\v_cmpled_reg[17]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(9),
- Q => v_cmpled(17),
- R => '0'
- );
-\v_cmpled_reg[18]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(10),
- Q => v_cmpled(18),
- R => '0'
- );
-\v_cmpled_reg[19]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(11),
- Q => v_cmpled(19),
- R => '0'
- );
-\v_cmpled_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[4]\(1),
- Q => v_cmpled(1),
- R => '0'
- );
-\v_cmpled_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[4]\(2),
- Q => v_cmpled(2),
- R => '0'
- );
-\v_cmpled_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[4]\(3),
- Q => v_cmpled(3),
- R => '0'
- );
-\v_cmpled_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[4]\(4),
- Q => v_cmpled(4),
- R => '0'
- );
-\v_cmpled_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[4]\(5),
- Q => v_cmpled(5),
- R => '0'
- );
-\v_cmpled_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[4]\(6),
- Q => v_cmpled(6),
- R => '0'
- );
-\v_cmpled_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[4]\(7),
- Q => v_cmpled(7),
- R => '0'
- );
-\v_cmpled_reg[8]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(0),
- Q => v_cmpled(8),
- R => '0'
- );
-\v_cmpled_reg[9]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \^s_count_reg\(1),
- Q => v_cmpled(9),
- R => '0'
- );
-\v_dout_reg[4]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[78][4]\,
- Q => v_dout(4),
- S => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2\
- );
-\v_dout_reg[5]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[78][5]\,
- Q => v_dout(5),
- S => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2\
- );
-\v_dout_reg[6]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[78][6]\,
- Q => v_dout(6),
- S => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2\
- );
-\v_dout_reg[7]\: unisim.vcomponents.FDSE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \data_rw_o_reg[78][7]\,
- Q => v_dout(7),
- S => \fmc_03287_channels[0].gen_chs.cmp_ch_pulseMeasure_n_2\
- );
-\v_fbd_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \FMC2_LA_N_b[32]\(21),
- Q => v_fbd(0),
- R => '0'
- );
-\v_fbd_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \FMC2_LA_P_b[32]\(21),
- Q => v_fbd(1),
- R => '0'
- );
-\v_fbd_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \FMC2_LA_N_b[32]\(20),
- Q => v_fbd(2),
- R => '0'
- );
-\v_fbd_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \FMC2_LA_P_b[32]\(20),
- Q => v_fbd(3),
- R => '0'
- );
-\v_outleds_reg[0]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[5]\(0),
- Q => v_outleds(0),
- R => '0'
- );
-\v_outleds_reg[1]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[5]\(1),
- Q => v_outleds(1),
- R => '0'
- );
-\v_outleds_reg[2]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[5]\(2),
- Q => v_outleds(2),
- R => '0'
- );
-\v_outleds_reg[3]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[5]\(3),
- Q => v_outleds(3),
- R => '0'
- );
-\v_outleds_reg[4]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[5]\(4),
- Q => v_outleds(4),
- R => '0'
- );
-\v_outleds_reg[5]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[5]\(5),
- Q => v_outleds(5),
- R => '0'
- );
-\v_outleds_reg[6]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[5]\(6),
- Q => v_outleds(6),
- R => '0'
- );
-\v_outleds_reg[7]\: unisim.vcomponents.FDRE
- port map (
- C => s00_axi_aclk,
- CE => '1',
- D => \s_datao_fmc2[5]\(7),
- Q => v_outleds(7),
- R => '0'
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0_fasec_hwtest is
- port (
- ps_clk_i : in STD_LOGIC;
- osc100_clk_i : in STD_LOGIC;
- FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC2_PRSNTM2C_n_i : in STD_LOGIC;
- FMC2_CLK0M2C_P_i : in STD_LOGIC;
- FMC2_CLK0M2C_N_i : in STD_LOGIC;
- FMC2_CLK0C2M_P_o : out STD_LOGIC;
- FMC2_CLK0C2M_N_o : out STD_LOGIC;
- FMC2_GP0_i : in STD_LOGIC;
- FMC2_GP1_i : in STD_LOGIC;
- FMC2_GP2_i : in STD_LOGIC;
- FMC2_GP3_b : inout STD_LOGIC;
- FMC1_PRSNTM2C_n_i : in STD_LOGIC;
- FMC1_CLK0M2C_P_i : in STD_LOGIC;
- FMC1_CLK0M2C_N_i : in STD_LOGIC;
- FMC1_CLK0C2M_P_o : out STD_LOGIC;
- FMC1_CLK0C2M_N_o : out STD_LOGIC;
- FMC1_GP0_i : in STD_LOGIC;
- FMC1_GP1_i : in STD_LOGIC;
- FMC1_GP2_i : in STD_LOGIC;
- FMC1_GP3_b : inout STD_LOGIC;
- pb_gp_n_i : in STD_LOGIC;
- led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
- led_line_en_pl_o : out STD_LOGIC;
- led_line_pl_o : out STD_LOGIC;
- watchdog_pl_o : out STD_LOGIC;
- dig_in1_i : in STD_LOGIC;
- dig_in2_i : in STD_LOGIC;
- dig_in3_n_i : in STD_LOGIC;
- dig_in4_n_i : in STD_LOGIC;
- dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
- dig_out5_n : out STD_LOGIC;
- dig_out6_n : out STD_LOGIC;
- gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
- intr_o : out STD_LOGIC;
- intr_led_o : out STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_awvalid : in STD_LOGIC;
- s00_axi_awready : out STD_LOGIC;
- s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s00_axi_wvalid : in STD_LOGIC;
- s00_axi_wready : out STD_LOGIC;
- s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_bvalid : out STD_LOGIC;
- s00_axi_bready : in STD_LOGIC;
- s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_arvalid : in STD_LOGIC;
- s00_axi_arready : out STD_LOGIC;
- s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_rvalid : out STD_LOGIC;
- s00_axi_rready : in STD_LOGIC
- );
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of system_design_fasec_hwtest_0_0_fasec_hwtest : entity is "fasec_hwtest";
- attribute g_FMC1 : string;
- attribute g_FMC1 of system_design_fasec_hwtest_0_0_fasec_hwtest : entity is "EDA-03287";
- attribute g_FMC2 : string;
- attribute g_FMC2 of system_design_fasec_hwtest_0_0_fasec_hwtest : entity is "EDA-03287";
- attribute g_S00_AXI_ADDR_WIDTH : integer;
- attribute g_S00_AXI_ADDR_WIDTH of system_design_fasec_hwtest_0_0_fasec_hwtest : entity is 32;
- attribute g_S00_AXI_DATA_WIDTH : integer;
- attribute g_S00_AXI_DATA_WIDTH of system_design_fasec_hwtest_0_0_fasec_hwtest : entity is 32;
- attribute g_USE_GEM_LEDS : string;
- attribute g_USE_GEM_LEDS of system_design_fasec_hwtest_0_0_fasec_hwtest : entity is "FALSE";
-end system_design_fasec_hwtest_0_0_fasec_hwtest;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0_fasec_hwtest is
- signal \<const0>\ : STD_LOGIC;
- signal \<const1>\ : STD_LOGIC;
- signal axi_araddr : STD_LOGIC_VECTOR ( 5 downto 2 );
- signal clear : STD_LOGIC;
- signal cmp_axi4lite_slave_n_217 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_218 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_219 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_220 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_509 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_516 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_517 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_518 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_519 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_520 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_521 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_522 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_523 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_524 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_527 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_528 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_529 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_530 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_531 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_532 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_533 : STD_LOGIC;
- signal cmp_axi4lite_slave_n_534 : STD_LOGIC;
- signal cmp_general_fmc1_n_113 : STD_LOGIC;
- signal cmp_general_fmc1_n_126 : STD_LOGIC;
- signal cmp_general_fmc1_n_127 : STD_LOGIC;
- signal cmp_general_fmc1_n_128 : STD_LOGIC;
- signal cmp_general_fmc1_n_129 : STD_LOGIC;
- signal cmp_general_fmc1_n_130 : STD_LOGIC;
- signal cmp_general_fmc1_n_131 : STD_LOGIC;
- signal cmp_general_fmc1_n_132 : STD_LOGIC;
- signal cmp_general_fmc1_n_133 : STD_LOGIC;
- signal cmp_general_fmc1_n_134 : STD_LOGIC;
- signal cmp_general_fmc1_n_135 : STD_LOGIC;
- signal cmp_general_fmc1_n_136 : STD_LOGIC;
- signal cmp_general_fmc1_n_137 : STD_LOGIC;
- signal cmp_general_fmc1_n_138 : STD_LOGIC;
- signal cmp_general_fmc1_n_139 : STD_LOGIC;
- signal cmp_general_fmc1_n_140 : STD_LOGIC;
- signal cmp_general_fmc1_n_141 : STD_LOGIC;
- signal cmp_general_fmc1_n_142 : STD_LOGIC;
- signal cmp_general_fmc1_n_143 : STD_LOGIC;
- signal cmp_general_fmc1_n_144 : STD_LOGIC;
- signal cmp_general_fmc1_n_145 : STD_LOGIC;
- signal cmp_general_fmc1_n_146 : STD_LOGIC;
- signal cmp_general_fmc1_n_147 : STD_LOGIC;
- signal cmp_general_fmc1_n_148 : STD_LOGIC;
- signal cmp_general_fmc1_n_149 : STD_LOGIC;
- signal cmp_general_fmc1_n_150 : STD_LOGIC;
- signal cmp_general_fmc1_n_151 : STD_LOGIC;
- signal cmp_general_fmc1_n_152 : STD_LOGIC;
- signal cmp_general_fmc1_n_153 : STD_LOGIC;
- signal cmp_general_fmc1_n_154 : STD_LOGIC;
- signal cmp_general_fmc1_n_155 : STD_LOGIC;
- signal cmp_general_fmc1_n_156 : STD_LOGIC;
- signal cmp_general_fmc1_n_157 : STD_LOGIC;
- signal cmp_general_fmc1_n_158 : STD_LOGIC;
- signal cmp_general_fmc1_n_159 : STD_LOGIC;
- signal cmp_general_fmc1_n_160 : STD_LOGIC;
- signal cmp_general_fmc1_n_161 : STD_LOGIC;
- signal cmp_general_fmc1_n_162 : STD_LOGIC;
- signal cmp_general_fmc1_n_163 : STD_LOGIC;
- signal cmp_general_fmc1_n_164 : STD_LOGIC;
- signal cmp_general_fmc1_n_165 : STD_LOGIC;
- signal cmp_general_fmc1_n_166 : STD_LOGIC;
- signal cmp_general_fmc1_n_167 : STD_LOGIC;
- signal cmp_general_fmc1_n_168 : STD_LOGIC;
- signal cmp_general_fmc1_n_169 : STD_LOGIC;
- signal cmp_general_fmc1_n_170 : STD_LOGIC;
- signal cmp_general_fmc1_n_171 : STD_LOGIC;
- signal cmp_general_fmc1_n_172 : STD_LOGIC;
- signal cmp_general_fmc1_n_173 : STD_LOGIC;
- signal cmp_general_fmc1_n_174 : STD_LOGIC;
- signal cmp_general_fmc1_n_175 : STD_LOGIC;
- signal cmp_general_fmc1_n_176 : STD_LOGIC;
- signal cmp_general_fmc1_n_177 : STD_LOGIC;
- signal cmp_general_fmc1_n_178 : STD_LOGIC;
- signal cmp_general_fmc1_n_179 : STD_LOGIC;
- signal cmp_general_fmc1_n_180 : STD_LOGIC;
- signal cmp_general_fmc1_n_181 : STD_LOGIC;
- signal cmp_general_fmc1_n_182 : STD_LOGIC;
- signal cmp_general_fmc1_n_183 : STD_LOGIC;
- signal cmp_general_fmc1_n_184 : STD_LOGIC;
- signal cmp_general_fmc1_n_185 : STD_LOGIC;
- signal cmp_general_fmc1_n_186 : STD_LOGIC;
- signal cmp_general_fmc1_n_187 : STD_LOGIC;
- signal cmp_general_fmc1_n_188 : STD_LOGIC;
- signal cmp_general_fmc1_n_189 : STD_LOGIC;
- signal cmp_general_fmc1_n_190 : STD_LOGIC;
- signal cmp_general_fmc1_n_191 : STD_LOGIC;
- signal cmp_general_fmc1_n_192 : STD_LOGIC;
- signal cmp_general_fmc1_n_193 : STD_LOGIC;
- signal cmp_general_fmc1_n_194 : STD_LOGIC;
- signal cmp_general_fmc1_n_195 : STD_LOGIC;
- signal cmp_general_fmc1_n_196 : STD_LOGIC;
- signal cmp_general_fmc1_n_197 : STD_LOGIC;
- signal cmp_general_fmc1_n_198 : STD_LOGIC;
- signal cmp_general_fmc1_n_199 : STD_LOGIC;
- signal cmp_general_fmc1_n_200 : STD_LOGIC;
- signal cmp_general_fmc1_n_201 : STD_LOGIC;
- signal cmp_general_fmc1_n_202 : STD_LOGIC;
- signal cmp_general_fmc1_n_203 : STD_LOGIC;
- signal cmp_general_fmc1_n_204 : STD_LOGIC;
- signal cmp_general_fmc1_n_205 : STD_LOGIC;
- signal cmp_general_fmc1_n_206 : STD_LOGIC;
- signal cmp_general_fmc1_n_207 : STD_LOGIC;
- signal cmp_general_fmc1_n_208 : STD_LOGIC;
- signal cmp_general_fmc1_n_209 : STD_LOGIC;
- signal cmp_general_fmc1_n_210 : STD_LOGIC;
- signal cmp_general_fmc1_n_211 : STD_LOGIC;
- signal cmp_general_fmc1_n_212 : STD_LOGIC;
- signal cmp_general_fmc1_n_213 : STD_LOGIC;
- signal cmp_general_fmc1_n_214 : STD_LOGIC;
- signal cmp_general_fmc1_n_215 : STD_LOGIC;
- signal cmp_general_fmc1_n_216 : STD_LOGIC;
- signal cmp_general_fmc1_n_217 : STD_LOGIC;
- signal cmp_general_fmc1_n_218 : STD_LOGIC;
- signal cmp_general_fmc1_n_219 : STD_LOGIC;
- signal cmp_general_fmc1_n_220 : STD_LOGIC;
- signal cmp_general_fmc1_n_221 : STD_LOGIC;
- signal cmp_general_fmc1_n_222 : STD_LOGIC;
- signal cmp_general_fmc1_n_223 : STD_LOGIC;
- signal cmp_general_fmc1_n_224 : STD_LOGIC;
- signal cmp_general_fmc1_n_225 : STD_LOGIC;
- signal cmp_general_fmc1_n_226 : STD_LOGIC;
- signal cmp_general_fmc1_n_227 : STD_LOGIC;
- signal cmp_general_fmc1_n_228 : STD_LOGIC;
- signal cmp_general_fmc1_n_229 : STD_LOGIC;
- signal cmp_general_fmc1_n_230 : STD_LOGIC;
- signal cmp_general_fmc1_n_231 : STD_LOGIC;
- signal cmp_general_fmc1_n_232 : STD_LOGIC;
- signal cmp_general_fmc2_n_114 : STD_LOGIC;
- signal cmp_general_fmc2_n_127 : STD_LOGIC;
- signal cmp_general_fmc2_n_128 : STD_LOGIC;
- signal cmp_general_fmc2_n_129 : STD_LOGIC;
- signal cmp_general_fmc2_n_130 : STD_LOGIC;
- signal cmp_general_fmc2_n_131 : STD_LOGIC;
- signal cmp_general_fmc2_n_132 : STD_LOGIC;
- signal cmp_general_fmc2_n_133 : STD_LOGIC;
- signal cmp_general_fmc2_n_134 : STD_LOGIC;
- signal cmp_general_fmc2_n_135 : STD_LOGIC;
- signal cmp_general_fmc2_n_136 : STD_LOGIC;
- signal cmp_general_fmc2_n_137 : STD_LOGIC;
- signal cmp_general_fmc2_n_138 : STD_LOGIC;
- signal cmp_general_fmc2_n_139 : STD_LOGIC;
- signal cmp_general_fmc2_n_140 : STD_LOGIC;
- signal cmp_general_fmc2_n_141 : STD_LOGIC;
- signal cmp_general_fmc2_n_142 : STD_LOGIC;
- signal cmp_general_fmc2_n_143 : STD_LOGIC;
- signal cmp_general_fmc2_n_144 : STD_LOGIC;
- signal cmp_general_fmc2_n_145 : STD_LOGIC;
- signal cmp_general_fmc2_n_146 : STD_LOGIC;
- signal cmp_general_fmc2_n_147 : STD_LOGIC;
- signal cmp_general_fmc2_n_148 : STD_LOGIC;
- signal cmp_general_fmc2_n_149 : STD_LOGIC;
- signal cmp_general_fmc2_n_150 : STD_LOGIC;
- signal cmp_general_fmc2_n_151 : STD_LOGIC;
- signal cmp_general_fmc2_n_152 : STD_LOGIC;
- signal cmp_general_fmc2_n_153 : STD_LOGIC;
- signal cmp_general_fmc2_n_154 : STD_LOGIC;
- signal cmp_general_fmc2_n_155 : STD_LOGIC;
- signal cmp_general_fmc2_n_156 : STD_LOGIC;
- signal cmp_general_fmc2_n_157 : STD_LOGIC;
- signal cmp_general_fmc2_n_158 : STD_LOGIC;
- signal cmp_general_fmc2_n_159 : STD_LOGIC;
- signal cmp_general_fmc2_n_160 : STD_LOGIC;
- signal cmp_general_fmc2_n_161 : STD_LOGIC;
- signal cmp_general_fmc2_n_162 : STD_LOGIC;
- signal cmp_general_fmc2_n_163 : STD_LOGIC;
- signal cmp_general_fmc2_n_164 : STD_LOGIC;
- signal cmp_general_fmc2_n_165 : STD_LOGIC;
- signal cmp_general_fmc2_n_166 : STD_LOGIC;
- signal cmp_general_fmc2_n_167 : STD_LOGIC;
- signal cmp_general_fmc2_n_168 : STD_LOGIC;
- signal cmp_general_fmc2_n_169 : STD_LOGIC;
- signal cmp_general_fmc2_n_170 : STD_LOGIC;
- signal cmp_general_fmc2_n_171 : STD_LOGIC;
- signal cmp_general_fmc2_n_172 : STD_LOGIC;
- signal cmp_general_fmc2_n_173 : STD_LOGIC;
- signal cmp_general_fmc2_n_174 : STD_LOGIC;
- signal cmp_general_fmc2_n_175 : STD_LOGIC;
- signal cmp_general_fmc2_n_176 : STD_LOGIC;
- signal cmp_general_fmc2_n_177 : STD_LOGIC;
- signal cmp_general_fmc2_n_178 : STD_LOGIC;
- signal cmp_general_fmc2_n_179 : STD_LOGIC;
- signal cmp_general_fmc2_n_180 : STD_LOGIC;
- signal cmp_general_fmc2_n_181 : STD_LOGIC;
- signal cmp_general_fmc2_n_182 : STD_LOGIC;
- signal cmp_general_fmc2_n_183 : STD_LOGIC;
- signal cmp_general_fmc2_n_184 : STD_LOGIC;
- signal cmp_general_fmc2_n_185 : STD_LOGIC;
- signal \data_rw_o[100]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[101]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[102]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[103]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[11]\ : STD_LOGIC_VECTOR ( 7 downto 1 );
- signal \data_rw_o[16]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[17]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[18]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[19]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[20]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[21]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[22]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[23]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[24]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[25]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[26]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[27]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[28]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[29]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[30]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[31]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[32]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[33]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[34]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[35]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[79]\ : STD_LOGIC_VECTOR ( 7 downto 1 );
- signal \data_rw_o[84]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[85]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[86]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[87]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[88]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[89]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[90]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[91]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[92]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[93]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[94]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[95]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[96]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[97]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[98]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \data_rw_o[99]\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \^dig_out6_n\ : STD_LOGIC;
- signal \^dig_outs_i\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal fmc2_intr : STD_LOGIC;
- signal fmc2_intr_led : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/[0].[0].s_reqs_reg[0][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[0].[0].s_reqs_reg[0][value]__0_14\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[0].[1].s_reqs_reg[1][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[0].[1].s_reqs_reg[1][value]__0_13\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[0].[2].s_reqs_reg[2][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[0].[2].s_reqs_reg[2][value]__0_12\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0_15\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[1].[0].s_reqs_reg[4][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[1].[0].s_reqs_reg[4][value]__0_10\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[1].[1].s_reqs_reg[5][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[1].[1].s_reqs_reg[5][value]__0_9\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[1].[2].s_reqs_reg[6][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[1].[2].s_reqs_reg[6][value]__0_8\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[1].[3].s_reqs_reg[7][value]__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/[1].[3].s_reqs_reg[7][value]__0_11\ : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal \gen_spi.cmp_dac7716_spi/p_12_out\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_12_out_0\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_13_out\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_13_out_1\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_14_out\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_14_out_2\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_15_out\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_15_out_3\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_16_out\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_16_out_7\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_17_out\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_17_out_6\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_18_out\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_18_out_5\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_19_out\ : STD_LOGIC;
- signal \gen_spi.cmp_dac7716_spi/p_19_out_4\ : STD_LOGIC;
- signal \^led_line_pl_o\ : STD_LOGIC;
- signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 2 );
- signal p_2_in : STD_LOGIC;
- signal rst_i : STD_LOGIC;
- signal \^s00_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
- signal \^s00_axi_rresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
- signal \s_datao_fmc1[0]\ : STD_LOGIC_VECTOR ( 19 downto 0 );
- signal \s_datao_fmc1[1]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \s_datao_fmc1[28]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal \s_datao_fmc1[4]\ : STD_LOGIC_VECTOR ( 19 downto 8 );
- signal \s_datao_fmc2[0]\ : STD_LOGIC_VECTOR ( 19 downto 0 );
- signal \s_datao_fmc2[1]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \s_datao_fmc2[28]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal \s_datao_fmc2[4]\ : STD_LOGIC_VECTOR ( 19 downto 8 );
- signal \s_ins_reg_n_0_[0]\ : STD_LOGIC;
- signal \s_ins_reg_n_0_[1]\ : STD_LOGIC;
- signal \s_ins_reg_n_0_[2]\ : STD_LOGIC;
- signal \s_ins_reg_n_0_[3]\ : STD_LOGIC;
- signal s_led_line_i_1_n_0 : STD_LOGIC;
- signal s_led_line_i_2_n_0 : STD_LOGIC;
- signal \s_leds[0]_i_1_n_0\ : STD_LOGIC;
- signal \s_leds[1]_i_1_n_0\ : STD_LOGIC;
- signal \s_leds[2]_i_1_n_0\ : STD_LOGIC;
- signal \s_leds[3]_i_1_n_0\ : STD_LOGIC;
- signal \s_leds[3]_i_2_n_0\ : STD_LOGIC;
- signal \s_leds[3]_i_3_n_0\ : STD_LOGIC;
- signal \s_leds[3]_i_4_n_0\ : STD_LOGIC;
- signal \s_leds[3]_i_5_n_0\ : STD_LOGIC;
- signal s_tick : STD_LOGIC;
- signal s_tick_i_1_n_0 : STD_LOGIC;
- signal \v_cntr[0]_i_10_n_0\ : STD_LOGIC;
- signal \v_cntr[0]_i_11_n_0\ : STD_LOGIC;
- signal \v_cntr[0]_i_3_n_0\ : STD_LOGIC;
- signal \v_cntr[0]_i_4_n_0\ : STD_LOGIC;
- signal \v_cntr[0]_i_5_n_0\ : STD_LOGIC;
- signal \v_cntr[0]_i_9_n_0\ : STD_LOGIC;
- signal v_cntr_reg : STD_LOGIC_VECTOR ( 31 downto 9 );
- signal \v_cntr_reg[0]_i_2_n_0\ : STD_LOGIC;
- signal \v_cntr_reg[0]_i_2_n_1\ : STD_LOGIC;
- signal \v_cntr_reg[0]_i_2_n_2\ : STD_LOGIC;
- signal \v_cntr_reg[0]_i_2_n_3\ : STD_LOGIC;
- signal \v_cntr_reg[0]_i_2_n_4\ : STD_LOGIC;
- signal \v_cntr_reg[0]_i_2_n_5\ : STD_LOGIC;
- signal \v_cntr_reg[0]_i_2_n_6\ : STD_LOGIC;
- signal \v_cntr_reg[0]_i_2_n_7\ : STD_LOGIC;
- signal \v_cntr_reg[12]_i_1_n_0\ : STD_LOGIC;
- signal \v_cntr_reg[12]_i_1_n_1\ : STD_LOGIC;
- signal \v_cntr_reg[12]_i_1_n_2\ : STD_LOGIC;
- signal \v_cntr_reg[12]_i_1_n_3\ : STD_LOGIC;
- signal \v_cntr_reg[12]_i_1_n_4\ : STD_LOGIC;
- signal \v_cntr_reg[12]_i_1_n_5\ : STD_LOGIC;
- signal \v_cntr_reg[12]_i_1_n_6\ : STD_LOGIC;
- signal \v_cntr_reg[12]_i_1_n_7\ : STD_LOGIC;
- signal \v_cntr_reg[16]_i_1_n_0\ : STD_LOGIC;
- signal \v_cntr_reg[16]_i_1_n_1\ : STD_LOGIC;
- signal \v_cntr_reg[16]_i_1_n_2\ : STD_LOGIC;
- signal \v_cntr_reg[16]_i_1_n_3\ : STD_LOGIC;
- signal \v_cntr_reg[16]_i_1_n_4\ : STD_LOGIC;
- signal \v_cntr_reg[16]_i_1_n_5\ : STD_LOGIC;
- signal \v_cntr_reg[16]_i_1_n_6\ : STD_LOGIC;
- signal \v_cntr_reg[16]_i_1_n_7\ : STD_LOGIC;
- signal \v_cntr_reg[20]_i_1_n_0\ : STD_LOGIC;
- signal \v_cntr_reg[20]_i_1_n_1\ : STD_LOGIC;
- signal \v_cntr_reg[20]_i_1_n_2\ : STD_LOGIC;
- signal \v_cntr_reg[20]_i_1_n_3\ : STD_LOGIC;
- signal \v_cntr_reg[20]_i_1_n_4\ : STD_LOGIC;
- signal \v_cntr_reg[20]_i_1_n_5\ : STD_LOGIC;
- signal \v_cntr_reg[20]_i_1_n_6\ : STD_LOGIC;
- signal \v_cntr_reg[20]_i_1_n_7\ : STD_LOGIC;
- signal \v_cntr_reg[24]_i_1_n_0\ : STD_LOGIC;
- signal \v_cntr_reg[24]_i_1_n_1\ : STD_LOGIC;
- signal \v_cntr_reg[24]_i_1_n_2\ : STD_LOGIC;
- signal \v_cntr_reg[24]_i_1_n_3\ : STD_LOGIC;
- signal \v_cntr_reg[24]_i_1_n_4\ : STD_LOGIC;
- signal \v_cntr_reg[24]_i_1_n_5\ : STD_LOGIC;
- signal \v_cntr_reg[24]_i_1_n_6\ : STD_LOGIC;
- signal \v_cntr_reg[24]_i_1_n_7\ : STD_LOGIC;
- signal \v_cntr_reg[28]_i_1_n_1\ : STD_LOGIC;
- signal \v_cntr_reg[28]_i_1_n_2\ : STD_LOGIC;
- signal \v_cntr_reg[28]_i_1_n_3\ : STD_LOGIC;
- signal \v_cntr_reg[28]_i_1_n_4\ : STD_LOGIC;
- signal \v_cntr_reg[28]_i_1_n_5\ : STD_LOGIC;
- signal \v_cntr_reg[28]_i_1_n_6\ : STD_LOGIC;
- signal \v_cntr_reg[28]_i_1_n_7\ : STD_LOGIC;
- signal \v_cntr_reg[4]_i_1_n_0\ : STD_LOGIC;
- signal \v_cntr_reg[4]_i_1_n_1\ : STD_LOGIC;
- signal \v_cntr_reg[4]_i_1_n_2\ : STD_LOGIC;
- signal \v_cntr_reg[4]_i_1_n_3\ : STD_LOGIC;
- signal \v_cntr_reg[4]_i_1_n_4\ : STD_LOGIC;
- signal \v_cntr_reg[4]_i_1_n_5\ : STD_LOGIC;
- signal \v_cntr_reg[4]_i_1_n_6\ : STD_LOGIC;
- signal \v_cntr_reg[4]_i_1_n_7\ : STD_LOGIC;
- signal \v_cntr_reg[8]_i_1_n_0\ : STD_LOGIC;
- signal \v_cntr_reg[8]_i_1_n_1\ : STD_LOGIC;
- signal \v_cntr_reg[8]_i_1_n_2\ : STD_LOGIC;
- signal \v_cntr_reg[8]_i_1_n_3\ : STD_LOGIC;
- signal \v_cntr_reg[8]_i_1_n_4\ : STD_LOGIC;
- signal \v_cntr_reg[8]_i_1_n_5\ : STD_LOGIC;
- signal \v_cntr_reg[8]_i_1_n_6\ : STD_LOGIC;
- signal \v_cntr_reg[8]_i_1_n_7\ : STD_LOGIC;
- signal \v_cntr_reg_n_0_[0]\ : STD_LOGIC;
- signal \v_cntr_reg_n_0_[1]\ : STD_LOGIC;
- signal \v_cntr_reg_n_0_[2]\ : STD_LOGIC;
- signal \v_cntr_reg_n_0_[3]\ : STD_LOGIC;
- signal \v_cntr_reg_n_0_[4]\ : STD_LOGIC;
- signal \v_cntr_reg_n_0_[5]\ : STD_LOGIC;
- signal \v_cntr_reg_n_0_[6]\ : STD_LOGIC;
- signal \v_cntr_reg_n_0_[7]\ : STD_LOGIC;
- signal \v_cntr_reg_n_0_[8]\ : STD_LOGIC;
- signal v_ins : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal \v_pbreg_reg_n_0_[0]\ : STD_LOGIC;
- signal v_shift : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal \v_shift[0]_i_1_n_0\ : STD_LOGIC;
- signal \v_shift[1]_i_1_n_0\ : STD_LOGIC;
- signal \v_shift[2]_i_1_n_0\ : STD_LOGIC;
- signal \v_shift[3]_i_1_n_0\ : STD_LOGIC;
- signal \NLW_v_cntr_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
- attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of s_led_line_i_1 : label is "soft_lutpair58";
- attribute SOFT_HLUTNM of s_led_line_i_2 : label is "soft_lutpair59";
- attribute SOFT_HLUTNM of \s_leds[3]_i_3\ : label is "soft_lutpair58";
- attribute SOFT_HLUTNM of \s_leds[3]_i_4\ : label is "soft_lutpair60";
- attribute SOFT_HLUTNM of s_tick_i_1 : label is "soft_lutpair61";
- attribute SOFT_HLUTNM of \v_shift[0]_i_1\ : label is "soft_lutpair62";
- attribute SOFT_HLUTNM of \v_shift[1]_i_1\ : label is "soft_lutpair62";
- attribute SOFT_HLUTNM of \v_shift[3]_i_1\ : label is "soft_lutpair63";
- attribute SOFT_HLUTNM of \v_shift[4]_i_1\ : label is "soft_lutpair63";
- attribute SOFT_HLUTNM of \v_shift[5]_i_1\ : label is "soft_lutpair59";
- attribute SOFT_HLUTNM of \v_shift[6]_i_1\ : label is "soft_lutpair61";
- attribute SOFT_HLUTNM of \v_shift[7]_i_1\ : label is "soft_lutpair60";
-begin
- FMC1_CLK0C2M_N_o <= \<const0>\;
- FMC1_CLK0C2M_P_o <= \<const0>\;
- FMC2_CLK0C2M_N_o <= \<const0>\;
- FMC2_CLK0C2M_P_o <= \<const0>\;
- dig_out5_n <= \^dig_out6_n\;
- dig_out6_n <= \^dig_out6_n\;
- dig_outs_i(3) <= \^dig_outs_i\(0);
- dig_outs_i(2) <= \^dig_outs_i\(0);
- dig_outs_i(1) <= \^dig_outs_i\(0);
- dig_outs_i(0) <= \^dig_outs_i\(0);
- led_line_en_pl_o <= \<const1>\;
- led_line_pl_o <= \^led_line_pl_o\;
- s00_axi_bresp(1) <= \^s00_axi_bresp\(1);
- s00_axi_bresp(0) <= \<const0>\;
- s00_axi_rresp(1) <= \^s00_axi_rresp\(1);
- s00_axi_rresp(0) <= \<const0>\;
-GND: unisim.vcomponents.GND
- port map (
- G => \<const0>\
- );
-VCC: unisim.vcomponents.VCC
- port map (
- P => \<const1>\
- );
-cmp_axi4lite_slave: entity work.system_design_fasec_hwtest_0_0_axi4lite_slave
- port map (
- CO(0) => \gen_spi.cmp_dac7716_spi/p_16_out_7\,
- Q(11 downto 0) => \data_rw_o[19]\(11 downto 0),
- \[0].[0].s_reqs_reg[0][changed]\(0) => \gen_spi.cmp_dac7716_spi/p_19_out_4\,
- \[0].[0].s_reqs_reg[0][changed]_0\(0) => \gen_spi.cmp_dac7716_spi/p_19_out\,
- \[0].[0].s_reqs_reg[0][value][11]\(11 downto 0) => \data_rw_o[16]\(11 downto 0),
- \[0].[0].s_reqs_reg[0][value][11]_0\(11 downto 0) => \data_rw_o[84]\(11 downto 0),
- \[0].[0].s_reqs_reg[0][value][11]_1\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[0].s_reqs_reg[0][value]__0\(11 downto 0),
- \[0].[0].s_reqs_reg[0][value][11]_2\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[0].s_reqs_reg[0][value]__0_14\(11 downto 0),
- \[0].[1].s_reqs_reg[1][changed]\(0) => \gen_spi.cmp_dac7716_spi/p_18_out_5\,
- \[0].[1].s_reqs_reg[1][changed]_0\(0) => \gen_spi.cmp_dac7716_spi/p_18_out\,
- \[0].[1].s_reqs_reg[1][value][11]\(11 downto 0) => \data_rw_o[17]\(11 downto 0),
- \[0].[1].s_reqs_reg[1][value][11]_0\(11 downto 0) => \data_rw_o[85]\(11 downto 0),
- \[0].[1].s_reqs_reg[1][value][11]_1\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[1].s_reqs_reg[1][value]__0\(11 downto 0),
- \[0].[1].s_reqs_reg[1][value][11]_2\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[1].s_reqs_reg[1][value]__0_13\(11 downto 0),
- \[0].[2].s_reqs_reg[2][changed]\(0) => \gen_spi.cmp_dac7716_spi/p_17_out_6\,
- \[0].[2].s_reqs_reg[2][changed]_0\(0) => \gen_spi.cmp_dac7716_spi/p_17_out\,
- \[0].[2].s_reqs_reg[2][value][11]\(11 downto 0) => \data_rw_o[18]\(11 downto 0),
- \[0].[2].s_reqs_reg[2][value][11]_0\(11 downto 0) => \data_rw_o[86]\(11 downto 0),
- \[0].[2].s_reqs_reg[2][value][11]_1\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[2].s_reqs_reg[2][value]__0\(11 downto 0),
- \[0].[2].s_reqs_reg[2][value][11]_2\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[2].s_reqs_reg[2][value]__0_12\(11 downto 0),
- \[0].[3].s_reqs_reg[3][changed]\(0) => \gen_spi.cmp_dac7716_spi/p_16_out\,
- \[0].[3].s_reqs_reg[3][value][11]\(11 downto 0) => \data_rw_o[87]\(11 downto 0),
- \[0].[3].s_reqs_reg[3][value][11]_0\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0\(11 downto 0),
- \[0].[3].s_reqs_reg[3][value][11]_1\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0_15\(11 downto 0),
- \[1].[0].s_reqs_reg[4][changed]\(0) => \gen_spi.cmp_dac7716_spi/p_15_out_3\,
- \[1].[0].s_reqs_reg[4][changed]_0\(0) => \gen_spi.cmp_dac7716_spi/p_15_out\,
- \[1].[0].s_reqs_reg[4][value][11]\(11 downto 0) => \data_rw_o[20]\(11 downto 0),
- \[1].[0].s_reqs_reg[4][value][11]_0\(11 downto 0) => \data_rw_o[88]\(11 downto 0),
- \[1].[0].s_reqs_reg[4][value][11]_1\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[0].s_reqs_reg[4][value]__0\(11 downto 0),
- \[1].[0].s_reqs_reg[4][value][11]_2\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[0].s_reqs_reg[4][value]__0_10\(11 downto 0),
- \[1].[1].s_reqs_reg[5][changed]\(0) => \gen_spi.cmp_dac7716_spi/p_14_out_2\,
- \[1].[1].s_reqs_reg[5][changed]_0\(0) => \gen_spi.cmp_dac7716_spi/p_14_out\,
- \[1].[1].s_reqs_reg[5][value][11]\(11 downto 0) => \data_rw_o[21]\(11 downto 0),
- \[1].[1].s_reqs_reg[5][value][11]_0\(11 downto 0) => \data_rw_o[89]\(11 downto 0),
- \[1].[1].s_reqs_reg[5][value][11]_1\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[1].s_reqs_reg[5][value]__0\(11 downto 0),
- \[1].[1].s_reqs_reg[5][value][11]_2\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[1].s_reqs_reg[5][value]__0_9\(11 downto 0),
- \[1].[2].s_reqs_reg[6][changed]\(0) => \gen_spi.cmp_dac7716_spi/p_13_out_1\,
- \[1].[2].s_reqs_reg[6][changed]_0\(0) => \gen_spi.cmp_dac7716_spi/p_13_out\,
- \[1].[2].s_reqs_reg[6][value][11]\(11 downto 0) => \data_rw_o[22]\(11 downto 0),
- \[1].[2].s_reqs_reg[6][value][11]_0\(11 downto 0) => \data_rw_o[90]\(11 downto 0),
- \[1].[2].s_reqs_reg[6][value][11]_1\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[2].s_reqs_reg[6][value]__0\(11 downto 0),
- \[1].[2].s_reqs_reg[6][value][11]_2\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[2].s_reqs_reg[6][value]__0_8\(11 downto 0),
- \[1].[3].s_reqs_reg[7][changed]\(0) => \gen_spi.cmp_dac7716_spi/p_12_out_0\,
- \[1].[3].s_reqs_reg[7][changed]_0\(0) => \gen_spi.cmp_dac7716_spi/p_12_out\,
- \[1].[3].s_reqs_reg[7][value][11]\(11 downto 0) => \data_rw_o[23]\(11 downto 0),
- \[1].[3].s_reqs_reg[7][value][11]_0\(11 downto 0) => \data_rw_o[91]\(11 downto 0),
- \[1].[3].s_reqs_reg[7][value][11]_1\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[3].s_reqs_reg[7][value]__0\(11 downto 0),
- \[1].[3].s_reqs_reg[7][value][11]_2\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[3].s_reqs_reg[7][value]__0_11\(11 downto 0),
- \[2].[0].s_reqs_reg[8][value][11]\(11 downto 0) => \data_rw_o[24]\(11 downto 0),
- \[2].[0].s_reqs_reg[8][value][11]_0\(11 downto 0) => \data_rw_o[92]\(11 downto 0),
- \[2].[1].s_reqs_reg[9][value][11]\(11 downto 0) => \data_rw_o[25]\(11 downto 0),
- \[2].[1].s_reqs_reg[9][value][11]_0\(11 downto 0) => \data_rw_o[93]\(11 downto 0),
- \[2].[2].s_reqs_reg[10][value][11]\(11 downto 0) => \data_rw_o[26]\(11 downto 0),
- \[2].[2].s_reqs_reg[10][value][11]_0\(11 downto 0) => \data_rw_o[94]\(11 downto 0),
- \[2].[3].s_reqs_reg[11][value][11]\(11 downto 0) => \data_rw_o[27]\(11 downto 0),
- \[2].[3].s_reqs_reg[11][value][11]_0\(11 downto 0) => \data_rw_o[95]\(11 downto 0),
- \[3].[0].s_reqs_reg[12][value][11]\(11 downto 0) => \data_rw_o[28]\(11 downto 0),
- \[3].[0].s_reqs_reg[12][value][11]_0\(11 downto 0) => \data_rw_o[96]\(11 downto 0),
- \[3].[1].s_reqs_reg[13][value][11]\(11 downto 0) => \data_rw_o[29]\(11 downto 0),
- \[3].[1].s_reqs_reg[13][value][11]_0\(11 downto 0) => \data_rw_o[97]\(11 downto 0),
- \[3].[2].s_reqs_reg[14][value][11]\(11 downto 0) => \data_rw_o[30]\(11 downto 0),
- \[3].[2].s_reqs_reg[14][value][11]_0\(11 downto 0) => \data_rw_o[98]\(11 downto 0),
- \[3].[3].s_reqs_reg[15][value][11]\(11 downto 0) => \data_rw_o[31]\(11 downto 0),
- \[3].[3].s_reqs_reg[15][value][11]_0\(11 downto 0) => \data_rw_o[99]\(11 downto 0),
- \[4].[0].s_reqs_reg[16][value][11]\(11 downto 0) => \data_rw_o[32]\(11 downto 0),
- \[4].[0].s_reqs_reg[16][value][11]_0\(11 downto 0) => \data_rw_o[100]\(11 downto 0),
- \[4].[1].s_reqs_reg[17][value][11]\(11 downto 0) => \data_rw_o[33]\(11 downto 0),
- \[4].[1].s_reqs_reg[17][value][11]_0\(11 downto 0) => \data_rw_o[101]\(11 downto 0),
- \[4].[2].s_reqs_reg[18][value][11]\(11 downto 0) => \data_rw_o[34]\(11 downto 0),
- \[4].[2].s_reqs_reg[18][value][11]_0\(11 downto 0) => \data_rw_o[102]\(11 downto 0),
- \[4].[3].s_reqs_reg[19][value][11]\(11 downto 0) => \data_rw_o[35]\(11 downto 0),
- \[4].[3].s_reqs_reg[19][value][11]_0\(11 downto 0) => \data_rw_o[103]\(11 downto 0),
- \axi_araddr_reg[4]_0\ => cmp_general_fmc1_n_211,
- \axi_araddr_reg[4]_1\ => cmp_general_fmc2_n_184,
- \axi_araddr_reg[4]_2\ => cmp_general_fmc2_n_185,
- \axi_araddr_reg[4]_3\ => cmp_general_fmc2_n_181,
- \axi_araddr_reg[4]_4\ => cmp_general_fmc2_n_182,
- \axi_araddr_reg[4]_5\ => cmp_general_fmc2_n_178,
- \axi_araddr_reg[4]_6\ => cmp_general_fmc2_n_179,
- \axi_araddr_reg[4]_7\ => cmp_general_fmc2_n_175,
- \axi_araddr_reg[4]_8\ => cmp_general_fmc2_n_176,
- \axi_araddr_reg[4]_rep_0\ => cmp_general_fmc1_n_175,
- \axi_araddr_reg[4]_rep_1\ => cmp_general_fmc1_n_179,
- \axi_araddr_reg[4]_rep_2\ => cmp_general_fmc1_n_183,
- \axi_araddr_reg[4]_rep_3\ => cmp_general_fmc1_n_187,
- \axi_araddr_reg[4]_rep_4\ => cmp_general_fmc1_n_191,
- \axi_araddr_reg[4]_rep_5\ => cmp_general_fmc1_n_195,
- \axi_araddr_reg[4]_rep_6\ => cmp_general_fmc1_n_199,
- \axi_araddr_reg[4]_rep_7\ => cmp_general_fmc1_n_203,
- \axi_araddr_reg[4]_rep_8\ => cmp_general_fmc1_n_207,
- \axi_araddr_reg[4]_rep__0_0\ => cmp_general_fmc1_n_133,
- \axi_araddr_reg[4]_rep__0_1\ => cmp_general_fmc1_n_138,
- \axi_araddr_reg[4]_rep__0_2\ => cmp_general_fmc1_n_143,
- \axi_araddr_reg[4]_rep__0_3\ => cmp_general_fmc1_n_148,
- \axi_araddr_reg[4]_rep__0_4\ => cmp_general_fmc1_n_153,
- \axi_araddr_reg[4]_rep__0_5\ => cmp_general_fmc1_n_158,
- \axi_araddr_reg[4]_rep__0_6\ => cmp_general_fmc1_n_163,
- \axi_araddr_reg[4]_rep__0_7\ => cmp_general_fmc1_n_167,
- \axi_araddr_reg[4]_rep__0_8\ => cmp_general_fmc1_n_171,
- \axi_araddr_reg[4]_rep__1_0\ => cmp_general_fmc1_n_128,
- \axi_araddr_reg[5]_0\ => cmp_general_fmc2_n_173,
- \axi_araddr_reg[5]_1\ => cmp_general_fmc2_n_171,
- \axi_araddr_reg[5]_2\ => cmp_general_fmc2_n_169,
- \axi_araddr_reg[5]_3\ => cmp_general_fmc2_n_167,
- \axi_araddr_reg[5]_4\ => cmp_general_fmc2_n_165,
- \axi_araddr_reg[5]_5\ => cmp_general_fmc2_n_163,
- \axi_araddr_reg[5]_6\ => cmp_general_fmc2_n_161,
- \axi_araddr_reg[5]_7\ => cmp_general_fmc2_n_159,
- \axi_araddr_reg[5]_8\ => cmp_general_fmc2_n_157,
- \axi_araddr_reg[5]_rep_0\ => cmp_general_fmc2_n_155,
- \axi_araddr_reg[5]_rep_1\ => cmp_general_fmc2_n_153,
- \axi_araddr_reg[5]_rep_10\ => cmp_general_fmc2_n_128,
- \axi_araddr_reg[5]_rep_2\ => cmp_general_fmc2_n_151,
- \axi_araddr_reg[5]_rep_3\ => cmp_general_fmc2_n_149,
- \axi_araddr_reg[5]_rep_4\ => cmp_general_fmc2_n_146,
- \axi_araddr_reg[5]_rep_5\ => cmp_general_fmc2_n_143,
- \axi_araddr_reg[5]_rep_6\ => cmp_general_fmc2_n_140,
- \axi_araddr_reg[5]_rep_7\ => cmp_general_fmc2_n_137,
- \axi_araddr_reg[5]_rep_8\ => cmp_general_fmc2_n_134,
- \axi_araddr_reg[5]_rep_9\ => cmp_general_fmc2_n_131,
- \axi_rdata_reg[0]_0\ => cmp_axi4lite_slave_n_218,
- \axi_rdata_reg[10]_0\ => cmp_axi4lite_slave_n_217,
- \axi_rdata_reg[12]_0\ => cmp_axi4lite_slave_n_518,
- \axi_rdata_reg[12]_1\ => cmp_axi4lite_slave_n_519,
- \axi_rdata_reg[17]_0\ => cmp_axi4lite_slave_n_521,
- \axi_rdata_reg[17]_1\ => cmp_axi4lite_slave_n_522,
- \axi_rdata_reg[18]_0\ => cmp_axi4lite_slave_n_520,
- \axi_rdata_reg[22]_0\ => cmp_axi4lite_slave_n_523,
- \axi_rdata_reg[22]_1\ => cmp_axi4lite_slave_n_524,
- \axi_rdata_reg[23]_0\(3 downto 0) => axi_araddr(5 downto 2),
- \axi_rdata_reg[2]_0\ => cmp_axi4lite_slave_n_219,
- \axi_rdata_reg[2]_1\ => cmp_axi4lite_slave_n_220,
- \axi_rdata_reg[7]_0\ => cmp_axi4lite_slave_n_516,
- \axi_rdata_reg[7]_1\ => cmp_axi4lite_slave_n_517,
- \axi_rdata_reg[9]_0\ => cmp_axi4lite_slave_n_509,
- \dac_ch_o_reg[0][31]\(31 downto 0) => \s_datao_fmc2[28]\(31 downto 0),
- \dac_ch_o_reg[0][31]_0\(31 downto 0) => \s_datao_fmc1[28]\(31 downto 0),
- \data_o_reg[1][3]\(3 downto 0) => \s_datao_fmc1[1]\(3 downto 0),
- \data_o_reg[1][3]_0\(3 downto 0) => \s_datao_fmc2[1]\(3 downto 0),
- \data_o_reg[6][0]\ => cmp_general_fmc1_n_113,
- \data_o_reg[6][0]_0\ => cmp_general_fmc2_n_114,
- \data_o_reg[6][1]\ => cmp_general_fmc1_n_130,
- \data_o_reg[6][1]_0\ => cmp_general_fmc2_n_129,
- \data_o_reg[6][2]\ => cmp_general_fmc1_n_135,
- \data_o_reg[6][2]_0\ => cmp_general_fmc2_n_132,
- \data_o_reg[6][3]\ => cmp_general_fmc1_n_140,
- \data_o_reg[6][3]_0\ => cmp_general_fmc2_n_135,
- \data_o_reg[6][4]\ => cmp_general_fmc1_n_145,
- \data_o_reg[6][4]_0\ => cmp_general_fmc2_n_138,
- \data_o_reg[6][5]\ => cmp_general_fmc1_n_150,
- \data_o_reg[6][5]_0\ => cmp_general_fmc2_n_141,
- \data_o_reg[6][6]\ => cmp_general_fmc1_n_155,
- \data_o_reg[6][6]_0\ => cmp_general_fmc2_n_144,
- \data_o_reg[6][7]\ => cmp_general_fmc1_n_160,
- \data_o_reg[6][7]_0\ => cmp_general_fmc2_n_147,
- dig_out6_n => \^dig_out6_n\,
- dig_outs_i(0) => \^dig_outs_i\(0),
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][20]\ => cmp_general_fmc1_n_215,
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][21]\ => cmp_general_fmc1_n_220,
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][22]\ => cmp_general_fmc1_n_225,
- \fmc_03287_channels[11].gen_chs.data_o_reg[59][23]\ => cmp_general_fmc1_n_230,
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][20]\ => cmp_general_fmc1_n_216,
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][21]\ => cmp_general_fmc1_n_221,
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][22]\ => cmp_general_fmc1_n_226,
- \fmc_03287_channels[15].gen_chs.data_o_reg[63][23]\ => cmp_general_fmc1_n_231,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][0]\ => cmp_general_fmc1_n_129,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][10]\ => cmp_general_fmc1_n_176,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][11]\ => cmp_general_fmc1_n_180,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][12]\ => cmp_general_fmc1_n_184,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][13]\ => cmp_general_fmc1_n_188,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][14]\ => cmp_general_fmc1_n_192,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][15]\ => cmp_general_fmc1_n_196,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][16]\ => cmp_general_fmc1_n_200,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][17]\ => cmp_general_fmc1_n_204,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][18]\ => cmp_general_fmc1_n_208,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][19]\ => cmp_general_fmc1_n_212,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][1]\ => cmp_general_fmc1_n_134,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][20]\ => cmp_general_fmc1_n_217,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][21]\ => cmp_general_fmc1_n_222,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][22]\ => cmp_general_fmc1_n_227,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][23]\ => cmp_general_fmc1_n_232,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][2]\ => cmp_general_fmc1_n_139,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][3]\ => cmp_general_fmc1_n_144,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][4]\ => cmp_general_fmc1_n_149,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][5]\ => cmp_general_fmc1_n_154,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][6]\ => cmp_general_fmc1_n_159,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][7]\ => cmp_general_fmc1_n_164,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][8]\ => cmp_general_fmc1_n_168,
- \fmc_03287_channels[19].gen_chs.data_o_reg[67][9]\ => cmp_general_fmc1_n_172,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][0]\ => cmp_general_fmc1_n_126,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][0]_0\ => cmp_general_fmc2_n_127,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][10]\ => cmp_general_fmc1_n_173,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][10]_0\ => cmp_general_fmc2_n_154,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][11]\ => cmp_general_fmc1_n_177,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][11]_0\ => cmp_general_fmc2_n_156,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][12]\ => cmp_general_fmc1_n_181,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][12]_0\ => cmp_general_fmc2_n_158,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][13]\ => cmp_general_fmc1_n_185,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][13]_0\ => cmp_general_fmc2_n_160,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][14]\ => cmp_general_fmc1_n_189,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][14]_0\ => cmp_general_fmc2_n_162,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][15]\ => cmp_general_fmc1_n_193,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][15]_0\ => cmp_general_fmc2_n_164,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][16]\ => cmp_general_fmc1_n_197,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][16]_0\ => cmp_general_fmc2_n_166,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][17]\ => cmp_general_fmc1_n_201,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][17]_0\ => cmp_general_fmc2_n_168,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][18]\ => cmp_general_fmc1_n_205,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][18]_0\ => cmp_general_fmc2_n_170,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][19]\ => cmp_general_fmc1_n_209,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][19]_0\ => cmp_general_fmc2_n_172,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][1]\ => cmp_general_fmc1_n_131,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][1]_0\ => cmp_general_fmc2_n_130,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][20]\ => cmp_general_fmc1_n_213,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][20]_0\ => cmp_general_fmc2_n_174,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][21]\ => cmp_general_fmc1_n_218,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][21]_0\ => cmp_general_fmc2_n_177,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][22]\ => cmp_general_fmc1_n_223,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][22]_0\ => cmp_general_fmc2_n_180,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]\ => cmp_general_fmc1_n_228,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][23]_0\ => cmp_general_fmc2_n_183,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][2]\ => cmp_general_fmc1_n_136,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][2]_0\ => cmp_general_fmc2_n_133,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][3]\ => cmp_general_fmc1_n_141,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][3]_0\ => cmp_general_fmc2_n_136,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][4]\ => cmp_general_fmc1_n_146,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][4]_0\ => cmp_general_fmc2_n_139,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][5]\ => cmp_general_fmc1_n_151,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][5]_0\ => cmp_general_fmc2_n_142,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][6]\ => cmp_general_fmc1_n_156,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][6]_0\ => cmp_general_fmc2_n_145,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][7]\ => cmp_general_fmc1_n_161,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][7]_0\ => cmp_general_fmc2_n_148,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][8]\ => cmp_general_fmc1_n_165,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][8]_0\ => cmp_general_fmc2_n_150,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][9]\ => cmp_general_fmc1_n_169,
- \fmc_03287_channels[3].gen_chs.data_o_reg[51][9]_0\ => cmp_general_fmc2_n_152,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][0]\ => cmp_general_fmc1_n_127,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][10]\ => cmp_general_fmc1_n_174,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][11]\ => cmp_general_fmc1_n_178,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][12]\ => cmp_general_fmc1_n_182,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][13]\ => cmp_general_fmc1_n_186,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][14]\ => cmp_general_fmc1_n_190,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][15]\ => cmp_general_fmc1_n_194,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][16]\ => cmp_general_fmc1_n_198,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][17]\ => cmp_general_fmc1_n_202,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][18]\ => cmp_general_fmc1_n_206,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][19]\ => cmp_general_fmc1_n_210,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][1]\ => cmp_general_fmc1_n_132,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][20]\ => cmp_general_fmc1_n_214,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][21]\ => cmp_general_fmc1_n_219,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][22]\ => cmp_general_fmc1_n_224,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][23]\ => cmp_general_fmc1_n_229,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][2]\ => cmp_general_fmc1_n_137,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][3]\ => cmp_general_fmc1_n_142,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][4]\ => cmp_general_fmc1_n_147,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][5]\ => cmp_general_fmc1_n_152,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][6]\ => cmp_general_fmc1_n_157,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][7]\ => cmp_general_fmc1_n_162,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][8]\ => cmp_general_fmc1_n_166,
- \fmc_03287_channels[7].gen_chs.data_o_reg[55][9]\ => cmp_general_fmc1_n_170,
- gem_status_vector_i(15 downto 0) => gem_status_vector_i(15 downto 0),
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_araddr(8 downto 0) => s00_axi_araddr(10 downto 2),
- s00_axi_aresetn => s00_axi_aresetn,
- s00_axi_arready => s00_axi_arready,
- s00_axi_arvalid => s00_axi_arvalid,
- s00_axi_awaddr(7 downto 0) => s00_axi_awaddr(9 downto 2),
- s00_axi_awready => s00_axi_awready,
- s00_axi_awvalid => s00_axi_awvalid,
- s00_axi_bready => s00_axi_bready,
- s00_axi_bresp(0) => \^s00_axi_bresp\(1),
- s00_axi_bvalid => s00_axi_bvalid,
- s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
- s00_axi_rready => s00_axi_rready,
- s00_axi_rresp(0) => \^s00_axi_rresp\(1),
- s00_axi_rvalid => s00_axi_rvalid,
- s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
- s00_axi_wready => s00_axi_wready,
- s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
- s00_axi_wvalid => s00_axi_wvalid,
- \s_datao_fmc1[0]\(19 downto 0) => \s_datao_fmc1[0]\(19 downto 0),
- \s_datao_fmc1[4]\(11 downto 0) => \s_datao_fmc1[4]\(19 downto 8),
- \s_datao_fmc2[0]\(19 downto 0) => \s_datao_fmc2[0]\(19 downto 0),
- \s_datao_fmc2[4]\(11 downto 0) => \s_datao_fmc2[4]\(19 downto 8),
- \s_ins_reg[3]\(3) => \s_ins_reg_n_0_[3]\,
- \s_ins_reg[3]\(2) => \s_ins_reg_n_0_[2]\,
- \s_ins_reg[3]\(1) => \s_ins_reg_n_0_[1]\,
- \s_ins_reg[3]\(0) => \s_ins_reg_n_0_[0]\,
- s_tick => s_tick,
- \v_dout_reg[4]\ => cmp_axi4lite_slave_n_530,
- \v_dout_reg[4]_0\ => cmp_axi4lite_slave_n_534,
- \v_dout_reg[5]\ => cmp_axi4lite_slave_n_529,
- \v_dout_reg[5]_0\ => cmp_axi4lite_slave_n_533,
- \v_dout_reg[6]\ => cmp_axi4lite_slave_n_528,
- \v_dout_reg[6]_0\ => cmp_axi4lite_slave_n_532,
- \v_dout_reg[7]\(2) => \data_rw_o[11]\(7),
- \v_dout_reg[7]\(1 downto 0) => \data_rw_o[11]\(2 downto 1),
- \v_dout_reg[7]_0\(2) => \data_rw_o[79]\(7),
- \v_dout_reg[7]_0\(1 downto 0) => \data_rw_o[79]\(2 downto 1),
- \v_dout_reg[7]_1\ => cmp_axi4lite_slave_n_527,
- \v_dout_reg[7]_2\ => cmp_axi4lite_slave_n_531
- );
-cmp_general_fmc1: entity work.system_design_fasec_hwtest_0_0_general_fmc
- port map (
- CO(0) => \gen_spi.cmp_dac7716_spi/p_16_out_7\,
- D(3) => FMC1_GP3_b,
- D(2) => FMC1_GP2_i,
- D(1) => FMC1_GP1_i,
- D(0) => FMC1_GP0_i,
- FMC1_LA_N_b(1 downto 0) => FMC1_LA_N_b(29 downto 28),
- \FMC1_LA_N_b[27]\(7 downto 0) => FMC1_LA_N_b(27 downto 20),
- \FMC1_LA_N_b[32]\(21 downto 20) => FMC1_LA_N_b(32 downto 31),
- \FMC1_LA_N_b[32]\(19 downto 0) => FMC1_LA_N_b(19 downto 0),
- FMC1_LA_P_b(1 downto 0) => FMC1_LA_P_b(29 downto 28),
- \FMC1_LA_P_b[27]\(7 downto 0) => FMC1_LA_P_b(27 downto 20),
- \FMC1_LA_P_b[32]\(21 downto 20) => FMC1_LA_P_b(32 downto 31),
- \FMC1_LA_P_b[32]\(19 downto 0) => FMC1_LA_P_b(19 downto 0),
- Q(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0\(11 downto 0),
- \axi_araddr_reg[2]_rep\ => cmp_axi4lite_slave_n_524,
- \axi_araddr_reg[2]_rep__0\ => cmp_axi4lite_slave_n_522,
- \axi_araddr_reg[2]_rep__1\ => cmp_axi4lite_slave_n_518,
- \axi_araddr_reg[2]_rep__2\ => cmp_axi4lite_slave_n_517,
- \axi_araddr_reg[2]_rep__3\ => cmp_axi4lite_slave_n_220,
- \axi_araddr_reg[3]_rep\ => cmp_axi4lite_slave_n_523,
- \axi_araddr_reg[3]_rep__0\ => cmp_axi4lite_slave_n_521,
- \axi_araddr_reg[3]_rep__1\ => cmp_axi4lite_slave_n_519,
- \axi_araddr_reg[3]_rep__2\ => cmp_axi4lite_slave_n_516,
- \axi_araddr_reg[3]_rep__3\ => cmp_axi4lite_slave_n_219,
- \axi_araddr_reg[4]\(2 downto 0) => axi_araddr(4 downto 2),
- \axi_araddr_reg[4]_rep\ => cmp_axi4lite_slave_n_520,
- \axi_araddr_reg[4]_rep__0\ => cmp_axi4lite_slave_n_509,
- \axi_araddr_reg[4]_rep__1\ => cmp_axi4lite_slave_n_218,
- \axi_rdata_reg[0]\ => cmp_general_fmc1_n_113,
- \axi_rdata_reg[0]_0\ => cmp_general_fmc1_n_126,
- \axi_rdata_reg[0]_1\ => cmp_general_fmc1_n_127,
- \axi_rdata_reg[0]_2\ => cmp_general_fmc1_n_128,
- \axi_rdata_reg[0]_3\ => cmp_general_fmc1_n_129,
- \axi_rdata_reg[10]\ => cmp_general_fmc1_n_173,
- \axi_rdata_reg[10]_0\ => cmp_general_fmc1_n_174,
- \axi_rdata_reg[10]_1\ => cmp_general_fmc1_n_175,
- \axi_rdata_reg[10]_2\ => cmp_general_fmc1_n_176,
- \axi_rdata_reg[11]\ => cmp_general_fmc1_n_177,
- \axi_rdata_reg[11]_0\ => cmp_general_fmc1_n_178,
- \axi_rdata_reg[11]_1\ => cmp_general_fmc1_n_179,
- \axi_rdata_reg[11]_2\ => cmp_general_fmc1_n_180,
- \axi_rdata_reg[12]\ => cmp_general_fmc1_n_181,
- \axi_rdata_reg[12]_0\ => cmp_general_fmc1_n_182,
- \axi_rdata_reg[12]_1\ => cmp_general_fmc1_n_183,
- \axi_rdata_reg[12]_2\ => cmp_general_fmc1_n_184,
- \axi_rdata_reg[13]\ => cmp_general_fmc1_n_185,
- \axi_rdata_reg[13]_0\ => cmp_general_fmc1_n_186,
- \axi_rdata_reg[13]_1\ => cmp_general_fmc1_n_187,
- \axi_rdata_reg[13]_2\ => cmp_general_fmc1_n_188,
- \axi_rdata_reg[14]\ => cmp_general_fmc1_n_189,
- \axi_rdata_reg[14]_0\ => cmp_general_fmc1_n_190,
- \axi_rdata_reg[14]_1\ => cmp_general_fmc1_n_191,
- \axi_rdata_reg[14]_2\ => cmp_general_fmc1_n_192,
- \axi_rdata_reg[15]\ => cmp_general_fmc1_n_193,
- \axi_rdata_reg[15]_0\ => cmp_general_fmc1_n_194,
- \axi_rdata_reg[15]_1\ => cmp_general_fmc1_n_195,
- \axi_rdata_reg[15]_2\ => cmp_general_fmc1_n_196,
- \axi_rdata_reg[16]\ => cmp_general_fmc1_n_197,
- \axi_rdata_reg[16]_0\ => cmp_general_fmc1_n_198,
- \axi_rdata_reg[16]_1\ => cmp_general_fmc1_n_199,
- \axi_rdata_reg[16]_2\ => cmp_general_fmc1_n_200,
- \axi_rdata_reg[17]\ => cmp_general_fmc1_n_201,
- \axi_rdata_reg[17]_0\ => cmp_general_fmc1_n_202,
- \axi_rdata_reg[17]_1\ => cmp_general_fmc1_n_203,
- \axi_rdata_reg[17]_2\ => cmp_general_fmc1_n_204,
- \axi_rdata_reg[18]\ => cmp_general_fmc1_n_205,
- \axi_rdata_reg[18]_0\ => cmp_general_fmc1_n_206,
- \axi_rdata_reg[18]_1\ => cmp_general_fmc1_n_207,
- \axi_rdata_reg[18]_2\ => cmp_general_fmc1_n_208,
- \axi_rdata_reg[19]\ => cmp_general_fmc1_n_209,
- \axi_rdata_reg[19]_0\ => cmp_general_fmc1_n_210,
- \axi_rdata_reg[19]_1\ => cmp_general_fmc1_n_211,
- \axi_rdata_reg[19]_2\ => cmp_general_fmc1_n_212,
- \axi_rdata_reg[1]\ => cmp_general_fmc1_n_130,
- \axi_rdata_reg[1]_0\ => cmp_general_fmc1_n_131,
- \axi_rdata_reg[1]_1\ => cmp_general_fmc1_n_132,
- \axi_rdata_reg[1]_2\ => cmp_general_fmc1_n_133,
- \axi_rdata_reg[1]_3\ => cmp_general_fmc1_n_134,
- \axi_rdata_reg[20]\ => cmp_general_fmc1_n_213,
- \axi_rdata_reg[20]_0\ => cmp_general_fmc1_n_214,
- \axi_rdata_reg[20]_1\ => cmp_general_fmc1_n_215,
- \axi_rdata_reg[20]_2\ => cmp_general_fmc1_n_216,
- \axi_rdata_reg[20]_3\ => cmp_general_fmc1_n_217,
- \axi_rdata_reg[21]\ => cmp_general_fmc1_n_218,
- \axi_rdata_reg[21]_0\ => cmp_general_fmc1_n_219,
- \axi_rdata_reg[21]_1\ => cmp_general_fmc1_n_220,
- \axi_rdata_reg[21]_2\ => cmp_general_fmc1_n_221,
- \axi_rdata_reg[21]_3\ => cmp_general_fmc1_n_222,
- \axi_rdata_reg[22]\ => cmp_general_fmc1_n_223,
- \axi_rdata_reg[22]_0\ => cmp_general_fmc1_n_224,
- \axi_rdata_reg[22]_1\ => cmp_general_fmc1_n_225,
- \axi_rdata_reg[22]_2\ => cmp_general_fmc1_n_226,
- \axi_rdata_reg[22]_3\ => cmp_general_fmc1_n_227,
- \axi_rdata_reg[23]\ => cmp_general_fmc1_n_228,
- \axi_rdata_reg[23]_0\ => cmp_general_fmc1_n_229,
- \axi_rdata_reg[23]_1\ => cmp_general_fmc1_n_230,
- \axi_rdata_reg[23]_2\ => cmp_general_fmc1_n_231,
- \axi_rdata_reg[23]_3\ => cmp_general_fmc1_n_232,
- \axi_rdata_reg[2]\ => cmp_general_fmc1_n_135,
- \axi_rdata_reg[2]_0\ => cmp_general_fmc1_n_136,
- \axi_rdata_reg[2]_1\ => cmp_general_fmc1_n_137,
- \axi_rdata_reg[2]_2\ => cmp_general_fmc1_n_138,
- \axi_rdata_reg[2]_3\ => cmp_general_fmc1_n_139,
- \axi_rdata_reg[31]\(31 downto 0) => \s_datao_fmc1[28]\(31 downto 0),
- \axi_rdata_reg[3]\ => cmp_general_fmc1_n_140,
- \axi_rdata_reg[3]_0\ => cmp_general_fmc1_n_141,
- \axi_rdata_reg[3]_1\ => cmp_general_fmc1_n_142,
- \axi_rdata_reg[3]_2\ => cmp_general_fmc1_n_143,
- \axi_rdata_reg[3]_3\ => cmp_general_fmc1_n_144,
- \axi_rdata_reg[3]_4\(3 downto 0) => \s_datao_fmc1[1]\(3 downto 0),
- \axi_rdata_reg[4]\ => cmp_general_fmc1_n_145,
- \axi_rdata_reg[4]_0\ => cmp_general_fmc1_n_146,
- \axi_rdata_reg[4]_1\ => cmp_general_fmc1_n_147,
- \axi_rdata_reg[4]_2\ => cmp_general_fmc1_n_148,
- \axi_rdata_reg[4]_3\ => cmp_general_fmc1_n_149,
- \axi_rdata_reg[5]\ => cmp_general_fmc1_n_150,
- \axi_rdata_reg[5]_0\ => cmp_general_fmc1_n_151,
- \axi_rdata_reg[5]_1\ => cmp_general_fmc1_n_152,
- \axi_rdata_reg[5]_2\ => cmp_general_fmc1_n_153,
- \axi_rdata_reg[5]_3\ => cmp_general_fmc1_n_154,
- \axi_rdata_reg[6]\ => cmp_general_fmc1_n_155,
- \axi_rdata_reg[6]_0\ => cmp_general_fmc1_n_156,
- \axi_rdata_reg[6]_1\ => cmp_general_fmc1_n_157,
- \axi_rdata_reg[6]_2\ => cmp_general_fmc1_n_158,
- \axi_rdata_reg[6]_3\ => cmp_general_fmc1_n_159,
- \axi_rdata_reg[7]\ => cmp_general_fmc1_n_160,
- \axi_rdata_reg[7]_0\ => cmp_general_fmc1_n_161,
- \axi_rdata_reg[7]_1\ => cmp_general_fmc1_n_162,
- \axi_rdata_reg[7]_2\ => cmp_general_fmc1_n_163,
- \axi_rdata_reg[7]_3\ => cmp_general_fmc1_n_164,
- \axi_rdata_reg[8]\ => cmp_general_fmc1_n_165,
- \axi_rdata_reg[8]_0\ => cmp_general_fmc1_n_166,
- \axi_rdata_reg[8]_1\ => cmp_general_fmc1_n_167,
- \axi_rdata_reg[8]_2\ => cmp_general_fmc1_n_168,
- \axi_rdata_reg[9]\ => cmp_general_fmc1_n_169,
- \axi_rdata_reg[9]_0\ => cmp_general_fmc1_n_170,
- \axi_rdata_reg[9]_1\ => cmp_general_fmc1_n_171,
- \axi_rdata_reg[9]_2\ => cmp_general_fmc1_n_172,
- \data_rw_o_reg[10][4]\ => cmp_axi4lite_slave_n_530,
- \data_rw_o_reg[10][5]\ => cmp_axi4lite_slave_n_529,
- \data_rw_o_reg[10][6]\ => cmp_axi4lite_slave_n_528,
- \data_rw_o_reg[10][7]\ => cmp_axi4lite_slave_n_527,
- \data_rw_o_reg[11][7]\(2) => \data_rw_o[11]\(7),
- \data_rw_o_reg[11][7]\(1 downto 0) => \data_rw_o[11]\(2 downto 1),
- \data_rw_o_reg[16][11]\(11 downto 0) => \data_rw_o[16]\(11 downto 0),
- \data_rw_o_reg[16][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_19_out_4\,
- \data_rw_o_reg[17][11]\(11 downto 0) => \data_rw_o[17]\(11 downto 0),
- \data_rw_o_reg[17][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_18_out_5\,
- \data_rw_o_reg[18][11]\(11 downto 0) => \data_rw_o[18]\(11 downto 0),
- \data_rw_o_reg[18][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_17_out_6\,
- \data_rw_o_reg[19][11]\(11 downto 0) => \data_rw_o[19]\(11 downto 0),
- \data_rw_o_reg[20][11]\(11 downto 0) => \data_rw_o[20]\(11 downto 0),
- \data_rw_o_reg[20][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_15_out_3\,
- \data_rw_o_reg[21][11]\(11 downto 0) => \data_rw_o[21]\(11 downto 0),
- \data_rw_o_reg[21][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_14_out_2\,
- \data_rw_o_reg[22][11]\(11 downto 0) => \data_rw_o[22]\(11 downto 0),
- \data_rw_o_reg[22][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_13_out_1\,
- \data_rw_o_reg[23][11]\(11 downto 0) => \data_rw_o[23]\(11 downto 0),
- \data_rw_o_reg[23][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_12_out_0\,
- \data_rw_o_reg[24][11]\(11 downto 0) => \data_rw_o[24]\(11 downto 0),
- \data_rw_o_reg[25][11]\(11 downto 0) => \data_rw_o[25]\(11 downto 0),
- \data_rw_o_reg[26][11]\(11 downto 0) => \data_rw_o[26]\(11 downto 0),
- \data_rw_o_reg[27][11]\(11 downto 0) => \data_rw_o[27]\(11 downto 0),
- \data_rw_o_reg[28][11]\(11 downto 0) => \data_rw_o[28]\(11 downto 0),
- \data_rw_o_reg[29][11]\(11 downto 0) => \data_rw_o[29]\(11 downto 0),
- \data_rw_o_reg[30][11]\(11 downto 0) => \data_rw_o[30]\(11 downto 0),
- \data_rw_o_reg[31][11]\(11 downto 0) => \data_rw_o[31]\(11 downto 0),
- \data_rw_o_reg[32][11]\(11 downto 0) => \data_rw_o[32]\(11 downto 0),
- \data_rw_o_reg[33][11]\(11 downto 0) => \data_rw_o[33]\(11 downto 0),
- \data_rw_o_reg[34][11]\(11 downto 0) => \data_rw_o[34]\(11 downto 0),
- \data_rw_o_reg[35][11]\(11 downto 0) => \data_rw_o[35]\(11 downto 0),
- fmc2_intr => fmc2_intr,
- fmc2_intr_led => fmc2_intr_led,
- intr_led_o => intr_led_o,
- intr_o => intr_o,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_count_reg(11 downto 0) => \s_datao_fmc1[4]\(19 downto 8),
- \s_datao_fmc1[0]\(19 downto 0) => \s_datao_fmc1[0]\(19 downto 0),
- \s_tx_data_reg[111]\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[0].s_reqs_reg[0][value]__0\(11 downto 0),
- \s_tx_data_reg[15]\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[1].s_reqs_reg[1][value]__0\(11 downto 0),
- \s_tx_data_reg[15]_0\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[2].s_reqs_reg[2][value]__0\(11 downto 0),
- \s_tx_data_reg[39]\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[3].s_reqs_reg[7][value]__0\(11 downto 0),
- \s_tx_data_reg[39]_0\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[0].s_reqs_reg[4][value]__0\(11 downto 0),
- \s_tx_data_reg[39]_1\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[1].s_reqs_reg[5][value]__0\(11 downto 0),
- \s_tx_data_reg[39]_2\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[2].s_reqs_reg[6][value]__0\(11 downto 0)
- );
-cmp_general_fmc2: entity work.system_design_fasec_hwtest_0_0_general_fmc_0
- port map (
- D(3) => FMC2_GP3_b,
- D(2) => FMC2_GP2_i,
- D(1) => FMC2_GP1_i,
- D(0) => FMC2_GP0_i,
- FMC2_LA_N_b(1 downto 0) => FMC2_LA_N_b(29 downto 28),
- \FMC2_LA_N_b[27]\(7 downto 0) => FMC2_LA_N_b(27 downto 20),
- \FMC2_LA_N_b[32]\(21 downto 20) => FMC2_LA_N_b(32 downto 31),
- \FMC2_LA_N_b[32]\(19 downto 0) => FMC2_LA_N_b(19 downto 0),
- FMC2_LA_P_b(1 downto 0) => FMC2_LA_P_b(29 downto 28),
- \FMC2_LA_P_b[27]\(7 downto 0) => FMC2_LA_P_b(27 downto 20),
- \FMC2_LA_P_b[32]\(21 downto 20) => FMC2_LA_P_b(32 downto 31),
- \FMC2_LA_P_b[32]\(19 downto 0) => FMC2_LA_P_b(19 downto 0),
- Q(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[3].s_reqs_reg[3][value]__0_15\(11 downto 0),
- \axi_araddr_reg[2]_rep\ => cmp_axi4lite_slave_n_524,
- \axi_araddr_reg[2]_rep__0\ => cmp_axi4lite_slave_n_522,
- \axi_araddr_reg[2]_rep__1\ => cmp_axi4lite_slave_n_518,
- \axi_araddr_reg[2]_rep__2\ => cmp_axi4lite_slave_n_517,
- \axi_araddr_reg[2]_rep__3\ => cmp_axi4lite_slave_n_220,
- \axi_araddr_reg[3]_rep\ => cmp_axi4lite_slave_n_523,
- \axi_araddr_reg[3]_rep__0\ => cmp_axi4lite_slave_n_521,
- \axi_araddr_reg[3]_rep__1\ => cmp_axi4lite_slave_n_519,
- \axi_araddr_reg[3]_rep__2\ => cmp_axi4lite_slave_n_516,
- \axi_araddr_reg[3]_rep__3\ => cmp_axi4lite_slave_n_219,
- \axi_araddr_reg[4]_rep\ => cmp_axi4lite_slave_n_520,
- \axi_araddr_reg[4]_rep__0\ => cmp_axi4lite_slave_n_509,
- \axi_araddr_reg[4]_rep__1\ => cmp_axi4lite_slave_n_218,
- \axi_araddr_reg[5]\(3 downto 0) => axi_araddr(5 downto 2),
- \axi_araddr_reg[5]_rep\ => cmp_axi4lite_slave_n_217,
- \axi_rdata_reg[0]\ => cmp_general_fmc2_n_114,
- \axi_rdata_reg[0]_0\ => cmp_general_fmc2_n_127,
- \axi_rdata_reg[0]_1\ => cmp_general_fmc2_n_128,
- \axi_rdata_reg[10]\ => cmp_general_fmc2_n_154,
- \axi_rdata_reg[10]_0\ => cmp_general_fmc2_n_155,
- \axi_rdata_reg[11]\ => cmp_general_fmc2_n_156,
- \axi_rdata_reg[11]_0\ => cmp_general_fmc2_n_157,
- \axi_rdata_reg[12]\ => cmp_general_fmc2_n_158,
- \axi_rdata_reg[12]_0\ => cmp_general_fmc2_n_159,
- \axi_rdata_reg[13]\ => cmp_general_fmc2_n_160,
- \axi_rdata_reg[13]_0\ => cmp_general_fmc2_n_161,
- \axi_rdata_reg[14]\ => cmp_general_fmc2_n_162,
- \axi_rdata_reg[14]_0\ => cmp_general_fmc2_n_163,
- \axi_rdata_reg[15]\ => cmp_general_fmc2_n_164,
- \axi_rdata_reg[15]_0\ => cmp_general_fmc2_n_165,
- \axi_rdata_reg[16]\ => cmp_general_fmc2_n_166,
- \axi_rdata_reg[16]_0\ => cmp_general_fmc2_n_167,
- \axi_rdata_reg[17]\ => cmp_general_fmc2_n_168,
- \axi_rdata_reg[17]_0\ => cmp_general_fmc2_n_169,
- \axi_rdata_reg[18]\ => cmp_general_fmc2_n_170,
- \axi_rdata_reg[18]_0\ => cmp_general_fmc2_n_171,
- \axi_rdata_reg[19]\ => cmp_general_fmc2_n_172,
- \axi_rdata_reg[19]_0\ => cmp_general_fmc2_n_173,
- \axi_rdata_reg[1]\ => cmp_general_fmc2_n_129,
- \axi_rdata_reg[1]_0\ => cmp_general_fmc2_n_130,
- \axi_rdata_reg[1]_1\ => cmp_general_fmc2_n_131,
- \axi_rdata_reg[20]\ => cmp_general_fmc2_n_174,
- \axi_rdata_reg[20]_0\ => cmp_general_fmc2_n_175,
- \axi_rdata_reg[20]_1\ => cmp_general_fmc2_n_176,
- \axi_rdata_reg[21]\ => cmp_general_fmc2_n_177,
- \axi_rdata_reg[21]_0\ => cmp_general_fmc2_n_178,
- \axi_rdata_reg[21]_1\ => cmp_general_fmc2_n_179,
- \axi_rdata_reg[22]\ => cmp_general_fmc2_n_180,
- \axi_rdata_reg[22]_0\ => cmp_general_fmc2_n_181,
- \axi_rdata_reg[22]_1\ => cmp_general_fmc2_n_182,
- \axi_rdata_reg[23]\ => cmp_general_fmc2_n_183,
- \axi_rdata_reg[23]_0\ => cmp_general_fmc2_n_184,
- \axi_rdata_reg[23]_1\ => cmp_general_fmc2_n_185,
- \axi_rdata_reg[2]\ => cmp_general_fmc2_n_132,
- \axi_rdata_reg[2]_0\ => cmp_general_fmc2_n_133,
- \axi_rdata_reg[2]_1\ => cmp_general_fmc2_n_134,
- \axi_rdata_reg[31]\(31 downto 0) => \s_datao_fmc2[28]\(31 downto 0),
- \axi_rdata_reg[3]\ => cmp_general_fmc2_n_135,
- \axi_rdata_reg[3]_0\ => cmp_general_fmc2_n_136,
- \axi_rdata_reg[3]_1\ => cmp_general_fmc2_n_137,
- \axi_rdata_reg[3]_2\(3 downto 0) => \s_datao_fmc2[1]\(3 downto 0),
- \axi_rdata_reg[4]\ => cmp_general_fmc2_n_138,
- \axi_rdata_reg[4]_0\ => cmp_general_fmc2_n_139,
- \axi_rdata_reg[4]_1\ => cmp_general_fmc2_n_140,
- \axi_rdata_reg[5]\ => cmp_general_fmc2_n_141,
- \axi_rdata_reg[5]_0\ => cmp_general_fmc2_n_142,
- \axi_rdata_reg[5]_1\ => cmp_general_fmc2_n_143,
- \axi_rdata_reg[6]\ => cmp_general_fmc2_n_144,
- \axi_rdata_reg[6]_0\ => cmp_general_fmc2_n_145,
- \axi_rdata_reg[6]_1\ => cmp_general_fmc2_n_146,
- \axi_rdata_reg[7]\ => cmp_general_fmc2_n_147,
- \axi_rdata_reg[7]_0\ => cmp_general_fmc2_n_148,
- \axi_rdata_reg[7]_1\ => cmp_general_fmc2_n_149,
- \axi_rdata_reg[8]\ => cmp_general_fmc2_n_150,
- \axi_rdata_reg[8]_0\ => cmp_general_fmc2_n_151,
- \axi_rdata_reg[9]\ => cmp_general_fmc2_n_152,
- \axi_rdata_reg[9]_0\ => cmp_general_fmc2_n_153,
- \data_rw_o_reg[100][11]\(11 downto 0) => \data_rw_o[100]\(11 downto 0),
- \data_rw_o_reg[101][11]\(11 downto 0) => \data_rw_o[101]\(11 downto 0),
- \data_rw_o_reg[102][11]\(11 downto 0) => \data_rw_o[102]\(11 downto 0),
- \data_rw_o_reg[103][11]\(11 downto 0) => \data_rw_o[103]\(11 downto 0),
- \data_rw_o_reg[78][4]\ => cmp_axi4lite_slave_n_534,
- \data_rw_o_reg[78][5]\ => cmp_axi4lite_slave_n_533,
- \data_rw_o_reg[78][6]\ => cmp_axi4lite_slave_n_532,
- \data_rw_o_reg[78][7]\ => cmp_axi4lite_slave_n_531,
- \data_rw_o_reg[79][7]\(2) => \data_rw_o[79]\(7),
- \data_rw_o_reg[79][7]\(1 downto 0) => \data_rw_o[79]\(2 downto 1),
- \data_rw_o_reg[84][11]\(11 downto 0) => \data_rw_o[84]\(11 downto 0),
- \data_rw_o_reg[84][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_19_out\,
- \data_rw_o_reg[85][11]\(11 downto 0) => \data_rw_o[85]\(11 downto 0),
- \data_rw_o_reg[85][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_18_out\,
- \data_rw_o_reg[86][11]\(11 downto 0) => \data_rw_o[86]\(11 downto 0),
- \data_rw_o_reg[86][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_17_out\,
- \data_rw_o_reg[87][11]\(11 downto 0) => \data_rw_o[87]\(11 downto 0),
- \data_rw_o_reg[87][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_16_out\,
- \data_rw_o_reg[88][11]\(11 downto 0) => \data_rw_o[88]\(11 downto 0),
- \data_rw_o_reg[88][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_15_out\,
- \data_rw_o_reg[89][11]\(11 downto 0) => \data_rw_o[89]\(11 downto 0),
- \data_rw_o_reg[89][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_14_out\,
- \data_rw_o_reg[90][11]\(11 downto 0) => \data_rw_o[90]\(11 downto 0),
- \data_rw_o_reg[90][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_13_out\,
- \data_rw_o_reg[91][11]\(11 downto 0) => \data_rw_o[91]\(11 downto 0),
- \data_rw_o_reg[91][11]_0\(0) => \gen_spi.cmp_dac7716_spi/p_12_out\,
- \data_rw_o_reg[92][11]\(11 downto 0) => \data_rw_o[92]\(11 downto 0),
- \data_rw_o_reg[93][11]\(11 downto 0) => \data_rw_o[93]\(11 downto 0),
- \data_rw_o_reg[94][11]\(11 downto 0) => \data_rw_o[94]\(11 downto 0),
- \data_rw_o_reg[95][11]\(11 downto 0) => \data_rw_o[95]\(11 downto 0),
- \data_rw_o_reg[96][11]\(11 downto 0) => \data_rw_o[96]\(11 downto 0),
- \data_rw_o_reg[97][11]\(11 downto 0) => \data_rw_o[97]\(11 downto 0),
- \data_rw_o_reg[98][11]\(11 downto 0) => \data_rw_o[98]\(11 downto 0),
- \data_rw_o_reg[99][11]\(11 downto 0) => \data_rw_o[99]\(11 downto 0),
- fmc2_intr => fmc2_intr,
- fmc2_intr_led => fmc2_intr_led,
- rst_i => rst_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_aresetn => s00_axi_aresetn,
- s_count_reg(11 downto 0) => \s_datao_fmc2[4]\(19 downto 8),
- \s_datao_fmc2[0]\(19 downto 0) => \s_datao_fmc2[0]\(19 downto 0),
- \s_tx_data_reg[111]\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[0].s_reqs_reg[0][value]__0_14\(11 downto 0),
- \s_tx_data_reg[15]\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[1].s_reqs_reg[1][value]__0_13\(11 downto 0),
- \s_tx_data_reg[15]_0\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[0].[2].s_reqs_reg[2][value]__0_12\(11 downto 0),
- \s_tx_data_reg[39]\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[3].s_reqs_reg[7][value]__0_11\(11 downto 0),
- \s_tx_data_reg[39]_0\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[0].s_reqs_reg[4][value]__0_10\(11 downto 0),
- \s_tx_data_reg[39]_1\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[1].s_reqs_reg[5][value]__0_9\(11 downto 0),
- \s_tx_data_reg[39]_2\(11 downto 0) => \gen_spi.cmp_dac7716_spi/[1].[2].s_reqs_reg[6][value]__0_8\(11 downto 0)
- );
-cmp_watchdog: entity work.system_design_fasec_hwtest_0_0_clockDivider
- port map (
- ps_clk_i => ps_clk_i,
- rst_i => rst_i,
- watchdog_pl_o => watchdog_pl_o
- );
-\s_ins_reg[0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => v_ins(0),
- Q => \s_ins_reg_n_0_[0]\,
- R => '0'
- );
-\s_ins_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => v_ins(1),
- Q => \s_ins_reg_n_0_[1]\,
- R => '0'
- );
-\s_ins_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => v_ins(2),
- Q => \s_ins_reg_n_0_[2]\,
- R => '0'
- );
-\s_ins_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => v_ins(3),
- Q => \s_ins_reg_n_0_[3]\,
- R => '0'
- );
-s_led_line_i_1: unisim.vcomponents.LUT5
- generic map(
- INIT => X"77777775"
- )
- port map (
- I0 => p_2_in,
- I1 => \s_leds[3]_i_5_n_0\,
- I2 => \^led_line_pl_o\,
- I3 => s_led_line_i_2_n_0,
- I4 => \s_leds[3]_i_4_n_0\,
- O => s_led_line_i_1_n_0
- );
-s_led_line_i_2: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFAC"
- )
- port map (
- I0 => v_shift(3),
- I1 => v_shift(5),
- I2 => s_tick,
- I3 => v_shift(4),
- O => s_led_line_i_2_n_0
- );
-s_led_line_reg: unisim.vcomponents.FDRE
- generic map(
- INIT => '1'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => s_led_line_i_1_n_0,
- Q => \^led_line_pl_o\,
- R => '0'
- );
-\s_leds[0]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"B8B800FF00000000"
- )
- port map (
- I0 => v_shift(7),
- I1 => s_tick,
- I2 => v_shift(0),
- I3 => p_0_in(0),
- I4 => \s_leds[3]_i_5_n_0\,
- I5 => p_2_in,
- O => \s_leds[0]_i_1_n_0\
- );
-\s_leds[1]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"B8B800FF00000000"
- )
- port map (
- I0 => v_shift(0),
- I1 => s_tick,
- I2 => v_shift(1),
- I3 => p_0_in(1),
- I4 => \s_leds[3]_i_5_n_0\,
- I5 => p_2_in,
- O => \s_leds[1]_i_1_n_0\
- );
-\s_leds[2]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"B8B800FF00000000"
- )
- port map (
- I0 => v_shift(1),
- I1 => s_tick,
- I2 => v_shift(2),
- I3 => p_0_in(2),
- I4 => \s_leds[3]_i_5_n_0\,
- I5 => p_2_in,
- O => \s_leds[2]_i_1_n_0\
- );
-\s_leds[3]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFFFEEFA"
- )
- port map (
- I0 => \s_leds[3]_i_3_n_0\,
- I1 => v_shift(3),
- I2 => v_shift(5),
- I3 => s_tick,
- I4 => v_shift(4),
- I5 => \s_leds[3]_i_4_n_0\,
- O => \s_leds[3]_i_1_n_0\
- );
-\s_leds[3]_i_2\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"B8B800FF00000000"
- )
- port map (
- I0 => v_shift(2),
- I1 => s_tick,
- I2 => v_shift(3),
- I3 => p_0_in(3),
- I4 => \s_leds[3]_i_5_n_0\,
- I5 => p_2_in,
- O => \s_leds[3]_i_2_n_0\
- );
-\s_leds[3]_i_3\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"B"
- )
- port map (
- I0 => \s_leds[3]_i_5_n_0\,
- I1 => p_2_in,
- O => \s_leds[3]_i_3_n_0\
- );
-\s_leds[3]_i_4\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FECE"
- )
- port map (
- I0 => v_shift(7),
- I1 => v_shift(6),
- I2 => s_tick,
- I3 => v_shift(5),
- O => \s_leds[3]_i_4_n_0\
- );
-\s_leds[3]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFEFFFEFFFFFFFC"
- )
- port map (
- I0 => v_shift(7),
- I1 => v_shift(1),
- I2 => v_shift(2),
- I3 => v_shift(0),
- I4 => v_shift(3),
- I5 => s_tick,
- O => \s_leds[3]_i_5_n_0\
- );
-\s_leds_reg[0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => \s_leds[3]_i_1_n_0\,
- D => \s_leds[0]_i_1_n_0\,
- Q => led_col_pl_o(0),
- R => '0'
- );
-\s_leds_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => \s_leds[3]_i_1_n_0\,
- D => \s_leds[1]_i_1_n_0\,
- Q => led_col_pl_o(1),
- R => '0'
- );
-\s_leds_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => \s_leds[3]_i_1_n_0\,
- D => \s_leds[2]_i_1_n_0\,
- Q => led_col_pl_o(2),
- R => '0'
- );
-\s_leds_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => \s_leds[3]_i_1_n_0\,
- D => \s_leds[3]_i_2_n_0\,
- Q => led_col_pl_o(3),
- R => '0'
- );
-s_tick_i_1: unisim.vcomponents.LUT2
- generic map(
- INIT => X"6"
- )
- port map (
- I0 => clear,
- I1 => s_tick,
- O => s_tick_i_1_n_0
- );
-s_tick_reg: unisim.vcomponents.FDRE
- port map (
- C => ps_clk_i,
- CE => '1',
- D => s_tick_i_1_n_0,
- Q => s_tick,
- R => '0'
- );
-\v_cntr[0]_i_1\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFFFFFFFFEEFEEE"
- )
- port map (
- I0 => \v_cntr[0]_i_3_n_0\,
- I1 => \v_cntr[0]_i_4_n_0\,
- I2 => v_cntr_reg(24),
- I3 => v_cntr_reg(25),
- I4 => v_cntr_reg(23),
- I5 => \v_cntr[0]_i_5_n_0\,
- O => clear
- );
-\v_cntr[0]_i_10\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"80"
- )
- port map (
- I0 => v_cntr_reg(22),
- I1 => v_cntr_reg(21),
- I2 => v_cntr_reg(25),
- O => \v_cntr[0]_i_10_n_0\
- );
-\v_cntr[0]_i_11\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"EAEAEAAA00000000"
- )
- port map (
- I0 => v_cntr_reg(13),
- I1 => v_cntr_reg(12),
- I2 => v_cntr_reg(11),
- I3 => v_cntr_reg(10),
- I4 => v_cntr_reg(9),
- I5 => v_cntr_reg(14),
- O => \v_cntr[0]_i_11_n_0\
- );
-\v_cntr[0]_i_3\: unisim.vcomponents.LUT4
- generic map(
- INIT => X"FFFE"
- )
- port map (
- I0 => v_cntr_reg(27),
- I1 => v_cntr_reg(26),
- I2 => v_cntr_reg(29),
- I3 => v_cntr_reg(28),
- O => \v_cntr[0]_i_3_n_0\
- );
-\v_cntr[0]_i_4\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"88888880"
- )
- port map (
- I0 => v_cntr_reg(17),
- I1 => \v_cntr[0]_i_10_n_0\,
- I2 => v_cntr_reg(15),
- I3 => v_cntr_reg(16),
- I4 => \v_cntr[0]_i_11_n_0\,
- O => \v_cntr[0]_i_4_n_0\
- );
-\v_cntr[0]_i_5\: unisim.vcomponents.LUT6
- generic map(
- INIT => X"FFFCFFFCFFFCFEFC"
- )
- port map (
- I0 => v_cntr_reg(18),
- I1 => v_cntr_reg(30),
- I2 => v_cntr_reg(31),
- I3 => \v_cntr[0]_i_10_n_0\,
- I4 => v_cntr_reg(20),
- I5 => v_cntr_reg(19),
- O => \v_cntr[0]_i_5_n_0\
- );
-\v_cntr[0]_i_9\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => \v_cntr_reg_n_0_[0]\,
- O => \v_cntr[0]_i_9_n_0\
- );
-\v_cntr_reg[0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[0]_i_2_n_7\,
- Q => \v_cntr_reg_n_0_[0]\,
- R => clear
- );
-\v_cntr_reg[0]_i_2\: unisim.vcomponents.CARRY4
- port map (
- CI => '0',
- CO(3) => \v_cntr_reg[0]_i_2_n_0\,
- CO(2) => \v_cntr_reg[0]_i_2_n_1\,
- CO(1) => \v_cntr_reg[0]_i_2_n_2\,
- CO(0) => \v_cntr_reg[0]_i_2_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0001",
- O(3) => \v_cntr_reg[0]_i_2_n_4\,
- O(2) => \v_cntr_reg[0]_i_2_n_5\,
- O(1) => \v_cntr_reg[0]_i_2_n_6\,
- O(0) => \v_cntr_reg[0]_i_2_n_7\,
- S(3) => \v_cntr_reg_n_0_[3]\,
- S(2) => \v_cntr_reg_n_0_[2]\,
- S(1) => \v_cntr_reg_n_0_[1]\,
- S(0) => \v_cntr[0]_i_9_n_0\
- );
-\v_cntr_reg[10]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[8]_i_1_n_5\,
- Q => v_cntr_reg(10),
- R => clear
- );
-\v_cntr_reg[11]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[8]_i_1_n_4\,
- Q => v_cntr_reg(11),
- R => clear
- );
-\v_cntr_reg[12]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[12]_i_1_n_7\,
- Q => v_cntr_reg(12),
- R => clear
- );
-\v_cntr_reg[12]_i_1\: unisim.vcomponents.CARRY4
- port map (
- CI => \v_cntr_reg[8]_i_1_n_0\,
- CO(3) => \v_cntr_reg[12]_i_1_n_0\,
- CO(2) => \v_cntr_reg[12]_i_1_n_1\,
- CO(1) => \v_cntr_reg[12]_i_1_n_2\,
- CO(0) => \v_cntr_reg[12]_i_1_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3) => \v_cntr_reg[12]_i_1_n_4\,
- O(2) => \v_cntr_reg[12]_i_1_n_5\,
- O(1) => \v_cntr_reg[12]_i_1_n_6\,
- O(0) => \v_cntr_reg[12]_i_1_n_7\,
- S(3 downto 0) => v_cntr_reg(15 downto 12)
- );
-\v_cntr_reg[13]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[12]_i_1_n_6\,
- Q => v_cntr_reg(13),
- R => clear
- );
-\v_cntr_reg[14]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[12]_i_1_n_5\,
- Q => v_cntr_reg(14),
- R => clear
- );
-\v_cntr_reg[15]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[12]_i_1_n_4\,
- Q => v_cntr_reg(15),
- R => clear
- );
-\v_cntr_reg[16]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[16]_i_1_n_7\,
- Q => v_cntr_reg(16),
- R => clear
- );
-\v_cntr_reg[16]_i_1\: unisim.vcomponents.CARRY4
- port map (
- CI => \v_cntr_reg[12]_i_1_n_0\,
- CO(3) => \v_cntr_reg[16]_i_1_n_0\,
- CO(2) => \v_cntr_reg[16]_i_1_n_1\,
- CO(1) => \v_cntr_reg[16]_i_1_n_2\,
- CO(0) => \v_cntr_reg[16]_i_1_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3) => \v_cntr_reg[16]_i_1_n_4\,
- O(2) => \v_cntr_reg[16]_i_1_n_5\,
- O(1) => \v_cntr_reg[16]_i_1_n_6\,
- O(0) => \v_cntr_reg[16]_i_1_n_7\,
- S(3 downto 0) => v_cntr_reg(19 downto 16)
- );
-\v_cntr_reg[17]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[16]_i_1_n_6\,
- Q => v_cntr_reg(17),
- R => clear
- );
-\v_cntr_reg[18]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[16]_i_1_n_5\,
- Q => v_cntr_reg(18),
- R => clear
- );
-\v_cntr_reg[19]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[16]_i_1_n_4\,
- Q => v_cntr_reg(19),
- R => clear
- );
-\v_cntr_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[0]_i_2_n_6\,
- Q => \v_cntr_reg_n_0_[1]\,
- R => clear
- );
-\v_cntr_reg[20]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[20]_i_1_n_7\,
- Q => v_cntr_reg(20),
- R => clear
- );
-\v_cntr_reg[20]_i_1\: unisim.vcomponents.CARRY4
- port map (
- CI => \v_cntr_reg[16]_i_1_n_0\,
- CO(3) => \v_cntr_reg[20]_i_1_n_0\,
- CO(2) => \v_cntr_reg[20]_i_1_n_1\,
- CO(1) => \v_cntr_reg[20]_i_1_n_2\,
- CO(0) => \v_cntr_reg[20]_i_1_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3) => \v_cntr_reg[20]_i_1_n_4\,
- O(2) => \v_cntr_reg[20]_i_1_n_5\,
- O(1) => \v_cntr_reg[20]_i_1_n_6\,
- O(0) => \v_cntr_reg[20]_i_1_n_7\,
- S(3 downto 0) => v_cntr_reg(23 downto 20)
- );
-\v_cntr_reg[21]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[20]_i_1_n_6\,
- Q => v_cntr_reg(21),
- R => clear
- );
-\v_cntr_reg[22]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[20]_i_1_n_5\,
- Q => v_cntr_reg(22),
- R => clear
- );
-\v_cntr_reg[23]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[20]_i_1_n_4\,
- Q => v_cntr_reg(23),
- R => clear
- );
-\v_cntr_reg[24]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[24]_i_1_n_7\,
- Q => v_cntr_reg(24),
- R => clear
- );
-\v_cntr_reg[24]_i_1\: unisim.vcomponents.CARRY4
- port map (
- CI => \v_cntr_reg[20]_i_1_n_0\,
- CO(3) => \v_cntr_reg[24]_i_1_n_0\,
- CO(2) => \v_cntr_reg[24]_i_1_n_1\,
- CO(1) => \v_cntr_reg[24]_i_1_n_2\,
- CO(0) => \v_cntr_reg[24]_i_1_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3) => \v_cntr_reg[24]_i_1_n_4\,
- O(2) => \v_cntr_reg[24]_i_1_n_5\,
- O(1) => \v_cntr_reg[24]_i_1_n_6\,
- O(0) => \v_cntr_reg[24]_i_1_n_7\,
- S(3 downto 0) => v_cntr_reg(27 downto 24)
- );
-\v_cntr_reg[25]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[24]_i_1_n_6\,
- Q => v_cntr_reg(25),
- R => clear
- );
-\v_cntr_reg[26]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[24]_i_1_n_5\,
- Q => v_cntr_reg(26),
- R => clear
- );
-\v_cntr_reg[27]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[24]_i_1_n_4\,
- Q => v_cntr_reg(27),
- R => clear
- );
-\v_cntr_reg[28]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[28]_i_1_n_7\,
- Q => v_cntr_reg(28),
- R => clear
- );
-\v_cntr_reg[28]_i_1\: unisim.vcomponents.CARRY4
- port map (
- CI => \v_cntr_reg[24]_i_1_n_0\,
- CO(3) => \NLW_v_cntr_reg[28]_i_1_CO_UNCONNECTED\(3),
- CO(2) => \v_cntr_reg[28]_i_1_n_1\,
- CO(1) => \v_cntr_reg[28]_i_1_n_2\,
- CO(0) => \v_cntr_reg[28]_i_1_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3) => \v_cntr_reg[28]_i_1_n_4\,
- O(2) => \v_cntr_reg[28]_i_1_n_5\,
- O(1) => \v_cntr_reg[28]_i_1_n_6\,
- O(0) => \v_cntr_reg[28]_i_1_n_7\,
- S(3 downto 0) => v_cntr_reg(31 downto 28)
- );
-\v_cntr_reg[29]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[28]_i_1_n_6\,
- Q => v_cntr_reg(29),
- R => clear
- );
-\v_cntr_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[0]_i_2_n_5\,
- Q => \v_cntr_reg_n_0_[2]\,
- R => clear
- );
-\v_cntr_reg[30]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[28]_i_1_n_5\,
- Q => v_cntr_reg(30),
- R => clear
- );
-\v_cntr_reg[31]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[28]_i_1_n_4\,
- Q => v_cntr_reg(31),
- R => clear
- );
-\v_cntr_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[0]_i_2_n_4\,
- Q => \v_cntr_reg_n_0_[3]\,
- R => clear
- );
-\v_cntr_reg[4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[4]_i_1_n_7\,
- Q => \v_cntr_reg_n_0_[4]\,
- R => clear
- );
-\v_cntr_reg[4]_i_1\: unisim.vcomponents.CARRY4
- port map (
- CI => \v_cntr_reg[0]_i_2_n_0\,
- CO(3) => \v_cntr_reg[4]_i_1_n_0\,
- CO(2) => \v_cntr_reg[4]_i_1_n_1\,
- CO(1) => \v_cntr_reg[4]_i_1_n_2\,
- CO(0) => \v_cntr_reg[4]_i_1_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3) => \v_cntr_reg[4]_i_1_n_4\,
- O(2) => \v_cntr_reg[4]_i_1_n_5\,
- O(1) => \v_cntr_reg[4]_i_1_n_6\,
- O(0) => \v_cntr_reg[4]_i_1_n_7\,
- S(3) => \v_cntr_reg_n_0_[7]\,
- S(2) => \v_cntr_reg_n_0_[6]\,
- S(1) => \v_cntr_reg_n_0_[5]\,
- S(0) => \v_cntr_reg_n_0_[4]\
- );
-\v_cntr_reg[5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[4]_i_1_n_6\,
- Q => \v_cntr_reg_n_0_[5]\,
- R => clear
- );
-\v_cntr_reg[6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[4]_i_1_n_5\,
- Q => \v_cntr_reg_n_0_[6]\,
- R => clear
- );
-\v_cntr_reg[7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[4]_i_1_n_4\,
- Q => \v_cntr_reg_n_0_[7]\,
- R => clear
- );
-\v_cntr_reg[8]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[8]_i_1_n_7\,
- Q => \v_cntr_reg_n_0_[8]\,
- R => clear
- );
-\v_cntr_reg[8]_i_1\: unisim.vcomponents.CARRY4
- port map (
- CI => \v_cntr_reg[4]_i_1_n_0\,
- CO(3) => \v_cntr_reg[8]_i_1_n_0\,
- CO(2) => \v_cntr_reg[8]_i_1_n_1\,
- CO(1) => \v_cntr_reg[8]_i_1_n_2\,
- CO(0) => \v_cntr_reg[8]_i_1_n_3\,
- CYINIT => '0',
- DI(3 downto 0) => B"0000",
- O(3) => \v_cntr_reg[8]_i_1_n_4\,
- O(2) => \v_cntr_reg[8]_i_1_n_5\,
- O(1) => \v_cntr_reg[8]_i_1_n_6\,
- O(0) => \v_cntr_reg[8]_i_1_n_7\,
- S(3 downto 1) => v_cntr_reg(11 downto 9),
- S(0) => \v_cntr_reg_n_0_[8]\
- );
-\v_cntr_reg[9]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_cntr_reg[8]_i_1_n_6\,
- Q => v_cntr_reg(9),
- R => clear
- );
-\v_ins[2]_i_1\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => dig_in3_n_i,
- O => p_0_out(2)
- );
-\v_ins[3]_i_1\: unisim.vcomponents.LUT1
- generic map(
- INIT => X"1"
- )
- port map (
- I0 => dig_in4_n_i,
- O => p_0_out(3)
- );
-\v_ins_reg[0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => dig_in1_i,
- Q => v_ins(0),
- R => '0'
- );
-\v_ins_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => dig_in2_i,
- Q => v_ins(1),
- R => '0'
- );
-\v_ins_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => p_0_out(2),
- Q => v_ins(2),
- R => '0'
- );
-\v_ins_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => p_0_out(3),
- Q => v_ins(3),
- R => '0'
- );
-\v_pbreg_reg[0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => pb_gp_n_i,
- Q => \v_pbreg_reg_n_0_[0]\,
- R => '0'
- );
-\v_pbreg_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_pbreg_reg_n_0_[0]\,
- Q => p_2_in,
- R => '0'
- );
-\v_shift[0]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => v_shift(7),
- I1 => s_tick,
- I2 => v_shift(0),
- O => \v_shift[0]_i_1_n_0\
- );
-\v_shift[1]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => v_shift(0),
- I1 => s_tick,
- I2 => v_shift(1),
- O => \v_shift[1]_i_1_n_0\
- );
-\v_shift[2]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => v_shift(1),
- I1 => s_tick,
- I2 => v_shift(2),
- O => \v_shift[2]_i_1_n_0\
- );
-\v_shift[3]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => v_shift(2),
- I1 => s_tick,
- I2 => v_shift(3),
- O => \v_shift[3]_i_1_n_0\
- );
-\v_shift[4]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => v_shift(3),
- I1 => s_tick,
- I2 => v_shift(4),
- O => p_0_in(0)
- );
-\v_shift[5]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => v_shift(4),
- I1 => s_tick,
- I2 => v_shift(5),
- O => p_0_in(1)
- );
-\v_shift[6]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => v_shift(5),
- I1 => s_tick,
- I2 => v_shift(6),
- O => p_0_in(2)
- );
-\v_shift[7]_i_1\: unisim.vcomponents.LUT3
- generic map(
- INIT => X"B8"
- )
- port map (
- I0 => v_shift(6),
- I1 => s_tick,
- I2 => v_shift(7),
- O => p_0_in(3)
- );
-\v_shift_reg[0]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '1'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_shift[0]_i_1_n_0\,
- Q => v_shift(0),
- R => '0'
- );
-\v_shift_reg[1]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_shift[1]_i_1_n_0\,
- Q => v_shift(1),
- R => '0'
- );
-\v_shift_reg[2]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_shift[2]_i_1_n_0\,
- Q => v_shift(2),
- R => '0'
- );
-\v_shift_reg[3]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => \v_shift[3]_i_1_n_0\,
- Q => v_shift(3),
- R => '0'
- );
-\v_shift_reg[4]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => p_0_in(0),
- Q => v_shift(4),
- R => '0'
- );
-\v_shift_reg[5]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => p_0_in(1),
- Q => v_shift(5),
- R => '0'
- );
-\v_shift_reg[6]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => p_0_in(2),
- Q => v_shift(6),
- R => '0'
- );
-\v_shift_reg[7]\: unisim.vcomponents.FDRE
- generic map(
- INIT => '0'
- )
- port map (
- C => ps_clk_i,
- CE => '1',
- D => p_0_in(3),
- Q => v_shift(7),
- R => '0'
- );
-end STRUCTURE;
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity system_design_fasec_hwtest_0_0 is
- port (
- ps_clk_i : in STD_LOGIC;
- osc100_clk_i : in STD_LOGIC;
- FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC2_PRSNTM2C_n_i : in STD_LOGIC;
- FMC2_CLK0M2C_P_i : in STD_LOGIC;
- FMC2_CLK0M2C_N_i : in STD_LOGIC;
- FMC2_CLK0C2M_P_o : out STD_LOGIC;
- FMC2_CLK0C2M_N_o : out STD_LOGIC;
- FMC2_GP0_i : in STD_LOGIC;
- FMC2_GP1_i : in STD_LOGIC;
- FMC2_GP2_i : in STD_LOGIC;
- FMC2_GP3_b : inout STD_LOGIC;
- FMC1_PRSNTM2C_n_i : in STD_LOGIC;
- FMC1_CLK0M2C_P_i : in STD_LOGIC;
- FMC1_CLK0M2C_N_i : in STD_LOGIC;
- FMC1_CLK0C2M_P_o : out STD_LOGIC;
- FMC1_CLK0C2M_N_o : out STD_LOGIC;
- FMC1_GP0_i : in STD_LOGIC;
- FMC1_GP1_i : in STD_LOGIC;
- FMC1_GP2_i : in STD_LOGIC;
- FMC1_GP3_b : inout STD_LOGIC;
- pb_gp_n_i : in STD_LOGIC;
- led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
- led_line_en_pl_o : out STD_LOGIC;
- led_line_pl_o : out STD_LOGIC;
- watchdog_pl_o : out STD_LOGIC;
- dig_in1_i : in STD_LOGIC;
- dig_in2_i : in STD_LOGIC;
- dig_in3_n_i : in STD_LOGIC;
- dig_in4_n_i : in STD_LOGIC;
- dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
- dig_out5_n : out STD_LOGIC;
- dig_out6_n : out STD_LOGIC;
- gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
- intr_o : out STD_LOGIC;
- intr_led_o : out STD_LOGIC;
- s00_axi_aclk : in STD_LOGIC;
- s00_axi_aresetn : in STD_LOGIC;
- s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_awvalid : in STD_LOGIC;
- s00_axi_awready : out STD_LOGIC;
- s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s00_axi_wvalid : in STD_LOGIC;
- s00_axi_wready : out STD_LOGIC;
- s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_bvalid : out STD_LOGIC;
- s00_axi_bready : in STD_LOGIC;
- s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s00_axi_arvalid : in STD_LOGIC;
- s00_axi_arready : out STD_LOGIC;
- s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s00_axi_rvalid : out STD_LOGIC;
- s00_axi_rready : in STD_LOGIC
- );
- attribute NotValidForBitStream : boolean;
- attribute NotValidForBitStream of system_design_fasec_hwtest_0_0 : entity is true;
- attribute CHECK_LICENSE_TYPE : string;
- attribute CHECK_LICENSE_TYPE of system_design_fasec_hwtest_0_0 : entity is "system_design_fasec_hwtest_0_0,fasec_hwtest,{}";
- attribute downgradeipidentifiedwarnings : string;
- attribute downgradeipidentifiedwarnings of system_design_fasec_hwtest_0_0 : entity is "yes";
- attribute x_core_info : string;
- attribute x_core_info of system_design_fasec_hwtest_0_0 : entity is "fasec_hwtest,Vivado 2016.2";
-end system_design_fasec_hwtest_0_0;
-
-architecture STRUCTURE of system_design_fasec_hwtest_0_0 is
- attribute g_FMC1 : string;
- attribute g_FMC1 of U0 : label is "EDA-03287";
- attribute g_FMC2 : string;
- attribute g_FMC2 of U0 : label is "EDA-03287";
- attribute g_S00_AXI_ADDR_WIDTH : integer;
- attribute g_S00_AXI_ADDR_WIDTH of U0 : label is 32;
- attribute g_S00_AXI_DATA_WIDTH : integer;
- attribute g_S00_AXI_DATA_WIDTH of U0 : label is 32;
- attribute g_USE_GEM_LEDS : string;
- attribute g_USE_GEM_LEDS of U0 : label is "FALSE";
-begin
-U0: entity work.system_design_fasec_hwtest_0_0_fasec_hwtest
- port map (
- FMC1_CLK0C2M_N_o => FMC1_CLK0C2M_N_o,
- FMC1_CLK0C2M_P_o => FMC1_CLK0C2M_P_o,
- FMC1_CLK0M2C_N_i => FMC1_CLK0M2C_N_i,
- FMC1_CLK0M2C_P_i => FMC1_CLK0M2C_P_i,
- FMC1_GP0_i => FMC1_GP0_i,
- FMC1_GP1_i => FMC1_GP1_i,
- FMC1_GP2_i => FMC1_GP2_i,
- FMC1_GP3_b => FMC1_GP3_b,
- FMC1_LA_N_b(33 downto 0) => FMC1_LA_N_b(33 downto 0),
- FMC1_LA_P_b(33 downto 0) => FMC1_LA_P_b(33 downto 0),
- FMC1_PRSNTM2C_n_i => FMC1_PRSNTM2C_n_i,
- FMC2_CLK0C2M_N_o => FMC2_CLK0C2M_N_o,
- FMC2_CLK0C2M_P_o => FMC2_CLK0C2M_P_o,
- FMC2_CLK0M2C_N_i => FMC2_CLK0M2C_N_i,
- FMC2_CLK0M2C_P_i => FMC2_CLK0M2C_P_i,
- FMC2_GP0_i => FMC2_GP0_i,
- FMC2_GP1_i => FMC2_GP1_i,
- FMC2_GP2_i => FMC2_GP2_i,
- FMC2_GP3_b => FMC2_GP3_b,
- FMC2_LA_N_b(33 downto 0) => FMC2_LA_N_b(33 downto 0),
- FMC2_LA_P_b(33 downto 0) => FMC2_LA_P_b(33 downto 0),
- FMC2_PRSNTM2C_n_i => FMC2_PRSNTM2C_n_i,
- dig_in1_i => dig_in1_i,
- dig_in2_i => dig_in2_i,
- dig_in3_n_i => dig_in3_n_i,
- dig_in4_n_i => dig_in4_n_i,
- dig_out5_n => dig_out5_n,
- dig_out6_n => dig_out6_n,
- dig_outs_i(3 downto 0) => dig_outs_i(3 downto 0),
- gem_status_vector_i(15 downto 0) => gem_status_vector_i(15 downto 0),
- intr_led_o => intr_led_o,
- intr_o => intr_o,
- led_col_pl_o(3 downto 0) => led_col_pl_o(3 downto 0),
- led_line_en_pl_o => led_line_en_pl_o,
- led_line_pl_o => led_line_pl_o,
- osc100_clk_i => osc100_clk_i,
- pb_gp_n_i => pb_gp_n_i,
- ps_clk_i => ps_clk_i,
- s00_axi_aclk => s00_axi_aclk,
- s00_axi_araddr(31 downto 0) => s00_axi_araddr(31 downto 0),
- s00_axi_aresetn => s00_axi_aresetn,
- s00_axi_arprot(2 downto 0) => s00_axi_arprot(2 downto 0),
- s00_axi_arready => s00_axi_arready,
- s00_axi_arvalid => s00_axi_arvalid,
- s00_axi_awaddr(31 downto 0) => s00_axi_awaddr(31 downto 0),
- s00_axi_awprot(2 downto 0) => s00_axi_awprot(2 downto 0),
- s00_axi_awready => s00_axi_awready,
- s00_axi_awvalid => s00_axi_awvalid,
- s00_axi_bready => s00_axi_bready,
- s00_axi_bresp(1 downto 0) => s00_axi_bresp(1 downto 0),
- s00_axi_bvalid => s00_axi_bvalid,
- s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
- s00_axi_rready => s00_axi_rready,
- s00_axi_rresp(1 downto 0) => s00_axi_rresp(1 downto 0),
- s00_axi_rvalid => s00_axi_rvalid,
- s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
- s00_axi_wready => s00_axi_wready,
- s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
- s00_axi_wvalid => s00_axi_wvalid,
- watchdog_pl_o => watchdog_pl_o
- );
-end STRUCTURE;
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
similarity index 99%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
index 6cc1d46b..d3e925bf 100755
--- a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
@@ -6,7 +6,7 @@
-- Author : Pieter Van Trappen <pvantrap@cern.ch>
-- Company : CERN
-- Created : 2016-11-22
--- Last update: 2017-06-21
+-- Last update: 2017-10-12
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@@ -86,7 +86,7 @@ architecture rtl of general_fmc is
-- EDA-03287 constants
constant c_COMP : positive := 20; -- 20 comparators on EDA-03287
constant c_DOUTS : positive := 8; -- 8 outputs
- constant c_DOUTSGP : positive := 4; -- first 4 outputs will be linked to GP signals (for white rabbit debugging)
+ constant c_DOUTSGP : positive := 0; -- first 4 outputs will be linked to GP signals (for white rabbit debugging)
constant c_OUTFBD : positive := 4; -- of which 4 with feedback
constant c_NODAC : positive := 5;
constant c_NOCHANNELS : positive := 4;
@@ -296,7 +296,7 @@ begin
);
end generate gen_spi;
- -- for white rabbit debugging, link some FMC outputs directly to GP inputs
+ -- for white rabbit core (wrc) debugging, link some FMC outputs directly to GP inputs
gen_clkouts : if g_FMC = "EDA-03287" and c_DOUTSGP>0 generate
s_diffouts_o(c_DOUTSGP-1 downto 0) <= FMC_GP3_b & FMC_GP2_i & FMC_GP1_i & FMC_GP0_i;
end generate gen_clkouts;
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
similarity index 99%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
index 3fbc2b0f..ee33a825 100755
--- a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
@@ -294,8 +294,8 @@ begin
s_data(c_FASEC_BASE+1) <= resize(unsigned(s_ins), g_S00_AXI_DATA_WIDTH);
s_data(c_FASEC_BASE+2) <= resize(unsigned(gem_status_vector_i), g_S00_AXI_DATA_WIDTH);
-- s_data(c_FASEC_BASE+3).data used in p_fasec_dio
- s_data(c_FASEC_BASE+6) <= x"59DDF043"; -- tcl-script will put unix build time
- s_data(c_FASEC_BASE+7) <= x"f08bde95"; -- tcl-script will put git commit id
+ s_data(c_FASEC_BASE+6) <= x"DEADBEE1"; -- tcl-script will put unix build time
+ s_data(c_FASEC_BASE+7) <= x"DEADBEE2"; -- tcl-script will put git commit id
-- copy in rw data, 'for generate' only possible with constants!
gen_data_readwrite : for i in 0 to c_MEMMAX-1 generate
gen_fasec : if c_FASECMEM(i).ro = '0' generate
@@ -452,4 +452,3 @@ begin
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready);
end rtl;
-
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt
index 44e20f51..cdca0e21 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
-# Generated by export_simulation on Wed Oct 11 14:50:53 CEST 2017
+# Generated by export_simulation on Thu Oct 12 09:59:21 CEST 2017
#
################################################################################
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do
index 34a97eff..4561ce1f 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do
@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
vcom -work lib_cdc_v1_0_2 -93 \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt
index 680a3c1f..acd82ba7 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt
@@ -1,12 +1,12 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_wr.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_rd.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_wr_4.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh
index 7a4e0087..13b0ebfb 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh
@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
-# Generated by Vivado on Wed Oct 11 14:50:53 CEST 2017
+# Generated by Vivado on Thu Oct 12 09:59:21 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt
index 44e20f51..cdca0e21 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
-# Generated by export_simulation on Wed Oct 11 14:50:53 CEST 2017
+# Generated by export_simulation on Thu Oct 12 09:59:21 CEST 2017
#
################################################################################
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt
index f171fec8..5a6c58e8 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt
@@ -1,12 +1,12 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_wr.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_rd.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_wr_4.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f
index 8f996ee2..e272f2ba 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f
@@ -40,22 +40,22 @@
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
-endlib
-makelib ies/hdl_lib \
- "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
- "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
- "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
- "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd" \
- "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
+ "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+ "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+ "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+ "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+ "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
-endlib
-makelib ies/xil_defaultlib \
- "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+ "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
-endlib
-makelib ies/hdl_lib \
- "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
- "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+ "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+ "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
-endlib
-makelib ies/xil_defaultlib \
- "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
- "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+ "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+ "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
-endlib
-makelib ies/lib_cdc_v1_0_2 \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh
index 1e4ee4d7..6107fd2d 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh
@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
-# Generated by Vivado on Wed Oct 11 14:50:53 CEST 2017
+# Generated by Vivado on Thu Oct 12 09:59:21 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt
index 44e20f51..cdca0e21 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
-# Generated by export_simulation on Wed Oct 11 14:50:53 CEST 2017
+# Generated by export_simulation on Thu Oct 12 09:59:21 CEST 2017
#
################################################################################
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do
index 7872b127..fe50aa38 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do
@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructur
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
vcom -work hdl_lib -64 -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
vcom -work hdl_lib -64 -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
vcom -work lib_cdc_v1_0_2 -64 -93 \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt
index 680a3c1f..acd82ba7 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt
@@ -1,12 +1,12 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_wr.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_rd.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_wr_4.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh
index 0fb8ff8b..aab3d583 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh
@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
-# Generated by Vivado on Wed Oct 11 14:50:53 CEST 2017
+# Generated by Vivado on Thu Oct 12 09:59:21 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt
index 44e20f51..cdca0e21 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
-# Generated by export_simulation on Wed Oct 11 14:50:53 CEST 2017
+# Generated by export_simulation on Thu Oct 12 09:59:21 CEST 2017
#
################################################################################
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do
index 7203b7eb..5b49736f 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do
@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
vcom -work hdl_lib -64 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
vcom -work hdl_lib -64 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
vcom -work lib_cdc_v1_0_2 -64 \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt
index 680a3c1f..acd82ba7 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt
@@ -1,12 +1,12 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_wr.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_rd.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_wr_4.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh
index 4ab08ed4..c05cb2a4 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh
@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
-# Generated by Vivado on Wed Oct 11 14:50:53 CEST 2017
+# Generated by Vivado on Thu Oct 12 09:59:21 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt
index 44e20f51..cdca0e21 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
-# Generated by export_simulation on Wed Oct 11 14:50:53 CEST 2017
+# Generated by export_simulation on Thu Oct 12 09:59:21 CEST 2017
#
################################################################################
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do
index 11adc601..22a4cf7e 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do
@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
vcom -work lib_cdc_v1_0_2 -93 \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt
index 680a3c1f..acd82ba7 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt
@@ -1,12 +1,12 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_wr.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_rd.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_wr_4.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh
index 29e2158b..3062bc9f 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh
@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
-# Generated by Vivado on Wed Oct 11 14:50:53 CEST 2017
+# Generated by Vivado on Thu Oct 12 09:59:21 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt
index 44e20f51..cdca0e21 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
-# Generated by export_simulation on Wed Oct 11 14:50:53 CEST 2017
+# Generated by export_simulation on Thu Oct 12 09:59:21 CEST 2017
#
################################################################################
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt
index f171fec8..5a6c58e8 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt
@@ -1,12 +1,12 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_wr.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_rd.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_wr_4.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh
index f4c97937..d6977515 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh
@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
-# Generated by Vivado on Wed Oct 11 14:50:53 CEST 2017
+# Generated by Vivado on Thu Oct 12 09:59:21 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
@@ -113,25 +113,25 @@ compile()
2>&1 | tee -a vlogan.log
vhdlan -work hdl_lib $vhdlan_opts \
- "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
- "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
- "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
- "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd" \
- "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
2>&1 | tee -a vhdlan.log
vhdlan -work xil_defaultlib $vhdlan_opts \
- "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
2>&1 | tee -a vhdlan.log
vhdlan -work hdl_lib $vhdlan_opts \
- "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
- "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
2>&1 | tee -a vhdlan.log
vhdlan -work xil_defaultlib $vhdlan_opts \
- "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
- "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+ "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"$ref_dir/../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
2>&1 | tee -a vhdlan.log
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt
index 44e20f51..cdca0e21 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
-# Generated by export_simulation on Wed Oct 11 14:50:53 CEST 2017
+# Generated by export_simulation on Thu Oct 12 09:59:21 CEST 2017
#
################################################################################
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt
index f171fec8..5a6c58e8 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt
@@ -1,12 +1,12 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_wr.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_rd.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_arb_wr_4.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh
index fe157a45..090752d7 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh
@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
-# Generated by Vivado on Wed Oct 11 14:50:53 CEST 2017
+# Generated by Vivado on Thu Oct 12 09:59:21 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj
index cc5dc1ac..916cd39b 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj
@@ -1,14 +1,14 @@
vhdl xpm "/local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd"
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd"
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd"
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/counterUpDown.vhd"
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/main_pkg.vhd"
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd"
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd"
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd"
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/ip_cores/hdl_lib/modules/general/clockDivider.vhd"
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd"
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd"
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd"
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd"
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/counterUpDown.vhd"
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/main_pkg.vhd"
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd"
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd"
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd"
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/ip_cores/hdl_lib/modules/general/clockDivider.vhd"
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd"
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_7/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd"
vhdl lib_cdc_v1_0_2 "../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd"
vhdl proc_sys_reset_v5_0_9 "../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd"
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef
index ac89b4d3f784dcfbd5d2b04f86df2cd32795c493..94bc0553b1ae4b67fe880310e7688d561795dfff 100644
GIT binary patch
literal 73082
zcmV*KKxMyBO9KQH000080BKK5OHw#7dL01(0IC5100{s90BCn)Wo9mTZES6kPj7-S
z7{<@zQ#9{gL{0Pp7^E*krj)ek;;GrRDvRO<WD`HVWe|7Rj(z_8-Y2O&y`E3xOBH2y
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diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
index 113209b1..21496934 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
@@ -1,7 +1,7 @@
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
---Date : Wed Oct 11 14:54:59 2017
+--Date : Thu Oct 12 09:59:12 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.2
--Command : generate_target system_design.bd
--Design : system_design
@@ -4075,47 +4075,15 @@ architecture STRUCTURE of system_design is
s00_axi_rready : in STD_LOGIC
);
end component system_design_wrc_1p_kintex7_0_0;
- component system_design_fasec_hwtest_0_0 is
+ component system_design_axi_wb_i2c_master_0_1 is
port (
- ps_clk_i : in STD_LOGIC;
- osc100_clk_i : in STD_LOGIC;
- FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
- FMC2_PRSNTM2C_n_i : in STD_LOGIC;
- FMC2_CLK0M2C_P_i : in STD_LOGIC;
- FMC2_CLK0M2C_N_i : in STD_LOGIC;
- FMC2_CLK0C2M_P_o : out STD_LOGIC;
- FMC2_CLK0C2M_N_o : out STD_LOGIC;
- FMC2_GP0_i : in STD_LOGIC;
- FMC2_GP1_i : in STD_LOGIC;
- FMC2_GP2_i : in STD_LOGIC;
- FMC2_GP3_b : inout STD_LOGIC;
- FMC1_PRSNTM2C_n_i : in STD_LOGIC;
- FMC1_CLK0M2C_P_i : in STD_LOGIC;
- FMC1_CLK0M2C_N_i : in STD_LOGIC;
- FMC1_CLK0C2M_P_o : out STD_LOGIC;
- FMC1_CLK0C2M_N_o : out STD_LOGIC;
- FMC1_GP0_i : in STD_LOGIC;
- FMC1_GP1_i : in STD_LOGIC;
- FMC1_GP2_i : in STD_LOGIC;
- FMC1_GP3_b : inout STD_LOGIC;
- pb_gp_n_i : in STD_LOGIC;
- led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
- led_line_en_pl_o : out STD_LOGIC;
- led_line_pl_o : out STD_LOGIC;
- watchdog_pl_o : out STD_LOGIC;
- dig_in1_i : in STD_LOGIC;
- dig_in2_i : in STD_LOGIC;
- dig_in3_n_i : in STD_LOGIC;
- dig_in4_n_i : in STD_LOGIC;
- dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
- dig_out5_n : out STD_LOGIC;
- dig_out6_n : out STD_LOGIC;
- gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
- intr_o : out STD_LOGIC;
- intr_led_o : out STD_LOGIC;
+ i2c_scl_i : in STD_LOGIC;
+ i2c_scl_o : out STD_LOGIC;
+ i2c_scl_t : out STD_LOGIC;
+ i2c_sda_i : in STD_LOGIC;
+ i2c_sda_o : out STD_LOGIC;
+ i2c_sda_t : out STD_LOGIC;
+ axi_int_o : out STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -4138,8 +4106,8 @@ architecture STRUCTURE of system_design is
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
- end component system_design_fasec_hwtest_0_0;
- component system_design_axi_wb_i2c_master_0_1 is
+ end component system_design_axi_wb_i2c_master_0_1;
+ component system_design_axi_wb_i2c_master_2_0 is
port (
i2c_scl_i : in STD_LOGIC;
i2c_scl_o : out STD_LOGIC;
@@ -4170,16 +4138,48 @@ architecture STRUCTURE of system_design is
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
- end component system_design_axi_wb_i2c_master_0_1;
- component system_design_axi_wb_i2c_master_2_0 is
+ end component system_design_axi_wb_i2c_master_2_0;
+ component system_design_fasec_hwtest_0_0 is
port (
- i2c_scl_i : in STD_LOGIC;
- i2c_scl_o : out STD_LOGIC;
- i2c_scl_t : out STD_LOGIC;
- i2c_sda_i : in STD_LOGIC;
- i2c_sda_o : out STD_LOGIC;
- i2c_sda_t : out STD_LOGIC;
- axi_int_o : out STD_LOGIC;
+ ps_clk_i : in STD_LOGIC;
+ osc100_clk_i : in STD_LOGIC;
+ FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+ FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+ FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+ FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+ FMC2_PRSNTM2C_n_i : in STD_LOGIC;
+ FMC2_CLK0M2C_P_i : in STD_LOGIC;
+ FMC2_CLK0M2C_N_i : in STD_LOGIC;
+ FMC2_CLK0C2M_P_o : out STD_LOGIC;
+ FMC2_CLK0C2M_N_o : out STD_LOGIC;
+ FMC2_GP0_i : in STD_LOGIC;
+ FMC2_GP1_i : in STD_LOGIC;
+ FMC2_GP2_i : in STD_LOGIC;
+ FMC2_GP3_b : inout STD_LOGIC;
+ FMC1_PRSNTM2C_n_i : in STD_LOGIC;
+ FMC1_CLK0M2C_P_i : in STD_LOGIC;
+ FMC1_CLK0M2C_N_i : in STD_LOGIC;
+ FMC1_CLK0C2M_P_o : out STD_LOGIC;
+ FMC1_CLK0C2M_N_o : out STD_LOGIC;
+ FMC1_GP0_i : in STD_LOGIC;
+ FMC1_GP1_i : in STD_LOGIC;
+ FMC1_GP2_i : in STD_LOGIC;
+ FMC1_GP3_b : inout STD_LOGIC;
+ pb_gp_n_i : in STD_LOGIC;
+ led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ led_line_en_pl_o : out STD_LOGIC;
+ led_line_pl_o : out STD_LOGIC;
+ watchdog_pl_o : out STD_LOGIC;
+ dig_in1_i : in STD_LOGIC;
+ dig_in2_i : in STD_LOGIC;
+ dig_in3_n_i : in STD_LOGIC;
+ dig_in4_n_i : in STD_LOGIC;
+ dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ dig_out5_n : out STD_LOGIC;
+ dig_out6_n : out STD_LOGIC;
+ gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
+ intr_o : out STD_LOGIC;
+ intr_led_o : out STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -4202,7 +4202,7 @@ architecture STRUCTURE of system_design is
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
- end component system_design_axi_wb_i2c_master_2_0;
+ end component system_design_fasec_hwtest_0_0;
signal FMC1_CLK0M2C_N_i_1 : STD_LOGIC;
signal FMC1_CLK0M2C_P_i_1 : STD_LOGIC;
signal FMC1_PRSNTM2C_n_i_1 : STD_LOGIC;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
index a7e17e51..a247d67a 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
@@ -1,7 +1,7 @@
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
---Date : Wed Oct 11 14:54:59 2017
+--Date : Thu Oct 12 09:59:13 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.2
--Command : generate_target system_design_wrapper.bd
--Design : system_design_wrapper
@@ -149,6 +149,12 @@ architecture STRUCTURE of system_design_wrapper is
gtp_wr_mod_abs : in STD_LOGIC;
gtp_wr_txp : out STD_LOGIC;
gtp_wr_scl : inout STD_LOGIC;
+ i2c_master_fmcx_scl_i : in STD_LOGIC;
+ i2c_master_fmcx_scl_o : out STD_LOGIC;
+ i2c_master_fmcx_scl_t : out STD_LOGIC;
+ i2c_master_fmcx_sda_o : out STD_LOGIC;
+ i2c_master_fmcx_sda_i : in STD_LOGIC;
+ i2c_master_fmcx_sda_t : out STD_LOGIC;
pb_gp_i : in STD_LOGIC;
led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_line_en_pl_o : out STD_LOGIC;
@@ -186,13 +192,7 @@ architecture STRUCTURE of system_design_wrapper is
eeprom_sda : inout STD_LOGIC;
gtp_dedicated_clk_p_i : in STD_LOGIC;
gtp_dedicated_clk_n_i : in STD_LOGIC;
- dig_out6_n : out STD_LOGIC_VECTOR ( 0 to 0 );
- i2c_master_fmcx_scl_i : in STD_LOGIC;
- i2c_master_fmcx_scl_o : out STD_LOGIC;
- i2c_master_fmcx_scl_t : out STD_LOGIC;
- i2c_master_fmcx_sda_o : out STD_LOGIC;
- i2c_master_fmcx_sda_i : in STD_LOGIC;
- i2c_master_fmcx_sda_t : out STD_LOGIC
+ dig_out6_n : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_design;
component IOBUF is
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
index a6df6822..df15d86b 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Wed Oct 11 14:55:00 2017" VIVADOVERSION="2016.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu Oct 12 09:59:14 2017" VIVADOVERSION="2016.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z030" NAME="system_design" PACKAGE="ffg676" SPEEDGRADE="-2"/>
@@ -49,6 +49,12 @@
<PORT DIR="I" NAME="gtp_wr_mod_abs" SIGIS="undef"/>
<PORT DIR="O" NAME="gtp_wr_txp" SIGIS="undef"/>
<PORT DIR="IO" NAME="gtp_wr_scl" SIGIS="undef"/>
+ <PORT DIR="I" NAME="i2c_master_fmcx_scl_i" SIGIS="undef"/>
+ <PORT DIR="O" NAME="i2c_master_fmcx_scl_o" SIGIS="undef"/>
+ <PORT DIR="O" NAME="i2c_master_fmcx_scl_t" SIGIS="undef"/>
+ <PORT DIR="O" NAME="i2c_master_fmcx_sda_o" SIGIS="undef"/>
+ <PORT DIR="I" NAME="i2c_master_fmcx_sda_i" SIGIS="undef"/>
+ <PORT DIR="O" NAME="i2c_master_fmcx_sda_t" SIGIS="undef"/>
<PORT DIR="I" NAME="pb_gp_i" SIGIS="undef" SIGNAME="External_Ports_pb_gp_i">
<CONNECTIONS>
<CONNECTION INSTANCE="wrc_1p_kintex7_0" PORT="button_rst_n_i"/>
@@ -241,12 +247,6 @@
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="dig_out6_n"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="i2c_master_fmcx_scl_i" SIGIS="undef"/>
- <PORT DIR="O" NAME="i2c_master_fmcx_scl_o" SIGIS="undef"/>
- <PORT DIR="O" NAME="i2c_master_fmcx_scl_t" SIGIS="undef"/>
- <PORT DIR="O" NAME="i2c_master_fmcx_sda_o" SIGIS="undef"/>
- <PORT DIR="I" NAME="i2c_master_fmcx_sda_i" SIGIS="undef"/>
- <PORT DIR="O" NAME="i2c_master_fmcx_sda_t" SIGIS="undef"/>
</EXTERNALPORTS>
<EXTERNALINTERFACES>
@@ -3711,7 +3711,7 @@
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
- <MODULE FULLNAME="/fasec_hwtest_0" HWVERSION="3.2.6" INSTANCE="fasec_hwtest_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="fasec_hwtest" VLNV="user.org:user:fasec_hwtest:3.2.6">
+ <MODULE FULLNAME="/fasec_hwtest_0" HWVERSION="3.2.7" INSTANCE="fasec_hwtest_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="fasec_hwtest" VLNV="user.org:user:fasec_hwtest:3.2.7">
<DOCUMENTS/>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="" INTERFACE="S00_AXI" NAME="S00_AXI_reg" RANGE="4096" USAGE=""/>
@@ -5611,6 +5611,8 @@
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_aclk"/>
<CONNECTION INSTANCE="xadc_wiz_0" PORT="s_axis_aclk"/>
<CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aclk"/>
+ <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aclk"/>
+ <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aclk"/>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="ACLK"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="ACLK"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M06_ACLK"/>
@@ -5626,8 +5628,6 @@
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M07_ACLK"/>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="ps_clk_i"/>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="s00_axi_aclk"/>
- <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aclk"/>
- <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aclk"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="10000000" DIR="O" NAME="FCLK_CLK1" SIGIS="clk"/>
@@ -7449,6 +7449,8 @@
<CONNECTION INSTANCE="axi_dma_0" PORT="axi_resetn"/>
<CONNECTION INSTANCE="xadc_axis_fifo_adapter_0" PORT="AXIS_RESET_N"/>
<CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aresetn"/>
+ <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aresetn"/>
+ <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aresetn"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="S00_ARESETN"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M06_ARESETN"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M05_ARESETN"/>
@@ -7462,8 +7464,6 @@
<CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_ARESETN"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M07_ARESETN"/>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="s00_axi_aresetn"/>
- <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aresetn"/>
- <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aresetn"/>
</CONNECTIONS>
</PORT>
</PORTS>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
index 6ba479c0..edd59a9c 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
@@ -246,7 +246,7 @@ CONFIG.C_S_AXI_ACLK_FREQ_HZ.VALUE_SRC {DEFAULT} \
set axi_wb_i2c_master_2 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.2.0 axi_wb_i2c_master_2 ]
# Create instance: fasec_hwtest_0, and set properties
- set fasec_hwtest_0 [ create_bd_cell -type ip -vlnv user.org:user:fasec_hwtest:3.2.6 fasec_hwtest_0 ]
+ set fasec_hwtest_0 [ create_bd_cell -type ip -vlnv user.org:user:fasec_hwtest:3.2.7 fasec_hwtest_0 ]
set_property -dict [ list \
CONFIG.g_FMC1 {EDA-03287} \
CONFIG.g_FMC2 {EDA-03287} \
@@ -1708,95 +1708,95 @@ preplace inst axi_interconnect_1 -pg 1 -lvl 8 -y 870 -defaultsOSRD
preplace inst rst_wrc_1p_kintex7_0_62M -pg 1 -lvl 7 -y 850 -defaultsOSRD
preplace inst processing_system7_0_axi_periph -pg 1 -lvl 2 -y 280 -defaultsOSRD
preplace inst processing_system7_0 -pg 1 -lvl 7 -y 520 -defaultsOSRD
-preplace netloc osc100_clk_i_1 1 0 9 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ
+preplace netloc osc100_clk_i_1 1 0 9 NJ 680 NJ 680 NJ 680 NJ 680 NJ 680 NJ 720 NJ 720 NJ 710 NJ
preplace netloc fasec_hwtest_0_led_col_pl_o 1 9 1 NJ
preplace netloc dig_in4_n_i_1 1 0 9 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ 1200 NJ
preplace netloc processing_system7_0_FIXED_IO 1 7 3 NJ 450 NJ 450 NJ
preplace netloc fasec_hwtest_0_dig_outs_i 1 9 1 NJ
-preplace netloc gtp_dedicated_clk_n_i_1 1 0 9 NJ 1650 NJ 1650 NJ 1650 NJ 1650 NJ 1650 NJ 1650 NJ 1650 NJ 1650 NJ
+preplace netloc gtp_dedicated_clk_n_i_1 1 0 9 NJ 1640 NJ 1640 NJ 1640 NJ 1640 NJ 1640 NJ 1640 NJ 1640 NJ 1640 NJ
preplace netloc wrc_1p_kintex7_0_dac_din_o 1 9 1 NJ
preplace netloc gtp_dedicated_clk_p_i_1 1 0 9 NJ 1630 NJ 1630 NJ 1630 NJ 1630 NJ 1630 NJ 1630 NJ 1630 NJ 1630 NJ
-preplace netloc wrc_1p_kintex7_0_clk_rx_rbclk_o 1 8 2 2880 1330 3270
-preplace netloc wrc_1p_kintex7_0_pps_o 1 8 2 2850 1370 3230
-preplace netloc axi_uartlite_0_tx 1 3 7 NJ 650 NJ 650 NJ 710 NJ 710 NJ 710 NJ 710 3300
+preplace netloc wrc_1p_kintex7_0_clk_rx_rbclk_o 1 8 2 2980 1320 3330
+preplace netloc wrc_1p_kintex7_0_pps_o 1 8 2 2960 1340 3350
+preplace netloc axi_uartlite_0_tx 1 3 7 NJ 600 NJ 600 NJ 710 NJ 710 NJ 620 NJ 620 3390
preplace netloc dig_in3_n_i_1 1 0 9 NJ 1180 NJ 1180 NJ 1180 NJ 1180 NJ 1180 NJ 1180 NJ 1180 NJ 1180 NJ
-preplace netloc FMC1_PRSNTM2C_n_i_1 1 0 9 NJ 710 NJ 700 NJ 690 NJ 690 NJ 690 NJ 750 NJ 750 NJ 750 NJ
+preplace netloc FMC1_PRSNTM2C_n_i_1 1 0 9 NJ 660 NJ 660 NJ 660 NJ 660 NJ 660 NJ 730 NJ 730 NJ 730 NJ
preplace netloc dig_in1_i_1 1 0 9 NJ 1140 NJ 1140 NJ 1140 NJ 1140 NJ 1140 NJ 1140 NJ 1140 NJ 1140 NJ
-preplace netloc xlconcat_0_dout 1 6 1 2030
+preplace netloc xlconcat_0_dout 1 6 1 2040
preplace netloc fasec_hwtest_0_FMC1_CLK0C2M_P_o 1 9 1 NJ
-preplace netloc pb_gp_i_1 1 0 9 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 2820
+preplace netloc pb_gp_i_1 1 0 9 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 NJ 1660 2930
preplace netloc wrc_1p_kintex7_0_dac_sclk_o 1 9 1 NJ
preplace netloc fasec_hwtest_0_led_line_pl_o 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph_M06_AXI 1 2 3 670 320 NJ 260 NJ
-preplace netloc axi_wb_i2c_master_2_axi_int_o 1 5 5 1690 470 NJ 680 NJ 680 NJ 680 3320
+preplace netloc processing_system7_0_axi_periph_M06_AXI 1 2 3 720 320 NJ 260 NJ
+preplace netloc axi_wb_i2c_master_2_axi_int_o 1 5 5 1730 750 NJ 750 NJ 590 NJ 590 3400
preplace netloc processing_system7_0_DDR 1 7 3 NJ 430 NJ 430 NJ
preplace netloc FMC1_CLK0M2C_N_i_1 1 0 9 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ
preplace netloc wrc_1p_kintex7_0_dac_cs2_n_o 1 9 1 NJ
preplace netloc axi_wb_i2c_master_2_i2c_master 1 9 1 NJ
-preplace netloc axi_interconnect_1_M00_AXI 1 8 1 2740
-preplace netloc FMC2_CLK0M2C_N_i_1 1 0 9 NJ 690 NJ 690 NJ 680 NJ 680 NJ 680 NJ 740 NJ 740 NJ 740 NJ
+preplace netloc axi_interconnect_1_M00_AXI 1 8 1 2870
+preplace netloc FMC2_CLK0M2C_N_i_1 1 0 9 NJ 670 NJ 670 NJ 670 NJ 670 NJ 670 NJ 700 NJ 700 NJ 700 NJ
preplace netloc processing_system7_0_axi_periph_M05_AXI 1 2 2 N 310 NJ
preplace netloc fasec_hwtest_0_dig_out6_n 1 9 1 NJ
-preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 8 30 20 NJ 20 NJ 20 NJ 20 NJ 20 NJ 20 2010 380 2420
-preplace netloc FMC2_PRSNTM2C_n_i_1 1 0 9 NJ 650 NJ 650 NJ 660 NJ 660 NJ 660 NJ 720 NJ 720 NJ 720 NJ
-preplace netloc rst_wrc_1p_kintex7_0_62M_interconnect_aresetn 1 7 1 2420
+preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 8 30 690 NJ 690 NJ 690 NJ 690 NJ 690 NJ 780 2070 760 2460
+preplace netloc FMC2_PRSNTM2C_n_i_1 1 0 9 NJ 540 NJ 540 NJ 500 NJ 500 NJ 500 NJ 740 NJ 670 NJ 670 NJ
+preplace netloc rst_wrc_1p_kintex7_0_62M_interconnect_aresetn 1 7 1 2490
preplace netloc xadc_wiz_0_M_AXIS 1 3 1 1030
-preplace netloc processing_system7_0_axi_periph_M02_AXI 1 2 7 680 990 NJ 990 NJ 990 NJ 990 NJ 990 NJ 990 NJ
-preplace netloc xadc_axis_fifo_adapter_0_M_AXIS 1 4 1 1290
-preplace netloc processing_system7_0_axi_periph_M07_AXI 1 2 1 730
-preplace netloc fasec_hwtest_0_intr_led_o 1 5 5 1690 700 NJ 700 NJ 700 NJ 700 3310
-preplace netloc wrc_1p_kintex7_0_gtp0_synced_led_o 1 8 2 2840 1350 3250
+preplace netloc processing_system7_0_axi_periph_M02_AXI 1 2 7 690 120 NJ 120 NJ 120 NJ 120 NJ 120 NJ 120 NJ
+preplace netloc xadc_axis_fifo_adapter_0_M_AXIS 1 4 1 1280
+preplace netloc processing_system7_0_axi_periph_M07_AXI 1 2 1 680
+preplace netloc fasec_hwtest_0_intr_led_o 1 5 5 1740 760 NJ 680 NJ 680 NJ 680 3330
+preplace netloc wrc_1p_kintex7_0_gtp0_synced_led_o 1 8 2 2970 760 3370
preplace netloc fasec_hwtest_0_FMC2_CLK0C2M_N_o 1 9 1 NJ
-preplace netloc rst_wrc_1p_kintex7_0_62M_peripheral_aresetn 1 7 2 2440 1760 NJ
-preplace netloc clk_25m_vcxo_i_1 1 0 9 NJ 1610 NJ 1610 NJ 1610 NJ 1610 NJ 1610 NJ 1610 NJ 1610 NJ 1610 2760
-preplace netloc axi_dma_0_M_AXI_S2MM 1 5 1 1630
-preplace netloc wrc_1p_kintex7_0_gtp0_link_led_o 1 8 2 2830 1360 3240
+preplace netloc rst_wrc_1p_kintex7_0_62M_peripheral_aresetn 1 7 2 2560 750 NJ
+preplace netloc clk_25m_vcxo_i_1 1 0 9 NJ 1610 NJ 1610 NJ 1610 NJ 1610 NJ 1610 NJ 1610 NJ 1610 NJ 1610 2890
+preplace netloc axi_dma_0_M_AXI_S2MM 1 5 1 1670
+preplace netloc wrc_1p_kintex7_0_gtp0_link_led_o 1 8 2 2980 770 3360
preplace netloc fasec_hwtest_0_FMC2_CLK0C2M_P_o 1 9 1 NJ
preplace netloc Vaux2_1 1 0 3 NJ 820 NJ 820 NJ
preplace netloc Vp_Vn_1 1 0 3 NJ 760 NJ 760 NJ
preplace netloc fasec_hwtest_0_FMC1_CLK0C2M_N_o 1 9 1 NJ
preplace netloc fasec_hwtest_0_watchdog_pl_o 1 9 1 NJ
-preplace netloc processing_system7_0_axi_periph_M01_AXI 1 2 1 740
+preplace netloc processing_system7_0_axi_periph_M01_AXI 1 2 1 730
preplace netloc fasec_hwtest_0_dig_out5_n 1 9 1 NJ
preplace netloc FMC1_CLK0M2C_P_i_1 1 0 9 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ
preplace netloc Vaux0_1 1 0 3 NJ 780 NJ 780 NJ
preplace netloc Net10 1 9 1 NJ
-preplace netloc wrc_1p_kintex7_0_uart_txd_o 1 3 7 1020 1310 NJ 1310 NJ 1310 NJ 1310 NJ 1310 NJ 1310 3290
-preplace netloc processing_system7_0_FCLK_CLK0 1 0 9 20 10 360 550 740 460 1050 480 1280 220 1670 450 2020 660 2430 600 2800
+preplace netloc wrc_1p_kintex7_0_uart_txd_o 1 3 7 N 570 NJ 570 NJ 690 NJ 690 NJ 640 NJ 640 3380
+preplace netloc processing_system7_0_FCLK_CLK0 1 0 9 30 20 350 550 730 460 1010 230 1310 230 1740 360 2050 660 2470 570 2940
preplace netloc Net11 1 9 1 NJ
preplace netloc Net2 1 9 1 NJ
-preplace netloc fasec_hwtest_0_intr_o 1 5 5 1680 690 NJ 690 NJ 690 NJ 690 3320
+preplace netloc fasec_hwtest_0_intr_o 1 5 5 1720 770 NJ 740 NJ 690 NJ 690 3320
preplace netloc Net3 1 9 1 NJ
-preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 1 350
-preplace netloc processing_system7_0_axi_periph_M00_AXI 1 2 7 N 210 NJ 210 NJ 210 NJ 360 NJ 360 NJ 360 NJ
+preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 1 360
+preplace netloc processing_system7_0_axi_periph_M00_AXI 1 2 7 680 110 NJ 110 NJ 110 NJ 110 NJ 110 NJ 110 NJ
preplace netloc fasec_hwtest_0_led_line_en_pl_o 1 9 1 NJ
-preplace netloc wrc_1p_kintex7_0_s00_axi_aclk_o 1 6 4 2040 760 2430 1380 NJ 1380 3220
+preplace netloc wrc_1p_kintex7_0_s00_axi_aclk_o 1 6 4 2080 940 2540 650 NJ 650 3400
preplace netloc Net4 1 9 1 NJ
preplace netloc Vaux8_1 1 0 3 NJ 840 NJ 840 NJ
-preplace netloc wrc_1p_kintex7_0_gtp0_activity_led_o 1 8 2 2860 1340 3260
+preplace netloc wrc_1p_kintex7_0_gtp0_activity_led_o 1 8 2 2950 1330 3320
preplace netloc Net5 1 9 1 NJ
-preplace netloc xadc_wiz_0_ip2intc_irpt 1 3 3 NJ 770 NJ 770 1670
+preplace netloc xadc_wiz_0_ip2intc_irpt 1 3 3 NJ 540 NJ 540 N
preplace netloc Net6 1 9 1 NJ
preplace netloc xlconstant_6_dout 1 8 1 NJ
preplace netloc Net7 1 9 1 NJ
preplace netloc dig_in2_i_1 1 0 9 NJ 1160 NJ 1160 NJ 1160 NJ 1160 NJ 1160 NJ 1160 NJ 1160 NJ 1160 NJ
-preplace netloc axi_uartlite_0_interrupt 1 3 3 1050 600 NJ 600 NJ
+preplace netloc axi_uartlite_0_interrupt 1 3 3 1040 590 NJ 590 NJ
preplace netloc Vaux10_1 1 0 3 NJ 880 NJ 880 NJ
-preplace netloc processing_system7_0_M_AXI_GP0 1 1 7 370 540 NJ 500 NJ 500 NJ 500 NJ 440 NJ 370 2440
-preplace netloc wrc_1p_kintex7_0_clk_ref_o 1 8 2 2870 1320 3280
+preplace netloc processing_system7_0_M_AXI_GP0 1 1 7 380 20 NJ 20 NJ 20 NJ 20 NJ 20 NJ 20 2460
+preplace netloc wrc_1p_kintex7_0_clk_ref_o 1 8 2 2970 1310 3340
preplace netloc Vaux1_1 1 0 3 NJ 800 NJ 800 NJ
preplace netloc Vaux9_1 1 0 3 NJ 860 NJ 860 NJ
-preplace netloc axi_dma_0_s2mm_introut 1 5 1 1630
-preplace netloc processing_system7_0_axi_periph_M04_AXI 1 2 1 710
-preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 1 8 350 560 690 470 1060 490 1300 230 1690 460 NJ 670 NJ 670 2810
-preplace netloc FMC2_CLK0M2C_P_i_1 1 0 9 NJ 670 NJ 670 NJ 670 NJ 670 NJ 670 NJ 730 NJ 730 NJ 730 NJ
+preplace netloc axi_dma_0_s2mm_introut 1 5 1 1730
+preplace netloc processing_system7_0_axi_periph_M04_AXI 1 2 1 690
+preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 1 8 370 10 700 250 1050 250 1290 410 1720 380 NJ 380 NJ 380 2900
+preplace netloc FMC2_CLK0M2C_P_i_1 1 0 9 NJ 580 NJ 580 NJ 490 NJ 490 NJ 490 NJ 950 NJ 950 NJ 740 NJ
preplace netloc wrc_1p_kintex7_0_dac_cs1_n_o 1 9 1 NJ
preplace netloc wrc_1p_kintex7_0_gtp_wr 1 9 1 NJ
-preplace netloc S00_AXI_1 1 7 1 2440
-preplace netloc axi_interconnect_0_M00_AXI 1 6 1 2040
+preplace netloc S00_AXI_1 1 7 1 2510
+preplace netloc axi_interconnect_0_M00_AXI 1 6 1 2080
preplace netloc xlconstant_7_dout 1 8 1 NJ
-preplace netloc axi_wb_i2c_master_0_axi_int_o 1 3 3 1040 580 NJ 580 NJ
-levelinfo -pg 1 0 190 520 880 1170 1460 1840 2230 2590 3050 3340 -top 0 -bot 1940
+preplace netloc axi_wb_i2c_master_0_axi_int_o 1 3 3 1020 480 NJ 480 NJ
+levelinfo -pg 1 -40 190 530 880 1170 1470 1890 2270 2710 3150 3420 -top 0 -bot 1940
",
}
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.dcp b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.dcp
index a6cb00b5a111bae29ac2d86b6cafb5559fbd0be6..aade593482f874934da55b9ab41d34e7ec826b4b 100644
GIT binary patch
delta 175364
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diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
index 7d0e39e4..73a6460a 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1223,7 +1223,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:56:48 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 08:01:44 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v
index 056d9449..550b25f7 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Oct 11 14:56:47 2017
+// Date : Thu Oct 12 10:01:43 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode funcsim
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl
index 5439030d..c5b76975 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Oct 11 14:56:47 2017
+-- Date : Thu Oct 12 10:01:44 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode funcsim
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_sim_netlist.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v
index 53bf4f2e..f6e950d5 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Oct 11 14:56:47 2017
+// Date : Thu Oct 12 10:01:43 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode synth_stub
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl
index d7010ae7..8a3acb1c 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Oct 11 14:56:47 2017
+-- Date : Thu Oct 12 10:01:43 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode synth_stub
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0_stub.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.dcp b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.dcp
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diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
index 84877b69..42e39a31 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1223,7 +1223,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:56:45 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 08:01:50 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v
index 795246d6..f13fe3ee 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Oct 11 14:56:45 2017
+// Date : Thu Oct 12 10:01:50 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode funcsim
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl
index 7dd8f70d..f41f47f0 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Oct 11 14:56:45 2017
+-- Date : Thu Oct 12 10:01:50 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode funcsim
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_sim_netlist.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v
index 7b0baf39..c2c923da 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Oct 11 14:56:45 2017
+// Date : Thu Oct 12 10:01:49 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode synth_stub
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl
index 883775f8..c985ca0e 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Oct 11 14:56:45 2017
+-- Date : Thu Oct 12 10:01:50 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode synth_stub
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1_stub.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.dcp b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.dcp
index f33a4465d16aa130ff5bd845bdb9615c1aae805f..f02cb053081f0543d6a1d92f7576b65e8c62dac6 100644
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diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
index 81e401c3..4753219a 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:55:00 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 07:59:14 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
@@ -1223,7 +1223,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Wed Oct 11 12:56:45 UTC 2017</spirit:value>
+ <spirit:value>Thu Oct 12 08:01:50 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v
index 8adcda08..1b677d2e 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Oct 11 14:56:44 2017
+// Date : Thu Oct 12 10:01:50 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode funcsim
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl
index bc6e750d..69c2992b 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Oct 11 14:56:45 2017
+-- Date : Thu Oct 12 10:01:50 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode funcsim
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_sim_netlist.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v
index d369b145..0eae9605 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v
@@ -1,7 +1,7 @@
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-// Date : Wed Oct 11 14:56:44 2017
+// Date : Thu Oct 12 10:01:50 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode synth_stub
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.v
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl
index 62a392ad..f6e265c7 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl
@@ -1,7 +1,7 @@
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--- Date : Wed Oct 11 14:56:44 2017
+-- Date : Thu Oct 12 10:01:50 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode synth_stub
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2_stub.vhdl
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
index e8dbc970..cb35c120 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
--- IP VLNV: user.org:user:fasec_hwtest:3.2.6
--- IP Revision: 34
+-- IP VLNV: user.org:user:fasec_hwtest:3.2.7
+-- IP Revision: 35
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/synth/system_design_fasec_hwtest_0_0.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/synth/system_design_fasec_hwtest_0_0.vhd
index b33310e1..90621aa3 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/synth/system_design_fasec_hwtest_0_0.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/synth/system_design_fasec_hwtest_0_0.vhd
@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
--- IP VLNV: user.org:user:fasec_hwtest:3.2.6
--- IP Revision: 34
+-- IP VLNV: user.org:user:fasec_hwtest:3.2.7
+-- IP Revision: 35
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.dcp b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.dcp
index c949308fe112c23c654fc15c04a41e5631214a9f..5db6ea15953d7723c164160961f9e9b6192cead6 100644
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