diff --git a/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd b/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd
index 034fae5ce15ebcb04a6b7eda21e96cab0f2a5ad3..4cb515f13180be5fbcebb4e0c0e8c4116ce641a9 100644
--- a/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd
@@ -1,7 +1,7 @@
 --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------
 --Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
---Date        : Thu Apr 13 09:57:53 2017
+--Date        : Thu May 11 16:53:06 2017
 --Host        : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
 --Command     : generate_target system_design.bd
 --Design      : system_design
@@ -4009,70 +4009,6 @@ architecture STRUCTURE of system_design is
     peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
   );
   end component system_design_rst_wrc_1p_kintex7_0_62M_0;
-  component system_design_fasec_hwtest_0_0 is
-  port (
-    ps_clk_i : in STD_LOGIC;
-    osc100_clk_i : in STD_LOGIC;
-    FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
-    FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
-    FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
-    FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
-    FMC2_PRSNTM2C_n_i : in STD_LOGIC;
-    FMC2_CLK0M2C_P_i : in STD_LOGIC;
-    FMC2_CLK0M2C_N_i : in STD_LOGIC;
-    FMC2_CLK0C2M_P_o : out STD_LOGIC;
-    FMC2_CLK0C2M_N_o : out STD_LOGIC;
-    FMC2_GP0_i : in STD_LOGIC;
-    FMC2_GP1_i : in STD_LOGIC;
-    FMC2_GP2_i : in STD_LOGIC;
-    FMC2_GP3_b : inout STD_LOGIC;
-    FMC1_PRSNTM2C_n_i : in STD_LOGIC;
-    FMC1_CLK0M2C_P_i : in STD_LOGIC;
-    FMC1_CLK0M2C_N_i : in STD_LOGIC;
-    FMC1_CLK0C2M_P_o : out STD_LOGIC;
-    FMC1_CLK0C2M_N_o : out STD_LOGIC;
-    FMC1_GP0_i : in STD_LOGIC;
-    FMC1_GP1_i : in STD_LOGIC;
-    FMC1_GP2_i : in STD_LOGIC;
-    FMC1_GP3_b : inout STD_LOGIC;
-    pb_gp_n_i : in STD_LOGIC;
-    led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
-    led_line_en_pl_o : out STD_LOGIC;
-    led_line_pl_o : out STD_LOGIC;
-    watchdog_pl_o : out STD_LOGIC;
-    dig_in1_i : in STD_LOGIC;
-    dig_in2_i : in STD_LOGIC;
-    dig_in3_n_i : in STD_LOGIC;
-    dig_in4_n_i : in STD_LOGIC;
-    dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
-    dig_out5_n : out STD_LOGIC;
-    dig_out6_n : out STD_LOGIC;
-    gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
-    intr_o : out STD_LOGIC;
-    intr_led_o : out STD_LOGIC;
-    s00_axi_aclk : in STD_LOGIC;
-    s00_axi_aresetn : in STD_LOGIC;
-    s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
-    s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
-    s00_axi_awvalid : in STD_LOGIC;
-    s00_axi_awready : out STD_LOGIC;
-    s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
-    s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
-    s00_axi_wvalid : in STD_LOGIC;
-    s00_axi_wready : out STD_LOGIC;
-    s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
-    s00_axi_bvalid : out STD_LOGIC;
-    s00_axi_bready : in STD_LOGIC;
-    s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
-    s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
-    s00_axi_arvalid : in STD_LOGIC;
-    s00_axi_arready : out STD_LOGIC;
-    s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
-    s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
-    s00_axi_rvalid : out STD_LOGIC;
-    s00_axi_rready : in STD_LOGIC
-  );
-  end component system_design_fasec_hwtest_0_0;
   component system_design_axi_wb_i2c_master_0_1 is
   port (
     i2c_scl_io : inout STD_LOGIC;
@@ -4191,6 +4127,70 @@ architecture STRUCTURE of system_design is
     s00_axi_rready : in STD_LOGIC
   );
   end component system_design_wrc_1p_kintex7_0_0;
+  component system_design_fasec_hwtest_0_0 is
+  port (
+    ps_clk_i : in STD_LOGIC;
+    osc100_clk_i : in STD_LOGIC;
+    FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+    FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+    FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+    FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+    FMC2_PRSNTM2C_n_i : in STD_LOGIC;
+    FMC2_CLK0M2C_P_i : in STD_LOGIC;
+    FMC2_CLK0M2C_N_i : in STD_LOGIC;
+    FMC2_CLK0C2M_P_o : out STD_LOGIC;
+    FMC2_CLK0C2M_N_o : out STD_LOGIC;
+    FMC2_GP0_i : in STD_LOGIC;
+    FMC2_GP1_i : in STD_LOGIC;
+    FMC2_GP2_i : in STD_LOGIC;
+    FMC2_GP3_b : inout STD_LOGIC;
+    FMC1_PRSNTM2C_n_i : in STD_LOGIC;
+    FMC1_CLK0M2C_P_i : in STD_LOGIC;
+    FMC1_CLK0M2C_N_i : in STD_LOGIC;
+    FMC1_CLK0C2M_P_o : out STD_LOGIC;
+    FMC1_CLK0C2M_N_o : out STD_LOGIC;
+    FMC1_GP0_i : in STD_LOGIC;
+    FMC1_GP1_i : in STD_LOGIC;
+    FMC1_GP2_i : in STD_LOGIC;
+    FMC1_GP3_b : inout STD_LOGIC;
+    pb_gp_n_i : in STD_LOGIC;
+    led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    led_line_en_pl_o : out STD_LOGIC;
+    led_line_pl_o : out STD_LOGIC;
+    watchdog_pl_o : out STD_LOGIC;
+    dig_in1_i : in STD_LOGIC;
+    dig_in2_i : in STD_LOGIC;
+    dig_in3_n_i : in STD_LOGIC;
+    dig_in4_n_i : in STD_LOGIC;
+    dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    dig_out5_n : out STD_LOGIC;
+    dig_out6_n : out STD_LOGIC;
+    gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    intr_o : out STD_LOGIC;
+    intr_led_o : out STD_LOGIC;
+    s00_axi_aclk : in STD_LOGIC;
+    s00_axi_aresetn : in STD_LOGIC;
+    s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    s00_axi_awvalid : in STD_LOGIC;
+    s00_axi_awready : out STD_LOGIC;
+    s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s00_axi_wvalid : in STD_LOGIC;
+    s00_axi_wready : out STD_LOGIC;
+    s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s00_axi_bvalid : out STD_LOGIC;
+    s00_axi_bready : in STD_LOGIC;
+    s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    s00_axi_arvalid : in STD_LOGIC;
+    s00_axi_arready : out STD_LOGIC;
+    s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s00_axi_rvalid : out STD_LOGIC;
+    s00_axi_rready : in STD_LOGIC
+  );
+  end component system_design_fasec_hwtest_0_0;
   signal FMC1_CLK0M2C_N_i_1 : STD_LOGIC;
   signal FMC1_CLK0M2C_P_i_1 : STD_LOGIC;
   signal FMC1_PRSNTM2C_n_i_1 : STD_LOGIC;
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
index 81188bf2719509efae3ca271a6c4d10c2f982f25..483fc098980346fc4635975a1197b9dd2ac28a33 100644
--- a/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
@@ -46,8 +46,8 @@
 -- 
 -- DO NOT MODIFY THIS FILE.
 
--- IP VLNV: user.org:user:fasec_hwtest:3.2.0
--- IP Revision: 27
+-- IP VLNV: user.org:user:fasec_hwtest:3.2.1
+-- IP Revision: 29
 
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
similarity index 94%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
index 55c96e87d38820a900247767cf454795764dcb4d..18a82b67dadaacd58f989d82600c483a1da3002a 100755
--- a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
+++ b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
@@ -6,7 +6,7 @@
 -- Author     : Pieter Van Trappen  <pvantrap@cern.ch>
 -- Company    : CERN
 -- Created    : 2016-11-22
--- Last update: 2017-04-12
+-- Last update: 2017-05-11
 -- Platform   : 
 -- Standard   : VHDL'93/02
 -------------------------------------------------------------------------------
@@ -112,6 +112,7 @@ architecture rtl of general_fmc is
   type t_cmplengths is array (0 to c_COMP-1) of std_logic_vector(c_COUNTERWIDTH-1 downto 0);
   signal s_cmp_lengths   : t_cmplengths;
   signal s_diffouts_o    : std_logic_vector(c_DOUTS-1 downto 0);
+  signal s_outleds	: std_logic_vector(c_DOUTS-1 downto 0);
   signal s_outsfeedbak_i : std_logic_vector(c_OUTFBD-1 downto 0);
   signal s_spi_sclk      : std_logic;
   signal s_spi_mosi      : std_logic;
@@ -201,6 +202,7 @@ begin
   -- outputs loop
   fmc_03287_obufds : for I in 0 to c_DOUTS-1 generate
     gen_outs : if g_FMC = "EDA-03287" generate
+      -- output LVDS buffers
       cmp_OBUFDS_fmc : OBUFDS
         generic map (
 --          IOSTANDARD => "LVDS_25",      -- Specify the output I/O standard
@@ -209,6 +211,24 @@ begin
           O  => FMC_LA_P_b(c_COMP+I),  -- Diff_p output (connect directly to top-level port)
           OB => FMC_LA_N_b(c_COMP+I),  -- Diff_n output (connect directly to top-level port)
           I  => s_diffouts_o(I));       -- Buffer input
+      -- pulse extenders for LEDs
+      cmp_outs_pulseMeasure : pulseMeasure
+        generic map (
+          g_COUNTERWIDTH    => c_COUNTERWIDTH,
+          g_LEDCOUNTERWIDTH => c_LEDCOUNTERWIDTH,
+          g_LEDWAIT         => 10000000,  -- 100ms when 10ns clock
+          g_MISSINGCDC      => false)
+        port map (
+          clk_dsp_i       => clk_i,     -- for now no clock domain crossing
+          reset_n_i       => s_reset_n,
+          pulse_i         => s_diffouts_o(I),
+          missingWindow_i => to_unsigned(0, c_LEDCOUNTERWIDTH),
+          pulse_o         => open,
+          edgeDetected_o  => open,
+          usrLed_o        => s_outleds(I),
+          window_o        => open,
+          pulseLength_o   => open,
+          LedCount_o      => open);
     end generate gen_outs;
   end generate fmc_03287_obufds;
   -- SPI DAC for comparator reference
@@ -270,6 +290,7 @@ begin
     variable v_cmpled : std_logic_vector(c_COMP-1 downto 0);
     variable v_dout   : std_logic_vector(c_DOUTS-1 downto 0);
     variable v_fbd    : std_logic_vector(c_OUTFBD-1 downto 0);
+    variable v_outleds : std_logic_vector(c_DOUTS-1 downto 0);
   begin
     if g_FMC = "EDA-03287" and rising_edge(clk_i) then
       -- in/outputs
@@ -284,7 +305,7 @@ begin
       else
         intr_o <= '0';
       end if;
-      if (v_cmpled /= s_compleds) then
+      if (v_cmpled /= s_compleds) or (v_outleds /= s_outleds) then
         intr_led_o <= '1';
       else
         intr_led_o <= '0';
@@ -292,6 +313,7 @@ begin
       -- clocking in data for above interrupt generation
       v_cmpled := s_compleds(c_COMP-1 downto 0);
       v_cmp    := s_cmp_pulse(c_COMP-1 downto 0);
+      v_outleds := s_outleds(c_DOUTS-1 downto 0);
     end if;
   end process p_fmc_03287_io;
   -- no additional clocking of comparators & LEDs
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
diff --git a/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd b/FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd
similarity index 100%
rename from FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd
rename to FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt
index 7d3d2b1289cb55c72ff682e4f3498a75708bec4f..390a971044e42b1ee1d912440e32573bc664328a 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Apr 13 09:58:27 CEST 2017
+# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
 #
 ################################################################################
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do
index 6344b1234d77f0bfbb0c88cc1241254c9ae456a4..184b01cc98f34627b0f14747543955abe4e6fd1f 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do
@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1
 "../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
 
 vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
 
 vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
 "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
 
 vcom -work lib_cdc_v1_0_2 -93 \
@@ -576,6 +576,7 @@ vcom -work xil_defaultlib -93 \
 "../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
 "../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
 "../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
+"../../../bd/system_design/hdl/system_design.vhd" \
 
 vlog -work axi_protocol_converter_v2_1_9 -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
 "../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v" \
@@ -603,8 +604,5 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1
 "../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v" \
 "../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v" \
 
-vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/hdl/system_design.vhd" \
-
 vlog -work xil_defaultlib "glbl.v"
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt
index b3e1417c1fc80a3cee049ae36b8e83190e744d24..733ef8658ef2f8c740d7b952bcca80f1e11fc836 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/file_info.txt
@@ -1,12 +1,12 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_wr.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_rd.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_wr_4.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
 processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -400,6 +400,7 @@ axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/ce
 system_design_axi_wb_i2c_master_2_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_axi_wb_i2c_master_0_1.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+system_design.vhd,vhdl,xil_defaultlib,../../../bd/system_design/hdl/system_design.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_a_axi3_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_axi3_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_axilite_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -422,5 +423,4 @@ axi_protocol_converter_v2_1_axi_protocol_converter.v,verilog,axi_protocol_conver
 system_design_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_0/sim/system_design_auto_pc_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_auto_pc_1.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_auto_pc_2.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-system_design.vhd,vhdl,xil_defaultlib,../../../bd/system_design/hdl/system_design.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh
index 18e2d583a7293ced2478c1f6d035dcad35d3cf7e..3017f19f61ad75080709256d749e4fd75cf746a3 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh
@@ -8,7 +8,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Apr 13 09:58:27 CEST 2017
+# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016 
 #
 # usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt
index 7d3d2b1289cb55c72ff682e4f3498a75708bec4f..390a971044e42b1ee1d912440e32573bc664328a 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Apr 13 09:58:27 CEST 2017
+# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
 #
 ################################################################################
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt
index e6c09f3b11194b72ecbaa95ced32614ce676b751..09a8bd1f97c2ff223cc0f83869c2963b1a65e24a 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/file_info.txt
@@ -1,12 +1,12 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_wr.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_rd.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_wr_4.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
 processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -400,6 +400,7 @@ axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/ce
 system_design_axi_wb_i2c_master_2_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_axi_wb_i2c_master_0_1.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+system_design.vhd,vhdl,xil_defaultlib,../../../bd/system_design/hdl/system_design.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_a_axi3_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_axi3_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_axilite_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -422,5 +423,4 @@ axi_protocol_converter_v2_1_axi_protocol_converter.v,verilog,axi_protocol_conver
 system_design_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_0/sim/system_design_auto_pc_0.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_auto_pc_1.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_auto_pc_2.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-system_design.vhd,vhdl,xil_defaultlib,../../../bd/system_design/hdl/system_design.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f
index d602eb0fd2e7cbb6dbaed842dc56b971206497fc..9682c8dca53aa2b2e1bb6d193e6abea03fc8988b 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f
@@ -40,22 +40,22 @@
   "../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
 -endlib
 -makelib ies/hdl_lib \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
 -endlib
 -makelib ies/xil_defaultlib \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
 -endlib
 -makelib ies/hdl_lib \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
 -endlib
 -makelib ies/xil_defaultlib \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+  "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
   "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
 -endlib
 -makelib ies/lib_cdc_v1_0_2 \
@@ -525,6 +525,7 @@
   "../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
   "../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
   "../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
+  "../../../bd/system_design/hdl/system_design.vhd" \
 -endlib
 -makelib ies/axi_protocol_converter_v2_1_9 \
   "../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v" \
@@ -552,9 +553,6 @@
   "../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v" \
   "../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v" \
 -endlib
--makelib ies/xil_defaultlib \
-  "../../../bd/system_design/hdl/system_design.vhd" \
--endlib
 -makelib ies/xil_defaultlib \
   glbl.v
 -endlib
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh
index d7c24cd37b9b6407aae8e2485800dcb4423409d9..1e73aa92c0ad5c7cf7906a93ab13b8c660e33f62 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh
@@ -8,7 +8,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Apr 13 09:58:27 CEST 2017
+# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016 
 #
 # usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt
index 7d3d2b1289cb55c72ff682e4f3498a75708bec4f..390a971044e42b1ee1d912440e32573bc664328a 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Apr 13 09:58:27 CEST 2017
+# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
 #
 ################################################################################
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do
index 3f5b8773dc8ec88b11c17fc894b07c76bb124932..23391578fa0116be3fc67643ae61bf471f81a6c3 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do
@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructur
 "../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
 
 vcom -work hdl_lib -64 -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
 
 vcom -work hdl_lib -64 -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
 
 vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
 "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
 
 vcom -work lib_cdc_v1_0_2 -64 -93 \
@@ -576,6 +576,7 @@ vcom -work xil_defaultlib -64 -93 \
 "../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
 "../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
 "../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
+"../../../bd/system_design/hdl/system_design.vhd" \
 
 vlog -work axi_protocol_converter_v2_1_9 -64 -incr "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
 "../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v" \
@@ -603,8 +604,5 @@ vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructur
 "../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v" \
 "../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v" \
 
-vcom -work xil_defaultlib -64 -93 \
-"../../../bd/system_design/hdl/system_design.vhd" \
-
 vlog -work xil_defaultlib "glbl.v"
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt
index b3e1417c1fc80a3cee049ae36b8e83190e744d24..733ef8658ef2f8c740d7b952bcca80f1e11fc836 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/file_info.txt
@@ -1,12 +1,12 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_wr.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_rd.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_wr_4.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
 processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -400,6 +400,7 @@ axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/ce
 system_design_axi_wb_i2c_master_2_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_axi_wb_i2c_master_0_1.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+system_design.vhd,vhdl,xil_defaultlib,../../../bd/system_design/hdl/system_design.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_a_axi3_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_axi3_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_axilite_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -422,5 +423,4 @@ axi_protocol_converter_v2_1_axi_protocol_converter.v,verilog,axi_protocol_conver
 system_design_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_0/sim/system_design_auto_pc_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_auto_pc_1.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_auto_pc_2.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-system_design.vhd,vhdl,xil_defaultlib,../../../bd/system_design/hdl/system_design.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh
index d76df66edf9c4fe8d4687e272f36635fd8a6d7f2..d5f863a22627c9cc75440fddf26472c4fb3b174a 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh
@@ -8,7 +8,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Apr 13 09:58:27 CEST 2017
+# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016 
 #
 # usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt
index 7d3d2b1289cb55c72ff682e4f3498a75708bec4f..390a971044e42b1ee1d912440e32573bc664328a 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Apr 13 09:58:27 CEST 2017
+# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
 #
 ################################################################################
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do
index 31fa7a2f38a4ce80224827b6400edc5f2fdc99a9..cd8390a3660eafe22089747a9e9617d8c6954076 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do
@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1
 "../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
 
 vcom -work hdl_lib -64 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
 
 vcom -work hdl_lib -64 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
 
 vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
 "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
 
 vcom -work lib_cdc_v1_0_2 -64 \
@@ -576,6 +576,7 @@ vcom -work xil_defaultlib -64 \
 "../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
 "../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
 "../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
+"../../../bd/system_design/hdl/system_design.vhd" \
 
 vlog -work axi_protocol_converter_v2_1_9 -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
 "../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v" \
@@ -603,8 +604,5 @@ vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1
 "../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v" \
 "../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v" \
 
-vcom -work xil_defaultlib -64 \
-"../../../bd/system_design/hdl/system_design.vhd" \
-
 vlog -work xil_defaultlib "glbl.v"
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt
index b3e1417c1fc80a3cee049ae36b8e83190e744d24..733ef8658ef2f8c740d7b952bcca80f1e11fc836 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/file_info.txt
@@ -1,12 +1,12 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_wr.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_rd.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_wr_4.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
 processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -400,6 +400,7 @@ axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/ce
 system_design_axi_wb_i2c_master_2_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_axi_wb_i2c_master_0_1.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+system_design.vhd,vhdl,xil_defaultlib,../../../bd/system_design/hdl/system_design.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_a_axi3_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_axi3_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_axilite_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -422,5 +423,4 @@ axi_protocol_converter_v2_1_axi_protocol_converter.v,verilog,axi_protocol_conver
 system_design_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_0/sim/system_design_auto_pc_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_auto_pc_1.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_auto_pc_2.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-system_design.vhd,vhdl,xil_defaultlib,../../../bd/system_design/hdl/system_design.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh
index 705e8659acdcff7245214e6c7867678f333714e7..d684db329c3441de8d23b7157aedf35148ae501f 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh
@@ -8,7 +8,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Apr 13 09:58:27 CEST 2017
+# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016 
 #
 # usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt
index 7d3d2b1289cb55c72ff682e4f3498a75708bec4f..390a971044e42b1ee1d912440e32573bc664328a 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Apr 13 09:58:27 CEST 2017
+# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
 #
 ################################################################################
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do
index f98635a08234bb2041ccccaba8c8b68427f91f30..45be97f76b7dd1454062e99bb7b4b78f0464b712 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do
@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1
 "../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
 
 vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
 
 vcom -work hdl_lib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
 
 vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
 "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
 
 vcom -work lib_cdc_v1_0_2 -93 \
@@ -576,6 +576,7 @@ vcom -work xil_defaultlib -93 \
 "../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
 "../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
 "../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
+"../../../bd/system_design/hdl/system_design.vhd" \
 
 vlog -work axi_protocol_converter_v2_1_9 -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
 "../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v" \
@@ -603,8 +604,5 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1
 "../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v" \
 "../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v" \
 
-vcom -work xil_defaultlib -93 \
-"../../../bd/system_design/hdl/system_design.vhd" \
-
 vlog -work xil_defaultlib "glbl.v"
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt
index b3e1417c1fc80a3cee049ae36b8e83190e744d24..733ef8658ef2f8c740d7b952bcca80f1e11fc836 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/file_info.txt
@@ -1,12 +1,12 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_wr.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_rd.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_wr_4.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
 processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -400,6 +400,7 @@ axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/ce
 system_design_axi_wb_i2c_master_2_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_axi_wb_i2c_master_0_1.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+system_design.vhd,vhdl,xil_defaultlib,../../../bd/system_design/hdl/system_design.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_a_axi3_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_axi3_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_axilite_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -422,5 +423,4 @@ axi_protocol_converter_v2_1_axi_protocol_converter.v,verilog,axi_protocol_conver
 system_design_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_0/sim/system_design_auto_pc_0.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_auto_pc_1.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_auto_pc_2.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-system_design.vhd,vhdl,xil_defaultlib,../../../bd/system_design/hdl/system_design.vhd,incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh
index 48e809bfb4682b1c08cfafea7e7472a39af395c2..66644badafb0edfc51c3e6fb2b0af04f95280117 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh
@@ -8,7 +8,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Apr 13 09:58:27 CEST 2017
+# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016 
 #
 # usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt
index 7d3d2b1289cb55c72ff682e4f3498a75708bec4f..390a971044e42b1ee1d912440e32573bc664328a 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Apr 13 09:58:27 CEST 2017
+# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
 #
 ################################################################################
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt
index e6c09f3b11194b72ecbaa95ced32614ce676b751..09a8bd1f97c2ff223cc0f83869c2963b1a65e24a 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/file_info.txt
@@ -1,12 +1,12 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_wr.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_rd.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_wr_4.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
 processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -400,6 +400,7 @@ axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/ce
 system_design_axi_wb_i2c_master_2_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_axi_wb_i2c_master_0_1.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+system_design.vhd,vhdl,xil_defaultlib,../../../bd/system_design/hdl/system_design.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_a_axi3_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_axi3_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_axilite_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -422,5 +423,4 @@ axi_protocol_converter_v2_1_axi_protocol_converter.v,verilog,axi_protocol_conver
 system_design_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_0/sim/system_design_auto_pc_0.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_auto_pc_1.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_auto_pc_2.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-system_design.vhd,vhdl,xil_defaultlib,../../../bd/system_design/hdl/system_design.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh
index b677f0491319223ddacd25a1dbe222fbd9096f85..96c5130d83702ba356cd3c23671c29274d26cf94 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh
@@ -8,7 +8,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Apr 13 09:58:27 CEST 2017
+# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016 
 #
 # usage: system_design.sh [-help]
@@ -113,25 +113,25 @@ compile()
   2>&1 | tee -a vlogan.log
 
   vhdlan -work hdl_lib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vhdlan -work hdl_lib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
-    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
+    "$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
     "$ref_dir/../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
   2>&1 | tee -a vhdlan.log
 
@@ -656,6 +656,7 @@ compile()
     "$ref_dir/../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
     "$ref_dir/../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
     "$ref_dir/../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
+    "$ref_dir/../../../bd/system_design/hdl/system_design.vhd" \
   2>&1 | tee -a vhdlan.log
 
   vlogan -work axi_protocol_converter_v2_1_9 $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" +incdir+"$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
@@ -686,10 +687,6 @@ compile()
     "$ref_dir/../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v" \
   2>&1 | tee -a vlogan.log
 
-  vhdlan -work xil_defaultlib $vhdlan_opts \
-    "$ref_dir/../../../bd/system_design/hdl/system_design.vhd" \
-  2>&1 | tee -a vhdlan.log
-
 
   vlogan -work xil_defaultlib $vlogan_opts +v2k \
     glbl.v \
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt
index 7d3d2b1289cb55c72ff682e4f3498a75708bec4f..390a971044e42b1ee1d912440e32573bc664328a 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu Apr 13 09:58:27 CEST 2017
+# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
 #
 ################################################################################
 
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt
index e6c09f3b11194b72ecbaa95ced32614ce676b751..09a8bd1f97c2ff223cc0f83869c2963b1a65e24a 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/file_info.txt
@@ -1,12 +1,12 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_base.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dpdistram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_dprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_spram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_sprom.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_memory_tdpram.sv,systemverilog,xil_defaultlib,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_wr.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_rd.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_rd.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_arb_wr_4.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr_4.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -31,16 +31,16 @@ processing_system7_bfm_v2_0_axi_master.v,verilog,processing_system7_bfm_v2_0_5,.
 processing_system7_bfm_v2_0_afi_slave.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_afi_slave.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 processing_system7_bfm_v2_0_processing_system7_bfm.v,verilog,processing_system7_bfm_v2_0_5,../../../ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_processing_system7_bfm.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+spi_transceiver.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+doubleBufferEdge.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+counterUpDown.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+main_pkg.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+pulseMeasure.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+dac7716_spi.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+axi4lite_slave.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+clockDivider.vhd,vhdl,hdl_lib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+general_fmc.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+top_mod.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_fasec_hwtest_0_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 cdc_sync.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 upcnt_n.vhd,vhdl,proc_sys_reset_v5_0_9,../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -400,6 +400,7 @@ axis_to_i2c_wbs_tb.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ipshared/ce
 system_design_axi_wb_i2c_master_2_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_axi_wb_i2c_master_0_1.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,vhdl,xil_defaultlib,../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
+system_design.vhd,vhdl,xil_defaultlib,../../../bd/system_design/hdl/system_design.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_a_axi3_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_axi3_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 axi_protocol_converter_v2_1_axilite_conv.v,verilog,axi_protocol_converter_v2_1_9,../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
@@ -422,5 +423,4 @@ axi_protocol_converter_v2_1_axi_protocol_converter.v,verilog,axi_protocol_conver
 system_design_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_0/sim/system_design_auto_pc_0.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_auto_pc_1.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 system_design_auto_pc_2.v,verilog,xil_defaultlib,../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
-system_design.vhd,vhdl,xil_defaultlib,../../../bd/system_design/hdl/system_design.vhd,incdir="$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl"incdir="../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog"incdir="../../../ipstatic/processing_system7_bfm_v2_0/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh
index 9bb662ffdc4581bf56f6a5e45cc7d9b789806240..daac5c303b4e851fe7a3d4bc8054f67f2ab027a4 100755
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh
@@ -8,7 +8,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu Apr 13 09:58:27 CEST 2017
+# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
 # IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016 
 #
 # usage: system_design.sh [-help]
diff --git a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj
index 694db11fea47060323ac7b36e0d9c4639a701d10..5f5a57a61ed7411498fa878cdb1632c0d0cd9d4b 100644
--- a/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj
+++ b/FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj
@@ -1,14 +1,14 @@
 vhdl xpm "/local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" 
-vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" 
-vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" 
+vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" 
+vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" 
 vhdl xil_defaultlib "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" 
 vhdl lib_cdc_v1_0_2 "../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd" 
 vhdl proc_sys_reset_v5_0_9 "../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd" 
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef
index ae3f9931b323014afe9137237c32ef06046b44ca..1797c350a198322a8a586b78a8ba42e9faf100d8 100644
Binary files a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef and b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.hwdef differ
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
index 034fae5ce15ebcb04a6b7eda21e96cab0f2a5ad3..4cb515f13180be5fbcebb4e0c0e8c4116ce641a9 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
@@ -1,7 +1,7 @@
 --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------
 --Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
---Date        : Thu Apr 13 09:57:53 2017
+--Date        : Thu May 11 16:53:06 2017
 --Host        : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
 --Command     : generate_target system_design.bd
 --Design      : system_design
@@ -4009,70 +4009,6 @@ architecture STRUCTURE of system_design is
     peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
   );
   end component system_design_rst_wrc_1p_kintex7_0_62M_0;
-  component system_design_fasec_hwtest_0_0 is
-  port (
-    ps_clk_i : in STD_LOGIC;
-    osc100_clk_i : in STD_LOGIC;
-    FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
-    FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
-    FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
-    FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
-    FMC2_PRSNTM2C_n_i : in STD_LOGIC;
-    FMC2_CLK0M2C_P_i : in STD_LOGIC;
-    FMC2_CLK0M2C_N_i : in STD_LOGIC;
-    FMC2_CLK0C2M_P_o : out STD_LOGIC;
-    FMC2_CLK0C2M_N_o : out STD_LOGIC;
-    FMC2_GP0_i : in STD_LOGIC;
-    FMC2_GP1_i : in STD_LOGIC;
-    FMC2_GP2_i : in STD_LOGIC;
-    FMC2_GP3_b : inout STD_LOGIC;
-    FMC1_PRSNTM2C_n_i : in STD_LOGIC;
-    FMC1_CLK0M2C_P_i : in STD_LOGIC;
-    FMC1_CLK0M2C_N_i : in STD_LOGIC;
-    FMC1_CLK0C2M_P_o : out STD_LOGIC;
-    FMC1_CLK0C2M_N_o : out STD_LOGIC;
-    FMC1_GP0_i : in STD_LOGIC;
-    FMC1_GP1_i : in STD_LOGIC;
-    FMC1_GP2_i : in STD_LOGIC;
-    FMC1_GP3_b : inout STD_LOGIC;
-    pb_gp_n_i : in STD_LOGIC;
-    led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
-    led_line_en_pl_o : out STD_LOGIC;
-    led_line_pl_o : out STD_LOGIC;
-    watchdog_pl_o : out STD_LOGIC;
-    dig_in1_i : in STD_LOGIC;
-    dig_in2_i : in STD_LOGIC;
-    dig_in3_n_i : in STD_LOGIC;
-    dig_in4_n_i : in STD_LOGIC;
-    dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
-    dig_out5_n : out STD_LOGIC;
-    dig_out6_n : out STD_LOGIC;
-    gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
-    intr_o : out STD_LOGIC;
-    intr_led_o : out STD_LOGIC;
-    s00_axi_aclk : in STD_LOGIC;
-    s00_axi_aresetn : in STD_LOGIC;
-    s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
-    s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
-    s00_axi_awvalid : in STD_LOGIC;
-    s00_axi_awready : out STD_LOGIC;
-    s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
-    s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
-    s00_axi_wvalid : in STD_LOGIC;
-    s00_axi_wready : out STD_LOGIC;
-    s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
-    s00_axi_bvalid : out STD_LOGIC;
-    s00_axi_bready : in STD_LOGIC;
-    s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
-    s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
-    s00_axi_arvalid : in STD_LOGIC;
-    s00_axi_arready : out STD_LOGIC;
-    s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
-    s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
-    s00_axi_rvalid : out STD_LOGIC;
-    s00_axi_rready : in STD_LOGIC
-  );
-  end component system_design_fasec_hwtest_0_0;
   component system_design_axi_wb_i2c_master_0_1 is
   port (
     i2c_scl_io : inout STD_LOGIC;
@@ -4191,6 +4127,70 @@ architecture STRUCTURE of system_design is
     s00_axi_rready : in STD_LOGIC
   );
   end component system_design_wrc_1p_kintex7_0_0;
+  component system_design_fasec_hwtest_0_0 is
+  port (
+    ps_clk_i : in STD_LOGIC;
+    osc100_clk_i : in STD_LOGIC;
+    FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+    FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+    FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+    FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
+    FMC2_PRSNTM2C_n_i : in STD_LOGIC;
+    FMC2_CLK0M2C_P_i : in STD_LOGIC;
+    FMC2_CLK0M2C_N_i : in STD_LOGIC;
+    FMC2_CLK0C2M_P_o : out STD_LOGIC;
+    FMC2_CLK0C2M_N_o : out STD_LOGIC;
+    FMC2_GP0_i : in STD_LOGIC;
+    FMC2_GP1_i : in STD_LOGIC;
+    FMC2_GP2_i : in STD_LOGIC;
+    FMC2_GP3_b : inout STD_LOGIC;
+    FMC1_PRSNTM2C_n_i : in STD_LOGIC;
+    FMC1_CLK0M2C_P_i : in STD_LOGIC;
+    FMC1_CLK0M2C_N_i : in STD_LOGIC;
+    FMC1_CLK0C2M_P_o : out STD_LOGIC;
+    FMC1_CLK0C2M_N_o : out STD_LOGIC;
+    FMC1_GP0_i : in STD_LOGIC;
+    FMC1_GP1_i : in STD_LOGIC;
+    FMC1_GP2_i : in STD_LOGIC;
+    FMC1_GP3_b : inout STD_LOGIC;
+    pb_gp_n_i : in STD_LOGIC;
+    led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    led_line_en_pl_o : out STD_LOGIC;
+    led_line_pl_o : out STD_LOGIC;
+    watchdog_pl_o : out STD_LOGIC;
+    dig_in1_i : in STD_LOGIC;
+    dig_in2_i : in STD_LOGIC;
+    dig_in3_n_i : in STD_LOGIC;
+    dig_in4_n_i : in STD_LOGIC;
+    dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    dig_out5_n : out STD_LOGIC;
+    dig_out6_n : out STD_LOGIC;
+    gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    intr_o : out STD_LOGIC;
+    intr_led_o : out STD_LOGIC;
+    s00_axi_aclk : in STD_LOGIC;
+    s00_axi_aresetn : in STD_LOGIC;
+    s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    s00_axi_awvalid : in STD_LOGIC;
+    s00_axi_awready : out STD_LOGIC;
+    s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s00_axi_wvalid : in STD_LOGIC;
+    s00_axi_wready : out STD_LOGIC;
+    s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s00_axi_bvalid : out STD_LOGIC;
+    s00_axi_bready : in STD_LOGIC;
+    s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    s00_axi_arvalid : in STD_LOGIC;
+    s00_axi_arready : out STD_LOGIC;
+    s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s00_axi_rvalid : out STD_LOGIC;
+    s00_axi_rready : in STD_LOGIC
+  );
+  end component system_design_fasec_hwtest_0_0;
   signal FMC1_CLK0M2C_N_i_1 : STD_LOGIC;
   signal FMC1_CLK0M2C_P_i_1 : STD_LOGIC;
   signal FMC1_PRSNTM2C_n_i_1 : STD_LOGIC;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
index 2c14804ece0706764a8e72de1b31a19ece56d4fc..d64bea6a609672fc07fac39699fb905b212997e7 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
@@ -1,7 +1,7 @@
 --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------
 --Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
---Date        : Thu Apr 13 09:57:53 2017
+--Date        : Thu May 11 16:53:07 2017
 --Host        : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
 --Command     : generate_target system_design_wrapper.bd
 --Design      : system_design_wrapper
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
index a84769904cec5326444c2bdfd11960021375df20..5815a17c151637ff4e5b0532a476636403e78fc1 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu Apr 13 09:58:22 2017" VIVADOVERSION="2016.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu May 11 16:53:08 2017" VIVADOVERSION="2016.2">
 
   <SYSTEMINFO ARCH="zynq" DEVICE="7z030" NAME="system_design" PACKAGE="ffg676" SPEEDGRADE="-2"/>
 
@@ -51,8 +51,8 @@
     <PORT DIR="IO" NAME="gtp_wr_scl" SIGIS="undef"/>
     <PORT DIR="I" NAME="pb_gp_i" SIGIS="undef" SIGNAME="External_Ports_pb_gp_i">
       <CONNECTIONS>
-        <CONNECTION INSTANCE="fasec_hwtest_0" PORT="pb_gp_n_i"/>
         <CONNECTION INSTANCE="wrc_1p_kintex7_0" PORT="button_rst_n_i"/>
+        <CONNECTION INSTANCE="fasec_hwtest_0" PORT="pb_gp_n_i"/>
       </CONNECTIONS>
     </PORT>
     <PORT DIR="O" LEFT="3" NAME="led_col_pl_o" RIGHT="0" SIGIS="undef" SIGNAME="fasec_hwtest_0_led_col_pl_o">
@@ -3685,7 +3685,7 @@
         </BUSINTERFACE>
       </BUSINTERFACES>
     </MODULE>
-    <MODULE FULLNAME="/fasec_hwtest_0" HWVERSION="3.2.0" INSTANCE="fasec_hwtest_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="fasec_hwtest" VLNV="user.org:user:fasec_hwtest:3.2.0">
+    <MODULE FULLNAME="/fasec_hwtest_0" HWVERSION="3.2.1" INSTANCE="fasec_hwtest_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="fasec_hwtest" VLNV="user.org:user:fasec_hwtest:3.2.1">
       <DOCUMENTS/>
       <ADDRESSBLOCKS>
         <ADDRESSBLOCK ACCESS="" INTERFACE="S00_AXI" NAME="S00_AXI_reg" RANGE="4096" USAGE=""/>
@@ -5585,8 +5585,8 @@
             <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_aclk"/>
             <CONNECTION INSTANCE="xadc_wiz_0" PORT="s_axis_aclk"/>
             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aclk"/>
-            <CONNECTION INSTANCE="fasec_hwtest_0" PORT="ps_clk_i"/>
-            <CONNECTION INSTANCE="fasec_hwtest_0" PORT="s00_axi_aclk"/>
+            <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aclk"/>
+            <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aclk"/>
             <CONNECTION INSTANCE="axi_interconnect_0" PORT="ACLK"/>
             <CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="ACLK"/>
             <CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M06_ACLK"/>
@@ -5600,8 +5600,8 @@
             <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_ACLK"/>
             <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_ACLK"/>
             <CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M07_ACLK"/>
-            <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aclk"/>
-            <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aclk"/>
+            <CONNECTION INSTANCE="fasec_hwtest_0" PORT="ps_clk_i"/>
+            <CONNECTION INSTANCE="fasec_hwtest_0" PORT="s00_axi_aclk"/>
           </CONNECTIONS>
         </PORT>
         <PORT CLKFREQUENCY="10000000" DIR="O" NAME="FCLK_CLK1" SIGIS="clk"/>
@@ -7423,7 +7423,8 @@
             <CONNECTION INSTANCE="axi_dma_0" PORT="axi_resetn"/>
             <CONNECTION INSTANCE="xadc_axis_fifo_adapter_0" PORT="AXIS_RESET_N"/>
             <CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aresetn"/>
-            <CONNECTION INSTANCE="fasec_hwtest_0" PORT="s00_axi_aresetn"/>
+            <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aresetn"/>
+            <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aresetn"/>
             <CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="S00_ARESETN"/>
             <CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M06_ARESETN"/>
             <CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M05_ARESETN"/>
@@ -7436,8 +7437,7 @@
             <CONNECTION INSTANCE="axi_interconnect_0" PORT="ARESETN"/>
             <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_ARESETN"/>
             <CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M07_ARESETN"/>
-            <CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aresetn"/>
-            <CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aresetn"/>
+            <CONNECTION INSTANCE="fasec_hwtest_0" PORT="s00_axi_aresetn"/>
           </CONNECTIONS>
         </PORT>
       </PORTS>
@@ -7486,9 +7486,9 @@
         </PORT>
         <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" RIGHT="0" SIGIS="rst" SIGNAME="rst_wrc_1p_kintex7_0_62M_peripheral_aresetn">
           <CONNECTIONS>
+            <CONNECTION INSTANCE="wrc_1p_kintex7_0" PORT="s00_axi_aresetn"/>
             <CONNECTION INSTANCE="axi_interconnect_1" PORT="M00_ARESETN"/>
             <CONNECTION INSTANCE="axi_interconnect_1" PORT="S00_ARESETN"/>
-            <CONNECTION INSTANCE="wrc_1p_kintex7_0" PORT="s00_axi_aresetn"/>
           </CONNECTIONS>
         </PORT>
       </PORTS>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
index 8aeab6115b30d4b658c4f1680bf86df8703f1636..5ba3208cd5af073743186cae0a055743b8b4e037 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
@@ -247,7 +247,7 @@ CONFIG.C_S_AXI_ACLK_FREQ_HZ.VALUE_SRC {DEFAULT} \
   set axi_wb_i2c_master_2 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.1.1 axi_wb_i2c_master_2 ]
 
   # Create instance: fasec_hwtest_0, and set properties
-  set fasec_hwtest_0 [ create_bd_cell -type ip -vlnv user.org:user:fasec_hwtest:3.2.0 fasec_hwtest_0 ]
+  set fasec_hwtest_0 [ create_bd_cell -type ip -vlnv user.org:user:fasec_hwtest:3.2.1 fasec_hwtest_0 ]
   set_property -dict [ list \
 CONFIG.g_FMC1 {EDA-03287} \
 CONFIG.g_FMC2 {EDA-03287} \
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
index 5f20d8e5df7efb4f5926373d45ef9f47ab560910..5cb803725c3bf3d6c2ddb4f4affd5dea3d4eb3f9 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
@@ -1055,7 +1055,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1085,7 +1085,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1116,7 +1116,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1162,7 +1162,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1193,7 +1193,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
index 946961f90177bef5ae27bec181bd163caa75479a..0e75260c58a755948ab3af7405c0952325ee7619 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
@@ -1055,7 +1055,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1085,7 +1085,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1116,7 +1116,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1162,7 +1162,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1193,7 +1193,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
index 2b3af8bcc95bf714e6c3f32a64044b1a621a31d3..7b0ffdae712aae005cef3a1ff7533557bec4ac30 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
@@ -1055,7 +1055,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1085,7 +1085,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1116,7 +1116,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1162,7 +1162,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -1193,7 +1193,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
index 81188bf2719509efae3ca271a6c4d10c2f982f25..483fc098980346fc4635975a1197b9dd2ac28a33 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
@@ -46,8 +46,8 @@
 -- 
 -- DO NOT MODIFY THIS FILE.
 
--- IP VLNV: user.org:user:fasec_hwtest:3.2.0
--- IP Revision: 27
+-- IP VLNV: user.org:user:fasec_hwtest:3.2.1
+-- IP Revision: 29
 
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/synth/system_design_fasec_hwtest_0_0.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/synth/system_design_fasec_hwtest_0_0.vhd
index 9cf20c3c01da65bce7012df0e3bcbcdc77d8e4a4..9dc64dd6b3b2686817d576b6167b41ed391f9130 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/synth/system_design_fasec_hwtest_0_0.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/synth/system_design_fasec_hwtest_0_0.vhd
@@ -46,8 +46,8 @@
 -- 
 -- DO NOT MODIFY THIS FILE.
 
--- IP VLNV: user.org:user:fasec_hwtest:3.2.0
--- IP Revision: 27
+-- IP VLNV: user.org:user:fasec_hwtest:3.2.1
+-- IP Revision: 29
 
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci
index 5250bca814981f0d9c54e6d553a1a1acb3f71254..6f6723c4a2e2bcc26683116d54a39f7a4dd379e2 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci
@@ -7,7 +7,7 @@
   <spirit:componentInstances>
     <spirit:componentInstance>
       <spirit:instanceName>system_design_fasec_hwtest_0_0</spirit:instanceName>
-      <spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="fasec_hwtest" spirit:version="3.2.0"/>
+      <spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="fasec_hwtest" spirit:version="3.2.1"/>
       <spirit:configurableElementValues>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
@@ -61,7 +61,7 @@
         <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">27</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">29</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
index de365e61c26a097c29a440da758949622b26a2a5..f851701d5af64e39acad86b081fd772288f1df70 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
@@ -358,7 +358,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:15 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -370,7 +370,7 @@
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>a92dde1d</spirit:value>
+            <spirit:value>e568c03c</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRCversion</spirit:name>
@@ -389,7 +389,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:15 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -401,7 +401,7 @@
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>a92dde1d</spirit:value>
+            <spirit:value>e568c03c</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRCversion</spirit:name>
@@ -419,7 +419,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:15 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -431,7 +431,7 @@
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>d015f4f5</spirit:value>
+            <spirit:value>a6c6f11b</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRCversion</spirit:name>
@@ -450,7 +450,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Thu Apr 13 07:58:15 UTC 2017</spirit:value>
+            <spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>boundaryCRC</spirit:name>
@@ -462,7 +462,7 @@
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRC</spirit:name>
-            <spirit:value>d015f4f5</spirit:value>
+            <spirit:value>a6c6f11b</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>customizationCRCversion</spirit:name>
@@ -1377,50 +1377,50 @@
         <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
     </spirit:fileSet>
@@ -1435,50 +1435,50 @@
     <spirit:fileSet>
       <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
         <spirit:logicalName>hdl_lib</spirit:logicalName>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
       <spirit:file>
-        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd</spirit:name>
+        <spirit:name>../../ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
       </spirit:file>
     </spirit:fileSet>
@@ -1526,7 +1526,7 @@
   <spirit:vendorExtensions>
     <xilinx:coreExtensions>
       <xilinx:displayName>fasec_hwtest</xilinx:displayName>
-      <xilinx:coreRevision>27</xilinx:coreRevision>
+      <xilinx:coreRevision>29</xilinx:coreRevision>
       <xilinx:tags>
         <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:1.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
         <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:2.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
@@ -1553,6 +1553,7 @@
         <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.0.1_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
         <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.1.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
         <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.2.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
+        <xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.2.1_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
       </xilinx:tags>
       <xilinx:configElementInfos>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valueSource="user"/>
@@ -1590,8 +1591,8 @@
       <xilinx:xilinxVersion>2016.2</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="92ed6682"/>
       <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="6bf44be4"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="13b43890"/>
-      <xilinx:checksum xilinx:scope="ports" xilinx:value="5b0e6141"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f5301c99"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="fe85f838"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="455aa684"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="f383f867"/>
     </xilinx:packagingInfo>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
similarity index 94%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
index 55c96e87d38820a900247767cf454795764dcb4d..18a82b67dadaacd58f989d82600c483a1da3002a 100755
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
@@ -6,7 +6,7 @@
 -- Author     : Pieter Van Trappen  <pvantrap@cern.ch>
 -- Company    : CERN
 -- Created    : 2016-11-22
--- Last update: 2017-04-12
+-- Last update: 2017-05-11
 -- Platform   : 
 -- Standard   : VHDL'93/02
 -------------------------------------------------------------------------------
@@ -112,6 +112,7 @@ architecture rtl of general_fmc is
   type t_cmplengths is array (0 to c_COMP-1) of std_logic_vector(c_COUNTERWIDTH-1 downto 0);
   signal s_cmp_lengths   : t_cmplengths;
   signal s_diffouts_o    : std_logic_vector(c_DOUTS-1 downto 0);
+  signal s_outleds	: std_logic_vector(c_DOUTS-1 downto 0);
   signal s_outsfeedbak_i : std_logic_vector(c_OUTFBD-1 downto 0);
   signal s_spi_sclk      : std_logic;
   signal s_spi_mosi      : std_logic;
@@ -201,6 +202,7 @@ begin
   -- outputs loop
   fmc_03287_obufds : for I in 0 to c_DOUTS-1 generate
     gen_outs : if g_FMC = "EDA-03287" generate
+      -- output LVDS buffers
       cmp_OBUFDS_fmc : OBUFDS
         generic map (
 --          IOSTANDARD => "LVDS_25",      -- Specify the output I/O standard
@@ -209,6 +211,24 @@ begin
           O  => FMC_LA_P_b(c_COMP+I),  -- Diff_p output (connect directly to top-level port)
           OB => FMC_LA_N_b(c_COMP+I),  -- Diff_n output (connect directly to top-level port)
           I  => s_diffouts_o(I));       -- Buffer input
+      -- pulse extenders for LEDs
+      cmp_outs_pulseMeasure : pulseMeasure
+        generic map (
+          g_COUNTERWIDTH    => c_COUNTERWIDTH,
+          g_LEDCOUNTERWIDTH => c_LEDCOUNTERWIDTH,
+          g_LEDWAIT         => 10000000,  -- 100ms when 10ns clock
+          g_MISSINGCDC      => false)
+        port map (
+          clk_dsp_i       => clk_i,     -- for now no clock domain crossing
+          reset_n_i       => s_reset_n,
+          pulse_i         => s_diffouts_o(I),
+          missingWindow_i => to_unsigned(0, c_LEDCOUNTERWIDTH),
+          pulse_o         => open,
+          edgeDetected_o  => open,
+          usrLed_o        => s_outleds(I),
+          window_o        => open,
+          pulseLength_o   => open,
+          LedCount_o      => open);
     end generate gen_outs;
   end generate fmc_03287_obufds;
   -- SPI DAC for comparator reference
@@ -270,6 +290,7 @@ begin
     variable v_cmpled : std_logic_vector(c_COMP-1 downto 0);
     variable v_dout   : std_logic_vector(c_DOUTS-1 downto 0);
     variable v_fbd    : std_logic_vector(c_OUTFBD-1 downto 0);
+    variable v_outleds : std_logic_vector(c_DOUTS-1 downto 0);
   begin
     if g_FMC = "EDA-03287" and rising_edge(clk_i) then
       -- in/outputs
@@ -284,7 +305,7 @@ begin
       else
         intr_o <= '0';
       end if;
-      if (v_cmpled /= s_compleds) then
+      if (v_cmpled /= s_compleds) or (v_outleds /= s_outleds) then
         intr_led_o <= '1';
       else
         intr_led_o <= '0';
@@ -292,6 +313,7 @@ begin
       -- clocking in data for above interrupt generation
       v_cmpled := s_compleds(c_COMP-1 downto 0);
       v_cmp    := s_cmp_pulse(c_COMP-1 downto 0);
+      v_outleds := s_outleds(c_DOUTS-1 downto 0);
     end if;
   end process p_fmc_03287_io;
   -- no additional clocking of comparators & LEDs
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
similarity index 99%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
index dc24f53a63c1e7b466c04df6c1a3d08dfe0e1b9b..ee33a82527ff3d43c4207855f0a61fb8cc1f01ef 100755
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
@@ -294,8 +294,8 @@ begin
   s_data(c_FASEC_BASE+1) <= resize(unsigned(s_ins), g_S00_AXI_DATA_WIDTH);
   s_data(c_FASEC_BASE+2) <= resize(unsigned(gem_status_vector_i), g_S00_AXI_DATA_WIDTH);
   -- s_data(c_FASEC_BASE+3).data used in p_fasec_dio
-  s_data(c_FASEC_BASE+6) <= x"58EF3049";  -- tcl-script will put unix build time
-  s_data(c_FASEC_BASE+7) <= x"fbf1ca09";  -- tcl-script will put git commit id
+  s_data(c_FASEC_BASE+6) <= x"DEADBEE1";  -- tcl-script will put unix build time
+  s_data(c_FASEC_BASE+7) <= x"DEADBEE2";  -- tcl-script will put git commit id
   -- copy in rw data, 'for generate' only possible with constants!
   gen_data_readwrite : for i in 0 to c_MEMMAX-1 generate
     gen_fasec : if c_FASECMEM(i).ro = '0' generate
@@ -452,4 +452,3 @@ begin
       S_AXI_RVALID  => s00_axi_rvalid,
       S_AXI_RREADY  => s00_axi_rready);
 end rtl;
-
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd b/FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd
similarity index 100%
rename from FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd
rename to FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
index 189c4dae380c8e51fc3283cc094bd6fc7a9a1853..1874e298e995cfbbc357796ac439e92a7bdaf04d 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
@@ -704,15 +704,6 @@
           <spirit:configurableElementValue spirit:referenceId="appcore">xilinx.com:ip:axi_interconnect:2.1</spirit:configurableElementValue>
         </spirit:configurableElementValues>
       </spirit:componentInstance>
-      <spirit:componentInstance>
-        <spirit:instanceName>fasec_hwtest_0</spirit:instanceName>
-        <spirit:componentRef spirit:library="user" spirit:name="fasec_hwtest" spirit:vendor="user.org" spirit:version="3.2.0"/>
-        <spirit:configurableElementValues>
-          <spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_fasec_hwtest_0_0</spirit:configurableElementValue>
-          <spirit:configurableElementValue spirit:referenceId="g_FMC1">EDA-03287</spirit:configurableElementValue>
-          <spirit:configurableElementValue spirit:referenceId="g_FMC2">EDA-03287</spirit:configurableElementValue>
-        </spirit:configurableElementValues>
-      </spirit:componentInstance>
       <spirit:componentInstance>
         <spirit:instanceName>axi_wb_i2c_master_0</spirit:instanceName>
         <spirit:componentRef spirit:library="ip" spirit:name="axi_wb_i2c_master" spirit:vendor="cern.ch" spirit:version="3.1.1"/>
@@ -734,6 +725,15 @@
           <spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_wrc_1p_kintex7_0_0</spirit:configurableElementValue>
         </spirit:configurableElementValues>
       </spirit:componentInstance>
+      <spirit:componentInstance>
+        <spirit:instanceName>fasec_hwtest_0</spirit:instanceName>
+        <spirit:componentRef spirit:library="user" spirit:name="fasec_hwtest" spirit:vendor="user.org" spirit:version="3.2.1"/>
+        <spirit:configurableElementValues>
+          <spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_fasec_hwtest_0_0</spirit:configurableElementValue>
+          <spirit:configurableElementValue spirit:referenceId="g_FMC1">EDA-03287</spirit:configurableElementValue>
+          <spirit:configurableElementValue spirit:referenceId="g_FMC2">EDA-03287</spirit:configurableElementValue>
+        </spirit:configurableElementValues>
+      </spirit:componentInstance>
     </spirit:componentInstances>
     <spirit:interconnections>
       <spirit:interconnection>
@@ -811,8 +811,8 @@
       <spirit:adHocConnection>
         <spirit:name>pb_gp_i_1</spirit:name>
         <spirit:externalPortReference spirit:portRef="pb_gp_i"/>
-        <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="pb_gp_n_i"/>
         <spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="button_rst_n_i"/>
+        <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="pb_gp_n_i"/>
       </spirit:adHocConnection>
       <spirit:adHocConnection>
         <spirit:name>fasec_hwtest_0_led_col_pl_o</spirit:name>
@@ -843,8 +843,8 @@
         <spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="m_axi_s2mm_aclk"/>
         <spirit:internalPortReference spirit:componentRef="xadc_wiz_0" spirit:portRef="s_axis_aclk"/>
         <spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="s_axi_aclk"/>
-        <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="ps_clk_i"/>
-        <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aclk"/>
+        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aclk"/>
+        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aclk"/>
         <spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="ACLK"/>
         <spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="ACLK"/>
         <spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M06_ACLK"/>
@@ -858,8 +858,8 @@
         <spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="S00_ACLK"/>
         <spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="M00_ACLK"/>
         <spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M07_ACLK"/>
-        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aclk"/>
-        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aclk"/>
+        <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="ps_clk_i"/>
+        <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aclk"/>
       </spirit:adHocConnection>
       <spirit:adHocConnection>
         <spirit:name>processing_system7_0_FCLK_RESET0_N</spirit:name>
@@ -875,7 +875,8 @@
         <spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="axi_resetn"/>
         <spirit:internalPortReference spirit:componentRef="xadc_axis_fifo_adapter_0" spirit:portRef="AXIS_RESET_N"/>
         <spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="s_axi_aresetn"/>
-        <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aresetn"/>
         <spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="S00_ARESETN"/>
         <spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M06_ARESETN"/>
         <spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M05_ARESETN"/>
@@ -888,8 +889,7 @@
         <spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="ARESETN"/>
         <spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="S00_ARESETN"/>
         <spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M07_ARESETN"/>
-        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aresetn"/>
-        <spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aresetn"/>
       </spirit:adHocConnection>
       <spirit:adHocConnection>
         <spirit:name>Net</spirit:name>
@@ -1134,9 +1134,9 @@
       <spirit:adHocConnection>
         <spirit:name>rst_wrc_1p_kintex7_0_62M_peripheral_aresetn</spirit:name>
         <spirit:internalPortReference spirit:componentRef="rst_wrc_1p_kintex7_0_62M" spirit:portRef="peripheral_aresetn"/>
+        <spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="s00_axi_aresetn"/>
         <spirit:internalPortReference spirit:componentRef="axi_interconnect_1" spirit:portRef="M00_ARESETN"/>
         <spirit:internalPortReference spirit:componentRef="axi_interconnect_1" spirit:portRef="S00_ARESETN"/>
-        <spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="s00_axi_aresetn"/>
       </spirit:adHocConnection>
       <spirit:adHocConnection>
         <spirit:name>rst_wrc_1p_kintex7_0_62M_interconnect_aresetn</spirit:name>
@@ -4992,12 +4992,6 @@
             <spirit:addressOffset>0x40400000</spirit:addressOffset>
             <spirit:range>64K</spirit:range>
           </spirit:segment>
-          <spirit:segment>
-            <spirit:name>SEG_fasec_hwtest_0_S00_AXI_reg</spirit:name>
-            <spirit:displayName>/fasec_hwtest_0/S00_AXI/S00_AXI_reg</spirit:displayName>
-            <spirit:addressOffset>0x43C30000</spirit:addressOffset>
-            <spirit:range>64K</spirit:range>
-          </spirit:segment>
           <spirit:segment>
             <spirit:name>SEG_axi_wb_i2c_master_0_Reg</spirit:name>
             <spirit:displayName>/axi_wb_i2c_master_0/s00_axi/Reg</spirit:displayName>
@@ -5016,6 +5010,12 @@
             <spirit:addressOffset>0x80000000</spirit:addressOffset>
             <spirit:range>64K</spirit:range>
           </spirit:segment>
+          <spirit:segment>
+            <spirit:name>SEG_fasec_hwtest_0_S00_AXI_reg</spirit:name>
+            <spirit:displayName>/fasec_hwtest_0/S00_AXI/S00_AXI_reg</spirit:displayName>
+            <spirit:addressOffset>0x43C30000</spirit:addressOffset>
+            <spirit:range>64K</spirit:range>
+          </spirit:segment>
         </spirit:segments>
       </spirit:addressSpace>
     </spirit:addressSpaces>
diff --git a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
index 31e08d77f9d4a20368a66ec25a816ff0cc34473a..fb5ab3078c1a2b07f11e800e6637064000b0ff8e 100644
--- a/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
+++ b/FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
@@ -2,9 +2,9 @@
 <Root MajorVersion="0" MinorVersion="33">
   <CompositeFile CompositeFileTopName="system_design" CanBeSetAsTop="true" CanDisplayChildGraph="true">
     <Description>Composite Fileset</Description>
-    <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1492070306"/>
-    <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1492070306"/>
-    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1492070306"/>
+    <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1494514392"/>
+    <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1494514392"/>
+    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1494514392"/>
     <FileCollection Name="SOURCES" Type="SOURCES">
       <File Name="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci" Type="IP">
         <Instance HierarchyPath="processing_system7_0"/>
@@ -23,7 +23,6 @@
         <UsedIn Val="SIMULATION"/>
       </File>
       <File Name="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci" Type="IP">
-        <Instance HierarchyPath="processing_system7_0_axi_periph"/>
         <Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
         <Library Name="xil_defaultlib"/>
         <UsedIn Val="SYNTHESIS"/>
@@ -79,7 +78,6 @@
         <UsedIn Val="SIMULATION"/>
       </File>
       <File Name="ip/system_design_axi_interconnect_0_0/system_design_axi_interconnect_0_0.xci" Type="IP">
-        <Instance HierarchyPath="axi_interconnect_0"/>
         <Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
         <Library Name="xil_defaultlib"/>
         <UsedIn Val="SYNTHESIS"/>
@@ -143,13 +141,18 @@
         <UsedIn Val="SIMULATION"/>
       </File>
       <File Name="ip/system_design_axi_interconnect_1_0/system_design_axi_interconnect_1_0.xci" Type="IP">
-        <Instance HierarchyPath="axi_interconnect_1"/>
         <Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
         <Library Name="xil_defaultlib"/>
         <UsedIn Val="SYNTHESIS"/>
         <UsedIn Val="IMPLEMENTATION"/>
         <UsedIn Val="SIMULATION"/>
       </File>
+      <File Name="hdl/system_design.vhd" Type="VHDL">
+        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="SIMULATION"/>
+      </File>
       <File Name="ip/system_design_auto_pc_0/system_design_auto_pc_0.xci" Type="IP">
         <Instance HierarchyPath="axi_interconnect_0/s00_couplers/auto_pc"/>
         <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
@@ -174,12 +177,6 @@
         <UsedIn Val="IMPLEMENTATION"/>
         <UsedIn Val="SIMULATION"/>
       </File>
-      <File Name="hdl/system_design.vhd" Type="VHDL">
-        <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
-        <Library Name="xil_defaultlib"/>
-        <UsedIn Val="SYNTHESIS"/>
-        <UsedIn Val="SIMULATION"/>
-      </File>
       <File Name="system_design_ooc.xdc" Type="XDC">
         <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
         <Library Name="xil_defaultlib"/>
diff --git a/FASEC_prototype.xpr b/FASEC_prototype.xpr
index f671f0edd41b1062687a8792be8e3159e096cdca..dc9616f06b79bd3792b7b938f1ff0bb7366301d8 100644
--- a/FASEC_prototype.xpr
+++ b/FASEC_prototype.xpr
@@ -10,12 +10,12 @@
     <Option Name="Part" Val="xc7z030ffg676-2"/>
     <Option Name="CompiledLibDir" Val="$PPRDIR/../../../../../../local/EDA/xilinx_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
-    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
-    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
-    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
-    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
-    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
-    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="CompiledLibDirModelSim" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirVCS" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/activehdl"/>
     <Option Name="TargetLanguage" Val="VHDL"/>
     <Option Name="BoardPart" Val=""/>
     <Option Name="ActiveSimSet" Val="sim_1"/>
@@ -36,13 +36,13 @@
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="76"/>
-    <Option Name="WTModelSimExportSim" Val="76"/>
-    <Option Name="WTQuestaExportSim" Val="76"/>
-    <Option Name="WTIesExportSim" Val="76"/>
-    <Option Name="WTVcsExportSim" Val="76"/>
-    <Option Name="WTRivieraExportSim" Val="76"/>
-    <Option Name="WTActivehdlExportSim" Val="76"/>
+    <Option Name="WTXSimExportSim" Val="77"/>
+    <Option Name="WTModelSimExportSim" Val="77"/>
+    <Option Name="WTQuestaExportSim" Val="77"/>
+    <Option Name="WTIesExportSim" Val="77"/>
+    <Option Name="WTVcsExportSim" Val="77"/>
+    <Option Name="WTRivieraExportSim" Val="77"/>
+    <Option Name="WTActivehdlExportSim" Val="77"/>
   </Configuration>
   <FileSets Version="1" Minor="31">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
@@ -53,6 +53,25 @@
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_6_0/system_design_xlconstant_6_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_0_0/system_design_axi_interconnect_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xbar_0/system_design_xbar_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.vhd"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_1_0/system_design_axi_interconnect_1_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_wrc_1p_kintex7_0_62M_0/system_design_rst_wrc_1p_kintex7_0_62M_0.xci"/>
+        <CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci"/>
       </File>
       <File Path="$PSRCDIR/sources_1/bd/system_design/hdl/system_design_wrapper.vhd">
         <FileInfo>
diff --git a/ip_upgrade.log b/ip_upgrade.log
index 76f8af17bc63aa7f3d7de8fb803837a924c10746..383a9670adaa03e10a771ecc4a04af4072d814ae 100644
--- a/ip_upgrade.log
+++ b/ip_upgrade.log
@@ -1,3 +1,24 @@
+Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016
+| Date         : Thu May 11 16:52:53 2017
+| Host         : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
+| Command      : upgrade_ip
+| Device       : xc7z030ffg676-2
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_design_fasec_hwtest_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.2.0 (Rev. 27) to user.org:user:fasec_hwtest:3.2.1 (Rev. 29)
+
+
+
+
+
+
 Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
 ------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun  2 16:32:35 MDT 2016