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Euro ADC 65M 14b 40cha gw PUMA-gw
Commit c094ee8a authored by Dave Newbold's avatar Dave Newbold
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Adding nzs_blks register; update to v22

parent d5f7a475
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Showing with 31 additions and 13 deletions
components/solid/addr_table/sc_timing.xml
View file @ c094ee8a
......@@ -13,6 +13,7 @@
<node id="chan_cap" mask="0x4000"/>
<node id="chan_inc" mask="0x8000"/>
<node id="zs_blks" mask="0xff0000"/>
<node id="nzs_blks" mask="0xf000000"/>
</node>
<node id="stat" address="0x8">
<node id="wait_sync" mask="0x1"/>
......
components/solid/firmware/hdl/sc_chan.vhd
View file @ c094ee8a
......@@ -36,7 +36,8 @@ entity sc_chan is
sync_ctrl: in std_logic_vector(3 downto 0);
zs_sel: in std_logic_vector(1 downto 0);
sctr: in std_logic_vector(47 downto 0);
fake: in std_logic_vector(13 downto 0);
fake: in std_logic_vector(13 downto 0);
nzs_blks: in std_logic_vector(3 downto 0);
nzs_en: in std_logic;
zs_en: in std_logic;
keep: in std_logic;
......@@ -214,6 +215,7 @@ begin
ipb_in => ipbw(N_SLV_BUF),
ipb_out => ipbr(N_SLV_BUF),
mode => ctrl_mode,
nzs_blks => nzs_blks,
clk40 => clk40,
clk160 => clk160,
buf_rst => rst40,
......
components/solid/firmware/hdl/sc_chan_buf.vhd
View file @ c094ee8a
......@@ -22,6 +22,7 @@ entity sc_chan_buf is
ipb_in: in ipb_wbus; -- clk dom
ipb_out: out ipb_rbus; -- clk dom
mode: in std_logic; -- buffer counter mode; clk dom
nzs_blks: in std_logic_vector(3 downto 0); -- number of blocks in NZS buffer
clk40: in std_logic;
clk160: in std_logic;
buf_rst: in std_logic; -- general reset; clk40 dom
......@@ -51,7 +52,7 @@ architecture rtl of sc_chan_buf is
signal we: std_logic;
signal d_ram, q_ram, d_nzs, q_nzs, d_zs, q_zs, q_zs_b: std_logic_vector(15 downto 0);
signal a_ram: std_logic_vector(BUF_RADIX - 1 downto 0);
signal pnz, pzw, pzr: unsigned(BUF_RADIX - 1 downto 0);
signal pnz, pzw, pzr, zs_first_addr: unsigned(BUF_RADIX - 1 downto 0);
signal cap_run, cap_done: std_logic;
signal zctr: unsigned(BLK_RADIX - 1 downto 0);
signal z0, z1: std_logic;
......@@ -60,6 +61,8 @@ architecture rtl of sc_chan_buf is
begin
zs_first_addr <= shift_left(unsigned((BUF_RADIX - 1 downto 4 => '0') & nzs_blks), BLK_RADIX) + ZS_DEL;
-- NZS / ZS buffer
ram: entity work.ipbus_ported_dpram
......@@ -124,7 +127,7 @@ begin
if (mode = '1' and nzen = '0') or (mode = '0' and nzen_d = '0') then
pnz <= (others => '0');
else
if (mode = '0' and pnz = ZS_FIRST_ADDR - 1) or pnz = ZS_LAST_ADDR then
if (mode = '0' and pnz = zs_first_addr - 1) or pnz = ZS_LAST_ADDR then
pnz <= (others => '0');
else
pnz <= pnz + 1;
......@@ -171,19 +174,19 @@ begin
begin
if rising_edge(clk40) then
if zs_en = '0' then
pzw <= to_unsigned(ZS_FIRST_ADDR, pzw'length);
pzr <= to_unsigned(ZS_FIRST_ADDR, pzr'length);
pzw <= zs_first_addr;
pzr <= zs_first_addr;
elsif buf_full_i = '0' then
if wez = '1' then
if pzw = ZS_LAST_ADDR then
pzw <= to_unsigned(ZS_FIRST_ADDR, pzw'length);
pzw <= zs_first_addr;
else
pzw <= pzw + 1;
end if;
end if;
if rez = '1' then
if pzr = ZS_LAST_ADDR then
pzr <= to_unsigned(ZS_FIRST_ADDR, pzr'length);
pzr <= zs_first_addr;
else
pzr <= pzr + 1;
end if;
......
components/solid/firmware/hdl/sc_channels.vhd
View file @ c094ee8a
......@@ -33,6 +33,7 @@ entity sc_channels is
zs_sel: in std_logic_vector(1 downto 0);
sctr: in std_logic_vector(47 downto 0);
fake: in std_logic_vector(13 downto 0);
nzs_blks: in std_logic_vector(3 downto 0);
nzs_en: in std_logic;
zs_en: in std_logic;
keep: in std_logic_vector(N_CHAN - 1 downto 0);
......@@ -109,6 +110,7 @@ begin
zs_sel => zs_sel,
sctr => sctr,
fake => fake,
nzs_blks => nzs_blks,
nzs_en => nzs_en,
zs_en => zs_en,
keep => keep(i),
......
components/solid/firmware/hdl/sc_daq.vhd
View file @ c094ee8a
......@@ -51,6 +51,7 @@ architecture rtl of sc_daq is
signal trig_keep, trig_flush, trig_veto: std_logic_vector(N_CHAN - 1 downto 0);
signal fake: std_logic_vector(13 downto 0);
signal force_trig, thresh_hit: std_logic;
signal nzs_blks: std_logic_vector(3 downto 0);
signal zs_sel: std_logic_vector(1 downto 0);
signal chan_trig: sc_trig_array;
signal link_d, link_q: std_logic_vector(15 downto 0);
......@@ -101,7 +102,8 @@ begin
trig_en => trig_en,
nzs_en => nzs_en,
zs_en => zs_en,
rand => rand
rand => rand,
nzs_blks => nzs_blks
);
clk40 <= clk40_i;
......@@ -155,6 +157,7 @@ begin
zs_sel => zs_sel,
sctr => sctr,
fake => fake,
nzs_blks => nzs_blks,
nzs_en => nzs_en,
zs_en => zs_en,
keep => trig_keep,
......
components/solid/firmware/hdl/sc_timing.vhd
View file @ c094ee8a
......@@ -36,7 +36,8 @@ entity sc_timing is
trig_en: out std_logic;
nzs_en: out std_logic;
zs_en: out std_logic;
rand: out std_logic_vector(31 downto 0)
rand: out std_logic_vector(31 downto 0);
nzs_blks: out std_logic_vector(3 downto 0)
);
end sc_timing;
......@@ -51,6 +52,7 @@ architecture rtl of sc_timing is
signal ctrl_rst_ctr, ctrl_cap_ctr, ctrl_en_sync, ctrl_force_sync, ctrl_pipeline_en, ctrl_send_sync: std_logic;
signal ctrl_chan_slip_l, ctrl_chan_slip_h, ctrl_chan_rst_buf, ctrl_chan_cap, ctrl_chan_inc: std_logic;
signal ctrl_zs_blks: std_logic_vector(7 downto 0);
signal ctrl_nzs_blks: std_logic_vector(3 downto 0);
signal sync, wait_sync, sync_err, io_err: std_logic;
signal sync_in_r, trig_in_r, trig_in_r_d: std_logic;
signal sync_ctr, trig_ctr: unsigned(31 downto 0);
......@@ -111,6 +113,7 @@ begin
ctrl_chan_cap <= ctrl(0)(14);
ctrl_chan_inc <= ctrl(0)(15);
ctrl_zs_blks <= ctrl(0)(23 downto 16);
ctrl_nzs_blks <= ctrl(0)(27 downto 24);
stat(0) <= X"0000000" & "00" & sync_err & wait_sync;
stat(1) <= std_logic_vector(sctr_s(31 downto 0));
stat(2) <= X"0000" & std_logic_vector(sctr_s(47 downto 32));
......@@ -195,12 +198,15 @@ begin
rst40 => rst40_i,
en => ctrl_pipeline_en,
zs_blks => ctrl_zs_blks,
nzs_blks => ctrl_nzs_blks,
sync => sync,
sctr => sctr_i,
nzs_en => nzs_en,
zs_en => zs_en,
trig_en => trig_en
);
nzs_blks <= ctrl_nzs_blks;
-- Channel sync control
......
components/solid/firmware/hdl/sc_timing_startup.vhd
View file @ c094ee8a
......@@ -17,6 +17,7 @@ entity sc_timing_startup is
rst40: in std_logic;
en: in std_logic;
zs_blks: in std_logic_vector(7 downto 0);
nzs_blks: in std_logic_vector(3 downto 0);
sync: in std_logic;
sctr: in unsigned(47 downto 0);
nzs_en: out std_logic;
......@@ -47,9 +48,9 @@ begin
if up = '1' then
if and_reduce(std_logic_vector(sctr(BLK_RADIX - 1 downto 0))) = '1' then
nzs_en <= '1';
elsif unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = NZS_BLKS + 1 and sctr(BLK_RADIX - 1 downto 0) = to_unsigned(ZS_DEL - 1, BLK_RADIX) then
elsif unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = unsigned(nzs_blks) + 1 and sctr(BLK_RADIX - 1 downto 0) = to_unsigned(ZS_DEL - 1, BLK_RADIX) then
zs_en <= '1';
elsif unsigned(sctr(7 + BLK_RADIX downto BLK_RADIX)) = NZS_BLKS + 1 + unsigned(zs_blks) then
elsif unsigned(sctr(7 + BLK_RADIX downto BLK_RADIX)) = unsigned(nzs_blks) + 1 + unsigned(zs_blks) then
trig_en <= '1';
end if;
end if;
......
projects/64ch/firmware/hdl/top_decl.vhd
View file @ c094ee8a
......@@ -11,7 +11,7 @@ package top_decl is
constant MAC_ADDR: std_logic_vector(47 downto 0) := X"020ddba11500"; -- last byte from local addr
constant IP_ADDR: std_logic_vector(31 downto 0) := X"c0a8eb00"; -- last byte from local addr
constant FW_REV: std_logic_vector(15 downto 0) := X"0015";
constant FW_REV: std_logic_vector(15 downto 0) := X"0016";
constant N_CHAN: integer := 64;
constant BLK_RADIX: integer := 8; -- 256 sample blocks
......
projects/8ch/firmware/hdl/top_decl.vhd
View file @ c094ee8a
......@@ -11,7 +11,7 @@ package top_decl is
constant MAC_ADDR: std_logic_vector(47 downto 0) := X"020ddba11503";
constant IP_ADDR: std_logic_vector(31 downto 0) := X"c0a8eb00";
constant FW_REV: std_logic_vector(15 downto 0) := X"0015";
constant FW_REV: std_logic_vector(15 downto 0) := X"0016";
constant N_CHAN: integer := 8;
constant BLK_RADIX: integer := 8; -- 256 sample blocks
......
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