Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
E
Euro ADC 65M 14b 40cha gw PUMA-gw
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Euro ADC 65M 14b 40cha gw PUMA-gw
Commits
7ad2ad9c
Commit
7ad2ad9c
authored
May 01, 2018
by
Dave Newbold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Adding kack, removing veto
parent
7265401b
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
1 addition
and
1 deletion
+1
-1
sc_trig.vhd
components/solid/firmware/hdl/sc_trig.vhd
+1
-1
No files found.
components/solid/firmware/hdl/sc_trig.vhd
View file @
7ad2ad9c
...
...
@@ -63,7 +63,7 @@ architecture rtl of sc_trig is
signal
lq
:
std_logic_vector
(
15
downto
0
);
signal
rveto
,
lvalid
,
lack
,
mark
,
err
:
std_logic
;
signal
zs_cfg
:
std_logic_vector
(
31
downto
0
);
signal
veto_p
,
veto_i
,
keep_i
,
flush_i
:
std_logic_vector
(
N_CHAN
-
1
downto
0
)
;
signal
keep_i
,
flush_i
:
std_logic
;
signal
b_q
,
t_q
:
std_logic_vector
(
31
downto
0
);
signal
b_go
,
t_go
,
b_valid
,
t_valid
,
b_blkend
,
t_blkend
,
blkend
:
std_logic
;
signal
tctr
:
std_logic_vector
(
27
downto
0
);
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment