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Euro ADC 65M 14b 40cha gw PUMA-gw
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Euro ADC 65M 14b 40cha gw PUMA-gw
Commits
72805f35
Commit
72805f35
authored
May 01, 2018
by
Dave Newbold
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Fix in sequencer for back-to-back triggers
parent
3ab113d8
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2 changed files
with
6 additions
and
6 deletions
+6
-6
sc_chan.vhd
components/solid/firmware/hdl/sc_chan.vhd
+1
-2
sc_seq.vhd
components/solid/firmware/hdl/sc_seq.vhd
+5
-4
No files found.
components/solid/firmware/hdl/sc_chan.vhd
View file @
72805f35
...
...
@@ -73,8 +73,7 @@ architecture rtl of sc_chan is
signal
zs_thresh
:
std_logic_vector
(
13
downto
0
);
signal
sctr_p
:
std_logic_vector
(
11
downto
0
);
signal
dr_d
:
std_logic_vector
(
31
downto
0
);
signal
ro_en
,
keep_i
,
flush_i
,
err_i
,
req
,
blkend
,
dr_blkend
,
dr_wen
:
std_logic
;
signal
ctrl_tt
:
std_logic
;
signal
ro_en
,
keep_i
,
flush_i
,
err_i
,
blkend
,
dr_blkend
,
dr_wen
:
std_logic
;
begin
...
...
components/solid/firmware/hdl/sc_seq.vhd
View file @
72805f35
...
...
@@ -47,7 +47,7 @@ architecture rtl of sc_seq is
signal
ipbw
:
ipb_wbus_array
(
N_SLAVES
-
1
downto
0
);
signal
ipbr
:
ipb_rbus_array
(
N_SLAVES
-
1
downto
0
);
signal
td
:
std_logic_vector
(
15
downto
0
);
signal
tv
,
terr
:
std_logic
;
signal
tv
,
terr
,
tv_d
:
std_logic
;
signal
we
:
std_logic
;
signal
d_ram
,
q_ram
:
std_logic_vector
(
15
downto
0
);
signal
a_ram
:
std_logic_vector
(
BUF_RADIX
-
1
downto
0
);
...
...
@@ -80,8 +80,9 @@ begin
td
<=
d_loc
when
valid_loc
=
'1'
else
d_ext
;
tv
<=
(
valid_loc
or
valid_ext
)
and
not
rseq
and
zs_en
;
ack_loc
<=
valid_loc
;
ack_ext
<=
valid_ext
and
not
valid_loc
;
tv_d
<=
tv
when
rising_edge
(
clk40
);
ack_loc
<=
valid_loc
and
tv_d
;
ack_ext
<=
valid_ext
and
not
valid_loc
and
tv_d
;
process
(
clk40
)
begin
...
...
@@ -166,7 +167,7 @@ begin
addr
=>
a_ram
);
we
<=
'1'
when
(
tv
=
'1'
and
unsigned
(
d_ram
)
>
unsigned
(
q_ram
))
or
(
rseq
=
'1'
and
sctr
(
1
downto
0
)
=
"11"
)
else
'0'
;
we
<=
'1'
when
(
tv
_d
=
'1'
and
unsigned
(
d_ram
)
>
unsigned
(
q_ram
))
or
(
rseq
=
'1'
and
sctr
(
1
downto
0
)
=
"11"
)
else
'0'
;
a_ram
<=
std_logic_vector
(
ptr
+
unsigned
(
q_s_ram
(
BUF_RADIX
-
1
downto
0
)))
when
rseq
=
'0'
else
std_logic_vector
(
ptr
);
d_ram
<=
q_s_ram
(
31
downto
16
)
when
rseq
=
'0'
else
(
others
=>
'0'
);
...
...
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