Introduction
Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet. A software library is provided that permits any computer with an Ethernet card to easily communicate with remote cores on the Etherbone network. The Etherbone core implements a wishbone master and a wishbone slave bus controller. With this scheme, any number of Etherbone FPGA-cores and application software tasks can be connected together to implement hybrid distributed networks of arbitrary complexity such as field-buses, timing systems, or testbeds for hardware debugging. Etherbone provides basic read, write and addressing functions. Etherbone data transfers are initiated either by FPGA cores connected to the Etherbone wishbone buses or by application software via the library. It is within in these Etherbone Accessible Devices (EAD) that specific cores may implement other levels of abstraction on top of Etherbone as required. More information is available in the Document document.
Work so far
Date | Event |
19-08-2010 | Project start. |
11-10-2010 | First functional spec draft released for comments. |
Outlook
The target date for a first implementation is March 2011. The functional spec should be approved at the end of October 2010 and the technical spec should be ready by December 2010.