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E
EtherBone Core
Commit 67819d32 authored by Michael Reese's avatar Michael Reese
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eb_sim_core: fix a few issues. eb-ls works

parent d010c791
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Showing with 90 additions and 116 deletions
hdl/eb_sim_core/simbridge.vhd
View file @ 67819d32
......@@ -2,10 +2,12 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.file_access.all;
use work.simbridge_pkg.all;
entity simbridge is
generic (
g_sdb_address : t_wishbone_address
);
port (
clk_i : in std_logic;
rstn_i : in std_logic;
......@@ -21,6 +23,7 @@ begin
variable master_o_dat,master_o_adr,master_o_sel : integer;
variable master_i_ack,master_i_err,master_i_rty,master_i_stall : std_logic;
variable master_i_dat : integer;
constant stop_until_connected : integer := 1;
begin
master_o.cyc <= '0';
master_o.stb <= '0';
......@@ -31,11 +34,11 @@ begin
wait until rising_edge(rstn_i);
wait until rising_edge(clk_i);
eb_slave_init(true);
eb_simbridge_init(stop_until_connected, to_integer(signed(g_sdb_address)));
while true loop
wait until rising_edge(clk_i);
eb_slave_control_out(master_o_cyc,master_o_stb,master_o_we,master_o_adr,master_o_dat,master_o_sel);
eb_simbridge_control_out(master_o_cyc,master_o_stb,master_o_we,master_o_adr,master_o_dat,master_o_sel);
master_o.cyc <= master_o_cyc;
master_o.stb <= master_o_stb;
master_o.we <= master_o_we;
......@@ -49,9 +52,9 @@ begin
master_i_rty := master_i.rty;
master_i_stall := master_i.stall;
master_i_dat := to_integer(signed(master_i.dat));
eb_slave_control_in(master_i_ack,master_i_err,master_i_rty,master_i_stall,master_i_dat);
eb_simbridge_control_in(master_i_ack,master_i_err,master_i_rty,master_i_stall,master_i_dat);
end loop;
end process;
end architecture;
\ No newline at end of file
end architecture;
hdl/eb_sim_core/simbridge_pkg.vhd
View file @ 67819d32
......@@ -20,30 +20,30 @@ package simbridge_pkg is
--eb_slave_control(master_o_cyc,master_o_stb,master_o_we,master_o_adr,master_o_dat,
-- master_i_ack,master_i_err,master_i_rty,master_i_stall_master_i_dat);
procedure eb_slave_init(stop_unitl_connected : in boolean);
attribute foreign of eb_slave_init: procedure is "VHPIDIRECT eb_slave_init";
procedure eb_simbridge_init(stop_unitl_connected : in integer; sdb_adr : in integer);
attribute foreign of eb_simbridge_init: procedure is "VHPIDIRECT eb_simbridge_init";
procedure eb_slave_control_out(cyc, stb, we : out std_logic; adr, dat , sel: out integer);
attribute foreign of eb_slave_control_out : procedure is "VHPIDIRECT eb_slave_control_out";
procedure eb_simbridge_control_out(cyc, stb, we : out std_logic; adr, dat , sel: out integer);
attribute foreign of eb_simbridge_control_out : procedure is "VHPIDIRECT eb_simbridge_control_out";
procedure eb_slave_control_in(ack, err, rty, stall : in std_logic; dat : in integer);
attribute foreign of eb_slave_control_in : procedure is "VHPIDIRECT eb_slave_control_in";
procedure eb_simbridge_control_in(ack, err, rty, stall : in std_logic; dat : in integer);
attribute foreign of eb_simbridge_control_in : procedure is "VHPIDIRECT eb_simbridge_control_in";
end package;
package body simbridge_pkg is
procedure eb_slave_init(stop_unitl_connected : in boolean) is
procedure eb_simbridge_init(stop_unitl_connected : in integer; sdb_adr : in integer) is
begin
assert false report "VHPI" severity failure;
end procedure;
procedure eb_slave_control_out(cyc, stb, we : out std_logic; adr, dat , sel: out integer) is
procedure eb_simbridge_control_out(cyc, stb, we : out std_logic; adr, dat , sel: out integer) is
begin
assert false report "VHPI" severity failure;
end procedure;
procedure eb_slave_control_in(ack, err, rty, stall : in std_logic; dat : in integer) is
procedure eb_simbridge_control_in(ack, err, rty, stall : in std_logic; dat : in integer) is
begin
assert false report "VHPI" severity failure;
end procedure;
......
hdl/eb_sim_core/simbridge_pkg_c.cpp
View file @ 67819d32
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