From f2a0dffb496db2e8bfb653976b7d6ff55c2e9d3b Mon Sep 17 00:00:00 2001
From: Mathias Kreider <m.kreider@gsi.de>
Date: Fri, 10 Feb 2012 12:26:40 +0000
Subject: [PATCH]
---
hdl/eb_testbench/EB_2_wb_converter.vhd | 45 +++++--
hdl/eb_testbench/EB_2_wb_converter.vhd.bak | 47 +++++--
hdl/eb_testbench/EB_CORE.vhd | 63 ++--------
hdl/eb_testbench/EB_CORE.vhd.bak | 54 +-------
hdl/eb_testbench/EB_RX_CTRL.vhd | 87 ++++++-------
hdl/eb_testbench/EB_RX_CTRL.vhd.bak | 87 ++++++-------
hdl/eb_testbench/EB_TX_CTRL.vhd | 1 -
hdl/eb_testbench/EB_TX_CTRL.vhd.bak | 2 +-
hdl/eb_testbench/eb_tb.cr.mti | 116 +++++++++---------
hdl/eb_testbench/eb_tb.mpf | 62 +++++-----
hdl/eb_testbench/main.sv | 2 +-
hdl/eb_testbench/main.sv.bak | 4 +-
hdl/eb_testbench/wb_binary_file_source.svh | 2 +-
.../wb_binary_file_source.svh.bak | 10 +-
14 files changed, 256 insertions(+), 326 deletions(-)
diff --git a/hdl/eb_testbench/EB_2_wb_converter.vhd b/hdl/eb_testbench/EB_2_wb_converter.vhd
index e34528a..73bba01 100644
--- a/hdl/eb_testbench/EB_2_wb_converter.vhd
+++ b/hdl/eb_testbench/EB_2_wb_converter.vhd
@@ -74,7 +74,9 @@ architecture behavioral of eb_2_wb_converter is
------------------------------------------------------------------------------------------
constant c_width_int : integer := 24;
type t_state_RX is (IDLE, EB_HDR_REC, EB_HDR_PROC, EB_HDR_PROBE_ID, CYC_HDR_REC, CYC_HDR_READ_PROC, CYC_HDR_READ_GET_ADR, WB_READ_RDY, WB_READ, CYC_HDR_WRITE_PROC, CYC_HDR_WRITE_GET_ADR, WB_WRITE_RDY, WB_WRITE, CYC_DONE, EB_DONE, ERROR);
-type t_state_TX is (IDLE, EB_HDR_INIT, EB_HDR_PROBE_ID, PACKET_HDR_SEND, EB_HDR_SEND, RDY, CYC_HDR_INIT, CYC_HDR_SEND, BASE_WRITE_ADR_SEND, DATA_SEND, ZERO_PAD_WRITE, ZERO_PAD_WAIT, ERROR);
+type t_state_TX is (IDLE, EB_HDR_INIT, EB_HDR_PROBE_ID, EB_HDR_PROBE_WAIT, PACKET_HDR_SEND, EB_HDR_SEND, RDY, CYC_HDR_INIT, CYC_HDR_SEND, BASE_WRITE_ADR_SEND, DATA_SEND, ZERO_PAD_WRITE, ZERO_PAD_WAIT, ERROR);
+
+
signal s_state_RX : t_state_RX := IDLE;
signal s_state_TX : t_state_TX := IDLE;
@@ -103,6 +105,7 @@ signal s_WB_ACK_cnt_big : unsigned(8 downto 0);
alias a_WB_ACK_cnt : unsigned(7 downto 0) is s_WB_ACK_cnt_big(7 downto 0);
alias a_WB_ACK_cnt_err : unsigned(0 downto 0) is s_WB_ACK_cnt_big(8 downto 8);
+signal s_EB_probe_wait_cnt : unsigned(3 downto 0);
signal s_EB_TX_zeropad_cnt : unsigned(7 downto 0);
signal s_EB_RX_byte_cnt : unsigned(15 downto 0);
signal s_EB_TX_byte_cnt : unsigned(15 downto 0);
@@ -261,6 +264,7 @@ s_WB_master_o.CYC <= s_WB_CYC;
s_WB_master_o.WE <= s_WB_WE;
EB_RX_o.STALL <= s_rx_fifo_am_full;
EB_RX_o.ACK <= s_EB_RX_ACK;
+EB_RX_o.ERR <= '0';
s_rx_fifo_we <= EB_RX_i.STB AND NOT (s_rx_fifo_am_full); -- OR s_packet_reception_complete);
@@ -346,6 +350,16 @@ begin
end if;
end if;
+ --Counter: Probewait
+ if(s_state_TX = EB_HDR_PROBE_ID) then
+ s_EB_probe_wait_cnt <= (others => '0');
+ else
+ if(s_state_TX = EB_HDR_PROBE_WAIT) then
+ s_EB_probe_wait_cnt <= s_EB_probe_wait_cnt +1;
+ end if;
+ end if;
+
+
end if;
end if;
end process;
@@ -399,13 +413,15 @@ begin
else
--eb hdr seems valid, prepare answering packet. Prefill RX buffer
if(unsigned(s_rx_fifo_gauge) > 3) then
- s_state_TX <= EB_HDR_INIT;
- if(s_EB_RX_HDR.PROBE = '0') then -- no probe, prepare cycle reception
- s_state_RX <= CYC_HDR_REC;
- else
- s_state_RX <= EB_HDR_PROBE_ID ;
- end if;
+ s_state_RX <= CYC_HDR_REC;
+ s_state_TX <= EB_HDR_INIT;
+ else
+ report "EB: Waiting for buffer ..." severity note;
end if;
+ if(s_EB_RX_HDR.PROBE = '1') then -- no probe, prepare cycle reception
+ s_state_RX <= EB_HDR_PROBE_ID ;
+ s_state_TX <= EB_HDR_INIT;
+ end if;
end if;
when EB_HDR_PROBE_ID => s_state_RX <= EB_DONE;
@@ -502,12 +518,23 @@ begin
--TODO: padding to 64bit alignment
when EB_HDR_SEND => if(s_tx_fifo_full = '0') then
if(s_EB_RX_HDR.PROBE = '1') then
- s_state_TX <= IDLE;
+ s_state_TX <= EB_HDR_PROBE_ID;
else
s_state_TX <= RDY;
end if;
end if;
+ when EB_HDR_PROBE_ID => s_state_TX <= EB_HDR_PROBE_WAIT;
+
+
+
+
+ when EB_HDR_PROBE_WAIT => if(s_EB_probe_wait_cnt > 3 AND s_tx_fifo_empty = '1' ) then
+ s_state_TX <= IDLE;
+ end if;
+
+
+
when CYC_HDR_INIT => s_state_TX <= CYC_HDR_SEND;
when CYC_HDR_SEND => if(s_tx_fifo_full = '0') then
@@ -609,7 +636,7 @@ begin
when EB_HDR_REC => if(EB_RX_i.CYC = '1' AND s_rx_fifo_empty = '0') then
s_EB_RX_HDR <= to_EB_HDR(s_rx_fifo_q);
- s_EB_packet_length <= unsigned(byte_count_rx_i) - 42; -- Length - IPHDR - UDPHDR
+ s_EB_packet_length <= unsigned(byte_count_rx_i);
s_rx_fifo_rd <= '1';
end if;
diff --git a/hdl/eb_testbench/EB_2_wb_converter.vhd.bak b/hdl/eb_testbench/EB_2_wb_converter.vhd.bak
index 4595ba4..653578e 100644
--- a/hdl/eb_testbench/EB_2_wb_converter.vhd.bak
+++ b/hdl/eb_testbench/EB_2_wb_converter.vhd.bak
@@ -74,7 +74,9 @@ architecture behavioral of eb_2_wb_converter is
------------------------------------------------------------------------------------------
constant c_width_int : integer := 24;
type t_state_RX is (IDLE, EB_HDR_REC, EB_HDR_PROC, EB_HDR_PROBE_ID, CYC_HDR_REC, CYC_HDR_READ_PROC, CYC_HDR_READ_GET_ADR, WB_READ_RDY, WB_READ, CYC_HDR_WRITE_PROC, CYC_HDR_WRITE_GET_ADR, WB_WRITE_RDY, WB_WRITE, CYC_DONE, EB_DONE, ERROR);
-type t_state_TX is (IDLE, EB_HDR_INIT, EB_HDR_PROBE_ID, PACKET_HDR_SEND, EB_HDR_SEND, RDY, CYC_HDR_INIT, CYC_HDR_SEND, BASE_WRITE_ADR_SEND, DATA_SEND, ZERO_PAD_WRITE, ZERO_PAD_WAIT, ERROR);
+type t_state_TX is (IDLE, EB_HDR_INIT, EB_HDR_PROBE_ID, EB_HDR_PROBE_WAIT, PACKET_HDR_SEND, EB_HDR_SEND, RDY, CYC_HDR_INIT, CYC_HDR_SEND, BASE_WRITE_ADR_SEND, DATA_SEND, ZERO_PAD_WRITE, ZERO_PAD_WAIT, ERROR);
+
+
signal s_state_RX : t_state_RX := IDLE;
signal s_state_TX : t_state_TX := IDLE;
@@ -103,6 +105,7 @@ signal s_WB_ACK_cnt_big : unsigned(8 downto 0);
alias a_WB_ACK_cnt : unsigned(7 downto 0) is s_WB_ACK_cnt_big(7 downto 0);
alias a_WB_ACK_cnt_err : unsigned(0 downto 0) is s_WB_ACK_cnt_big(8 downto 8);
+signal s_EB_probe_wait_cnt : unsigned(7 downto 0);
signal s_EB_TX_zeropad_cnt : unsigned(7 downto 0);
signal s_EB_RX_byte_cnt : unsigned(15 downto 0);
signal s_EB_TX_byte_cnt : unsigned(15 downto 0);
@@ -261,6 +264,7 @@ s_WB_master_o.CYC <= s_WB_CYC;
s_WB_master_o.WE <= s_WB_WE;
EB_RX_o.STALL <= s_rx_fifo_am_full;
EB_RX_o.ACK <= s_EB_RX_ACK;
+EB_RX_o.ERR <= '0';
s_rx_fifo_we <= EB_RX_i.STB AND NOT (s_rx_fifo_am_full); -- OR s_packet_reception_complete);
@@ -346,6 +350,16 @@ begin
end if;
end if;
+ --Counter: Probewait
+ if(s_state_TX = EB_HDR_PROBE_ID) then
+ s_EB_probe_wait_cnt <= (others => '0');
+ else
+ if(s_state_TX = EB_HDR_PROBE_WAIT) then
+ s_EB_probe_wait_cnt <= s_EB_probe_wait_cnt +1;
+ end if;
+ end if;
+
+
end if;
end if;
end process;
@@ -399,13 +413,15 @@ begin
else
--eb hdr seems valid, prepare answering packet. Prefill RX buffer
if(unsigned(s_rx_fifo_gauge) > 3) then
- s_state_TX <= EB_HDR_INIT;
- if(s_EB_RX_HDR.PROBE = '0') then -- no probe, prepare cycle reception
- s_state_RX <= CYC_HDR_REC;
- else
- s_state_RX <= EB_HDR_PROBE_ID ;
- end if;
+ s_state_RX <= CYC_HDR_REC;
+ s_state_TX <= EB_HDR_INIT;
+ else
+ report "EB: Waiting for buffer ..." severity note;
end if;
+ if(s_EB_RX_HDR.PROBE = '1') then -- no probe, prepare cycle reception
+ s_state_RX <= EB_HDR_PROBE_ID ;
+ s_state_TX <= EB_HDR_INIT;
+ end if;
end if;
when EB_HDR_PROBE_ID => s_state_RX <= EB_DONE;
@@ -502,12 +518,23 @@ begin
--TODO: padding to 64bit alignment
when EB_HDR_SEND => if(s_tx_fifo_full = '0') then
if(s_EB_RX_HDR.PROBE = '1') then
- s_state_TX <= IDLE;
+ s_state_TX <= EB_HDR_PROBE_ID;
else
s_state_TX <= RDY;
end if;
end if;
+ when EB_HDR_PROBE_ID => s_state_TX <= EB_HDR_PROBE_WAIT;
+
+
+
+
+ when EB_HDR_PROBE_WAIT => if(s_EB_probe_wait_cnt > 3 AND s_tx_fifo_empty = '1' ) then
+ s_state_TX <= IDLE;
+ end if;
+
+
+
when CYC_HDR_INIT => s_state_TX <= CYC_HDR_SEND;
when CYC_HDR_SEND => if(s_tx_fifo_full = '0') then
@@ -550,7 +577,7 @@ begin
if (nRST_i = '0') then
s_EB_TX_HDR <= init_EB_HDR;
- PROBE_ID <= X"DEADBEEF";
+ PROBE_ID <= X"1337BEEF";
s_EB_TX_CUR_CYCLE <= to_EB_CYC(test);
s_EB_TX_base_wr_adr<= (others => '0');
s_EB_RX_CUR_CYCLE <= to_EB_CYC(test);
@@ -609,7 +636,7 @@ begin
when EB_HDR_REC => if(EB_RX_i.CYC = '1' AND s_rx_fifo_empty = '0') then
s_EB_RX_HDR <= to_EB_HDR(s_rx_fifo_q);
- s_EB_packet_length <= unsigned(byte_count_rx_i) - 42; -- Length - IPHDR - UDPHDR
+ s_EB_packet_length <= unsigned(byte_count_rx_i);
s_rx_fifo_rd <= '1';
end if;
diff --git a/hdl/eb_testbench/EB_CORE.vhd b/hdl/eb_testbench/EB_CORE.vhd
index d907ffa..6ce2a6b 100644
--- a/hdl/eb_testbench/EB_CORE.vhd
+++ b/hdl/eb_testbench/EB_CORE.vhd
@@ -39,7 +39,7 @@ use work.wb16_package.all;
entity EB_CORE is
-generic(g_master_slave : STRING := "SLAVE"; g_eth_framing : natural := 1);
+generic(g_master_slave : STRING := "SLAVE");
port
(
clk_i : in std_logic; --! clock input
@@ -65,9 +65,9 @@ port
src_STALL_i : in std_logic; --
src_ERR_i : in std_logic; --
src_ACK_i : in std_logic; --
- src_adr_o : out std_logic_vector(1 downto 0);
+ src_adr_o : out std_logic_vector(1 downto 0);
- src_sel_o : out std_logic_vector(1 downto 0);
+ src_sel_o : out std_logic_vector(1 downto 0);
--------------------------------------------------------------
debug_TX_TOL_o : out std_logic_vector(15 downto 0);
hex_switch_i : in std_logic_vector(3 downto 0);
@@ -146,6 +146,7 @@ signal RXCTRL_2_TXCTRL_reply_MAC : std_logic_vector(47 downto 0);
signal RXCTRL_2_TXCTRL_reply_IP : std_logic_vector(31 downto 0);
signal RXCTRL_2_TXCTRL_reply_PORT : std_logic_vector(15 downto 0);
signal RXCTRL_2_TXCTRL_TOL : std_logic_vector(15 downto 0);
+signal RXCTRL_2_CORE_LEN : std_logic_vector(15 downto 0);
signal RXCTRL_2_TXCTRL_valid : std_logic;
--EB <-> TXCTRL
@@ -179,7 +180,6 @@ end component;
component EB_TX_CTRL is
-generic(g_eth_framing : natural := 1);
port(
clk_i : in std_logic;
nRst_i : in std_logic;
@@ -205,8 +205,7 @@ port(
end component;
component EB_RX_CTRL is
-generic(g_eth_framing : natural := 1);
- port(
+ port(
clk_i : in std_logic;
nRst_i : in std_logic;
@@ -222,7 +221,8 @@ generic(g_eth_framing : natural := 1);
reply_IP_o : out std_logic_vector(4*8-1 downto 0);
reply_Port_o : out std_logic_vector(2*8-1 downto 0);
TOL_o : out std_logic_vector(2*8-1 downto 0);
-
+ payload_len_o : out std_logic_vector(2*8-1 downto 0);
+
my_mac_i : in std_logic_vector(6*8-1 downto 0);
my_ip_i : in std_logic_vector(4*8-1 downto 0);
my_port_i : in std_logic_vector(2*8-1 downto 0);
@@ -310,50 +310,8 @@ end component;
debug_TX_TOL_o <= RXCTRL_2_TXCTRL_TOL;
-
--- file_sink1: binary_sink generic map ( filename => "Eb_RX_data.dat",
- -- wordsize => 32,
- -- endian => 0)
- -- port map ( clk_i => clk_i,
- -- nRST_i => nRST_i,
- -- rdy_o => open,
- -- sample_i => RXCTRL_2_EB_wb_master.CYC,
- -- valid_i => DEBUG_sink1_valid,
- -- data_i => RXCTRL_2_EB_wb_master.DAT );
-
--- file_sink2: binary_sink generic map ( filename => "Eb_WB_data_o.dat",
- -- wordsize => 32,
- -- endian => 0)
- -- port map ( clk_i => clk_i,
- -- nRST_i => nRST_i,
- -- rdy_o => open,
- -- sample_i => DEBUG_WB_master_o.CYC,
- -- valid_i => DEBUG_sink23_valid,
- -- data_i => DEBUG_WB_master_o.DAT );
-
- -- file_sink3: binary_sink generic map ( filename => "Eb_WB_addr.dat",
- -- wordsize => 32,
- -- endian => 0)
- -- port map ( clk_i => clk_i,
- -- nRST_i => nRST_i,
- -- rdy_o => open,
- -- sample_i => DEBUG_WB_master_o.CYC,
- -- valid_i => DEBUG_sink23_valid,
- -- data_i => DEBUG_WB_master_o.ADR );
-
- -- file_sink4: binary_sink generic map ( filename => "Eb_WB_data_i.dat",
- -- wordsize => 32,
- -- endian => 0)
- -- port map ( clk_i => clk_i,
- -- nRST_i => nRST_i,
- -- rdy_o => open,
- -- sample_i => DEBUG_WB_master_o.CYC,
- -- valid_i => WB_master_i.ACK,
- -- data_i => WB_master_i.DAT );
-
-
DEBUG_sink1_valid <= (RXCTRL_2_EB_wb_master.STB AND NOT EB_2_RXCTRL_wb_slave.STALL);
DEBUG_sink23_valid <= (DEBUG_WB_master_o.STB AND NOT WB_master_i.STALL);
@@ -444,7 +402,6 @@ master : if(g_master_slave = "MASTER") generate
);
TXCTRL : EB_TX_CTRL
- generic map(g_eth_framing => g_eth_framing)
port map
(
clk_i => clk_i,
@@ -469,7 +426,6 @@ master : if(g_master_slave = "MASTER") generate
RXCTRL: EB_RX_CTRL
- generic map(g_eth_framing => g_eth_framing)
port map ( clk_i => clk_i,
nRst_i => nRst_i,
wb_master_i => EB_2_RXCTRL_wb_master,
@@ -494,7 +450,6 @@ end generate;
slave : if(g_master_slave = "SLAVE") generate
TXCTRL : EB_TX_CTRL
- generic map(g_eth_framing => g_eth_framing)
port map
(
clk_i => clk_i,
@@ -519,7 +474,6 @@ slave : if(g_master_slave = "SLAVE") generate
RXCTRL: EB_RX_CTRL
- generic map(g_eth_framing => g_eth_framing)
port map ( clk_i => clk_i,
nRst_i => nRst_i,
wb_master_i => EB_2_RXCTRL_wb_master,
@@ -532,6 +486,7 @@ slave : if(g_master_slave = "SLAVE") generate
reply_IP_o => RXCTRL_2_TXCTRL_reply_IP,
reply_PORT_o => RXCTRL_2_TXCTRL_reply_PORT,
TOL_o => RXCTRL_2_TXCTRL_TOL,
+ payload_len_o => RXCTRL_2_CORE_LEN,
my_mac_i => CFG_MY_MAC,
my_ip_i => CFG_MY_IP,
my_port_i => CFG_MY_PORT,
@@ -553,7 +508,7 @@ slave : if(g_master_slave = "SLAVE") generate
EB_TX_i => TXCTRL_2_EB_wb_master,
EB_TX_o => EB_2_TXCTRL_wb_master,
- byte_count_rx_i => RXCTRL_2_TXCTRL_TOL,
+ byte_count_rx_i => RXCTRL_2_CORE_LEN,
config_master_i => CFG_2_eb_slave,
config_master_o => eb_2_CFG_slave,
diff --git a/hdl/eb_testbench/EB_CORE.vhd.bak b/hdl/eb_testbench/EB_CORE.vhd.bak
index 2035ff8..0b9e2f7 100644
--- a/hdl/eb_testbench/EB_CORE.vhd.bak
+++ b/hdl/eb_testbench/EB_CORE.vhd.bak
@@ -39,7 +39,7 @@ use work.wb16_package.all;
entity EB_CORE is
-generic(g_master_slave : STRING := "SLAVE"; g_eth_framing : natural := 1);
+generic(g_master_slave : STRING := "SLAVE");
port
(
clk_i : in std_logic; --! clock input
@@ -65,9 +65,9 @@ port
src_STALL_i : in std_logic; --
src_ERR_i : in std_logic; --
src_ACK_i : in std_logic; --
- src_adr_o : out std_logic_vector(1 downto 0);
+ src_adr_o : out std_logic_vector(1 downto 0);
- src_sel_o : out std_logic_vector(1 downto 0);
+ src_sel_o : out std_logic_vector(1 downto 0);
--------------------------------------------------------------
debug_TX_TOL_o : out std_logic_vector(15 downto 0);
hex_switch_i : in std_logic_vector(3 downto 0);
@@ -179,7 +179,6 @@ end component;
component EB_TX_CTRL is
-generic(g_eth_framing : STRING := "ON");
port(
clk_i : in std_logic;
nRst_i : in std_logic;
@@ -205,7 +204,6 @@ port(
end component;
component EB_RX_CTRL is
-generic(g_eth_framing : natural := 1);
port(
clk_i : in std_logic;
nRst_i : in std_logic;
@@ -310,49 +308,7 @@ end component;
debug_TX_TOL_o <= RXCTRL_2_TXCTRL_TOL;
-
-
--- file_sink1: binary_sink generic map ( filename => "Eb_RX_data.dat",
- -- wordsize => 32,
- -- endian => 0)
- -- port map ( clk_i => clk_i,
- -- nRST_i => nRST_i,
- -- rdy_o => open,
- -- sample_i => RXCTRL_2_EB_wb_master.CYC,
- -- valid_i => DEBUG_sink1_valid,
- -- data_i => RXCTRL_2_EB_wb_master.DAT );
-
--- file_sink2: binary_sink generic map ( filename => "Eb_WB_data_o.dat",
- -- wordsize => 32,
- -- endian => 0)
- -- port map ( clk_i => clk_i,
- -- nRST_i => nRST_i,
- -- rdy_o => open,
- -- sample_i => DEBUG_WB_master_o.CYC,
- -- valid_i => DEBUG_sink23_valid,
- -- data_i => DEBUG_WB_master_o.DAT );
-
- -- file_sink3: binary_sink generic map ( filename => "Eb_WB_addr.dat",
- -- wordsize => 32,
- -- endian => 0)
- -- port map ( clk_i => clk_i,
- -- nRST_i => nRST_i,
- -- rdy_o => open,
- -- sample_i => DEBUG_WB_master_o.CYC,
- -- valid_i => DEBUG_sink23_valid,
- -- data_i => DEBUG_WB_master_o.ADR );
-
- -- file_sink4: binary_sink generic map ( filename => "Eb_WB_data_i.dat",
- -- wordsize => 32,
- -- endian => 0)
- -- port map ( clk_i => clk_i,
- -- nRST_i => nRST_i,
- -- rdy_o => open,
- -- sample_i => DEBUG_WB_master_o.CYC,
- -- valid_i => WB_master_i.ACK,
- -- data_i => WB_master_i.DAT );
-
DEBUG_sink1_valid <= (RXCTRL_2_EB_wb_master.STB AND NOT EB_2_RXCTRL_wb_slave.STALL);
DEBUG_sink23_valid <= (DEBUG_WB_master_o.STB AND NOT WB_master_i.STALL);
@@ -444,7 +400,6 @@ master : if(g_master_slave = "MASTER") generate
);
TXCTRL : EB_TX_CTRL
- generic map(g_eth_framing => g_eth_framing)
port map
(
clk_i => clk_i,
@@ -469,7 +424,6 @@ master : if(g_master_slave = "MASTER") generate
RXCTRL: EB_RX_CTRL
- generic map(g_eth_framing => g_eth_framing)
port map ( clk_i => clk_i,
nRst_i => nRst_i,
wb_master_i => EB_2_RXCTRL_wb_master,
@@ -494,7 +448,6 @@ end generate;
slave : if(g_master_slave = "SLAVE") generate
TXCTRL : EB_TX_CTRL
- generic map(g_eth_framing => g_eth_framing)
port map
(
clk_i => clk_i,
@@ -519,7 +472,6 @@ slave : if(g_master_slave = "SLAVE") generate
RXCTRL: EB_RX_CTRL
- generic map(g_eth_framing => g_eth_framing)
port map ( clk_i => clk_i,
nRst_i => nRst_i,
wb_master_i => EB_2_RXCTRL_wb_master,
diff --git a/hdl/eb_testbench/EB_RX_CTRL.vhd b/hdl/eb_testbench/EB_RX_CTRL.vhd
index 727ed53..6fe41ff 100644
--- a/hdl/eb_testbench/EB_RX_CTRL.vhd
+++ b/hdl/eb_testbench/EB_RX_CTRL.vhd
@@ -40,7 +40,6 @@ use work.wb32_package.all;
use work.wb16_package.all;
entity EB_RX_CTRL is
- generic(g_eth_framing : natural := 1);
port(
clk_i : in std_logic;
nRst_i : in std_logic;
@@ -57,7 +56,8 @@ entity EB_RX_CTRL is
reply_IP_o : out std_logic_vector(4*8-1 downto 0);
reply_Port_o : out std_logic_vector(2*8-1 downto 0);
TOL_o : out std_logic_vector(2*8-1 downto 0);
-
+ payload_len_o : out std_logic_vector(2*8-1 downto 0);
+
my_mac_i : in std_logic_vector(6*8-1 downto 0);
my_ip_i : in std_logic_vector(4*8-1 downto 0);
my_port_i : in std_logic_vector(2*8-1 downto 0);
@@ -133,6 +133,7 @@ architecture behavioral of EB_RX_CTRL is
signal ETH_RX : ETH_HDR;
signal IPV4_RX : IPV4_HDR;
signal UDP_RX : UDP_HDR;
+ signal payload_len : std_logic_vector(2*8-1 downto 0);
signal RX_HDR_slv : std_logic_vector(c_IPV4_HLEN*8-1 downto 0) ;
@@ -164,7 +165,7 @@ begin
- Shift_in : sipo_flag generic map (16, c_IPV4_HLEN*8)
+ Shift_in : sipo_flag generic map (16, c_IPV4_HLEN*8) --IP header is longest possibility
port map (d_i => RX_slave_i.DAT,
q_o => RX_HDR_slv,
clk_i => clk_i,
@@ -216,7 +217,7 @@ begin
RX_hdr_o.STALL <= HDR_STALL;
-
+
MUX_RX : with state_mux select
RX_slave_o <= conv_A when PAYLOAD,
RX_hdr_o when others;
@@ -240,6 +241,7 @@ begin
reply_MAC_o <= ETH_RX.SRC;
reply_IP_o <= IPV4_RX.SRC;
reply_PORT_o <= UDP_RX.SRC_PORT;
+ payload_len_o <= payload_len;
TOL_o <= IPV4_RX.TOL;
@@ -251,34 +253,28 @@ begin
-- SYNC RESET
--==========================================================================
if (nRST_i = '0') then
- if(g_eth_framing = 1) then
- state_HDR <= ETH;
- else
- state_HDR <= IPV4;
- end if;
- counter_input <= 0;
- hdr_done <= '0';
- HDR_STALL <= '0';
- else
-
- if(counter_clr = '1') then
- if(g_eth_framing = 1) then
- state_HDR <= ETH;
- else
- state_HDR <= IPV4;
- end if;
- counter_input <= 0;
+
+ state_HDR <= ETH;
+ counter_input <= 0;
+ hdr_done <= '0';
+ state_mux <= HEADER;
+ HDR_STALL <= '0';
+ else
+
+ if(counter_clr = '1') then
+ state_HDR <= ETH;
+ counter_input <= 0;
hdr_done <= '0';
state_mux <= HEADER;
+
end if;
+
+
-
-
-
-
- if(state_RX = HDR_RECEIVE) then
+ if(state_RX = HDR_RECEIVE) then
if(RX_slave_i.CYC = '1' and RX_slave_i.STB = '1') then
counter_input <= counter_input +2;
+
end if;
case state_HDR is
@@ -336,13 +332,18 @@ end process;
-
+ payload_len <= (others => '0');
else
counter_clr <= '0';
sipo_clr <= '0';
-
+ RX_hdr_o.ACK <= '0';
+ if(RX_slave_i.CYC = '1' and RX_slave_i.STB = '1') then
+ RX_hdr_o.ACK <= '1';
+ end if;
+
+
if((RX_slave_i.CYC = '0') and not ((state_RX = PAYLOAD_RECEIVE) or (state_RX = IDLE))) then --packet aborted before completion
state_RX <= error;
else
@@ -350,32 +351,16 @@ end process;
case state_RX is
when IDLE => counter_clr <= '1';
if(RX_slave_i.CYC = '1' and RX_slave_i.STB = '1') then
- --check if this is synthesised correctly
-
-
- state_RX <= HDR_RECEIVE;
- valid_o <= '1';
- end if;
+ state_RX <= HDR_RECEIVE;
+ end if;
when HDR_RECEIVE => if(hdr_done = '1') then
state_RX <= PAYLOAD_RECEIVE;
-
-
- end if;
-
- when WAIT_STATE => state_RX <= CHECK_HDR;
-
- when CHECK_HDR => if(ETH_RX.TYP = x"0800" and IPV4_RX.PRO = x"11") then
- valid_o <= '1';
- --
-
- state_rx <= PAYLOAD_RECEIVE;
- else
- report("BAD PACKET HDR") severity warning;
- state_rx <= error;
- end if;
-
-
+ payload_len <= std_logic_vector(unsigned(UDP_RX .MLEN)-8);
+ valid_o <= '1';
+ end if;
+
+
when PAYLOAD_RECEIVE => if(RX_slave_i.CYC = '0') then
state_RX <= IDLE;
diff --git a/hdl/eb_testbench/EB_RX_CTRL.vhd.bak b/hdl/eb_testbench/EB_RX_CTRL.vhd.bak
index 809ab9e..cfa2f47 100644
--- a/hdl/eb_testbench/EB_RX_CTRL.vhd.bak
+++ b/hdl/eb_testbench/EB_RX_CTRL.vhd.bak
@@ -40,7 +40,6 @@ use work.wb32_package.all;
use work.wb16_package.all;
entity EB_RX_CTRL is
- generic(g_eth_framing : natural := 1);
port(
clk_i : in std_logic;
nRst_i : in std_logic;
@@ -57,7 +56,8 @@ entity EB_RX_CTRL is
reply_IP_o : out std_logic_vector(4*8-1 downto 0);
reply_Port_o : out std_logic_vector(2*8-1 downto 0);
TOL_o : out std_logic_vector(2*8-1 downto 0);
-
+ payload_len_o : out std_logic_vector(2*8-1 downto 0);
+
my_mac_i : in std_logic_vector(6*8-1 downto 0);
my_ip_i : in std_logic_vector(4*8-1 downto 0);
my_port_i : in std_logic_vector(2*8-1 downto 0);
@@ -133,6 +133,7 @@ architecture behavioral of EB_RX_CTRL is
signal ETH_RX : ETH_HDR;
signal IPV4_RX : IPV4_HDR;
signal UDP_RX : UDP_HDR;
+ signal payload_len : std_logic_vector(2*8-1 downto 0);
signal RX_HDR_slv : std_logic_vector(c_IPV4_HLEN*8-1 downto 0) ;
@@ -164,7 +165,7 @@ begin
- Shift_in : sipo_flag generic map (16, c_IPV4_HLEN*8)
+ Shift_in : sipo_flag generic map (16, c_IPV4_HLEN*8) --IP header is longest possibility
port map (d_i => RX_slave_i.DAT,
q_o => RX_HDR_slv,
clk_i => clk_i,
@@ -216,7 +217,7 @@ begin
RX_hdr_o.STALL <= HDR_STALL;
-
+
MUX_RX : with state_mux select
RX_slave_o <= conv_A when PAYLOAD,
RX_hdr_o when others;
@@ -240,6 +241,7 @@ begin
reply_MAC_o <= ETH_RX.SRC;
reply_IP_o <= IPV4_RX.SRC;
reply_PORT_o <= UDP_RX.SRC_PORT;
+ payload_len_o <= payload_len;
TOL_o <= IPV4_RX.TOL;
@@ -251,34 +253,28 @@ begin
-- SYNC RESET
--==========================================================================
if (nRST_i = '0') then
- if(g_eth_framing = 1) then
- state_HDR <= ETH;
- else
- state_HDR <= IPV4;
- end if;
- counter_input <= 0;
- hdr_done <= '0';
- HDR_STALL <= '0';
- else
-
- if(counter_clr = '1') then
- if(g_eth_framing = 1) then
- state_HDR <= ETH;
- else
- state_HDR <= IPV4;
- end if;
- counter_input <= 0;
+
+ state_HDR <= ETH;
+ counter_input <= 0;
+ hdr_done <= '0';
+ state_mux <= HEADER;
+ HDR_STALL <= '0';
+ else
+
+ if(counter_clr = '1') then
+ state_HDR <= ETH;
+ counter_input <= 0;
hdr_done <= '0';
state_mux <= HEADER;
+
end if;
+
+
-
-
-
-
- if(state_RX = HDR_RECEIVE) then
+ if(state_RX = HDR_RECEIVE) then
if(RX_slave_i.CYC = '1' and RX_slave_i.STB = '1') then
counter_input <= counter_input +2;
+
end if;
case state_HDR is
@@ -336,13 +332,18 @@ end process;
-
+ payload_len <= (others => '0');
else
counter_clr <= '0';
sipo_clr <= '0';
-
+ RX_slave_o.ACK <= '0';
+ if(RX_slave_i.CYC = '1' and RX_slave_i.STB = '1') then
+ RX_slave_o.ACK <= '1';
+ end if;
+
+
if((RX_slave_i.CYC = '0') and not ((state_RX = PAYLOAD_RECEIVE) or (state_RX = IDLE))) then --packet aborted before completion
state_RX <= error;
else
@@ -350,32 +351,16 @@ end process;
case state_RX is
when IDLE => counter_clr <= '1';
if(RX_slave_i.CYC = '1' and RX_slave_i.STB = '1') then
- --check if this is synthesised correctly
-
-
- state_RX <= HDR_RECEIVE;
-
- end if;
+ state_RX <= HDR_RECEIVE;
+ end if;
when HDR_RECEIVE => if(hdr_done = '1') then
state_RX <= PAYLOAD_RECEIVE;
-
-
- end if;
-
- when WAIT_STATE => state_RX <= CHECK_HDR;
-
- when CHECK_HDR => if(ETH_RX.TYP = x"0800" and IPV4_RX.PRO = x"11") then
- valid_o <= '1';
- --
-
- state_rx <= PAYLOAD_RECEIVE;
- else
- report("BAD PACKET HDR") severity warning;
- state_rx <= error;
- end if;
-
-
+ payload_len <= std_logic_vector(unsigned(UDP_RX .MLEN)-8);
+ valid_o <= '1';
+ end if;
+
+
when PAYLOAD_RECEIVE => if(RX_slave_i.CYC = '0') then
state_RX <= IDLE;
diff --git a/hdl/eb_testbench/EB_TX_CTRL.vhd b/hdl/eb_testbench/EB_TX_CTRL.vhd
index cfb4ce7..8860c6d 100644
--- a/hdl/eb_testbench/EB_TX_CTRL.vhd
+++ b/hdl/eb_testbench/EB_TX_CTRL.vhd
@@ -39,7 +39,6 @@ use work.wb32_package.all;
use work.wb16_package.all;
entity EB_TX_CTRL is
-generic(g_eth_framing : natural := 1);
port(
clk_i : in std_logic;
nRst_i : in std_logic;
diff --git a/hdl/eb_testbench/EB_TX_CTRL.vhd.bak b/hdl/eb_testbench/EB_TX_CTRL.vhd.bak
index bb24fe0..cfb4ce7 100644
--- a/hdl/eb_testbench/EB_TX_CTRL.vhd.bak
+++ b/hdl/eb_testbench/EB_TX_CTRL.vhd.bak
@@ -39,7 +39,7 @@ use work.wb32_package.all;
use work.wb16_package.all;
entity EB_TX_CTRL is
-generic(g_eth_framing : STRING := "ON");
+generic(g_eth_framing : natural := 1);
port(
clk_i : in std_logic;
nRst_i : in std_logic;
diff --git a/hdl/eb_testbench/eb_tb.cr.mti b/hdl/eb_testbench/eb_tb.cr.mti
index 3e81434..155f0b1 100644
--- a/hdl/eb_testbench/eb_tb.cr.mti
+++ b/hdl/eb_testbench/eb_tb.cr.mti
@@ -23,6 +23,18 @@ Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
Top level modules:
--none--
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/EB_RX_CTRL.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/EB_RX_CTRL.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package EB_HDR_PKG
+-- Loading package wb32_package
+-- Loading package wb16_package
+-- Compiling entity EB_RX_CTRL
+-- Compiling architecture behavioral of EB_RX_CTRL
+
} {} {}} /home/mkreider/hdlprojects/eb_testbench/alt_FIFO_am_full_flag.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/alt_FIFO_am_full_flag.vhd
Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Loading package STANDARD
@@ -98,28 +110,28 @@ Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
Top level modules:
--none--
-} {} {}} /home/mkreider/hdlprojects/eb_testbench/if_wishbone_types.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/if_wishbone_types.svh
-Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
-
-Top level modules:
- --none--
-
-} {} {}} /home/mkreider/hdlprojects/eb_testbench/wishbone_pkg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/wishbone_pkg.vhd
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/wr_fabric_pkg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/wr_fabric_pkg.vhd
Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
--- Loading package NUMERIC_STD
--- Compiling package wishbone_pkg
+-- Compiling package wr_fabric_pkg
+-- Compiling package body wr_fabric_pkg
+-- Loading package wr_fabric_pkg
-} {} {}} /home/mkreider/hdlprojects/eb_testbench/wr_fabric_pkg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/wr_fabric_pkg.vhd
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/wishbone_pkg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/wishbone_pkg.vhd
Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
--- Compiling package wr_fabric_pkg
--- Compiling package body wr_fabric_pkg
--- Loading package wr_fabric_pkg
+-- Loading package NUMERIC_STD
+-- Compiling package wishbone_pkg
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/if_wishbone_types.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/if_wishbone_types.svh
+Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
+
+Top level modules:
+ --none--
} {} {}} /home/mkreider/hdlprojects/eb_testbench/EB_checksum.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/EB_checksum.vhd
Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
@@ -131,6 +143,16 @@ Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Compiling entity EB_checksum
-- Compiling architecture behavioral of EB_checksum
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/vhdl_2008_workaround_pkg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/vhdl_2008_workaround_pkg.vhd
+Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling package vhdl_2008_workaround_pkg
+-- Compiling package body vhdl_2008_workaround_pkg
+-- Loading package vhdl_2008_workaround_pkg
+
} {} {}} /home/mkreider/hdlprojects/eb_testbench/if_wb_link.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/if_wb_link.svh
Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
-- Compiling interface IWishboneLink
@@ -144,27 +166,15 @@ Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
Top level modules:
--none--
-} {} {}} /home/mkreider/hdlprojects/eb_testbench/vhdl_2008_workaround_pkg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/vhdl_2008_workaround_pkg.vhd
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/sipo_flag.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/sipo_flag.vhd
Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
--- Compiling package vhdl_2008_workaround_pkg
--- Compiling package body vhdl_2008_workaround_pkg
-- Loading package vhdl_2008_workaround_pkg
-
-} {} {}} /home/mkreider/hdlprojects/eb_testbench/main.sv {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/main.sv
-Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
--- Compiling interface IWishboneMaster
--- Compiling interface IWishboneSlave
--- Compiling package main_sv_unit
--- Compiling interface IWishboneMaster
--- Compiling interface IWishboneSlave
--- Compiling module main
-
-Top level modules:
- main
+-- Compiling entity sipo_flag
+-- Compiling architecture behavioral of sipo_flag
} {} {}} /home/mkreider/hdlprojects/eb_testbench/piso_flag.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/piso_flag.vhd
Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
@@ -175,15 +185,11 @@ Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Compiling entity piso_flag
-- Compiling architecture behavioral of piso_flag
-} {} {}} /home/mkreider/hdlprojects/eb_testbench/sipo_flag.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/sipo_flag.vhd
-Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
--- Loading package STANDARD
--- Loading package TEXTIO
--- Loading package std_logic_1164
--- Loading package NUMERIC_STD
--- Loading package vhdl_2008_workaround_pkg
--- Compiling entity sipo_flag
--- Compiling architecture behavioral of sipo_flag
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/simdrv_defs.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/simdrv_defs.svh
+Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
+
+Top level modules:
+ --none--
} {} {}} /home/mkreider/hdlprojects/eb_testbench/EB_HDR_pkg.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/EB_HDR_pkg.vhd
Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
@@ -195,12 +201,6 @@ Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Compiling package body EB_HDR_PKG
-- Loading package EB_HDR_PKG
-} {} {}} /home/mkreider/hdlprojects/eb_testbench/simdrv_defs.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/simdrv_defs.svh
-Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
-
-Top level modules:
- --none--
-
} {} {}} /home/mkreider/hdlprojects/eb_testbench/if_wishbone_accessor.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/if_wishbone_accessor.svh
Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
@@ -217,16 +217,7 @@ Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Compiling package body wb32_package
-- Loading package wb32_package
-} {} {}} /home/mkreider/hdlprojects/eb_testbench/if_wb_slave.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/if_wb_slave.svh
-Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
--- Compiling interface IWishboneSlave
--- Compiling package if_wb_slave_svh_unit
--- Compiling interface IWishboneSlave
-
-Top level modules:
- --none--
-
-} {} {}} /home/mkreider/hdlprojects/eb_testbench/mini_bone.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/mini_bone.vhd
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/xmini_bone.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/xmini_bone.vhd
Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Loading package STANDARD
-- Loading package TEXTIO
@@ -234,10 +225,10 @@ Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Loading package NUMERIC_STD
-- Loading package wishbone_pkg
-- Loading package wr_fabric_pkg
--- Compiling entity mini_bone
--- Compiling architecture wrapper of mini_bone
+-- Compiling entity xmini_bone
+-- Compiling architecture behavioral of xmini_bone
-} {} {}} /home/mkreider/hdlprojects/eb_testbench/xmini_bone.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/xmini_bone.vhd
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/mini_bone.vhd {1 {vcom -work work -2002 -explicit -vopt /home/mkreider/hdlprojects/eb_testbench/mini_bone.vhd
Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Loading package STANDARD
-- Loading package TEXTIO
@@ -245,7 +236,16 @@ Model Technology ModelSim SE vcom 10.0c Compiler 2011.07 Jul 21 2011
-- Loading package NUMERIC_STD
-- Loading package wishbone_pkg
-- Loading package wr_fabric_pkg
--- Compiling entity xmini_bone
--- Compiling architecture behavioral of xmini_bone
+-- Compiling entity mini_bone
+-- Compiling architecture wrapper of mini_bone
+
+} {} {}} /home/mkreider/hdlprojects/eb_testbench/if_wb_slave.svh {1 {vlog -work work -vopt -sv -nocovercells /home/mkreider/hdlprojects/eb_testbench/if_wb_slave.svh
+Model Technology ModelSim SE vlog 10.0c Compiler 2011.07 Jul 21 2011
+-- Compiling interface IWishboneSlave
+-- Compiling package if_wb_slave_svh_unit
+-- Compiling interface IWishboneSlave
+
+Top level modules:
+ --none--
} {} {}}
diff --git a/hdl/eb_testbench/eb_tb.mpf b/hdl/eb_testbench/eb_tb.mpf
index 871752b..76f2c3c 100644
--- a/hdl/eb_testbench/eb_tb.mpf
+++ b/hdl/eb_testbench/eb_tb.mpf
@@ -654,7 +654,7 @@ Resolution = ns
UserTimeUnit = default
; Default run length
-RunLength = 100 ns
+RunLength = 15 us
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
@@ -1678,61 +1678,61 @@ Project_Files_Count = 29
Project_File_0 = /home/mkreider/hdlprojects/eb_testbench/wishbone_package16.vhd
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191040 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 25 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_1 = /home/mkreider/hdlprojects/eb_testbench/if_wb_master.svh
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1327407856 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1327407856 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = /home/mkreider/hdlprojects/eb_testbench/wb_packet_sink.svh
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1327407856 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1327407856 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = /home/mkreider/hdlprojects/eb_testbench/alt_FIFO_am_full_flag.vhd
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191766 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 27 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_4 = /home/mkreider/hdlprojects/eb_testbench/WB_bus_adapter_streaming_sg.vhd
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191114 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 24 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_5 = /home/mkreider/hdlprojects/eb_testbench/EB_RX_CTRL.vhd
-Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328808735 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 19 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328869211 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_6 = /home/mkreider/hdlprojects/eb_testbench/eb_config_new.vhd
Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328792784 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 28 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_7 = /home/mkreider/hdlprojects/eb_testbench/EB_TX_CTRL.vhd
-Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328792966 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 20 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328864313 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 20 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_8 = /home/mkreider/hdlprojects/eb_testbench/EB_2_wb_converter.vhd
-Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328801786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 16 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328872196 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_9 = /home/mkreider/hdlprojects/eb_testbench/EB_CORE.vhd
-Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328792886 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328867050 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_10 = /home/mkreider/hdlprojects/eb_testbench/wb_fabric_defs.svh
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1327407856 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1327407856 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_11 = /home/mkreider/hdlprojects/eb_testbench/eth_packet.svh
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1327407856 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_12 = /home/mkreider/hdlprojects/eb_testbench/wr_fabric_pkg.vhd
-Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1327407856 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1327407856 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_12 = /home/mkreider/hdlprojects/eb_testbench/if_wishbone_types.svh
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1327407856 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = /home/mkreider/hdlprojects/eb_testbench/wishbone_pkg.vhd
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328182231 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_14 = /home/mkreider/hdlprojects/eb_testbench/if_wishbone_types.svh
-Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1327407856 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_14 = /home/mkreider/hdlprojects/eb_testbench/wr_fabric_pkg.vhd
+Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1327407856 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_15 = /home/mkreider/hdlprojects/eb_testbench/EB_checksum.vhd
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191632 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_16 = /home/mkreider/hdlprojects/eb_testbench/vhdl_2008_workaround_pkg.vhd
-Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191147 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_16 = /home/mkreider/hdlprojects/eb_testbench/if_wb_link.svh
+Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1327407856 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_17 = /home/mkreider/hdlprojects/eb_testbench/wb_binary_file_source.svh
-Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1328266887 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_18 = /home/mkreider/hdlprojects/eb_testbench/if_wb_link.svh
-Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1327407856 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_19 = /home/mkreider/hdlprojects/eb_testbench/sipo_flag.vhd
-Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191228 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1328872346 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_18 = /home/mkreider/hdlprojects/eb_testbench/vhdl_2008_workaround_pkg.vhd
+Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191147 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_19 = /home/mkreider/hdlprojects/eb_testbench/main.sv
+Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1328872936 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_20 = /home/mkreider/hdlprojects/eb_testbench/piso_flag.vhd
Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191255 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_21 = /home/mkreider/hdlprojects/eb_testbench/main.sv
-Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1328793452 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_22 = /home/mkreider/hdlprojects/eb_testbench/EB_HDR_pkg.vhd
-Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328801006 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 18 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_23 = /home/mkreider/hdlprojects/eb_testbench/simdrv_defs.svh
-Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1327407856 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_21 = /home/mkreider/hdlprojects/eb_testbench/sipo_flag.vhd
+Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191228 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_22 = /home/mkreider/hdlprojects/eb_testbench/simdrv_defs.svh
+Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1327407856 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_23 = /home/mkreider/hdlprojects/eb_testbench/EB_HDR_pkg.vhd
+Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328801006 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 18 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_24 = /home/mkreider/hdlprojects/eb_testbench/if_wishbone_accessor.svh
-Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1327407856 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1327407856 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_25 = /home/mkreider/hdlprojects/eb_testbench/wishbone_package32.vhd
Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328191023 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 26 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_26 = /home/mkreider/hdlprojects/eb_testbench/if_wb_slave.svh
-Project_File_P_26 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1328197801 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_26 = /home/mkreider/hdlprojects/eb_testbench/xmini_bone.vhd
+Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1327407856 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_27 = /home/mkreider/hdlprojects/eb_testbench/mini_bone.vhd
Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1328197717 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_28 = /home/mkreider/hdlprojects/eb_testbench/xmini_bone.vhd
-Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1327407856 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_28 = /home/mkreider/hdlprojects/eb_testbench/if_wb_slave.svh
+Project_File_P_28 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} last_compile 1328197801 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 1
diff --git a/hdl/eb_testbench/main.sv b/hdl/eb_testbench/main.sv
index 26f010d..80caa2a 100644
--- a/hdl/eb_testbench/main.sv
+++ b/hdl/eb_testbench/main.sv
@@ -223,7 +223,7 @@ module main;
$display("Iteration %d", retries);
- seed = retries;
+ seed = retries+3;
for(i=0;i<n_writes;i++)
mbone_write(i, $dist_uniform(seed, 0, (1<<31)-1));
diff --git a/hdl/eb_testbench/main.sv.bak b/hdl/eb_testbench/main.sv.bak
index e7a6f56..32bb6a4 100644
--- a/hdl/eb_testbench/main.sv.bak
+++ b/hdl/eb_testbench/main.sv.bak
@@ -51,7 +51,7 @@ module main;
EB_CORE
#(
.g_master_slave("SLAVE"),
- .g_eth_framing("OFF"))
+ .g_eth_framing(1))
DUT
(
.clk_i (clk_sys),
@@ -223,7 +223,7 @@ module main;
$display("Iteration %d", retries);
- seed = retries;
+ seed = retries+2;
for(i=0;i<n_writes;i++)
mbone_write(i, $dist_uniform(seed, 0, (1<<31)-1));
diff --git a/hdl/eb_testbench/wb_binary_file_source.svh b/hdl/eb_testbench/wb_binary_file_source.svh
index c0dff36..f65692d 100644
--- a/hdl/eb_testbench/wb_binary_file_source.svh
+++ b/hdl/eb_testbench/wb_binary_file_source.svh
@@ -37,7 +37,7 @@ int r, i, j, len, file;
wb_cycle_t cyc;
wb_xfer_t xf;
- file_name = "test_V4.pcap";
+ file_name = "etherbone-v4-req.pcap";
file = $fopen(file_name, "rb");
i = $fgetc(file);
$display("test char %0d \n", i);
diff --git a/hdl/eb_testbench/wb_binary_file_source.svh.bak b/hdl/eb_testbench/wb_binary_file_source.svh.bak
index 43f5fe2..0f71c1a 100644
--- a/hdl/eb_testbench/wb_binary_file_source.svh.bak
+++ b/hdl/eb_testbench/wb_binary_file_source.svh.bak
@@ -33,11 +33,11 @@ class WBPacketSource extends EthPacketSource;
reg [15:0] pdata[0:`MEM_SIZE];
reg [80*8:1] file_name;
-int r, i, len, file;
+int r, i, j, len, file;
wb_cycle_t cyc;
wb_xfer_t xf;
- file_name = "test_V4.pcap";
+ file_name = "etherbone-v4-pf.pcap";
file = $fopen(file_name, "rb");
i = $fgetc(file);
$display("test char %0d \n", i);
@@ -58,8 +58,8 @@ int r, i, len, file;
-
- for(i=0; i < len; i += 0)
+ j = 0;
+ for(i=0; j < len; i++)
begin
xf.a = WRF_DATA;
if(i==len-1 && (len&1))
@@ -70,7 +70,7 @@ int r, i, len, file;
xf.size = 2;
xf.d = pdata[i];
end
- i += xf.size;
+ j += xf.size;
cyc.data.push_back(xf);
end
--
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