From c1b7f76efad625bdf6158411c490840f36c62375 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <w.terpstra@gsi.de>
Date: Thu, 28 Mar 2013 11:03:58 +0100
Subject: [PATCH] Initial firmware derived from Wolfgang Wieser.
---
hdl/eb_usb_core/cdc_acm.c | 591 ++++++++++++++++++++++++++++++++++
hdl/eb_usb_core/fx2.h | 380 ++++++++++++++++++++++
hdl/eb_usb_core/fx2regs.h | 649 ++++++++++++++++++++++++++++++++++++++
3 files changed, 1620 insertions(+)
create mode 100644 hdl/eb_usb_core/cdc_acm.c
create mode 100644 hdl/eb_usb_core/fx2.h
create mode 100644 hdl/eb_usb_core/fx2regs.h
diff --git a/hdl/eb_usb_core/cdc_acm.c b/hdl/eb_usb_core/cdc_acm.c
new file mode 100644
index 0000000..17e28d7
--- /dev/null
+++ b/hdl/eb_usb_core/cdc_acm.c
@@ -0,0 +1,591 @@
+/* -*- mode: C; c-basic-offset: 3; -*-
+ *
+ * convert_serial2 -- FX2 USB serial port converter
+ *
+ * by Brent Baccala <cosine@freesoft.org> July 2009
+ * and Wolfgang Wieser ] wwieser (a) gmx <*> de [ Aug. 2009
+ *
+ * Based on both usb-fx2-local-examples by Wolfgang Wieser (GPLv2) and
+ * the Cypress FX2 examples.
+ *
+ * This is an FX2 program which re-enumerates to mimic a USB-attached
+ * serial port (a Sierra Wireless modem).
+ * Anything transmitted to it by the host is echoed back after converting
+ * lowercase to uppercase.
+ * The re-enumerated FX2 appears on a Debian Linux machine as something
+ * like /dev/ttyUSB0, and can be tested with a serial port program
+ * like 'minicom'.
+ *
+ * Features like setting and querying things like the baudrate
+ * and line/modem status are unimplemented, and will return USB errors
+ * when the host attempts to perform these operations. However, the
+ * program works, and I decided to leave out the additional clutter in
+ * favor of a simpler program that can be easily modified to suit
+ * individual needs.
+ *
+ * The program ignores USB Suspend interrupts, and probably violates
+ * the USB standard in this regard, as all USB devices are required to
+ * support Suspend. The remote wakeup feature is parsed and correctly
+ * handled in the protocol, but of course does nothing since the
+ * device never suspends.
+ */
+
+#define ALLOCATE_EXTERN
+#include "fx2regs.h"
+#include "fx2.h"
+
+// If Rwuen_allowed is TRUE, the device allows the remote wakeup
+// feature to be set by the host. If the host sets the feature, Rwuen
+// becomes TRUE but nothing else is done. If Rwuen_allowed is FALSE,
+// the device will signal an error on an attempt to set remote wakeup.
+
+BOOL Rwuen_allowed = FALSE; // Allow remote wakeup to be enabled
+BOOL Rwuen = FALSE; // Remote wakeup enable
+BOOL Selfpwr = FALSE; // Device is (not) self-powered
+
+// USB allows a device to support multiple configurations, only one of
+// which can be active at any given time. Each configuration can have
+// multiple interfaces, all of which can be active simultaneously, and
+// each interface can also have a setting. This driver only uses a
+// single configuration with a single interface, which has a single
+// setting, but these variables are here as place holders in case you
+// want to make the driver more sophisticated.
+
+#define NUM_INTERFACES 1
+
+BYTE Configuration; // Current device configuration
+BYTE InterfaceSetting[NUM_INTERFACES]; // Current interface settings
+
+// this table is used by the epcs macro
+const char code EPCS_Offset_Lookup_Table[] =
+{
+ 0, // EP1OUT
+ 1, // EP1IN
+ 2, // EP2OUT
+ 2, // EP2IN
+ 3, // EP4OUT
+ 3, // EP4IN
+ 4, // EP6OUT
+ 4, // EP6IN
+ 5, // EP8OUT
+ 5, // EP8IN
+};
+
+// macro for generating the address of an endpoint's control and status register (EPnCS)
+#define epcs(EP) (EPCS_Offset_Lookup_Table[(EP & 0x7E) | (EP > 128)] + 0xE6A1)
+
+
+// Read TRM 15.14 for an explanation of which commands need this.
+//
+// nop's take 4 clock cyles. A single nop is sufficient for both the
+// default setup (48 MHz CPU and interface clock) and this program's
+// setup (12 MHz CPU and 48 MHz interface clocks).
+
+#define NOP _asm nop _endasm
+#define SYNCDELAY NOP;
+
+
+// USB string descriptors are constructed from this array. Indices
+// into this array can be placed into the other descriptors to specify
+// manufacturer name, serial number, etc. Index 0 is reserved for a
+// list of language codes that this program currently ignores, but in
+// principle you can switch between different string tables based on
+// the language requested by the host.
+//
+// The wire format is specified in 16-bit Unicode. I just use ASCII
+// here and add zero bytes when I construct the string descriptor. If
+// you actually want to specify Unicode here, disable the code that
+// doubles up these bytes with zeros.
+//
+// Also, since I build the string descriptors directly in the EP0
+// output buffer, I'm limited to 31 character strings (64 byte packet;
+// 2 char overhead; 16 bits per char). If this is a problem, I'd
+// suggest allocating a block of memory for a longer string descriptor
+// (just like the other descriptors below), building the string
+// descriptors there, then transferring them using the same SUDPTR
+// technique used for the other descriptors, which can handle larger
+// descriptors and breaks them up automatically into small packets.
+
+char * USB_strings[] = { "EN", "WieserLabs & freesoft.org", "FX2 case converter" };
+
+// Descriptors are a real pain since Device and Configuration
+// descriptors have to be word-aligned (this is an FX2 requirement),
+// but Interface and Endpoint descriptors can't be word aligned - they
+// have directly follow their corresponding Configuration descriptor.
+// 'sdcc' provides no facility for structure alignment anyway, so I
+// just hardwire the addresses towards the end of the FX2's 16K RAM.
+//
+// This code will break if you try it on an 8K FX2. Sigh.
+//
+// I use the DSCR_OFFSET macro both to simplify the address
+// calculations and to figure what value goes into the third field of
+// the Configuration descriptor.
+
+#define DSCR_OFFSET(intrfc, endpnt) (sizeof(CONFIGDSCR) + \
+ intrfc*sizeof(INTRFCDSCR) + endpnt*sizeof(ENDPNTDSCR))
+
+DEVICEDSCR xdata at 0x3d00 myDeviceDscr = {
+ sizeof(DEVICEDSCR), // Descriptor length
+ DEVICE_DSCR, // Descriptor type
+ 0x200, // USB spec version 2.00
+ 0, // Device class
+ 0, // Device sub-class
+ 0, // Device sub-sub-class
+ 64, // Max packet size for EP0 (bytes)
+ 0x1199, // Vendor ID
+ 0x0017, // Product ID
+ 0x0100, // Product version (1.00)
+ 1, // Manufacturer string index
+ 2, // Product string index
+ 0, // Serial number string index
+ 1 // Number of configurations
+};
+
+// In theory, this descriptor returns information about the "other"
+// speed. So, if we're operating at high speed, the Device descriptor
+// would contain high speed configuration information and this
+// descriptor would contain full speed information, and vice versa if
+// we're operating at full speed. I take a simpler approach - the
+// configuration information is the same for both speeds, so we never
+// care which one is which.
+
+DEVICEQUALDSCR xdata at 0x3d20 myDeviceQualDscr = {
+ sizeof(DEVICEQUALDSCR), // Descriptor length
+ DEVQUAL_DSCR, // Descriptor type
+ 0x200, // USB spec version 2.00
+ 0, // Device class
+ 0, // Device sub-class
+ 0, // Device sub-sub-class
+ 64, // Max packet size for EP0 (bytes)
+ 1 // Number of alternate configurations
+};
+
+// Likewise, we should another full set of these configuration
+// descriptors. In this case, however, the structures are identical
+// and the few fields that differ (descriptor type and endpoint max
+// packet size) can be tweaked at run-time, so this next set of
+// descriptors does double duty as both Configuration and Other Speed
+// Configuration descriptors.
+
+CONFIGDSCR xdata at 0x3d30 myConfigDscr = {
+ sizeof(CONFIGDSCR), // Descriptor length
+ CONFIG_DSCR, // Descriptor Type
+ DSCR_OFFSET(1,2), // Total len of (config + intrfcs + end points)
+ 1, // Number of interfaces supported
+ 1, // Configuration index for SetConfiguration()
+ 0, // Config descriptor string index
+ bmBUSPWR|bmRWU, // Attributes
+ 0x1E // Max power consumption; 2*30 = 60 mA
+};
+
+INTRFCDSCR xdata at 0x3d30+DSCR_OFFSET(0,0) myIntrfcDscr = {
+ sizeof(INTRFCDSCR), // Descriptor length
+ INTRFC_DSCR, // Descriptor type
+ 0, // Index of this interface (zero based)
+ 0, // Value used to select alternate
+ 2, // Number of endpoints
+ 0xFF, // Class Code
+ 0xFF, // Subclass Code
+ 0xFF, // Protocol Code
+ 0 // Index of interface string description
+};
+
+ENDPNTDSCR xdata at 0x3d30+DSCR_OFFSET(1,0) myInEndpntDscr = {
+ sizeof(ENDPNTDSCR), // Descriptor length
+ ENDPNT_DSCR, // Descriptor type
+ 0x86, // Address of endpoint
+ EP_BULK, // Endpoint type
+ 512, // Maximum packet size
+ 0 // Interrupt polling interval
+ // (ignored for bulk endpoints)
+};
+
+ENDPNTDSCR xdata at 0x3d30+DSCR_OFFSET(1,1) myOutEndpntDscr = {
+ sizeof(ENDPNTDSCR), // Descriptor length
+ ENDPNT_DSCR, // Descriptor type
+ 0x02, // Address of endpoint
+ EP_BULK, // Endpoint type
+ 512, // Maximum packet size
+ 0 // Interrupt polling interval
+ // (ignored for bulk endpoints)
+};
+
+//-----------------------------------------------------------------------------
+// Endpoint 0 Device Request handler
+//-----------------------------------------------------------------------------
+
+static int count_array_size(void ** array)
+{
+ int size;
+ for (size=0; *array != 0; array++, size++);
+ return size;
+}
+
+static void SetupCommand(void)
+{
+ int i;
+ int interface;
+
+ // Errors are signaled by stalling endpoint 0.
+
+ switch(SETUPDAT[0] & SETUP_MASK) {
+
+ case SETUP_STANDARD_REQUEST:
+ switch(SETUPDAT[1])
+ {
+ case SC_GET_DESCRIPTOR:
+ switch(SETUPDAT[3])
+ {
+ case GD_DEVICE:
+ SUDPTRH = MSB(&myDeviceDscr);
+ SUDPTRL = LSB(&myDeviceDscr);
+ break;
+ case GD_DEVICE_QUALIFIER:
+ SUDPTRH = MSB(&myDeviceQualDscr);
+ SUDPTRL = LSB(&myDeviceQualDscr);
+ break;
+ case GD_CONFIGURATION:
+ myConfigDscr.type = CONFIG_DSCR;
+ if (USBCS & bmHSM) {
+ // High speed parameters
+ myInEndpntDscr.mp = 512;
+ myOutEndpntDscr.mp = 512;
+ } else {
+ // Full speed parameters
+ myInEndpntDscr.mp = 64;
+ myOutEndpntDscr.mp = 64;
+ }
+ SUDPTRH = MSB(&myConfigDscr);
+ SUDPTRL = LSB(&myConfigDscr);
+ break;
+ case GD_OTHER_SPEED_CONFIGURATION:
+ myConfigDscr.type = OTHERSPEED_DSCR;
+ if (USBCS & bmHSM) {
+ // We're in high speed mode, this is the Other
+ // descriptor, so these are full speed parameters
+ myInEndpntDscr.mp = 64;
+ myOutEndpntDscr.mp = 64;
+ } else {
+ // We're in full speed mode, this is the Other
+ // descriptor, so these are high speed parameters
+ myInEndpntDscr.mp = 512;
+ myOutEndpntDscr.mp = 512;
+ }
+ SUDPTRH = MSB(&myConfigDscr);
+ SUDPTRL = LSB(&myConfigDscr);
+ break;
+ case GD_STRING:
+ if (SETUPDAT[2] >= count_array_size((void **) USB_strings)) {
+ EZUSB_STALL_EP0();
+ } else {
+ for (i=0; i<31; i++) {
+ if (USB_strings[SETUPDAT[2]][i] == '\0') break;
+ EP0BUF[2*i+2] = USB_strings[SETUPDAT[2]][i];
+ EP0BUF[2*i+3] = '\0';
+ }
+ EP0BUF[0] = 2*i+2;
+ EP0BUF[1] = STRING_DSCR;
+ SYNCDELAY; EP0BCH = 0;
+ SYNCDELAY; EP0BCL = 2*i+2;
+ }
+ break;
+ default: // Invalid request
+ EZUSB_STALL_EP0();
+ }
+ break;
+ case SC_GET_INTERFACE:
+ interface = SETUPDAT[4];
+ if (interface < NUM_INTERFACES) {
+ EP0BUF[0] = InterfaceSetting[interface];
+ EP0BCH = 0;
+ EP0BCL = 1;
+ }
+ break;
+ case SC_SET_INTERFACE:
+ interface = SETUPDAT[4];
+ if (interface < NUM_INTERFACES) {
+ InterfaceSetting[interface] = SETUPDAT[2];
+ }
+ break;
+ case SC_SET_CONFIGURATION:
+ Configuration = SETUPDAT[2];
+ break;
+ case SC_GET_CONFIGURATION:
+ EP0BUF[0] = Configuration;
+ EP0BCH = 0;
+ EP0BCL = 1;
+ break;
+ case SC_GET_STATUS:
+ switch(SETUPDAT[0])
+ {
+ case GS_DEVICE:
+ EP0BUF[0] = ((BYTE)Rwuen << 1) | (BYTE)Selfpwr;
+ EP0BUF[1] = 0;
+ EP0BCH = 0;
+ EP0BCL = 2;
+ break;
+ case GS_INTERFACE:
+ EP0BUF[0] = 0;
+ EP0BUF[1] = 0;
+ EP0BCH = 0;
+ EP0BCL = 2;
+ break;
+ case GS_ENDPOINT:
+ EP0BUF[0] = *(BYTE xdata *) epcs(SETUPDAT[4]) & bmEPSTALL;
+ EP0BUF[1] = 0;
+ EP0BCH = 0;
+ EP0BCL = 2;
+ break;
+ default: // Invalid Command
+ EZUSB_STALL_EP0();
+ }
+ break;
+ case SC_CLEAR_FEATURE:
+ switch(SETUPDAT[0])
+ {
+ case FT_DEVICE:
+ if(SETUPDAT[2] == 1)
+ Rwuen = FALSE; // Disable Remote Wakeup
+ else
+ EZUSB_STALL_EP0();
+ break;
+ case FT_ENDPOINT:
+ if(SETUPDAT[2] == 0)
+ {
+ *(BYTE xdata *) epcs(SETUPDAT[4]) &= ~bmEPSTALL;
+ EZUSB_RESET_DATA_TOGGLE( SETUPDAT[4] );
+ }
+ else
+ EZUSB_STALL_EP0();
+ break;
+ }
+ break;
+ case SC_SET_FEATURE:
+ switch(SETUPDAT[0])
+ {
+ case FT_DEVICE:
+ if((SETUPDAT[2] == 1) && Rwuen_allowed)
+ Rwuen = TRUE; // Enable Remote Wakeup
+ else if(SETUPDAT[2] == 2)
+ // Set Feature Test Mode. The core handles this
+ // request. However, it is necessary for the
+ // firmware to complete the handshake phase of the
+ // control transfer before the chip will enter test
+ // mode. It is also necessary for FX2 to be
+ // physically disconnected (D+ and D-) from the host
+ // before it will enter test mode.
+ break;
+ else
+ EZUSB_STALL_EP0();
+ break;
+ case FT_ENDPOINT:
+ *(BYTE xdata *) epcs(SETUPDAT[4]) |= bmEPSTALL;
+ break;
+ default:
+ EZUSB_STALL_EP0();
+ }
+ break;
+ default: // *** Invalid Command
+ EZUSB_STALL_EP0();
+ break;
+ }
+ break;
+
+ default:
+ EZUSB_STALL_EP0();
+ break;
+ }
+
+ // Acknowledge handshake phase of device request
+ EP0CS |= bmHSNAK;
+}
+
+static void USB_isr(void) __interrupt 8
+{
+ // Clear global USB IRQ
+ EXIF &= ~0x10;
+
+ // Clear SUDAV IRQ
+ USBIRQ = 0x01;
+
+ SetupCommand();
+}
+
+//-----------------------------------------------------------------------------
+// Main program
+//-----------------------------------------------------------------------------
+
+static void Initialize(void)
+{
+ // Note that increasing the clock speed to 24 or 48 MHz would
+ // affect our timer calculations below. I use 12 MHz because
+ // this lets me use the smallest numbers for our counter (i.e,
+ // 40000 for the default 40 ms latency); the counter is only
+ // sixteen bits.
+
+ //IFCONFIG=0xc0; // Internal IFCLK, 48MHz; A,B as normal ports.
+ IFCONFIG=0xcb; // slave ports
+ SYNCDELAY;
+
+ REVCTL=0x03; // See TRM...
+ SYNCDELAY;
+
+ EP1OUTCFG=0;
+ EP1INCFG=0;
+ EP4CFG=0;
+ EP8CFG=0;
+
+ // Set up EP2 and EP6 as quad-buffered, 512 bytes per buffer, bulk.
+ EP6CFG=0xe0; // 1110 0000 (IN)
+ EP2CFG=0xa0; // 1010 0000 (OUT)
+
+ // To be sure, clear and reset all FIFOs although
+ // this is probably not strictly required.
+ FIFORESET = 0x80; SYNCDELAY; // NAK all requests from host.
+ FIFORESET = 0x82; SYNCDELAY; // Reset individual EP (2,4,6,8)
+ FIFORESET = 0x84; SYNCDELAY;
+ FIFORESET = 0x86; SYNCDELAY;
+ FIFORESET = 0x88; SYNCDELAY;
+ FIFORESET = 0x80; SYNCDELAY; // NAK all requests from host.
+ FIFORESET = 0x00; SYNCDELAY; // Resume normal operation.
+
+ // Flush input and output quad-buffers.
+ OUTPKTEND = 0x82; SYNCDELAY;
+ OUTPKTEND = 0x82; SYNCDELAY;
+ OUTPKTEND = 0x82; SYNCDELAY;
+
+ INPKTEND = 0x86; SYNCDELAY;
+ INPKTEND = 0x86; SYNCDELAY;
+ INPKTEND = 0x86; SYNCDELAY;
+
+ /* EP6FIFOCFG: */
+ // bit7: 0
+ // bit6: INFM6 See TRM 15-29 (p.351): Signal line one clock earlier.
+ // bit5: OEP6
+ // bit4: AUTOOUT 1 = enable
+ // bit3: AUTOIN 1 = enable
+ // bit2: ZEROLENIN 1 = enable (?)
+ // bit1: 0
+ // bit0: WORDWIDE 1 = 16bit (default)
+ //EP2FIFOCFG = 0; SYNCDELAY;
+ //EP6FIFOCFG = 0; SYNCDELAY;
+ EP2FIFOCFG = 0xC; SYNCDELAY;
+ EP6FIFOCFG = 0xC; SYNCDELAY;
+
+ // Setup Data Pointer - AUTO mode
+ //
+ // In this mode, there are two ways to send data on EP0. You
+ // can either copy the data into EP0BUF and write the packet
+ // length into EP0BCH/L to start the transfer, or you can
+ // write the (word-aligned) address of a USB descriptor into
+ // SUDPTRH/L; the length is computed automatically.
+ SUDPTRCTL = 1;
+
+ // Enable USB interrupt
+ IE = 0x80;
+ EIE = 0x01;
+
+ // Enable SUDAV (setup data available) interrupt
+ USBIE = 0x01;
+}
+
+
+// We want to buffer any outgoing data for a short time (40 ms) to see
+// if any other data becomes available and it can all be sent
+// together. At 12 MHz we consume 83.3 ns/cycle and divide this rate
+// by 12 so that our counters increment almost exactly once every us.
+// The counter is sixteen bits, so we can specify latencies up to
+// about 65 ms.
+
+unsigned int bytes_waiting_for_xmit = 0;
+unsigned int latency_us = 40000;
+
+
+static void ProcessXmitData(void)
+{
+ // reset Timer 0
+ TCON &= ~0x30;
+
+ SYNCDELAY;
+
+ // Send the packet.
+ EP6BCH = MSB(bytes_waiting_for_xmit);
+ EP6BCL = LSB(bytes_waiting_for_xmit);
+
+ bytes_waiting_for_xmit = 0;
+}
+
+
+static void putchar(char c)
+{
+ xdata unsigned char *dest=EP6FIFOBUF + bytes_waiting_for_xmit;
+
+ // Wait for EP6 buffer to become non-full so that we don't
+ // overwrite content.
+ while(EP6CS & (1<<3));
+
+ *dest = c;
+ ++bytes_waiting_for_xmit;
+
+ // Either send 64 byte packets or send 512 byte packets.
+ // Concerning the data, there is no difference under linux.
+ if (bytes_waiting_for_xmit >= 512 ) ProcessXmitData();
+
+ // Set Timer 0 if it isn't set and we've got data ready to go
+ if (bytes_waiting_for_xmit && !(TCON & 0x10)) {
+ TH0 = MSB(0xffff - latency_us);
+ TL0 = LSB(0xffff - latency_us);
+ TCON |= 0x10;
+ }
+}
+
+
+static void ProcessRecvData(void)
+{
+ xdata const unsigned char *src=EP2FIFOBUF;
+ int len = (((int)EP2BCH)<<8) | EP2BCL;
+ int i;
+
+ for(i=0; i<len; i++,src++)
+ {
+ if(*src>='a' && *src<='z')
+ { putchar(*src-'a'+'A'); }
+ else
+ { putchar(*src); }
+ }
+
+ // "Skip" the received OUT packet to "forget" it (see TRM p. 9-26):
+ SYNCDELAY;
+ OUTPKTEND=0x82;
+}
+
+
+void main(void)
+{
+ // Disconnect the USB interface, initialize, renumerate, reconnect
+ USBCS |= 0x08;
+ Initialize();
+ USBCS |= 0x02;
+ USBCS &= ~(0x08);
+
+ // Configure Timer 0 (but leave it unset)
+ // mode 1 (16-bit); ungated; divide system clock by 12
+ CKCO &= ~(0x08);
+ TMOD = 0x01;
+ TCON &= ~0x30;
+
+ for(;;)
+ {
+ // Input data on EP2
+ if(!(EP2CS & (1<<2)))
+ {
+ //ProcessRecvData();
+ }
+
+ // Timer expiration; send buffered data
+ if((TCON & 0x20))
+ {
+ //ProcessXmitData();
+ }
+ }
+}
diff --git a/hdl/eb_usb_core/fx2.h b/hdl/eb_usb_core/fx2.h
new file mode 100644
index 0000000..ad99ad6
--- /dev/null
+++ b/hdl/eb_usb_core/fx2.h
@@ -0,0 +1,380 @@
+/*
+//-----------------------------------------------------------------------------
+// File: FX2.h
+// Contents: EZ-USB FX2 constants, macros, datatypes, globals, and library
+// function prototypes.
+//
+// Copyright (c) 2000 Cypress Semiconductor, All rights reserved
+//
+// Modified to be used with the sdcc compiler.
+//
+//-----------------------------------------------------------------------------
+*/
+#ifndef FX2_H //Header sentry
+#define FX2_H
+
+#include "fx2regs.h"
+
+
+#define INTERNAL_DSCR_ADDR 0x0080 // Relocate Descriptors to 0x80
+#define bmSTRETCH 0x07
+#define FW_STRETCH_VALUE 0x0 // Set stretch to 0 in frameworks
+ // Note: a RevE eratta states that stretch must=0 to set OUTxBC
+
+/*
+//-----------------------------------------------------------------------------
+// Constants
+//-----------------------------------------------------------------------------
+*/
+#define TRUE 1
+#define FALSE 0
+
+#define DEVICE_DSCR 0x01 // Descriptor type: Device
+#define CONFIG_DSCR 0x02 // Descriptor type: Configuration
+#define STRING_DSCR 0x03 // Descriptor type: String
+#define INTRFC_DSCR 0x04 // Descriptor type: Interface
+#define ENDPNT_DSCR 0x05 // Descriptor type: End Point
+#define DEVQUAL_DSCR 0x06 // Descriptor type: Device Qualifier
+#define OTHERSPEED_DSCR 0x07 // Descriptor type: Other Speed Configuration
+
+#define bmBUSPWR bmBIT7 // Config. attribute: Bus powered
+#define bmSELFPWR bmBIT6 // Config. attribute: Self powered
+#define bmRWU bmBIT5 // Config. attribute: Remote Wakeup
+
+#define bmEPOUT bmBIT7
+#define bmEPIN 0x00
+
+#define EP_CONTROL 0x00 // End Point type: Control
+#define EP_ISO 0x01 // End Point type: Isochronous
+#define EP_BULK 0x02 // End Point type: Bulk
+#define EP_INT 0x03 // End Point type: Interrupt
+
+#define SUD_SIZE 8 // Setup data packet size
+
+/*
+//////////////////////////////////////////////////////////////////////////////
+//Added for HID
+*/
+
+#define SETUP_MASK 0x60 //Used to mask off request type
+#define SETUP_STANDARD_REQUEST 0 //Standard Request
+#define SETUP_CLASS_REQUEST 0x20 //Class Request
+#define SETUP_VENDOR_REQUEST 0x40 //Vendor Request
+#define SETUP_RESERVED_REQUEST 0x60 //Reserved or illegal request
+
+/*
+//////////////////////////////////////////////////////////////////////////////
+*/
+
+
+#define SC_GET_STATUS 0x00 // Setup command: Get Status
+#define SC_CLEAR_FEATURE 0x01 // Setup command: Clear Feature
+#define SC_RESERVED 0x02 // Setup command: Reserved
+#define SC_SET_FEATURE 0x03 // Setup command: Set Feature
+#define SC_SET_ADDRESS 0x05 // Setup command: Set Address
+#define SC_GET_DESCRIPTOR 0x06 // Setup command: Get Descriptor
+#define SC_SET_DESCRIPTOR 0x07 // Setup command: Set Descriptor
+#define SC_GET_CONFIGURATION 0x08 // Setup command: Get Configuration
+#define SC_SET_CONFIGURATION 0x09 // Setup command: Set Configuration
+#define SC_GET_INTERFACE 0x0a // Setup command: Get Interface
+#define SC_SET_INTERFACE 0x0b // Setup command: Set Interface
+#define SC_SYNC_FRAME 0x0c // Setup command: Sync Frame
+#define SC_ANCHOR_LOAD 0xa0 // Setup command: Anchor load
+
+#define GD_DEVICE 0x01 // Get descriptor: Device
+#define GD_CONFIGURATION 0x02 // Get descriptor: Configuration
+#define GD_STRING 0x03 // Get descriptor: String
+#define GD_INTERFACE 0x04 // Get descriptor: Interface
+#define GD_ENDPOINT 0x05 // Get descriptor: Endpoint
+#define GD_DEVICE_QUALIFIER 0x06 // Get descriptor: Device Qualifier
+#define GD_OTHER_SPEED_CONFIGURATION 0x07 // Get descriptor: Other Configuration
+#define GD_INTERFACE_POWER 0x08 // Get descriptor: Interface Power
+#define GD_HID 0x21 // Get descriptor: HID
+#define GD_REPORT 0x22 // Get descriptor: Report
+
+#define GS_DEVICE 0x80 // Get Status: Device
+#define GS_INTERFACE 0x81 // Get Status: Interface
+#define GS_ENDPOINT 0x82 // Get Status: End Point
+
+#define FT_DEVICE 0x00 // Feature: Device
+#define FT_ENDPOINT 0x02 // Feature: End Point
+
+#define I2C_IDLE 0 // I2C Status: Idle mode
+#define I2C_SENDING 1 // I2C Status: I2C is sending data
+#define I2C_RECEIVING 2 // I2C Status: I2C is receiving data
+#define I2C_PRIME 3 // I2C Status: I2C is receiving the first byte of a string
+#define I2C_STOP 5 // I2C Status: I2C waiting for stop completion
+#define I2C_BERROR 6 // I2C Status: I2C error; Bit Error
+#define I2C_NACK 7 // I2C Status: I2C error; No Acknowledge
+#define I2C_OK 8 // I2C positive return code
+#define I2C_WAITSTOP 9 // I2C Status: Wait for STOP complete
+
+/*-----------------------------------------------------------------------------
+ Macros
+-----------------------------------------------------------------------------*/
+
+#define MSB(word) (BYTE)(((WORD)(word) >> 8) & 0xff)
+#define LSB(word) (BYTE)((WORD)(word) & 0xff)
+
+#define SWAP_ENDIAN(word) ((BYTE*)&word)[0] ^= ((BYTE*)&word)[1]; ((BYTE*)&word)[1] ^= ((BYTE*)&word)[0]; ((BYTE*)&word)[0] ^= ((BYTE*)&word)[1]
+
+#define EZUSB_IRQ_ENABLE() EUSB = 1
+#define EZUSB_IRQ_DISABLE() EUSB = 0
+#define EZUSB_IRQ_CLEAR() EXIF &= ~0x10 // IE2_
+
+#define EZUSB_STALL_EP0() EP0CS |= bmEPSTALL
+#define EZUSB_STALL_EP(ep_id) // fx2bug
+#define EZUSB_UNSTALL_EP(ep_id) // fx2bug
+#define EZUSB_GET_EP_STATUS(ep_id) // fx2bug
+#define EZUSB_SET_EP_BYTES(ep_id,count) // fx2bug
+
+
+/*
+// WRITEDELAY() has been replaced by SYNCDELAY; macro in fx2sdly.h
+// ...it is here for backwards compatibility...
+
+// the WRITEDELAY macro compiles to the time equivalent of 3 NOPs.
+// It is used in the frameworks to allow for write recovery time
+// requirements of certain registers. This is only necessary for
+// EZ-USB FX parts. See the EZ-USB FX TRM for
+// more information on write recovery time issues.
+*/
+#define WRITEDELAY() {char writedelaydummy = 0;}
+/*
+// if this firmware will never run on an EZ-USB FX part replace
+// with:
+// #define WRITEDELAY()
+*/
+
+/*
+// macro to reset and endpoint data toggle
+*/
+#define EZUSB_RESET_DATA_TOGGLE(ep) TOGCTL = (((ep & 0x80) >> 3) + (ep & 0x0F)); TOGCTL |= bmRESETTOGGLE
+
+
+#define EZUSB_ENABLE_RSMIRQ() (EICON |= 0x20) // Enable Resume Interrupt (EPFI_)
+#define EZUSB_DISABLE_RSMIRQ() (EICON &= ~0x20) // Disable Resume Interrupt (EPFI_)
+#define EZUSB_CLEAR_RSMIRQ() (EICON &= ~0x10) // Clear Resume Interrupt Flag (PFI_)
+
+#define EZUSB_GETI2CSTATUS() (I2CPckt.status)
+#define EZUSB_CLEARI2CSTATUS() if((I2CPckt.status == I2C_BERROR) || (I2CPckt.status == I2C_NACK)) I2CPckt.status = I2C_IDLE;
+
+#define EZUSB_ENABLEBP() (BREAKPT |= bmBPEN) // TGE fx2bug
+#define EZUSB_DISABLEBP() (BREAKPT &= ~bmBPEN) // TGE fx2bug
+#define EZUSB_CLEARBP() (BREAKPT |= bmBREAK) // TGE fx2bug
+#define EZUSB_BP(addr) BPADDRH = (BYTE)(((WORD)addr >> 8) & 0xff); BPADDRL = (BYTE)addr // TGE fx2bug
+
+#define EZUSB_EXTWAKEUP() (((WAKEUPCS & bmWU2) && (WAKEUPCS & bmWU2EN)) || ((WAKEUPCS & bmWU) && (WAKEUPCS & bmWUEN)))
+
+#define EZUSB_HIGHSPEED() (USBCS & bmHSM)
+
+/*
+//-----------------------------------------------------------------------------
+// Datatypes
+//-----------------------------------------------------------------------------
+*/
+//typedef unsigned char BYTE; -> already typedef'ed in fx2regs.h
+//typedef unsigned short WORD; -> already typedef'ed in fx2regs.h
+typedef unsigned long DWORD;
+typedef bit BOOL;
+
+#define INT0_VECT 0
+#define TMR0_VECT 1
+#define INT1_VECT 2
+#define TMR1_VECT 3
+#define COM0_VECT 4
+#define TMR2_VECT 5
+#define WKUP_VECT 6
+#define COM1_VECT 7
+#define USB_VECT 8
+#define I2C_VECT 9
+#define INT4_VECT 10
+#define INT5_VECT 11
+#define INT6_VECT 12
+
+
+/*
+// TGE fx2bug
+*/
+#define SUDAV_USBVECT (0 << 2)
+#define SOF_USBVECT (1 << 2)
+#define SUTOK_USBVECT (2 << 2)
+#define SUSP_USBVECT (3 << 2)
+#define URES_USBVECT (4 << 2)
+#define HS_USBVECT (5 << 2)
+#define EP0ACK_USBVECT (6 << 2)
+#define SPARE0_USBVECT (7 << 2)
+#define IN0BUF_USBVECT (8 << 2)
+#define OUT0BUF_USBVECT (9 << 2)
+#define IN1BUF_USBVECT (10 << 2)
+#define OUT1BUF_USBVECT (11 << 2)
+#define INOUT2BUF_USBVECT (12 << 2)
+#define INOUT4BUF_USBVECT (13 << 2)
+#define INOUT6BUF_USBVECT (14 << 2)
+#define INOUT8BUF_USBVECT (15 << 2)
+#define IBN_USBVECT (16 << 2)
+#define SPARE1_USBVECT (17 << 2)
+#define EP0PINGNAK_USBVECT (18 << 2)
+#define EP1PINGNAK_USBVECT (19 << 2)
+#define EP2PINGNAK_USBVECT (20 << 2)
+#define EP4PINGNAK_USBVECT (21 << 2)
+#define EP6PINGNAK_USBVECT (22 << 2)
+#define EP8PINGNAK_USBVECT (23 << 2)
+#define ERRLIM_USBVECT (24 << 2)
+#define SPARE2_USBVECT (25 << 2)
+#define SPARE3_USBVECT (26 << 2)
+#define SPARE4_USBVECT (27 << 2)
+#define EP2PIDERR_USBVECT (28 << 2)
+#define EP4PIDERR_USBVECT (29 << 2)
+#define EP6PIDERR_USBVECT (30 << 2)
+#define EP8PIDERR_USBVECT (31 << 2)
+
+typedef struct
+{
+ BYTE length;
+ BYTE type;
+}DSCR;
+
+typedef struct // Device Descriptor
+{
+ BYTE length; // Descriptor length ( = sizeof(DEVICEDSCR) )
+ BYTE type; // Decriptor type (Device = 1)
+ WORD spec_ver; // USB Specification Version (BCD)
+ BYTE dev_class; // Device class
+ BYTE sub_class; // Device sub-class
+ BYTE protocol; // Device sub-sub-class
+ BYTE max_packet; // Maximum packet size
+ WORD vendor_id; // Vendor ID
+ WORD product_id; // Product ID
+ WORD version_id; // Product version ID
+ BYTE mfg_str; // Manufacturer string index
+ BYTE prod_str; // Product string index
+ BYTE serialnum_str; // Serial number string index
+ BYTE configs; // Number of configurations
+}DEVICEDSCR;
+
+typedef struct // Device Qualifier Descriptor
+{
+ BYTE length; // Descriptor length ( = sizeof(DEVICEQUALDSCR) )
+ BYTE type; // Decriptor type (Device Qualifier = 6)
+ WORD spec_ver; // Specification Version (BCD) minor
+ BYTE dev_class; // Device class
+ BYTE sub_class; // Device sub-class
+ BYTE protocol; // Device sub-sub-class
+ BYTE max_packet; // Maximum packet size
+ BYTE configs; // Number of configurations
+ BYTE reserved0;
+}DEVICEQUALDSCR;
+
+typedef struct
+{
+ BYTE length; // Configuration length ( = sizeof(CONFIGDSCR) )
+ BYTE type; // Descriptor type (Configuration = 2)
+ WORD config_len; // Configuration + End Points length
+ BYTE interfaces; // Number of interfaces
+ BYTE index; // Configuration number
+ BYTE config_str; // Configuration string
+ BYTE attrib; // Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu
+ BYTE power; // Power requirement (div 2 ma)
+}CONFIGDSCR;
+
+typedef struct
+{
+ BYTE length; // Interface descriptor length ( - sizeof(INTRFCDSCR) )
+ BYTE type; // Descriptor type (Interface = 4)
+ BYTE index; // Zero-based index of this interface
+ BYTE alt_setting; // Alternate setting
+ BYTE ep_cnt; // Number of end points
+ BYTE class; // Interface class
+ BYTE sub_class; // Interface sub class
+ BYTE protocol; // Interface sub sub class
+ BYTE interface_str; // Interface descriptor string index
+}INTRFCDSCR;
+
+typedef struct
+{
+ BYTE length; // End point descriptor length ( = sizeof(ENDPNTDSCR) )
+ BYTE type; // Descriptor type (End point = 5)
+ BYTE addr; // End point address
+ BYTE ep_type; // End point type
+ WORD mp; // Maximum packet size
+ BYTE interval; // Interrupt polling interval
+}ENDPNTDSCR;
+
+typedef struct
+{
+ BYTE length; // String descriptor length
+ BYTE type; // Descriptor type
+}STRINGDSCR;
+
+typedef struct
+{
+ BYTE cntrl; // End point control register
+ BYTE bytes; // End point buffer byte count
+}EPIOC;
+
+typedef struct
+{
+ BYTE length;
+ BYTE *dat;
+ BYTE count;
+ BYTE status;
+}I2CPCKT;
+
+/*
+//-----------------------------------------------------------------------------
+// Globals
+//-----------------------------------------------------------------------------
+*/
+extern code BYTE USB_AutoVector;
+
+extern WORD pDeviceDscr;
+extern WORD pDeviceQualDscr;
+extern WORD pHighSpeedConfigDscr;
+extern WORD pFullSpeedConfigDscr;
+extern WORD pConfigDscr;
+extern WORD pOtherConfigDscr;
+extern WORD pStringDscr;
+
+extern code DEVICEDSCR DeviceDscr;
+extern code DEVICEQUALDSCR DeviceQualDscr;
+extern code CONFIGDSCR HighSpeedConfigDscr;
+extern code CONFIGDSCR FullSpeedConfigDscr;
+extern code STRINGDSCR StringDscr;
+extern code DSCR UserDscr;
+
+extern I2CPCKT volatile I2CPckt;
+
+/*
+//-----------------------------------------------------------------------------
+// Function Prototypes
+//-----------------------------------------------------------------------------
+// fx2bug #ifdef CHIPREV_B
+// fx2bug extern void EZUSB_IRQ_CLEAR(void);
+// fx2bug #endif
+*/
+
+extern void EZUSB_Renum(void);
+extern void EZUSB_Discon(BOOL renum);
+
+extern void EZUSB_Susp(void);
+extern void EZUSB_Resume(void);
+
+extern void EZUSB_Delay1ms(void);
+extern void EZUSB_Delay(WORD ms);
+
+extern CONFIGDSCR xdata* EZUSB_GetConfigDscr(BYTE ConfigIdx);
+extern INTRFCDSCR xdata* EZUSB_GetIntrfcDscr(BYTE ConfigIdx, BYTE IntrfcIdx, BYTE AltSetting);
+extern STRINGDSCR xdata* EZUSB_GetStringDscr(BYTE StrIdx);
+extern DSCR xdata* EZUSB_GetDscr(BYTE index, DSCR* dscr, BYTE type);
+
+extern void EZUSB_InitI2C(void);
+extern BYTE EZUSB_WriteI2C_(BYTE addr, BYTE length, BYTE xdata *dat);
+extern BYTE EZUSB_ReadI2C_(BYTE addr, BYTE length, BYTE xdata *dat);
+extern BYTE EZUSB_WriteI2C(BYTE addr, BYTE length, BYTE xdata *dat);
+extern BYTE EZUSB_ReadI2C(BYTE addr, BYTE length, BYTE xdata *dat);
+extern void EZUSB_WaitForEEPROMWrite(BYTE addr);
+
+extern void modify_endpoint_stall(BYTE epid, BYTE stall);
+
+#endif // FX2_H
diff --git a/hdl/eb_usb_core/fx2regs.h b/hdl/eb_usb_core/fx2regs.h
new file mode 100644
index 0000000..fb03400
--- /dev/null
+++ b/hdl/eb_usb_core/fx2regs.h
@@ -0,0 +1,649 @@
+/*
+//-----------------------------------------------------------------------------
+// File: FX2regs.h
+// Contents: EZ-USB FX2 register declarations and bit mask definitions.
+//
+// $Archive: /USB/Target/Inc/fx2regs.h $
+// $Date: 2005/07/20 16:23:46 $
+// $Revision: 1.2 $
+//
+//
+// Copyright (c) 2000 Cypress Semiconductor, All rights reserved
+//-----------------------------------------------------------------------------
+*/
+
+#ifndef FX2REGS_H /* Header Sentry */
+#define FX2REGS_H
+
+/*
+//-----------------------------------------------------------------------------
+// FX2 Related Register Assignments
+//-----------------------------------------------------------------------------
+
+// The Ez-USB FX2 registers are defined here. We use FX2regs.h for register
+// address allocation by using "#define ALLOCATE_EXTERN".
+// When using "#define ALLOCATE_EXTERN", you get (for instance):
+// xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40;
+// Such lines are created from FX2.h by using the preprocessor.
+// Incidently, these lines will not generate any space in the resulting hex
+// file; they just bind the symbols to the addresses for compilation.
+// You just need to put "#define ALLOCATE_EXTERN" in your main program file;
+// i.e. fw.c or a stand-alone C source file.
+// Without "#define ALLOCATE_EXTERN", you just get the external reference:
+// extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40;
+// This uses the concatenation operator "##" to insert a comment "//"
+// to cut off the end of the line, "_at_ 0x7B40;", which is not wanted.
+*/
+
+#define ALLOCATE_EXTERN
+
+#ifdef ALLOCATE_EXTERN
+#define EXTERN
+#define _AT_(a) at a
+#else
+#define EXTERN extern
+#define _AT_ ;/ ## /
+#endif
+
+typedef unsigned char BYTE;
+typedef unsigned short WORD;
+
+EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA ;
+EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ;
+
+// General Configuration
+
+EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status
+EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration
+EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments
+EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments
+EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state
+EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint
+EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H
+EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L
+EXTERN xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2
+EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities
+EXTERN xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision
+EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control
+
+// Endpoint Configuration
+
+EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration
+EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration
+EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration
+EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration
+EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration
+EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration
+EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration
+EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration
+EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration
+EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration
+EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only)
+EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only)
+EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only)
+EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only)
+EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only)
+EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only)
+EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only)
+EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only)
+EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H
+EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L
+EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H
+EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L
+EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H
+EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L
+EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H
+EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L
+EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3)
+EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3)
+EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3)
+EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3)
+EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End
+EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End
+
+// Interrupts
+
+EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable
+EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request
+EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable
+EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request
+EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable
+EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request
+EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable
+EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request
+EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable
+EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request
+EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable
+EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request
+EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables
+EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests
+EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables
+EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests
+EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable
+EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request
+EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables
+EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests
+EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit
+EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0]
+EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector
+EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector
+EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup
+
+// Input/Output
+
+EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration
+EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration
+EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration
+EXTERN xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status
+EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data
+EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control
+EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access
+EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access
+
+#define EXTAUTODAT1 XAUTODAT1
+#define EXTAUTODAT2 XAUTODAT2
+
+// USB Control
+
+EXTERN xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status
+EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend
+EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity
+EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control
+EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H
+EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L
+EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7
+EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address
+
+// Endpoints
+
+EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H
+EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L
+EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count
+EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count
+EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H
+EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L
+EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H
+EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L
+EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H
+EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L
+EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H
+EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L
+EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status
+EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status
+EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status
+EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status
+EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status
+EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status
+EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status
+EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags
+EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags
+EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags
+EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags
+EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H
+EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L
+EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H
+EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L
+EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H
+EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L
+EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H
+EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L
+EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte
+EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte
+EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode
+EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data
+
+// GPIF
+
+EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector
+EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode
+EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states
+EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive
+EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H
+EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L
+
+EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3
+EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2
+EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1
+EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0
+
+#define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility
+#define EP2GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
+#define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility
+#define EP4GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
+#define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility
+#define EP6GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
+#define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility
+#define EP8GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
+
+// EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High
+// EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low
+EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select
+EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag
+EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger
+// EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High
+// EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low
+EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select
+EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag
+EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger
+// EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High
+// EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low
+EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select
+EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag
+EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger
+// EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High
+// EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low
+EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select
+EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag
+EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger
+EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only)
+EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac
+EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger
+EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG
+EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states
+EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles
+
+// UDMA
+
+EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state
+EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria
+EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state
+EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state
+EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ;
+EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe
+EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge
+EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe
+EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift
+EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte
+EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte
+EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only
+
+
+// Debug/Test
+
+EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug
+EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration
+EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes
+EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override
+EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM
+EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals
+EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs
+
+// Endpoint Buffers
+
+EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer
+EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer
+EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer
+EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT)
+EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT)
+EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT)
+EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT)
+
+#undef EXTERN
+#undef _AT_
+
+/*-----------------------------------------------------------------------------
+ Special Function Registers (SFRs)
+ The byte registers and bits defined in the following list are based
+ on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
+ If you modify the register definitions below, please regenerate the file
+ "ezregs.inc" which includes the same basic information for assembly inclusion.
+-----------------------------------------------------------------------------*/
+
+sfr at 0x80 IOA ;
+sfr at 0x81 SP ;
+sfr at 0x82 DPL ;
+sfr at 0x83 DPH ;
+sfr at 0x84 DPL1;
+sfr at 0x85 DPH1;
+sfr at 0x86 DPS ;
+ /* DPS */
+ // sbit SEL = 0x86+0;
+sfr at 0x87 PCON ;
+ /* PCON */
+ //sbit IDLE = 0x87+0;
+ //sbit STOP = 0x87+1;
+ //sbit GF0 = 0x87+2;
+ //sbit GF1 = 0x87+3;
+ //sbit SMOD0 = 0x87+7;
+sfr at 0x88 TCON;
+ /* TCON */
+/* sbit IT0 = 0x88+0;
+ sbit IE0 = 0x88+1;
+ sbit IT1 = 0x88+2;
+ sbit IE1 = 0x88+3;
+ sbit TR0 = 0x88+4;
+ sbit TF0 = 0x88+5;
+ sbit TR1 = 0x88+6;
+ sbit TF1 = 0x88+7;*/
+sfr at 0x89 TMOD;
+ /* TMOD */
+ //sbit M00 = 0x89+0;
+ //sbit M10 = 0x89+1;
+ //sbit CT0 = 0x89+2;
+ //sbit GATE0 = 0x89+3;
+ //sbit M01 = 0x89+4;
+ //sbit M11 = 0x89+5;
+ //sbit CT1 = 0x89+6;
+ //sbit GATE1 = 0x89+7;
+sfr at 0x8A TL0 ;
+sfr at 0x8B TL1 ;
+sfr at 0x8C TH0 ;
+sfr at 0x8D TH1 ;
+sfr at 0x8E CKCO;
+ /* CKCON */
+ //sbit MD0 = 0x89+0;
+ //sbit MD1 = 0x89+1;
+ //sbit MD2 = 0x89+2;
+ //sbit T0M = 0x89+3;
+ //sbit T1M = 0x89+4;
+ //sbit T2M = 0x89+5;
+sfr at 0x8F SPC_; // Was WRS in Reg320
+ /* CKCON */
+ //sbit WRS = 0x8F+0;
+sfr at 0x90 IOB ;
+sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320
+ /* EXIF */
+ //sbit USBINT = 0x91+4;
+ //sbit I2CINT = 0x91+5;
+ //sbit IE4 = 0x91+6;
+ //sbit IE5 = 0x91+7;
+sfr at 0x92 MPA;
+sfr at 0x98 SCO;
+ /* SCON0 */
+/* sbit RI = 0x98+0;
+ sbit TI = 0x98+1;
+ sbit RB8 = 0x98+2;
+ sbit TB8 = 0x98+3;
+ sbit REN = 0x98+4;
+ sbit SM2 = 0x98+5;
+ sbit SM1 = 0x98+6;
+ sbit SM0 = 0x98+7;*/
+sfr at 0x99 SBU;
+
+sfr at 0x9A APTR1H ;
+sfr at 0x9B APTR1L ;
+sfr at 0x9C AUTODAT1;
+sfr at 0x9D AUTOPTRH2;
+sfr at 0x9E AUTOPTRL2;
+sfr at 0x9F AUTODAT2;
+sfr at 0xA0 IOC ;
+sfr at 0xA1 INT2CLR;
+sfr at 0xA2 INT4CLR;
+
+sfr at 0xA8 IE ;
+ /* IE */
+// sbit EX0 = 0xA8+0;
+// sbit ET0 = 0xA8+1;
+// sbit EX1 = 0xA8+2;
+// sbit ET1 = 0xA8+3;
+// sbit ES0 = 0xA8+4;
+// sbit ET2 = 0xA8+5;
+// sbit ES1 = 0xA8+6;
+// sbit EA = 0xA8+7;
+
+sfr at 0xAA EP2468STAT;
+ /* EP2468STAT */
+ //sbit EP2E = 0xAA+0;
+ //sbit EP2F = 0xAA+1;
+ //sbit EP4E = 0xAA+2;
+ //sbit EP4F = 0xAA+3;
+ //sbit EP6E = 0xAA+4;
+ //sbit EP6F = 0xAA+5;
+ //sbit EP8E = 0xAA+6;
+ //sbit EP8F = 0xAA+7;
+
+sfr at 0xAB EP24FIFOFLGS;
+sfr at 0xAC EP68FIFOFLGS;
+sfr at 0xAF AUTOPTRSETUP;
+ /* AUTOPTRSETUP */
+// sbit EXTACC = 0xAF+0;
+// sbit APTR1FZ = 0xAF+1;
+// sbit APTR2FZ = 0xAF+2;
+
+sfr at 0xB0 IOD ;
+sfr at 0xB1 IOE ;
+sfr at 0xB2 OEA ;
+sfr at 0xB3 OEB ;
+sfr at 0xB4 OEC ;
+sfr at 0xB5 OED ;
+sfr at 0xB6 OEE ;
+
+sfr at 0xB8 IP ;
+ /* IP */
+// sbit PX0 = 0xB8+0;
+// sbit PT0 = 0xB8+1;
+// sbit PX1 = 0xB8+2;
+// sbit PT1 = 0xB8+3;
+// sbit PS0 = 0xB8+4;
+// sbit PT2 = 0xB8+5;
+// sbit PS1 = 0xB8+6;
+
+sfr at 0xBA EP01STAT;
+sfr at 0xBB GPIFTRIG;
+
+sfr at 0xBD GPIFSGLDATH;
+sfr at 0xBE GPIFSGLDATLX;
+sfr at 0xBF GPIFSGLDATLNOX;
+
+sfr at 0xC0 SCON1;
+ /* SCON1 */
+/* sbit RI1 = 0xC0+0;
+ sbit TI1 = 0xC0+1;
+ sbit RB81 = 0xC0+2;
+ sbit TB81 = 0xC0+3;
+ sbit REN1 = 0xC0+4;
+ sbit SM21 = 0xC0+5;
+ sbit SM11 = 0xC0+6;
+ sbit SM01 = 0xC0+7;*/
+sfr at 0xC1 SBUF1;
+sfr at 0xC8 T2CON;
+ /* T2CON */
+/* sbit CP_RL2 = 0xC8+0;
+ sbit C_T2 = 0xC8+1;
+ sbit TR2 = 0xC8+2;
+ sbit EXEN2 = 0xC8+3;
+ sbit TCLK = 0xC8+4;
+ sbit RCLK = 0xC8+5;
+ sbit EXF2 = 0xC8+6;
+ sbit TF2 = 0xC8+7;*/
+sfr at 0xCA RCAP2L;
+sfr at 0xCB RCAP2H;
+sfr at 0xCC TL2;
+sfr at 0xCD TH2;
+sfr at 0xD0 PSW;
+ /* PSW */
+/* sbit P = 0xD0+0;
+ sbit FL = 0xD0+1;
+ sbit OV = 0xD0+2;
+ sbit RS0 = 0xD0+3;
+ sbit RS1 = 0xD0+4;
+ sbit F0 = 0xD0+5;
+ sbit AC = 0xD0+6;
+ sbit CY = 0xD0+7;*/
+sfr at 0xD8 EICON; // Was WDCON in DS80C320; Bit Values differ from Reg320
+ /* EICON */
+/* sbit INT6 = 0xD8+3;
+ sbit RESI = 0xD8+4;
+ sbit ERESI = 0xD8+5;
+ sbit SMOD1 = 0xD8+7;*/
+sfr at 0xE0 ACC;
+sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320
+ /* EIE */
+/* sbit EUSB = 0xE8+0;
+ sbit EI2C = 0xE8+1;
+ sbit EIEX4 = 0xE8+2;
+ sbit EIEX5 = 0xE8+3;
+ sbit EIEX6 = 0xE8+4;*/
+sfr at 0xF0 B ;
+sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320
+ /* EIP */
+// sbit PUSB = 0xF8+0;
+// sbit PI2C = 0xF8+1;
+// sbit EIPX4 = 0xF8+2;
+// sbit EIPX5 = 0xF8+3;
+// sbit EIPX6 = 0xF8+4;
+
+/*-----------------------------------------------------------------------------
+ Bit Masks
+-----------------------------------------------------------------------------*/
+
+#define bmBIT0 1
+#define bmBIT1 2
+#define bmBIT2 4
+#define bmBIT3 8
+#define bmBIT4 16
+#define bmBIT5 32
+#define bmBIT6 64
+#define bmBIT7 128
+
+
+/* CPU Control & Status Register (CPUCS) */
+#define bmPRTCSTB bmBIT5
+#define bmCLKSPD (bmBIT4 | bmBIT3)
+#define bmCLKSPD1 bmBIT4
+#define bmCLKSPD0 bmBIT3
+#define bmCLKINV bmBIT2
+#define bmCLKOE bmBIT1
+#define bm8051RES bmBIT0
+/* Port Alternate Configuration Registers */
+/* Port A (PORTACFG) */
+#define bmFLAGD bmBIT7
+#define bmINT1 bmBIT1
+#define bmINT0 bmBIT0
+/* Port C (PORTCCFG) */
+#define bmGPIFA7 bmBIT7
+#define bmGPIFA6 bmBIT6
+#define bmGPIFA5 bmBIT5
+#define bmGPIFA4 bmBIT4
+#define bmGPIFA3 bmBIT3
+#define bmGPIFA2 bmBIT2
+#define bmGPIFA1 bmBIT1
+#define bmGPIFA0 bmBIT0
+/* Port E (PORTECFG) */
+#define bmGPIFA8 bmBIT7
+#define bmT2EX bmBIT6
+#define bmINT6 bmBIT5
+#define bmRXD1OUT bmBIT4
+#define bmRXD0OUT bmBIT3
+#define bmT2OUT bmBIT2
+#define bmT1OUT bmBIT1
+#define bmT0OUT bmBIT0
+
+/* I2C Control & Status Register (I2CS) */
+#define bmSTART bmBIT7
+#define bmSTOP bmBIT6
+#define bmLASTRD bmBIT5
+#define bmID (bmBIT4 | bmBIT3)
+#define bmBERR bmBIT2
+#define bmACK bmBIT1
+#define bmDONE bmBIT0
+/* I2C Control Register (I2CTL) */
+#define bmSTOPIE bmBIT1
+#define bm400KHZ bmBIT0
+/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
+#define bmIV4 bmBIT6
+#define bmIV3 bmBIT5
+#define bmIV2 bmBIT4
+#define bmIV1 bmBIT3
+#define bmIV0 bmBIT2
+/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
+#define bmEP0ACK bmBIT6
+#define bmHSGRANT bmBIT5
+#define bmURES bmBIT4
+#define bmSUSP bmBIT3
+#define bmSUTOK bmBIT2
+#define bmSOF bmBIT1
+#define bmSUDAV bmBIT0
+/* Breakpoint register (BREAKPT) */
+#define bmBREAK bmBIT3
+#define bmBPPULSE bmBIT2
+#define bmBPEN bmBIT1
+/* Interrupt 2 & 4 Setup (INTSETUP) */
+#define bmAV2EN bmBIT3
+#define INT4IN bmBIT1
+#define bmAV4EN bmBIT0
+/* USB Control & Status Register (USBCS) */
+#define bmHSM bmBIT7
+#define bmDISCON bmBIT3
+#define bmNOSYNSOF bmBIT2
+#define bmRENUM bmBIT1
+#define bmSIGRESUME bmBIT0
+/* Wakeup Control and Status Register (WAKEUPCS) */
+#define bmWU2 bmBIT7
+#define bmWU bmBIT6
+#define bmWU2POL bmBIT5
+#define bmWUPOL bmBIT4
+#define bmDPEN bmBIT2
+#define bmWU2EN bmBIT1
+#define bmWUEN bmBIT0
+/* End Point 0 Control & Status Register (EP0CS) */
+#define bmHSNAK bmBIT7
+/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
+#define bmEPBUSY bmBIT1
+#define bmEPSTALL bmBIT0
+/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
+#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
+#define bmEPFULL bmBIT3
+#define bmEPEMPTY bmBIT2
+/* Endpoint Status (EP2468STAT) SFR bits */
+#define bmEP8FULL bmBIT7
+#define bmEP8EMPTY bmBIT6
+#define bmEP6FULL bmBIT5
+#define bmEP6EMPTY bmBIT4
+#define bmEP4FULL bmBIT3
+#define bmEP4EMPTY bmBIT2
+#define bmEP2FULL bmBIT1
+#define bmEP2EMPTY bmBIT0
+/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
+#define bmSDPAUTO bmBIT0
+/* Endpoint Data Toggle Control (TOGCTL) */
+#define bmQUERYTOGGLE bmBIT7
+#define bmSETTOGGLE bmBIT6
+#define bmRESETTOGGLE bmBIT5
+#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
+/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
+#define bmEP8IBN bmBIT5
+#define bmEP6IBN bmBIT4
+#define bmEP4IBN bmBIT3
+#define bmEP2IBN bmBIT2
+#define bmEP1IBN bmBIT1
+#define bmEP0IBN bmBIT0
+
+/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
+#define bmEP8PING bmBIT7
+#define bmEP6PING bmBIT6
+#define bmEP4PING bmBIT5
+#define bmEP2PING bmBIT4
+#define bmEP1PING bmBIT3
+#define bmEP0PING bmBIT2
+#define bmIBN bmBIT0
+
+/* Interface Configuration bits (IFCONFIG) */
+#define bmIFCLKSRC bmBIT7
+#define bm3048MHZ bmBIT6
+#define bmIFCLKOE bmBIT5
+#define bmIFCLKPOL bmBIT4
+#define bmASYNC bmBIT3
+#define bmGSTATE bmBIT2
+#define bmIFCFG1 bmBIT1
+#define bmIFCFG0 bmBIT0
+#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
+#define bmIFGPIF bmIFCFG1
+
+/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
+#define bmINFM bmBIT6
+#define bmOEP bmBIT5
+#define bmAUTOOUT bmBIT4
+#define bmAUTOIN bmBIT3
+#define bmZEROLENIN bmBIT2
+#define bmWORDWIDE bmBIT0
+
+/* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specidic
+ features */
+#define bmNOAUTOARM bmBIT1
+#define bmSKIPCOMMIT bmBIT0
+
+/* Fifo Reset bits (FIFORESET) */
+#define bmNAKALL bmBIT7
+
+#endif /* FX2REGS_H */
--
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