From a3fd39a1938352a93b09e7b7608b52be7f635705 Mon Sep 17 00:00:00 2001
From: Mathias Kreider <m.kreider@gsi.de>
Date: Wed, 15 Feb 2012 16:42:53 +0000
Subject: [PATCH]
---
hdl/EB_SPEC_Test/EB_2_wb_converter.vhd | 86 +++---
hdl/EB_SPEC_Test/EB_CORE.vhd | 49 +++-
hdl/EB_SPEC_Test/EB_RX_CTRL.vhd | 28 +-
hdl/EB_SPEC_Test/EB_TX_CTRL.vhd | 383 ++++++++++++++-----------
hdl/EB_SPEC_Test/eb_config_new.vhd | 22 +-
5 files changed, 330 insertions(+), 238 deletions(-)
diff --git a/hdl/EB_SPEC_Test/EB_2_wb_converter.vhd b/hdl/EB_SPEC_Test/EB_2_wb_converter.vhd
index 048513a..981a3a9 100644
--- a/hdl/EB_SPEC_Test/EB_2_wb_converter.vhd
+++ b/hdl/EB_SPEC_Test/EB_2_wb_converter.vhd
@@ -73,7 +73,7 @@ architecture behavioral of eb_2_wb_converter is
--State Machines
------------------------------------------------------------------------------------------
constant c_width_int : integer := 24;
-type t_state_RX is (IDLE, EB_HDR_REC, EB_HDR_PROC, EB_HDR_PROBE_ID, CYC_HDR_REC, CYC_HDR_READ_PROC, CYC_HDR_READ_GET_ADR, WB_READ_RDY, WB_READ, CYC_HDR_WRITE_PROC, CYC_HDR_WRITE_GET_ADR, WB_WRITE_RDY, WB_WRITE, CYC_DONE, EB_DONE, ERROR);
+type t_state_RX is (IDLE, EB_HDR_REC, EB_HDR_PROC, EB_HDR_PROBE_ID, EB_HDR_PROBE_RDY, CYC_HDR_REC, CYC_HDR_READ_PROC, CYC_HDR_READ_GET_ADR, WB_READ_RDY, WB_READ, CYC_HDR_WRITE_PROC, CYC_HDR_WRITE_GET_ADR, WB_WRITE_RDY, WB_WRITE, CYC_DONE, EB_DONE, ERROR);
type t_state_TX is (IDLE, EB_HDR_INIT, EB_HDR_PROBE_ID, EB_HDR_PROBE_WAIT, PACKET_HDR_SEND, EB_HDR_SEND, RDY, CYC_HDR_INIT, CYC_HDR_SEND, BASE_WRITE_ADR_SEND, DATA_SEND, ZERO_PAD_WRITE, ZERO_PAD_WAIT, ERROR);
@@ -304,13 +304,13 @@ begin
--Counter: RX bytes received
- if(s_state_RX = IDLE) then
+ if(s_state_RX = EB_DONE) then
s_EB_RX_byte_cnt <= (others => '0');
- else
+ end if;
if(s_rx_fifo_we = '1') then
s_EB_RX_byte_cnt <= s_EB_RX_byte_cnt + 4;
end if;
- end if;
+ --end if;
-- packet reception is not complete if min packet size not reached and < s_EB_packet_length
--
if((s_EB_RX_byte_cnt < s_EB_packet_length) OR (s_EB_RX_byte_cnt < 16)) then
@@ -379,27 +379,27 @@ begin
else
-- RX cycle line lowered before all words were transferred
- if (s_EB_RX_byte_cnt < s_EB_packet_length
- AND EB_RX_i.CYC = '0') then
- -- report "EB: PACKET WAS ABORTED" severity note;
- -- ERROR: -- RX cycle line lowered before all words were transferred
- -- s_state_RX <= IDLE;
- -- s_state_TX <= IDLE;
+ if ((s_EB_RX_byte_cnt < s_EB_packet_length) AND (s_rx_fifo_empty = '1') AND EB_RX_i.CYC = '0') then
+ report "EB: PACKET WAS ABORTED" severity note;
+ --ERROR: -- RX cycle line lowered before all words were transferred
+ s_state_RX <= IDLE;
+ s_state_TX <= IDLE;
--
- elsif(s_EB_RX_byte_cnt > s_EB_packet_length AND NOT (s_EB_RX_byte_cnt < 16)) then
- -- report "EB: PACKET TOO LONG" severity note;
- -- s_state_RX <= IDLE;
- -- s_state_TX <= IDLE;
+ elsif((s_EB_RX_byte_cnt > s_EB_packet_length) AND ((s_state_RX /= IDLE) AND (s_state_RX /= EB_HDR_REC))) then
+ report "EB: PACKET TOO LONG" severity note;
+ s_state_RX <= IDLE;
+ s_state_TX <= IDLE;
else
case s_state_RX is
- when IDLE => if(s_rx_fifo_empty = '1') then
+ when IDLE => if(s_rx_fifo_empty = '0') then
s_state_TX <= IDLE;
s_state_RX <= EB_HDR_REC;
+
report "EB: RDY" severity note;
end if;
- when EB_HDR_REC => if(EB_RX_i.CYC = '1' AND s_rx_fifo_empty = '0') then
+ when EB_HDR_REC => if(s_rx_fifo_empty = '0') then
s_state_RX <= EB_HDR_PROC;
end if;
@@ -424,7 +424,14 @@ begin
end if;
end if;
- when EB_HDR_PROBE_ID => s_state_RX <= EB_DONE;
+ when EB_HDR_PROBE_ID => if(s_rx_fifo_empty = '0') then
+ s_state_RX <= EB_HDR_PROBE_RDY;
+ end if;
+
+ when EB_HDR_PROBE_RDY => if(s_state_TX = RDY) then
+ s_state_RX <= EB_DONE;
+ end if;
+
when CYC_HDR_REC => if(s_rx_fifo_empty = '0') then
s_state_RX <= CYC_HDR_WRITE_PROC;
@@ -531,7 +538,7 @@ begin
when EB_HDR_PROBE_WAIT => if(s_EB_probe_wait_cnt > 3 AND s_tx_fifo_empty = '1' ) then
- s_state_TX <= IDLE;
+ s_state_TX <= RDY;
end if;
@@ -631,29 +638,27 @@ begin
case s_state_RX is
- when IDLE => s_tx_fifo_clr <= '1';
- s_rx_fifo_clr <= '1';
+ when IDLE => s_EB_packet_length <= (others => '0');
s_status_clr <= '1';
+
- when EB_HDR_REC => if(EB_RX_i.CYC = '1' AND s_rx_fifo_empty = '0') then
- s_EB_RX_HDR <= to_EB_HDR(s_rx_fifo_q);
- s_EB_packet_length <= unsigned(byte_count_rx_i)-8;
- s_rx_fifo_rd <= '1';
- end if;
+ when EB_HDR_REC => s_EB_packet_length <= unsigned(byte_count_rx_i)-8;
+ s_EB_RX_HDR <= to_EB_HDR(s_rx_fifo_q);
+ s_rx_fifo_rd <= '1';
+
when EB_HDR_PROC => null;
- when EB_HDR_PROBE_ID => if(EB_RX_i.CYC = '1' AND s_rx_fifo_empty = '0') then
- PROBE_ID <= s_rx_fifo_q;
- s_rx_fifo_rd <= '1';
- end if;
+ when EB_HDR_PROBE_ID => PROBE_ID <= s_rx_fifo_q;
+ s_rx_fifo_rd <= '1';
+
+ when EB_HDR_PROBE_RDY => null;
- when CYC_HDR_REC => if(s_rx_fifo_empty = '0') then
- s_EB_RX_CUR_CYCLE <= TO_EB_CYC(s_rx_fifo_q);
+ when CYC_HDR_REC => s_EB_RX_CUR_CYCLE <= TO_EB_CYC(s_rx_fifo_q);
s_rx_fifo_rd <= '1';
- end if;
+
when CYC_HDR_WRITE_PROC => if(s_EB_RX_CUR_CYCLE.WR_CNT > 0) then
--setup word counters
@@ -661,10 +666,9 @@ begin
end if;
- when CYC_HDR_WRITE_GET_ADR => if(s_rx_fifo_am_empty = '0') then
- s_WB_addr_cnt <= unsigned(s_rx_fifo_q);
- s_rx_fifo_rd <= '1'; -- only stall RX if we got an adress, otherwise continue listening
- end if;
+ when CYC_HDR_WRITE_GET_ADR => s_WB_addr_cnt <= unsigned(s_rx_fifo_q);
+ s_rx_fifo_rd <= '1'; -- only stall RX if we got an adress, otherwise continue listening
+
when WB_WRITE_RDY => if(s_state_TX = RDY) then
s_WB_CYC <= '1';
@@ -716,11 +720,10 @@ begin
end if;
- when CYC_HDR_READ_GET_ADR => if(s_rx_fifo_am_empty = '0') then
- --wait for ready from tx output
+ when CYC_HDR_READ_GET_ADR => --wait for ready from tx output
s_EB_TX_base_wr_adr <= s_rx_fifo_q;
s_rx_fifo_rd <= '1';
- end if;
+
when WB_READ_RDY => if(s_state_TX = RDY) then
@@ -764,10 +767,15 @@ begin
when EB_DONE => --report "EB: PACKET COMPLETE" severity note;
--TODO: test multi packet mode
s_WB_CYC <= NOT s_EB_RX_CUR_CYCLE.DROP_CYC;
+ s_tx_fifo_clr <= '1';
+ s_rx_fifo_clr <= '1';
+
--make sure there is no running transfer before resetting FSMs, also do not start a new packet proc before cyc has been lowered
when ERROR => report "EB: ERROR" severity warning;
s_WB_CYC <= '0';
+ s_tx_fifo_clr <= '1';
+ s_rx_fifo_clr <= '1';
end case;
diff --git a/hdl/EB_SPEC_Test/EB_CORE.vhd b/hdl/EB_SPEC_Test/EB_CORE.vhd
index ed522cc..05dd8db 100644
--- a/hdl/EB_SPEC_Test/EB_CORE.vhd
+++ b/hdl/EB_SPEC_Test/EB_CORE.vhd
@@ -161,8 +161,8 @@ signal RXCTRL_2_EB_wb_slave : wb32_slave_in;
signal EB_RX_i : t_wrf_sink_in;
signal EB_RX_o : t_wrf_sink_out;
-signal EB_TX_i : wb16_master_in;
-signal EB_TX_o : wb16_master_out;
+signal EB_TX_i : t_wrf_source_in;
+signal EB_TX_o : t_wrf_source_out;
component binary_sink is
generic(filename : string := "123.pcap"; wordsize : natural := 64; endian : natural := 0);
@@ -189,17 +189,26 @@ port(
wb_slave_i : in wb32_slave_in;
wb_slave_o : out wb32_slave_out;
- TX_master_o : out wb16_master_out; --! Wishbone master output lines
- TX_master_i : in wb16_master_in; --!
-
-
- reply_MAC_i : in std_logic_vector(47 downto 0);
- reply_IP_i : in std_logic_vector(31 downto 0);
- reply_PORT_i : in std_logic_vector(15 downto 0);
+ src_i : in t_wrf_source_in;
+ src_o : out t_wrf_source_out;
- TOL_i : in std_logic_vector(15 downto 0);
+
+ reply_MAC_i : in std_logic_vector(6*8-1 downto 0);
+ reply_IP_i : in std_logic_vector(4*8-1 downto 0);
+ reply_Port_i : in std_logic_vector(2*8-1 downto 0);
+
+
+ TOL_i : in std_logic_vector(2*8-1 downto 0);
payload_len_i : in std_logic_vector(2*8-1 downto 0);
+
+ my_mac_i : in std_logic_vector(6*8-1 downto 0);
+ my_vlan_i : in std_logic_vector(2*8-1 downto 0);
+ my_ip_i : in std_logic_vector(4*8-1 downto 0);
+ my_port_i : in std_logic_vector(2*8-1 downto 0);
+
+
+
valid_i : in std_logic
);
@@ -416,8 +425,8 @@ master : if(g_master_slave = "MASTER") generate
wb_slave_i => EB_2_TXCTRL_wb_slave,
wb_slave_o => TXCTRL_2_EB_wb_slave,
- TX_master_o => EB_TX_o,
- TX_master_i => EB_TX_i, --!
+ src_o => EB_TX_o,
+ src_i => EB_TX_i, --!
reply_MAC_i => RXCTRL_2_TXCTRL_reply_MAC,
reply_IP_i => RXCTRL_2_TXCTRL_reply_IP,
@@ -425,6 +434,12 @@ master : if(g_master_slave = "MASTER") generate
TOL_i => RXCTRL_2_TXCTRL_TOL,
payload_len_i => RXCTRL_2_CORE_LEN,
+
+ my_mac_i => CFG_MY_MAC,
+ my_ip_i => CFG_MY_IP,
+ my_port_i => CFG_MY_PORT,
+ my_vlan_i => (others => '0'),
+
valid_i => RXCTRL_2_TXCTRL_valid
);
@@ -465,8 +480,8 @@ slave : if(g_master_slave = "SLAVE") generate
wb_slave_i => EB_2_TXCTRL_wb_slave,
wb_slave_o => TXCTRL_2_EB_wb_slave,
- TX_master_o => EB_TX_o,
- TX_master_i => EB_TX_i, --!
+ src_o => EB_TX_o,
+ src_i => EB_TX_i, --!
reply_MAC_i => RXCTRL_2_TXCTRL_reply_MAC,
reply_IP_i => RXCTRL_2_TXCTRL_reply_IP,
@@ -474,6 +489,12 @@ slave : if(g_master_slave = "SLAVE") generate
TOL_i => RXCTRL_2_TXCTRL_TOL,
payload_len_i => RXCTRL_2_CORE_LEN,
+
+ my_mac_i => CFG_MY_MAC,
+ my_ip_i => CFG_MY_IP,
+ my_port_i => CFG_MY_PORT,
+ my_vlan_i => (others => '0'),
+
valid_i => RXCTRL_2_TXCTRL_valid
);
diff --git a/hdl/EB_SPEC_Test/EB_RX_CTRL.vhd b/hdl/EB_SPEC_Test/EB_RX_CTRL.vhd
index 0ef4789..9972057 100644
--- a/hdl/EB_SPEC_Test/EB_RX_CTRL.vhd
+++ b/hdl/EB_SPEC_Test/EB_RX_CTRL.vhd
@@ -163,6 +163,9 @@ signal RX_HDR_slv : std_logic_vector(c_IPV4_HLEN*8-1 downto 0) ;
--shift register input and control signals
signal byte_count : natural range 0 to 1600;
signal counter_comp : natural range 0 to 1600;
+
+
+
signal eop : natural range 0 to 1600;
@@ -286,7 +289,7 @@ begin
end if;
end process;
-
+
snk_WR <= NOT snk_hdr_fsm.stall AND snk_i.cyc AND snk_i.stb;
@@ -460,7 +463,7 @@ begin
state <= HEADER;
end if;
- when HEADER => if(parse = DONE) then
+ when HEADER => if(parse = DONE) then
eop <= (counter_comp + to_integer(unsigned(IPV4_RX.IHL)*4) + to_integer(unsigned(UDP_RX.MLEN)) -2);
state <= PAYLOAD;
--snk_hdr_fsm_STALL <= '1';
@@ -476,32 +479,33 @@ begin
if(snk_i.cyc = '0') then
report("RX: runt frame (< 64)") severity warning; state <= ERRORS;
- elsif(byte_count = eop) then
+ elsif(byte_count = eop AND snk_i.STB = '1' AND snk_payload_conv.stall = '0') then
state <= PADDING;
end if;
else
- if(snk_i.cyc = '0') then
- if(byte_count = eop) then state <= DONE;
- elsif(byte_count > eop) then
- report("RX: frame too long") severity warning; state <= ERRORS;
- else
- report("RX: frame cut short") severity warning; state <= ERRORS;
+ if(byte_count = eop AND snk_i.STB = '1' AND snk_payload_conv.stall = '0') then
+ state <= DONE;
+ --elsif(byte_count > eop AND ) then
+ -- report("RX: frame too long") severity warning; state <= ERRORS;
+ -- else
+ -- report("RX: frame cut short") severity warning; state <= ERRORS;
end if;
- end if;
+ --end if;
end if;
when PADDING => if(snk_i.cyc = '0') then
if(byte_count = c_ETH_FRAME_MIN_END) then state <= DONE;
- elsif(byte_count > c_ETH_FRAME_MIN_END) then
+ elsif(byte_count > c_ETH_FRAME_MIN_END +2) then
report("RX: frame too long") severity warning; state <= ERRORS;
else
report("RX: frame cut short") severity warning; state <= ERRORS;
end if;
end if;
- when DONE => parser_reset <= '1'; state <= IDLE;
+ when DONE => parser_reset <= '1'; state <= IDLE;
+
when ERRORS => parser_reset <= '1'; state <= IDLE;
when others => parser_reset <= '1'; state <= IDLE;
end case;
diff --git a/hdl/EB_SPEC_Test/EB_TX_CTRL.vhd b/hdl/EB_SPEC_Test/EB_TX_CTRL.vhd
index d08b464..3033572 100644
--- a/hdl/EB_SPEC_Test/EB_TX_CTRL.vhd
+++ b/hdl/EB_SPEC_Test/EB_TX_CTRL.vhd
@@ -37,6 +37,11 @@ library work;
use work.EB_HDR_PKG.all;
use work.wb32_package.all;
use work.wb16_package.all;
+use work.wr_fabric_pkg.all;
+
+
+
+
entity EB_TX_CTRL is
port(
@@ -47,17 +52,25 @@ port(
wb_slave_i : in wb32_slave_in;
wb_slave_o : out wb32_slave_out;
- TX_master_o : out wb16_master_out; --! Wishbone master output lines
- TX_master_i : in wb16_master_in; --!
-
+
+ src_i : in t_wrf_source_in;
+ src_o : out t_wrf_source_out;
+
+
+ reply_MAC_i : in std_logic_vector(6*8-1 downto 0);
+ reply_IP_i : in std_logic_vector(4*8-1 downto 0);
+ reply_Port_i : in std_logic_vector(2*8-1 downto 0);
- reply_MAC_i : in std_logic_vector(47 downto 0);
- reply_IP_i : in std_logic_vector(31 downto 0);
- reply_PORT_i : in std_logic_vector(15 downto 0);
+ TOL_i : in std_logic_vector(2*8-1 downto 0);
+ payload_len_i : in std_logic_vector(2*8-1 downto 0);
+
+ my_mac_i : in std_logic_vector(6*8-1 downto 0);
+ my_vlan_i : in std_logic_vector(2*8-1 downto 0);
+ my_ip_i : in std_logic_vector(4*8-1 downto 0);
+ my_port_i : in std_logic_vector(2*8-1 downto 0);
- TOL_i : in std_logic_vector(15 downto 0);
- payload_len_i : in std_logic_vector(15 downto 0);
+
valid_i : in std_logic
@@ -129,44 +142,48 @@ port(
);
end component;
-signal conv_B : wb16_master_out; --! Wishbone master output lines
+
signal conv_A : wb32_slave_out; --!
-- main FSM
-type st is (IDLE, CALC_CHKSUM, WAIT_SEND_REQ, HDR_SEND, PAYLOAD_SEND, WAIT_IFGAP);
-signal state_tx : st := IDLE;
+type st is (IDLE, CALC_CHKSUM, WAIT_SEND_REQ, PREP_ETH, ETH, IPV4, UDP, HDR_SEND, PAYLOAD_SEND, PADDING, WAIT_IFGAP);
+signal state : st := IDLE;
--- convert shift register input from hdr records to standard logic vectors and join them
signal ETH_TX : ETH_HDR;
signal IPV4_TX : IPV4_HDR;
signal UDP_TX : UDP_HDR;
-signal TX_HDR_slv : std_logic_vector((c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN) * 8-1 downto 0);
-alias ETH_TX_slv : std_logic_vector(c_ETH_HLEN*8-1 downto 0) is TX_HDR_slv((c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN)*8-1 downto (c_IPV4_HLEN + c_UDP_HLEN)*8);
-alias IPV4_TX_slv : std_logic_vector(c_IPV4_HLEN*8-1 downto 0) is TX_HDR_slv((c_IPV4_HLEN + c_UDP_HLEN)*8-1 downto c_UDP_HLEN*8);
-alias UDP_TX_slv : std_logic_vector(c_UDP_HLEN*8-1 downto 0) is TX_HDR_slv(c_UDP_HLEN*8-1 downto 0);
+
+signal TX_HDR_slv : std_logic_vector(c_IPV4_HLEN*8 -1 downto 0);
+
--shift register output and control signals
-signal s_out : std_logic_vector(31 downto 0);
+signal byte_count : natural range 0 to 1600;
+signal counter_comp : natural range 0 to 1600;
+
+
+
+ signal eop : natural range 0 to 1600;
+
signal sh_hdr_en : std_logic;
signal s_sh_hdr_en : std_logic;
signal ld_hdr : std_logic;
-signal counter_ouput : unsigned(7 downto 0);
+signal hdr_empty : std_logic;
+signal hdr_full : std_logic;
signal chksum_empty : std_logic;
-signal hdr_empty : std_logic;
signal chksum_full : std_logic;
-signal hdr_full : std_logic;
+
-- forking the bus
-type stmux is (HEADER, PAYLOAD);
+type stmux is (HEADER, PAYLOAD, PADDING, NONE);
signal state_mux : stmux := HEADER;
-signal TX_hdr_o : wb16_master_out; --! Wishbone master output lines
+
signal wb_payload_stall_o : wb32_slave_out;
signal stalled : std_logic;
-- IP checksum generator
-signal counter_chksum : unsigned(7 downto 0);
+
signal p_chk_vals : std_logic_vector(95 downto 0);
signal s_chk_vals : std_logic_vector(15 downto 0);
signal IP_chk_sum : std_logic_vector(15 downto 0);
@@ -175,46 +192,69 @@ signal calc_chk_en : std_logic;
signal ld_p_chk_vals : std_logic; --parallel load
signal chksum_done : std_logic;
-signal DEBUG_cmp_chksum : IPV4_HDR;
-
-signal PISO_STALL : std_logic;
-
-function calc_ip_chksum(input : IPV4_HDR)
-return IPV4_HDR is
- variable tmp : unsigned(c_IPV4_HLEN*8-1 downto 0);
- variable output : IPV4_HDR;
- variable tmp_sum : unsigned(31 downto 0) := (others => '0');
- variable tmp_slice : unsigned(15 downto 0);
- begin
- tmp := unsigned(to_std_logic_vector(input));
- for i in c_IPV4_HLEN*8/16-1 downto 0 loop
- tmp_slice := tmp((i+1)*16-1 downto i*16);
- tmp_sum := tmp_sum + (x"0000" & tmp_slice);
- end loop;
- tmp_sum := (x"0000" & tmp_sum(15 downto 0)) + (x"0000" + tmp_sum(31 downto 16));
- output.SUM := std_logic_vector(NOT(tmp_sum(15 downto 0) + tmp_sum(31 downto 16)));
- return output;
-end function calc_ip_chksum;
+
+signal s_src_o : t_wrf_source_out;
+signal s_src_hdr_o : t_wrf_source_out;
+signal s_src_payload_o : t_wrf_source_out;
+signal s_src_padding_o : t_wrf_source_out;
+
+signal payload_stall : std_logic;
+signal hdr_wait : std_logic;
+
+signal hdr_done : std_logic;
+
begin
-ETH_TX_slv <= TO_STD_LOGIC_VECTOR(ETH_TX);
-IPV4_TX_slv <= TO_STD_LOGIC_VECTOR(IPV4_TX);
-UDP_TX_slv <= TO_STD_LOGIC_VECTOR(UDP_TX);
+count_tx_bytes : process(clk_i)
+begin
+ if rising_edge(clk_i) then
+ if (nRST_i = '0' or state = IDLE) then
+ byte_count <= 0;
+ else
+ if(s_src_o.stb = '1' and s_src_o.cyc = '1' and src_i.stall = '0') then
+ byte_count <= byte_count + 2;
+ end if;
+
+ end if;
+
+ end if;
+end process;
+
+-- source output mapping to source output signals
+src_o.cyc <= '0' when state_mux = NONE
+ else '1';
+
+src_o.stb <= s_src_o.stb;
+src_o.dat <= s_src_o.dat;
+src_o.sel <= "11";
+src_o.adr <= c_WRF_DATA;
+src_o.we <= '1';
+
+-- source mux
MUX_TX : with state_mux select
-TX_master_o <= conv_B when PAYLOAD,
- TX_hdr_o when others;
+s_src_o <= s_src_hdr_o when HEADER,
+ s_src_payload_o when PAYLOAD,
+ s_src_padding_o when PADDING,
+ s_src_padding_o when others;
-MUX_WB : with state_mux select
-wb_slave_o <= conv_A when others; --wb_payload_stall_o when HEADER,
-
-
-MUX_PISO : with state_mux select
-PISO_STALL <= '1' when HEADER,
- TX_master_i.STALL when others;
+-- wb_slave mux
+MUX_WB : with state_mux select
+wb_slave_o.STALL <= conv_A.STALL when PAYLOAD,
+ '1' when others;
+
+wb_slave_o.ACK <= conv_A.ACK;
+wb_slave_o.ERR <= conv_A.ERR;
+wb_slave_o.RTY <= '0';
+wb_slave_o.DAT <= (others => '0');
+
+
+s_sh_hdr_en <= s_src_hdr_o.cyc and s_src_hdr_o.stb and not src_i.stall;
+
+
shift_hdr_chk_sum : piso_flag generic map( 96, 16)
@@ -224,8 +264,8 @@ port map ( d_i => p_chk_vals,
nRST_i => nRST_i,
en_i => sh_chk_en,
ld_i => ld_p_chk_vals,
- full_o => chksum_full,
- empty_o => chksum_empty
+ full_o => chksum_full,
+ empty_o => chksum_empty
);
p_chk_vals <= x"C511" & IPV4_TX.SRC & IPV4_TX.DST & IPV4_TX.TOL;
@@ -242,16 +282,16 @@ chksum_generator: EB_checksum port map ( clk_i => clk_i,
-Shift_out: piso_flag generic map ((c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN)*8, 16)
- port map ( d_i => TX_HDR_slv ,
- q_o => TX_hdr_o.DAT,
+Shift_out: piso_flag generic map (c_IPV4_HLEN*8, 16)
+ port map ( d_i => TX_HDR_slv,
+ q_o => s_src_hdr_o.DAT,
clk_i => clk_i,
nRST_i => nRST_i,
en_i => s_sh_hdr_en,
ld_i => ld_hdr,
- full_o => hdr_full,
- empty_o => hdr_empty
- );
+ full_o => hdr_full,
+ empty_o => hdr_empty
+ );
@@ -260,7 +300,7 @@ Shift_out: piso_flag generic map ((c_ETH_HLEN + c_IPV4_HLEN + c_UDP_HLEN)*8, 16)
-- convert streaming input from 16 to 32 bit data width
uut: WB_bus_adapter_streaming_sg generic map ( g_adr_width_A => 32,
- g_adr_width_B => 32,
+ g_adr_width_B => 2,
g_dat_width_A => 32,
g_dat_width_B => 16,
g_pipeline => 3)
@@ -277,28 +317,21 @@ uut: WB_bus_adapter_streaming_sg generic map ( g_adr_width_A => 32,
A_RTY_o => conv_A.RTY,
A_STALL_o => conv_A.STALL,
A_DAT_o => conv_A.DAT,
- B_CYC_o => conv_B.CYC,
- B_STB_o => conv_B.STB,
- B_ADR_o => conv_B.ADR,
- B_SEL_o => conv_B.SEL,
- B_WE_o => conv_B.WE,
- B_DAT_o => conv_B.DAT,
- B_ACK_i => TX_master_i.ACK,
- B_ERR_i => TX_master_i.ERR,
- B_RTY_i => TX_master_i.RTY,
- B_STALL_i => PISO_STALL,
- B_DAT_i => TX_master_i.DAT);
-
-
-
+ B_CYC_o => s_src_payload_o.cyc,
+ B_STB_o => s_src_payload_o.stb,
+ B_ADR_o => s_src_payload_o.adr,
+ B_SEL_o => s_src_payload_o.sel,
+ B_WE_o => open,
+ B_DAT_o => s_src_payload_o.dat,
+ B_ACK_i => src_i.ack,
+ B_ERR_i => src_i.err,
+ B_RTY_i => src_i.rty,
+ B_STALL_i => src_i.stall,
+ B_DAT_i => (others => '0'));
-TX_hdr_o.STB <= '1' when state_tx = HDR_SEND AND hdr_empty = '0'
-else '0';
-s_sh_hdr_en <= TX_hdr_o.STB AND NOT TX_master_i.STALL;
-
main_fsm : process(clk_i)
begin
@@ -308,113 +341,133 @@ begin
-- SYNC RESET
--==========================================================================
if (nRST_i = '0') then
- ETH_TX <= INIT_ETH_HDR(c_MY_MAC);
- IPV4_TX <= INIT_IPV4_HDR(c_MY_IP);
- UDP_TX <= INIT_UDP_HDR(c_EB_PORT);
-
- IPV4_TX.TOL <= std_logic_vector(to_unsigned(112, 16));
+ ETH_TX <= INIT_ETH_HDR (my_mac_i);
+ IPV4_TX <= INIT_IPV4_HDR(my_ip_i);
+ UDP_TX <= INIT_UDP_HDR (my_port_i);
- TX_hdr_o.CYC <= '0';
- --TX_hdr_o.STB <= '0';
- TX_hdr_o.WE <= '1';
- TX_hdr_o.ADR <= (others => '0');
- TX_hdr_o.SEL <= (others => '1');
- wb_payload_stall_o.STALL <= '1';
- wb_payload_stall_o.ACK <= '0';
- wb_payload_stall_o.DAT <= (others => '0');
- wb_payload_stall_o.ERR <= '0';
- wb_payload_stall_o.RTY <= '0';
+ state_mux <= NONE;
- state_mux <= HEADER;
- sh_hdr_en <= '0';
+ sh_hdr_en <= '0';
ld_hdr <= '0';
- stalled <= '0';
- counter_ouput <= (others => '0');
- counter_chksum <= (others => '0');
- -- prepare chk sum field_tx_hdr, fill in reply IP and TOL field_tx_hdr when available
+
+
ld_p_chk_vals <= '0';
- sh_chk_en <= '0';
+ sh_chk_en <= '0';
calc_chk_en <= '0';
+
+ s_src_padding_o <= (cyc => '1',
+ stb => '0',
+ adr => (others => '0'),
+ sel => (others => '1'),
+ we => '1',
+ dat => x"9AD1");
+
+ s_src_hdr_o.cyc <= '1';
+ s_src_hdr_o.stb <= '0';
+ s_src_hdr_o.adr <= (others => '0');
+ s_src_hdr_o.we <= '1';
+ s_src_hdr_o.sel <= (others => '1');
+ TX_HDR_slv <= (others => '0');
+
else
- --TX_hdr_o.STB <= '0';
ld_hdr <= '0';
- sh_hdr_en <= '0';
+ sh_hdr_en <= '0';
ld_p_chk_vals <= '0';
sh_chk_en <= '0';
calc_chk_en <= '0';
- case state_tx is
- when IDLE => ETH_TX <= INIT_ETH_HDR (c_MY_MAC);
- IPV4_TX <= INIT_IPV4_HDR(c_MY_IP);
- UDP_TX <= INIT_UDP_HDR (c_EB_PORT);
- state_mux <= HEADER;
- counter_chksum <= (others => '0');
- counter_ouput <= (others => '0');
-
- if(valid_i = '1') then
- ETH_TX.DST <= reply_MAC_i;
- IPV4_TX.DST <= reply_IP_i;
- IPV4_TX.TOL <= TOL_i;
- UDP_TX.MLEN <= payload_len_i;
- UDP_TX.DST_PORT <= reply_PORT_i;
- ld_p_chk_vals <= '1';
- state_tx <= CALC_CHKSUM;
- end if;
-
- when CALC_CHKSUM => if(chksum_empty = '0') then
- sh_chk_en <= '1';
- calc_chk_en <= '1';
- counter_chksum <= counter_chksum +1;
- else
- if(chksum_done = '1') then
- DEBUG_cmp_chksum <= calc_ip_chksum(IPV4_TX);
- IPV4_TX.SUM <= IP_chk_sum;
- ld_hdr <= '1';
- state_tx <= WAIT_SEND_REQ;
- end if;
- end if;
-
- when WAIT_SEND_REQ => state_mux <= HEADER;
- if(wb_slave_i.CYC = '1') then
- TX_hdr_o.CYC <= '1';
- --TX_hdr_o.STB <= '1';
-
- state_tx <= HDR_SEND;
- end if;
+ case state is
+ when IDLE => state_mux <= NONE;
+
+ if(valid_i = '1') then
+ ETH_TX.DST <= reply_MAC_i;
+ IPV4_TX.DST <= reply_IP_i;
+ IPV4_TX.TOL <= TOL_i;
+ UDP_TX.MLEN <= payload_len_i;
+ UDP_TX.DST_PORT <= reply_PORT_i;
+ ld_p_chk_vals <= '1';
+ state <= CALC_CHKSUM;
+ end if;
- when HDR_SEND => if(hdr_empty = '0') then
- --TX_hdr_o.STB <= '1';
- if(TX_master_i.STALL = '0') then
+ when CALC_CHKSUM => if(chksum_empty = '0') then
+ sh_chk_en <= '1';
+ calc_chk_en <= '1';
+ else
+ if(chksum_done = '1') then
+ IPV4_TX.SUM <= IP_chk_sum;
+ ld_hdr <= '1';
+ state <= WAIT_SEND_REQ;
- sh_hdr_en <= '1';
- counter_ouput <= counter_ouput +1;
- end if;
-
- else
- state_mux <= PAYLOAD;
- state_tx <= PAYLOAD_SEND;
end if;
+ end if;
+
+ when WAIT_SEND_REQ => if(wb_slave_i.CYC = '1') then
+ state <= PREP_ETH;
+ state_mux <= HEADER;
+ end if;
+
- when PAYLOAD_SEND => if(wb_slave_i.CYC = '0' AND conv_B.STB = '0' AND TX_master_i.STALL = '0') then
- state_tx <= WAIT_IFGAP;
- state_mux <= HEADER;
- TX_hdr_o.CYC <= '0';
- end if;
+
+ when PREP_ETH => TX_HDR_slv(TX_HDR_slv'left downto TX_HDR_slv'length-c_ETH_HLEN*8) <= to_std_logic_vector(ETH_TX);
+ ld_hdr <= '1';
+ state <= ETH;
+
+ when ETH =>
+ s_src_hdr_o.stb <= '1';
+ if(byte_count = c_ETH_end and src_i.stall = '0') then
+ TX_HDR_slv <= to_std_logic_vector(IPV4_TX);
+ ld_hdr <= '1';
+ state <= IPV4;
+ s_src_hdr_o.stb <= '0';
+ end if;
+
+ when IPV4 => s_src_hdr_o.stb <= '1';
+ if((byte_count = (c_ETH_end + c_IPV4_HLEN)) and src_i.stall = '0') then
+ TX_HDR_slv(TX_HDR_slv'left downto TX_HDR_slv'length-c_UDP_HLEN*8) <= to_std_logic_vector(UDP_TX);
+ ld_hdr <= '1';
+ state <= UDP;
+ s_src_hdr_o.stb <= '0';
+ end if;
+
+ when UDP => s_src_hdr_o.stb <= '1';
+ if(byte_count = (c_ETH_end + c_IPV4_HLEN + c_UDP_HLEN) and src_i.stall = '0') then
+ state <= HDR_SEND;
+ s_src_hdr_o.stb <= '0';
+ end if;
+
+ when HDR_SEND => state_mux <= PAYLOAD;
+ state <= PAYLOAD_SEND;
+
+
+ when PAYLOAD_SEND => if( s_src_payload_o.cyc = '0') then
+ if(byte_count < c_ETH_FRAME_MIN_END) then
+ state <= PADDING;
+ state_mux <= PADDING;
+ else
+ state <= WAIT_IFGAP;
+ state_mux <= NONE;
+ end if;
+ end if;
+
+ when PADDING => if(byte_count >= c_ETH_FRAME_MIN_END) then
+ state <= WAIT_IFGAP;
+ state_mux <= NONE;
+ end if;
when WAIT_IFGAP => --ensure interframe gap
- if(counter_ouput < 10) then
- counter_ouput <= counter_ouput +1;
- else
- state_tx <= IDLE;
- end if;
+ --if(counter_ouput < 10) then
+ -- counter_ouput <= counter_ouput +1;
+ --else
+ state <= IDLE;
+ --end if;
- when others => state_tx <= IDLE;
+ when others => state <= IDLE;
end case;
diff --git a/hdl/EB_SPEC_Test/eb_config_new.vhd b/hdl/EB_SPEC_Test/eb_config_new.vhd
index fb398bf..4b31430 100644
--- a/hdl/EB_SPEC_Test/eb_config_new.vhd
+++ b/hdl/EB_SPEC_Test/eb_config_new.vhd
@@ -68,12 +68,13 @@ signal local_write_reg : std_logic_vector(31 downto 0);
signal status_reg : std_logic_vector(63 downto 0);
signal p_auto_cfg : std_logic_vector(63 downto 0);
-signal my_mac : std_logic_vector(47 downto 0);
-signal my_ip : std_logic_vector(31 downto 0);
-
-constant c_my_default_ip : std_logic_vector(31 downto 0) := x"C0A80064";
-constant c_my_default_mac : std_logic_vector(47 downto 0) := x"D15EA5EDBEEF";
+signal my_mac : std_logic_vector(6*8-1 downto 0);
+signal my_ip : std_logic_vector(4*8-1 downto 0);
+signal my_port : std_logic_vector(2*8-1 downto 0);
+constant c_my_default_mac : std_logic_vector(6*8-1 downto 0) := x"D15EA5EDBEEF";
+constant c_my_default_ip : std_logic_vector(4*8-1 downto 0) := x"C0A80064";
+constant c_my_default_port : std_logic_vector(2*8-1 downto 0) := x"EBD0";
begin
@@ -85,6 +86,7 @@ local_adr <= to_integer(unsigned(local_slave_i.ADR(7 downto 0)));
my_mac_o <= my_mac;
my_ip_o <= my_ip;
+my_port_o <= my_port;
local_slave_o.STALL <= eb_slave_i.CYC;
@@ -110,7 +112,8 @@ eb_if : process (clk_i)
local_slave_o.DAT <= (others => '0');
my_ip <= c_my_default_ip;
- my_mac <= c_my_default_mac;
+ my_mac <= c_my_default_mac;
+ my_port <= c_my_default_port;
p_auto_cfg <= (others => '0');
else
@@ -124,6 +127,7 @@ eb_if : process (clk_i)
when 16 => my_mac(47 downto 16) <= eb_slave_i.DAT(31 downto 0);
when 20 => my_mac(15 downto 0) <= eb_slave_i.DAT(31 downto 16);
when 24 => my_ip <= eb_slave_i.DAT;
+ when 28 => my_port <= eb_slave_i.DAT(31 downto 16);
when others => null;
end case;
else
@@ -135,7 +139,8 @@ eb_if : process (clk_i)
when 16 => eb_slave_o.DAT <= my_mac(47 downto 16);
when 20 => eb_slave_o.DAT <= (my_mac(15 downto 0) & std_logic_vector(to_unsigned(0, 16)));
when 24 => eb_slave_o.DAT <= my_ip;
-
+ when 28 => eb_slave_o.DAT <= my_port & std_logic_vector(to_unsigned(0, 16));
+
when others => eb_slave_o.DAT <= status_reg(63 downto 32);
end case;
end if;
@@ -152,6 +157,7 @@ eb_if : process (clk_i)
when 16 => my_mac(47 downto 16) <= local_write_reg(31 downto 0);
when 20 => my_mac(15 downto 0) <= local_write_reg(31 downto 16);
when 24 => my_ip <= local_write_reg;
+ when 28 => my_port <= local_write_reg(31 downto 16);
when others => null;
end case;
else
@@ -163,7 +169,7 @@ eb_if : process (clk_i)
when 16 => local_slave_o.DAT <= my_mac(47 downto 16);
when 20 => local_slave_o.DAT <= my_mac(15 downto 0) & std_logic_vector(to_unsigned(0, 16));
when 24 => local_slave_o.DAT <= my_ip;
-
+ when 28 => local_slave_o.DAT <= my_port & std_logic_vector(to_unsigned(0, 16)) ;
when others => local_slave_o.DAT <= status_reg(63 downto 32);
end case;
end if;
--
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